1253789Srpaulo/*- 2253789Srpaulo * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3253789Srpaulo * 4253789Srpaulo * Permission to use, copy, modify, and distribute this software for any 5253789Srpaulo * purpose with or without fee is hereby granted, provided that the above 6253789Srpaulo * copyright notice and this permission notice appear in all copies. 7253789Srpaulo * 8253789Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9253789Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10253789Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11253789Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12253789Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13253789Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14253789Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15253789Srpaulo * 16253789Srpaulo * $OpenBSD: if_rsureg.h,v 1.3 2013/04/15 09:23:01 mglocker Exp $ 17253789Srpaulo * $FreeBSD: stable/11/sys/dev/usb/wlan/if_rsureg.h 345636 2019-03-28 09:50:25Z avos $ 18253789Srpaulo */ 19253789Srpaulo 20253789Srpaulo/* USB Requests. */ 21253789Srpaulo#define R92S_REQ_REGS 0x05 22253789Srpaulo 23253789Srpaulo/* 24253789Srpaulo * MAC registers. 25253789Srpaulo */ 26253789Srpaulo#define R92S_SYSCFG 0x0000 27253789Srpaulo#define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000) 28253789Srpaulo#define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002) 29253789Srpaulo#define R92S_PMC_FSM (R92S_SYSCFG + 0x004) 30253789Srpaulo#define R92S_SYS_CLKR (R92S_SYSCFG + 0x008) 31253789Srpaulo#define R92S_EE_9346CR (R92S_SYSCFG + 0x00a) 32253789Srpaulo#define R92S_AFE_MISC (R92S_SYSCFG + 0x010) 33253789Srpaulo#define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011) 34253789Srpaulo#define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018) 35253789Srpaulo#define R92S_RF_CTRL (R92S_SYSCFG + 0x01f) 36253789Srpaulo#define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020) 37253789Srpaulo#define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021) 38253789Srpaulo#define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026) 39253789Srpaulo#define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028) 40253789Srpaulo#define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030) 41253789Srpaulo#define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034) 42253789Srpaulo#define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8) 43253789Srpaulo 44253789Srpaulo#define R92S_CMDCTRL 0x0040 45253789Srpaulo#define R92S_CR (R92S_CMDCTRL + 0x000) 46253789Srpaulo#define R92S_TCR (R92S_CMDCTRL + 0x004) 47253789Srpaulo#define R92S_RCR (R92S_CMDCTRL + 0x008) 48253789Srpaulo 49253789Srpaulo#define R92S_MACIDSETTING 0x0050 50253789Srpaulo#define R92S_MACID (R92S_MACIDSETTING + 0x000) 51253789Srpaulo 52253789Srpaulo#define R92S_GP 0x01e0 53253789Srpaulo#define R92S_GPIO_CTRL (R92S_GP + 0x00c) 54253789Srpaulo#define R92S_GPIO_IO_SEL (R92S_GP + 0x00e) 55253789Srpaulo#define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011) 56253789Srpaulo 57253789Srpaulo#define R92S_IOCMD_CTRL 0x0370 58253789Srpaulo#define R92S_IOCMD_DATA 0x0374 59253789Srpaulo 60253789Srpaulo#define R92S_USB_HRPWM 0xfe58 61253789Srpaulo 62253789Srpaulo/* Bits for R92S_SYS_FUNC_EN. */ 63253789Srpaulo#define R92S_FEN_CPUEN 0x0400 64253789Srpaulo 65253789Srpaulo/* Bits for R92S_PMC_FSM. */ 66253789Srpaulo#define R92S_PMC_FSM_CUT_M 0x000f8000 67253789Srpaulo#define R92S_PMC_FSM_CUT_S 15 68253789Srpaulo 69253789Srpaulo/* Bits for R92S_SYS_CLKR. */ 70253789Srpaulo#define R92S_SYS_CLKSEL 0x0001 71253789Srpaulo#define R92S_SYS_PS_CLKSEL 0x0002 72253789Srpaulo#define R92S_SYS_CPU_CLKSEL 0x0004 73253789Srpaulo#define R92S_MAC_CLK_EN 0x0800 74253789Srpaulo#define R92S_SYS_CLK_EN 0x1000 75253789Srpaulo#define R92S_SWHW_SEL 0x4000 76253789Srpaulo#define R92S_FWHW_SEL 0x8000 77253789Srpaulo 78253789Srpaulo/* Bits for R92S_EE_9346CR. */ 79253789Srpaulo#define R92S_9356SEL 0x10 80253789Srpaulo#define R92S_EEPROM_EN 0x20 81253789Srpaulo 82253789Srpaulo/* Bits for R92S_AFE_MISC. */ 83253789Srpaulo#define R92S_AFE_MISC_BGEN 0x01 84253789Srpaulo#define R92S_AFE_MISC_MBEN 0x02 85253789Srpaulo#define R92S_AFE_MISC_I32_EN 0x08 86253789Srpaulo 87253789Srpaulo/* Bits for R92S_SPS1_CTRL. */ 88253789Srpaulo#define R92S_SPS1_LDEN 0x01 89253789Srpaulo#define R92S_SPS1_SWEN 0x02 90253789Srpaulo 91253789Srpaulo/* Bits for R92S_LDOA15_CTRL. */ 92253789Srpaulo#define R92S_LDA15_EN 0x01 93253789Srpaulo 94253789Srpaulo/* Bits for R92S_LDOV12D_CTRL. */ 95253789Srpaulo#define R92S_LDV12_EN 0x01 96253789Srpaulo 97253789Srpaulo/* Bits for R92C_EFUSE_CTRL. */ 98253789Srpaulo#define R92S_EFUSE_CTRL_DATA_M 0x000000ff 99253789Srpaulo#define R92S_EFUSE_CTRL_DATA_S 0 100253789Srpaulo#define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00 101253789Srpaulo#define R92S_EFUSE_CTRL_ADDR_S 8 102253789Srpaulo#define R92S_EFUSE_CTRL_VALID 0x80000000 103253789Srpaulo 104253789Srpaulo/* Bits for R92S_CR. */ 105253789Srpaulo#define R92S_CR_TXDMA_EN 0x10 106253789Srpaulo 107253789Srpaulo/* Bits for R92S_TCR. */ 108253789Srpaulo#define R92S_TCR_IMEM_CODE_DONE 0x01 109253789Srpaulo#define R92S_TCR_IMEM_CHK_RPT 0x02 110253789Srpaulo#define R92S_TCR_EMEM_CODE_DONE 0x04 111253789Srpaulo#define R92S_TCR_EMEM_CHK_RPT 0x08 112253789Srpaulo#define R92S_TCR_DMEM_CODE_DONE 0x10 113253789Srpaulo#define R92S_TCR_IMEM_RDY 0x20 114253789Srpaulo#define R92S_TCR_FWRDY 0x80 115253789Srpaulo 116253789Srpaulo/* Bits for R92S_GPIO_IO_SEL. */ 117253789Srpaulo#define R92S_GPIO_WPS 0x10 118253789Srpaulo 119253789Srpaulo/* Bits for R92S_MAC_PINMUX_CTRL. */ 120253789Srpaulo#define R92S_GPIOSEL_GPIO_M 0x03 121253789Srpaulo#define R92S_GPIOSEL_GPIO_S 0 122253789Srpaulo#define R92S_GPIOSEL_GPIO_JTAG 0 123253789Srpaulo#define R92S_GPIOSEL_GPIO_PHYDBG 1 124253789Srpaulo#define R92S_GPIOSEL_GPIO_BT 2 125253789Srpaulo#define R92S_GPIOSEL_GPIO_WLANDBG 3 126253789Srpaulo#define R92S_GPIOMUX_EN 0x08 127253789Srpaulo 128253789Srpaulo/* Bits for R92S_IOCMD_CTRL. */ 129253789Srpaulo#define R92S_IOCMD_CLASS_M 0xff000000 130253789Srpaulo#define R92S_IOCMD_CLASS_S 24 131253789Srpaulo#define R92S_IOCMD_CLASS_BB_RF 0xf0 132253789Srpaulo#define R92S_IOCMD_VALUE_M 0x00ffff00 133253789Srpaulo#define R92S_IOCMD_VALUE_S 8 134253789Srpaulo#define R92S_IOCMD_INDEX_M 0x000000ff 135253789Srpaulo#define R92S_IOCMD_INDEX_S 0 136253789Srpaulo#define R92S_IOCMD_INDEX_BB_READ 0 137253789Srpaulo#define R92S_IOCMD_INDEX_BB_WRITE 1 138253789Srpaulo#define R92S_IOCMD_INDEX_RF_READ 2 139253789Srpaulo#define R92S_IOCMD_INDEX_RF_WRITE 3 140253789Srpaulo 141253789Srpaulo/* Bits for R92S_USB_HRPWM. */ 142253789Srpaulo#define R92S_USB_HRPWM_PS_ALL_ON 0x04 143253789Srpaulo#define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08 144253789Srpaulo 145253789Srpaulo/* 146253789Srpaulo * Macros to access subfields in registers. 147253789Srpaulo */ 148253789Srpaulo/* Mask and Shift (getter). */ 149253789Srpaulo#define MS(val, field) \ 150253789Srpaulo (((val) & field##_M) >> field##_S) 151253789Srpaulo 152253789Srpaulo/* Shift and Mask (setter). */ 153253789Srpaulo#define SM(field, val) \ 154253789Srpaulo (((val) << field##_S) & field##_M) 155253789Srpaulo 156253789Srpaulo/* Rewrite. */ 157253789Srpaulo#define RW(var, field, val) \ 158253789Srpaulo (((var) & ~field##_M) | SM(field, val)) 159253789Srpaulo 160253789Srpaulo/* 161288357Sadrian * ROM field with RF config. 162288357Sadrian */ 163288357Sadrianenum { 164288357Sadrian RTL8712_RFCONFIG_1T = 0x10, 165288357Sadrian RTL8712_RFCONFIG_2T = 0x20, 166288357Sadrian RTL8712_RFCONFIG_1R = 0x01, 167288357Sadrian RTL8712_RFCONFIG_2R = 0x02, 168288357Sadrian RTL8712_RFCONFIG_1T1R = 0x11, 169288357Sadrian RTL8712_RFCONFIG_1T2R = 0x12, 170288357Sadrian RTL8712_RFCONFIG_TURBO = 0x92, 171288357Sadrian RTL8712_RFCONFIG_2T2R = 0x22 172288357Sadrian}; 173288357Sadrian 174288357Sadrian/* 175253789Srpaulo * Firmware image header. 176253789Srpaulo */ 177253789Srpaulostruct r92s_fw_priv { 178253789Srpaulo /* QWORD0 */ 179253789Srpaulo uint16_t signature; 180253789Srpaulo uint8_t hci_sel; 181253789Srpaulo#define R92S_HCI_SEL_PCIE 0x01 182253789Srpaulo#define R92S_HCI_SEL_USB 0x02 183253789Srpaulo#define R92S_HCI_SEL_SDIO 0x04 184253789Srpaulo#define R92S_HCI_SEL_8172 0x10 185253789Srpaulo#define R92S_HCI_SEL_AP 0x80 186253789Srpaulo 187253789Srpaulo uint8_t chip_version; 188253789Srpaulo uint16_t custid; 189253789Srpaulo uint8_t rf_config; 190288357Sadrian//0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R 191253789Srpaulo uint8_t nendpoints; 192253789Srpaulo /* QWORD1 */ 193253789Srpaulo uint32_t regulatory; 194253789Srpaulo uint8_t rfintfs; 195253789Srpaulo uint8_t def_nettype; 196253789Srpaulo uint8_t turbo_mode; 197253789Srpaulo uint8_t lowpower_mode; 198253789Srpaulo /* QWORD2 */ 199253789Srpaulo uint8_t lbk_mode; 200253789Srpaulo uint8_t mp_mode; 201253789Srpaulo uint8_t vcs_type; 202253789Srpaulo#define R92S_VCS_TYPE_DISABLE 0 203253789Srpaulo#define R92S_VCS_TYPE_ENABLE 1 204253789Srpaulo#define R92S_VCS_TYPE_AUTO 2 205253789Srpaulo 206253789Srpaulo uint8_t vcs_mode; 207253789Srpaulo#define R92S_VCS_MODE_NONE 0 208253789Srpaulo#define R92S_VCS_MODE_RTS_CTS 1 209253789Srpaulo#define R92S_VCS_MODE_CTS2SELF 2 210253789Srpaulo 211253789Srpaulo uint32_t reserved1; 212253789Srpaulo /* QWORD3 */ 213253789Srpaulo uint8_t qos_en; 214253789Srpaulo uint8_t bw40_en; 215253789Srpaulo uint8_t amsdu2ampdu_en; 216253789Srpaulo uint8_t ampdu_en; 217253789Srpaulo uint8_t rc_offload; 218253789Srpaulo uint8_t agg_offload; 219253789Srpaulo uint16_t reserved2; 220253789Srpaulo /* QWORD4 */ 221253789Srpaulo uint8_t beacon_offload; 222253789Srpaulo uint8_t mlme_offload; 223253789Srpaulo uint8_t hwpc_offload; 224253789Srpaulo uint8_t tcpcsum_offload; 225253789Srpaulo uint8_t tcp_offload; 226253789Srpaulo uint8_t ps_offload; 227253789Srpaulo uint8_t wwlan_offload; 228253789Srpaulo uint8_t reserved3; 229253789Srpaulo /* QWORD5 */ 230253789Srpaulo uint16_t tcp_tx_len; 231253789Srpaulo uint16_t tcp_rx_len; 232253789Srpaulo uint32_t reserved4; 233253789Srpaulo} __packed; 234253789Srpaulo 235253789Srpaulostruct r92s_fw_hdr { 236253789Srpaulo uint16_t signature; 237253789Srpaulo uint16_t version; 238253789Srpaulo uint32_t dmemsz; 239253789Srpaulo uint32_t imemsz; 240253789Srpaulo uint32_t sramsz; 241253789Srpaulo uint32_t privsz; 242253789Srpaulo uint16_t efuse_addr; 243253789Srpaulo uint16_t h2c_resp_addr; 244253789Srpaulo uint32_t svnrev; 245253789Srpaulo uint8_t month; 246253789Srpaulo uint8_t day; 247253789Srpaulo uint8_t hour; 248253789Srpaulo uint8_t minute; 249253789Srpaulo struct r92s_fw_priv priv; 250253789Srpaulo} __packed; 251253789Srpaulo 252253789Srpaulo/* Structure for FW commands and FW events notifications. */ 253253789Srpaulostruct r92s_fw_cmd_hdr { 254253789Srpaulo uint16_t len; 255253789Srpaulo uint8_t code; 256253789Srpaulo uint8_t seq; 257253789Srpaulo#define R92S_FW_CMD_MORE 0x80 258253789Srpaulo 259253789Srpaulo uint32_t reserved; 260253789Srpaulo} __packed; 261253789Srpaulo 262253789Srpaulo/* FW commands codes. */ 263253789Srpaulo#define R92S_CMD_READ_MACREG 0 264253789Srpaulo#define R92S_CMD_WRITE_MACREG 1 265253789Srpaulo#define R92S_CMD_READ_BBREG 2 266253789Srpaulo#define R92S_CMD_WRITE_BBREG 3 267253789Srpaulo#define R92S_CMD_READ_RFREG 4 268253789Srpaulo#define R92S_CMD_WRITE_RFREG 5 269253789Srpaulo#define R92S_CMD_READ_EEPROM 6 270253789Srpaulo#define R92S_CMD_WRITE_EEPROM 7 271253789Srpaulo#define R92S_CMD_READ_EFUSE 8 272253789Srpaulo#define R92S_CMD_WRITE_EFUSE 9 273253789Srpaulo#define R92S_CMD_READ_CAM 10 274253789Srpaulo#define R92S_CMD_WRITE_CAM 11 275253789Srpaulo#define R92S_CMD_SET_BCNITV 12 276253789Srpaulo#define R92S_CMD_SET_MBIDCFG 13 277253789Srpaulo#define R92S_CMD_JOIN_BSS 14 278253789Srpaulo#define R92S_CMD_DISCONNECT 15 279253789Srpaulo#define R92S_CMD_CREATE_BSS 16 280253789Srpaulo#define R92S_CMD_SET_OPMODE 17 281253789Srpaulo#define R92S_CMD_SITE_SURVEY 18 282253789Srpaulo#define R92S_CMD_SET_AUTH 19 283253789Srpaulo#define R92S_CMD_SET_KEY 20 284253789Srpaulo#define R92S_CMD_SET_STA_KEY 21 285253789Srpaulo#define R92S_CMD_SET_ASSOC_STA 22 286253789Srpaulo#define R92S_CMD_DEL_ASSOC_STA 23 287253789Srpaulo#define R92S_CMD_SET_STAPWRSTATE 24 288253789Srpaulo#define R92S_CMD_SET_BASIC_RATE 25 289253789Srpaulo#define R92S_CMD_GET_BASIC_RATE 26 290253789Srpaulo#define R92S_CMD_SET_DATA_RATE 27 291253789Srpaulo#define R92S_CMD_GET_DATA_RATE 28 292253789Srpaulo#define R92S_CMD_SET_PHY_INFO 29 293253789Srpaulo#define R92S_CMD_GET_PHY_INFO 30 294253789Srpaulo#define R92S_CMD_SET_PHY 31 295253789Srpaulo#define R92S_CMD_GET_PHY 32 296253789Srpaulo#define R92S_CMD_READ_RSSI 33 297253789Srpaulo#define R92S_CMD_READ_GAIN 34 298253789Srpaulo#define R92S_CMD_SET_ATIM 35 299253789Srpaulo#define R92S_CMD_SET_PWR_MODE 36 300253789Srpaulo#define R92S_CMD_JOIN_BSS_RPT 37 301253789Srpaulo#define R92S_CMD_SET_RA_TABLE 38 302253789Srpaulo#define R92S_CMD_GET_RA_TABLE 39 303253789Srpaulo#define R92S_CMD_GET_CCX_REPORT 40 304253789Srpaulo#define R92S_CMD_GET_DTM_REPORT 41 305253789Srpaulo#define R92S_CMD_GET_TXRATE_STATS 42 306253789Srpaulo#define R92S_CMD_SET_USB_SUSPEND 43 307253789Srpaulo#define R92S_CMD_SET_H2C_LBK 44 308253789Srpaulo#define R92S_CMD_ADDBA_REQ 45 309253789Srpaulo#define R92S_CMD_SET_CHANNEL 46 310253789Srpaulo#define R92S_CMD_SET_TXPOWER 47 311253789Srpaulo#define R92S_CMD_SWITCH_ANTENNA 48 312253789Srpaulo#define R92S_CMD_SET_CRYSTAL_CAL 49 313253789Srpaulo#define R92S_CMD_SET_SINGLE_CARRIER_TX 50 314253789Srpaulo#define R92S_CMD_SET_SINGLE_TONE_TX 51 315253789Srpaulo#define R92S_CMD_SET_CARRIER_SUPPR_TX 52 316253789Srpaulo#define R92S_CMD_SET_CONTINUOUS_TX 53 317253789Srpaulo#define R92S_CMD_SWITCH_BANDWIDTH 54 318253789Srpaulo#define R92S_CMD_TX_BEACON 55 319253789Srpaulo#define R92S_CMD_SET_POWER_TRACKING 56 320253789Srpaulo#define R92S_CMD_AMSDU_TO_AMPDU 57 321253789Srpaulo#define R92S_CMD_SET_MAC_ADDRESS 58 322253789Srpaulo#define R92S_CMD_GET_H2C_LBK 59 323253789Srpaulo#define R92S_CMD_SET_PBREQ_IE 60 324253789Srpaulo#define R92S_CMD_SET_ASSOCREQ_IE 61 325253789Srpaulo#define R92S_CMD_SET_PBRESP_IE 62 326253789Srpaulo#define R92S_CMD_SET_ASSOCRESP_IE 63 327253789Srpaulo#define R92S_CMD_GET_CURDATARATE 64 328253789Srpaulo#define R92S_CMD_GET_TXRETRY_CNT 65 329253789Srpaulo#define R92S_CMD_GET_RXRETRY_CNT 66 330253789Srpaulo#define R92S_CMD_GET_BCNOK_CNT 67 331253789Srpaulo#define R92S_CMD_GET_BCNERR_CNT 68 332253789Srpaulo#define R92S_CMD_GET_CURTXPWR_LEVEL 69 333253789Srpaulo#define R92S_CMD_SET_DIG 70 334253789Srpaulo#define R92S_CMD_SET_RA 71 335253789Srpaulo#define R92S_CMD_SET_PT 72 336253789Srpaulo#define R92S_CMD_READ_TSSI 73 337253789Srpaulo 338253789Srpaulo/* FW events notifications codes. */ 339253789Srpaulo#define R92S_EVT_READ_MACREG 0 340253789Srpaulo#define R92S_EVT_READ_BBREG 1 341253789Srpaulo#define R92S_EVT_READ_RFREG 2 342253789Srpaulo#define R92S_EVT_READ_EEPROM 3 343253789Srpaulo#define R92S_EVT_READ_EFUSE 4 344253789Srpaulo#define R92S_EVT_READ_CAM 5 345253789Srpaulo#define R92S_EVT_GET_BASICRATE 6 346253789Srpaulo#define R92S_EVT_GET_DATARATE 7 347253789Srpaulo#define R92S_EVT_SURVEY 8 348253789Srpaulo#define R92S_EVT_SURVEY_DONE 9 349253789Srpaulo#define R92S_EVT_JOIN_BSS 10 350253789Srpaulo#define R92S_EVT_ADD_STA 11 351253789Srpaulo#define R92S_EVT_DEL_STA 12 352253789Srpaulo#define R92S_EVT_ATIM_DONE 13 353253789Srpaulo#define R92S_EVT_TX_REPORT 14 354253789Srpaulo#define R92S_EVT_CCX_REPORT 15 355253789Srpaulo#define R92S_EVT_DTM_REPORT 16 356253789Srpaulo#define R92S_EVT_TXRATE_STATS 17 357253789Srpaulo#define R92S_EVT_C2H_LBK 18 358253789Srpaulo#define R92S_EVT_FWDBG 19 359253789Srpaulo#define R92S_EVT_C2H_FEEDBACK 20 360253789Srpaulo#define R92S_EVT_ADDBA 21 361253789Srpaulo#define R92S_EVT_C2H_BCN 22 362253789Srpaulo#define R92S_EVT_PWR_STATE 23 363253789Srpaulo#define R92S_EVT_WPS_PBC 24 364253789Srpaulo#define R92S_EVT_ADDBA_REQ_REPORT 25 365253789Srpaulo 366253789Srpaulo/* Structure for R92S_CMD_SITE_SURVEY. */ 367253789Srpaulostruct r92s_fw_cmd_sitesurvey { 368253789Srpaulo uint32_t active; 369253789Srpaulo uint32_t limit; 370253789Srpaulo uint32_t ssidlen; 371253789Srpaulo uint8_t ssid[32 + 1]; 372253789Srpaulo} __packed; 373253789Srpaulo 374253789Srpaulo/* Structure for R92S_CMD_SET_AUTH. */ 375253789Srpaulostruct r92s_fw_cmd_auth { 376253789Srpaulo uint8_t mode; 377253789Srpaulo#define R92S_AUTHMODE_OPEN 0 378253789Srpaulo#define R92S_AUTHMODE_SHARED 1 379253789Srpaulo#define R92S_AUTHMODE_WPA 2 380253789Srpaulo 381253789Srpaulo uint8_t dot1x; 382253789Srpaulo} __packed; 383253789Srpaulo 384253789Srpaulo/* Structure for R92S_CMD_SET_KEY. */ 385253789Srpaulostruct r92s_fw_cmd_set_key { 386253789Srpaulo uint8_t algo; 387253789Srpaulo#define R92S_KEY_ALGO_NONE 0 388253789Srpaulo#define R92S_KEY_ALGO_WEP40 1 389253789Srpaulo#define R92S_KEY_ALGO_TKIP 2 390253789Srpaulo#define R92S_KEY_ALGO_TKIP_MMIC 3 391253789Srpaulo#define R92S_KEY_ALGO_AES 4 392253789Srpaulo#define R92S_KEY_ALGO_WEP104 5 393253789Srpaulo 394253789Srpaulo uint8_t id; 395253789Srpaulo uint8_t grpkey; 396253789Srpaulo uint8_t key[16]; 397253789Srpaulo} __packed; 398253789Srpaulo 399253789Srpaulo/* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */ 400253789Srpaulo/* NDIS_802_11_SSID. */ 401253789Srpaulostruct ndis_802_11_ssid { 402253789Srpaulo uint32_t ssidlen; 403253789Srpaulo uint8_t ssid[32]; 404253789Srpaulo} __packed; 405253789Srpaulo 406253789Srpaulo/* NDIS_802_11_CONFIGURATION_FH. */ 407253789Srpaulostruct ndis_802_11_configuration_fh { 408253789Srpaulo uint32_t len; 409253789Srpaulo uint32_t hoppattern; 410253789Srpaulo uint32_t hopset; 411253789Srpaulo uint32_t dwelltime; 412253789Srpaulo} __packed; 413253789Srpaulo 414253789Srpaulo/* NDIS_802_11_CONFIGURATION. */ 415253789Srpaulostruct ndis_802_11_configuration { 416253789Srpaulo uint32_t len; 417253789Srpaulo uint32_t bintval; 418253789Srpaulo uint32_t atim; 419253789Srpaulo uint32_t dsconfig; 420253789Srpaulo struct ndis_802_11_configuration_fh fhconfig; 421253789Srpaulo} __packed; 422253789Srpaulo 423253789Srpaulo/* NDIS_WLAN_BSSID_EX. */ 424253789Srpaulostruct ndis_wlan_bssid_ex { 425253789Srpaulo uint32_t len; 426253789Srpaulo uint8_t macaddr[IEEE80211_ADDR_LEN]; 427253789Srpaulo uint8_t reserved[2]; 428253789Srpaulo struct ndis_802_11_ssid ssid; 429253789Srpaulo uint32_t privacy; 430253789Srpaulo int32_t rssi; 431253789Srpaulo uint32_t networktype; 432253789Srpaulo#define NDIS802_11FH 0 433253789Srpaulo#define NDIS802_11DS 1 434253789Srpaulo#define NDIS802_11OFDM5 2 435253789Srpaulo#define NDIS802_11OFDM24 3 436253789Srpaulo#define NDIS802_11AUTOMODE 4 437253789Srpaulo 438253789Srpaulo struct ndis_802_11_configuration config; 439253789Srpaulo uint32_t inframode; 440253789Srpaulo#define NDIS802_11IBSS 0 441253789Srpaulo#define NDIS802_11INFRASTRUCTURE 1 442253789Srpaulo#define NDIS802_11AUTOUNKNOWN 2 443253789Srpaulo#define NDIS802_11MONITOR 3 444253789Srpaulo#define NDIS802_11APMODE 4 445253789Srpaulo 446253789Srpaulo uint8_t supprates[16]; 447253789Srpaulo uint32_t ieslen; 448253789Srpaulo /* Followed by ``ieslen'' bytes. */ 449253789Srpaulo} __packed; 450253789Srpaulo 451253789Srpaulo/* NDIS_802_11_FIXED_IEs. */ 452253789Srpaulostruct ndis_802_11_fixed_ies { 453253789Srpaulo uint8_t tstamp[8]; 454253789Srpaulo uint16_t bintval; 455253789Srpaulo uint16_t capabilities; 456253789Srpaulo} __packed; 457253789Srpaulo 458253789Srpaulo/* Structure for R92S_CMD_SET_PWR_MODE. */ 459253789Srpaulostruct r92s_set_pwr_mode { 460253789Srpaulo uint8_t mode; 461253789Srpaulo#define R92S_PS_MODE_ACTIVE 0 462253789Srpaulo#define R92S_PS_MODE_MIN 1 463253789Srpaulo#define R92S_PS_MODE_MAX 2 464253789Srpaulo#define R92S_PS_MODE_DTIM 3 465253789Srpaulo#define R92S_PS_MODE_VOIP 4 466253789Srpaulo#define R92S_PS_MODE_UAPSD_WMM 5 467253789Srpaulo#define R92S_PS_MODE_UAPSD 6 468253789Srpaulo#define R92S_PS_MODE_IBSS 7 469253789Srpaulo#define R92S_PS_MODE_WWLAN 8 470253789Srpaulo#define R92S_PS_MODE_RADIOOFF 9 471253789Srpaulo#define R92S_PS_MODE_DISABLE 10 472253789Srpaulo 473253789Srpaulo uint8_t low_traffic_en; 474253789Srpaulo uint8_t lpnav_en; 475253789Srpaulo uint8_t rf_low_snr_en; 476253789Srpaulo uint8_t dps_en; 477253789Srpaulo uint8_t bcn_rx_en; 478253789Srpaulo uint8_t bcn_pass_cnt; 479253789Srpaulo uint8_t bcn_to; 480253789Srpaulo uint16_t bcn_itv; 481253789Srpaulo uint8_t app_itv; 482253789Srpaulo uint8_t awake_bcn_itv; 483253789Srpaulo uint8_t smart_ps; 484253789Srpaulo uint8_t bcn_pass_time; 485253789Srpaulo} __packed; 486253789Srpaulo 487253789Srpaulo/* Structure for event R92S_EVENT_JOIN_BSS. */ 488253789Srpaulostruct r92s_event_join_bss { 489253789Srpaulo uint32_t next; 490253789Srpaulo uint32_t prev; 491253789Srpaulo uint32_t networktype; 492253789Srpaulo uint32_t fixed; 493253789Srpaulo uint32_t lastscanned; 494253789Srpaulo uint32_t associd; 495253789Srpaulo uint32_t join_res; 496253789Srpaulo struct ndis_wlan_bssid_ex bss; 497253789Srpaulo} __packed; 498253789Srpaulo 499253789Srpaulo#define R92S_MACID_BSS 5 500253789Srpaulo 501253789Srpaulo/* Rx MAC descriptor. */ 502253789Srpaulostruct r92s_rx_stat { 503253789Srpaulo uint32_t rxdw0; 504253789Srpaulo#define R92S_RXDW0_PKTLEN_M 0x00003fff 505253789Srpaulo#define R92S_RXDW0_PKTLEN_S 0 506253789Srpaulo#define R92S_RXDW0_CRCERR 0x00004000 507253789Srpaulo#define R92S_RXDW0_INFOSZ_M 0x000f0000 508253789Srpaulo#define R92S_RXDW0_INFOSZ_S 16 509253789Srpaulo#define R92S_RXDW0_QOS 0x00800000 510253789Srpaulo#define R92S_RXDW0_SHIFT_M 0x03000000 511253789Srpaulo#define R92S_RXDW0_SHIFT_S 24 512253789Srpaulo#define R92S_RXDW0_DECRYPTED 0x08000000 513253789Srpaulo 514253789Srpaulo uint32_t rxdw1; 515253789Srpaulo#define R92S_RXDW1_MOREFRAG 0x08000000 516253789Srpaulo 517253789Srpaulo uint32_t rxdw2; 518253789Srpaulo#define R92S_RXDW2_FRAG_M 0x0000f000 519253789Srpaulo#define R92S_RXDW2_FRAG_S 12 520253789Srpaulo#define R92S_RXDW2_PKTCNT_M 0x00ff0000 521253789Srpaulo#define R92S_RXDW2_PKTCNT_S 16 522253789Srpaulo 523253789Srpaulo uint32_t rxdw3; 524253789Srpaulo#define R92S_RXDW3_RATE_M 0x0000003f 525253789Srpaulo#define R92S_RXDW3_RATE_S 0 526253789Srpaulo#define R92S_RXDW3_TCPCHKRPT 0x00000800 527253789Srpaulo#define R92S_RXDW3_IPCHKRPT 0x00001000 528253789Srpaulo#define R92S_RXDW3_TCPCHKVALID 0x00002000 529253789Srpaulo#define R92S_RXDW3_HTC 0x00004000 530253789Srpaulo 531253789Srpaulo uint32_t rxdw4; 532253789Srpaulo uint32_t rxdw5; 533266505Shselasky} __packed __aligned(4); 534253789Srpaulo 535253789Srpaulo/* Rx PHY descriptor. */ 536253789Srpaulostruct r92s_rx_phystat { 537253789Srpaulo uint32_t phydw0; 538253789Srpaulo uint32_t phydw1; 539253789Srpaulo uint32_t phydw2; 540253789Srpaulo uint32_t phydw3; 541253789Srpaulo uint32_t phydw4; 542253789Srpaulo uint32_t phydw5; 543253789Srpaulo uint32_t phydw6; 544253789Srpaulo uint32_t phydw7; 545266505Shselasky} __packed __aligned(4); 546253789Srpaulo 547253789Srpaulo/* Rx PHY CCK descriptor. */ 548253789Srpaulostruct r92s_rx_cck { 549253789Srpaulo uint8_t adc_pwdb[4]; 550253789Srpaulo uint8_t sq_rpt; 551253789Srpaulo uint8_t agc_rpt; 552253789Srpaulo} __packed; 553253789Srpaulo 554253789Srpaulo/* Tx MAC descriptor. */ 555253789Srpaulostruct r92s_tx_desc { 556253789Srpaulo uint32_t txdw0; 557253789Srpaulo#define R92S_TXDW0_PKTLEN_M 0x0000ffff 558253789Srpaulo#define R92S_TXDW0_PKTLEN_S 0 559253789Srpaulo#define R92S_TXDW0_OFFSET_M 0x00ff0000 560253789Srpaulo#define R92S_TXDW0_OFFSET_S 16 561253789Srpaulo#define R92S_TXDW0_TYPE_M 0x03000000 562253789Srpaulo#define R92S_TXDW0_TYPE_S 24 563253789Srpaulo#define R92S_TXDW0_LSG 0x04000000 564253789Srpaulo#define R92S_TXDW0_FSG 0x08000000 565253789Srpaulo#define R92S_TXDW0_LINIP 0x10000000 566253789Srpaulo#define R92S_TXDW0_OWN 0x80000000 567253789Srpaulo 568253789Srpaulo uint32_t txdw1; 569253789Srpaulo#define R92S_TXDW1_MACID_M 0x0000001f 570253789Srpaulo#define R92S_TXDW1_MACID_S 0 571253789Srpaulo#define R92S_TXDW1_MOREDATA 0x00000020 572253789Srpaulo#define R92S_TXDW1_MOREFRAG 0x00000040 573253789Srpaulo#define R92S_TXDW1_QSEL_M 0x00001f00 574253789Srpaulo#define R92S_TXDW1_QSEL_S 8 575253789Srpaulo#define R92S_TXDW1_QSEL_BE 0x03 576253789Srpaulo#define R92S_TXDW1_QSEL_H2C 0x1f 577253789Srpaulo#define R92S_TXDW1_NONQOS 0x00010000 578253789Srpaulo#define R92S_TXDW1_KEYIDX_M 0x00060000 579253789Srpaulo#define R92S_TXDW1_KEYIDX_S 17 580253789Srpaulo#define R92S_TXDW1_CIPHER_M 0x00c00000 581253789Srpaulo#define R92S_TXDW1_CIPHER_S 22 582253789Srpaulo#define R92S_TXDW1_CIPHER_WEP 1 583253789Srpaulo#define R92S_TXDW1_CIPHER_TKIP 2 584253789Srpaulo#define R92S_TXDW1_CIPHER_AES 3 585253789Srpaulo#define R92S_TXDW1_HWPC 0x80000000 586253789Srpaulo 587253789Srpaulo uint32_t txdw2; 588253789Srpaulo#define R92S_TXDW2_BMCAST 0x00000080 589253789Srpaulo#define R92S_TXDW2_AGGEN 0x20000000 590253789Srpaulo#define R92S_TXDW2_BK 0x40000000 591253789Srpaulo 592253789Srpaulo uint32_t txdw3; 593253789Srpaulo#define R92S_TXDW3_SEQ_M 0x0fff0000 594253789Srpaulo#define R92S_TXDW3_SEQ_S 16 595253789Srpaulo#define R92S_TXDW3_FRAG_M 0xf0000000 596253789Srpaulo#define R92S_TXDW3_FRAG_S 28 597253789Srpaulo 598253789Srpaulo uint32_t txdw4; 599253789Srpaulo#define R92S_TXDW4_TXBW 0x00040000 600253789Srpaulo 601253789Srpaulo uint32_t txdw5; 602253789Srpaulo#define R92S_TXDW5_DISFB 0x00008000 603253789Srpaulo 604253789Srpaulo uint16_t ipchksum; 605253789Srpaulo uint16_t tcpchksum; 606253789Srpaulo 607253789Srpaulo uint16_t txbufsize; 608253789Srpaulo uint16_t reserved1; 609266505Shselasky} __packed __aligned(4); 610253789Srpaulo 611287949Sadrianstruct r92s_add_ba_event { 612287949Sadrian uint8_t mac_addr[IEEE80211_ADDR_LEN]; 613287949Sadrian uint16_t ssn; 614287949Sadrian uint8_t tid; 615287949Sadrian}; 616253789Srpaulo 617288089Sadrianstruct r92s_add_ba_req { 618288089Sadrian uint32_t tid; 619288089Sadrian}; 620288089Sadrian 621253789Srpaulo/* 622253789Srpaulo * Driver definitions. 623253789Srpaulo */ 624287893Sadrian#define RSU_RX_LIST_COUNT 100 625253789Srpaulo#define RSU_TX_LIST_COUNT 32 626253789Srpaulo 627253789Srpaulo#define RSU_HOST_CMD_RING_COUNT 32 628253789Srpaulo 629253789Srpaulo#define RSU_RXBUFSZ (8 * 1024) 630253789Srpaulo#define RSU_TXBUFSZ \ 631253789Srpaulo ((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3) 632253789Srpaulo 633253789Srpaulo#define RSU_TX_TIMEOUT 5000 /* ms */ 634253789Srpaulo#define RSU_CMD_TIMEOUT 2000 /* ms */ 635253789Srpaulo 636253789Srpaulo/* Queue ids (used by soft only). */ 637253789Srpaulo#define RSU_QID_BCN 0 638253789Srpaulo#define RSU_QID_MGT 1 639253789Srpaulo#define RSU_QID_BMC 2 640253789Srpaulo#define RSU_QID_VO 3 641253789Srpaulo#define RSU_QID_VI 4 642253789Srpaulo#define RSU_QID_BE 5 643253789Srpaulo#define RSU_QID_BK 6 644253789Srpaulo#define RSU_QID_RXOFF 7 645253789Srpaulo#define RSU_QID_H2C 8 646253789Srpaulo#define RSU_QID_C2H 9 647253789Srpaulo 648253789Srpaulo/* Map AC to queue id. */ 649253789Srpaulostatic const uint8_t rsu_ac2qid[WME_NUM_AC] = { 650253789Srpaulo RSU_QID_BE, 651253789Srpaulo RSU_QID_BK, 652253789Srpaulo RSU_QID_VI, 653253789Srpaulo RSU_QID_VO 654253789Srpaulo}; 655253789Srpaulo 656253789Srpaulo/* Pipe index to endpoint address mapping. */ 657253789Srpaulostatic const uint8_t r92s_epaddr[] = 658253789Srpaulo { 0x83, 0x04, 0x06, 0x0d, 659253789Srpaulo 0x05, 0x07, 660253789Srpaulo 0x89, 0x0a, 0x0b, 0x0c }; 661253789Srpaulo 662253789Srpaulo/* Queue id to pipe index mapping for 4 endpoints configurations. */ 663253789Srpaulostatic const uint8_t rsu_qid2idx_4ep[] = 664253789Srpaulo { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 }; 665253789Srpaulo 666253789Srpaulo/* Queue id to pipe index mapping for 6 endpoints configurations. */ 667253789Srpaulostatic const uint8_t rsu_qid2idx_6ep[] = 668253789Srpaulo { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 }; 669253789Srpaulo 670253789Srpaulo/* Queue id to pipe index mapping for 11 endpoints configurations. */ 671253789Srpaulostatic const uint8_t rsu_qid2idx_11ep[] = 672253789Srpaulo { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 }; 673253789Srpaulo 674253789Srpaulostruct rsu_rx_radiotap_header { 675253789Srpaulo struct ieee80211_radiotap_header wr_ihdr; 676253789Srpaulo uint8_t wr_flags; 677253789Srpaulo uint8_t wr_rate; 678253789Srpaulo uint16_t wr_chan_freq; 679253789Srpaulo uint16_t wr_chan_flags; 680253789Srpaulo uint8_t wr_dbm_antsignal; 681253789Srpaulo} __packed __aligned(8); 682253789Srpaulo 683253789Srpaulo#define RSU_RX_RADIOTAP_PRESENT \ 684253789Srpaulo (1 << IEEE80211_RADIOTAP_FLAGS | \ 685253789Srpaulo 1 << IEEE80211_RADIOTAP_RATE | \ 686253789Srpaulo 1 << IEEE80211_RADIOTAP_CHANNEL | \ 687253789Srpaulo 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 688253789Srpaulo 689253789Srpaulostruct rsu_tx_radiotap_header { 690253789Srpaulo struct ieee80211_radiotap_header wt_ihdr; 691253789Srpaulo uint8_t wt_flags; 692345636Savos uint8_t wt_pad; 693253789Srpaulo uint16_t wt_chan_freq; 694253789Srpaulo uint16_t wt_chan_flags; 695345636Savos} __packed; 696253789Srpaulo 697253789Srpaulo#define RSU_TX_RADIOTAP_PRESENT \ 698253789Srpaulo (1 << IEEE80211_RADIOTAP_FLAGS | \ 699253789Srpaulo 1 << IEEE80211_RADIOTAP_CHANNEL) 700253789Srpaulo 701253789Srpaulostruct rsu_softc; 702253789Srpaulo 703253789Srpaulostruct rsu_host_cmd { 704253789Srpaulo void (*cb)(struct rsu_softc *, void *); 705253789Srpaulo uint8_t data[256]; 706253789Srpaulo}; 707253789Srpaulo 708253789Srpaulostruct rsu_cmd_newstate { 709253789Srpaulo enum ieee80211_state state; 710253789Srpaulo int arg; 711253789Srpaulo}; 712253789Srpaulo 713253789Srpaulostruct rsu_cmd_key { 714253789Srpaulo struct ieee80211_key key; 715253789Srpaulo}; 716253789Srpaulo 717253789Srpaulostruct rsu_host_cmd_ring { 718253789Srpaulo struct rsu_host_cmd cmd[RSU_HOST_CMD_RING_COUNT]; 719253789Srpaulo int cur; 720253789Srpaulo int next; 721253789Srpaulo int queued; 722253789Srpaulo}; 723253789Srpaulo 724253789Srpauloenum { 725253789Srpaulo RSU_BULK_RX, 726267041Shselasky RSU_BULK_TX_BE_BK, /* = WME_AC_BE/BK */ 727267041Shselasky RSU_BULK_TX_VI_VO, /* = WME_AC_VI/VO */ 728287896Sadrian RSU_BULK_TX_H2C, /* H2C */ 729267041Shselasky RSU_N_TRANSFER, 730253789Srpaulo}; 731253789Srpaulo 732253789Srpaulostruct rsu_data { 733253789Srpaulo struct rsu_softc *sc; 734253789Srpaulo uint8_t *buf; 735253789Srpaulo uint16_t buflen; 736253789Srpaulo struct mbuf *m; 737253789Srpaulo struct ieee80211_node *ni; 738253789Srpaulo STAILQ_ENTRY(rsu_data) next; 739253789Srpaulo}; 740253789Srpaulo 741253789Srpaulostruct rsu_vap { 742253789Srpaulo struct ieee80211vap vap; 743253789Srpaulo 744253789Srpaulo int (*newstate)(struct ieee80211vap *, 745253789Srpaulo enum ieee80211_state, int); 746253789Srpaulo}; 747253789Srpaulo#define RSU_VAP(vap) ((struct rsu_vap *)(vap)) 748253789Srpaulo 749253789Srpaulo#define RSU_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 750253789Srpaulo#define RSU_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 751253789Srpaulo#define RSU_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 752253789Srpaulo 753253789Srpaulostruct rsu_softc { 754287197Sglebius struct ieee80211com sc_ic; 755287197Sglebius struct mbufq sc_snd; 756253789Srpaulo device_t sc_dev; 757253789Srpaulo struct usb_device *sc_udev; 758253789Srpaulo int (*sc_newstate)(struct ieee80211com *, 759253789Srpaulo enum ieee80211_state, int); 760253789Srpaulo struct usbd_interface *sc_iface; 761253789Srpaulo struct timeout_task calib_task; 762288052Sadrian struct task tx_task; 763253789Srpaulo const uint8_t *qid2idx; 764253789Srpaulo struct mtx sc_mtx; 765287894Sadrian int sc_ht; 766287894Sadrian int sc_nendpoints; 767288094Sadrian int sc_curpwrstate; 768288414Sadrian int sc_currssi; 769253789Srpaulo 770287197Sglebius u_int sc_running:1, 771287197Sglebius sc_calibrating:1, 772287954Sadrian sc_scanning:1, 773287197Sglebius sc_scan_pass:1; 774253789Srpaulo u_int cut; 775288357Sadrian uint8_t sc_rftype; 776288357Sadrian int8_t sc_nrxstream; 777288357Sadrian int8_t sc_ntxstream; 778253789Srpaulo struct rsu_host_cmd_ring cmdq; 779253789Srpaulo struct rsu_data sc_rx[RSU_RX_LIST_COUNT]; 780253789Srpaulo struct rsu_data sc_tx[RSU_TX_LIST_COUNT]; 781253789Srpaulo struct rsu_data *fwcmd_data; 782253789Srpaulo uint8_t cmd_seq; 783253789Srpaulo uint8_t rom[128]; 784253789Srpaulo struct usb_xfer *sc_xfer[RSU_N_TRANSFER]; 785253789Srpaulo 786253789Srpaulo STAILQ_HEAD(, rsu_data) sc_rx_active; 787253789Srpaulo STAILQ_HEAD(, rsu_data) sc_rx_inactive; 788267041Shselasky STAILQ_HEAD(, rsu_data) sc_tx_active[RSU_N_TRANSFER]; 789253789Srpaulo STAILQ_HEAD(, rsu_data) sc_tx_inactive; 790267041Shselasky STAILQ_HEAD(, rsu_data) sc_tx_pending[RSU_N_TRANSFER]; 791253789Srpaulo 792253789Srpaulo union { 793253789Srpaulo struct rsu_rx_radiotap_header th; 794253789Srpaulo uint8_t pad[64]; 795253789Srpaulo } sc_rxtapu; 796253789Srpaulo#define sc_rxtap sc_rxtapu.th 797253789Srpaulo 798253789Srpaulo union { 799253789Srpaulo struct rsu_tx_radiotap_header th; 800253789Srpaulo uint8_t pad[64]; 801253789Srpaulo } sc_txtapu; 802253789Srpaulo#define sc_txtap sc_txtapu.th 803253789Srpaulo}; 804