udl.h revision 278853
1278799Shselasky/* $OpenBSD: udl.h,v 1.21 2013/04/15 09:23:02 mglocker Exp $ */ 2278799Shselasky/* $FreeBSD: head/sys/dev/usb/video/udl.h 278853 2015-02-16 15:47:55Z hselasky $ */ 3278799Shselasky 4278799Shselasky/* 5278799Shselasky * Copyright (c) 2009 Marcus Glocker <mglocker@openbsd.org> 6278799Shselasky * 7278799Shselasky * Permission to use, copy, modify, and distribute this software for any 8278799Shselasky * purpose with or without fee is hereby granted, provided that the above 9278799Shselasky * copyright notice and this permission notice appear in all copies. 10278799Shselasky * 11278799Shselasky * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12278799Shselasky * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13278799Shselasky * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14278799Shselasky * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15278799Shselasky * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16278799Shselasky * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17278799Shselasky * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18278799Shselasky */ 19278799Shselasky 20278799Shselasky#ifndef _UDL_H_ 21278799Shselasky#define _UDL_H_ 22278799Shselasky 23278799Shselasky#include <sys/types.h> 24278799Shselasky#include <sys/queue.h> 25278799Shselasky 26278799Shselasky/* 27278799Shselasky * BULK command transfer structure. 28278799Shselasky */ 29278799Shselasky#define UDL_CMD_MAX_FRAMES 64 /* units */ 30278799Shselasky#define UDL_CMD_MAX_DATA_SIZE 512 /* bytes */ 31278799Shselasky#define UDL_CMD_MAX_HEAD_SIZE 16 /* bytes */ 32278799Shselasky#define UDL_CMD_MAX_PIXEL_COUNT ((UDL_CMD_MAX_DATA_SIZE - UDL_CMD_MAX_HEAD_SIZE) / 2) 33278853Shselasky#define UDL_CMD_MAX_BUFFERS (3 * UDL_CMD_MAX_FRAMES) 34278799Shselasky#define UDL_FONT_HEIGHT 16 /* pixels */ 35278799Shselasky#define UDL_MAX_MODES 25 /* units */ 36278799Shselasky 37278799Shselaskystruct udl_cmd_buf { 38278799Shselasky TAILQ_ENTRY(udl_cmd_buf) entry; 39278799Shselasky uint32_t off; 40278799Shselasky uint8_t buf[UDL_CMD_MAX_DATA_SIZE] __aligned(4); 41278799Shselasky}; 42278799Shselasky 43278799ShselaskyTAILQ_HEAD(udl_cmd_head, udl_cmd_buf); 44278799Shselasky 45278799Shselaskyenum { 46278799Shselasky UDL_BULK_WRITE_0, 47278799Shselasky UDL_BULK_WRITE_1, 48278799Shselasky UDL_N_TRANSFER, 49278799Shselasky}; 50278799Shselasky 51278799Shselasky/* 52278799Shselasky * Our per device structure. 53278799Shselasky */ 54278799Shselaskystruct udl_softc { 55278799Shselasky struct mtx sc_mtx; 56278799Shselasky struct cv sc_cv; 57278799Shselasky struct callout sc_callout; 58278799Shselasky struct usb_xfer *sc_xfer[UDL_N_TRANSFER]; 59278799Shselasky struct usb_device *sc_udev; 60278799Shselasky device_t sc_fbdev; 61278799Shselasky struct fb_info sc_fb_info; 62278799Shselasky uint8_t sc_edid[128]; 63278799Shselasky struct edid_info sc_edid_info; 64278799Shselasky struct udl_cmd_head sc_xfer_head[2]; 65278799Shselasky struct udl_cmd_head sc_cmd_buf_free; 66278799Shselasky struct udl_cmd_head sc_cmd_buf_pending; 67278799Shselasky struct udl_cmd_buf sc_cmd_buf_temp[UDL_CMD_MAX_BUFFERS]; 68278799Shselasky uint32_t sc_sync_off; 69278799Shselasky uint32_t sc_fb_size; 70278799Shselasky uint8_t *sc_fb_addr; 71278799Shselasky uint8_t *sc_fb_copy; 72278799Shselasky int sc_def_chip; /* default chip version */ 73278799Shselasky int sc_chip; 74278799Shselasky#define DLALL 0x0000 75278799Shselasky#define DL125 0x0000 /* max 1280x1024, 1440x900 */ 76278799Shselasky#define DL120 0x0001 /* max 1280x1024, 1440x1050 */ 77278799Shselasky#define DL160 0x0002 /* max 1600x1200, 1680x1050 */ 78278799Shselasky#define DL165 0x0003 /* max 1600x1200, 1920x1080 */ 79278799Shselasky#define DL195 0x0004 /* max 1920x1200, 2048x1152 */ 80278799Shselasky#define DLMAX 0x0004 81278799Shselasky#define DLUNK 0x00ff /* unknown */ 82278799Shselasky int sc_def_mode; /* default mode */ 83278799Shselasky int sc_cur_mode; 84278799Shselasky uint8_t sc_power_save; /* set if power save is enabled */ 85278799Shselasky uint8_t sc_gone; 86278799Shselasky}; 87278799Shselasky 88278799Shselasky#define UDL_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 89278799Shselasky#define UDL_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 90278799Shselasky 91278799Shselasky/* 92278799Shselasky * Chip commands. 93278799Shselasky */ 94278799Shselasky#define UDL_CTRL_CMD_READ_EDID 0x02 95278799Shselasky#define UDL_CTRL_CMD_WRITE_1 0x03 96278799Shselasky#define UDL_CTRL_CMD_READ_1 0x04 97278799Shselasky#define UDL_CTRL_CMD_POLL 0x06 98278799Shselasky#define UDL_CTRL_CMD_SET_KEY 0x12 99278799Shselasky 100278799Shselasky#define UDL_BULK_SOC 0xaf /* start of command token */ 101278799Shselasky 102278799Shselasky#define UDL_BULK_CMD_REG_WRITE_1 0x20 /* write 1 byte to register */ 103278799Shselasky#define UDL_BULK_CMD_EOC 0xa0 /* end of command stack */ 104278799Shselasky#define UDL_BULK_CMD_DECOMP 0xe0 /* send decompression table */ 105278799Shselasky 106278799Shselasky#define UDL_BULK_CMD_FB_BASE 0x60 107278799Shselasky#define UDL_BULK_CMD_FB_WORD 0x08 108278799Shselasky#define UDL_BULK_CMD_FB_COMP 0x10 109278799Shselasky#define UDL_BULK_CMD_FB_WRITE (UDL_BULK_CMD_FB_BASE | 0x00) 110278799Shselasky#define UDL_BULK_CMD_FB_COPY (UDL_BULK_CMD_FB_BASE | 0x02) 111278799Shselasky 112278799Shselasky/* 113278799Shselasky * Chip registers. 114278799Shselasky */ 115278799Shselasky#define UDL_REG_ADDR_START16 0x20 116278799Shselasky#define UDL_REG_ADDR_STRIDE16 0x23 117278799Shselasky#define UDL_REG_ADDR_START8 0x26 118278799Shselasky#define UDL_REG_ADDR_STRIDE8 0x29 119278799Shselasky 120278799Shselasky#define UDL_REG_SCREEN 0x1f 121278799Shselasky#define UDL_REG_SCREEN_ON 0x00 122278799Shselasky#define UDL_REG_SCREEN_OFF 0x01 123278799Shselasky#define UDL_REG_SYNC 0xff 124278799Shselasky 125278799Shselasky#define UDL_MODE_SIZE 29 126278799Shselasky 127278799Shselasky/* 128278799Shselasky * Register values for screen resolution initialization. 129278799Shselasky */ 130278799Shselaskystatic const uint8_t udl_reg_vals_640x480_60[UDL_MODE_SIZE] = { /* 25.17 Mhz 59.9 Hz 131278799Shselasky * VESA std */ 132278799Shselasky 0x00, 0x99, 0x30, 0x26, 0x94, 0x60, 0xa9, 0xce, 0x60, 0x07, 0xb3, 0x0f, 133278799Shselasky 0x79, 0xff, 0xff, 0x02, 0x80, 0x83, 0xbc, 0xff, 0xfc, 0xff, 0xff, 0x01, 134278799Shselasky 0xe0, 0x01, 0x02, 0xab, 0x13 135278799Shselasky}; 136278799Shselaskystatic const uint8_t udl_reg_vals_640x480_67[UDL_MODE_SIZE] = { /* 30.25 MHz 66.6 Hz MAC 137278799Shselasky * std */ 138278799Shselasky 0x00, 0x1d, 0x33, 0x07, 0xb3, 0x60, 0xa9, 0xce, 0x60, 0xb6, 0xa8, 0xff, 139278799Shselasky 0xff, 0xbf, 0x70, 0x02, 0x80, 0x83, 0xbc, 0xff, 0xff, 0xff, 0xf9, 0x01, 140278799Shselasky 0xe0, 0x01, 0x02, 0xa2, 0x17 141278799Shselasky}; 142278799Shselaskystatic const uint8_t udl_reg_vals_640x480_72[UDL_MODE_SIZE] = { /* 31.50 Mhz 72.8 Hz 143278799Shselasky * VESA std */ 144278799Shselasky 0x00, 0x2b, 0xeb, 0x35, 0xd3, 0x0a, 0x95, 0xe6, 0x0e, 0x0f, 0xb5, 0x15, 145278799Shselasky 0x2a, 0xff, 0xff, 0x02, 0x80, 0xcc, 0x1d, 0xff, 0xf9, 0xff, 0xff, 0x01, 146278799Shselasky 0xe0, 0x01, 0x02, 0x9c, 0x18 147278799Shselasky}; 148278799Shselaskystatic const uint8_t udl_reg_vals_640x480_75[UDL_MODE_SIZE] = { /* 31.50 Mhz 75.7 Hz 149278799Shselasky * VESA std */ 150278799Shselasky 0x00, 0xeb, 0xf7, 0xd3, 0x0f, 0x4f, 0x93, 0xfa, 0x47, 0xb5, 0x58, 0xff, 151278799Shselasky 0xff, 0xbf, 0x70, 0x02, 0x80, 0xf4, 0x8f, 0xff, 0xff, 0xff, 0xf9, 0x01, 152278799Shselasky 0xe0, 0x01, 0x02, 0x9c, 0x18 153278799Shselasky}; 154278799Shselaskystatic const uint8_t udl_reg_vals_800x480_61[UDL_MODE_SIZE] = { /* 33.00 MHz 61.9 Hz */ 155278799Shselasky 0x00, 0x20, 0x3c, 0x7a, 0xc9, 0xf2, 0x6c, 0x48, 0xf9, 0x70, 0x53, 0xff, 156278799Shselasky 0xff, 0x21, 0x27, 0x03, 0x20, 0x91, 0xf3, 0xff, 0xff, 0xff, 0xf9, 0x01, 157278799Shselasky 0xe0, 0x01, 0x02, 0xc8, 0x19 158278799Shselasky}; 159278799Shselaskystatic const uint8_t udl_reg_vals_800x600_56[UDL_MODE_SIZE] = { /* 36.00 MHz 56.2 Hz 160278799Shselasky * VESA std */ 161278799Shselasky 0x00, 0x65, 0x35, 0x48, 0xf4, 0xf2, 0x6c, 0x19, 0x18, 0xc9, 0x4b, 0xff, 162278799Shselasky 0xff, 0x70, 0x35, 0x03, 0x20, 0x32, 0x31, 0xff, 0xff, 0xff, 0xfc, 0x02, 163278799Shselasky 0x58, 0x01, 0x02, 0x20, 0x1c 164278799Shselasky}; 165278799Shselaskystatic const uint8_t udl_reg_vals_800x600_60[UDL_MODE_SIZE] = { /* 40.00 MHz 60.3 Hz 166278799Shselasky * VESA std */ 167278799Shselasky 0x00, 0x20, 0x3c, 0x7a, 0xc9, 0x93, 0x60, 0xc8, 0xc7, 0x70, 0x53, 0xff, 168278799Shselasky 0xff, 0x21, 0x27, 0x03, 0x20, 0x91, 0x8f, 0xff, 0xff, 0xff, 0xf2, 0x02, 169278799Shselasky 0x58, 0x01, 0x02, 0x40, 0x1f 170278799Shselasky}; 171278799Shselaskystatic const uint8_t udl_reg_vals_800x600_72[UDL_MODE_SIZE] = { /* 50.00 MHz 72.1 Hz 172278799Shselasky * VESA std */ 173278799Shselasky 0x00, 0xeb, 0xf7, 0xd1, 0x90, 0x4d, 0x82, 0x23, 0x1f, 0x39, 0xcf, 0xff, 174278799Shselasky 0xff, 0x43, 0x21, 0x03, 0x20, 0x62, 0xc5, 0xff, 0xff, 0xff, 0xca, 0x02, 175278799Shselasky 0x58, 0x01, 0x02, 0x10, 0x27 176278799Shselasky}; 177278799Shselaskystatic const uint8_t udl_reg_vals_800x600_74[UDL_MODE_SIZE] = { /* 50.00 MHz 74.4 Hz */ 178278799Shselasky 0x00, 0xb3, 0x76, 0x39, 0xcf, 0x60, 0xa9, 0xc7, 0xf4, 0x70, 0x53, 0xff, 179278799Shselasky 0xff, 0x35, 0x33, 0x03, 0x20, 0x8f, 0xe9, 0xff, 0xff, 0xff, 0xf9, 0x02, 180278799Shselasky 0x58, 0x01, 0x02, 0x10, 0x27 181278799Shselasky}; 182278799Shselaskystatic const uint8_t udl_reg_vals_800x600_75[UDL_MODE_SIZE] = { /* 49.50 MHz 75.0 Hz 183278799Shselasky * VESA std */ 184278799Shselasky 0x00, 0xb3, 0x76, 0x39, 0xcf, 0xf2, 0x6c, 0x19, 0x18, 0x70, 0x53, 0xff, 185278799Shselasky 0xff, 0x35, 0x33, 0x03, 0x20, 0x32, 0x31, 0xff, 0xff, 0xff, 0xf9, 0x02, 186278799Shselasky 0x58, 0x01, 0x02, 0xac, 0x26 187278799Shselasky}; 188278799Shselaskystatic const uint8_t udl_reg_vals_1024x768_60[UDL_MODE_SIZE] = { /* 65.00 MHz 60.0 Hz 189278799Shselasky * VESA std */ 190278799Shselasky 0x00, 0x36, 0x18, 0xd5, 0x10, 0x60, 0xa9, 0x7b, 0x33, 0xa1, 0x2b, 0x27, 191278799Shselasky 0x32, 0xff, 0xff, 0x04, 0x00, 0xd9, 0x9a, 0xff, 0xca, 0xff, 0xff, 0x03, 192278799Shselasky 0x00, 0x04, 0x03, 0xc8, 0x32 193278799Shselasky}; 194278799Shselaskystatic const uint8_t udl_reg_vals_1024x768_70[UDL_MODE_SIZE] = { /* 75.00 MHz 70.0 Hz 195278799Shselasky * VESA std */ 196278799Shselasky 0x00, 0xb4, 0xed, 0x4c, 0x5e, 0x60, 0xa9, 0x7b, 0x33, 0x10, 0x4d, 0xff, 197278799Shselasky 0xff, 0x27, 0x32, 0x04, 0x00, 0xd9, 0x9a, 0xff, 0xff, 0xff, 0xca, 0x03, 198278799Shselasky 0x00, 0x04, 0x02, 0x98, 0x3a 199278799Shselasky}; 200278799Shselaskystatic const uint8_t udl_reg_vals_1024x768_75[UDL_MODE_SIZE] = { /* 78.75 MHz 75.0 Hz 201278799Shselasky * VESA std */ 202278799Shselasky 0x00, 0xec, 0xb4, 0xa0, 0x4c, 0x36, 0x0a, 0x07, 0xb3, 0x5e, 0xd5, 0xff, 203278799Shselasky 0xff, 0x0f, 0x79, 0x04, 0x00, 0x0f, 0x66, 0xff, 0xff, 0xff, 0xf9, 0x03, 204278799Shselasky 0x00, 0x04, 0x02, 0x86, 0x3d 205278799Shselasky}; 206278799Shselaskystatic const uint8_t udl_reg_vals_1280x800_60[UDL_MODE_SIZE] = { /* 83.46 MHz 59.9 MHz */ 207278799Shselasky 0x00, 0xb2, 0x19, 0x34, 0xdf, 0x93, 0x60, 0x30, 0xfb, 0x9f, 0xca, 0xff, 208278799Shselasky 0xff, 0x27, 0x32, 0x05, 0x00, 0x61, 0xf6, 0xff, 0xff, 0xff, 0xf9, 0x03, 209278799Shselasky 0x20, 0x04, 0x02, 0x34, 0x41 210278799Shselasky}; 211278799Shselaskystatic const uint8_t udl_reg_vals_1280x960_60[UDL_MODE_SIZE] = { /* 108.00 MHz 60.0 Hz 212278799Shselasky * VESA std */ 213278799Shselasky 0x00, 0xa6, 0x03, 0x5c, 0x7e, 0x0a, 0x95, 0x48, 0xf4, 0x61, 0xbd, 0xff, 214278799Shselasky 0xff, 0x94, 0x43, 0x05, 0x00, 0x91, 0xe8, 0xff, 0xff, 0xff, 0xf9, 0x03, 215278799Shselasky 0xc0, 0x04, 0x02, 0x60, 0x54 216278799Shselasky}; 217278799Shselaskystatic const uint8_t udl_reg_vals_1280x1024_60[UDL_MODE_SIZE] = { /* 108.00 MHz 60.0 Hz 218278799Shselasky * VESA std */ 219278799Shselasky 0x00, 0x98, 0xf8, 0x0d, 0x57, 0x2a, 0x55, 0x4d, 0x54, 0xca, 0x0d, 0xff, 220278799Shselasky 0xff, 0x94, 0x43, 0x05, 0x00, 0x9a, 0xa8, 0xff, 0xff, 0xff, 0xf9, 0x04, 221278799Shselasky 0x00, 0x04, 0x02, 0x60, 0x54 222278799Shselasky}; 223278799Shselaskystatic const uint8_t udl_reg_vals_1280x1024_75[UDL_MODE_SIZE] = { /* 135.00 MHz 75.0 Hz 224278799Shselasky * VESA std */ 225278799Shselasky 0x00, 0xce, 0x12, 0x3f, 0x9f, 0x2a, 0x55, 0x4d, 0x54, 0xca, 0x0d, 0xff, 226278799Shselasky 0xff, 0x32, 0x60, 0x05, 0x00, 0x9a, 0xa8, 0xff, 0xff, 0xff, 0xf9, 0x04, 227278799Shselasky 0x00, 0x04, 0x02, 0x78, 0x69 228278799Shselasky}; 229278799Shselaskystatic const uint8_t udl_reg_vals_1366x768_60[UDL_MODE_SIZE] = { /* 90 MHz 60.0 Hz */ 230278799Shselasky 0x01, 0x19, 0x1e, 0x1f, 0xb0, 0x93, 0x60, 0x40, 0x7b, 0x36, 0xe8, 0x27, 231278799Shselasky 0x32, 0xff, 0xff, 0x05, 0x56, 0x03, 0xd9, 0xff, 0xff, 0xfc, 0xa7, 0x03, 232278799Shselasky 0x00, 0x04, 0x02, 0x9a, 0x42 233278799Shselasky}; 234278799Shselaskystatic const uint8_t udl_reg_vals_1440x900_60[UDL_MODE_SIZE] = { /* 106.47 MHz 59.9 Hz */ 235278799Shselasky 0x00, 0x24, 0xce, 0xe7, 0x72, 0x36, 0x0a, 0x86, 0xca, 0x1c, 0x10, 0xff, 236278799Shselasky 0xff, 0x60, 0x3a, 0x05, 0xa0, 0x0d, 0x94, 0xff, 0xff, 0xff, 0xf9, 0x03, 237278799Shselasky 0x84, 0x04, 0x02, 0x2e, 0x53 238278799Shselasky}; 239278799Shselaskystatic const uint8_t udl_reg_vals_1440x900_59[UDL_MODE_SIZE] = { /* 106.50 MHz 59.8 Hz */ 240278799Shselasky 0x00, 0x24, 0xce, 0xe7, 0x72, 0xd8, 0x2a, 0x1b, 0x28, 0x1c, 0x10, 0xff, 241278799Shselasky 0xff, 0x60, 0x3a, 0x05, 0xa0, 0x36, 0x50, 0xff, 0xff, 0xff, 0xf9, 0x03, 242278799Shselasky 0x84, 0x04, 0x02, 0x34, 0x53 243278799Shselasky}; 244278799Shselaskystatic const uint8_t udl_reg_vals_1440x900_75[UDL_MODE_SIZE] = { /* 136.49 MHz 75.0 Hz */ 245278799Shselasky 0x00, 0x73, 0xa6, 0x14, 0xea, 0x0a, 0x95, 0xca, 0x10, 0x7f, 0x46, 0xff, 246278799Shselasky 0xff, 0x60, 0x3a, 0x05, 0xa0, 0x94, 0x20, 0xff, 0xff, 0xff, 0xf9, 0x03, 247278799Shselasky 0x84, 0x04, 0x02, 0xa2, 0x6a 248278799Shselasky}; 249278799Shselaskystatic const uint8_t udl_reg_vals_1680x1050_60[UDL_MODE_SIZE] = { /* 147.14 MHz 60.0 Hz */ 250278799Shselasky 0x00, 0x53, 0x43, 0xa6, 0x71, 0xc1, 0x52, 0xd9, 0x29, 0x69, 0x9f, 0xff, 251278799Shselasky 0xff, 0xd7, 0xee, 0x06, 0x90, 0xb2, 0x53, 0xff, 0xff, 0xff, 0xf9, 0x04, 252278799Shselasky 0x1a, 0x04, 0x02, 0xf4, 0x72 253278799Shselasky}; 254278799Shselaskystatic const uint8_t udl_reg_vals_1600x1200_60[UDL_MODE_SIZE] = { /* 162.00 MHz 60.0 Hz 255278799Shselasky * VESA std */ 256278799Shselasky 0x00, 0xcf, 0xa4, 0x3c, 0x4e, 0x55, 0x73, 0x71, 0x2b, 0x71, 0x52, 0xff, 257278799Shselasky 0xff, 0xee, 0xca, 0x06, 0x40, 0xe2, 0x57, 0xff, 0xff, 0xff, 0xf9, 0x04, 258278799Shselasky 0xb0, 0x04, 0x02, 0x90, 0x7e 259278799Shselasky}; 260278799Shselaskystatic const uint8_t udl_reg_vals_1920x1080_60[UDL_MODE_SIZE] = { /* 138.50 MHz 59.9 Hz */ 261278799Shselasky 0x00, 0x73, 0xa6, 0x28, 0xb3, 0x54, 0xaa, 0x41, 0x5d, 0x0d, 0x9f, 0x32, 262278799Shselasky 0x60, 0xff, 0xff, 0x07, 0x80, 0x0a, 0xea, 0xff, 0xf9, 0xff, 0xff, 0x04, 263278799Shselasky 0x38, 0x04, 0x02, 0xe0, 0x7c 264278799Shselasky}; 265278799Shselasky 266278799Shselaskystruct udl_mode { 267278799Shselasky uint16_t hdisplay; 268278799Shselasky uint16_t vdisplay; 269278799Shselasky uint8_t hz; 270278799Shselasky uint16_t chip; 271278799Shselasky uint32_t clock; 272278799Shselasky const uint8_t *mode; 273278799Shselasky}; 274278799Shselasky 275278799Shselaskystatic const struct udl_mode udl_modes[UDL_MAX_MODES] = { 276278799Shselasky {640, 480, 60, DLALL, 2520, udl_reg_vals_640x480_60}, 277278799Shselasky {640, 480, 67, DLALL, 3025, udl_reg_vals_640x480_67}, 278278799Shselasky {640, 480, 72, DLALL, 3150, udl_reg_vals_640x480_72}, 279278799Shselasky {640, 480, 75, DLALL, 3150, udl_reg_vals_640x480_75}, 280278799Shselasky {800, 480, 59, DLALL, 5000, udl_reg_vals_800x480_61}, 281278799Shselasky {800, 480, 61, DLALL, 3300, udl_reg_vals_800x480_61}, 282278799Shselasky {800, 600, 56, DLALL, 3600, udl_reg_vals_800x600_56}, 283278799Shselasky {800, 600, 60, DLALL, 4000, udl_reg_vals_800x600_60}, 284278799Shselasky {800, 600, 72, DLALL, 5000, udl_reg_vals_800x600_72}, 285278799Shselasky {800, 600, 74, DLALL, 5000, udl_reg_vals_800x600_74}, 286278799Shselasky {800, 600, 75, DLALL, 4950, udl_reg_vals_800x600_75}, 287278799Shselasky {1024, 768, 60, DLALL, 6500, udl_reg_vals_1024x768_60}, 288278799Shselasky {1024, 768, 70, DLALL, 7500, udl_reg_vals_1024x768_70}, 289278799Shselasky {1024, 768, 75, DLALL, 7850, udl_reg_vals_1024x768_75}, 290278799Shselasky {1280, 800, 60, DLALL, 8346, udl_reg_vals_1280x800_60}, 291278799Shselasky {1280, 960, 60, DLALL, 10800, udl_reg_vals_1280x960_60}, 292278799Shselasky {1280, 1024, 60, DLALL, 10800, udl_reg_vals_1280x1024_60}, 293278799Shselasky {1280, 1024, 75, DLALL, 13500, udl_reg_vals_1280x1024_75}, 294278799Shselasky {1366, 768, 60, DLALL, 9000, udl_reg_vals_1366x768_60}, 295278799Shselasky {1440, 900, 59, DL125, 10650, udl_reg_vals_1440x900_59}, 296278799Shselasky {1440, 900, 60, DL125, 10647, udl_reg_vals_1440x900_60}, 297278799Shselasky {1440, 900, 75, DL125, 13649, udl_reg_vals_1440x900_75}, 298278799Shselasky {1680, 1050, 60, DL160, 14714, udl_reg_vals_1680x1050_60}, 299278799Shselasky {1600, 1200, 60, DL160, 16200, udl_reg_vals_1600x1200_60}, 300278799Shselasky {1920, 1080, 60, DL165, 13850, udl_reg_vals_1920x1080_60} 301278799Shselasky}; 302278799Shselasky 303278799Shselasky/* 304278799Shselasky * Encryption. 305278799Shselasky */ 306278799Shselaskystatic const uint8_t udl_null_key_1[] = { 307278799Shselasky 0x57, 0xcd, 0xdc, 0xa7, 0x1c, 0x88, 0x5e, 0x15, 0x60, 0xfe, 0xc6, 0x97, 308278799Shselasky 0x16, 0x3d, 0x47, 0xf2 309278799Shselasky}; 310278799Shselasky 311278799Shselasky#endif /* _UDL_H_ */ 312