xhci.c revision 358874
1/* $FreeBSD: stable/11/sys/dev/usb/controller/xhci.c 358874 2020-03-11 08:21:04Z hselasky $ */ 2/*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36/* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43#ifdef USB_GLOBAL_INCLUDE_FILE 44#include USB_GLOBAL_INCLUDE_FILE 45#else 46#include <sys/stdint.h> 47#include <sys/stddef.h> 48#include <sys/param.h> 49#include <sys/queue.h> 50#include <sys/types.h> 51#include <sys/systm.h> 52#include <sys/kernel.h> 53#include <sys/bus.h> 54#include <sys/module.h> 55#include <sys/lock.h> 56#include <sys/mutex.h> 57#include <sys/condvar.h> 58#include <sys/sysctl.h> 59#include <sys/sx.h> 60#include <sys/unistd.h> 61#include <sys/callout.h> 62#include <sys/malloc.h> 63#include <sys/priv.h> 64 65#include <dev/usb/usb.h> 66#include <dev/usb/usbdi.h> 67 68#define USB_DEBUG_VAR xhcidebug 69 70#include <dev/usb/usb_core.h> 71#include <dev/usb/usb_debug.h> 72#include <dev/usb/usb_busdma.h> 73#include <dev/usb/usb_process.h> 74#include <dev/usb/usb_transfer.h> 75#include <dev/usb/usb_device.h> 76#include <dev/usb/usb_hub.h> 77#include <dev/usb/usb_util.h> 78 79#include <dev/usb/usb_controller.h> 80#include <dev/usb/usb_bus.h> 81#endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83#include <dev/usb/controller/xhci.h> 84#include <dev/usb/controller/xhcireg.h> 85 86#define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 92static int xhcistreams; 93SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN, 94 &xhcistreams, 0, "Set to enable streams mode support"); 95 96static int xhcictlquirk = 1; 97SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlquirk, CTLFLAG_RWTUN, 98 &xhcictlquirk, 0, "Set to enable control endpoint quirk"); 99 100#ifdef USB_DEBUG 101static int xhcidebug; 102static int xhciroute; 103static int xhcipolling; 104static int xhcidma32; 105static int xhcictlstep; 106 107SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN, 108 &xhcidebug, 0, "Debug level"); 109SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN, 110 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller"); 111SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN, 112 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller"); 113SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN, 114 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller"); 115SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN, 116 &xhcictlstep, 0, "Set to enable control endpoint status stage stepping"); 117#else 118#define xhciroute 0 119#define xhcidma32 0 120#define xhcictlstep 0 121#endif 122 123#define XHCI_INTR_ENDPT 1 124 125struct xhci_std_temp { 126 struct xhci_softc *sc; 127 struct usb_page_cache *pc; 128 struct xhci_td *td; 129 struct xhci_td *td_next; 130 uint32_t len; 131 uint32_t offset; 132 uint32_t max_packet_size; 133 uint32_t average; 134 uint16_t isoc_delta; 135 uint16_t isoc_frame; 136 uint8_t shortpkt; 137 uint8_t multishort; 138 uint8_t last_frame; 139 uint8_t trb_type; 140 uint8_t direction; 141 uint8_t tbc; 142 uint8_t tlbpc; 143 uint8_t step_td; 144 uint8_t do_isoc_sync; 145}; 146 147static void xhci_do_poll(struct usb_bus *); 148static void xhci_device_done(struct usb_xfer *, usb_error_t); 149static void xhci_root_intr(struct xhci_softc *); 150static void xhci_free_device_ext(struct usb_device *); 151static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 152 struct usb_endpoint_descriptor *); 153static usb_proc_callback_t xhci_configure_msg; 154static usb_error_t xhci_configure_device(struct usb_device *); 155static usb_error_t xhci_configure_endpoint(struct usb_device *, 156 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 157 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 158 uint8_t); 159static usb_error_t xhci_configure_mask(struct usb_device *, 160 uint32_t, uint8_t); 161static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 162 uint64_t, uint8_t); 163static void xhci_endpoint_doorbell(struct usb_xfer *); 164static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 165static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 166static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 167#ifdef USB_DEBUG 168static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 169#endif 170 171static const struct usb_bus_methods xhci_bus_methods; 172 173#ifdef USB_DEBUG 174static void 175xhci_dump_trb(struct xhci_trb *trb) 176{ 177 DPRINTFN(5, "trb = %p\n", trb); 178 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 179 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 180 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 181} 182 183static void 184xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 185{ 186 DPRINTFN(5, "pep = %p\n", pep); 187 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 188 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 189 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 190 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 191 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 192 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 193 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 194} 195 196static void 197xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 198{ 199 DPRINTFN(5, "psl = %p\n", psl); 200 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 201 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 202 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 203 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 204} 205#endif 206 207uint8_t 208xhci_use_polling(void) 209{ 210#ifdef USB_DEBUG 211 return (xhcipolling != 0); 212#else 213 return (0); 214#endif 215} 216 217static void 218xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 219{ 220 struct xhci_softc *sc = XHCI_BUS2SC(bus); 221 uint16_t i; 222 223 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 224 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 225 226 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 227 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 228 229 for (i = 0; i != sc->sc_noscratch; i++) { 230 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 231 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 232 } 233} 234 235static void 236xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 237{ 238 if (sc->sc_ctx_is_64_byte) { 239 uint32_t offset; 240 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 241 /* all contexts are initially 32-bytes */ 242 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 243 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 244 } 245 *ptr = htole32(val); 246} 247 248static uint32_t 249xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 250{ 251 if (sc->sc_ctx_is_64_byte) { 252 uint32_t offset; 253 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 254 /* all contexts are initially 32-bytes */ 255 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 256 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 257 } 258 return (le32toh(*ptr)); 259} 260 261static void 262xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 263{ 264 if (sc->sc_ctx_is_64_byte) { 265 uint32_t offset; 266 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 267 /* all contexts are initially 32-bytes */ 268 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 269 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 270 } 271 *ptr = htole64(val); 272} 273 274#ifdef USB_DEBUG 275static uint64_t 276xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 277{ 278 if (sc->sc_ctx_is_64_byte) { 279 uint32_t offset; 280 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 281 /* all contexts are initially 32-bytes */ 282 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 283 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 284 } 285 return (le64toh(*ptr)); 286} 287#endif 288 289static int 290xhci_reset_command_queue_locked(struct xhci_softc *sc) 291{ 292 struct usb_page_search buf_res; 293 struct xhci_hw_root *phwr; 294 uint64_t addr; 295 uint32_t temp; 296 297 DPRINTF("\n"); 298 299 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 300 if (temp & XHCI_CRCR_LO_CRR) { 301 DPRINTF("Command ring running\n"); 302 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 303 304 /* 305 * Try to abort the last command as per section 306 * 4.6.1.2 "Aborting a Command" of the XHCI 307 * specification: 308 */ 309 310 /* stop and cancel */ 311 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 312 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 313 314 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 315 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 316 317 /* wait 250ms */ 318 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 319 320 /* check if command ring is still running */ 321 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 322 if (temp & XHCI_CRCR_LO_CRR) { 323 DPRINTF("Comand ring still running\n"); 324 return (USB_ERR_IOERROR); 325 } 326 } 327 328 /* reset command ring */ 329 sc->sc_command_ccs = 1; 330 sc->sc_command_idx = 0; 331 332 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 333 334 /* set up command ring control base address */ 335 addr = buf_res.physaddr; 336 phwr = buf_res.buffer; 337 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 338 339 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 340 341 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 342 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 343 344 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 345 346 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 347 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 348 349 return (0); 350} 351 352usb_error_t 353xhci_start_controller(struct xhci_softc *sc) 354{ 355 struct usb_page_search buf_res; 356 struct xhci_hw_root *phwr; 357 struct xhci_dev_ctx_addr *pdctxa; 358 usb_error_t err; 359 uint64_t addr; 360 uint32_t temp; 361 uint16_t i; 362 363 DPRINTF("\n"); 364 365 sc->sc_event_ccs = 1; 366 sc->sc_event_idx = 0; 367 sc->sc_command_ccs = 1; 368 sc->sc_command_idx = 0; 369 370 err = xhci_reset_controller(sc); 371 if (err) 372 return (err); 373 374 /* set up number of device slots */ 375 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 376 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 377 378 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 379 380 temp = XREAD4(sc, oper, XHCI_USBSTS); 381 382 /* clear interrupts */ 383 XWRITE4(sc, oper, XHCI_USBSTS, temp); 384 /* disable all device notifications */ 385 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 386 387 /* set up device context base address */ 388 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 389 pdctxa = buf_res.buffer; 390 memset(pdctxa, 0, sizeof(*pdctxa)); 391 392 addr = buf_res.physaddr; 393 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 394 395 /* slot 0 points to the table of scratchpad pointers */ 396 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 397 398 for (i = 0; i != sc->sc_noscratch; i++) { 399 struct usb_page_search buf_scp; 400 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 401 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 402 } 403 404 addr = buf_res.physaddr; 405 406 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 407 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 408 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 409 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 410 411 /* set up event table size */ 412 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 413 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max); 414 415 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max)); 416 417 /* set up interrupt rate */ 418 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 419 420 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 421 422 phwr = buf_res.buffer; 423 addr = buf_res.physaddr; 424 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 425 426 /* reset hardware root structure */ 427 memset(phwr, 0, sizeof(*phwr)); 428 429 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 430 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 431 432 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 433 434 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 435 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 436 437 addr = buf_res.physaddr; 438 439 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 440 441 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 442 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 443 444 /* set up interrupter registers */ 445 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 446 temp |= XHCI_IMAN_INTR_ENA; 447 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 448 449 /* set up command ring control base address */ 450 addr = buf_res.physaddr; 451 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 452 453 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 454 455 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 456 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 457 458 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 459 460 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 461 462 /* Go! */ 463 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 464 XHCI_CMD_INTE | XHCI_CMD_HSEE); 465 466 for (i = 0; i != 100; i++) { 467 usb_pause_mtx(NULL, hz / 100); 468 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 469 if (!temp) 470 break; 471 } 472 if (temp) { 473 XWRITE4(sc, oper, XHCI_USBCMD, 0); 474 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 475 return (USB_ERR_IOERROR); 476 } 477 478 /* catch any lost interrupts */ 479 xhci_do_poll(&sc->sc_bus); 480 481 if (sc->sc_port_route != NULL) { 482 /* Route all ports to the XHCI by default */ 483 sc->sc_port_route(sc->sc_bus.parent, 484 ~xhciroute, xhciroute); 485 } 486 return (0); 487} 488 489usb_error_t 490xhci_halt_controller(struct xhci_softc *sc) 491{ 492 uint32_t temp; 493 uint16_t i; 494 495 DPRINTF("\n"); 496 497 sc->sc_capa_off = 0; 498 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 499 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 500 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 501 502 /* Halt controller */ 503 XWRITE4(sc, oper, XHCI_USBCMD, 0); 504 505 for (i = 0; i != 100; i++) { 506 usb_pause_mtx(NULL, hz / 100); 507 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 508 if (temp) 509 break; 510 } 511 512 if (!temp) { 513 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 514 return (USB_ERR_IOERROR); 515 } 516 return (0); 517} 518 519usb_error_t 520xhci_reset_controller(struct xhci_softc *sc) 521{ 522 uint32_t temp = 0; 523 uint16_t i; 524 525 DPRINTF("\n"); 526 527 /* Reset controller */ 528 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 529 530 for (i = 0; i != 100; i++) { 531 usb_pause_mtx(NULL, hz / 100); 532 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 533 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 534 if (!temp) 535 break; 536 } 537 538 if (temp) { 539 device_printf(sc->sc_bus.parent, "Controller " 540 "reset timeout.\n"); 541 return (USB_ERR_IOERROR); 542 } 543 return (0); 544} 545 546usb_error_t 547xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32) 548{ 549 uint32_t temp; 550 551 DPRINTF("\n"); 552 553 /* initialize some bus fields */ 554 sc->sc_bus.parent = self; 555 556 /* set the bus revision */ 557 sc->sc_bus.usbrev = USB_REV_3_0; 558 559 /* set up the bus struct */ 560 sc->sc_bus.methods = &xhci_bus_methods; 561 562 /* set up devices array */ 563 sc->sc_bus.devices = sc->sc_devices; 564 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 565 566 /* set default cycle state in case of early interrupts */ 567 sc->sc_event_ccs = 1; 568 sc->sc_command_ccs = 1; 569 570 /* set up bus space offsets */ 571 sc->sc_capa_off = 0; 572 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 573 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 574 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 575 576 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 577 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 578 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 579 580 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 581 582 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 583 device_printf(sc->sc_bus.parent, "Controller does " 584 "not support 4K page size.\n"); 585 return (ENXIO); 586 } 587 588 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 589 590 DPRINTF("HCS0 = 0x%08x\n", temp); 591 592 /* set up context size */ 593 if (XHCI_HCS0_CSZ(temp)) { 594 sc->sc_ctx_is_64_byte = 1; 595 } else { 596 sc->sc_ctx_is_64_byte = 0; 597 } 598 599 /* get DMA bits */ 600 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && 601 xhcidma32 == 0 && dma32 == 0) ? 64 : 32; 602 603 device_printf(self, "%d bytes context size, %d-bit DMA\n", 604 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); 605 606 /* enable 64Kbyte control endpoint quirk */ 607 sc->sc_bus.control_ep_quirk = (xhcictlquirk ? 1 : 0); 608 609 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 610 611 /* get number of device slots */ 612 sc->sc_noport = XHCI_HCS1_N_PORTS(temp); 613 614 if (sc->sc_noport == 0) { 615 device_printf(sc->sc_bus.parent, "Invalid number " 616 "of ports: %u\n", sc->sc_noport); 617 return (ENXIO); 618 } 619 620 sc->sc_noport = sc->sc_noport; 621 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 622 623 DPRINTF("Max slots: %u\n", sc->sc_noslot); 624 625 if (sc->sc_noslot > XHCI_MAX_DEVICES) 626 sc->sc_noslot = XHCI_MAX_DEVICES; 627 628 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 629 630 DPRINTF("HCS2=0x%08x\n", temp); 631 632 /* get number of scratchpads */ 633 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 634 635 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 636 device_printf(sc->sc_bus.parent, "XHCI request " 637 "too many scratchpads\n"); 638 return (ENOMEM); 639 } 640 641 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 642 643 /* get event table size */ 644 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); 645 if (sc->sc_erst_max > XHCI_MAX_RSEG) 646 sc->sc_erst_max = XHCI_MAX_RSEG; 647 648 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 649 650 /* get maximum exit latency */ 651 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 652 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 653 654 /* Check if we should use the default IMOD value. */ 655 if (sc->sc_imod_default == 0) 656 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 657 658 /* get all DMA memory */ 659 if (usb_bus_mem_alloc_all(&sc->sc_bus, 660 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 661 return (ENOMEM); 662 } 663 664 /* set up command queue mutex and condition varible */ 665 cv_init(&sc->sc_cmd_cv, "CMDQ"); 666 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 667 668 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 669 sc->sc_config_msg[0].bus = &sc->sc_bus; 670 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 671 sc->sc_config_msg[1].bus = &sc->sc_bus; 672 673 return (0); 674} 675 676void 677xhci_uninit(struct xhci_softc *sc) 678{ 679 /* 680 * NOTE: At this point the control transfer process is gone 681 * and "xhci_configure_msg" is no longer called. Consequently 682 * waiting for the configuration messages to complete is not 683 * needed. 684 */ 685 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 686 687 cv_destroy(&sc->sc_cmd_cv); 688 sx_destroy(&sc->sc_cmd_sx); 689} 690 691static void 692xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 693{ 694 struct xhci_softc *sc = XHCI_BUS2SC(bus); 695 696 switch (state) { 697 case USB_HW_POWER_SUSPEND: 698 DPRINTF("Stopping the XHCI\n"); 699 xhci_halt_controller(sc); 700 xhci_reset_controller(sc); 701 break; 702 case USB_HW_POWER_SHUTDOWN: 703 DPRINTF("Stopping the XHCI\n"); 704 xhci_halt_controller(sc); 705 xhci_reset_controller(sc); 706 break; 707 case USB_HW_POWER_RESUME: 708 DPRINTF("Starting the XHCI\n"); 709 xhci_start_controller(sc); 710 break; 711 default: 712 break; 713 } 714} 715 716static usb_error_t 717xhci_generic_done_sub(struct usb_xfer *xfer) 718{ 719 struct xhci_td *td; 720 struct xhci_td *td_alt_next; 721 uint32_t len; 722 uint8_t status; 723 724 td = xfer->td_transfer_cache; 725 td_alt_next = td->alt_next; 726 727 if (xfer->aframes != xfer->nframes) 728 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 729 730 while (1) { 731 732 usb_pc_cpu_invalidate(td->page_cache); 733 734 status = td->status; 735 len = td->remainder; 736 737 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 738 xfer, (unsigned int)xfer->aframes, 739 (unsigned int)xfer->nframes, 740 (unsigned int)len, (unsigned int)td->len, 741 (unsigned int)status); 742 743 /* 744 * Verify the status length and 745 * add the length to "frlengths[]": 746 */ 747 if (len > td->len) { 748 /* should not happen */ 749 DPRINTF("Invalid status length, " 750 "0x%04x/0x%04x bytes\n", len, td->len); 751 status = XHCI_TRB_ERROR_LENGTH; 752 } else if (xfer->aframes != xfer->nframes) { 753 xfer->frlengths[xfer->aframes] += td->len - len; 754 } 755 /* Check for last transfer */ 756 if (((void *)td) == xfer->td_transfer_last) { 757 td = NULL; 758 break; 759 } 760 /* Check for transfer error */ 761 if (status != XHCI_TRB_ERROR_SHORT_PKT && 762 status != XHCI_TRB_ERROR_SUCCESS) { 763 /* the transfer is finished */ 764 td = NULL; 765 break; 766 } 767 /* Check for short transfer */ 768 if (len > 0) { 769 if (xfer->flags_int.short_frames_ok || 770 xfer->flags_int.isochronous_xfr || 771 xfer->flags_int.control_xfr) { 772 /* follow alt next */ 773 td = td->alt_next; 774 } else { 775 /* the transfer is finished */ 776 td = NULL; 777 } 778 break; 779 } 780 td = td->obj_next; 781 782 if (td->alt_next != td_alt_next) { 783 /* this USB frame is complete */ 784 break; 785 } 786 } 787 788 /* update transfer cache */ 789 790 xfer->td_transfer_cache = td; 791 792 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 793 (status != XHCI_TRB_ERROR_SHORT_PKT && 794 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 795 USB_ERR_NORMAL_COMPLETION); 796} 797 798static void 799xhci_generic_done(struct usb_xfer *xfer) 800{ 801 usb_error_t err = 0; 802 803 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 804 xfer, xfer->endpoint); 805 806 /* reset scanner */ 807 808 xfer->td_transfer_cache = xfer->td_transfer_first; 809 810 if (xfer->flags_int.control_xfr) { 811 812 if (xfer->flags_int.control_hdr) 813 err = xhci_generic_done_sub(xfer); 814 815 xfer->aframes = 1; 816 817 if (xfer->td_transfer_cache == NULL) 818 goto done; 819 } 820 821 while (xfer->aframes != xfer->nframes) { 822 823 err = xhci_generic_done_sub(xfer); 824 xfer->aframes++; 825 826 if (xfer->td_transfer_cache == NULL) 827 goto done; 828 } 829 830 if (xfer->flags_int.control_xfr && 831 !xfer->flags_int.control_act) 832 err = xhci_generic_done_sub(xfer); 833done: 834 /* transfer is complete */ 835 xhci_device_done(xfer, err); 836} 837 838static void 839xhci_activate_transfer(struct usb_xfer *xfer) 840{ 841 struct xhci_td *td; 842 843 td = xfer->td_transfer_cache; 844 845 usb_pc_cpu_invalidate(td->page_cache); 846 847 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 848 849 /* activate the transfer */ 850 851 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 852 usb_pc_cpu_flush(td->page_cache); 853 854 xhci_endpoint_doorbell(xfer); 855 } 856} 857 858static void 859xhci_skip_transfer(struct usb_xfer *xfer) 860{ 861 struct xhci_td *td; 862 struct xhci_td *td_last; 863 864 td = xfer->td_transfer_cache; 865 td_last = xfer->td_transfer_last; 866 867 td = td->alt_next; 868 869 usb_pc_cpu_invalidate(td->page_cache); 870 871 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 872 873 usb_pc_cpu_invalidate(td_last->page_cache); 874 875 /* copy LINK TRB to current waiting location */ 876 877 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 878 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 879 usb_pc_cpu_flush(td->page_cache); 880 881 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 882 usb_pc_cpu_flush(td->page_cache); 883 884 xhci_endpoint_doorbell(xfer); 885 } 886} 887 888/*------------------------------------------------------------------------* 889 * xhci_check_transfer 890 *------------------------------------------------------------------------*/ 891static void 892xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 893{ 894 struct xhci_endpoint_ext *pepext; 895 int64_t offset; 896 uint64_t td_event; 897 uint32_t temp; 898 uint32_t remainder; 899 uint16_t stream_id = 0; 900 uint16_t i; 901 uint8_t status; 902 uint8_t halted; 903 uint8_t epno; 904 uint8_t index; 905 906 /* decode TRB */ 907 td_event = le64toh(trb->qwTrb0); 908 temp = le32toh(trb->dwTrb2); 909 910 remainder = XHCI_TRB_2_REM_GET(temp); 911 status = XHCI_TRB_2_ERROR_GET(temp); 912 913 temp = le32toh(trb->dwTrb3); 914 epno = XHCI_TRB_3_EP_GET(temp); 915 index = XHCI_TRB_3_SLOT_GET(temp); 916 917 /* check if error means halted */ 918 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 919 status != XHCI_TRB_ERROR_SUCCESS); 920 921 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 922 index, epno, remainder, status); 923 924 if (index > sc->sc_noslot) { 925 DPRINTF("Invalid slot.\n"); 926 return; 927 } 928 929 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 930 DPRINTF("Invalid endpoint.\n"); 931 return; 932 } 933 934 pepext = &sc->sc_hw.devs[index].endp[epno]; 935 936 /* try to find the USB transfer that generated the event */ 937 for (i = 0;; i++) { 938 struct usb_xfer *xfer; 939 struct xhci_td *td; 940 941 if (i == (XHCI_MAX_TRANSFERS - 1)) { 942 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS || 943 stream_id == (XHCI_MAX_STREAMS - 1)) 944 break; 945 stream_id++; 946 i = 0; 947 DPRINTFN(5, "stream_id=%u\n", stream_id); 948 } 949 950 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 951 if (xfer == NULL) 952 continue; 953 954 td = xfer->td_transfer_cache; 955 956 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 957 (long long)td_event, 958 (long long)td->td_self, 959 (long long)td->td_self + sizeof(td->td_trb)); 960 961 /* 962 * NOTE: Some XHCI implementations might not trigger 963 * an event on the last LINK TRB so we need to 964 * consider both the last and second last event 965 * address as conditions for a successful transfer. 966 * 967 * NOTE: We assume that the XHCI will only trigger one 968 * event per chain of TRBs. 969 */ 970 971 offset = td_event - td->td_self; 972 973 if (offset >= 0 && 974 offset < (int64_t)sizeof(td->td_trb)) { 975 976 usb_pc_cpu_invalidate(td->page_cache); 977 978 /* compute rest of remainder, if any */ 979 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 980 temp = le32toh(td->td_trb[i].dwTrb2); 981 remainder += XHCI_TRB_2_BYTES_GET(temp); 982 } 983 984 DPRINTFN(5, "New remainder: %u\n", remainder); 985 986 /* clear isochronous transfer errors */ 987 if (xfer->flags_int.isochronous_xfr) { 988 if (halted) { 989 halted = 0; 990 status = XHCI_TRB_ERROR_SUCCESS; 991 remainder = td->len; 992 } 993 } 994 995 /* "td->remainder" is verified later */ 996 td->remainder = remainder; 997 td->status = status; 998 999 usb_pc_cpu_flush(td->page_cache); 1000 1001 /* 1002 * 1) Last transfer descriptor makes the 1003 * transfer done 1004 */ 1005 if (((void *)td) == xfer->td_transfer_last) { 1006 DPRINTF("TD is last\n"); 1007 xhci_generic_done(xfer); 1008 break; 1009 } 1010 1011 /* 1012 * 2) Any kind of error makes the transfer 1013 * done 1014 */ 1015 if (halted) { 1016 DPRINTF("TD has I/O error\n"); 1017 xhci_generic_done(xfer); 1018 break; 1019 } 1020 1021 /* 1022 * 3) If there is no alternate next transfer, 1023 * a short packet also makes the transfer done 1024 */ 1025 if (td->remainder > 0) { 1026 if (td->alt_next == NULL) { 1027 DPRINTF( 1028 "short TD has no alternate next\n"); 1029 xhci_generic_done(xfer); 1030 break; 1031 } 1032 DPRINTF("TD has short pkt\n"); 1033 if (xfer->flags_int.short_frames_ok || 1034 xfer->flags_int.isochronous_xfr || 1035 xfer->flags_int.control_xfr) { 1036 /* follow the alt next */ 1037 xfer->td_transfer_cache = td->alt_next; 1038 xhci_activate_transfer(xfer); 1039 break; 1040 } 1041 xhci_skip_transfer(xfer); 1042 xhci_generic_done(xfer); 1043 break; 1044 } 1045 1046 /* 1047 * 4) Transfer complete - go to next TD 1048 */ 1049 DPRINTF("Following next TD\n"); 1050 xfer->td_transfer_cache = td->obj_next; 1051 xhci_activate_transfer(xfer); 1052 break; /* there should only be one match */ 1053 } 1054 } 1055} 1056 1057static int 1058xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1059{ 1060 if (sc->sc_cmd_addr == trb->qwTrb0) { 1061 DPRINTF("Received command event\n"); 1062 sc->sc_cmd_result[0] = trb->dwTrb2; 1063 sc->sc_cmd_result[1] = trb->dwTrb3; 1064 cv_signal(&sc->sc_cmd_cv); 1065 return (1); /* command match */ 1066 } 1067 return (0); 1068} 1069 1070static int 1071xhci_interrupt_poll(struct xhci_softc *sc) 1072{ 1073 struct usb_page_search buf_res; 1074 struct xhci_hw_root *phwr; 1075 uint64_t addr; 1076 uint32_t temp; 1077 int retval = 0; 1078 uint16_t i; 1079 uint8_t event; 1080 uint8_t j; 1081 uint8_t k; 1082 uint8_t t; 1083 1084 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1085 1086 phwr = buf_res.buffer; 1087 1088 /* Receive any events */ 1089 1090 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1091 1092 i = sc->sc_event_idx; 1093 j = sc->sc_event_ccs; 1094 t = 2; 1095 1096 while (1) { 1097 1098 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1099 1100 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1101 1102 if (j != k) 1103 break; 1104 1105 event = XHCI_TRB_3_TYPE_GET(temp); 1106 1107 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1108 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1109 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1110 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1111 1112 switch (event) { 1113 case XHCI_TRB_EVENT_TRANSFER: 1114 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1115 break; 1116 case XHCI_TRB_EVENT_CMD_COMPLETE: 1117 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1118 break; 1119 default: 1120 DPRINTF("Unhandled event = %u\n", event); 1121 break; 1122 } 1123 1124 i++; 1125 1126 if (i == XHCI_MAX_EVENTS) { 1127 i = 0; 1128 j ^= 1; 1129 1130 /* check for timeout */ 1131 if (!--t) 1132 break; 1133 } 1134 } 1135 1136 sc->sc_event_idx = i; 1137 sc->sc_event_ccs = j; 1138 1139 /* 1140 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1141 * latched. That means to activate the register we need to 1142 * write both the low and high double word of the 64-bit 1143 * register. 1144 */ 1145 1146 addr = buf_res.physaddr; 1147 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1148 1149 /* try to clear busy bit */ 1150 addr |= XHCI_ERDP_LO_BUSY; 1151 1152 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1153 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1154 1155 return (retval); 1156} 1157 1158static usb_error_t 1159xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1160 uint16_t timeout_ms) 1161{ 1162 struct usb_page_search buf_res; 1163 struct xhci_hw_root *phwr; 1164 uint64_t addr; 1165 uint32_t temp; 1166 uint8_t i; 1167 uint8_t j; 1168 uint8_t timeout = 0; 1169 int err; 1170 1171 XHCI_CMD_ASSERT_LOCKED(sc); 1172 1173 /* get hardware root structure */ 1174 1175 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1176 1177 phwr = buf_res.buffer; 1178 1179 /* Queue command */ 1180 1181 USB_BUS_LOCK(&sc->sc_bus); 1182retry: 1183 i = sc->sc_command_idx; 1184 j = sc->sc_command_ccs; 1185 1186 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1187 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1188 (long long)le64toh(trb->qwTrb0), 1189 (long)le32toh(trb->dwTrb2), 1190 (long)le32toh(trb->dwTrb3)); 1191 1192 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1193 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1194 1195 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1196 1197 temp = trb->dwTrb3; 1198 1199 if (j) 1200 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1201 else 1202 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1203 1204 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1205 1206 phwr->hwr_commands[i].dwTrb3 = temp; 1207 1208 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1209 1210 addr = buf_res.physaddr; 1211 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1212 1213 sc->sc_cmd_addr = htole64(addr); 1214 1215 i++; 1216 1217 if (i == (XHCI_MAX_COMMANDS - 1)) { 1218 1219 if (j) { 1220 temp = htole32(XHCI_TRB_3_TC_BIT | 1221 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1222 XHCI_TRB_3_CYCLE_BIT); 1223 } else { 1224 temp = htole32(XHCI_TRB_3_TC_BIT | 1225 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1226 } 1227 1228 phwr->hwr_commands[i].dwTrb3 = temp; 1229 1230 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1231 1232 i = 0; 1233 j ^= 1; 1234 } 1235 1236 sc->sc_command_idx = i; 1237 sc->sc_command_ccs = j; 1238 1239 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1240 1241 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1242 USB_MS_TO_TICKS(timeout_ms)); 1243 1244 /* 1245 * In some error cases event interrupts are not generated. 1246 * Poll one time to see if the command has completed. 1247 */ 1248 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1249 DPRINTF("Command was completed when polling\n"); 1250 err = 0; 1251 } 1252 if (err != 0) { 1253 DPRINTF("Command timeout!\n"); 1254 /* 1255 * After some weeks of continuous operation, it has 1256 * been observed that the ASMedia Technology, ASM1042 1257 * SuperSpeed USB Host Controller can suddenly stop 1258 * accepting commands via the command queue. Try to 1259 * first reset the command queue. If that fails do a 1260 * host controller reset. 1261 */ 1262 if (timeout == 0 && 1263 xhci_reset_command_queue_locked(sc) == 0) { 1264 temp = le32toh(trb->dwTrb3); 1265 1266 /* 1267 * Avoid infinite XHCI reset loops if the set 1268 * address command fails to respond due to a 1269 * non-enumerating device: 1270 */ 1271 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1272 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1273 DPRINTF("Set address timeout\n"); 1274 } else { 1275 timeout = 1; 1276 goto retry; 1277 } 1278 } else { 1279 DPRINTF("Controller reset!\n"); 1280 usb_bus_reset_async_locked(&sc->sc_bus); 1281 } 1282 err = USB_ERR_TIMEOUT; 1283 trb->dwTrb2 = 0; 1284 trb->dwTrb3 = 0; 1285 } else { 1286 temp = le32toh(sc->sc_cmd_result[0]); 1287 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1288 err = USB_ERR_IOERROR; 1289 1290 trb->dwTrb2 = sc->sc_cmd_result[0]; 1291 trb->dwTrb3 = sc->sc_cmd_result[1]; 1292 } 1293 1294 USB_BUS_UNLOCK(&sc->sc_bus); 1295 1296 return (err); 1297} 1298 1299#if 0 1300static usb_error_t 1301xhci_cmd_nop(struct xhci_softc *sc) 1302{ 1303 struct xhci_trb trb; 1304 uint32_t temp; 1305 1306 DPRINTF("\n"); 1307 1308 trb.qwTrb0 = 0; 1309 trb.dwTrb2 = 0; 1310 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1311 1312 trb.dwTrb3 = htole32(temp); 1313 1314 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1315} 1316#endif 1317 1318static usb_error_t 1319xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1320{ 1321 struct xhci_trb trb; 1322 uint32_t temp; 1323 usb_error_t err; 1324 1325 DPRINTF("\n"); 1326 1327 trb.qwTrb0 = 0; 1328 trb.dwTrb2 = 0; 1329 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1330 1331 err = xhci_do_command(sc, &trb, 100 /* ms */); 1332 if (err) 1333 goto done; 1334 1335 temp = le32toh(trb.dwTrb3); 1336 1337 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1338 1339done: 1340 return (err); 1341} 1342 1343static usb_error_t 1344xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1345{ 1346 struct xhci_trb trb; 1347 uint32_t temp; 1348 1349 DPRINTF("\n"); 1350 1351 trb.qwTrb0 = 0; 1352 trb.dwTrb2 = 0; 1353 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1354 XHCI_TRB_3_SLOT_SET(slot_id); 1355 1356 trb.dwTrb3 = htole32(temp); 1357 1358 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1359} 1360 1361static usb_error_t 1362xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1363 uint8_t bsr, uint8_t slot_id) 1364{ 1365 struct xhci_trb trb; 1366 uint32_t temp; 1367 1368 DPRINTF("\n"); 1369 1370 trb.qwTrb0 = htole64(input_ctx); 1371 trb.dwTrb2 = 0; 1372 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1373 XHCI_TRB_3_SLOT_SET(slot_id); 1374 1375 if (bsr) 1376 temp |= XHCI_TRB_3_BSR_BIT; 1377 1378 trb.dwTrb3 = htole32(temp); 1379 1380 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1381} 1382 1383static usb_error_t 1384xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1385{ 1386 struct usb_page_search buf_inp; 1387 struct usb_page_search buf_dev; 1388 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1389 struct xhci_hw_dev *hdev; 1390 struct xhci_dev_ctx *pdev; 1391 struct xhci_endpoint_ext *pepext; 1392 uint32_t temp; 1393 uint16_t mps; 1394 usb_error_t err; 1395 uint8_t index; 1396 1397 /* the root HUB case is not handled here */ 1398 if (udev->parent_hub == NULL) 1399 return (USB_ERR_INVAL); 1400 1401 index = udev->controller_slot_id; 1402 1403 hdev = &sc->sc_hw.devs[index]; 1404 1405 if (mtx != NULL) 1406 mtx_unlock(mtx); 1407 1408 XHCI_CMD_LOCK(sc); 1409 1410 switch (hdev->state) { 1411 case XHCI_ST_DEFAULT: 1412 case XHCI_ST_ENABLED: 1413 1414 hdev->state = XHCI_ST_ENABLED; 1415 1416 /* set configure mask to slot and EP0 */ 1417 xhci_configure_mask(udev, 3, 0); 1418 1419 /* configure input slot context structure */ 1420 err = xhci_configure_device(udev); 1421 1422 if (err != 0) { 1423 DPRINTF("Could not configure device\n"); 1424 break; 1425 } 1426 1427 /* configure input endpoint context structure */ 1428 switch (udev->speed) { 1429 case USB_SPEED_LOW: 1430 case USB_SPEED_FULL: 1431 mps = 8; 1432 break; 1433 case USB_SPEED_HIGH: 1434 mps = 64; 1435 break; 1436 default: 1437 mps = 512; 1438 break; 1439 } 1440 1441 pepext = xhci_get_endpoint_ext(udev, 1442 &udev->ctrl_ep_desc); 1443 1444 /* ensure the control endpoint is setup again */ 1445 USB_BUS_LOCK(udev->bus); 1446 pepext->trb_halted = 1; 1447 pepext->trb_running = 0; 1448 USB_BUS_UNLOCK(udev->bus); 1449 1450 err = xhci_configure_endpoint(udev, 1451 &udev->ctrl_ep_desc, pepext, 1452 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1453 1454 if (err != 0) { 1455 DPRINTF("Could not configure default endpoint\n"); 1456 break; 1457 } 1458 1459 /* execute set address command */ 1460 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1461 1462 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1463 (address == 0), index); 1464 1465 if (err != 0) { 1466 temp = le32toh(sc->sc_cmd_result[0]); 1467 if (address == 0 && sc->sc_port_route != NULL && 1468 XHCI_TRB_2_ERROR_GET(temp) == 1469 XHCI_TRB_ERROR_PARAMETER) { 1470 /* LynxPoint XHCI - ports are not switchable */ 1471 /* Un-route all ports from the XHCI */ 1472 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1473 } 1474 DPRINTF("Could not set address " 1475 "for slot %u.\n", index); 1476 if (address != 0) 1477 break; 1478 } 1479 1480 /* update device address to new value */ 1481 1482 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1483 pdev = buf_dev.buffer; 1484 usb_pc_cpu_invalidate(&hdev->device_pc); 1485 1486 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1487 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1488 1489 /* update device state to new value */ 1490 1491 if (address != 0) 1492 hdev->state = XHCI_ST_ADDRESSED; 1493 else 1494 hdev->state = XHCI_ST_DEFAULT; 1495 break; 1496 1497 default: 1498 DPRINTF("Wrong state for set address.\n"); 1499 err = USB_ERR_IOERROR; 1500 break; 1501 } 1502 XHCI_CMD_UNLOCK(sc); 1503 1504 if (mtx != NULL) 1505 mtx_lock(mtx); 1506 1507 return (err); 1508} 1509 1510static usb_error_t 1511xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1512 uint8_t deconfigure, uint8_t slot_id) 1513{ 1514 struct xhci_trb trb; 1515 uint32_t temp; 1516 1517 DPRINTF("\n"); 1518 1519 trb.qwTrb0 = htole64(input_ctx); 1520 trb.dwTrb2 = 0; 1521 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1522 XHCI_TRB_3_SLOT_SET(slot_id); 1523 1524 if (deconfigure) 1525 temp |= XHCI_TRB_3_DCEP_BIT; 1526 1527 trb.dwTrb3 = htole32(temp); 1528 1529 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1530} 1531 1532static usb_error_t 1533xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1534 uint8_t slot_id) 1535{ 1536 struct xhci_trb trb; 1537 uint32_t temp; 1538 1539 DPRINTF("\n"); 1540 1541 trb.qwTrb0 = htole64(input_ctx); 1542 trb.dwTrb2 = 0; 1543 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1544 XHCI_TRB_3_SLOT_SET(slot_id); 1545 trb.dwTrb3 = htole32(temp); 1546 1547 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1548} 1549 1550static usb_error_t 1551xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1552 uint8_t ep_id, uint8_t slot_id) 1553{ 1554 struct xhci_trb trb; 1555 uint32_t temp; 1556 1557 DPRINTF("\n"); 1558 1559 trb.qwTrb0 = 0; 1560 trb.dwTrb2 = 0; 1561 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1562 XHCI_TRB_3_SLOT_SET(slot_id) | 1563 XHCI_TRB_3_EP_SET(ep_id); 1564 1565 if (preserve) 1566 temp |= XHCI_TRB_3_PRSV_BIT; 1567 1568 trb.dwTrb3 = htole32(temp); 1569 1570 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1571} 1572 1573static usb_error_t 1574xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1575 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1576{ 1577 struct xhci_trb trb; 1578 uint32_t temp; 1579 1580 DPRINTF("\n"); 1581 1582 trb.qwTrb0 = htole64(dequeue_ptr); 1583 1584 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1585 trb.dwTrb2 = htole32(temp); 1586 1587 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1588 XHCI_TRB_3_SLOT_SET(slot_id) | 1589 XHCI_TRB_3_EP_SET(ep_id); 1590 trb.dwTrb3 = htole32(temp); 1591 1592 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1593} 1594 1595static usb_error_t 1596xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1597 uint8_t ep_id, uint8_t slot_id) 1598{ 1599 struct xhci_trb trb; 1600 uint32_t temp; 1601 1602 DPRINTF("\n"); 1603 1604 trb.qwTrb0 = 0; 1605 trb.dwTrb2 = 0; 1606 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1607 XHCI_TRB_3_SLOT_SET(slot_id) | 1608 XHCI_TRB_3_EP_SET(ep_id); 1609 1610 if (suspend) 1611 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1612 1613 trb.dwTrb3 = htole32(temp); 1614 1615 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1616} 1617 1618static usb_error_t 1619xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1620{ 1621 struct xhci_trb trb; 1622 uint32_t temp; 1623 1624 DPRINTF("\n"); 1625 1626 trb.qwTrb0 = 0; 1627 trb.dwTrb2 = 0; 1628 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1629 XHCI_TRB_3_SLOT_SET(slot_id); 1630 1631 trb.dwTrb3 = htole32(temp); 1632 1633 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1634} 1635 1636/*------------------------------------------------------------------------* 1637 * xhci_interrupt - XHCI interrupt handler 1638 *------------------------------------------------------------------------*/ 1639void 1640xhci_interrupt(struct xhci_softc *sc) 1641{ 1642 uint32_t status; 1643 uint32_t temp; 1644 1645 USB_BUS_LOCK(&sc->sc_bus); 1646 1647 status = XREAD4(sc, oper, XHCI_USBSTS); 1648 1649 /* acknowledge interrupts, if any */ 1650 if (status != 0) { 1651 XWRITE4(sc, oper, XHCI_USBSTS, status); 1652 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1653 } 1654 1655 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1656 1657 /* force clearing of pending interrupts */ 1658 if (temp & XHCI_IMAN_INTR_PEND) 1659 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1660 1661 /* check for event(s) */ 1662 xhci_interrupt_poll(sc); 1663 1664 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1665 XHCI_STS_HSE | XHCI_STS_HCE)) { 1666 1667 if (status & XHCI_STS_PCD) { 1668 xhci_root_intr(sc); 1669 } 1670 1671 if (status & XHCI_STS_HCH) { 1672 printf("%s: host controller halted\n", 1673 __FUNCTION__); 1674 } 1675 1676 if (status & XHCI_STS_HSE) { 1677 printf("%s: host system error\n", 1678 __FUNCTION__); 1679 } 1680 1681 if (status & XHCI_STS_HCE) { 1682 printf("%s: host controller error\n", 1683 __FUNCTION__); 1684 } 1685 } 1686 USB_BUS_UNLOCK(&sc->sc_bus); 1687} 1688 1689/*------------------------------------------------------------------------* 1690 * xhci_timeout - XHCI timeout handler 1691 *------------------------------------------------------------------------*/ 1692static void 1693xhci_timeout(void *arg) 1694{ 1695 struct usb_xfer *xfer = arg; 1696 1697 DPRINTF("xfer=%p\n", xfer); 1698 1699 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1700 1701 /* transfer is transferred */ 1702 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1703} 1704 1705static void 1706xhci_do_poll(struct usb_bus *bus) 1707{ 1708 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1709 1710 USB_BUS_LOCK(&sc->sc_bus); 1711 xhci_interrupt_poll(sc); 1712 USB_BUS_UNLOCK(&sc->sc_bus); 1713} 1714 1715static void 1716xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1717{ 1718 struct usb_page_search buf_res; 1719 struct xhci_td *td; 1720 struct xhci_td *td_next; 1721 struct xhci_td *td_alt_next; 1722 struct xhci_td *td_first; 1723 uint32_t buf_offset; 1724 uint32_t average; 1725 uint32_t len_old; 1726 uint32_t npkt_off; 1727 uint32_t dword; 1728 uint8_t shortpkt_old; 1729 uint8_t precompute; 1730 uint8_t x; 1731 1732 td_alt_next = NULL; 1733 buf_offset = 0; 1734 shortpkt_old = temp->shortpkt; 1735 len_old = temp->len; 1736 npkt_off = 0; 1737 precompute = 1; 1738 1739restart: 1740 1741 td = temp->td; 1742 td_next = td_first = temp->td_next; 1743 1744 while (1) { 1745 1746 if (temp->len == 0) { 1747 1748 if (temp->shortpkt) 1749 break; 1750 1751 /* send a Zero Length Packet, ZLP, last */ 1752 1753 temp->shortpkt = 1; 1754 average = 0; 1755 1756 } else { 1757 1758 average = temp->average; 1759 1760 if (temp->len < average) { 1761 if (temp->len % temp->max_packet_size) { 1762 temp->shortpkt = 1; 1763 } 1764 average = temp->len; 1765 } 1766 } 1767 1768 if (td_next == NULL) 1769 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1770 1771 /* get next TD */ 1772 1773 td = td_next; 1774 td_next = td->obj_next; 1775 1776 /* check if we are pre-computing */ 1777 1778 if (precompute) { 1779 1780 /* update remaining length */ 1781 1782 temp->len -= average; 1783 1784 continue; 1785 } 1786 /* fill out current TD */ 1787 1788 td->len = average; 1789 td->remainder = 0; 1790 td->status = 0; 1791 1792 /* update remaining length */ 1793 1794 temp->len -= average; 1795 1796 /* reset TRB index */ 1797 1798 x = 0; 1799 1800 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1801 /* immediate data */ 1802 1803 if (average > 8) 1804 average = 8; 1805 1806 td->td_trb[0].qwTrb0 = 0; 1807 1808 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1809 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1810 average); 1811 1812 dword = XHCI_TRB_2_BYTES_SET(8) | 1813 XHCI_TRB_2_TDSZ_SET(0) | 1814 XHCI_TRB_2_IRQ_SET(0); 1815 1816 td->td_trb[0].dwTrb2 = htole32(dword); 1817 1818 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1819 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1820 1821 /* check wLength */ 1822 if (td->td_trb[0].qwTrb0 & 1823 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1824 if (td->td_trb[0].qwTrb0 & 1825 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1826 dword |= XHCI_TRB_3_TRT_IN; 1827 else 1828 dword |= XHCI_TRB_3_TRT_OUT; 1829 } 1830 1831 td->td_trb[0].dwTrb3 = htole32(dword); 1832#ifdef USB_DEBUG 1833 xhci_dump_trb(&td->td_trb[x]); 1834#endif 1835 x++; 1836 1837 } else do { 1838 1839 uint32_t npkt; 1840 1841 /* fill out buffer pointers */ 1842 1843 if (average == 0) { 1844 memset(&buf_res, 0, sizeof(buf_res)); 1845 } else { 1846 usbd_get_page(temp->pc, temp->offset + 1847 buf_offset, &buf_res); 1848 1849 /* get length to end of page */ 1850 if (buf_res.length > average) 1851 buf_res.length = average; 1852 1853 /* check for maximum length */ 1854 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1855 buf_res.length = XHCI_TD_PAGE_SIZE; 1856 1857 npkt_off += buf_res.length; 1858 } 1859 1860 /* set up npkt */ 1861 npkt = howmany(len_old - npkt_off, 1862 temp->max_packet_size); 1863 1864 if (npkt == 0) 1865 npkt = 1; 1866 else if (npkt > 31) 1867 npkt = 31; 1868 1869 /* fill out TRB's */ 1870 td->td_trb[x].qwTrb0 = 1871 htole64((uint64_t)buf_res.physaddr); 1872 1873 dword = 1874 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1875 XHCI_TRB_2_TDSZ_SET(npkt) | 1876 XHCI_TRB_2_IRQ_SET(0); 1877 1878 td->td_trb[x].dwTrb2 = htole32(dword); 1879 1880 switch (temp->trb_type) { 1881 case XHCI_TRB_TYPE_ISOCH: 1882 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1883 XHCI_TRB_3_TBC_SET(temp->tbc) | 1884 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1885 if (td != td_first) { 1886 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1887 } else if (temp->do_isoc_sync != 0) { 1888 temp->do_isoc_sync = 0; 1889 /* wait until "isoc_frame" */ 1890 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1891 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1892 } else { 1893 /* start data transfer at next interval */ 1894 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1895 XHCI_TRB_3_ISO_SIA_BIT; 1896 } 1897 if (temp->direction == UE_DIR_IN) 1898 dword |= XHCI_TRB_3_ISP_BIT; 1899 break; 1900 case XHCI_TRB_TYPE_DATA_STAGE: 1901 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1902 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1903 if (temp->direction == UE_DIR_IN) 1904 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1905 /* 1906 * Section 3.2.9 in the XHCI 1907 * specification about control 1908 * transfers says that we should use a 1909 * normal-TRB if there are more TRBs 1910 * extending the data-stage 1911 * TRB. Update the "trb_type". 1912 */ 1913 temp->trb_type = XHCI_TRB_TYPE_NORMAL; 1914 break; 1915 case XHCI_TRB_TYPE_STATUS_STAGE: 1916 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1917 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1918 if (temp->direction == UE_DIR_IN) 1919 dword |= XHCI_TRB_3_DIR_IN; 1920 break; 1921 default: /* XHCI_TRB_TYPE_NORMAL */ 1922 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1923 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1924 if (temp->direction == UE_DIR_IN) 1925 dword |= XHCI_TRB_3_ISP_BIT; 1926 break; 1927 } 1928 td->td_trb[x].dwTrb3 = htole32(dword); 1929 1930 average -= buf_res.length; 1931 buf_offset += buf_res.length; 1932#ifdef USB_DEBUG 1933 xhci_dump_trb(&td->td_trb[x]); 1934#endif 1935 x++; 1936 1937 } while (average != 0); 1938 1939 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1940 1941 /* store number of data TRB's */ 1942 1943 td->ntrb = x; 1944 1945 DPRINTF("NTRB=%u\n", x); 1946 1947 /* fill out link TRB */ 1948 1949 if (td_next != NULL) { 1950 /* link the current TD with the next one */ 1951 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1952 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1953 } else { 1954 /* this field will get updated later */ 1955 DPRINTF("NOLINK\n"); 1956 } 1957 1958 dword = XHCI_TRB_2_IRQ_SET(0); 1959 1960 td->td_trb[x].dwTrb2 = htole32(dword); 1961 1962 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1963 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1964 /* 1965 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1966 * frame only receives a single short packet event 1967 * by setting the CHAIN bit in the LINK field. In 1968 * addition some XHCI controllers have problems 1969 * sending a ZLP unless the CHAIN-BIT is set in 1970 * the LINK TRB. 1971 */ 1972 XHCI_TRB_3_CHAIN_BIT; 1973 1974 td->td_trb[x].dwTrb3 = htole32(dword); 1975 1976 td->alt_next = td_alt_next; 1977#ifdef USB_DEBUG 1978 xhci_dump_trb(&td->td_trb[x]); 1979#endif 1980 usb_pc_cpu_flush(td->page_cache); 1981 } 1982 1983 if (precompute) { 1984 precompute = 0; 1985 1986 /* set up alt next pointer, if any */ 1987 if (temp->last_frame) { 1988 td_alt_next = NULL; 1989 } else { 1990 /* we use this field internally */ 1991 td_alt_next = td_next; 1992 } 1993 1994 /* restore */ 1995 temp->shortpkt = shortpkt_old; 1996 temp->len = len_old; 1997 goto restart; 1998 } 1999 2000 /* 2001 * Remove cycle bit from the first TRB if we are 2002 * stepping them: 2003 */ 2004 if (temp->step_td != 0) { 2005 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2006 usb_pc_cpu_flush(td_first->page_cache); 2007 } 2008 2009 /* clear TD SIZE to zero, hence this is the last TRB */ 2010 /* remove chain bit because this is the last data TRB in the chain */ 2011 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31)); 2012 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 2013 /* remove CHAIN-BIT from last LINK TRB */ 2014 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 2015 2016 usb_pc_cpu_flush(td->page_cache); 2017 2018 temp->td = td; 2019 temp->td_next = td_next; 2020} 2021 2022static void 2023xhci_setup_generic_chain(struct usb_xfer *xfer) 2024{ 2025 struct xhci_std_temp temp; 2026 struct xhci_td *td; 2027 uint32_t x; 2028 uint32_t y; 2029 uint8_t mult; 2030 2031 temp.do_isoc_sync = 0; 2032 temp.step_td = 0; 2033 temp.tbc = 0; 2034 temp.tlbpc = 0; 2035 temp.average = xfer->max_hc_frame_size; 2036 temp.max_packet_size = xfer->max_packet_size; 2037 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 2038 temp.pc = NULL; 2039 temp.last_frame = 0; 2040 temp.offset = 0; 2041 temp.multishort = xfer->flags_int.isochronous_xfr || 2042 xfer->flags_int.control_xfr || 2043 xfer->flags_int.short_frames_ok; 2044 2045 /* toggle the DMA set we are using */ 2046 xfer->flags_int.curr_dma_set ^= 1; 2047 2048 /* get next DMA set */ 2049 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2050 2051 temp.td = NULL; 2052 temp.td_next = td; 2053 2054 xfer->td_transfer_first = td; 2055 xfer->td_transfer_cache = td; 2056 2057 if (xfer->flags_int.isochronous_xfr) { 2058 uint8_t shift; 2059 2060 /* compute multiplier for ISOCHRONOUS transfers */ 2061 mult = xfer->endpoint->ecomp ? 2062 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2063 : 0; 2064 /* check for USB 2.0 multiplier */ 2065 if (mult == 0) { 2066 mult = (xfer->endpoint->edesc-> 2067 wMaxPacketSize[1] >> 3) & 3; 2068 } 2069 /* range check */ 2070 if (mult > 2) 2071 mult = 3; 2072 else 2073 mult++; 2074 2075 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2076 2077 DPRINTF("MFINDEX=0x%08x\n", x); 2078 2079 switch (usbd_get_speed(xfer->xroot->udev)) { 2080 case USB_SPEED_FULL: 2081 shift = 3; 2082 temp.isoc_delta = 8; /* 1ms */ 2083 x += temp.isoc_delta - 1; 2084 x &= ~(temp.isoc_delta - 1); 2085 break; 2086 default: 2087 shift = usbd_xfer_get_fps_shift(xfer); 2088 temp.isoc_delta = 1U << shift; 2089 x += temp.isoc_delta - 1; 2090 x &= ~(temp.isoc_delta - 1); 2091 /* simple frame load balancing */ 2092 x += xfer->endpoint->usb_uframe; 2093 break; 2094 } 2095 2096 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2097 2098 if ((xfer->endpoint->is_synced == 0) || 2099 (y < (xfer->nframes << shift)) || 2100 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2101 /* 2102 * If there is data underflow or the pipe 2103 * queue is empty we schedule the transfer a 2104 * few frames ahead of the current frame 2105 * position. Else two isochronous transfers 2106 * might overlap. 2107 */ 2108 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2109 xfer->endpoint->is_synced = 1; 2110 temp.do_isoc_sync = 1; 2111 2112 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2113 } 2114 2115 /* compute isochronous completion time */ 2116 2117 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2118 2119 xfer->isoc_time_complete = 2120 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2121 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2122 2123 x = 0; 2124 temp.isoc_frame = xfer->endpoint->isoc_next; 2125 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2126 2127 xfer->endpoint->isoc_next += xfer->nframes << shift; 2128 2129 } else if (xfer->flags_int.control_xfr) { 2130 2131 /* check if we should prepend a setup message */ 2132 2133 if (xfer->flags_int.control_hdr) { 2134 2135 temp.len = xfer->frlengths[0]; 2136 temp.pc = xfer->frbuffers + 0; 2137 temp.shortpkt = temp.len ? 1 : 0; 2138 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2139 temp.direction = 0; 2140 2141 /* check for last frame */ 2142 if (xfer->nframes == 1) { 2143 /* no STATUS stage yet, SETUP is last */ 2144 if (xfer->flags_int.control_act) 2145 temp.last_frame = 1; 2146 } 2147 2148 xhci_setup_generic_chain_sub(&temp); 2149 } 2150 x = 1; 2151 mult = 1; 2152 temp.isoc_delta = 0; 2153 temp.isoc_frame = 0; 2154 temp.trb_type = xfer->flags_int.control_did_data ? 2155 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE; 2156 } else { 2157 x = 0; 2158 mult = 1; 2159 temp.isoc_delta = 0; 2160 temp.isoc_frame = 0; 2161 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2162 } 2163 2164 if (x != xfer->nframes) { 2165 /* set up page_cache pointer */ 2166 temp.pc = xfer->frbuffers + x; 2167 /* set endpoint direction */ 2168 temp.direction = UE_GET_DIR(xfer->endpointno); 2169 } 2170 2171 while (x != xfer->nframes) { 2172 2173 /* DATA0 / DATA1 message */ 2174 2175 temp.len = xfer->frlengths[x]; 2176 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2177 x != 0 && temp.multishort == 0); 2178 2179 x++; 2180 2181 if (x == xfer->nframes) { 2182 if (xfer->flags_int.control_xfr) { 2183 /* no STATUS stage yet, DATA is last */ 2184 if (xfer->flags_int.control_act) 2185 temp.last_frame = 1; 2186 } else { 2187 temp.last_frame = 1; 2188 } 2189 } 2190 if (temp.len == 0) { 2191 2192 /* make sure that we send an USB packet */ 2193 2194 temp.shortpkt = 0; 2195 2196 temp.tbc = 0; 2197 temp.tlbpc = mult - 1; 2198 2199 } else if (xfer->flags_int.isochronous_xfr) { 2200 2201 uint8_t tdpc; 2202 2203 /* 2204 * Isochronous transfers don't have short 2205 * packet termination: 2206 */ 2207 2208 temp.shortpkt = 1; 2209 2210 /* isochronous transfers have a transfer limit */ 2211 2212 if (temp.len > xfer->max_frame_size) 2213 temp.len = xfer->max_frame_size; 2214 2215 /* compute TD packet count */ 2216 tdpc = howmany(temp.len, xfer->max_packet_size); 2217 2218 temp.tbc = howmany(tdpc, mult) - 1; 2219 temp.tlbpc = (tdpc % mult); 2220 2221 if (temp.tlbpc == 0) 2222 temp.tlbpc = mult - 1; 2223 else 2224 temp.tlbpc--; 2225 } else { 2226 2227 /* regular data transfer */ 2228 2229 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2230 } 2231 2232 xhci_setup_generic_chain_sub(&temp); 2233 2234 if (xfer->flags_int.isochronous_xfr) { 2235 temp.offset += xfer->frlengths[x - 1]; 2236 temp.isoc_frame += temp.isoc_delta; 2237 } else { 2238 /* get next Page Cache pointer */ 2239 temp.pc = xfer->frbuffers + x; 2240 } 2241 } 2242 2243 /* check if we should append a status stage */ 2244 2245 if (xfer->flags_int.control_xfr && 2246 !xfer->flags_int.control_act) { 2247 2248 /* 2249 * Send a DATA1 message and invert the current 2250 * endpoint direction. 2251 */ 2252 if (xhcictlstep || temp.sc->sc_ctlstep) { 2253 /* 2254 * Some XHCI controllers will not delay the 2255 * status stage until the next SOF. Force this 2256 * behaviour to avoid failed control 2257 * transfers. 2258 */ 2259 temp.step_td = (xfer->nframes != 0); 2260 } else { 2261 temp.step_td = 0; 2262 } 2263 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2264 temp.len = 0; 2265 temp.pc = NULL; 2266 temp.shortpkt = 0; 2267 temp.last_frame = 1; 2268 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2269 2270 xhci_setup_generic_chain_sub(&temp); 2271 } 2272 2273 td = temp.td; 2274 2275 /* must have at least one frame! */ 2276 2277 xfer->td_transfer_last = td; 2278 2279 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2280} 2281 2282static void 2283xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2284{ 2285 struct usb_page_search buf_res; 2286 struct xhci_dev_ctx_addr *pdctxa; 2287 2288 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2289 2290 pdctxa = buf_res.buffer; 2291 2292 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2293 2294 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2295 2296 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2297} 2298 2299static usb_error_t 2300xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2301{ 2302 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2303 struct usb_page_search buf_inp; 2304 struct xhci_input_dev_ctx *pinp; 2305 uint32_t temp; 2306 uint8_t index; 2307 uint8_t x; 2308 2309 index = udev->controller_slot_id; 2310 2311 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2312 2313 pinp = buf_inp.buffer; 2314 2315 if (drop) { 2316 mask &= XHCI_INCTX_NON_CTRL_MASK; 2317 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2318 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2319 } else { 2320 /* 2321 * Some hardware requires that we drop the endpoint 2322 * context before adding it again: 2323 */ 2324 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 2325 mask & XHCI_INCTX_NON_CTRL_MASK); 2326 2327 /* Add new endpoint context */ 2328 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2329 2330 /* find most significant set bit */ 2331 for (x = 31; x != 1; x--) { 2332 if (mask & (1 << x)) 2333 break; 2334 } 2335 2336 /* adjust */ 2337 x--; 2338 2339 /* figure out the maximum number of contexts */ 2340 if (x > sc->sc_hw.devs[index].context_num) 2341 sc->sc_hw.devs[index].context_num = x; 2342 else 2343 x = sc->sc_hw.devs[index].context_num; 2344 2345 /* update number of contexts */ 2346 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2347 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2348 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2349 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2350 } 2351 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2352 return (0); 2353} 2354 2355static usb_error_t 2356xhci_configure_endpoint(struct usb_device *udev, 2357 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2358 uint16_t interval, uint8_t max_packet_count, 2359 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2360 uint16_t max_frame_size, uint8_t ep_mode) 2361{ 2362 struct usb_page_search buf_inp; 2363 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2364 struct xhci_input_dev_ctx *pinp; 2365 uint64_t ring_addr = pepext->physaddr; 2366 uint32_t temp; 2367 uint8_t index; 2368 uint8_t epno; 2369 uint8_t type; 2370 2371 index = udev->controller_slot_id; 2372 2373 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2374 2375 pinp = buf_inp.buffer; 2376 2377 epno = edesc->bEndpointAddress; 2378 type = edesc->bmAttributes & UE_XFERTYPE; 2379 2380 if (type == UE_CONTROL) 2381 epno |= UE_DIR_IN; 2382 2383 epno = XHCI_EPNO2EPID(epno); 2384 2385 if (epno == 0) 2386 return (USB_ERR_NO_PIPE); /* invalid */ 2387 2388 if (max_packet_count == 0) 2389 return (USB_ERR_BAD_BUFSIZE); 2390 2391 max_packet_count--; 2392 2393 if (mult == 0) 2394 return (USB_ERR_BAD_BUFSIZE); 2395 2396 /* store endpoint mode */ 2397 pepext->trb_ep_mode = ep_mode; 2398 /* store bMaxPacketSize for control endpoints */ 2399 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0]; 2400 usb_pc_cpu_flush(pepext->page_cache); 2401 2402 if (ep_mode == USB_EP_MODE_STREAMS) { 2403 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2404 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2405 XHCI_EPCTX_0_LSA_SET(1); 2406 2407 ring_addr += sizeof(struct xhci_trb) * 2408 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2409 } else { 2410 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2411 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2412 XHCI_EPCTX_0_LSA_SET(0); 2413 2414 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2415 } 2416 2417 switch (udev->speed) { 2418 case USB_SPEED_FULL: 2419 case USB_SPEED_LOW: 2420 /* 1ms -> 125us */ 2421 fps_shift += 3; 2422 break; 2423 default: 2424 break; 2425 } 2426 2427 switch (type) { 2428 case UE_INTERRUPT: 2429 if (fps_shift > 3) 2430 fps_shift--; 2431 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2432 break; 2433 case UE_ISOCHRONOUS: 2434 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2435 2436 switch (udev->speed) { 2437 case USB_SPEED_SUPER: 2438 if (mult > 3) 2439 mult = 3; 2440 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2441 max_packet_count /= mult; 2442 break; 2443 default: 2444 break; 2445 } 2446 break; 2447 default: 2448 break; 2449 } 2450 2451 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2452 2453 temp = 2454 XHCI_EPCTX_1_HID_SET(0) | 2455 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2456 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2457 2458 /* 2459 * Always enable the "three strikes and you are gone" feature 2460 * except for ISOCHRONOUS endpoints. This is suggested by 2461 * section 4.3.3 in the XHCI specification about device slot 2462 * initialisation. 2463 */ 2464 if (type != UE_ISOCHRONOUS) 2465 temp |= XHCI_EPCTX_1_CERR_SET(3); 2466 2467 switch (type) { 2468 case UE_CONTROL: 2469 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2470 break; 2471 case UE_ISOCHRONOUS: 2472 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2473 break; 2474 case UE_BULK: 2475 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2476 break; 2477 default: 2478 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2479 break; 2480 } 2481 2482 /* check for IN direction */ 2483 if (epno & 1) 2484 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2485 2486 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2487 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2488 2489 switch (edesc->bmAttributes & UE_XFERTYPE) { 2490 case UE_INTERRUPT: 2491 case UE_ISOCHRONOUS: 2492 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2493 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2494 max_frame_size)); 2495 break; 2496 case UE_CONTROL: 2497 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2498 break; 2499 default: 2500 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2501 break; 2502 } 2503 2504 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2505 2506#ifdef USB_DEBUG 2507 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2508#endif 2509 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2510 2511 return (0); /* success */ 2512} 2513 2514static usb_error_t 2515xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2516{ 2517 struct xhci_endpoint_ext *pepext; 2518 struct usb_endpoint_ss_comp_descriptor *ecomp; 2519 usb_stream_t x; 2520 2521 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2522 xfer->endpoint->edesc); 2523 2524 ecomp = xfer->endpoint->ecomp; 2525 2526 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2527 uint64_t temp; 2528 2529 /* halt any transfers */ 2530 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2531 2532 /* compute start of TRB ring for stream "x" */ 2533 temp = pepext->physaddr + 2534 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2535 XHCI_SCTX_0_SCT_SEC_TR_RING; 2536 2537 /* make tree structure */ 2538 pepext->trb[(XHCI_MAX_TRANSFERS * 2539 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2540 2541 /* reserved fields */ 2542 pepext->trb[(XHCI_MAX_TRANSFERS * 2543 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2544 pepext->trb[(XHCI_MAX_TRANSFERS * 2545 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2546 } 2547 usb_pc_cpu_flush(pepext->page_cache); 2548 2549 return (xhci_configure_endpoint(xfer->xroot->udev, 2550 xfer->endpoint->edesc, pepext, 2551 xfer->interval, xfer->max_packet_count, 2552 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2553 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2554 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2555} 2556 2557static usb_error_t 2558xhci_configure_device(struct usb_device *udev) 2559{ 2560 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2561 struct usb_page_search buf_inp; 2562 struct usb_page_cache *pcinp; 2563 struct xhci_input_dev_ctx *pinp; 2564 struct usb_device *hubdev; 2565 uint32_t temp; 2566 uint32_t route; 2567 uint32_t rh_port; 2568 uint8_t is_hub; 2569 uint8_t index; 2570 uint8_t depth; 2571 2572 index = udev->controller_slot_id; 2573 2574 DPRINTF("index=%u\n", index); 2575 2576 pcinp = &sc->sc_hw.devs[index].input_pc; 2577 2578 usbd_get_page(pcinp, 0, &buf_inp); 2579 2580 pinp = buf_inp.buffer; 2581 2582 rh_port = 0; 2583 route = 0; 2584 2585 /* figure out route string and root HUB port number */ 2586 2587 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2588 2589 if (hubdev->parent_hub == NULL) 2590 break; 2591 2592 depth = hubdev->parent_hub->depth; 2593 2594 /* 2595 * NOTE: HS/FS/LS devices and the SS root HUB can have 2596 * more than 15 ports 2597 */ 2598 2599 rh_port = hubdev->port_no; 2600 2601 if (depth == 0) 2602 break; 2603 2604 if (rh_port > 15) 2605 rh_port = 15; 2606 2607 if (depth < 6) 2608 route |= rh_port << (4 * (depth - 1)); 2609 } 2610 2611 DPRINTF("Route=0x%08x\n", route); 2612 2613 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2614 XHCI_SCTX_0_CTX_NUM_SET( 2615 sc->sc_hw.devs[index].context_num + 1); 2616 2617 switch (udev->speed) { 2618 case USB_SPEED_LOW: 2619 temp |= XHCI_SCTX_0_SPEED_SET(2); 2620 if (udev->parent_hs_hub != NULL && 2621 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2622 UDPROTO_HSHUBMTT) { 2623 DPRINTF("Device inherits MTT\n"); 2624 temp |= XHCI_SCTX_0_MTT_SET(1); 2625 } 2626 break; 2627 case USB_SPEED_HIGH: 2628 temp |= XHCI_SCTX_0_SPEED_SET(3); 2629 if (sc->sc_hw.devs[index].nports != 0 && 2630 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2631 DPRINTF("HUB supports MTT\n"); 2632 temp |= XHCI_SCTX_0_MTT_SET(1); 2633 } 2634 break; 2635 case USB_SPEED_FULL: 2636 temp |= XHCI_SCTX_0_SPEED_SET(1); 2637 if (udev->parent_hs_hub != NULL && 2638 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2639 UDPROTO_HSHUBMTT) { 2640 DPRINTF("Device inherits MTT\n"); 2641 temp |= XHCI_SCTX_0_MTT_SET(1); 2642 } 2643 break; 2644 default: 2645 temp |= XHCI_SCTX_0_SPEED_SET(4); 2646 break; 2647 } 2648 2649 is_hub = sc->sc_hw.devs[index].nports != 0 && 2650 (udev->speed == USB_SPEED_SUPER || 2651 udev->speed == USB_SPEED_HIGH); 2652 2653 if (is_hub) 2654 temp |= XHCI_SCTX_0_HUB_SET(1); 2655 2656 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2657 2658 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2659 2660 if (is_hub) { 2661 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2662 sc->sc_hw.devs[index].nports); 2663 } 2664 2665 switch (udev->speed) { 2666 case USB_SPEED_SUPER: 2667 switch (sc->sc_hw.devs[index].state) { 2668 case XHCI_ST_ADDRESSED: 2669 case XHCI_ST_CONFIGURED: 2670 /* enable power save */ 2671 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2672 break; 2673 default: 2674 /* disable power save */ 2675 break; 2676 } 2677 break; 2678 default: 2679 break; 2680 } 2681 2682 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2683 2684 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2685 2686 if (is_hub) { 2687 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2688 sc->sc_hw.devs[index].tt); 2689 } 2690 2691 hubdev = udev->parent_hs_hub; 2692 2693 /* check if we should activate the transaction translator */ 2694 switch (udev->speed) { 2695 case USB_SPEED_FULL: 2696 case USB_SPEED_LOW: 2697 if (hubdev != NULL) { 2698 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2699 hubdev->controller_slot_id); 2700 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2701 udev->hs_port_no); 2702 } 2703 break; 2704 default: 2705 break; 2706 } 2707 2708 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2709 2710 /* 2711 * These fields should be initialized to zero, according to 2712 * XHCI section 6.2.2 - slot context: 2713 */ 2714 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2715 XHCI_SCTX_3_SLOT_STATE_SET(0); 2716 2717 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2718 2719#ifdef USB_DEBUG 2720 xhci_dump_device(sc, &pinp->ctx_slot); 2721#endif 2722 usb_pc_cpu_flush(pcinp); 2723 2724 return (0); /* success */ 2725} 2726 2727static usb_error_t 2728xhci_alloc_device_ext(struct usb_device *udev) 2729{ 2730 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2731 struct usb_page_search buf_dev; 2732 struct usb_page_search buf_ep; 2733 struct xhci_trb *trb; 2734 struct usb_page_cache *pc; 2735 struct usb_page *pg; 2736 uint64_t addr; 2737 uint8_t index; 2738 uint8_t i; 2739 2740 index = udev->controller_slot_id; 2741 2742 pc = &sc->sc_hw.devs[index].device_pc; 2743 pg = &sc->sc_hw.devs[index].device_pg; 2744 2745 /* need to initialize the page cache */ 2746 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2747 2748 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2749 (2 * sizeof(struct xhci_dev_ctx)) : 2750 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2751 goto error; 2752 2753 usbd_get_page(pc, 0, &buf_dev); 2754 2755 pc = &sc->sc_hw.devs[index].input_pc; 2756 pg = &sc->sc_hw.devs[index].input_pg; 2757 2758 /* need to initialize the page cache */ 2759 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2760 2761 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2762 (2 * sizeof(struct xhci_input_dev_ctx)) : 2763 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2764 goto error; 2765 } 2766 2767 /* initialize all endpoint LINK TRBs */ 2768 2769 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2770 2771 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2772 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2773 2774 /* need to initialize the page cache */ 2775 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2776 2777 if (usb_pc_alloc_mem(pc, pg, 2778 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2779 goto error; 2780 } 2781 2782 /* lookup endpoint TRB ring */ 2783 usbd_get_page(pc, 0, &buf_ep); 2784 2785 /* get TRB pointer */ 2786 trb = buf_ep.buffer; 2787 trb += XHCI_MAX_TRANSFERS - 1; 2788 2789 /* get TRB start address */ 2790 addr = buf_ep.physaddr; 2791 2792 /* create LINK TRB */ 2793 trb->qwTrb0 = htole64(addr); 2794 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2795 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2796 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2797 2798 usb_pc_cpu_flush(pc); 2799 } 2800 2801 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2802 2803 return (0); 2804 2805error: 2806 xhci_free_device_ext(udev); 2807 2808 return (USB_ERR_NOMEM); 2809} 2810 2811static void 2812xhci_free_device_ext(struct usb_device *udev) 2813{ 2814 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2815 uint8_t index; 2816 uint8_t i; 2817 2818 index = udev->controller_slot_id; 2819 xhci_set_slot_pointer(sc, index, 0); 2820 2821 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2822 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2823 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2824 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2825} 2826 2827static struct xhci_endpoint_ext * 2828xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2829{ 2830 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2831 struct xhci_endpoint_ext *pepext; 2832 struct usb_page_cache *pc; 2833 struct usb_page_search buf_ep; 2834 uint8_t epno; 2835 uint8_t index; 2836 2837 epno = edesc->bEndpointAddress; 2838 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2839 epno |= UE_DIR_IN; 2840 2841 epno = XHCI_EPNO2EPID(epno); 2842 2843 index = udev->controller_slot_id; 2844 2845 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2846 2847 usbd_get_page(pc, 0, &buf_ep); 2848 2849 pepext = &sc->sc_hw.devs[index].endp[epno]; 2850 pepext->page_cache = pc; 2851 pepext->trb = buf_ep.buffer; 2852 pepext->physaddr = buf_ep.physaddr; 2853 2854 return (pepext); 2855} 2856 2857static void 2858xhci_endpoint_doorbell(struct usb_xfer *xfer) 2859{ 2860 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2861 uint8_t epno; 2862 uint8_t index; 2863 2864 epno = xfer->endpointno; 2865 if (xfer->flags_int.control_xfr) 2866 epno |= UE_DIR_IN; 2867 2868 epno = XHCI_EPNO2EPID(epno); 2869 index = xfer->xroot->udev->controller_slot_id; 2870 2871 if (xfer->xroot->udev->flags.self_suspended == 0) { 2872 XWRITE4(sc, door, XHCI_DOORBELL(index), 2873 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2874 } 2875} 2876 2877static void 2878xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2879{ 2880 struct xhci_endpoint_ext *pepext; 2881 2882 if (xfer->flags_int.bandwidth_reclaimed) { 2883 xfer->flags_int.bandwidth_reclaimed = 0; 2884 2885 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2886 xfer->endpoint->edesc); 2887 2888 pepext->trb_used[xfer->stream_id]--; 2889 2890 pepext->xfer[xfer->qh_pos] = NULL; 2891 2892 if (error && pepext->trb_running != 0) { 2893 pepext->trb_halted = 1; 2894 pepext->trb_running = 0; 2895 } 2896 } 2897} 2898 2899static usb_error_t 2900xhci_transfer_insert(struct usb_xfer *xfer) 2901{ 2902 struct xhci_td *td_first; 2903 struct xhci_td *td_last; 2904 struct xhci_trb *trb_link; 2905 struct xhci_endpoint_ext *pepext; 2906 uint64_t addr; 2907 usb_stream_t id; 2908 uint8_t i; 2909 uint8_t inext; 2910 uint8_t trb_limit; 2911 2912 DPRINTFN(8, "\n"); 2913 2914 id = xfer->stream_id; 2915 2916 /* check if already inserted */ 2917 if (xfer->flags_int.bandwidth_reclaimed) { 2918 DPRINTFN(8, "Already in schedule\n"); 2919 return (0); 2920 } 2921 2922 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2923 xfer->endpoint->edesc); 2924 2925 td_first = xfer->td_transfer_first; 2926 td_last = xfer->td_transfer_last; 2927 addr = pepext->physaddr; 2928 2929 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2930 case UE_CONTROL: 2931 case UE_INTERRUPT: 2932 /* single buffered */ 2933 trb_limit = 1; 2934 break; 2935 default: 2936 /* multi buffered */ 2937 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2938 break; 2939 } 2940 2941 if (pepext->trb_used[id] >= trb_limit) { 2942 DPRINTFN(8, "Too many TDs queued.\n"); 2943 return (USB_ERR_NOMEM); 2944 } 2945 2946 /* check if bMaxPacketSize changed */ 2947 if (xfer->flags_int.control_xfr != 0 && 2948 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) { 2949 2950 DPRINTFN(8, "Reconfigure control endpoint\n"); 2951 2952 /* force driver to reconfigure endpoint */ 2953 pepext->trb_halted = 1; 2954 pepext->trb_running = 0; 2955 } 2956 2957 /* check for stopped condition, after putting transfer on interrupt queue */ 2958 if (pepext->trb_running == 0) { 2959 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2960 2961 DPRINTFN(8, "Not running\n"); 2962 2963 /* start configuration */ 2964 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2965 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2966 return (0); 2967 } 2968 2969 pepext->trb_used[id]++; 2970 2971 /* get current TRB index */ 2972 i = pepext->trb_index[id]; 2973 2974 /* get next TRB index */ 2975 inext = (i + 1); 2976 2977 /* the last entry of the ring is a hardcoded link TRB */ 2978 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2979 inext = 0; 2980 2981 /* store next TRB index, before stream ID offset is added */ 2982 pepext->trb_index[id] = inext; 2983 2984 /* offset for stream */ 2985 i += id * XHCI_MAX_TRANSFERS; 2986 inext += id * XHCI_MAX_TRANSFERS; 2987 2988 /* compute terminating return address */ 2989 addr += (inext * sizeof(struct xhci_trb)); 2990 2991 /* compute link TRB pointer */ 2992 trb_link = td_last->td_trb + td_last->ntrb; 2993 2994 /* update next pointer of last link TRB */ 2995 trb_link->qwTrb0 = htole64(addr); 2996 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2997 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2998 XHCI_TRB_3_CYCLE_BIT | 2999 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 3000 3001#ifdef USB_DEBUG 3002 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 3003#endif 3004 usb_pc_cpu_flush(td_last->page_cache); 3005 3006 /* write ahead chain end marker */ 3007 3008 pepext->trb[inext].qwTrb0 = 0; 3009 pepext->trb[inext].dwTrb2 = 0; 3010 pepext->trb[inext].dwTrb3 = 0; 3011 3012 /* update next pointer of link TRB */ 3013 3014 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 3015 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 3016 3017#ifdef USB_DEBUG 3018 xhci_dump_trb(&pepext->trb[i]); 3019#endif 3020 usb_pc_cpu_flush(pepext->page_cache); 3021 3022 /* toggle cycle bit which activates the transfer chain */ 3023 3024 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 3025 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 3026 3027 usb_pc_cpu_flush(pepext->page_cache); 3028 3029 DPRINTF("qh_pos = %u\n", i); 3030 3031 pepext->xfer[i] = xfer; 3032 3033 xfer->qh_pos = i; 3034 3035 xfer->flags_int.bandwidth_reclaimed = 1; 3036 3037 xhci_endpoint_doorbell(xfer); 3038 3039 return (0); 3040} 3041 3042static void 3043xhci_root_intr(struct xhci_softc *sc) 3044{ 3045 uint16_t i; 3046 3047 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3048 3049 /* clear any old interrupt data */ 3050 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 3051 3052 for (i = 1; i <= sc->sc_noport; i++) { 3053 /* pick out CHANGE bits from the status register */ 3054 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 3055 XHCI_PS_CSC | XHCI_PS_PEC | 3056 XHCI_PS_OCC | XHCI_PS_WRC | 3057 XHCI_PS_PRC | XHCI_PS_PLC | 3058 XHCI_PS_CEC)) { 3059 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 3060 DPRINTF("port %d changed\n", i); 3061 } 3062 } 3063 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3064 sizeof(sc->sc_hub_idata)); 3065} 3066 3067/*------------------------------------------------------------------------* 3068 * xhci_device_done - XHCI done handler 3069 * 3070 * NOTE: This function can be called two times in a row on 3071 * the same USB transfer. From close and from interrupt. 3072 *------------------------------------------------------------------------*/ 3073static void 3074xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 3075{ 3076 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 3077 xfer, xfer->endpoint, error); 3078 3079 /* remove transfer from HW queue */ 3080 xhci_transfer_remove(xfer, error); 3081 3082 /* dequeue transfer and start next transfer */ 3083 usbd_transfer_done(xfer, error); 3084} 3085 3086/*------------------------------------------------------------------------* 3087 * XHCI data transfer support (generic type) 3088 *------------------------------------------------------------------------*/ 3089static void 3090xhci_device_generic_open(struct usb_xfer *xfer) 3091{ 3092 if (xfer->flags_int.isochronous_xfr) { 3093 switch (xfer->xroot->udev->speed) { 3094 case USB_SPEED_FULL: 3095 break; 3096 default: 3097 usb_hs_bandwidth_alloc(xfer); 3098 break; 3099 } 3100 } 3101} 3102 3103static void 3104xhci_device_generic_close(struct usb_xfer *xfer) 3105{ 3106 DPRINTF("\n"); 3107 3108 xhci_device_done(xfer, USB_ERR_CANCELLED); 3109 3110 if (xfer->flags_int.isochronous_xfr) { 3111 switch (xfer->xroot->udev->speed) { 3112 case USB_SPEED_FULL: 3113 break; 3114 default: 3115 usb_hs_bandwidth_free(xfer); 3116 break; 3117 } 3118 } 3119} 3120 3121static void 3122xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3123 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3124{ 3125 struct usb_xfer *xfer; 3126 3127 /* check if there is a current transfer */ 3128 xfer = ep->endpoint_q[stream_id].curr; 3129 if (xfer == NULL) 3130 return; 3131 3132 /* 3133 * Check if the current transfer is started and then pickup 3134 * the next one, if any. Else wait for next start event due to 3135 * block on failure feature. 3136 */ 3137 if (!xfer->flags_int.bandwidth_reclaimed) 3138 return; 3139 3140 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3141 if (xfer == NULL) { 3142 /* 3143 * In case of enter we have to consider that the 3144 * transfer is queued by the USB core after the enter 3145 * method is called. 3146 */ 3147 xfer = enter_xfer; 3148 3149 if (xfer == NULL) 3150 return; 3151 } 3152 3153 /* try to multi buffer */ 3154 xhci_transfer_insert(xfer); 3155} 3156 3157static void 3158xhci_device_generic_enter(struct usb_xfer *xfer) 3159{ 3160 DPRINTF("\n"); 3161 3162 /* set up TD's and QH */ 3163 xhci_setup_generic_chain(xfer); 3164 3165 xhci_device_generic_multi_enter(xfer->endpoint, 3166 xfer->stream_id, xfer); 3167} 3168 3169static void 3170xhci_device_generic_start(struct usb_xfer *xfer) 3171{ 3172 DPRINTF("\n"); 3173 3174 /* try to insert xfer on HW queue */ 3175 xhci_transfer_insert(xfer); 3176 3177 /* try to multi buffer */ 3178 xhci_device_generic_multi_enter(xfer->endpoint, 3179 xfer->stream_id, NULL); 3180 3181 /* add transfer last on interrupt queue */ 3182 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3183 3184 /* start timeout, if any */ 3185 if (xfer->timeout != 0) 3186 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3187} 3188 3189static const struct usb_pipe_methods xhci_device_generic_methods = 3190{ 3191 .open = xhci_device_generic_open, 3192 .close = xhci_device_generic_close, 3193 .enter = xhci_device_generic_enter, 3194 .start = xhci_device_generic_start, 3195}; 3196 3197/*------------------------------------------------------------------------* 3198 * xhci root HUB support 3199 *------------------------------------------------------------------------* 3200 * Simulate a hardware HUB by handling all the necessary requests. 3201 *------------------------------------------------------------------------*/ 3202 3203#define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3204 3205static const 3206struct usb_device_descriptor xhci_devd = 3207{ 3208 .bLength = sizeof(xhci_devd), 3209 .bDescriptorType = UDESC_DEVICE, /* type */ 3210 HSETW(.bcdUSB, 0x0300), /* USB version */ 3211 .bDeviceClass = UDCLASS_HUB, /* class */ 3212 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3213 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3214 .bMaxPacketSize = 9, /* max packet size */ 3215 HSETW(.idVendor, 0x0000), /* vendor */ 3216 HSETW(.idProduct, 0x0000), /* product */ 3217 HSETW(.bcdDevice, 0x0100), /* device version */ 3218 .iManufacturer = 1, 3219 .iProduct = 2, 3220 .iSerialNumber = 0, 3221 .bNumConfigurations = 1, /* # of configurations */ 3222}; 3223 3224static const 3225struct xhci_bos_desc xhci_bosd = { 3226 .bosd = { 3227 .bLength = sizeof(xhci_bosd.bosd), 3228 .bDescriptorType = UDESC_BOS, 3229 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3230 .bNumDeviceCaps = 3, 3231 }, 3232 .usb2extd = { 3233 .bLength = sizeof(xhci_bosd.usb2extd), 3234 .bDescriptorType = 1, 3235 .bDevCapabilityType = 2, 3236 .bmAttributes[0] = 2, 3237 }, 3238 .usbdcd = { 3239 .bLength = sizeof(xhci_bosd.usbdcd), 3240 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3241 .bDevCapabilityType = 3, 3242 .bmAttributes = 0, /* XXX */ 3243 HSETW(.wSpeedsSupported, 0x000C), 3244 .bFunctionalitySupport = 8, 3245 .bU1DevExitLat = 255, /* dummy - not used */ 3246 .wU2DevExitLat = { 0x00, 0x08 }, 3247 }, 3248 .cidd = { 3249 .bLength = sizeof(xhci_bosd.cidd), 3250 .bDescriptorType = 1, 3251 .bDevCapabilityType = 4, 3252 .bReserved = 0, 3253 .bContainerID = 0, /* XXX */ 3254 }, 3255}; 3256 3257static const 3258struct xhci_config_desc xhci_confd = { 3259 .confd = { 3260 .bLength = sizeof(xhci_confd.confd), 3261 .bDescriptorType = UDESC_CONFIG, 3262 .wTotalLength[0] = sizeof(xhci_confd), 3263 .bNumInterface = 1, 3264 .bConfigurationValue = 1, 3265 .iConfiguration = 0, 3266 .bmAttributes = UC_SELF_POWERED, 3267 .bMaxPower = 0 /* max power */ 3268 }, 3269 .ifcd = { 3270 .bLength = sizeof(xhci_confd.ifcd), 3271 .bDescriptorType = UDESC_INTERFACE, 3272 .bNumEndpoints = 1, 3273 .bInterfaceClass = UICLASS_HUB, 3274 .bInterfaceSubClass = UISUBCLASS_HUB, 3275 .bInterfaceProtocol = 0, 3276 }, 3277 .endpd = { 3278 .bLength = sizeof(xhci_confd.endpd), 3279 .bDescriptorType = UDESC_ENDPOINT, 3280 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3281 .bmAttributes = UE_INTERRUPT, 3282 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3283 .bInterval = 255, 3284 }, 3285 .endpcd = { 3286 .bLength = sizeof(xhci_confd.endpcd), 3287 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3288 .bMaxBurst = 0, 3289 .bmAttributes = 0, 3290 }, 3291}; 3292 3293static const 3294struct usb_hub_ss_descriptor xhci_hubd = { 3295 .bLength = sizeof(xhci_hubd), 3296 .bDescriptorType = UDESC_SS_HUB, 3297}; 3298 3299static usb_error_t 3300xhci_roothub_exec(struct usb_device *udev, 3301 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3302{ 3303 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3304 const char *str_ptr; 3305 const void *ptr; 3306 uint32_t port; 3307 uint32_t v; 3308 uint16_t len; 3309 uint16_t i; 3310 uint16_t value; 3311 uint16_t index; 3312 uint8_t j; 3313 usb_error_t err; 3314 3315 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3316 3317 /* buffer reset */ 3318 ptr = (const void *)&sc->sc_hub_desc; 3319 len = 0; 3320 err = 0; 3321 3322 value = UGETW(req->wValue); 3323 index = UGETW(req->wIndex); 3324 3325 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3326 "wValue=0x%04x wIndex=0x%04x\n", 3327 req->bmRequestType, req->bRequest, 3328 UGETW(req->wLength), value, index); 3329 3330#define C(x,y) ((x) | ((y) << 8)) 3331 switch (C(req->bRequest, req->bmRequestType)) { 3332 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3333 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3334 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3335 /* 3336 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3337 * for the integrated root hub. 3338 */ 3339 break; 3340 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3341 len = 1; 3342 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3343 break; 3344 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3345 switch (value >> 8) { 3346 case UDESC_DEVICE: 3347 if ((value & 0xff) != 0) { 3348 err = USB_ERR_IOERROR; 3349 goto done; 3350 } 3351 len = sizeof(xhci_devd); 3352 ptr = (const void *)&xhci_devd; 3353 break; 3354 3355 case UDESC_BOS: 3356 if ((value & 0xff) != 0) { 3357 err = USB_ERR_IOERROR; 3358 goto done; 3359 } 3360 len = sizeof(xhci_bosd); 3361 ptr = (const void *)&xhci_bosd; 3362 break; 3363 3364 case UDESC_CONFIG: 3365 if ((value & 0xff) != 0) { 3366 err = USB_ERR_IOERROR; 3367 goto done; 3368 } 3369 len = sizeof(xhci_confd); 3370 ptr = (const void *)&xhci_confd; 3371 break; 3372 3373 case UDESC_STRING: 3374 switch (value & 0xff) { 3375 case 0: /* Language table */ 3376 str_ptr = "\001"; 3377 break; 3378 3379 case 1: /* Vendor */ 3380 str_ptr = sc->sc_vendor; 3381 break; 3382 3383 case 2: /* Product */ 3384 str_ptr = "XHCI root HUB"; 3385 break; 3386 3387 default: 3388 str_ptr = ""; 3389 break; 3390 } 3391 3392 len = usb_make_str_desc( 3393 sc->sc_hub_desc.temp, 3394 sizeof(sc->sc_hub_desc.temp), 3395 str_ptr); 3396 break; 3397 3398 default: 3399 err = USB_ERR_IOERROR; 3400 goto done; 3401 } 3402 break; 3403 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3404 len = 1; 3405 sc->sc_hub_desc.temp[0] = 0; 3406 break; 3407 case C(UR_GET_STATUS, UT_READ_DEVICE): 3408 len = 2; 3409 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3410 break; 3411 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3412 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3413 len = 2; 3414 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3415 break; 3416 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3417 if (value >= XHCI_MAX_DEVICES) { 3418 err = USB_ERR_IOERROR; 3419 goto done; 3420 } 3421 break; 3422 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3423 if (value != 0 && value != 1) { 3424 err = USB_ERR_IOERROR; 3425 goto done; 3426 } 3427 sc->sc_conf = value; 3428 break; 3429 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3430 break; 3431 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3432 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3433 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3434 err = USB_ERR_IOERROR; 3435 goto done; 3436 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3437 break; 3438 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3439 break; 3440 /* Hub requests */ 3441 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3442 break; 3443 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3444 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3445 3446 if ((index < 1) || 3447 (index > sc->sc_noport)) { 3448 err = USB_ERR_IOERROR; 3449 goto done; 3450 } 3451 port = XHCI_PORTSC(index); 3452 3453 v = XREAD4(sc, oper, port); 3454 i = XHCI_PS_PLS_GET(v); 3455 v &= ~XHCI_PS_CLEAR; 3456 3457 switch (value) { 3458 case UHF_C_BH_PORT_RESET: 3459 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3460 break; 3461 case UHF_C_PORT_CONFIG_ERROR: 3462 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3463 break; 3464 case UHF_C_PORT_SUSPEND: 3465 case UHF_C_PORT_LINK_STATE: 3466 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3467 break; 3468 case UHF_C_PORT_CONNECTION: 3469 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3470 break; 3471 case UHF_C_PORT_ENABLE: 3472 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3473 break; 3474 case UHF_C_PORT_OVER_CURRENT: 3475 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3476 break; 3477 case UHF_C_PORT_RESET: 3478 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3479 break; 3480 case UHF_PORT_ENABLE: 3481 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3482 break; 3483 case UHF_PORT_POWER: 3484 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3485 break; 3486 case UHF_PORT_INDICATOR: 3487 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3488 break; 3489 case UHF_PORT_SUSPEND: 3490 3491 /* U3 -> U15 */ 3492 if (i == 3) { 3493 XWRITE4(sc, oper, port, v | 3494 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3495 } 3496 3497 /* wait 20ms for resume sequence to complete */ 3498 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3499 3500 /* U0 */ 3501 XWRITE4(sc, oper, port, v | 3502 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3503 break; 3504 default: 3505 err = USB_ERR_IOERROR; 3506 goto done; 3507 } 3508 break; 3509 3510 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3511 if ((value & 0xff) != 0) { 3512 err = USB_ERR_IOERROR; 3513 goto done; 3514 } 3515 3516 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3517 3518 sc->sc_hub_desc.hubd = xhci_hubd; 3519 3520 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3521 3522 if (XHCI_HCS0_PPC(v)) 3523 i = UHD_PWR_INDIVIDUAL; 3524 else 3525 i = UHD_PWR_GANGED; 3526 3527 if (XHCI_HCS0_PIND(v)) 3528 i |= UHD_PORT_IND; 3529 3530 i |= UHD_OC_INDIVIDUAL; 3531 3532 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3533 3534 /* see XHCI section 5.4.9: */ 3535 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3536 3537 for (j = 1; j <= sc->sc_noport; j++) { 3538 3539 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3540 if (v & XHCI_PS_DR) { 3541 sc->sc_hub_desc.hubd. 3542 DeviceRemovable[j / 8] |= 1U << (j % 8); 3543 } 3544 } 3545 len = sc->sc_hub_desc.hubd.bLength; 3546 break; 3547 3548 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3549 len = 16; 3550 memset(sc->sc_hub_desc.temp, 0, 16); 3551 break; 3552 3553 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3554 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3555 3556 if ((index < 1) || 3557 (index > sc->sc_noport)) { 3558 err = USB_ERR_IOERROR; 3559 goto done; 3560 } 3561 3562 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3563 3564 DPRINTFN(9, "port status=0x%08x\n", v); 3565 3566 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3567 3568 switch (XHCI_PS_SPEED_GET(v)) { 3569 case 3: 3570 i |= UPS_HIGH_SPEED; 3571 break; 3572 case 2: 3573 i |= UPS_LOW_SPEED; 3574 break; 3575 case 1: 3576 /* FULL speed */ 3577 break; 3578 default: 3579 i |= UPS_OTHER_SPEED; 3580 break; 3581 } 3582 3583 if (v & XHCI_PS_CCS) 3584 i |= UPS_CURRENT_CONNECT_STATUS; 3585 if (v & XHCI_PS_PED) 3586 i |= UPS_PORT_ENABLED; 3587 if (v & XHCI_PS_OCA) 3588 i |= UPS_OVERCURRENT_INDICATOR; 3589 if (v & XHCI_PS_PR) 3590 i |= UPS_RESET; 3591#if 0 3592 if (v & XHCI_PS_PP) 3593 /* XXX undefined */ 3594#endif 3595 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3596 3597 i = 0; 3598 if (v & XHCI_PS_CSC) 3599 i |= UPS_C_CONNECT_STATUS; 3600 if (v & XHCI_PS_PEC) 3601 i |= UPS_C_PORT_ENABLED; 3602 if (v & XHCI_PS_OCC) 3603 i |= UPS_C_OVERCURRENT_INDICATOR; 3604 if (v & XHCI_PS_WRC) 3605 i |= UPS_C_BH_PORT_RESET; 3606 if (v & XHCI_PS_PRC) 3607 i |= UPS_C_PORT_RESET; 3608 if (v & XHCI_PS_PLC) 3609 i |= UPS_C_PORT_LINK_STATE; 3610 if (v & XHCI_PS_CEC) 3611 i |= UPS_C_PORT_CONFIG_ERROR; 3612 3613 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3614 len = sizeof(sc->sc_hub_desc.ps); 3615 break; 3616 3617 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3618 err = USB_ERR_IOERROR; 3619 goto done; 3620 3621 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3622 break; 3623 3624 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3625 3626 i = index >> 8; 3627 index &= 0x00FF; 3628 3629 if ((index < 1) || 3630 (index > sc->sc_noport)) { 3631 err = USB_ERR_IOERROR; 3632 goto done; 3633 } 3634 3635 port = XHCI_PORTSC(index); 3636 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3637 3638 switch (value) { 3639 case UHF_PORT_U1_TIMEOUT: 3640 if (XHCI_PS_SPEED_GET(v) != 4) { 3641 err = USB_ERR_IOERROR; 3642 goto done; 3643 } 3644 port = XHCI_PORTPMSC(index); 3645 v = XREAD4(sc, oper, port); 3646 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3647 v |= XHCI_PM3_U1TO_SET(i); 3648 XWRITE4(sc, oper, port, v); 3649 break; 3650 case UHF_PORT_U2_TIMEOUT: 3651 if (XHCI_PS_SPEED_GET(v) != 4) { 3652 err = USB_ERR_IOERROR; 3653 goto done; 3654 } 3655 port = XHCI_PORTPMSC(index); 3656 v = XREAD4(sc, oper, port); 3657 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3658 v |= XHCI_PM3_U2TO_SET(i); 3659 XWRITE4(sc, oper, port, v); 3660 break; 3661 case UHF_BH_PORT_RESET: 3662 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3663 break; 3664 case UHF_PORT_LINK_STATE: 3665 XWRITE4(sc, oper, port, v | 3666 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3667 /* 4ms settle time */ 3668 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3669 break; 3670 case UHF_PORT_ENABLE: 3671 DPRINTFN(3, "set port enable %d\n", index); 3672 break; 3673 case UHF_PORT_SUSPEND: 3674 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3675 j = XHCI_PS_SPEED_GET(v); 3676 if ((j < 1) || (j > 3)) { 3677 /* non-supported speed */ 3678 err = USB_ERR_IOERROR; 3679 goto done; 3680 } 3681 XWRITE4(sc, oper, port, v | 3682 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3683 break; 3684 case UHF_PORT_RESET: 3685 DPRINTFN(6, "reset port %d\n", index); 3686 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3687 break; 3688 case UHF_PORT_POWER: 3689 DPRINTFN(3, "set port power %d\n", index); 3690 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3691 break; 3692 case UHF_PORT_TEST: 3693 DPRINTFN(3, "set port test %d\n", index); 3694 break; 3695 case UHF_PORT_INDICATOR: 3696 DPRINTFN(3, "set port indicator %d\n", index); 3697 3698 v &= ~XHCI_PS_PIC_SET(3); 3699 v |= XHCI_PS_PIC_SET(1); 3700 3701 XWRITE4(sc, oper, port, v); 3702 break; 3703 default: 3704 err = USB_ERR_IOERROR; 3705 goto done; 3706 } 3707 break; 3708 3709 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3710 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3711 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3712 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3713 break; 3714 default: 3715 err = USB_ERR_IOERROR; 3716 goto done; 3717 } 3718done: 3719 *plength = len; 3720 *pptr = ptr; 3721 return (err); 3722} 3723 3724static void 3725xhci_xfer_setup(struct usb_setup_params *parm) 3726{ 3727 struct usb_page_search page_info; 3728 struct usb_page_cache *pc; 3729 struct xhci_softc *sc; 3730 struct usb_xfer *xfer; 3731 void *last_obj; 3732 uint32_t ntd; 3733 uint32_t n; 3734 3735 sc = XHCI_BUS2SC(parm->udev->bus); 3736 xfer = parm->curr_xfer; 3737 3738 /* 3739 * The proof for the "ntd" formula is illustrated like this: 3740 * 3741 * +------------------------------------+ 3742 * | | 3743 * | |remainder -> | 3744 * | +-----+---+ | 3745 * | | xxx | x | frm 0 | 3746 * | +-----+---++ | 3747 * | | xxx | xx | frm 1 | 3748 * | +-----+----+ | 3749 * | ... | 3750 * +------------------------------------+ 3751 * 3752 * "xxx" means a completely full USB transfer descriptor 3753 * 3754 * "x" and "xx" means a short USB packet 3755 * 3756 * For the remainder of an USB transfer modulo 3757 * "max_data_length" we need two USB transfer descriptors. 3758 * One to transfer the remaining data and one to finalise with 3759 * a zero length packet in case the "force_short_xfer" flag is 3760 * set. We only need two USB transfer descriptors in the case 3761 * where the transfer length of the first one is a factor of 3762 * "max_frame_size". The rest of the needed USB transfer 3763 * descriptors is given by the buffer size divided by the 3764 * maximum data payload. 3765 */ 3766 parm->hc_max_packet_size = 0x400; 3767 parm->hc_max_packet_count = 16 * 3; 3768 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3769 3770 xfer->flags_int.bdma_enable = 1; 3771 3772 usbd_transfer_setup_sub(parm); 3773 3774 if (xfer->flags_int.isochronous_xfr) { 3775 ntd = ((1 * xfer->nframes) 3776 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3777 } else if (xfer->flags_int.control_xfr) { 3778 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3779 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3780 } else { 3781 ntd = ((2 * xfer->nframes) 3782 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3783 } 3784 3785alloc_dma_set: 3786 3787 if (parm->err) 3788 return; 3789 3790 /* 3791 * Allocate queue heads and transfer descriptors 3792 */ 3793 last_obj = NULL; 3794 3795 if (usbd_transfer_setup_sub_malloc( 3796 parm, &pc, sizeof(struct xhci_td), 3797 XHCI_TD_ALIGN, ntd)) { 3798 parm->err = USB_ERR_NOMEM; 3799 return; 3800 } 3801 if (parm->buf) { 3802 for (n = 0; n != ntd; n++) { 3803 struct xhci_td *td; 3804 3805 usbd_get_page(pc + n, 0, &page_info); 3806 3807 td = page_info.buffer; 3808 3809 /* init TD */ 3810 td->td_self = page_info.physaddr; 3811 td->obj_next = last_obj; 3812 td->page_cache = pc + n; 3813 3814 last_obj = td; 3815 3816 usb_pc_cpu_flush(pc + n); 3817 } 3818 } 3819 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3820 3821 if (!xfer->flags_int.curr_dma_set) { 3822 xfer->flags_int.curr_dma_set = 1; 3823 goto alloc_dma_set; 3824 } 3825} 3826 3827static usb_error_t 3828xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3829{ 3830 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3831 struct usb_page_search buf_inp; 3832 struct usb_device *udev; 3833 struct xhci_endpoint_ext *pepext; 3834 struct usb_endpoint_descriptor *edesc; 3835 struct usb_page_cache *pcinp; 3836 usb_error_t err; 3837 usb_stream_t stream_id; 3838 uint32_t mask; 3839 uint8_t index; 3840 uint8_t epno; 3841 3842 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3843 xfer->endpoint->edesc); 3844 3845 udev = xfer->xroot->udev; 3846 index = udev->controller_slot_id; 3847 3848 pcinp = &sc->sc_hw.devs[index].input_pc; 3849 3850 usbd_get_page(pcinp, 0, &buf_inp); 3851 3852 edesc = xfer->endpoint->edesc; 3853 3854 epno = edesc->bEndpointAddress; 3855 stream_id = xfer->stream_id; 3856 3857 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3858 epno |= UE_DIR_IN; 3859 3860 epno = XHCI_EPNO2EPID(epno); 3861 3862 if (epno == 0) 3863 return (USB_ERR_NO_PIPE); /* invalid */ 3864 3865 XHCI_CMD_LOCK(sc); 3866 3867 /* configure endpoint */ 3868 3869 err = xhci_configure_endpoint_by_xfer(xfer); 3870 3871 if (err != 0) { 3872 XHCI_CMD_UNLOCK(sc); 3873 return (err); 3874 } 3875 3876 /* 3877 * Get the endpoint into the stopped state according to the 3878 * endpoint context state diagram in the XHCI specification: 3879 */ 3880 3881 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3882 3883 if (err != 0) 3884 DPRINTF("Could not stop endpoint %u\n", epno); 3885 3886 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3887 3888 if (err != 0) 3889 DPRINTF("Could not reset endpoint %u\n", epno); 3890 3891 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3892 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3893 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3894 stream_id, epno, index); 3895 3896 if (err != 0) 3897 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3898 3899 /* 3900 * Get the endpoint into the running state according to the 3901 * endpoint context state diagram in the XHCI specification: 3902 */ 3903 3904 mask = (1U << epno); 3905 xhci_configure_mask(udev, mask | 1U, 0); 3906 3907 if (!(sc->sc_hw.devs[index].ep_configured & mask)) { 3908 sc->sc_hw.devs[index].ep_configured |= mask; 3909 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3910 } else { 3911 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3912 } 3913 3914 if (err != 0) { 3915 DPRINTF("Could not configure " 3916 "endpoint %u at slot %u.\n", epno, index); 3917 } 3918 XHCI_CMD_UNLOCK(sc); 3919 3920 return (0); 3921} 3922 3923static void 3924xhci_xfer_unsetup(struct usb_xfer *xfer) 3925{ 3926 return; 3927} 3928 3929static void 3930xhci_start_dma_delay(struct usb_xfer *xfer) 3931{ 3932 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3933 3934 /* put transfer on interrupt queue (again) */ 3935 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3936 3937 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3938 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3939} 3940 3941static void 3942xhci_configure_msg(struct usb_proc_msg *pm) 3943{ 3944 struct xhci_softc *sc; 3945 struct xhci_endpoint_ext *pepext; 3946 struct usb_xfer *xfer; 3947 3948 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3949 3950restart: 3951 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3952 3953 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3954 xfer->endpoint->edesc); 3955 3956 if ((pepext->trb_halted != 0) || 3957 (pepext->trb_running == 0)) { 3958 3959 uint16_t i; 3960 3961 /* clear halted and running */ 3962 pepext->trb_halted = 0; 3963 pepext->trb_running = 0; 3964 3965 /* nuke remaining buffered transfers */ 3966 3967 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3968 XHCI_MAX_STREAMS); i++) { 3969 /* 3970 * NOTE: We need to use the timeout 3971 * error code here else existing 3972 * isochronous clients can get 3973 * confused: 3974 */ 3975 if (pepext->xfer[i] != NULL) { 3976 xhci_device_done(pepext->xfer[i], 3977 USB_ERR_TIMEOUT); 3978 } 3979 } 3980 3981 /* 3982 * NOTE: The USB transfer cannot vanish in 3983 * this state! 3984 */ 3985 3986 USB_BUS_UNLOCK(&sc->sc_bus); 3987 3988 xhci_configure_reset_endpoint(xfer); 3989 3990 USB_BUS_LOCK(&sc->sc_bus); 3991 3992 /* check if halted is still cleared */ 3993 if (pepext->trb_halted == 0) { 3994 pepext->trb_running = 1; 3995 memset(pepext->trb_index, 0, 3996 sizeof(pepext->trb_index)); 3997 } 3998 goto restart; 3999 } 4000 4001 if (xfer->flags_int.did_dma_delay) { 4002 4003 /* remove transfer from interrupt queue (again) */ 4004 usbd_transfer_dequeue(xfer); 4005 4006 /* we are finally done */ 4007 usb_dma_delay_done_cb(xfer); 4008 4009 /* queue changed - restart */ 4010 goto restart; 4011 } 4012 } 4013 4014 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4015 4016 /* try to insert xfer on HW queue */ 4017 xhci_transfer_insert(xfer); 4018 4019 /* try to multi buffer */ 4020 xhci_device_generic_multi_enter(xfer->endpoint, 4021 xfer->stream_id, NULL); 4022 } 4023} 4024 4025static void 4026xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4027 struct usb_endpoint *ep) 4028{ 4029 struct xhci_endpoint_ext *pepext; 4030 4031 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 4032 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 4033 4034 if (udev->parent_hub == NULL) { 4035 /* root HUB has special endpoint handling */ 4036 return; 4037 } 4038 4039 ep->methods = &xhci_device_generic_methods; 4040 4041 pepext = xhci_get_endpoint_ext(udev, edesc); 4042 4043 USB_BUS_LOCK(udev->bus); 4044 pepext->trb_halted = 1; 4045 pepext->trb_running = 0; 4046 USB_BUS_UNLOCK(udev->bus); 4047} 4048 4049static void 4050xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 4051{ 4052 4053} 4054 4055static void 4056xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 4057{ 4058 struct xhci_endpoint_ext *pepext; 4059 4060 DPRINTF("\n"); 4061 4062 if (udev->flags.usb_mode != USB_MODE_HOST) { 4063 /* not supported */ 4064 return; 4065 } 4066 if (udev->parent_hub == NULL) { 4067 /* root HUB has special endpoint handling */ 4068 return; 4069 } 4070 4071 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 4072 4073 USB_BUS_LOCK(udev->bus); 4074 pepext->trb_halted = 1; 4075 pepext->trb_running = 0; 4076 USB_BUS_UNLOCK(udev->bus); 4077} 4078 4079static usb_error_t 4080xhci_device_init(struct usb_device *udev) 4081{ 4082 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4083 usb_error_t err; 4084 uint8_t temp; 4085 4086 /* no init for root HUB */ 4087 if (udev->parent_hub == NULL) 4088 return (0); 4089 4090 XHCI_CMD_LOCK(sc); 4091 4092 /* set invalid default */ 4093 4094 udev->controller_slot_id = sc->sc_noslot + 1; 4095 4096 /* try to get a new slot ID from the XHCI */ 4097 4098 err = xhci_cmd_enable_slot(sc, &temp); 4099 4100 if (err) { 4101 XHCI_CMD_UNLOCK(sc); 4102 return (err); 4103 } 4104 4105 if (temp > sc->sc_noslot) { 4106 XHCI_CMD_UNLOCK(sc); 4107 return (USB_ERR_BAD_ADDRESS); 4108 } 4109 4110 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4111 DPRINTF("slot %u already allocated.\n", temp); 4112 XHCI_CMD_UNLOCK(sc); 4113 return (USB_ERR_BAD_ADDRESS); 4114 } 4115 4116 /* store slot ID for later reference */ 4117 4118 udev->controller_slot_id = temp; 4119 4120 /* reset data structure */ 4121 4122 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4123 4124 /* set mark slot allocated */ 4125 4126 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4127 4128 err = xhci_alloc_device_ext(udev); 4129 4130 XHCI_CMD_UNLOCK(sc); 4131 4132 /* get device into default state */ 4133 4134 if (err == 0) 4135 err = xhci_set_address(udev, NULL, 0); 4136 4137 return (err); 4138} 4139 4140static void 4141xhci_device_uninit(struct usb_device *udev) 4142{ 4143 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4144 uint8_t index; 4145 4146 /* no init for root HUB */ 4147 if (udev->parent_hub == NULL) 4148 return; 4149 4150 XHCI_CMD_LOCK(sc); 4151 4152 index = udev->controller_slot_id; 4153 4154 if (index <= sc->sc_noslot) { 4155 xhci_cmd_disable_slot(sc, index); 4156 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4157 4158 /* free device extension */ 4159 xhci_free_device_ext(udev); 4160 } 4161 4162 XHCI_CMD_UNLOCK(sc); 4163} 4164 4165static void 4166xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4167{ 4168 /* 4169 * Wait until the hardware has finished any possible use of 4170 * the transfer descriptor(s) 4171 */ 4172 *pus = 2048; /* microseconds */ 4173} 4174 4175static void 4176xhci_device_resume(struct usb_device *udev) 4177{ 4178 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4179 uint8_t index; 4180 uint8_t n; 4181 uint8_t p; 4182 4183 DPRINTF("\n"); 4184 4185 /* check for root HUB */ 4186 if (udev->parent_hub == NULL) 4187 return; 4188 4189 index = udev->controller_slot_id; 4190 4191 XHCI_CMD_LOCK(sc); 4192 4193 /* blindly resume all endpoints */ 4194 4195 USB_BUS_LOCK(udev->bus); 4196 4197 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4198 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4199 XWRITE4(sc, door, XHCI_DOORBELL(index), 4200 n | XHCI_DB_SID_SET(p)); 4201 } 4202 } 4203 4204 USB_BUS_UNLOCK(udev->bus); 4205 4206 XHCI_CMD_UNLOCK(sc); 4207} 4208 4209static void 4210xhci_device_suspend(struct usb_device *udev) 4211{ 4212 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4213 uint8_t index; 4214 uint8_t n; 4215 usb_error_t err; 4216 4217 DPRINTF("\n"); 4218 4219 /* check for root HUB */ 4220 if (udev->parent_hub == NULL) 4221 return; 4222 4223 index = udev->controller_slot_id; 4224 4225 XHCI_CMD_LOCK(sc); 4226 4227 /* blindly suspend all endpoints */ 4228 4229 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4230 err = xhci_cmd_stop_ep(sc, 1, n, index); 4231 if (err != 0) { 4232 DPRINTF("Failed to suspend endpoint " 4233 "%u on slot %u (ignored).\n", n, index); 4234 } 4235 } 4236 4237 XHCI_CMD_UNLOCK(sc); 4238} 4239 4240static void 4241xhci_set_hw_power(struct usb_bus *bus) 4242{ 4243 DPRINTF("\n"); 4244} 4245 4246static void 4247xhci_device_state_change(struct usb_device *udev) 4248{ 4249 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4250 struct usb_page_search buf_inp; 4251 usb_error_t err; 4252 uint8_t index; 4253 4254 /* check for root HUB */ 4255 if (udev->parent_hub == NULL) 4256 return; 4257 4258 index = udev->controller_slot_id; 4259 4260 DPRINTF("\n"); 4261 4262 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4263 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4264 &sc->sc_hw.devs[index].tt); 4265 if (err != 0) 4266 sc->sc_hw.devs[index].nports = 0; 4267 } 4268 4269 XHCI_CMD_LOCK(sc); 4270 4271 switch (usb_get_device_state(udev)) { 4272 case USB_STATE_POWERED: 4273 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4274 break; 4275 4276 /* set default state */ 4277 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4278 sc->sc_hw.devs[index].ep_configured = 3U; 4279 4280 /* reset number of contexts */ 4281 sc->sc_hw.devs[index].context_num = 0; 4282 4283 err = xhci_cmd_reset_dev(sc, index); 4284 4285 if (err != 0) { 4286 DPRINTF("Device reset failed " 4287 "for slot %u.\n", index); 4288 } 4289 break; 4290 4291 case USB_STATE_ADDRESSED: 4292 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4293 break; 4294 4295 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4296 sc->sc_hw.devs[index].ep_configured = 3U; 4297 4298 /* set configure mask to slot only */ 4299 xhci_configure_mask(udev, 1, 0); 4300 4301 /* deconfigure all endpoints, except EP0 */ 4302 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4303 4304 if (err) { 4305 DPRINTF("Failed to deconfigure " 4306 "slot %u.\n", index); 4307 } 4308 break; 4309 4310 case USB_STATE_CONFIGURED: 4311 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) { 4312 /* deconfigure all endpoints, except EP0 */ 4313 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4314 4315 if (err) { 4316 DPRINTF("Failed to deconfigure " 4317 "slot %u.\n", index); 4318 } 4319 } 4320 4321 /* set configured state */ 4322 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4323 sc->sc_hw.devs[index].ep_configured = 3U; 4324 4325 /* reset number of contexts */ 4326 sc->sc_hw.devs[index].context_num = 0; 4327 4328 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4329 4330 xhci_configure_mask(udev, 3, 0); 4331 4332 err = xhci_configure_device(udev); 4333 if (err != 0) { 4334 DPRINTF("Could not configure device " 4335 "at slot %u.\n", index); 4336 } 4337 4338 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4339 if (err != 0) { 4340 DPRINTF("Could not evaluate device " 4341 "context at slot %u.\n", index); 4342 } 4343 break; 4344 4345 default: 4346 break; 4347 } 4348 XHCI_CMD_UNLOCK(sc); 4349} 4350 4351static usb_error_t 4352xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4353 uint8_t ep_mode) 4354{ 4355 switch (ep_mode) { 4356 case USB_EP_MODE_DEFAULT: 4357 return (0); 4358 case USB_EP_MODE_STREAMS: 4359 if (xhcistreams == 0 || 4360 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4361 udev->speed != USB_SPEED_SUPER) 4362 return (USB_ERR_INVAL); 4363 return (0); 4364 default: 4365 return (USB_ERR_INVAL); 4366 } 4367} 4368 4369static const struct usb_bus_methods xhci_bus_methods = { 4370 .endpoint_init = xhci_ep_init, 4371 .endpoint_uninit = xhci_ep_uninit, 4372 .xfer_setup = xhci_xfer_setup, 4373 .xfer_unsetup = xhci_xfer_unsetup, 4374 .get_dma_delay = xhci_get_dma_delay, 4375 .device_init = xhci_device_init, 4376 .device_uninit = xhci_device_uninit, 4377 .device_resume = xhci_device_resume, 4378 .device_suspend = xhci_device_suspend, 4379 .set_hw_power = xhci_set_hw_power, 4380 .roothub_exec = xhci_roothub_exec, 4381 .xfer_poll = xhci_do_poll, 4382 .start_dma_delay = xhci_start_dma_delay, 4383 .set_address = xhci_set_address, 4384 .clear_stall = xhci_ep_clear_stall, 4385 .device_state_change = xhci_device_state_change, 4386 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4387 .set_endpoint_mode = xhci_set_endpoint_mode, 4388}; 4389