atmegadci.h revision 187160
1109998Smarkm/* $FreeBSD: head/sys/dev/usb2/controller/atmegadci.h 187160 2009-01-13 18:49:35Z thompsa $ */ 2109998Smarkm/*- 3238405Sjkim * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 4109998Smarkm * 5109998Smarkm * Redistribution and use in source and binary forms, with or without 6109998Smarkm * modification, are permitted provided that the following conditions 7109998Smarkm * are met: 8109998Smarkm * 1. Redistributions of source code must retain the above copyright 9109998Smarkm * notice, this list of conditions and the following disclaimer. 10280304Sjkim * 2. Redistributions in binary form must reproduce the above copyright 11109998Smarkm * notice, this list of conditions and the following disclaimer in the 12109998Smarkm * documentation and/or other materials provided with the distribution. 13109998Smarkm * 14109998Smarkm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15109998Smarkm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16109998Smarkm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17109998Smarkm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18109998Smarkm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19109998Smarkm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20109998Smarkm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21109998Smarkm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22109998Smarkm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23109998Smarkm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24109998Smarkm * SUCH DAMAGE. 25109998Smarkm */ 26109998Smarkm 27109998Smarkm/* 28109998Smarkm * USB Device Port register definitions, copied from ATMEGA 29109998Smarkm * documentation provided by ATMEL. 30109998Smarkm */ 31109998Smarkm 32109998Smarkm#ifndef _ATMEGADCI_H_ 33109998Smarkm#define _ATMEGADCI_H_ 34109998Smarkm 35109998Smarkm#define ATMEGA_MAX_DEVICES (USB_MIN_DEVICES + 1) 36109998Smarkm 37109998Smarkm#ifndef ATMEGA_HAVE_BUS_SPACE 38109998Smarkm#define ATMEGA_HAVE_BUS_SPACE 1 39109998Smarkm#endif 40109998Smarkm 41109998Smarkm#define ATMEGA_UEINT 0xF4 42109998Smarkm#define ATMEGA_UEINT_MASK(n) (1 << (n)) /* endpoint interrupt mask */ 43109998Smarkm 44109998Smarkm#define ATMEGA_UEBCHX 0xF3 /* FIFO byte count high */ 45109998Smarkm#define ATMEGA_UEBCLX 0xF2 /* FIFO byte count low */ 46109998Smarkm#define ATMEGA_UEDATX 0xF1 /* FIFO data */ 47109998Smarkm 48109998Smarkm#define ATMEGA_UEIENX 0xF0 /* interrupt enable register */ 49109998Smarkm#define ATMEGA_UEIENX_TXINE (1 << 0) 50109998Smarkm#define ATMEGA_UEIENX_STALLEDE (1 << 1) 51109998Smarkm#define ATMEGA_UEIENX_RXOUTE (1 << 2) 52109998Smarkm#define ATMEGA_UEIENX_RXSTPE (1 << 3) /* received SETUP packet */ 53238405Sjkim#define ATMEGA_UEIENX_NAKOUTE (1 << 4) 54109998Smarkm#define ATMEGA_UEIENX_NAKINE (1 << 6) 55109998Smarkm#define ATMEGA_UEIENX_FLERRE (1 << 7) 56280304Sjkim 57280304Sjkim#define ATMEGA_UESTA1X 0xEF 58238405Sjkim#define ATMEGA_UESTA1X_CURRBK (3 << 0) /* current bank */ 59280304Sjkim#define ATMEGA_UESTA1X_CTRLDIR (1 << 2) /* control endpoint direction */ 60280304Sjkim 61109998Smarkm#define ATMEGA_UESTA0X 0xEE 62#define ATMEGA_UESTA0X_NBUSYBK (3 << 0) 63#define ATMEGA_UESTA0X_DTSEQ (3 << 2) 64#define ATMEGA_UESTA0X_UNDERFI (1 << 5) /* underflow */ 65#define ATMEGA_UESTA0X_OVERFI (1 << 6) /* overflow */ 66#define ATMEGA_UESTA0X_CFGOK (1 << 7) 67 68#define ATMEGA_UECFG1X 0xED /* endpoint config register */ 69#define ATMEGA_UECFG1X_ALLOC (1 << 1) 70#define ATMEGA_UECFG1X_EPBK0 (0 << 2) 71#define ATMEGA_UECFG1X_EPBK1 (1 << 2) 72#define ATMEGA_UECFG1X_EPBK2 (2 << 2) 73#define ATMEGA_UECFG1X_EPBK3 (3 << 2) 74#define ATMEGA_UECFG1X_EPSIZE(n) ((n) << 4) 75 76#define ATMEGA_UECFG0X 0xEC 77#define ATMEGA_UECFG0X_EPDIR (1 << 0) /* endpoint direction */ 78#define ATMEGA_UECFG0X_EPTYPE0 (0 << 6) 79#define ATMEGA_UECFG0X_EPTYPE1 (1 << 6) 80#define ATMEGA_UECFG0X_EPTYPE2 (2 << 6) 81#define ATMEGA_UECFG0X_EPTYPE3 (3 << 6) 82 83#define ATMEGA_UECONX 0xEB 84#define ATMEGA_UECONX_EPEN (1 << 0) 85#define ATMEGA_UECONX_RSTDT (1 << 3) 86#define ATMEGA_UECONX_STALLRQC (1 << 4) /* stall request clear */ 87#define ATMEGA_UECONX_STALLRQ (1 << 5) /* stall request set */ 88 89#define ATMEGA_UERST 0xEA /* endpoint reset register */ 90#define ATMEGA_UERST_MASK(n) (1 << (n)) 91 92#define ATMEGA_UENUM 0xE9 /* endpoint number */ 93 94#define ATMEGA_UEINTX 0xE8 /* interrupt register */ 95#define ATMEGA_UEINTX_TXINI (1 << 0) 96#define ATMEGA_UEINTX_STALLEDI (1 << 1) 97#define ATMEGA_UEINTX_RXOUTI (1 << 2) 98#define ATMEGA_UEINTX_RXSTPI (1 << 3) /* received setup packet */ 99#define ATMEGA_UEINTX_NAKOUTI (1 << 4) 100#define ATMEGA_UEINTX_RWAL (1 << 5) 101#define ATMEGA_UEINTX_NAKINI (1 << 6) 102#define ATMEGA_UEINTX_FIFOCON (1 << 7) 103 104#define ATMEGA_UDMFN 0xE6 105#define ATMEGA_UDMFN_FNCERR (1 << 4) 106 107#define ATMEGA_UDFNUMH 0xE5 /* frame number high */ 108#define ATMEGA_UDFNUMH_MASK 7 109 110#define ATMEGA_UDFNUML 0xE4 /* frame number low */ 111#define ATMEGA_UDFNUML_MASK 0xFF 112 113#define ATMEGA_FRAME_MASK 0x7FF 114 115#define ATMEGA_UDADDR 0xE3 /* USB address */ 116#define ATMEGA_UDADDR_MASK 0x7F 117#define ATMEGA_UDADDR_ADDEN (1 << 7) 118 119#define ATMEGA_UDIEN 0xE2 /* USB device interrupt enable */ 120#define ATMEGA_UDINT_SUSPE (1 << 0) 121#define ATMEGA_UDINT_MSOFE (1 << 1) 122#define ATMEGA_UDINT_SOFE (1 << 2) 123#define ATMEGA_UDINT_EORSTE (1 << 3) 124#define ATMEGA_UDINT_WAKEUPE (1 << 4) 125#define ATMEGA_UDINT_EORSME (1 << 5) 126#define ATMEGA_UDINT_UPRSME (1 << 6) 127 128#define ATMEGA_UDINT 0xE1 /* USB device interrupt status */ 129#define ATMEGA_UDINT_SUSPI (1 << 0) 130#define ATMEGA_UDINT_MSOFI (1 << 1) 131#define ATMEGA_UDINT_SOFI (1 << 2) 132#define ATMEGA_UDINT_EORSTI (1 << 3) 133#define ATMEGA_UDINT_WAKEUPI (1 << 4) 134#define ATMEGA_UDINT_EORSMI (1 << 5) 135#define ATMEGA_UDINT_UPRSMI (1 << 6) 136 137#define ATMEGA_UDCON 0xE0 /* USB device connection register */ 138#define ATMEGA_UDCON_DETACH (1 << 0) 139#define ATMEGA_UDCON_RMWKUP (1 << 1) 140#define ATMEGA_UDCON_LSM (1 << 2) 141#define ATMEGA_UDCON_RSTCPU (1 << 3) 142 143#define ATMEGA_USBINT 0xDA 144#define ATMEGA_USBINT_VBUSTI (1 << 0) /* USB VBUS interrupt */ 145 146#define ATMEGA_USBSTA 0xD9 147#define ATMEGA_USBSTA_VBUS (1 << 0) 148#define ATMEGA_USBSTA_ID (1 << 1) 149 150#define ATMEGA_USBCON 0xD8 151#define ATMEGA_USBCON_VBUSTE (1 << 0) 152#define ATMEGA_USBCON_OTGPADE (1 << 4) 153#define ATMEGA_USBCON_FRZCLK (1 << 5) 154#define ATMEGA_USBCON_USBE (1 << 7) 155 156#define ATMEGA_UHWCON 0xD7 157#define ATMEGA_UHWCON_UVREGE (1 << 0) 158 159#define ATMEGA_READ_1(sc, reg) \ 160 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 161 162#define ATMEGA_WRITE_1(sc, reg, data) \ 163 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 164 165#define ATMEGA_WRITE_MULTI_1(sc, reg, ptr, len) \ 166 bus_space_write_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len) 167 168#define ATMEGA_READ_MULTI_1(sc, reg, ptr, len) \ 169 bus_space_read_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len) 170 171/* 172 * Maximum number of endpoints supported: 173 */ 174#define ATMEGA_EP_MAX 7 175 176struct atmegadci_td; 177 178typedef uint8_t (atmegadci_cmd_t)(struct atmegadci_td *td); 179typedef void (atmegadci_clocks_t)(struct usb2_bus *); 180 181struct atmegadci_td { 182 struct atmegadci_td *obj_next; 183 atmegadci_cmd_t *func; 184 struct usb2_page_cache *pc; 185 uint32_t offset; 186 uint32_t remainder; 187 uint16_t max_packet_size; 188 uint8_t error:1; 189 uint8_t alt_next:1; 190 uint8_t short_pkt:1; 191 uint8_t support_multi_buffer:1; 192 uint8_t did_stall:1; 193 uint8_t ep_no:3; 194}; 195 196struct atmegadci_std_temp { 197 atmegadci_cmd_t *func; 198 struct usb2_page_cache *pc; 199 struct atmegadci_td *td; 200 struct atmegadci_td *td_next; 201 uint32_t len; 202 uint32_t offset; 203 uint16_t max_frame_size; 204 uint8_t short_pkt; 205 /* 206 * short_pkt = 0: transfer should be short terminated 207 * short_pkt = 1: transfer should not be short terminated 208 */ 209 uint8_t setup_alt_next; 210}; 211 212struct atmegadci_config_desc { 213 struct usb2_config_descriptor confd; 214 struct usb2_interface_descriptor ifcd; 215 struct usb2_endpoint_descriptor endpd; 216} __packed; 217 218union atmegadci_hub_temp { 219 uWord wValue; 220 struct usb2_port_status ps; 221}; 222 223struct atmegadci_flags { 224 uint8_t change_connect:1; 225 uint8_t change_suspend:1; 226 uint8_t status_suspend:1; /* set if suspended */ 227 uint8_t status_vbus:1; /* set if present */ 228 uint8_t status_bus_reset:1; /* set if reset complete */ 229 uint8_t remote_wakeup:1; 230 uint8_t self_powered:1; 231 uint8_t clocks_off:1; 232 uint8_t port_powered:1; 233 uint8_t port_enabled:1; 234 uint8_t d_pulled_up:1; 235}; 236 237struct atmegadci_softc { 238 struct usb2_bus sc_bus; 239 union atmegadci_hub_temp sc_hub_temp; 240 LIST_HEAD(, usb2_xfer) sc_interrupt_list_head; 241 struct usb2_sw_transfer sc_root_ctrl; 242 struct usb2_sw_transfer sc_root_intr; 243 244 /* must be set by by the bus interface layer */ 245 atmegadci_clocks_t *sc_clocks_on; 246 atmegadci_clocks_t *sc_clocks_off; 247 248 struct usb2_device *sc_devices[ATMEGA_MAX_DEVICES]; 249 struct resource *sc_irq_res; 250 void *sc_intr_hdl; 251#if (ATMEGA_HAVE_BUS_SPACE != 0) 252 struct resource *sc_io_res; 253 bus_space_tag_t sc_io_tag; 254 bus_space_handle_t sc_io_hdl; 255#endif 256 uint8_t sc_rt_addr; /* root hub address */ 257 uint8_t sc_dv_addr; /* device address */ 258 uint8_t sc_conf; /* root hub config */ 259 260 uint8_t sc_hub_idata[1]; 261 262 struct atmegadci_flags sc_flags; 263}; 264 265/* prototypes */ 266 267usb2_error_t atmegadci_init(struct atmegadci_softc *sc); 268void atmegadci_uninit(struct atmegadci_softc *sc); 269void atmegadci_suspend(struct atmegadci_softc *sc); 270void atmegadci_resume(struct atmegadci_softc *sc); 271void atmegadci_interrupt(struct atmegadci_softc *sc); 272 273#endif /* _ATMEGADCI_H_ */ 274