if_urtwn.c revision 302034
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2015 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#include <sys/cdefs.h> 22__FBSDID("$FreeBSD: head/sys/dev/urtwn/if_urtwn.c 302034 2016-06-20 22:39:32Z avos $"); 23 24/* 25 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 26 */ 27 28#include "opt_wlan.h" 29#include "opt_urtwn.h" 30 31#include <sys/param.h> 32#include <sys/sockio.h> 33#include <sys/sysctl.h> 34#include <sys/lock.h> 35#include <sys/mutex.h> 36#include <sys/condvar.h> 37#include <sys/mbuf.h> 38#include <sys/kernel.h> 39#include <sys/socket.h> 40#include <sys/systm.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/bus.h> 44#include <sys/endian.h> 45#include <sys/linker.h> 46#include <sys/firmware.h> 47#include <sys/kdb.h> 48 49#include <machine/bus.h> 50#include <machine/resource.h> 51#include <sys/rman.h> 52 53#include <net/bpf.h> 54#include <net/if.h> 55#include <net/if_var.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61 62#include <netinet/in.h> 63#include <netinet/in_systm.h> 64#include <netinet/in_var.h> 65#include <netinet/if_ether.h> 66#include <netinet/ip.h> 67 68#include <net80211/ieee80211_var.h> 69#include <net80211/ieee80211_regdomain.h> 70#include <net80211/ieee80211_radiotap.h> 71#include <net80211/ieee80211_ratectl.h> 72#ifdef IEEE80211_SUPPORT_SUPERG 73#include <net80211/ieee80211_superg.h> 74#endif 75 76#include <dev/usb/usb.h> 77#include <dev/usb/usbdi.h> 78#include <dev/usb/usb_device.h> 79#include "usbdevs.h" 80 81#include <dev/usb/usb_debug.h> 82 83#include <dev/urtwn/if_urtwnreg.h> 84#include <dev/urtwn/if_urtwnvar.h> 85 86#ifdef USB_DEBUG 87enum { 88 URTWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 89 URTWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 90 URTWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 91 URTWN_DEBUG_RA = 0x00000008, /* f/w rate adaptation setup */ 92 URTWN_DEBUG_USB = 0x00000010, /* usb requests */ 93 URTWN_DEBUG_FIRMWARE = 0x00000020, /* firmware(9) loading debug */ 94 URTWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 95 URTWN_DEBUG_INTR = 0x00000080, /* ISR */ 96 URTWN_DEBUG_TEMP = 0x00000100, /* temperature calibration */ 97 URTWN_DEBUG_ROM = 0x00000200, /* various ROM info */ 98 URTWN_DEBUG_KEY = 0x00000400, /* crypto keys management */ 99 URTWN_DEBUG_TXPWR = 0x00000800, /* dump Tx power values */ 100 URTWN_DEBUG_RSSI = 0x00001000, /* dump RSSI lookups */ 101 URTWN_DEBUG_ANY = 0xffffffff 102}; 103 104#define URTWN_DPRINTF(_sc, _m, ...) do { \ 105 if ((_sc)->sc_debug & (_m)) \ 106 device_printf((_sc)->sc_dev, __VA_ARGS__); \ 107} while(0) 108 109#else 110#define URTWN_DPRINTF(_sc, _m, ...) do { (void) sc; } while (0) 111#endif 112 113#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 114 115static int urtwn_enable_11n = 1; 116TUNABLE_INT("hw.usb.urtwn.enable_11n", &urtwn_enable_11n); 117 118/* various supported device vendors/products */ 119static const STRUCT_USB_HOST_ID urtwn_devs[] = { 120#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 121#define URTWN_RTL8188E_DEV(v,p) \ 122 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 123#define URTWN_RTL8188E 1 124 URTWN_DEV(ABOCOM, RTL8188CU_1), 125 URTWN_DEV(ABOCOM, RTL8188CU_2), 126 URTWN_DEV(ABOCOM, RTL8192CU), 127 URTWN_DEV(ASUS, RTL8192CU), 128 URTWN_DEV(ASUS, USBN10NANO), 129 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 130 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 131 URTWN_DEV(AZUREWAVE, RTL8188CU), 132 URTWN_DEV(BELKIN, F7D2102), 133 URTWN_DEV(BELKIN, RTL8188CU), 134 URTWN_DEV(BELKIN, RTL8192CU), 135 URTWN_DEV(CHICONY, RTL8188CUS_1), 136 URTWN_DEV(CHICONY, RTL8188CUS_2), 137 URTWN_DEV(CHICONY, RTL8188CUS_3), 138 URTWN_DEV(CHICONY, RTL8188CUS_4), 139 URTWN_DEV(CHICONY, RTL8188CUS_5), 140 URTWN_DEV(COREGA, RTL8192CU), 141 URTWN_DEV(DLINK, RTL8188CU), 142 URTWN_DEV(DLINK, RTL8192CU_1), 143 URTWN_DEV(DLINK, RTL8192CU_2), 144 URTWN_DEV(DLINK, RTL8192CU_3), 145 URTWN_DEV(DLINK, DWA131B), 146 URTWN_DEV(EDIMAX, EW7811UN), 147 URTWN_DEV(EDIMAX, RTL8192CU), 148 URTWN_DEV(FEIXUN, RTL8188CU), 149 URTWN_DEV(FEIXUN, RTL8192CU), 150 URTWN_DEV(GUILLEMOT, HWNUP150), 151 URTWN_DEV(HAWKING, RTL8192CU), 152 URTWN_DEV(HP3, RTL8188CU), 153 URTWN_DEV(NETGEAR, WNA1000M), 154 URTWN_DEV(NETGEAR, RTL8192CU), 155 URTWN_DEV(NETGEAR4, RTL8188CU), 156 URTWN_DEV(NOVATECH, RTL8188CU), 157 URTWN_DEV(PLANEX2, RTL8188CU_1), 158 URTWN_DEV(PLANEX2, RTL8188CU_2), 159 URTWN_DEV(PLANEX2, RTL8188CU_3), 160 URTWN_DEV(PLANEX2, RTL8188CU_4), 161 URTWN_DEV(PLANEX2, RTL8188CUS), 162 URTWN_DEV(PLANEX2, RTL8192CU), 163 URTWN_DEV(REALTEK, RTL8188CE_0), 164 URTWN_DEV(REALTEK, RTL8188CE_1), 165 URTWN_DEV(REALTEK, RTL8188CTV), 166 URTWN_DEV(REALTEK, RTL8188CU_0), 167 URTWN_DEV(REALTEK, RTL8188CU_1), 168 URTWN_DEV(REALTEK, RTL8188CU_2), 169 URTWN_DEV(REALTEK, RTL8188CU_3), 170 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 171 URTWN_DEV(REALTEK, RTL8188CUS), 172 URTWN_DEV(REALTEK, RTL8188RU_1), 173 URTWN_DEV(REALTEK, RTL8188RU_2), 174 URTWN_DEV(REALTEK, RTL8188RU_3), 175 URTWN_DEV(REALTEK, RTL8191CU), 176 URTWN_DEV(REALTEK, RTL8192CE), 177 URTWN_DEV(REALTEK, RTL8192CU), 178 URTWN_DEV(SITECOMEU, RTL8188CU_1), 179 URTWN_DEV(SITECOMEU, RTL8188CU_2), 180 URTWN_DEV(SITECOMEU, RTL8192CU), 181 URTWN_DEV(TRENDNET, RTL8188CU), 182 URTWN_DEV(TRENDNET, RTL8192CU), 183 URTWN_DEV(ZYXEL, RTL8192CU), 184 /* URTWN_RTL8188E */ 185 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 186 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 187 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 188 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 189 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 190 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 191#undef URTWN_RTL8188E_DEV 192#undef URTWN_DEV 193}; 194 195static device_probe_t urtwn_match; 196static device_attach_t urtwn_attach; 197static device_detach_t urtwn_detach; 198 199static usb_callback_t urtwn_bulk_tx_callback; 200static usb_callback_t urtwn_bulk_rx_callback; 201 202static void urtwn_sysctlattach(struct urtwn_softc *); 203static void urtwn_drain_mbufq(struct urtwn_softc *); 204static usb_error_t urtwn_do_request(struct urtwn_softc *, 205 struct usb_device_request *, void *); 206static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 207 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 208 const uint8_t [IEEE80211_ADDR_LEN], 209 const uint8_t [IEEE80211_ADDR_LEN]); 210static void urtwn_vap_delete(struct ieee80211vap *); 211static void urtwn_vap_clear_tx(struct urtwn_softc *, 212 struct ieee80211vap *); 213static void urtwn_vap_clear_tx_queue(struct urtwn_softc *, 214 urtwn_datahead *, struct ieee80211vap *); 215static struct mbuf * urtwn_rx_copy_to_mbuf(struct urtwn_softc *, 216 struct r92c_rx_stat *, int); 217static struct mbuf * urtwn_report_intr(struct usb_xfer *, 218 struct urtwn_data *); 219static struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int); 220static void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 221 void *); 222static struct ieee80211_node *urtwn_rx_frame(struct urtwn_softc *, 223 struct mbuf *, int8_t *); 224static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 225 int); 226static int urtwn_alloc_list(struct urtwn_softc *, 227 struct urtwn_data[], int, int); 228static int urtwn_alloc_rx_list(struct urtwn_softc *); 229static int urtwn_alloc_tx_list(struct urtwn_softc *); 230static void urtwn_free_list(struct urtwn_softc *, 231 struct urtwn_data data[], int); 232static void urtwn_free_rx_list(struct urtwn_softc *); 233static void urtwn_free_tx_list(struct urtwn_softc *); 234static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 235static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 236static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 237 uint8_t *, int); 238static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 239static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 240static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 241static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 242 uint8_t *, int); 243static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 244static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 245static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 246static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 247 const void *, int); 248static void urtwn_cmdq_cb(void *, int); 249static int urtwn_cmd_sleepable(struct urtwn_softc *, const void *, 250 size_t, CMD_FUNC_PROTO); 251static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 252 uint8_t, uint32_t); 253static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 254 uint8_t, uint32_t); 255static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 256static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 257 uint32_t); 258static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 259static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 260 uint8_t, uint8_t); 261#ifdef USB_DEBUG 262static void urtwn_dump_rom_contents(struct urtwn_softc *, 263 uint8_t *, uint16_t); 264#endif 265static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 266 uint16_t); 267static int urtwn_efuse_switch_power(struct urtwn_softc *); 268static int urtwn_read_chipid(struct urtwn_softc *); 269static int urtwn_read_rom(struct urtwn_softc *); 270static int urtwn_r88e_read_rom(struct urtwn_softc *); 271static int urtwn_ra_init(struct urtwn_softc *); 272static void urtwn_init_beacon(struct urtwn_softc *, 273 struct urtwn_vap *); 274static int urtwn_setup_beacon(struct urtwn_softc *, 275 struct ieee80211_node *); 276static void urtwn_update_beacon(struct ieee80211vap *, int); 277static int urtwn_tx_beacon(struct urtwn_softc *sc, 278 struct urtwn_vap *); 279static int urtwn_key_alloc(struct ieee80211vap *, 280 struct ieee80211_key *, ieee80211_keyix *, 281 ieee80211_keyix *); 282static void urtwn_key_set_cb(struct urtwn_softc *, 283 union sec_param *); 284static void urtwn_key_del_cb(struct urtwn_softc *, 285 union sec_param *); 286static int urtwn_key_set(struct ieee80211vap *, 287 const struct ieee80211_key *); 288static int urtwn_key_delete(struct ieee80211vap *, 289 const struct ieee80211_key *); 290static void urtwn_tsf_task_adhoc(void *, int); 291static void urtwn_tsf_sync_enable(struct urtwn_softc *, 292 struct ieee80211vap *); 293static void urtwn_get_tsf(struct urtwn_softc *, uint64_t *); 294static void urtwn_set_led(struct urtwn_softc *, int, int); 295static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 296static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 297 struct mbuf *, int, 298 const struct ieee80211_rx_stats *, int, int); 299static int urtwn_newstate(struct ieee80211vap *, 300 enum ieee80211_state, int); 301static void urtwn_calib_to(void *); 302static void urtwn_calib_cb(struct urtwn_softc *, 303 union sec_param *); 304static void urtwn_watchdog(void *); 305static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 306static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 307static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 308static int urtwn_tx_data(struct urtwn_softc *, 309 struct ieee80211_node *, struct mbuf *, 310 struct urtwn_data *); 311static int urtwn_tx_raw(struct urtwn_softc *, 312 struct ieee80211_node *, struct mbuf *, 313 struct urtwn_data *, 314 const struct ieee80211_bpf_params *); 315static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 316 uint8_t, struct urtwn_data *); 317static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 318static void urtwn_start(struct urtwn_softc *); 319static void urtwn_parent(struct ieee80211com *); 320static int urtwn_r92c_power_on(struct urtwn_softc *); 321static int urtwn_r88e_power_on(struct urtwn_softc *); 322static void urtwn_r92c_power_off(struct urtwn_softc *); 323static void urtwn_r88e_power_off(struct urtwn_softc *); 324static int urtwn_llt_init(struct urtwn_softc *); 325#ifndef URTWN_WITHOUT_UCODE 326static void urtwn_fw_reset(struct urtwn_softc *); 327static void urtwn_r88e_fw_reset(struct urtwn_softc *); 328static int urtwn_fw_loadpage(struct urtwn_softc *, int, 329 const uint8_t *, int); 330static int urtwn_load_firmware(struct urtwn_softc *); 331#endif 332static int urtwn_dma_init(struct urtwn_softc *); 333static int urtwn_mac_init(struct urtwn_softc *); 334static void urtwn_bb_init(struct urtwn_softc *); 335static void urtwn_rf_init(struct urtwn_softc *); 336static void urtwn_cam_init(struct urtwn_softc *); 337static int urtwn_cam_write(struct urtwn_softc *, uint32_t, 338 uint32_t); 339static void urtwn_pa_bias_init(struct urtwn_softc *); 340static void urtwn_rxfilter_init(struct urtwn_softc *); 341static void urtwn_edca_init(struct urtwn_softc *); 342static void urtwn_write_txpower(struct urtwn_softc *, int, 343 uint16_t[]); 344static void urtwn_get_txpower(struct urtwn_softc *, int, 345 struct ieee80211_channel *, 346 struct ieee80211_channel *, uint16_t[]); 347static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 348 struct ieee80211_channel *, 349 struct ieee80211_channel *, uint16_t[]); 350static void urtwn_set_txpower(struct urtwn_softc *, 351 struct ieee80211_channel *, 352 struct ieee80211_channel *); 353static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 354static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 355static void urtwn_scan_start(struct ieee80211com *); 356static void urtwn_scan_end(struct ieee80211com *); 357static void urtwn_getradiocaps(struct ieee80211com *, int, int *, 358 struct ieee80211_channel[]); 359static void urtwn_set_channel(struct ieee80211com *); 360static int urtwn_wme_update(struct ieee80211com *); 361static void urtwn_update_slot(struct ieee80211com *); 362static void urtwn_update_slot_cb(struct urtwn_softc *, 363 union sec_param *); 364static void urtwn_update_aifs(struct urtwn_softc *, uint8_t); 365static uint8_t urtwn_get_multi_pos(const uint8_t[]); 366static void urtwn_set_multi(struct urtwn_softc *); 367static void urtwn_set_promisc(struct urtwn_softc *); 368static void urtwn_update_promisc(struct ieee80211com *); 369static void urtwn_update_mcast(struct ieee80211com *); 370static struct ieee80211_node *urtwn_node_alloc(struct ieee80211vap *, 371 const uint8_t mac[IEEE80211_ADDR_LEN]); 372static void urtwn_newassoc(struct ieee80211_node *, int); 373static void urtwn_node_free(struct ieee80211_node *); 374static void urtwn_set_chan(struct urtwn_softc *, 375 struct ieee80211_channel *, 376 struct ieee80211_channel *); 377static void urtwn_iq_calib(struct urtwn_softc *); 378static void urtwn_lc_calib(struct urtwn_softc *); 379static void urtwn_temp_calib(struct urtwn_softc *); 380static void urtwn_setup_static_keys(struct urtwn_softc *, 381 struct urtwn_vap *); 382static int urtwn_init(struct urtwn_softc *); 383static void urtwn_stop(struct urtwn_softc *); 384static void urtwn_abort_xfers(struct urtwn_softc *); 385static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 386 const struct ieee80211_bpf_params *); 387static void urtwn_ms_delay(struct urtwn_softc *); 388 389/* Aliases. */ 390#define urtwn_bb_write urtwn_write_4 391#define urtwn_bb_read urtwn_read_4 392 393static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 394 [URTWN_BULK_RX] = { 395 .type = UE_BULK, 396 .endpoint = UE_ADDR_ANY, 397 .direction = UE_DIR_IN, 398 .bufsize = URTWN_RXBUFSZ, 399 .flags = { 400 .pipe_bof = 1, 401 .short_xfer_ok = 1 402 }, 403 .callback = urtwn_bulk_rx_callback, 404 }, 405 [URTWN_BULK_TX_BE] = { 406 .type = UE_BULK, 407 .endpoint = 0x03, 408 .direction = UE_DIR_OUT, 409 .bufsize = URTWN_TXBUFSZ, 410 .flags = { 411 .ext_buffer = 1, 412 .pipe_bof = 1, 413 .force_short_xfer = 1 414 }, 415 .callback = urtwn_bulk_tx_callback, 416 .timeout = URTWN_TX_TIMEOUT, /* ms */ 417 }, 418 [URTWN_BULK_TX_BK] = { 419 .type = UE_BULK, 420 .endpoint = 0x03, 421 .direction = UE_DIR_OUT, 422 .bufsize = URTWN_TXBUFSZ, 423 .flags = { 424 .ext_buffer = 1, 425 .pipe_bof = 1, 426 .force_short_xfer = 1, 427 }, 428 .callback = urtwn_bulk_tx_callback, 429 .timeout = URTWN_TX_TIMEOUT, /* ms */ 430 }, 431 [URTWN_BULK_TX_VI] = { 432 .type = UE_BULK, 433 .endpoint = 0x02, 434 .direction = UE_DIR_OUT, 435 .bufsize = URTWN_TXBUFSZ, 436 .flags = { 437 .ext_buffer = 1, 438 .pipe_bof = 1, 439 .force_short_xfer = 1 440 }, 441 .callback = urtwn_bulk_tx_callback, 442 .timeout = URTWN_TX_TIMEOUT, /* ms */ 443 }, 444 [URTWN_BULK_TX_VO] = { 445 .type = UE_BULK, 446 .endpoint = 0x02, 447 .direction = UE_DIR_OUT, 448 .bufsize = URTWN_TXBUFSZ, 449 .flags = { 450 .ext_buffer = 1, 451 .pipe_bof = 1, 452 .force_short_xfer = 1 453 }, 454 .callback = urtwn_bulk_tx_callback, 455 .timeout = URTWN_TX_TIMEOUT, /* ms */ 456 }, 457}; 458 459static const struct wme_to_queue { 460 uint16_t reg; 461 uint8_t qid; 462} wme2queue[WME_NUM_AC] = { 463 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 464 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 465 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 466 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 467}; 468 469static const uint8_t urtwn_chan_2ghz[] = 470 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 471 472static int 473urtwn_match(device_t self) 474{ 475 struct usb_attach_arg *uaa = device_get_ivars(self); 476 477 if (uaa->usb_mode != USB_MODE_HOST) 478 return (ENXIO); 479 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 480 return (ENXIO); 481 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 482 return (ENXIO); 483 484 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 485} 486 487static void 488urtwn_update_chw(struct ieee80211com *ic) 489{ 490} 491 492static int 493urtwn_ampdu_enable(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 494{ 495 496 /* We're driving this ourselves (eventually); don't involve net80211 */ 497 return (0); 498} 499 500static int 501urtwn_attach(device_t self) 502{ 503 struct usb_attach_arg *uaa = device_get_ivars(self); 504 struct urtwn_softc *sc = device_get_softc(self); 505 struct ieee80211com *ic = &sc->sc_ic; 506 int error; 507 508 device_set_usb_desc(self); 509 sc->sc_udev = uaa->device; 510 sc->sc_dev = self; 511 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 512 sc->chip |= URTWN_CHIP_88E; 513 514#ifdef USB_DEBUG 515 int debug; 516 if (resource_int_value(device_get_name(sc->sc_dev), 517 device_get_unit(sc->sc_dev), "debug", &debug) == 0) 518 sc->sc_debug = debug; 519#endif 520 521 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 522 MTX_NETWORK_LOCK, MTX_DEF); 523 URTWN_CMDQ_LOCK_INIT(sc); 524 URTWN_NT_LOCK_INIT(sc); 525 callout_init(&sc->sc_calib_to, 0); 526 callout_init(&sc->sc_watchdog_ch, 0); 527 mbufq_init(&sc->sc_snd, ifqmaxlen); 528 529 sc->sc_iface_index = URTWN_IFACE_INDEX; 530 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 531 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 532 if (error) { 533 device_printf(self, "could not allocate USB transfers, " 534 "err=%s\n", usbd_errstr(error)); 535 goto detach; 536 } 537 538 URTWN_LOCK(sc); 539 540 error = urtwn_read_chipid(sc); 541 if (error) { 542 device_printf(sc->sc_dev, "unsupported test chip\n"); 543 URTWN_UNLOCK(sc); 544 goto detach; 545 } 546 547 /* Determine number of Tx/Rx chains. */ 548 if (sc->chip & URTWN_CHIP_92C) { 549 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 550 sc->nrxchains = 2; 551 } else { 552 sc->ntxchains = 1; 553 sc->nrxchains = 1; 554 } 555 556 if (sc->chip & URTWN_CHIP_88E) 557 error = urtwn_r88e_read_rom(sc); 558 else 559 error = urtwn_read_rom(sc); 560 if (error != 0) { 561 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 562 __func__, error); 563 URTWN_UNLOCK(sc); 564 goto detach; 565 } 566 567 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 568 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 569 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 570 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 571 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 572 "8188CUS", sc->ntxchains, sc->nrxchains); 573 574 URTWN_UNLOCK(sc); 575 576 ic->ic_softc = sc; 577 ic->ic_name = device_get_nameunit(self); 578 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 579 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 580 581 /* set device capabilities */ 582 ic->ic_caps = 583 IEEE80211_C_STA /* station mode */ 584 | IEEE80211_C_MONITOR /* monitor mode */ 585 | IEEE80211_C_IBSS /* adhoc mode */ 586 | IEEE80211_C_HOSTAP /* hostap mode */ 587 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 588 | IEEE80211_C_SHSLOT /* short slot time supported */ 589#if 0 590 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 591#endif 592 | IEEE80211_C_WPA /* 802.11i */ 593 | IEEE80211_C_WME /* 802.11e */ 594 | IEEE80211_C_SWAMSDUTX /* Do software A-MSDU TX */ 595 | IEEE80211_C_FF /* Atheros fast-frames */ 596 ; 597 598 ic->ic_cryptocaps = 599 IEEE80211_CRYPTO_WEP | 600 IEEE80211_CRYPTO_TKIP | 601 IEEE80211_CRYPTO_AES_CCM; 602 603 /* Assume they're all 11n capable for now */ 604 if (urtwn_enable_11n) { 605 device_printf(self, "enabling 11n\n"); 606 ic->ic_htcaps = IEEE80211_HTC_HT | 607#if 0 608 IEEE80211_HTC_AMPDU | 609#endif 610 IEEE80211_HTC_AMSDU | 611 IEEE80211_HTCAP_MAXAMSDU_3839 | 612 IEEE80211_HTCAP_SMPS_OFF; 613 /* no HT40 just yet */ 614 // ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40; 615 616 /* XXX TODO: verify chains versus streams for urtwn */ 617 ic->ic_txstream = sc->ntxchains; 618 ic->ic_rxstream = sc->nrxchains; 619 } 620 621 /* XXX TODO: setup regdomain if R92C_CHANNEL_PLAN_BY_HW bit is set. */ 622 623 urtwn_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 624 ic->ic_channels); 625 626 ieee80211_ifattach(ic); 627 ic->ic_raw_xmit = urtwn_raw_xmit; 628 ic->ic_scan_start = urtwn_scan_start; 629 ic->ic_scan_end = urtwn_scan_end; 630 ic->ic_getradiocaps = urtwn_getradiocaps; 631 ic->ic_set_channel = urtwn_set_channel; 632 ic->ic_transmit = urtwn_transmit; 633 ic->ic_parent = urtwn_parent; 634 ic->ic_vap_create = urtwn_vap_create; 635 ic->ic_vap_delete = urtwn_vap_delete; 636 ic->ic_wme.wme_update = urtwn_wme_update; 637 ic->ic_updateslot = urtwn_update_slot; 638 ic->ic_update_promisc = urtwn_update_promisc; 639 ic->ic_update_mcast = urtwn_update_mcast; 640 if (sc->chip & URTWN_CHIP_88E) { 641 ic->ic_node_alloc = urtwn_node_alloc; 642 ic->ic_newassoc = urtwn_newassoc; 643 sc->sc_node_free = ic->ic_node_free; 644 ic->ic_node_free = urtwn_node_free; 645 } 646 ic->ic_update_chw = urtwn_update_chw; 647 ic->ic_ampdu_enable = urtwn_ampdu_enable; 648 649 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 650 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 651 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 652 URTWN_RX_RADIOTAP_PRESENT); 653 654 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc); 655 656 urtwn_sysctlattach(sc); 657 658 if (bootverbose) 659 ieee80211_announce(ic); 660 661 return (0); 662 663detach: 664 urtwn_detach(self); 665 return (ENXIO); /* failure */ 666} 667 668static void 669urtwn_sysctlattach(struct urtwn_softc *sc) 670{ 671#ifdef USB_DEBUG 672 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 673 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 674 675 SYSCTL_ADD_U32(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 676 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 677 "control debugging printfs"); 678#endif 679} 680 681static int 682urtwn_detach(device_t self) 683{ 684 struct urtwn_softc *sc = device_get_softc(self); 685 struct ieee80211com *ic = &sc->sc_ic; 686 unsigned int x; 687 688 /* Prevent further ioctls. */ 689 URTWN_LOCK(sc); 690 sc->sc_flags |= URTWN_DETACHED; 691 URTWN_UNLOCK(sc); 692 693 urtwn_stop(sc); 694 695 callout_drain(&sc->sc_watchdog_ch); 696 callout_drain(&sc->sc_calib_to); 697 698 /* stop all USB transfers */ 699 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 700 701 /* Prevent further allocations from RX/TX data lists. */ 702 URTWN_LOCK(sc); 703 STAILQ_INIT(&sc->sc_tx_active); 704 STAILQ_INIT(&sc->sc_tx_inactive); 705 STAILQ_INIT(&sc->sc_tx_pending); 706 707 STAILQ_INIT(&sc->sc_rx_active); 708 STAILQ_INIT(&sc->sc_rx_inactive); 709 URTWN_UNLOCK(sc); 710 711 /* drain USB transfers */ 712 for (x = 0; x != URTWN_N_TRANSFER; x++) 713 usbd_transfer_drain(sc->sc_xfer[x]); 714 715 /* Free data buffers. */ 716 URTWN_LOCK(sc); 717 urtwn_free_tx_list(sc); 718 urtwn_free_rx_list(sc); 719 URTWN_UNLOCK(sc); 720 721 if (ic->ic_softc == sc) { 722 ieee80211_draintask(ic, &sc->cmdq_task); 723 ieee80211_ifdetach(ic); 724 } 725 726 URTWN_NT_LOCK_DESTROY(sc); 727 URTWN_CMDQ_LOCK_DESTROY(sc); 728 mtx_destroy(&sc->sc_mtx); 729 730 return (0); 731} 732 733static void 734urtwn_drain_mbufq(struct urtwn_softc *sc) 735{ 736 struct mbuf *m; 737 struct ieee80211_node *ni; 738 URTWN_ASSERT_LOCKED(sc); 739 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 740 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 741 m->m_pkthdr.rcvif = NULL; 742 ieee80211_free_node(ni); 743 m_freem(m); 744 } 745} 746 747static usb_error_t 748urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 749 void *data) 750{ 751 usb_error_t err; 752 int ntries = 10; 753 754 URTWN_ASSERT_LOCKED(sc); 755 756 while (ntries--) { 757 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 758 req, data, 0, NULL, 250 /* ms */); 759 if (err == 0) 760 break; 761 762 URTWN_DPRINTF(sc, URTWN_DEBUG_USB, 763 "%s: control request failed, %s (retries left: %d)\n", 764 __func__, usbd_errstr(err), ntries); 765 usb_pause_mtx(&sc->sc_mtx, hz / 100); 766 } 767 return (err); 768} 769 770static struct ieee80211vap * 771urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 772 enum ieee80211_opmode opmode, int flags, 773 const uint8_t bssid[IEEE80211_ADDR_LEN], 774 const uint8_t mac[IEEE80211_ADDR_LEN]) 775{ 776 struct urtwn_softc *sc = ic->ic_softc; 777 struct urtwn_vap *uvp; 778 struct ieee80211vap *vap; 779 780 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 781 return (NULL); 782 783 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 784 vap = &uvp->vap; 785 /* enable s/w bmiss handling for sta mode */ 786 787 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 788 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 789 /* out of memory */ 790 free(uvp, M_80211_VAP); 791 return (NULL); 792 } 793 794 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 795 urtwn_init_beacon(sc, uvp); 796 797 /* override state transition machine */ 798 uvp->newstate = vap->iv_newstate; 799 vap->iv_newstate = urtwn_newstate; 800 vap->iv_update_beacon = urtwn_update_beacon; 801 vap->iv_key_alloc = urtwn_key_alloc; 802 vap->iv_key_set = urtwn_key_set; 803 vap->iv_key_delete = urtwn_key_delete; 804 805 /* 802.11n parameters */ 806 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_16; 807 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 808 809 if (opmode == IEEE80211_M_IBSS) { 810 uvp->recv_mgmt = vap->iv_recv_mgmt; 811 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 812 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 813 } 814 815 if (URTWN_CHIP_HAS_RATECTL(sc)) 816 ieee80211_ratectl_init(vap); 817 /* complete setup */ 818 ieee80211_vap_attach(vap, ieee80211_media_change, 819 ieee80211_media_status, mac); 820 ic->ic_opmode = opmode; 821 return (vap); 822} 823 824static void 825urtwn_vap_delete(struct ieee80211vap *vap) 826{ 827 struct ieee80211com *ic = vap->iv_ic; 828 struct urtwn_softc *sc = ic->ic_softc; 829 struct urtwn_vap *uvp = URTWN_VAP(vap); 830 831 /* Guarantee that nothing will go through this vap. */ 832 ieee80211_new_state(vap, IEEE80211_S_INIT, -1); 833 ieee80211_draintask(ic, &vap->iv_nstate_task); 834 835 URTWN_LOCK(sc); 836 if (uvp->bcn_mbuf != NULL) 837 m_freem(uvp->bcn_mbuf); 838 /* Cancel any unfinished Tx. */ 839 urtwn_vap_clear_tx(sc, vap); 840 URTWN_UNLOCK(sc); 841 if (vap->iv_opmode == IEEE80211_M_IBSS) 842 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 843 if (URTWN_CHIP_HAS_RATECTL(sc)) 844 ieee80211_ratectl_deinit(vap); 845 ieee80211_vap_detach(vap); 846 free(uvp, M_80211_VAP); 847} 848 849static void 850urtwn_vap_clear_tx(struct urtwn_softc *sc, struct ieee80211vap *vap) 851{ 852 853 URTWN_ASSERT_LOCKED(sc); 854 855 urtwn_vap_clear_tx_queue(sc, &sc->sc_tx_active, vap); 856 urtwn_vap_clear_tx_queue(sc, &sc->sc_tx_pending, vap); 857} 858 859static void 860urtwn_vap_clear_tx_queue(struct urtwn_softc *sc, urtwn_datahead *head, 861 struct ieee80211vap *vap) 862{ 863 struct urtwn_data *dp, *tmp; 864 865 STAILQ_FOREACH_SAFE(dp, head, next, tmp) { 866 if (dp->ni != NULL) { 867 if (dp->ni->ni_vap == vap) { 868 ieee80211_free_node(dp->ni); 869 dp->ni = NULL; 870 871 if (dp->m != NULL) { 872 m_freem(dp->m); 873 dp->m = NULL; 874 } 875 876 STAILQ_REMOVE(head, dp, urtwn_data, next); 877 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, dp, 878 next); 879 } 880 } 881 } 882} 883 884static struct mbuf * 885urtwn_rx_copy_to_mbuf(struct urtwn_softc *sc, struct r92c_rx_stat *stat, 886 int totlen) 887{ 888 struct ieee80211com *ic = &sc->sc_ic; 889 struct mbuf *m; 890 uint32_t rxdw0; 891 int pktlen; 892 893 /* 894 * don't pass packets to the ieee80211 framework if the driver isn't 895 * RUNNING. 896 */ 897 if (!(sc->sc_flags & URTWN_RUNNING)) 898 return (NULL); 899 900 rxdw0 = le32toh(stat->rxdw0); 901 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 902 /* 903 * This should not happen since we setup our Rx filter 904 * to not receive these frames. 905 */ 906 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 907 "%s: RX flags error (%s)\n", __func__, 908 rxdw0 & R92C_RXDW0_CRCERR ? "CRC" : "ICV"); 909 goto fail; 910 } 911 912 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 913 if (pktlen < sizeof(struct ieee80211_frame_ack)) { 914 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 915 "%s: frame is too short: %d\n", __func__, pktlen); 916 goto fail; 917 } 918 919 if (__predict_false(totlen > MCLBYTES)) { 920 /* convert to m_getjcl if this happens */ 921 device_printf(sc->sc_dev, "%s: frame too long: %d (%d)\n", 922 __func__, pktlen, totlen); 923 goto fail; 924 } 925 926 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 927 if (__predict_false(m == NULL)) { 928 device_printf(sc->sc_dev, "%s: could not allocate RX mbuf\n", 929 __func__); 930 goto fail; 931 } 932 933 /* Finalize mbuf. */ 934 memcpy(mtod(m, uint8_t *), (uint8_t *)stat, totlen); 935 m->m_pkthdr.len = m->m_len = totlen; 936 937 return (m); 938fail: 939 counter_u64_add(ic->ic_ierrors, 1); 940 return (NULL); 941} 942 943static struct mbuf * 944urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data) 945{ 946 struct urtwn_softc *sc = data->sc; 947 struct ieee80211com *ic = &sc->sc_ic; 948 struct r92c_rx_stat *stat; 949 uint8_t *buf; 950 int len; 951 952 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 953 954 if (len < sizeof(*stat)) { 955 counter_u64_add(ic->ic_ierrors, 1); 956 return (NULL); 957 } 958 959 buf = data->buf; 960 stat = (struct r92c_rx_stat *)buf; 961 962 /* 963 * For 88E chips we can tie the FF flushing here; 964 * this is where we do know exactly how deep the 965 * transmit queue is. 966 * 967 * But it won't work for R92 chips, so we can't 968 * take the easy way out. 969 */ 970 971 if (sc->chip & URTWN_CHIP_88E) { 972 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 973 974 switch (report_sel) { 975 case R88E_RXDW3_RPT_RX: 976 return (urtwn_rxeof(sc, buf, len)); 977 case R88E_RXDW3_RPT_TX1: 978 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 979 break; 980 default: 981 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, 982 "%s: case %d was not handled\n", __func__, 983 report_sel); 984 break; 985 } 986 } else 987 return (urtwn_rxeof(sc, buf, len)); 988 989 return (NULL); 990} 991 992static struct mbuf * 993urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len) 994{ 995 struct r92c_rx_stat *stat; 996 struct mbuf *m, *m0 = NULL, *prevm = NULL; 997 uint32_t rxdw0; 998 int totlen, pktlen, infosz, npkts; 999 1000 /* Get the number of encapsulated frames. */ 1001 stat = (struct r92c_rx_stat *)buf; 1002 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 1003 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 1004 "%s: Rx %d frames in one chunk\n", __func__, npkts); 1005 1006 /* Process all of them. */ 1007 while (npkts-- > 0) { 1008 if (len < sizeof(*stat)) 1009 break; 1010 stat = (struct r92c_rx_stat *)buf; 1011 rxdw0 = le32toh(stat->rxdw0); 1012 1013 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1014 if (pktlen == 0) 1015 break; 1016 1017 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1018 1019 /* Make sure everything fits in xfer. */ 1020 totlen = sizeof(*stat) + infosz + pktlen; 1021 if (totlen > len) 1022 break; 1023 1024 m = urtwn_rx_copy_to_mbuf(sc, stat, totlen); 1025 if (m0 == NULL) 1026 m0 = m; 1027 if (prevm == NULL) 1028 prevm = m; 1029 else { 1030 prevm->m_next = m; 1031 prevm = m; 1032 } 1033 1034 /* Next chunk is 128-byte aligned. */ 1035 totlen = (totlen + 127) & ~127; 1036 buf += totlen; 1037 len -= totlen; 1038 } 1039 1040 return (m0); 1041} 1042 1043static void 1044urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 1045{ 1046 struct r88e_tx_rpt_ccx *rpt = arg; 1047 struct ieee80211vap *vap; 1048 struct ieee80211_node *ni; 1049 uint8_t macid; 1050 int ntries; 1051 1052 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 1053 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 1054 1055 URTWN_NT_LOCK(sc); 1056 ni = sc->node_list[macid]; 1057 if (ni != NULL) { 1058 vap = ni->ni_vap; 1059 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: frame for macid %d was" 1060 "%s sent (%d retries)\n", __func__, macid, 1061 (rpt->rptb1 & R88E_RPTB1_PKT_OK) ? "" : " not", 1062 ntries); 1063 1064 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 1065 ieee80211_ratectl_tx_complete(vap, ni, 1066 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 1067 } else { 1068 ieee80211_ratectl_tx_complete(vap, ni, 1069 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 1070 } 1071 } else { 1072 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: macid %d, ni is NULL\n", 1073 __func__, macid); 1074 } 1075 URTWN_NT_UNLOCK(sc); 1076} 1077 1078static struct ieee80211_node * 1079urtwn_rx_frame(struct urtwn_softc *sc, struct mbuf *m, int8_t *rssi_p) 1080{ 1081 struct ieee80211com *ic = &sc->sc_ic; 1082 struct ieee80211_frame_min *wh; 1083 struct r92c_rx_stat *stat; 1084 uint32_t rxdw0, rxdw3; 1085 uint8_t rate, cipher; 1086 int8_t rssi = -127; 1087 int infosz; 1088 1089 stat = mtod(m, struct r92c_rx_stat *); 1090 rxdw0 = le32toh(stat->rxdw0); 1091 rxdw3 = le32toh(stat->rxdw3); 1092 1093 rate = MS(rxdw3, R92C_RXDW3_RATE); 1094 cipher = MS(rxdw0, R92C_RXDW0_CIPHER); 1095 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1096 1097 /* Get RSSI from PHY status descriptor if present. */ 1098 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1099 if (sc->chip & URTWN_CHIP_88E) 1100 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 1101 else 1102 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 1103 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: rssi=%d\n", __func__, rssi); 1104 /* Update our average RSSI. */ 1105 urtwn_update_avgrssi(sc, rate, rssi); 1106 } 1107 1108 if (ieee80211_radiotap_active(ic)) { 1109 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1110 1111 tap->wr_flags = 0; 1112 1113 urtwn_get_tsf(sc, &tap->wr_tsft); 1114 if (__predict_false(le32toh((uint32_t)tap->wr_tsft) < 1115 le32toh(stat->rxdw5))) { 1116 tap->wr_tsft = le32toh(tap->wr_tsft >> 32) - 1; 1117 tap->wr_tsft = (uint64_t)htole32(tap->wr_tsft) << 32; 1118 } else 1119 tap->wr_tsft &= 0xffffffff00000000; 1120 tap->wr_tsft += stat->rxdw5; 1121 1122 /* XXX 20/40? */ 1123 /* XXX shortgi? */ 1124 1125 /* Map HW rate index to 802.11 rate. */ 1126 if (!(rxdw3 & R92C_RXDW3_HT)) { 1127 tap->wr_rate = ridx2rate[rate]; 1128 } else if (rate >= 12) { /* MCS0~15. */ 1129 /* Bit 7 set means HT MCS instead of rate. */ 1130 tap->wr_rate = 0x80 | (rate - 12); 1131 } 1132 1133 /* XXX TODO: this isn't right; should use the last good RSSI */ 1134 tap->wr_dbm_antsignal = rssi; 1135 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 1136 } 1137 1138 *rssi_p = rssi; 1139 1140 /* Drop descriptor. */ 1141 m_adj(m, sizeof(*stat) + infosz); 1142 wh = mtod(m, struct ieee80211_frame_min *); 1143 1144 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1145 cipher != R92C_CAM_ALGO_NONE) { 1146 m->m_flags |= M_WEP; 1147 } 1148 1149 if (m->m_len >= sizeof(*wh)) 1150 return (ieee80211_find_rxnode(ic, wh)); 1151 1152 return (NULL); 1153} 1154 1155static void 1156urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 1157{ 1158 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1159 struct ieee80211com *ic = &sc->sc_ic; 1160 struct ieee80211_node *ni; 1161 struct mbuf *m = NULL, *next; 1162 struct urtwn_data *data; 1163 int8_t nf, rssi; 1164 1165 URTWN_ASSERT_LOCKED(sc); 1166 1167 switch (USB_GET_STATE(xfer)) { 1168 case USB_ST_TRANSFERRED: 1169 data = STAILQ_FIRST(&sc->sc_rx_active); 1170 if (data == NULL) 1171 goto tr_setup; 1172 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1173 m = urtwn_report_intr(xfer, data); 1174 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1175 /* FALLTHROUGH */ 1176 case USB_ST_SETUP: 1177tr_setup: 1178 data = STAILQ_FIRST(&sc->sc_rx_inactive); 1179 if (data == NULL) { 1180 KASSERT(m == NULL, ("mbuf isn't NULL")); 1181 goto finish; 1182 } 1183 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 1184 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 1185 usbd_xfer_set_frame_data(xfer, 0, data->buf, 1186 usbd_xfer_max_len(xfer)); 1187 usbd_transfer_submit(xfer); 1188 1189 /* 1190 * To avoid LOR we should unlock our private mutex here to call 1191 * ieee80211_input() because here is at the end of a USB 1192 * callback and safe to unlock. 1193 */ 1194 while (m != NULL) { 1195 next = m->m_next; 1196 m->m_next = NULL; 1197 1198 ni = urtwn_rx_frame(sc, m, &rssi); 1199 1200 /* Store a global last-good RSSI */ 1201 if (rssi != -127) 1202 sc->last_rssi = rssi; 1203 1204 URTWN_UNLOCK(sc); 1205 1206 nf = URTWN_NOISE_FLOOR; 1207 if (ni != NULL) { 1208 if (rssi != -127) 1209 URTWN_NODE(ni)->last_rssi = rssi; 1210 if (ni->ni_flags & IEEE80211_NODE_HT) 1211 m->m_flags |= M_AMPDU; 1212 (void)ieee80211_input(ni, m, 1213 URTWN_NODE(ni)->last_rssi - nf, nf); 1214 ieee80211_free_node(ni); 1215 } else { 1216 /* Use last good global RSSI */ 1217 (void)ieee80211_input_all(ic, m, 1218 sc->last_rssi - nf, nf); 1219 } 1220 URTWN_LOCK(sc); 1221 m = next; 1222 } 1223 break; 1224 default: 1225 /* needs it to the inactive queue due to a error. */ 1226 data = STAILQ_FIRST(&sc->sc_rx_active); 1227 if (data != NULL) { 1228 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1229 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1230 } 1231 if (error != USB_ERR_CANCELLED) { 1232 usbd_xfer_set_stall(xfer); 1233 counter_u64_add(ic->ic_ierrors, 1); 1234 goto tr_setup; 1235 } 1236 break; 1237 } 1238finish: 1239 /* Finished receive; age anything left on the FF queue by a little bump */ 1240 /* 1241 * XXX TODO: just make this a callout timer schedule so we can 1242 * flush the FF staging queue if we're approaching idle. 1243 */ 1244#ifdef IEEE80211_SUPPORT_SUPERG 1245 URTWN_UNLOCK(sc); 1246 ieee80211_ff_age_all(ic, 1); 1247 URTWN_LOCK(sc); 1248#endif 1249 1250 /* Kick-start more transmit in case we stalled */ 1251 urtwn_start(sc); 1252} 1253 1254static void 1255urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 1256{ 1257 1258 URTWN_ASSERT_LOCKED(sc); 1259 1260 if (data->ni != NULL) /* not a beacon frame */ 1261 ieee80211_tx_complete(data->ni, data->m, status); 1262 1263 if (sc->sc_tx_n_active > 0) 1264 sc->sc_tx_n_active--; 1265 1266 data->ni = NULL; 1267 data->m = NULL; 1268 1269 sc->sc_txtimer = 0; 1270 1271 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 1272} 1273 1274static int 1275urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1276 int ndata, int maxsz) 1277{ 1278 int i, error; 1279 1280 for (i = 0; i < ndata; i++) { 1281 struct urtwn_data *dp = &data[i]; 1282 dp->sc = sc; 1283 dp->m = NULL; 1284 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1285 if (dp->buf == NULL) { 1286 device_printf(sc->sc_dev, 1287 "could not allocate buffer\n"); 1288 error = ENOMEM; 1289 goto fail; 1290 } 1291 dp->ni = NULL; 1292 } 1293 1294 return (0); 1295fail: 1296 urtwn_free_list(sc, data, ndata); 1297 return (error); 1298} 1299 1300static int 1301urtwn_alloc_rx_list(struct urtwn_softc *sc) 1302{ 1303 int error, i; 1304 1305 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1306 URTWN_RXBUFSZ); 1307 if (error != 0) 1308 return (error); 1309 1310 STAILQ_INIT(&sc->sc_rx_active); 1311 STAILQ_INIT(&sc->sc_rx_inactive); 1312 1313 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1314 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1315 1316 return (0); 1317} 1318 1319static int 1320urtwn_alloc_tx_list(struct urtwn_softc *sc) 1321{ 1322 int error, i; 1323 1324 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1325 URTWN_TXBUFSZ); 1326 if (error != 0) 1327 return (error); 1328 1329 STAILQ_INIT(&sc->sc_tx_active); 1330 STAILQ_INIT(&sc->sc_tx_inactive); 1331 STAILQ_INIT(&sc->sc_tx_pending); 1332 1333 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1334 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1335 1336 return (0); 1337} 1338 1339static void 1340urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1341{ 1342 int i; 1343 1344 for (i = 0; i < ndata; i++) { 1345 struct urtwn_data *dp = &data[i]; 1346 1347 if (dp->buf != NULL) { 1348 free(dp->buf, M_USBDEV); 1349 dp->buf = NULL; 1350 } 1351 if (dp->ni != NULL) { 1352 ieee80211_free_node(dp->ni); 1353 dp->ni = NULL; 1354 } 1355 } 1356} 1357 1358static void 1359urtwn_free_rx_list(struct urtwn_softc *sc) 1360{ 1361 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1362} 1363 1364static void 1365urtwn_free_tx_list(struct urtwn_softc *sc) 1366{ 1367 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1368} 1369 1370static void 1371urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1372{ 1373 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1374#ifdef IEEE80211_SUPPORT_SUPERG 1375 struct ieee80211com *ic = &sc->sc_ic; 1376#endif 1377 struct urtwn_data *data; 1378 1379 URTWN_ASSERT_LOCKED(sc); 1380 1381 switch (USB_GET_STATE(xfer)){ 1382 case USB_ST_TRANSFERRED: 1383 data = STAILQ_FIRST(&sc->sc_tx_active); 1384 if (data == NULL) 1385 goto tr_setup; 1386 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1387 urtwn_txeof(sc, data, 0); 1388 /* FALLTHROUGH */ 1389 case USB_ST_SETUP: 1390tr_setup: 1391 data = STAILQ_FIRST(&sc->sc_tx_pending); 1392 if (data == NULL) { 1393 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1394 "%s: empty pending queue\n", __func__); 1395 sc->sc_tx_n_active = 0; 1396 goto finish; 1397 } 1398 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1399 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1400 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1401 usbd_transfer_submit(xfer); 1402 sc->sc_tx_n_active++; 1403 break; 1404 default: 1405 data = STAILQ_FIRST(&sc->sc_tx_active); 1406 if (data == NULL) 1407 goto tr_setup; 1408 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1409 urtwn_txeof(sc, data, 1); 1410 if (error != USB_ERR_CANCELLED) { 1411 usbd_xfer_set_stall(xfer); 1412 goto tr_setup; 1413 } 1414 break; 1415 } 1416finish: 1417#ifdef IEEE80211_SUPPORT_SUPERG 1418 /* 1419 * If the TX active queue drops below a certain 1420 * threshold, ensure we age fast-frames out so they're 1421 * transmitted. 1422 */ 1423 if (sc->sc_tx_n_active <= 1) { 1424 /* XXX ew - net80211 should defer this for us! */ 1425 1426 /* 1427 * Note: this sc_tx_n_active currently tracks 1428 * the number of pending transmit submissions 1429 * and not the actual depth of the TX frames 1430 * pending to the hardware. That means that 1431 * we're going to end up with some sub-optimal 1432 * aggregation behaviour. 1433 */ 1434 /* 1435 * XXX TODO: just make this a callout timer schedule so we can 1436 * flush the FF staging queue if we're approaching idle. 1437 */ 1438 URTWN_UNLOCK(sc); 1439 ieee80211_ff_flush(ic, WME_AC_VO); 1440 ieee80211_ff_flush(ic, WME_AC_VI); 1441 ieee80211_ff_flush(ic, WME_AC_BE); 1442 ieee80211_ff_flush(ic, WME_AC_BK); 1443 URTWN_LOCK(sc); 1444 } 1445#endif 1446 /* Kick-start more transmit */ 1447 urtwn_start(sc); 1448} 1449 1450static struct urtwn_data * 1451_urtwn_getbuf(struct urtwn_softc *sc) 1452{ 1453 struct urtwn_data *bf; 1454 1455 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1456 if (bf != NULL) 1457 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1458 else { 1459 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1460 "%s: out of xmit buffers\n", __func__); 1461 } 1462 return (bf); 1463} 1464 1465static struct urtwn_data * 1466urtwn_getbuf(struct urtwn_softc *sc) 1467{ 1468 struct urtwn_data *bf; 1469 1470 URTWN_ASSERT_LOCKED(sc); 1471 1472 bf = _urtwn_getbuf(sc); 1473 if (bf == NULL) { 1474 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: stop queue\n", 1475 __func__); 1476 } 1477 return (bf); 1478} 1479 1480static usb_error_t 1481urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1482 int len) 1483{ 1484 usb_device_request_t req; 1485 1486 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1487 req.bRequest = R92C_REQ_REGS; 1488 USETW(req.wValue, addr); 1489 USETW(req.wIndex, 0); 1490 USETW(req.wLength, len); 1491 return (urtwn_do_request(sc, &req, buf)); 1492} 1493 1494static usb_error_t 1495urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1496{ 1497 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1498} 1499 1500static usb_error_t 1501urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1502{ 1503 val = htole16(val); 1504 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1505} 1506 1507static usb_error_t 1508urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1509{ 1510 val = htole32(val); 1511 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1512} 1513 1514static usb_error_t 1515urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1516 int len) 1517{ 1518 usb_device_request_t req; 1519 1520 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1521 req.bRequest = R92C_REQ_REGS; 1522 USETW(req.wValue, addr); 1523 USETW(req.wIndex, 0); 1524 USETW(req.wLength, len); 1525 return (urtwn_do_request(sc, &req, buf)); 1526} 1527 1528static uint8_t 1529urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1530{ 1531 uint8_t val; 1532 1533 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1534 return (0xff); 1535 return (val); 1536} 1537 1538static uint16_t 1539urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1540{ 1541 uint16_t val; 1542 1543 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1544 return (0xffff); 1545 return (le16toh(val)); 1546} 1547 1548static uint32_t 1549urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1550{ 1551 uint32_t val; 1552 1553 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1554 return (0xffffffff); 1555 return (le32toh(val)); 1556} 1557 1558static int 1559urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1560{ 1561 struct r92c_fw_cmd cmd; 1562 usb_error_t error; 1563 int ntries; 1564 1565 if (!(sc->sc_flags & URTWN_FW_LOADED)) { 1566 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, "%s: firmware " 1567 "was not loaded; command (id %d) will be discarded\n", 1568 __func__, id); 1569 return (0); 1570 } 1571 1572 /* Wait for current FW box to be empty. */ 1573 for (ntries = 0; ntries < 100; ntries++) { 1574 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1575 break; 1576 urtwn_ms_delay(sc); 1577 } 1578 if (ntries == 100) { 1579 device_printf(sc->sc_dev, 1580 "could not send firmware command\n"); 1581 return (ETIMEDOUT); 1582 } 1583 memset(&cmd, 0, sizeof(cmd)); 1584 cmd.id = id; 1585 if (len > 3) 1586 cmd.id |= R92C_CMD_FLAG_EXT; 1587 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1588 memcpy(cmd.msg, buf, len); 1589 1590 /* Write the first word last since that will trigger the FW. */ 1591 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1592 (uint8_t *)&cmd + 4, 2); 1593 if (error != USB_ERR_NORMAL_COMPLETION) 1594 return (EIO); 1595 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1596 (uint8_t *)&cmd + 0, 4); 1597 if (error != USB_ERR_NORMAL_COMPLETION) 1598 return (EIO); 1599 1600 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1601 return (0); 1602} 1603 1604static void 1605urtwn_cmdq_cb(void *arg, int pending) 1606{ 1607 struct urtwn_softc *sc = arg; 1608 struct urtwn_cmdq *item; 1609 1610 /* 1611 * Device must be powered on (via urtwn_power_on()) 1612 * before any command may be sent. 1613 */ 1614 URTWN_LOCK(sc); 1615 if (!(sc->sc_flags & URTWN_RUNNING)) { 1616 URTWN_UNLOCK(sc); 1617 return; 1618 } 1619 1620 URTWN_CMDQ_LOCK(sc); 1621 while (sc->cmdq[sc->cmdq_first].func != NULL) { 1622 item = &sc->cmdq[sc->cmdq_first]; 1623 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE; 1624 URTWN_CMDQ_UNLOCK(sc); 1625 1626 item->func(sc, &item->data); 1627 1628 URTWN_CMDQ_LOCK(sc); 1629 memset(item, 0, sizeof (*item)); 1630 } 1631 URTWN_CMDQ_UNLOCK(sc); 1632 URTWN_UNLOCK(sc); 1633} 1634 1635static int 1636urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len, 1637 CMD_FUNC_PROTO) 1638{ 1639 struct ieee80211com *ic = &sc->sc_ic; 1640 1641 KASSERT(len <= sizeof(union sec_param), ("buffer overflow")); 1642 1643 URTWN_CMDQ_LOCK(sc); 1644 if (sc->cmdq[sc->cmdq_last].func != NULL) { 1645 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__); 1646 URTWN_CMDQ_UNLOCK(sc); 1647 1648 return (EAGAIN); 1649 } 1650 1651 if (ptr != NULL) 1652 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len); 1653 sc->cmdq[sc->cmdq_last].func = func; 1654 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE; 1655 URTWN_CMDQ_UNLOCK(sc); 1656 1657 ieee80211_runtask(ic, &sc->cmdq_task); 1658 1659 return (0); 1660} 1661 1662static __inline void 1663urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1664{ 1665 1666 sc->sc_rf_write(sc, chain, addr, val); 1667} 1668 1669static void 1670urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1671 uint32_t val) 1672{ 1673 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1674 SM(R92C_LSSI_PARAM_ADDR, addr) | 1675 SM(R92C_LSSI_PARAM_DATA, val)); 1676} 1677 1678static void 1679urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1680uint32_t val) 1681{ 1682 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1683 SM(R88E_LSSI_PARAM_ADDR, addr) | 1684 SM(R92C_LSSI_PARAM_DATA, val)); 1685} 1686 1687static uint32_t 1688urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1689{ 1690 uint32_t reg[R92C_MAX_CHAINS], val; 1691 1692 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1693 if (chain != 0) 1694 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1695 1696 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1697 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1698 urtwn_ms_delay(sc); 1699 1700 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1701 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1702 R92C_HSSI_PARAM2_READ_EDGE); 1703 urtwn_ms_delay(sc); 1704 1705 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1706 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1707 urtwn_ms_delay(sc); 1708 1709 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1710 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1711 else 1712 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1713 return (MS(val, R92C_LSSI_READBACK_DATA)); 1714} 1715 1716static int 1717urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1718{ 1719 usb_error_t error; 1720 int ntries; 1721 1722 error = urtwn_write_4(sc, R92C_LLT_INIT, 1723 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1724 SM(R92C_LLT_INIT_ADDR, addr) | 1725 SM(R92C_LLT_INIT_DATA, data)); 1726 if (error != USB_ERR_NORMAL_COMPLETION) 1727 return (EIO); 1728 /* Wait for write operation to complete. */ 1729 for (ntries = 0; ntries < 20; ntries++) { 1730 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1731 R92C_LLT_INIT_OP_NO_ACTIVE) 1732 return (0); 1733 urtwn_ms_delay(sc); 1734 } 1735 return (ETIMEDOUT); 1736} 1737 1738static int 1739urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1740{ 1741 uint32_t reg; 1742 usb_error_t error; 1743 int ntries; 1744 1745 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1746 return (EFAULT); 1747 1748 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1749 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1750 reg &= ~R92C_EFUSE_CTRL_VALID; 1751 1752 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1753 if (error != USB_ERR_NORMAL_COMPLETION) 1754 return (EIO); 1755 /* Wait for read operation to complete. */ 1756 for (ntries = 0; ntries < 100; ntries++) { 1757 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1758 if (reg & R92C_EFUSE_CTRL_VALID) 1759 break; 1760 urtwn_ms_delay(sc); 1761 } 1762 if (ntries == 100) { 1763 device_printf(sc->sc_dev, 1764 "could not read efuse byte at address 0x%x\n", 1765 sc->last_rom_addr); 1766 return (ETIMEDOUT); 1767 } 1768 1769 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1770 sc->last_rom_addr++; 1771 1772 return (0); 1773} 1774 1775static int 1776urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1777 uint8_t msk) 1778{ 1779 uint8_t reg; 1780 int i, error; 1781 1782 for (i = 0; i < 4; i++) { 1783 if (msk & (1 << i)) 1784 continue; 1785 error = urtwn_efuse_read_next(sc, ®); 1786 if (error != 0) 1787 return (error); 1788 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1789 off * 8 + i * 2, reg); 1790 rom[off * 8 + i * 2 + 0] = reg; 1791 1792 error = urtwn_efuse_read_next(sc, ®); 1793 if (error != 0) 1794 return (error); 1795 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1796 off * 8 + i * 2 + 1, reg); 1797 rom[off * 8 + i * 2 + 1] = reg; 1798 } 1799 1800 return (0); 1801} 1802 1803#ifdef USB_DEBUG 1804static void 1805urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1806{ 1807 int i; 1808 1809 /* Dump ROM contents. */ 1810 device_printf(sc->sc_dev, "%s:", __func__); 1811 for (i = 0; i < size; i++) { 1812 if (i % 32 == 0) 1813 printf("\n%03X: ", i); 1814 else if (i % 4 == 0) 1815 printf(" "); 1816 1817 printf("%02X", rom[i]); 1818 } 1819 printf("\n"); 1820} 1821#endif 1822 1823static int 1824urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1825{ 1826#define URTWN_CHK(res) do { \ 1827 if ((error = res) != 0) \ 1828 goto end; \ 1829} while(0) 1830 uint8_t msk, off, reg; 1831 int error; 1832 1833 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1834 1835 /* Read full ROM image. */ 1836 sc->last_rom_addr = 0; 1837 memset(rom, 0xff, size); 1838 1839 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1840 while (reg != 0xff) { 1841 /* check for extended header */ 1842 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1843 off = reg >> 5; 1844 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1845 1846 if ((reg & 0x0f) != 0x0f) 1847 off = ((reg & 0xf0) >> 1) | off; 1848 else 1849 continue; 1850 } else 1851 off = reg >> 4; 1852 msk = reg & 0xf; 1853 1854 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1855 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1856 } 1857 1858end: 1859 1860#ifdef USB_DEBUG 1861 if (sc->sc_debug & URTWN_DEBUG_ROM) 1862 urtwn_dump_rom_contents(sc, rom, size); 1863#endif 1864 1865 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1866 1867 if (error != 0) { 1868 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1869 __func__); 1870 } 1871 1872 return (error); 1873#undef URTWN_CHK 1874} 1875 1876static int 1877urtwn_efuse_switch_power(struct urtwn_softc *sc) 1878{ 1879 usb_error_t error; 1880 uint32_t reg; 1881 1882 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1883 if (error != USB_ERR_NORMAL_COMPLETION) 1884 return (EIO); 1885 1886 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1887 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1888 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1889 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1890 if (error != USB_ERR_NORMAL_COMPLETION) 1891 return (EIO); 1892 } 1893 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1894 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1895 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1896 reg | R92C_SYS_FUNC_EN_ELDR); 1897 if (error != USB_ERR_NORMAL_COMPLETION) 1898 return (EIO); 1899 } 1900 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1901 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1902 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1903 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1904 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1905 if (error != USB_ERR_NORMAL_COMPLETION) 1906 return (EIO); 1907 } 1908 1909 return (0); 1910} 1911 1912static int 1913urtwn_read_chipid(struct urtwn_softc *sc) 1914{ 1915 uint32_t reg; 1916 1917 if (sc->chip & URTWN_CHIP_88E) 1918 return (0); 1919 1920 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1921 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1922 return (EIO); 1923 1924 if (reg & R92C_SYS_CFG_TYPE_92C) { 1925 sc->chip |= URTWN_CHIP_92C; 1926 /* Check if it is a castrated 8192C. */ 1927 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1928 R92C_HPON_FSM_CHIP_BONDING_ID) == 1929 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1930 sc->chip |= URTWN_CHIP_92C_1T2R; 1931 } 1932 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1933 sc->chip |= URTWN_CHIP_UMC; 1934 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1935 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1936 } 1937 return (0); 1938} 1939 1940static int 1941urtwn_read_rom(struct urtwn_softc *sc) 1942{ 1943 struct r92c_rom *rom = &sc->rom.r92c_rom; 1944 int error; 1945 1946 /* Read full ROM image. */ 1947 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1948 if (error != 0) 1949 return (error); 1950 1951 /* XXX Weird but this is what the vendor driver does. */ 1952 sc->last_rom_addr = 0x1fa; 1953 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1954 if (error != 0) 1955 return (error); 1956 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: PA setting=0x%x\n", __func__, 1957 sc->pa_setting); 1958 1959 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1960 1961 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1962 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type=%d\n", 1963 __func__, sc->regulatory); 1964 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1965 1966 sc->sc_rf_write = urtwn_r92c_rf_write; 1967 sc->sc_power_on = urtwn_r92c_power_on; 1968 sc->sc_power_off = urtwn_r92c_power_off; 1969 1970 return (0); 1971} 1972 1973static int 1974urtwn_r88e_read_rom(struct urtwn_softc *sc) 1975{ 1976 struct r88e_rom *rom = &sc->rom.r88e_rom; 1977 int error; 1978 1979 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(sc->rom.r88e_rom)); 1980 if (error != 0) 1981 return (error); 1982 1983 sc->bw20_tx_pwr_diff = (rom->tx_pwr_diff >> 4); 1984 if (sc->bw20_tx_pwr_diff & 0x08) 1985 sc->bw20_tx_pwr_diff |= 0xf0; 1986 sc->ofdm_tx_pwr_diff = (rom->tx_pwr_diff & 0xf); 1987 if (sc->ofdm_tx_pwr_diff & 0x08) 1988 sc->ofdm_tx_pwr_diff |= 0xf0; 1989 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 1990 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type %d\n", 1991 __func__,sc->regulatory); 1992 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1993 1994 sc->sc_rf_write = urtwn_r88e_rf_write; 1995 sc->sc_power_on = urtwn_r88e_power_on; 1996 sc->sc_power_off = urtwn_r88e_power_off; 1997 1998 return (0); 1999} 2000 2001static __inline uint8_t 2002rate2ridx(uint8_t rate) 2003{ 2004 if (rate & IEEE80211_RATE_MCS) { 2005 /* 11n rates start at idx 12 */ 2006 return ((rate & 0xf) + 12); 2007 } 2008 switch (rate) { 2009 /* 11g */ 2010 case 12: return 4; 2011 case 18: return 5; 2012 case 24: return 6; 2013 case 36: return 7; 2014 case 48: return 8; 2015 case 72: return 9; 2016 case 96: return 10; 2017 case 108: return 11; 2018 /* 11b */ 2019 case 2: return 0; 2020 case 4: return 1; 2021 case 11: return 2; 2022 case 22: return 3; 2023 default: return URTWN_RIDX_UNKNOWN; 2024 } 2025} 2026 2027/* 2028 * Initialize rate adaptation in firmware. 2029 */ 2030static int 2031urtwn_ra_init(struct urtwn_softc *sc) 2032{ 2033 struct ieee80211com *ic = &sc->sc_ic; 2034 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2035 struct ieee80211_node *ni; 2036 struct ieee80211_rateset *rs, *rs_ht; 2037 struct r92c_fw_cmd_macid_cfg cmd; 2038 uint32_t rates, basicrates; 2039 uint8_t mode, ridx; 2040 int maxrate, maxbasicrate, error, i; 2041 2042 ni = ieee80211_ref_node(vap->iv_bss); 2043 rs = &ni->ni_rates; 2044 rs_ht = (struct ieee80211_rateset *) &ni->ni_htrates; 2045 2046 /* Get normal and basic rates mask. */ 2047 rates = basicrates = 0; 2048 maxrate = maxbasicrate = 0; 2049 2050 /* This is for 11bg */ 2051 for (i = 0; i < rs->rs_nrates; i++) { 2052 /* Convert 802.11 rate to HW rate index. */ 2053 ridx = rate2ridx(IEEE80211_RV(rs->rs_rates[i])); 2054 if (ridx == URTWN_RIDX_UNKNOWN) /* Unknown rate, skip. */ 2055 continue; 2056 rates |= 1 << ridx; 2057 if (ridx > maxrate) 2058 maxrate = ridx; 2059 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 2060 basicrates |= 1 << ridx; 2061 if (ridx > maxbasicrate) 2062 maxbasicrate = ridx; 2063 } 2064 } 2065 2066 /* If we're doing 11n, enable 11n rates */ 2067 if (ni->ni_flags & IEEE80211_NODE_HT) { 2068 for (i = 0; i < rs_ht->rs_nrates; i++) { 2069 if ((rs_ht->rs_rates[i] & 0x7f) > 0xf) 2070 continue; 2071 /* 11n rates start at index 12 */ 2072 ridx = ((rs_ht->rs_rates[i]) & 0xf) + 12; 2073 rates |= (1 << ridx); 2074 2075 /* Guard against the rate table being oddly ordered */ 2076 if (ridx > maxrate) 2077 maxrate = ridx; 2078 } 2079 } 2080 2081#if 0 2082 if (ic->ic_curmode == IEEE80211_MODE_11NG) 2083 raid = R92C_RAID_11GN; 2084#endif 2085 /* NB: group addressed frames are done at 11bg rates for now */ 2086 if (ic->ic_curmode == IEEE80211_MODE_11B) 2087 mode = R92C_RAID_11B; 2088 else 2089 mode = R92C_RAID_11BG; 2090 /* XXX misleading 'mode' value here for unicast frames */ 2091 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, 2092 "%s: mode 0x%x, rates 0x%08x, basicrates 0x%08x\n", __func__, 2093 mode, rates, basicrates); 2094 2095 /* Set rates mask for group addressed frames. */ 2096 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 2097 cmd.mask = htole32(mode << 28 | basicrates); 2098 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 2099 if (error != 0) { 2100 ieee80211_free_node(ni); 2101 device_printf(sc->sc_dev, 2102 "could not add broadcast station\n"); 2103 return (error); 2104 } 2105 2106 /* Set initial MRR rate. */ 2107 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxbasicrate %d\n", __func__, 2108 maxbasicrate); 2109 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 2110 maxbasicrate); 2111 2112 /* Set rates mask for unicast frames. */ 2113 if (ni->ni_flags & IEEE80211_NODE_HT) 2114 mode = R92C_RAID_11GN; 2115 else if (ic->ic_curmode == IEEE80211_MODE_11B) 2116 mode = R92C_RAID_11B; 2117 else 2118 mode = R92C_RAID_11BG; 2119 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 2120 cmd.mask = htole32(mode << 28 | rates); 2121 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 2122 if (error != 0) { 2123 ieee80211_free_node(ni); 2124 device_printf(sc->sc_dev, "could not add BSS station\n"); 2125 return (error); 2126 } 2127 /* Set initial MRR rate. */ 2128 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxrate %d\n", __func__, 2129 maxrate); 2130 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 2131 maxrate); 2132 2133 /* Indicate highest supported rate. */ 2134 if (ni->ni_flags & IEEE80211_NODE_HT) 2135 ni->ni_txrate = rs_ht->rs_rates[rs_ht->rs_nrates - 1] 2136 | IEEE80211_RATE_MCS; 2137 else 2138 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 2139 ieee80211_free_node(ni); 2140 2141 return (0); 2142} 2143 2144static void 2145urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2146{ 2147 struct r92c_tx_desc *txd = &uvp->bcn_desc; 2148 2149 txd->txdw0 = htole32( 2150 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 2151 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2152 txd->txdw1 = htole32( 2153 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 2154 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2155 2156 if (sc->chip & URTWN_CHIP_88E) { 2157 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 2158 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 2159 } else { 2160 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 2161 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2162 } 2163 2164 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 2165 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 2166} 2167 2168static int 2169urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 2170{ 2171 struct ieee80211vap *vap = ni->ni_vap; 2172 struct urtwn_vap *uvp = URTWN_VAP(vap); 2173 struct mbuf *m; 2174 int error; 2175 2176 URTWN_ASSERT_LOCKED(sc); 2177 2178 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 2179 return (EINVAL); 2180 2181 m = ieee80211_beacon_alloc(ni); 2182 if (m == NULL) { 2183 device_printf(sc->sc_dev, 2184 "%s: could not allocate beacon frame\n", __func__); 2185 return (ENOMEM); 2186 } 2187 2188 if (uvp->bcn_mbuf != NULL) 2189 m_freem(uvp->bcn_mbuf); 2190 2191 uvp->bcn_mbuf = m; 2192 2193 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 2194 return (error); 2195 2196 /* XXX bcnq stuck workaround */ 2197 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 2198 return (error); 2199 2200 URTWN_DPRINTF(sc, URTWN_DEBUG_BEACON, "%s: beacon was %srecognized\n", 2201 __func__, urtwn_read_1(sc, R92C_TDECTRL + 2) & 2202 (R92C_TDECTRL_BCN_VALID >> 16) ? "" : "not "); 2203 2204 return (0); 2205} 2206 2207static void 2208urtwn_update_beacon(struct ieee80211vap *vap, int item) 2209{ 2210 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2211 struct urtwn_vap *uvp = URTWN_VAP(vap); 2212 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 2213 struct ieee80211_node *ni = vap->iv_bss; 2214 int mcast = 0; 2215 2216 URTWN_LOCK(sc); 2217 if (uvp->bcn_mbuf == NULL) { 2218 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 2219 if (uvp->bcn_mbuf == NULL) { 2220 device_printf(sc->sc_dev, 2221 "%s: could not allocate beacon frame\n", __func__); 2222 URTWN_UNLOCK(sc); 2223 return; 2224 } 2225 } 2226 URTWN_UNLOCK(sc); 2227 2228 if (item == IEEE80211_BEACON_TIM) 2229 mcast = 1; /* XXX */ 2230 2231 setbit(bo->bo_flags, item); 2232 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 2233 2234 URTWN_LOCK(sc); 2235 urtwn_tx_beacon(sc, uvp); 2236 URTWN_UNLOCK(sc); 2237} 2238 2239/* 2240 * Push a beacon frame into the chip. Beacon will 2241 * be repeated by the chip every R92C_BCN_INTERVAL. 2242 */ 2243static int 2244urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2245{ 2246 struct r92c_tx_desc *desc = &uvp->bcn_desc; 2247 struct urtwn_data *bf; 2248 2249 URTWN_ASSERT_LOCKED(sc); 2250 2251 bf = urtwn_getbuf(sc); 2252 if (bf == NULL) 2253 return (ENOMEM); 2254 2255 memcpy(bf->buf, desc, sizeof(*desc)); 2256 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 2257 2258 sc->sc_txtimer = 5; 2259 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2260 2261 return (0); 2262} 2263 2264static int 2265urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2266 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2267{ 2268 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2269 uint8_t i; 2270 2271 if (!(&vap->iv_nw_keys[0] <= k && 2272 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2273 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2274 URTWN_LOCK(sc); 2275 /* 2276 * First 4 slots for group keys, 2277 * what is left - for pairwise. 2278 * XXX incompatible with IBSS RSN. 2279 */ 2280 for (i = IEEE80211_WEP_NKID; 2281 i < R92C_CAM_ENTRY_COUNT; i++) { 2282 if ((sc->keys_bmap & (1 << i)) == 0) { 2283 sc->keys_bmap |= 1 << i; 2284 *keyix = i; 2285 break; 2286 } 2287 } 2288 URTWN_UNLOCK(sc); 2289 if (i == R92C_CAM_ENTRY_COUNT) { 2290 device_printf(sc->sc_dev, 2291 "%s: no free space in the key table\n", 2292 __func__); 2293 return 0; 2294 } 2295 } else 2296 *keyix = 0; 2297 } else { 2298 *keyix = k - vap->iv_nw_keys; 2299 } 2300 *rxkeyix = *keyix; 2301 return 1; 2302} 2303 2304static void 2305urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data) 2306{ 2307 struct ieee80211_key *k = &data->key; 2308 uint8_t algo, keyid; 2309 int i, error; 2310 2311 if (k->wk_keyix < IEEE80211_WEP_NKID) 2312 keyid = k->wk_keyix; 2313 else 2314 keyid = 0; 2315 2316 /* Map net80211 cipher to HW crypto algorithm. */ 2317 switch (k->wk_cipher->ic_cipher) { 2318 case IEEE80211_CIPHER_WEP: 2319 if (k->wk_keylen < 8) 2320 algo = R92C_CAM_ALGO_WEP40; 2321 else 2322 algo = R92C_CAM_ALGO_WEP104; 2323 break; 2324 case IEEE80211_CIPHER_TKIP: 2325 algo = R92C_CAM_ALGO_TKIP; 2326 break; 2327 case IEEE80211_CIPHER_AES_CCM: 2328 algo = R92C_CAM_ALGO_AES; 2329 break; 2330 default: 2331 device_printf(sc->sc_dev, "%s: undefined cipher %d\n", 2332 __func__, k->wk_cipher->ic_cipher); 2333 return; 2334 } 2335 2336 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2337 "%s: keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, " 2338 "macaddr %s\n", __func__, k->wk_keyix, keyid, 2339 k->wk_cipher->ic_cipher, algo, k->wk_flags, k->wk_keylen, 2340 ether_sprintf(k->wk_macaddr)); 2341 2342 /* Write key. */ 2343 for (i = 0; i < 4; i++) { 2344 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 2345 le32dec(&k->wk_key[i * 4])); 2346 if (error != 0) 2347 goto fail; 2348 } 2349 2350 /* Write CTL0 last since that will validate the CAM entry. */ 2351 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 2352 le32dec(&k->wk_macaddr[2])); 2353 if (error != 0) 2354 goto fail; 2355 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 2356 SM(R92C_CAM_ALGO, algo) | 2357 SM(R92C_CAM_KEYID, keyid) | 2358 SM(R92C_CAM_MACLO, le16dec(&k->wk_macaddr[0])) | 2359 R92C_CAM_VALID); 2360 if (error != 0) 2361 goto fail; 2362 2363 return; 2364 2365fail: 2366 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error); 2367} 2368 2369static void 2370urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data) 2371{ 2372 struct ieee80211_key *k = &data->key; 2373 int i; 2374 2375 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2376 "%s: keyix %d, flags %04X, macaddr %s\n", __func__, 2377 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr)); 2378 2379 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0); 2380 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0); 2381 2382 /* Clear key. */ 2383 for (i = 0; i < 4; i++) 2384 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0); 2385 sc->keys_bmap &= ~(1 << k->wk_keyix); 2386} 2387 2388static int 2389urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 2390{ 2391 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2392 struct urtwn_vap *uvp = URTWN_VAP(vap); 2393 2394 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2395 /* Not for us. */ 2396 return (1); 2397 } 2398 2399 if (&vap->iv_nw_keys[0] <= k && 2400 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID]) { 2401 URTWN_LOCK(sc); 2402 uvp->keys[k->wk_keyix] = k; 2403 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2404 /* 2405 * The device was not started; 2406 * the key will be installed later. 2407 */ 2408 URTWN_UNLOCK(sc); 2409 return (1); 2410 } 2411 URTWN_UNLOCK(sc); 2412 } 2413 2414 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb)); 2415} 2416 2417static int 2418urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2419{ 2420 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2421 struct urtwn_vap *uvp = URTWN_VAP(vap); 2422 2423 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2424 /* Not for us. */ 2425 return (1); 2426 } 2427 2428 if (&vap->iv_nw_keys[0] <= k && 2429 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID]) { 2430 URTWN_LOCK(sc); 2431 uvp->keys[k->wk_keyix] = NULL; 2432 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2433 /* All keys are removed on device reset. */ 2434 URTWN_UNLOCK(sc); 2435 return (1); 2436 } 2437 URTWN_UNLOCK(sc); 2438 } 2439 2440 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb)); 2441} 2442 2443static void 2444urtwn_tsf_task_adhoc(void *arg, int pending) 2445{ 2446 struct ieee80211vap *vap = arg; 2447 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2448 struct ieee80211_node *ni; 2449 uint32_t reg; 2450 2451 URTWN_LOCK(sc); 2452 ni = ieee80211_ref_node(vap->iv_bss); 2453 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 2454 2455 /* Accept beacons with the same BSSID. */ 2456 urtwn_set_rx_bssid_all(sc, 0); 2457 2458 /* Enable synchronization. */ 2459 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 2460 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2461 2462 /* Synchronize. */ 2463 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 2464 2465 /* Disable synchronization. */ 2466 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 2467 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2468 2469 /* Remove beacon filter. */ 2470 urtwn_set_rx_bssid_all(sc, 1); 2471 2472 /* Enable beaconing. */ 2473 urtwn_write_1(sc, R92C_MBID_NUM, 2474 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2475 reg |= R92C_BCN_CTRL_EN_BCN; 2476 2477 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2478 ieee80211_free_node(ni); 2479 URTWN_UNLOCK(sc); 2480} 2481 2482static void 2483urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 2484{ 2485 struct ieee80211com *ic = &sc->sc_ic; 2486 struct urtwn_vap *uvp = URTWN_VAP(vap); 2487 2488 /* Reset TSF. */ 2489 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2490 2491 switch (vap->iv_opmode) { 2492 case IEEE80211_M_STA: 2493 /* Enable TSF synchronization. */ 2494 urtwn_write_1(sc, R92C_BCN_CTRL, 2495 urtwn_read_1(sc, R92C_BCN_CTRL) & 2496 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 2497 break; 2498 case IEEE80211_M_IBSS: 2499 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 2500 break; 2501 case IEEE80211_M_HOSTAP: 2502 /* Enable beaconing. */ 2503 urtwn_write_1(sc, R92C_MBID_NUM, 2504 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2505 urtwn_write_1(sc, R92C_BCN_CTRL, 2506 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 2507 break; 2508 default: 2509 device_printf(sc->sc_dev, "undefined opmode %d\n", 2510 vap->iv_opmode); 2511 return; 2512 } 2513} 2514 2515static void 2516urtwn_get_tsf(struct urtwn_softc *sc, uint64_t *buf) 2517{ 2518 urtwn_read_region_1(sc, R92C_TSFTR, (uint8_t *)buf, sizeof(*buf)); 2519} 2520 2521static void 2522urtwn_set_led(struct urtwn_softc *sc, int led, int on) 2523{ 2524 uint8_t reg; 2525 2526 if (led == URTWN_LED_LINK) { 2527 if (sc->chip & URTWN_CHIP_88E) { 2528 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 2529 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 2530 if (!on) { 2531 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 2532 urtwn_write_1(sc, R92C_LEDCFG2, 2533 reg | R92C_LEDCFG0_DIS); 2534 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 2535 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 2536 0xfe); 2537 } 2538 } else { 2539 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 2540 if (!on) 2541 reg |= R92C_LEDCFG0_DIS; 2542 urtwn_write_1(sc, R92C_LEDCFG0, reg); 2543 } 2544 sc->ledlink = on; /* Save LED state. */ 2545 } 2546} 2547 2548static void 2549urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 2550{ 2551 uint8_t reg; 2552 2553 reg = urtwn_read_1(sc, R92C_MSR); 2554 reg = (reg & ~R92C_MSR_MASK) | mode; 2555 urtwn_write_1(sc, R92C_MSR, reg); 2556} 2557 2558static void 2559urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 2560 const struct ieee80211_rx_stats *rxs, 2561 int rssi, int nf) 2562{ 2563 struct ieee80211vap *vap = ni->ni_vap; 2564 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2565 struct urtwn_vap *uvp = URTWN_VAP(vap); 2566 uint64_t ni_tstamp, curr_tstamp; 2567 2568 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 2569 2570 if (vap->iv_state == IEEE80211_S_RUN && 2571 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 2572 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 2573 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 2574 URTWN_LOCK(sc); 2575 urtwn_get_tsf(sc, &curr_tstamp); 2576 URTWN_UNLOCK(sc); 2577 curr_tstamp = le64toh(curr_tstamp); 2578 2579 if (ni_tstamp >= curr_tstamp) 2580 (void) ieee80211_ibss_merge(ni); 2581 } 2582} 2583 2584static int 2585urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2586{ 2587 struct urtwn_vap *uvp = URTWN_VAP(vap); 2588 struct ieee80211com *ic = vap->iv_ic; 2589 struct urtwn_softc *sc = ic->ic_softc; 2590 struct ieee80211_node *ni; 2591 enum ieee80211_state ostate; 2592 uint32_t reg; 2593 uint8_t mode; 2594 int error = 0; 2595 2596 ostate = vap->iv_state; 2597 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s -> %s\n", 2598 ieee80211_state_name[ostate], ieee80211_state_name[nstate]); 2599 2600 IEEE80211_UNLOCK(ic); 2601 URTWN_LOCK(sc); 2602 callout_stop(&sc->sc_watchdog_ch); 2603 2604 if (ostate == IEEE80211_S_RUN) { 2605 /* Stop calibration. */ 2606 callout_stop(&sc->sc_calib_to); 2607 2608 /* Turn link LED off. */ 2609 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2610 2611 /* Set media status to 'No Link'. */ 2612 urtwn_set_mode(sc, R92C_MSR_NOLINK); 2613 2614 /* Stop Rx of data frames. */ 2615 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2616 2617 /* Disable TSF synchronization. */ 2618 urtwn_write_1(sc, R92C_BCN_CTRL, 2619 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 2620 R92C_BCN_CTRL_DIS_TSF_UDT0); 2621 2622 /* Disable beaconing. */ 2623 urtwn_write_1(sc, R92C_MBID_NUM, 2624 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 2625 2626 /* Reset TSF. */ 2627 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2628 2629 /* Reset EDCA parameters. */ 2630 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2631 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2632 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2633 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2634 } 2635 2636 switch (nstate) { 2637 case IEEE80211_S_INIT: 2638 /* Turn link LED off. */ 2639 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2640 break; 2641 case IEEE80211_S_SCAN: 2642 /* Pause AC Tx queues. */ 2643 urtwn_write_1(sc, R92C_TXPAUSE, 2644 urtwn_read_1(sc, R92C_TXPAUSE) | R92C_TX_QUEUE_AC); 2645 break; 2646 case IEEE80211_S_AUTH: 2647 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2648 break; 2649 case IEEE80211_S_RUN: 2650 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2651 /* Turn link LED on. */ 2652 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2653 break; 2654 } 2655 2656 ni = ieee80211_ref_node(vap->iv_bss); 2657 2658 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2659 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2660 device_printf(sc->sc_dev, 2661 "%s: could not move to RUN state\n", __func__); 2662 error = EINVAL; 2663 goto end_run; 2664 } 2665 2666 switch (vap->iv_opmode) { 2667 case IEEE80211_M_STA: 2668 mode = R92C_MSR_INFRA; 2669 break; 2670 case IEEE80211_M_IBSS: 2671 mode = R92C_MSR_ADHOC; 2672 break; 2673 case IEEE80211_M_HOSTAP: 2674 mode = R92C_MSR_AP; 2675 break; 2676 default: 2677 device_printf(sc->sc_dev, "undefined opmode %d\n", 2678 vap->iv_opmode); 2679 error = EINVAL; 2680 goto end_run; 2681 } 2682 2683 /* Set media status to 'Associated'. */ 2684 urtwn_set_mode(sc, mode); 2685 2686 /* Set BSSID. */ 2687 urtwn_write_4(sc, R92C_BSSID + 0, le32dec(&ni->ni_bssid[0])); 2688 urtwn_write_4(sc, R92C_BSSID + 4, le16dec(&ni->ni_bssid[4])); 2689 2690 if (ic->ic_curmode == IEEE80211_MODE_11B) 2691 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2692 else /* 802.11b/g */ 2693 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2694 2695 /* Enable Rx of data frames. */ 2696 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2697 2698 /* Flush all AC queues. */ 2699 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2700 2701 /* Set beacon interval. */ 2702 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2703 2704 /* Allow Rx from our BSSID only. */ 2705 if (ic->ic_promisc == 0) { 2706 reg = urtwn_read_4(sc, R92C_RCR); 2707 2708 if (vap->iv_opmode != IEEE80211_M_HOSTAP) { 2709 reg |= R92C_RCR_CBSSID_DATA; 2710 if (vap->iv_opmode != IEEE80211_M_IBSS) 2711 reg |= R92C_RCR_CBSSID_BCN; 2712 } 2713 2714 urtwn_write_4(sc, R92C_RCR, reg); 2715 } 2716 2717 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2718 vap->iv_opmode == IEEE80211_M_IBSS) { 2719 error = urtwn_setup_beacon(sc, ni); 2720 if (error != 0) { 2721 device_printf(sc->sc_dev, 2722 "unable to push beacon into the chip, " 2723 "error %d\n", error); 2724 goto end_run; 2725 } 2726 } 2727 2728 /* Enable TSF synchronization. */ 2729 urtwn_tsf_sync_enable(sc, vap); 2730 2731 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2732 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2733 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2734 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2735 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2736 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2737 2738 /* Intialize rate adaptation. */ 2739 if (!(sc->chip & URTWN_CHIP_88E)) 2740 urtwn_ra_init(sc); 2741 /* Turn link LED on. */ 2742 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2743 2744 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2745 /* Reset temperature calibration state machine. */ 2746 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 2747 sc->thcal_lctemp = 0; 2748 /* Start periodic calibration. */ 2749 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2750 2751end_run: 2752 ieee80211_free_node(ni); 2753 break; 2754 default: 2755 break; 2756 } 2757 2758 URTWN_UNLOCK(sc); 2759 IEEE80211_LOCK(ic); 2760 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2761} 2762 2763static void 2764urtwn_calib_to(void *arg) 2765{ 2766 struct urtwn_softc *sc = arg; 2767 2768 /* Do it in a process context. */ 2769 urtwn_cmd_sleepable(sc, NULL, 0, urtwn_calib_cb); 2770} 2771 2772static void 2773urtwn_calib_cb(struct urtwn_softc *sc, union sec_param *data) 2774{ 2775 /* Do temperature compensation. */ 2776 urtwn_temp_calib(sc); 2777 2778 if ((urtwn_read_1(sc, R92C_MSR) & R92C_MSR_MASK) != R92C_MSR_NOLINK) 2779 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2780} 2781 2782static void 2783urtwn_watchdog(void *arg) 2784{ 2785 struct urtwn_softc *sc = arg; 2786 2787 if (sc->sc_txtimer > 0) { 2788 if (--sc->sc_txtimer == 0) { 2789 device_printf(sc->sc_dev, "device timeout\n"); 2790 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2791 return; 2792 } 2793 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2794 } 2795} 2796 2797static void 2798urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2799{ 2800 int pwdb; 2801 2802 /* Convert antenna signal to percentage. */ 2803 if (rssi <= -100 || rssi >= 20) 2804 pwdb = 0; 2805 else if (rssi >= 0) 2806 pwdb = 100; 2807 else 2808 pwdb = 100 + rssi; 2809 if (!(sc->chip & URTWN_CHIP_88E)) { 2810 if (rate <= URTWN_RIDX_CCK11) { 2811 /* CCK gain is smaller than OFDM/MCS gain. */ 2812 pwdb += 6; 2813 if (pwdb > 100) 2814 pwdb = 100; 2815 if (pwdb <= 14) 2816 pwdb -= 4; 2817 else if (pwdb <= 26) 2818 pwdb -= 8; 2819 else if (pwdb <= 34) 2820 pwdb -= 6; 2821 else if (pwdb <= 42) 2822 pwdb -= 2; 2823 } 2824 } 2825 if (sc->avg_pwdb == -1) /* Init. */ 2826 sc->avg_pwdb = pwdb; 2827 else if (sc->avg_pwdb < pwdb) 2828 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2829 else 2830 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2831 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: PWDB %d, EMA %d\n", __func__, 2832 pwdb, sc->avg_pwdb); 2833} 2834 2835static int8_t 2836urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2837{ 2838 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2839 struct r92c_rx_phystat *phy; 2840 struct r92c_rx_cck *cck; 2841 uint8_t rpt; 2842 int8_t rssi; 2843 2844 if (rate <= URTWN_RIDX_CCK11) { 2845 cck = (struct r92c_rx_cck *)physt; 2846 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2847 rpt = (cck->agc_rpt >> 5) & 0x3; 2848 rssi = (cck->agc_rpt & 0x1f) << 1; 2849 } else { 2850 rpt = (cck->agc_rpt >> 6) & 0x3; 2851 rssi = cck->agc_rpt & 0x3e; 2852 } 2853 rssi = cckoff[rpt] - rssi; 2854 } else { /* OFDM/HT. */ 2855 phy = (struct r92c_rx_phystat *)physt; 2856 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2857 } 2858 return (rssi); 2859} 2860 2861static int8_t 2862urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2863{ 2864 struct r92c_rx_phystat *phy; 2865 struct r88e_rx_cck *cck; 2866 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2867 int8_t rssi; 2868 2869 rssi = 0; 2870 if (rate <= URTWN_RIDX_CCK11) { 2871 cck = (struct r88e_rx_cck *)physt; 2872 cck_agc_rpt = cck->agc_rpt; 2873 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2874 vga_idx = cck_agc_rpt & 0x1f; 2875 switch (lna_idx) { 2876 case 7: 2877 if (vga_idx <= 27) 2878 rssi = -100 + 2* (27 - vga_idx); 2879 else 2880 rssi = -100; 2881 break; 2882 case 6: 2883 rssi = -48 + 2 * (2 - vga_idx); 2884 break; 2885 case 5: 2886 rssi = -42 + 2 * (7 - vga_idx); 2887 break; 2888 case 4: 2889 rssi = -36 + 2 * (7 - vga_idx); 2890 break; 2891 case 3: 2892 rssi = -24 + 2 * (7 - vga_idx); 2893 break; 2894 case 2: 2895 rssi = -12 + 2 * (5 - vga_idx); 2896 break; 2897 case 1: 2898 rssi = 8 - (2 * vga_idx); 2899 break; 2900 case 0: 2901 rssi = 14 - (2 * vga_idx); 2902 break; 2903 } 2904 rssi += 6; 2905 } else { /* OFDM/HT. */ 2906 phy = (struct r92c_rx_phystat *)physt; 2907 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2908 } 2909 return (rssi); 2910} 2911 2912static int 2913urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2914 struct mbuf *m, struct urtwn_data *data) 2915{ 2916 const struct ieee80211_txparam *tp; 2917 struct ieee80211com *ic = &sc->sc_ic; 2918 struct ieee80211vap *vap = ni->ni_vap; 2919 struct ieee80211_key *k = NULL; 2920 struct ieee80211_channel *chan; 2921 struct ieee80211_frame *wh; 2922 struct r92c_tx_desc *txd; 2923 uint8_t macid, raid, rate, ridx, type, tid, qos, qsel; 2924 int hasqos, ismcast; 2925 2926 URTWN_ASSERT_LOCKED(sc); 2927 2928 wh = mtod(m, struct ieee80211_frame *); 2929 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2930 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2931 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2932 2933 /* Select TX ring for this frame. */ 2934 if (hasqos) { 2935 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2936 tid = qos & IEEE80211_QOS_TID; 2937 } else { 2938 qos = 0; 2939 tid = 0; 2940 } 2941 2942 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2943 ni->ni_chan : ic->ic_curchan; 2944 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2945 2946 /* Choose a TX rate index. */ 2947 if (type == IEEE80211_FC0_TYPE_MGT) 2948 rate = tp->mgmtrate; 2949 else if (ismcast) 2950 rate = tp->mcastrate; 2951 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2952 rate = tp->ucastrate; 2953 else if (m->m_flags & M_EAPOL) 2954 rate = tp->mgmtrate; 2955 else { 2956 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2957 /* XXX pass pktlen */ 2958 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2959 rate = ni->ni_txrate; 2960 } else { 2961 /* XXX TODO: drop the default rate for 11b/11g? */ 2962 if (ni->ni_flags & IEEE80211_NODE_HT) 2963 rate = IEEE80211_RATE_MCS | 0x4; /* MCS4 */ 2964 else if (ic->ic_curmode != IEEE80211_MODE_11B) 2965 rate = 108; 2966 else 2967 rate = 22; 2968 } 2969 } 2970 2971 /* 2972 * XXX TODO: this should be per-node, for 11b versus 11bg 2973 * nodes in hostap mode 2974 */ 2975 ridx = rate2ridx(rate); 2976 if (ni->ni_flags & IEEE80211_NODE_HT) 2977 raid = R92C_RAID_11GN; 2978 else if (ic->ic_curmode != IEEE80211_MODE_11B) 2979 raid = R92C_RAID_11BG; 2980 else 2981 raid = R92C_RAID_11B; 2982 2983 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2984 k = ieee80211_crypto_encap(ni, m); 2985 if (k == NULL) { 2986 device_printf(sc->sc_dev, 2987 "ieee80211_crypto_encap returns NULL.\n"); 2988 return (ENOBUFS); 2989 } 2990 2991 /* in case packet header moved, reset pointer */ 2992 wh = mtod(m, struct ieee80211_frame *); 2993 } 2994 2995 /* Fill Tx descriptor. */ 2996 txd = (struct r92c_tx_desc *)data->buf; 2997 memset(txd, 0, sizeof(*txd)); 2998 2999 txd->txdw0 |= htole32( 3000 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 3001 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 3002 if (ismcast) 3003 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 3004 3005 if (!ismcast) { 3006 /* Unicast frame, check if an ACK is expected. */ 3007 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 3008 IEEE80211_QOS_ACKPOLICY_NOACK) { 3009 txd->txdw5 |= htole32(R92C_TXDW5_RTY_LMT_ENA); 3010 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTY_LMT, 3011 tp->maxretry)); 3012 } 3013 3014 if (sc->chip & URTWN_CHIP_88E) { 3015 struct urtwn_node *un = URTWN_NODE(ni); 3016 macid = un->id; 3017 } else 3018 macid = URTWN_MACID_BSS; 3019 3020 if (type == IEEE80211_FC0_TYPE_DATA) { 3021 qsel = tid % URTWN_MAX_TID; 3022 3023 if (sc->chip & URTWN_CHIP_88E) { 3024 txd->txdw2 |= htole32( 3025 R88E_TXDW2_AGGBK | 3026 R88E_TXDW2_CCX_RPT); 3027 } else 3028 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 3029 3030 /* protmode, non-HT */ 3031 /* XXX TODO: noack frames? */ 3032 if ((rate & 0x80) == 0 && 3033 (ic->ic_flags & IEEE80211_F_USEPROT)) { 3034 switch (ic->ic_protmode) { 3035 case IEEE80211_PROT_CTSONLY: 3036 txd->txdw4 |= htole32( 3037 R92C_TXDW4_CTS2SELF); 3038 break; 3039 case IEEE80211_PROT_RTSCTS: 3040 txd->txdw4 |= htole32( 3041 R92C_TXDW4_RTSEN | 3042 R92C_TXDW4_HWRTSEN); 3043 break; 3044 default: 3045 break; 3046 } 3047 } 3048 3049 /* protmode, HT */ 3050 /* XXX TODO: noack frames? */ 3051 if ((rate & 0x80) && 3052 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) { 3053 txd->txdw4 |= htole32( 3054 R92C_TXDW4_RTSEN | 3055 R92C_TXDW4_HWRTSEN); 3056 } 3057 3058 /* XXX TODO: rtsrate is configurable? 24mbit may 3059 * be a bit high for RTS rate? */ 3060 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 3061 URTWN_RIDX_OFDM24)); 3062 3063 txd->txdw5 |= htole32(0x0001ff00); 3064 } else /* IEEE80211_FC0_TYPE_MGT */ 3065 qsel = R92C_TXDW1_QSEL_MGNT; 3066 } else { 3067 macid = URTWN_MACID_BC; 3068 qsel = R92C_TXDW1_QSEL_MGNT; 3069 } 3070 3071 txd->txdw1 |= htole32( 3072 SM(R92C_TXDW1_QSEL, qsel) | 3073 SM(R92C_TXDW1_RAID, raid)); 3074 3075 /* XXX TODO: 40MHZ flag? */ 3076 /* XXX TODO: AMPDU flag? (AGG_ENABLE or AGG_BREAK?) Density shift? */ 3077 /* XXX Short preamble? */ 3078 /* XXX Short-GI? */ 3079 3080 if (sc->chip & URTWN_CHIP_88E) 3081 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 3082 else 3083 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 3084 3085 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 3086 3087 /* Force this rate if needed. */ 3088 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 3089 (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) || 3090 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 3091 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3092 3093 if (!hasqos) { 3094 /* Use HW sequence numbering for non-QoS frames. */ 3095 if (sc->chip & URTWN_CHIP_88E) 3096 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 3097 else 3098 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 3099 } else { 3100 /* Set sequence number. */ 3101 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 3102 } 3103 3104 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 3105 uint8_t cipher; 3106 3107 switch (k->wk_cipher->ic_cipher) { 3108 case IEEE80211_CIPHER_WEP: 3109 case IEEE80211_CIPHER_TKIP: 3110 cipher = R92C_TXDW1_CIPHER_RC4; 3111 break; 3112 case IEEE80211_CIPHER_AES_CCM: 3113 cipher = R92C_TXDW1_CIPHER_AES; 3114 break; 3115 default: 3116 device_printf(sc->sc_dev, "%s: unknown cipher %d\n", 3117 __func__, k->wk_cipher->ic_cipher); 3118 return (EINVAL); 3119 } 3120 3121 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 3122 } 3123 3124 if (ieee80211_radiotap_active_vap(vap)) { 3125 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3126 3127 tap->wt_flags = 0; 3128 if (k != NULL) 3129 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3130 ieee80211_radiotap_tx(vap, m); 3131 } 3132 3133 data->ni = ni; 3134 3135 urtwn_tx_start(sc, m, type, data); 3136 3137 return (0); 3138} 3139 3140static int 3141urtwn_tx_raw(struct urtwn_softc *sc, struct ieee80211_node *ni, 3142 struct mbuf *m, struct urtwn_data *data, 3143 const struct ieee80211_bpf_params *params) 3144{ 3145 struct ieee80211vap *vap = ni->ni_vap; 3146 struct ieee80211_key *k = NULL; 3147 struct ieee80211_frame *wh; 3148 struct r92c_tx_desc *txd; 3149 uint8_t cipher, ridx, type; 3150 3151 /* Encrypt the frame if need be. */ 3152 cipher = R92C_TXDW1_CIPHER_NONE; 3153 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 3154 /* Retrieve key for TX. */ 3155 k = ieee80211_crypto_encap(ni, m); 3156 if (k == NULL) 3157 return (ENOBUFS); 3158 3159 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 3160 switch (k->wk_cipher->ic_cipher) { 3161 case IEEE80211_CIPHER_WEP: 3162 case IEEE80211_CIPHER_TKIP: 3163 cipher = R92C_TXDW1_CIPHER_RC4; 3164 break; 3165 case IEEE80211_CIPHER_AES_CCM: 3166 cipher = R92C_TXDW1_CIPHER_AES; 3167 break; 3168 default: 3169 device_printf(sc->sc_dev, 3170 "%s: unknown cipher %d\n", 3171 __func__, k->wk_cipher->ic_cipher); 3172 return (EINVAL); 3173 } 3174 } 3175 } 3176 3177 /* XXX TODO: 11n checks, matching urtwn_tx_data() */ 3178 3179 wh = mtod(m, struct ieee80211_frame *); 3180 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3181 3182 /* Fill Tx descriptor. */ 3183 txd = (struct r92c_tx_desc *)data->buf; 3184 memset(txd, 0, sizeof(*txd)); 3185 3186 txd->txdw0 |= htole32( 3187 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 3188 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 3189 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3190 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 3191 3192 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3193 txd->txdw5 |= htole32(R92C_TXDW5_RTY_LMT_ENA); 3194 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTY_LMT, 3195 params->ibp_try0)); 3196 } 3197 if (params->ibp_flags & IEEE80211_BPF_RTS) 3198 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_HWRTSEN); 3199 if (params->ibp_flags & IEEE80211_BPF_CTS) 3200 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF); 3201 if (txd->txdw4 & htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_CTS2SELF)) { 3202 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 3203 URTWN_RIDX_OFDM24)); 3204 } 3205 3206 if (sc->chip & URTWN_CHIP_88E) 3207 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 3208 else 3209 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 3210 3211 /* XXX TODO: rate index/config (RAID) for 11n? */ 3212 txd->txdw1 |= htole32(SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT)); 3213 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 3214 3215 /* Choose a TX rate index. */ 3216 ridx = rate2ridx(params->ibp_rate0); 3217 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 3218 txd->txdw5 |= htole32(0x0001ff00); 3219 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3220 3221 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 3222 /* Use HW sequence numbering for non-QoS frames. */ 3223 if (sc->chip & URTWN_CHIP_88E) 3224 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 3225 else 3226 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 3227 } else { 3228 /* Set sequence number. */ 3229 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 3230 } 3231 3232 if (ieee80211_radiotap_active_vap(vap)) { 3233 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3234 3235 tap->wt_flags = 0; 3236 if (k != NULL) 3237 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3238 ieee80211_radiotap_tx(vap, m); 3239 } 3240 3241 data->ni = ni; 3242 3243 urtwn_tx_start(sc, m, type, data); 3244 3245 return (0); 3246} 3247 3248static void 3249urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 3250 struct urtwn_data *data) 3251{ 3252 struct usb_xfer *xfer; 3253 struct r92c_tx_desc *txd; 3254 uint16_t ac, sum; 3255 int i, xferlen; 3256 3257 URTWN_ASSERT_LOCKED(sc); 3258 3259 ac = M_WME_GETAC(m); 3260 3261 switch (type) { 3262 case IEEE80211_FC0_TYPE_CTL: 3263 case IEEE80211_FC0_TYPE_MGT: 3264 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 3265 break; 3266 default: 3267 xfer = sc->sc_xfer[wme2queue[ac].qid]; 3268 break; 3269 } 3270 3271 txd = (struct r92c_tx_desc *)data->buf; 3272 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 3273 3274 /* Compute Tx descriptor checksum. */ 3275 sum = 0; 3276 for (i = 0; i < sizeof(*txd) / 2; i++) 3277 sum ^= ((uint16_t *)txd)[i]; 3278 txd->txdsum = sum; /* NB: already little endian. */ 3279 3280 xferlen = sizeof(*txd) + m->m_pkthdr.len; 3281 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 3282 3283 data->buflen = xferlen; 3284 data->m = m; 3285 3286 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 3287 usbd_transfer_start(xfer); 3288} 3289 3290static int 3291urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 3292{ 3293 struct urtwn_softc *sc = ic->ic_softc; 3294 int error; 3295 3296 URTWN_LOCK(sc); 3297 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 3298 URTWN_UNLOCK(sc); 3299 return (ENXIO); 3300 } 3301 error = mbufq_enqueue(&sc->sc_snd, m); 3302 if (error) { 3303 URTWN_UNLOCK(sc); 3304 return (error); 3305 } 3306 urtwn_start(sc); 3307 URTWN_UNLOCK(sc); 3308 3309 return (0); 3310} 3311 3312static void 3313urtwn_start(struct urtwn_softc *sc) 3314{ 3315 struct ieee80211_node *ni; 3316 struct mbuf *m; 3317 struct urtwn_data *bf; 3318 3319 URTWN_ASSERT_LOCKED(sc); 3320 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 3321 bf = urtwn_getbuf(sc); 3322 if (bf == NULL) { 3323 mbufq_prepend(&sc->sc_snd, m); 3324 break; 3325 } 3326 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3327 m->m_pkthdr.rcvif = NULL; 3328 3329 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n", 3330 __func__, 3331 m); 3332 3333 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 3334 if_inc_counter(ni->ni_vap->iv_ifp, 3335 IFCOUNTER_OERRORS, 1); 3336 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3337 m_freem(m); 3338 ieee80211_free_node(ni); 3339 break; 3340 } 3341 sc->sc_txtimer = 5; 3342 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3343 } 3344} 3345 3346static void 3347urtwn_parent(struct ieee80211com *ic) 3348{ 3349 struct urtwn_softc *sc = ic->ic_softc; 3350 3351 URTWN_LOCK(sc); 3352 if (sc->sc_flags & URTWN_DETACHED) { 3353 URTWN_UNLOCK(sc); 3354 return; 3355 } 3356 URTWN_UNLOCK(sc); 3357 3358 if (ic->ic_nrunning > 0) { 3359 if (urtwn_init(sc) != 0) { 3360 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3361 if (vap != NULL) 3362 ieee80211_stop(vap); 3363 } else 3364 ieee80211_start_all(ic); 3365 } else 3366 urtwn_stop(sc); 3367} 3368 3369static __inline int 3370urtwn_power_on(struct urtwn_softc *sc) 3371{ 3372 3373 return sc->sc_power_on(sc); 3374} 3375 3376static int 3377urtwn_r92c_power_on(struct urtwn_softc *sc) 3378{ 3379 uint32_t reg; 3380 usb_error_t error; 3381 int ntries; 3382 3383 /* Wait for autoload done bit. */ 3384 for (ntries = 0; ntries < 1000; ntries++) { 3385 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3386 break; 3387 urtwn_ms_delay(sc); 3388 } 3389 if (ntries == 1000) { 3390 device_printf(sc->sc_dev, 3391 "timeout waiting for chip autoload\n"); 3392 return (ETIMEDOUT); 3393 } 3394 3395 /* Unlock ISO/CLK/Power control register. */ 3396 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3397 if (error != USB_ERR_NORMAL_COMPLETION) 3398 return (EIO); 3399 /* Move SPS into PWM mode. */ 3400 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3401 if (error != USB_ERR_NORMAL_COMPLETION) 3402 return (EIO); 3403 urtwn_ms_delay(sc); 3404 3405 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3406 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3407 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3408 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3409 if (error != USB_ERR_NORMAL_COMPLETION) 3410 return (EIO); 3411 urtwn_ms_delay(sc); 3412 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3413 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3414 ~R92C_SYS_ISO_CTRL_MD2PP); 3415 if (error != USB_ERR_NORMAL_COMPLETION) 3416 return (EIO); 3417 } 3418 3419 /* Auto enable WLAN. */ 3420 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3421 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3422 if (error != USB_ERR_NORMAL_COMPLETION) 3423 return (EIO); 3424 for (ntries = 0; ntries < 1000; ntries++) { 3425 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3426 R92C_APS_FSMCO_APFM_ONMAC)) 3427 break; 3428 urtwn_ms_delay(sc); 3429 } 3430 if (ntries == 1000) { 3431 device_printf(sc->sc_dev, 3432 "timeout waiting for MAC auto ON\n"); 3433 return (ETIMEDOUT); 3434 } 3435 3436 /* Enable radio, GPIO and LED functions. */ 3437 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3438 R92C_APS_FSMCO_AFSM_HSUS | 3439 R92C_APS_FSMCO_PDN_EN | 3440 R92C_APS_FSMCO_PFM_ALDN); 3441 if (error != USB_ERR_NORMAL_COMPLETION) 3442 return (EIO); 3443 /* Release RF digital isolation. */ 3444 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3445 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3446 if (error != USB_ERR_NORMAL_COMPLETION) 3447 return (EIO); 3448 3449 /* Initialize MAC. */ 3450 error = urtwn_write_1(sc, R92C_APSD_CTRL, 3451 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3452 if (error != USB_ERR_NORMAL_COMPLETION) 3453 return (EIO); 3454 for (ntries = 0; ntries < 200; ntries++) { 3455 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3456 R92C_APSD_CTRL_OFF_STATUS)) 3457 break; 3458 urtwn_ms_delay(sc); 3459 } 3460 if (ntries == 200) { 3461 device_printf(sc->sc_dev, 3462 "timeout waiting for MAC initialization\n"); 3463 return (ETIMEDOUT); 3464 } 3465 3466 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3467 reg = urtwn_read_2(sc, R92C_CR); 3468 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3469 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3470 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3471 R92C_CR_ENSEC; 3472 error = urtwn_write_2(sc, R92C_CR, reg); 3473 if (error != USB_ERR_NORMAL_COMPLETION) 3474 return (EIO); 3475 3476 error = urtwn_write_1(sc, 0xfe10, 0x19); 3477 if (error != USB_ERR_NORMAL_COMPLETION) 3478 return (EIO); 3479 return (0); 3480} 3481 3482static int 3483urtwn_r88e_power_on(struct urtwn_softc *sc) 3484{ 3485 uint32_t reg; 3486 usb_error_t error; 3487 int ntries; 3488 3489 /* Wait for power ready bit. */ 3490 for (ntries = 0; ntries < 5000; ntries++) { 3491 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 3492 break; 3493 urtwn_ms_delay(sc); 3494 } 3495 if (ntries == 5000) { 3496 device_printf(sc->sc_dev, 3497 "timeout waiting for chip power up\n"); 3498 return (ETIMEDOUT); 3499 } 3500 3501 /* Reset BB. */ 3502 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3503 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3504 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3505 if (error != USB_ERR_NORMAL_COMPLETION) 3506 return (EIO); 3507 3508 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3509 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3510 if (error != USB_ERR_NORMAL_COMPLETION) 3511 return (EIO); 3512 3513 /* Disable HWPDN. */ 3514 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3515 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3516 if (error != USB_ERR_NORMAL_COMPLETION) 3517 return (EIO); 3518 3519 /* Disable WL suspend. */ 3520 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3521 urtwn_read_2(sc, R92C_APS_FSMCO) & 3522 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 3523 if (error != USB_ERR_NORMAL_COMPLETION) 3524 return (EIO); 3525 3526 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3527 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3528 if (error != USB_ERR_NORMAL_COMPLETION) 3529 return (EIO); 3530 for (ntries = 0; ntries < 5000; ntries++) { 3531 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3532 R92C_APS_FSMCO_APFM_ONMAC)) 3533 break; 3534 urtwn_ms_delay(sc); 3535 } 3536 if (ntries == 5000) 3537 return (ETIMEDOUT); 3538 3539 /* Enable LDO normal mode. */ 3540 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 3541 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~R92C_LPLDO_CTRL_SLEEP); 3542 if (error != USB_ERR_NORMAL_COMPLETION) 3543 return (EIO); 3544 3545 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3546 error = urtwn_write_2(sc, R92C_CR, 0); 3547 if (error != USB_ERR_NORMAL_COMPLETION) 3548 return (EIO); 3549 reg = urtwn_read_2(sc, R92C_CR); 3550 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3551 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3552 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3553 error = urtwn_write_2(sc, R92C_CR, reg); 3554 if (error != USB_ERR_NORMAL_COMPLETION) 3555 return (EIO); 3556 3557 return (0); 3558} 3559 3560static __inline void 3561urtwn_power_off(struct urtwn_softc *sc) 3562{ 3563 3564 return sc->sc_power_off(sc); 3565} 3566 3567static void 3568urtwn_r92c_power_off(struct urtwn_softc *sc) 3569{ 3570 uint32_t reg; 3571 3572 /* Block all Tx queues. */ 3573 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3574 3575 /* Disable RF */ 3576 urtwn_rf_write(sc, 0, 0, 0); 3577 3578 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3579 3580 /* Reset BB state machine */ 3581 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3582 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA | 3583 R92C_SYS_FUNC_EN_BB_GLB_RST); 3584 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3585 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3586 3587 /* 3588 * Reset digital sequence 3589 */ 3590#ifndef URTWN_WITHOUT_UCODE 3591 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3592 /* Reset MCU ready status */ 3593 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3594 3595 /* If firmware in ram code, do reset */ 3596 urtwn_fw_reset(sc); 3597 } 3598#endif 3599 3600 /* Reset MAC and Enable 8051 */ 3601 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 3602 (R92C_SYS_FUNC_EN_CPUEN | 3603 R92C_SYS_FUNC_EN_ELDR | 3604 R92C_SYS_FUNC_EN_HWPDN) >> 8); 3605 3606 /* Reset MCU ready status */ 3607 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3608 3609 /* Disable MAC clock */ 3610 urtwn_write_2(sc, R92C_SYS_CLKR, 3611 R92C_SYS_CLKR_ANAD16V_EN | 3612 R92C_SYS_CLKR_ANA8M | 3613 R92C_SYS_CLKR_LOADER_EN | 3614 R92C_SYS_CLKR_80M_SSC_DIS | 3615 R92C_SYS_CLKR_SYS_EN | 3616 R92C_SYS_CLKR_RING_EN | 3617 0x4000); 3618 3619 /* Disable AFE PLL */ 3620 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3621 3622 /* Gated AFE DIG_CLOCK */ 3623 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3624 3625 /* Isolated digital to PON */ 3626 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3627 R92C_SYS_ISO_CTRL_MD2PP | 3628 R92C_SYS_ISO_CTRL_PA2PCIE | 3629 R92C_SYS_ISO_CTRL_PD2CORE | 3630 R92C_SYS_ISO_CTRL_IP2MAC | 3631 R92C_SYS_ISO_CTRL_DIOP | 3632 R92C_SYS_ISO_CTRL_DIOE); 3633 3634 /* 3635 * Pull GPIO PIN to balance level and LED control 3636 */ 3637 /* 1. Disable GPIO[7:0] */ 3638 urtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000); 3639 3640 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3641 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3642 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3643 3644 /* Disable GPIO[10:8] */ 3645 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x00); 3646 3647 reg = urtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0; 3648 reg |= (((reg & 0x000f) << 4) | 0x0780); 3649 urtwn_write_2(sc, R92C_GPIO_IO_SEL, reg); 3650 3651 /* Disable LED0 & 1 */ 3652 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3653 3654 /* 3655 * Reset digital sequence 3656 */ 3657 /* Disable ELDR clock */ 3658 urtwn_write_2(sc, R92C_SYS_CLKR, 3659 R92C_SYS_CLKR_ANAD16V_EN | 3660 R92C_SYS_CLKR_ANA8M | 3661 R92C_SYS_CLKR_LOADER_EN | 3662 R92C_SYS_CLKR_80M_SSC_DIS | 3663 R92C_SYS_CLKR_SYS_EN | 3664 R92C_SYS_CLKR_RING_EN | 3665 0x4000); 3666 3667 /* Isolated ELDR to PON */ 3668 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 3669 (R92C_SYS_ISO_CTRL_DIOR | 3670 R92C_SYS_ISO_CTRL_PWC_EV12V) >> 8); 3671 3672 /* 3673 * Disable analog sequence 3674 */ 3675 /* Disable A15 power */ 3676 urtwn_write_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_OBUF); 3677 /* Disable digital core power */ 3678 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3679 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3680 ~R92C_LDOV12D_CTRL_LDV12_EN); 3681 3682 /* Enter PFM mode */ 3683 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3684 3685 /* Set USB suspend */ 3686 urtwn_write_2(sc, R92C_APS_FSMCO, 3687 R92C_APS_FSMCO_APDM_HOST | 3688 R92C_APS_FSMCO_AFSM_HSUS | 3689 R92C_APS_FSMCO_PFM_ALDN); 3690 3691 /* Lock ISO/CLK/Power control register. */ 3692 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 3693} 3694 3695static void 3696urtwn_r88e_power_off(struct urtwn_softc *sc) 3697{ 3698 uint8_t reg; 3699 int ntries; 3700 3701 /* Disable any kind of TX reports. */ 3702 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 3703 urtwn_read_1(sc, R88E_TX_RPT_CTRL) & 3704 ~(R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA)); 3705 3706 /* Stop Rx. */ 3707 urtwn_write_1(sc, R92C_CR, 0); 3708 3709 /* Move card to Low Power State. */ 3710 /* Block all Tx queues. */ 3711 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3712 3713 for (ntries = 0; ntries < 20; ntries++) { 3714 /* Should be zero if no packet is transmitting. */ 3715 if (urtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 3716 break; 3717 3718 urtwn_ms_delay(sc); 3719 } 3720 if (ntries == 20) { 3721 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 3722 __func__); 3723 return; 3724 } 3725 3726 /* CCK and OFDM are disabled, and clock are gated. */ 3727 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3728 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_BBRSTB); 3729 3730 urtwn_ms_delay(sc); 3731 3732 /* Reset MAC TRX */ 3733 urtwn_write_1(sc, R92C_CR, 3734 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3735 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | 3736 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN); 3737 3738 /* check if removed later */ 3739 urtwn_write_1(sc, R92C_CR + 1, 3740 urtwn_read_1(sc, R92C_CR + 1) & ~(R92C_CR_ENSEC >> 8)); 3741 3742 /* Respond TxOK to scheduler */ 3743 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 3744 urtwn_read_1(sc, R92C_DUAL_TSF_RST) | 0x20); 3745 3746 /* If firmware in ram code, do reset. */ 3747#ifndef URTWN_WITHOUT_UCODE 3748 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) 3749 urtwn_r88e_fw_reset(sc); 3750#endif 3751 3752 /* Reset MCU ready status. */ 3753 urtwn_write_1(sc, R92C_MCUFWDL, 0x00); 3754 3755 /* Disable 32k. */ 3756 urtwn_write_1(sc, R88E_32K_CTRL, 3757 urtwn_read_1(sc, R88E_32K_CTRL) & ~0x01); 3758 3759 /* Move card to Disabled state. */ 3760 /* Turn off RF. */ 3761 urtwn_write_1(sc, R92C_RF_CTRL, 0); 3762 3763 /* LDO Sleep mode. */ 3764 urtwn_write_1(sc, R92C_LPLDO_CTRL, 3765 urtwn_read_1(sc, R92C_LPLDO_CTRL) | R92C_LPLDO_CTRL_SLEEP); 3766 3767 /* Turn off MAC by HW state machine */ 3768 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3769 urtwn_read_1(sc, R92C_APS_FSMCO + 1) | 3770 (R92C_APS_FSMCO_APFM_OFF >> 8)); 3771 3772 for (ntries = 0; ntries < 20; ntries++) { 3773 /* Wait until it will be disabled. */ 3774 if ((urtwn_read_1(sc, R92C_APS_FSMCO + 1) & 3775 (R92C_APS_FSMCO_APFM_OFF >> 8)) == 0) 3776 break; 3777 3778 urtwn_ms_delay(sc); 3779 } 3780 if (ntries == 20) { 3781 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 3782 __func__); 3783 return; 3784 } 3785 3786 /* schmit trigger */ 3787 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3788 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3789 3790 /* Enable WL suspend. */ 3791 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3792 (urtwn_read_1(sc, R92C_APS_FSMCO + 1) & ~0x10) | 0x08); 3793 3794 /* Enable bandgap mbias in suspend. */ 3795 urtwn_write_1(sc, R92C_APS_FSMCO + 3, 0); 3796 3797 /* Clear SIC_EN register. */ 3798 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 1, 3799 urtwn_read_1(sc, R92C_GPIO_MUXCFG + 1) & ~0x10); 3800 3801 /* Set USB suspend enable local register */ 3802 urtwn_write_1(sc, R92C_USB_SUSPEND, 3803 urtwn_read_1(sc, R92C_USB_SUSPEND) | 0x10); 3804 3805 /* Reset MCU IO Wrapper. */ 3806 reg = urtwn_read_1(sc, R92C_RSV_CTRL + 1); 3807 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08); 3808 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08); 3809 3810 /* marked as 'For Power Consumption' code. */ 3811 urtwn_write_1(sc, R92C_GPIO_OUT, urtwn_read_1(sc, R92C_GPIO_IN)); 3812 urtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff); 3813 3814 urtwn_write_1(sc, R92C_GPIO_IO_SEL, 3815 urtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4); 3816 urtwn_write_1(sc, R92C_GPIO_MOD, 3817 urtwn_read_1(sc, R92C_GPIO_MOD) | 0x0f); 3818 3819 /* Set LNA, TRSW, EX_PA Pin to output mode. */ 3820 urtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808); 3821} 3822 3823static int 3824urtwn_llt_init(struct urtwn_softc *sc) 3825{ 3826 int i, error, page_count, pktbuf_count; 3827 3828 page_count = (sc->chip & URTWN_CHIP_88E) ? 3829 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 3830 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 3831 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 3832 3833 /* Reserve pages [0; page_count]. */ 3834 for (i = 0; i < page_count; i++) { 3835 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3836 return (error); 3837 } 3838 /* NB: 0xff indicates end-of-list. */ 3839 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3840 return (error); 3841 /* 3842 * Use pages [page_count + 1; pktbuf_count - 1] 3843 * as ring buffer. 3844 */ 3845 for (++i; i < pktbuf_count - 1; i++) { 3846 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3847 return (error); 3848 } 3849 /* Make the last page point to the beginning of the ring buffer. */ 3850 error = urtwn_llt_write(sc, i, page_count + 1); 3851 return (error); 3852} 3853 3854#ifndef URTWN_WITHOUT_UCODE 3855static void 3856urtwn_fw_reset(struct urtwn_softc *sc) 3857{ 3858 uint16_t reg; 3859 int ntries; 3860 3861 /* Tell 8051 to reset itself. */ 3862 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3863 3864 /* Wait until 8051 resets by itself. */ 3865 for (ntries = 0; ntries < 100; ntries++) { 3866 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3867 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3868 return; 3869 urtwn_ms_delay(sc); 3870 } 3871 /* Force 8051 reset. */ 3872 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3873} 3874 3875static void 3876urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3877{ 3878 uint16_t reg; 3879 3880 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3881 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3882 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3883} 3884 3885static int 3886urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 3887{ 3888 uint32_t reg; 3889 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 3890 int off, mlen; 3891 3892 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3893 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3894 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3895 3896 off = R92C_FW_START_ADDR; 3897 while (len > 0) { 3898 if (len > 196) 3899 mlen = 196; 3900 else if (len > 4) 3901 mlen = 4; 3902 else 3903 mlen = 1; 3904 /* XXX fix this deconst */ 3905 error = urtwn_write_region_1(sc, off, 3906 __DECONST(uint8_t *, buf), mlen); 3907 if (error != USB_ERR_NORMAL_COMPLETION) 3908 break; 3909 off += mlen; 3910 buf += mlen; 3911 len -= mlen; 3912 } 3913 return (error); 3914} 3915 3916static int 3917urtwn_load_firmware(struct urtwn_softc *sc) 3918{ 3919 const struct firmware *fw; 3920 const struct r92c_fw_hdr *hdr; 3921 const char *imagename; 3922 const u_char *ptr; 3923 size_t len; 3924 uint32_t reg; 3925 int mlen, ntries, page, error; 3926 3927 URTWN_UNLOCK(sc); 3928 /* Read firmware image from the filesystem. */ 3929 if (sc->chip & URTWN_CHIP_88E) 3930 imagename = "urtwn-rtl8188eufw"; 3931 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3932 URTWN_CHIP_UMC_A_CUT) 3933 imagename = "urtwn-rtl8192cfwU"; 3934 else 3935 imagename = "urtwn-rtl8192cfwT"; 3936 3937 fw = firmware_get(imagename); 3938 URTWN_LOCK(sc); 3939 if (fw == NULL) { 3940 device_printf(sc->sc_dev, 3941 "failed loadfirmware of file %s\n", imagename); 3942 return (ENOENT); 3943 } 3944 3945 len = fw->datasize; 3946 3947 if (len < sizeof(*hdr)) { 3948 device_printf(sc->sc_dev, "firmware too short\n"); 3949 error = EINVAL; 3950 goto fail; 3951 } 3952 ptr = fw->data; 3953 hdr = (const struct r92c_fw_hdr *)ptr; 3954 /* Check if there is a valid FW header and skip it. */ 3955 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3956 (le16toh(hdr->signature) >> 4) == 0x88e || 3957 (le16toh(hdr->signature) >> 4) == 0x92c) { 3958 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, 3959 "FW V%d.%d %02d-%02d %02d:%02d\n", 3960 le16toh(hdr->version), le16toh(hdr->subversion), 3961 hdr->month, hdr->date, hdr->hour, hdr->minute); 3962 ptr += sizeof(*hdr); 3963 len -= sizeof(*hdr); 3964 } 3965 3966 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3967 if (sc->chip & URTWN_CHIP_88E) 3968 urtwn_r88e_fw_reset(sc); 3969 else 3970 urtwn_fw_reset(sc); 3971 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3972 } 3973 3974 if (!(sc->chip & URTWN_CHIP_88E)) { 3975 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3976 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3977 R92C_SYS_FUNC_EN_CPUEN); 3978 } 3979 urtwn_write_1(sc, R92C_MCUFWDL, 3980 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3981 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3982 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3983 3984 /* Reset the FWDL checksum. */ 3985 urtwn_write_1(sc, R92C_MCUFWDL, 3986 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3987 3988 for (page = 0; len > 0; page++) { 3989 mlen = min(len, R92C_FW_PAGE_SIZE); 3990 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3991 if (error != 0) { 3992 device_printf(sc->sc_dev, 3993 "could not load firmware page\n"); 3994 goto fail; 3995 } 3996 ptr += mlen; 3997 len -= mlen; 3998 } 3999 urtwn_write_1(sc, R92C_MCUFWDL, 4000 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 4001 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 4002 4003 /* Wait for checksum report. */ 4004 for (ntries = 0; ntries < 1000; ntries++) { 4005 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 4006 break; 4007 urtwn_ms_delay(sc); 4008 } 4009 if (ntries == 1000) { 4010 device_printf(sc->sc_dev, 4011 "timeout waiting for checksum report\n"); 4012 error = ETIMEDOUT; 4013 goto fail; 4014 } 4015 4016 reg = urtwn_read_4(sc, R92C_MCUFWDL); 4017 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 4018 urtwn_write_4(sc, R92C_MCUFWDL, reg); 4019 if (sc->chip & URTWN_CHIP_88E) 4020 urtwn_r88e_fw_reset(sc); 4021 /* Wait for firmware readiness. */ 4022 for (ntries = 0; ntries < 1000; ntries++) { 4023 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 4024 break; 4025 urtwn_ms_delay(sc); 4026 } 4027 if (ntries == 1000) { 4028 device_printf(sc->sc_dev, 4029 "timeout waiting for firmware readiness\n"); 4030 error = ETIMEDOUT; 4031 goto fail; 4032 } 4033fail: 4034 firmware_put(fw, FIRMWARE_UNLOAD); 4035 return (error); 4036} 4037#endif 4038 4039static int 4040urtwn_dma_init(struct urtwn_softc *sc) 4041{ 4042 struct usb_endpoint *ep, *ep_end; 4043 usb_error_t usb_err; 4044 uint32_t reg; 4045 int hashq, hasnq, haslq, nqueues, ntx; 4046 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 4047 4048 /* Initialize LLT table. */ 4049 error = urtwn_llt_init(sc); 4050 if (error != 0) 4051 return (error); 4052 4053 /* Determine the number of bulk-out pipes. */ 4054 ntx = 0; 4055 ep = sc->sc_udev->endpoints; 4056 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 4057 for (; ep != ep_end; ep++) { 4058 if ((ep->edesc == NULL) || 4059 (ep->iface_index != sc->sc_iface_index)) 4060 continue; 4061 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 4062 ntx++; 4063 } 4064 if (ntx == 0) { 4065 device_printf(sc->sc_dev, 4066 "%d: invalid number of Tx bulk pipes\n", ntx); 4067 return (EIO); 4068 } 4069 4070 /* Get Tx queues to USB endpoints mapping. */ 4071 hashq = hasnq = haslq = nqueues = 0; 4072 switch (ntx) { 4073 case 1: hashq = 1; break; 4074 case 2: hashq = hasnq = 1; break; 4075 case 3: case 4: hashq = hasnq = haslq = 1; break; 4076 } 4077 nqueues = hashq + hasnq + haslq; 4078 if (nqueues == 0) 4079 return (EIO); 4080 4081 npubqpages = nqpages = nrempages = pagecount = 0; 4082 if (sc->chip & URTWN_CHIP_88E) 4083 tx_boundary = R88E_TX_PAGE_BOUNDARY; 4084 else { 4085 pagecount = R92C_TX_PAGE_COUNT; 4086 npubqpages = R92C_PUBQ_NPAGES; 4087 tx_boundary = R92C_TX_PAGE_BOUNDARY; 4088 } 4089 4090 /* Set number of pages for normal priority queue. */ 4091 if (sc->chip & URTWN_CHIP_88E) { 4092 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 4093 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4094 return (EIO); 4095 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 4096 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4097 return (EIO); 4098 } else { 4099 /* Get the number of pages for each queue. */ 4100 nqpages = (pagecount - npubqpages) / nqueues; 4101 /* 4102 * The remaining pages are assigned to the high priority 4103 * queue. 4104 */ 4105 nrempages = (pagecount - npubqpages) % nqueues; 4106 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 4107 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4108 return (EIO); 4109 usb_err = urtwn_write_4(sc, R92C_RQPN, 4110 /* Set number of pages for public queue. */ 4111 SM(R92C_RQPN_PUBQ, npubqpages) | 4112 /* Set number of pages for high priority queue. */ 4113 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 4114 /* Set number of pages for low priority queue. */ 4115 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 4116 /* Load values. */ 4117 R92C_RQPN_LD); 4118 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4119 return (EIO); 4120 } 4121 4122 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 4123 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4124 return (EIO); 4125 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 4126 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4127 return (EIO); 4128 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 4129 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4130 return (EIO); 4131 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 4132 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4133 return (EIO); 4134 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 4135 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4136 return (EIO); 4137 4138 /* Set queue to USB pipe mapping. */ 4139 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4140 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4141 if (nqueues == 1) { 4142 if (hashq) 4143 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 4144 else if (hasnq) 4145 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 4146 else 4147 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4148 } else if (nqueues == 2) { 4149 /* 4150 * All 2-endpoints configs have high and normal 4151 * priority queues. 4152 */ 4153 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4154 } else 4155 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4156 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4157 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4158 return (EIO); 4159 4160 /* Set Tx/Rx transfer page boundary. */ 4161 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 4162 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 4163 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4164 return (EIO); 4165 4166 /* Set Tx/Rx transfer page size. */ 4167 usb_err = urtwn_write_1(sc, R92C_PBP, 4168 SM(R92C_PBP_PSRX, R92C_PBP_128) | 4169 SM(R92C_PBP_PSTX, R92C_PBP_128)); 4170 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4171 return (EIO); 4172 4173 return (0); 4174} 4175 4176static int 4177urtwn_mac_init(struct urtwn_softc *sc) 4178{ 4179 usb_error_t error; 4180 int i; 4181 4182 /* Write MAC initialization values. */ 4183 if (sc->chip & URTWN_CHIP_88E) { 4184 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 4185 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 4186 rtl8188eu_mac[i].val); 4187 if (error != USB_ERR_NORMAL_COMPLETION) 4188 return (EIO); 4189 } 4190 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 4191 } else { 4192 for (i = 0; i < nitems(rtl8192cu_mac); i++) 4193 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 4194 rtl8192cu_mac[i].val); 4195 if (error != USB_ERR_NORMAL_COMPLETION) 4196 return (EIO); 4197 } 4198 4199 return (0); 4200} 4201 4202static void 4203urtwn_bb_init(struct urtwn_softc *sc) 4204{ 4205 const struct urtwn_bb_prog *prog; 4206 uint32_t reg; 4207 uint8_t crystalcap; 4208 int i; 4209 4210 /* Enable BB and RF. */ 4211 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4212 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4213 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 4214 R92C_SYS_FUNC_EN_DIO_RF); 4215 4216 if (!(sc->chip & URTWN_CHIP_88E)) 4217 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 4218 4219 urtwn_write_1(sc, R92C_RF_CTRL, 4220 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 4221 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4222 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 4223 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 4224 4225 if (!(sc->chip & URTWN_CHIP_88E)) { 4226 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 4227 urtwn_write_1(sc, 0x15, 0xe9); 4228 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 4229 } 4230 4231 /* Select BB programming based on board type. */ 4232 if (sc->chip & URTWN_CHIP_88E) 4233 prog = &rtl8188eu_bb_prog; 4234 else if (!(sc->chip & URTWN_CHIP_92C)) { 4235 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4236 prog = &rtl8188ce_bb_prog; 4237 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4238 prog = &rtl8188ru_bb_prog; 4239 else 4240 prog = &rtl8188cu_bb_prog; 4241 } else { 4242 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4243 prog = &rtl8192ce_bb_prog; 4244 else 4245 prog = &rtl8192cu_bb_prog; 4246 } 4247 /* Write BB initialization values. */ 4248 for (i = 0; i < prog->count; i++) { 4249 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 4250 urtwn_ms_delay(sc); 4251 } 4252 4253 if (sc->chip & URTWN_CHIP_92C_1T2R) { 4254 /* 8192C 1T only configuration. */ 4255 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 4256 reg = (reg & ~0x00000003) | 0x2; 4257 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 4258 4259 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 4260 reg = (reg & ~0x00300033) | 0x00200022; 4261 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 4262 4263 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 4264 reg = (reg & ~0xff000000) | 0x45 << 24; 4265 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 4266 4267 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4268 reg = (reg & ~0x000000ff) | 0x23; 4269 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 4270 4271 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 4272 reg = (reg & ~0x00000030) | 1 << 4; 4273 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 4274 4275 reg = urtwn_bb_read(sc, 0xe74); 4276 reg = (reg & ~0x0c000000) | 2 << 26; 4277 urtwn_bb_write(sc, 0xe74, reg); 4278 reg = urtwn_bb_read(sc, 0xe78); 4279 reg = (reg & ~0x0c000000) | 2 << 26; 4280 urtwn_bb_write(sc, 0xe78, reg); 4281 reg = urtwn_bb_read(sc, 0xe7c); 4282 reg = (reg & ~0x0c000000) | 2 << 26; 4283 urtwn_bb_write(sc, 0xe7c, reg); 4284 reg = urtwn_bb_read(sc, 0xe80); 4285 reg = (reg & ~0x0c000000) | 2 << 26; 4286 urtwn_bb_write(sc, 0xe80, reg); 4287 reg = urtwn_bb_read(sc, 0xe88); 4288 reg = (reg & ~0x0c000000) | 2 << 26; 4289 urtwn_bb_write(sc, 0xe88, reg); 4290 } 4291 4292 /* Write AGC values. */ 4293 for (i = 0; i < prog->agccount; i++) { 4294 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 4295 prog->agcvals[i]); 4296 urtwn_ms_delay(sc); 4297 } 4298 4299 if (sc->chip & URTWN_CHIP_88E) { 4300 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4301 urtwn_ms_delay(sc); 4302 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4303 urtwn_ms_delay(sc); 4304 4305 crystalcap = sc->rom.r88e_rom.crystalcap; 4306 if (crystalcap == 0xff) 4307 crystalcap = 0x20; 4308 crystalcap &= 0x3f; 4309 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4310 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4311 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4312 crystalcap | crystalcap << 6)); 4313 } else { 4314 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4315 R92C_HSSI_PARAM2_CCK_HIPWR) 4316 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 4317 } 4318} 4319 4320static void 4321urtwn_rf_init(struct urtwn_softc *sc) 4322{ 4323 const struct urtwn_rf_prog *prog; 4324 uint32_t reg, type; 4325 int i, j, idx, off; 4326 4327 /* Select RF programming based on board type. */ 4328 if (sc->chip & URTWN_CHIP_88E) 4329 prog = rtl8188eu_rf_prog; 4330 else if (!(sc->chip & URTWN_CHIP_92C)) { 4331 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4332 prog = rtl8188ce_rf_prog; 4333 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4334 prog = rtl8188ru_rf_prog; 4335 else 4336 prog = rtl8188cu_rf_prog; 4337 } else 4338 prog = rtl8192ce_rf_prog; 4339 4340 for (i = 0; i < sc->nrxchains; i++) { 4341 /* Save RF_ENV control type. */ 4342 idx = i / 2; 4343 off = (i % 2) * 16; 4344 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4345 type = (reg >> off) & 0x10; 4346 4347 /* Set RF_ENV enable. */ 4348 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4349 reg |= 0x100000; 4350 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4351 urtwn_ms_delay(sc); 4352 /* Set RF_ENV output high. */ 4353 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4354 reg |= 0x10; 4355 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4356 urtwn_ms_delay(sc); 4357 /* Set address and data lengths of RF registers. */ 4358 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4359 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4360 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4361 urtwn_ms_delay(sc); 4362 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4363 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4364 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4365 urtwn_ms_delay(sc); 4366 4367 /* Write RF initialization values for this chain. */ 4368 for (j = 0; j < prog[i].count; j++) { 4369 if (prog[i].regs[j] >= 0xf9 && 4370 prog[i].regs[j] <= 0xfe) { 4371 /* 4372 * These are fake RF registers offsets that 4373 * indicate a delay is required. 4374 */ 4375 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 4376 continue; 4377 } 4378 urtwn_rf_write(sc, i, prog[i].regs[j], 4379 prog[i].vals[j]); 4380 urtwn_ms_delay(sc); 4381 } 4382 4383 /* Restore RF_ENV control type. */ 4384 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4385 reg &= ~(0x10 << off) | (type << off); 4386 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 4387 4388 /* Cache RF register CHNLBW. */ 4389 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4390 } 4391 4392 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4393 URTWN_CHIP_UMC_A_CUT) { 4394 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4395 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4396 } 4397} 4398 4399static void 4400urtwn_cam_init(struct urtwn_softc *sc) 4401{ 4402 /* Invalidate all CAM entries. */ 4403 urtwn_write_4(sc, R92C_CAMCMD, 4404 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4405} 4406 4407static int 4408urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 4409{ 4410 usb_error_t error; 4411 4412 error = urtwn_write_4(sc, R92C_CAMWRITE, data); 4413 if (error != USB_ERR_NORMAL_COMPLETION) 4414 return (EIO); 4415 error = urtwn_write_4(sc, R92C_CAMCMD, 4416 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 4417 SM(R92C_CAMCMD_ADDR, addr)); 4418 if (error != USB_ERR_NORMAL_COMPLETION) 4419 return (EIO); 4420 4421 return (0); 4422} 4423 4424static void 4425urtwn_pa_bias_init(struct urtwn_softc *sc) 4426{ 4427 uint8_t reg; 4428 int i; 4429 4430 for (i = 0; i < sc->nrxchains; i++) { 4431 if (sc->pa_setting & (1 << i)) 4432 continue; 4433 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4434 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4435 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4436 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4437 } 4438 if (!(sc->pa_setting & 0x10)) { 4439 reg = urtwn_read_1(sc, 0x16); 4440 reg = (reg & ~0xf0) | 0x90; 4441 urtwn_write_1(sc, 0x16, reg); 4442 } 4443} 4444 4445static void 4446urtwn_rxfilter_init(struct urtwn_softc *sc) 4447{ 4448 struct ieee80211com *ic = &sc->sc_ic; 4449 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4450 uint32_t rcr; 4451 uint16_t filter; 4452 4453 URTWN_ASSERT_LOCKED(sc); 4454 4455 /* Setup multicast filter. */ 4456 urtwn_set_multi(sc); 4457 4458 /* Filter for management frames. */ 4459 filter = 0x7f3f; 4460 switch (vap->iv_opmode) { 4461 case IEEE80211_M_STA: 4462 filter &= ~( 4463 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 4464 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 4465 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 4466 break; 4467 case IEEE80211_M_HOSTAP: 4468 filter &= ~( 4469 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 4470 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP)); 4471 break; 4472 case IEEE80211_M_MONITOR: 4473 case IEEE80211_M_IBSS: 4474 break; 4475 default: 4476 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4477 __func__, vap->iv_opmode); 4478 break; 4479 } 4480 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 4481 4482 /* Reject all control frames. */ 4483 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4484 4485 /* Reject all data frames. */ 4486 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 4487 4488 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 4489 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 4490 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 4491 4492 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 4493 /* Accept all frames. */ 4494 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 4495 R92C_RCR_AAP; 4496 } 4497 4498 /* Set Rx filter. */ 4499 urtwn_write_4(sc, R92C_RCR, rcr); 4500 4501 if (ic->ic_promisc != 0) { 4502 /* Update Rx filter. */ 4503 urtwn_set_promisc(sc); 4504 } 4505} 4506 4507static void 4508urtwn_edca_init(struct urtwn_softc *sc) 4509{ 4510 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4511 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4512 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4513 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4514 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4515 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4516 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4517 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4518} 4519 4520static void 4521urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4522 uint16_t power[URTWN_RIDX_COUNT]) 4523{ 4524 uint32_t reg; 4525 4526 /* Write per-CCK rate Tx power. */ 4527 if (chain == 0) { 4528 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4529 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4530 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4531 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4532 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4533 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4534 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4535 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4536 } else { 4537 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4538 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4539 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4540 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4541 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4542 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4543 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4544 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4545 } 4546 /* Write per-OFDM rate Tx power. */ 4547 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4548 SM(R92C_TXAGC_RATE06, power[ 4]) | 4549 SM(R92C_TXAGC_RATE09, power[ 5]) | 4550 SM(R92C_TXAGC_RATE12, power[ 6]) | 4551 SM(R92C_TXAGC_RATE18, power[ 7])); 4552 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4553 SM(R92C_TXAGC_RATE24, power[ 8]) | 4554 SM(R92C_TXAGC_RATE36, power[ 9]) | 4555 SM(R92C_TXAGC_RATE48, power[10]) | 4556 SM(R92C_TXAGC_RATE54, power[11])); 4557 /* Write per-MCS Tx power. */ 4558 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4559 SM(R92C_TXAGC_MCS00, power[12]) | 4560 SM(R92C_TXAGC_MCS01, power[13]) | 4561 SM(R92C_TXAGC_MCS02, power[14]) | 4562 SM(R92C_TXAGC_MCS03, power[15])); 4563 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4564 SM(R92C_TXAGC_MCS04, power[16]) | 4565 SM(R92C_TXAGC_MCS05, power[17]) | 4566 SM(R92C_TXAGC_MCS06, power[18]) | 4567 SM(R92C_TXAGC_MCS07, power[19])); 4568 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4569 SM(R92C_TXAGC_MCS08, power[20]) | 4570 SM(R92C_TXAGC_MCS09, power[21]) | 4571 SM(R92C_TXAGC_MCS10, power[22]) | 4572 SM(R92C_TXAGC_MCS11, power[23])); 4573 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4574 SM(R92C_TXAGC_MCS12, power[24]) | 4575 SM(R92C_TXAGC_MCS13, power[25]) | 4576 SM(R92C_TXAGC_MCS14, power[26]) | 4577 SM(R92C_TXAGC_MCS15, power[27])); 4578} 4579 4580static void 4581urtwn_get_txpower(struct urtwn_softc *sc, int chain, 4582 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4583 uint16_t power[URTWN_RIDX_COUNT]) 4584{ 4585 struct ieee80211com *ic = &sc->sc_ic; 4586 struct r92c_rom *rom = &sc->rom.r92c_rom; 4587 uint16_t cckpow, ofdmpow, htpow, diff, max; 4588 const struct urtwn_txpwr *base; 4589 int ridx, chan, group; 4590 4591 /* Determine channel group. */ 4592 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4593 if (chan <= 3) 4594 group = 0; 4595 else if (chan <= 9) 4596 group = 1; 4597 else 4598 group = 2; 4599 4600 /* Get original Tx power based on board type and RF chain. */ 4601 if (!(sc->chip & URTWN_CHIP_92C)) { 4602 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4603 base = &rtl8188ru_txagc[chain]; 4604 else 4605 base = &rtl8192cu_txagc[chain]; 4606 } else 4607 base = &rtl8192cu_txagc[chain]; 4608 4609 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4610 if (sc->regulatory == 0) { 4611 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4612 power[ridx] = base->pwr[0][ridx]; 4613 } 4614 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4615 if (sc->regulatory == 3) { 4616 power[ridx] = base->pwr[0][ridx]; 4617 /* Apply vendor limits. */ 4618 if (extc != NULL) 4619 max = rom->ht40_max_pwr[group]; 4620 else 4621 max = rom->ht20_max_pwr[group]; 4622 max = (max >> (chain * 4)) & 0xf; 4623 if (power[ridx] > max) 4624 power[ridx] = max; 4625 } else if (sc->regulatory == 1) { 4626 if (extc == NULL) 4627 power[ridx] = base->pwr[group][ridx]; 4628 } else if (sc->regulatory != 2) 4629 power[ridx] = base->pwr[0][ridx]; 4630 } 4631 4632 /* Compute per-CCK rate Tx power. */ 4633 cckpow = rom->cck_tx_pwr[chain][group]; 4634 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4635 power[ridx] += cckpow; 4636 if (power[ridx] > R92C_MAX_TX_PWR) 4637 power[ridx] = R92C_MAX_TX_PWR; 4638 } 4639 4640 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4641 if (sc->ntxchains > 1) { 4642 /* Apply reduction for 2 spatial streams. */ 4643 diff = rom->ht40_2s_tx_pwr_diff[group]; 4644 diff = (diff >> (chain * 4)) & 0xf; 4645 htpow = (htpow > diff) ? htpow - diff : 0; 4646 } 4647 4648 /* Compute per-OFDM rate Tx power. */ 4649 diff = rom->ofdm_tx_pwr_diff[group]; 4650 diff = (diff >> (chain * 4)) & 0xf; 4651 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4652 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4653 power[ridx] += ofdmpow; 4654 if (power[ridx] > R92C_MAX_TX_PWR) 4655 power[ridx] = R92C_MAX_TX_PWR; 4656 } 4657 4658 /* Compute per-MCS Tx power. */ 4659 if (extc == NULL) { 4660 diff = rom->ht20_tx_pwr_diff[group]; 4661 diff = (diff >> (chain * 4)) & 0xf; 4662 htpow += diff; /* HT40->HT20 correction. */ 4663 } 4664 for (ridx = 12; ridx <= 27; ridx++) { 4665 power[ridx] += htpow; 4666 if (power[ridx] > R92C_MAX_TX_PWR) 4667 power[ridx] = R92C_MAX_TX_PWR; 4668 } 4669#ifdef USB_DEBUG 4670 if (sc->sc_debug & URTWN_DEBUG_TXPWR) { 4671 /* Dump per-rate Tx power values. */ 4672 printf("Tx power for chain %d:\n", chain); 4673 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 4674 printf("Rate %d = %u\n", ridx, power[ridx]); 4675 } 4676#endif 4677} 4678 4679static void 4680urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 4681 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4682 uint16_t power[URTWN_RIDX_COUNT]) 4683{ 4684 struct ieee80211com *ic = &sc->sc_ic; 4685 struct r88e_rom *rom = &sc->rom.r88e_rom; 4686 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4687 const struct urtwn_r88e_txpwr *base; 4688 int ridx, chan, group; 4689 4690 /* Determine channel group. */ 4691 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4692 if (chan <= 2) 4693 group = 0; 4694 else if (chan <= 5) 4695 group = 1; 4696 else if (chan <= 8) 4697 group = 2; 4698 else if (chan <= 11) 4699 group = 3; 4700 else if (chan <= 13) 4701 group = 4; 4702 else 4703 group = 5; 4704 4705 /* Get original Tx power based on board type and RF chain. */ 4706 base = &rtl8188eu_txagc[chain]; 4707 4708 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4709 if (sc->regulatory == 0) { 4710 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4711 power[ridx] = base->pwr[0][ridx]; 4712 } 4713 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4714 if (sc->regulatory == 3) 4715 power[ridx] = base->pwr[0][ridx]; 4716 else if (sc->regulatory == 1) { 4717 if (extc == NULL) 4718 power[ridx] = base->pwr[group][ridx]; 4719 } else if (sc->regulatory != 2) 4720 power[ridx] = base->pwr[0][ridx]; 4721 } 4722 4723 /* Compute per-CCK rate Tx power. */ 4724 cckpow = rom->cck_tx_pwr[group]; 4725 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4726 power[ridx] += cckpow; 4727 if (power[ridx] > R92C_MAX_TX_PWR) 4728 power[ridx] = R92C_MAX_TX_PWR; 4729 } 4730 4731 htpow = rom->ht40_tx_pwr[group]; 4732 4733 /* Compute per-OFDM rate Tx power. */ 4734 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4735 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4736 power[ridx] += ofdmpow; 4737 if (power[ridx] > R92C_MAX_TX_PWR) 4738 power[ridx] = R92C_MAX_TX_PWR; 4739 } 4740 4741 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4742 for (ridx = 12; ridx <= 27; ridx++) { 4743 power[ridx] += bw20pow; 4744 if (power[ridx] > R92C_MAX_TX_PWR) 4745 power[ridx] = R92C_MAX_TX_PWR; 4746 } 4747} 4748 4749static void 4750urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 4751 struct ieee80211_channel *extc) 4752{ 4753 uint16_t power[URTWN_RIDX_COUNT]; 4754 int i; 4755 4756 for (i = 0; i < sc->ntxchains; i++) { 4757 /* Compute per-rate Tx power values. */ 4758 if (sc->chip & URTWN_CHIP_88E) 4759 urtwn_r88e_get_txpower(sc, i, c, extc, power); 4760 else 4761 urtwn_get_txpower(sc, i, c, extc, power); 4762 /* Write per-rate Tx power values to hardware. */ 4763 urtwn_write_txpower(sc, i, power); 4764 } 4765} 4766 4767static void 4768urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 4769{ 4770 uint32_t reg; 4771 4772 reg = urtwn_read_4(sc, R92C_RCR); 4773 if (enable) 4774 reg &= ~R92C_RCR_CBSSID_BCN; 4775 else 4776 reg |= R92C_RCR_CBSSID_BCN; 4777 urtwn_write_4(sc, R92C_RCR, reg); 4778} 4779 4780static void 4781urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 4782{ 4783 uint32_t reg; 4784 4785 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 4786 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4787 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 4788 4789 if (!(sc->chip & URTWN_CHIP_88E)) { 4790 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 4791 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4792 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 4793 } 4794} 4795 4796static void 4797urtwn_scan_start(struct ieee80211com *ic) 4798{ 4799 struct urtwn_softc *sc = ic->ic_softc; 4800 4801 URTWN_LOCK(sc); 4802 /* Receive beacons / probe responses from any BSSID. */ 4803 if (ic->ic_opmode != IEEE80211_M_IBSS && 4804 ic->ic_opmode != IEEE80211_M_HOSTAP) 4805 urtwn_set_rx_bssid_all(sc, 1); 4806 4807 /* Set gain for scanning. */ 4808 urtwn_set_gain(sc, 0x20); 4809 URTWN_UNLOCK(sc); 4810} 4811 4812static void 4813urtwn_scan_end(struct ieee80211com *ic) 4814{ 4815 struct urtwn_softc *sc = ic->ic_softc; 4816 4817 URTWN_LOCK(sc); 4818 /* Restore limitations. */ 4819 if (ic->ic_promisc == 0 && 4820 ic->ic_opmode != IEEE80211_M_IBSS && 4821 ic->ic_opmode != IEEE80211_M_HOSTAP) 4822 urtwn_set_rx_bssid_all(sc, 0); 4823 4824 /* Set gain under link. */ 4825 urtwn_set_gain(sc, 0x32); 4826 URTWN_UNLOCK(sc); 4827} 4828 4829static void 4830urtwn_getradiocaps(struct ieee80211com *ic, 4831 int maxchans, int *nchans, struct ieee80211_channel chans[]) 4832{ 4833 uint8_t bands[IEEE80211_MODE_BYTES]; 4834 4835 memset(bands, 0, sizeof(bands)); 4836 setbit(bands, IEEE80211_MODE_11B); 4837 setbit(bands, IEEE80211_MODE_11G); 4838 if (urtwn_enable_11n) 4839 setbit(bands, IEEE80211_MODE_11NG); 4840 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 4841 urtwn_chan_2ghz, nitems(urtwn_chan_2ghz), bands, 0); 4842} 4843 4844static void 4845urtwn_set_channel(struct ieee80211com *ic) 4846{ 4847 struct urtwn_softc *sc = ic->ic_softc; 4848 struct ieee80211_channel *c = ic->ic_curchan; 4849 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4850 4851 URTWN_LOCK(sc); 4852 if (vap->iv_state == IEEE80211_S_SCAN) { 4853 /* Make link LED blink during scan. */ 4854 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 4855 } 4856 urtwn_set_chan(sc, c, NULL); 4857 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 4858 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 4859 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 4860 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 4861 URTWN_UNLOCK(sc); 4862} 4863 4864static int 4865urtwn_wme_update(struct ieee80211com *ic) 4866{ 4867 const struct wmeParams *wmep = 4868 ic->ic_wme.wme_chanParams.cap_wmeParams; 4869 struct urtwn_softc *sc = ic->ic_softc; 4870 uint8_t aifs, acm, slottime; 4871 int ac; 4872 4873 acm = 0; 4874 slottime = IEEE80211_GET_SLOTTIME(ic); 4875 4876 URTWN_LOCK(sc); 4877 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4878 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4879 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4880 urtwn_write_4(sc, wme2queue[ac].reg, 4881 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 4882 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 4883 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 4884 SM(R92C_EDCA_PARAM_AIFS, aifs)); 4885 if (ac != WME_AC_BE) 4886 acm |= wmep[ac].wmep_acm << ac; 4887 } 4888 4889 if (acm != 0) 4890 acm |= R92C_ACMHWCTRL_EN; 4891 urtwn_write_1(sc, R92C_ACMHWCTRL, 4892 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 4893 acm); 4894 4895 URTWN_UNLOCK(sc); 4896 4897 return 0; 4898} 4899 4900static void 4901urtwn_update_slot(struct ieee80211com *ic) 4902{ 4903 urtwn_cmd_sleepable(ic->ic_softc, NULL, 0, urtwn_update_slot_cb); 4904} 4905 4906static void 4907urtwn_update_slot_cb(struct urtwn_softc *sc, union sec_param *data) 4908{ 4909 struct ieee80211com *ic = &sc->sc_ic; 4910 uint8_t slottime; 4911 4912 slottime = IEEE80211_GET_SLOTTIME(ic); 4913 4914 URTWN_DPRINTF(sc, URTWN_DEBUG_ANY, "%s: setting slot time to %uus\n", 4915 __func__, slottime); 4916 4917 urtwn_write_1(sc, R92C_SLOT, slottime); 4918 urtwn_update_aifs(sc, slottime); 4919} 4920 4921static void 4922urtwn_update_aifs(struct urtwn_softc *sc, uint8_t slottime) 4923{ 4924 const struct wmeParams *wmep = 4925 sc->sc_ic.ic_wme.wme_chanParams.cap_wmeParams; 4926 uint8_t aifs, ac; 4927 4928 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4929 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4930 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4931 urtwn_write_1(sc, wme2queue[ac].reg, aifs); 4932 } 4933} 4934 4935static uint8_t 4936urtwn_get_multi_pos(const uint8_t maddr[]) 4937{ 4938 uint64_t mask = 0x00004d101df481b4; 4939 uint8_t pos = 0x27; /* initial value */ 4940 int i, j; 4941 4942 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 4943 for (j = (i == 0) ? 1 : 0; j < 8; j++) 4944 if ((maddr[i] >> j) & 1) 4945 pos ^= (mask >> (i * 8 + j - 1)); 4946 4947 pos &= 0x3f; 4948 4949 return (pos); 4950} 4951 4952static void 4953urtwn_set_multi(struct urtwn_softc *sc) 4954{ 4955 struct ieee80211com *ic = &sc->sc_ic; 4956 uint32_t mfilt[2]; 4957 4958 URTWN_ASSERT_LOCKED(sc); 4959 4960 /* general structure was copied from ath(4). */ 4961 if (ic->ic_allmulti == 0) { 4962 struct ieee80211vap *vap; 4963 struct ifnet *ifp; 4964 struct ifmultiaddr *ifma; 4965 4966 /* 4967 * Merge multicast addresses to form the hardware filter. 4968 */ 4969 mfilt[0] = mfilt[1] = 0; 4970 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 4971 ifp = vap->iv_ifp; 4972 if_maddr_rlock(ifp); 4973 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4974 caddr_t dl; 4975 uint8_t pos; 4976 4977 dl = LLADDR((struct sockaddr_dl *) 4978 ifma->ifma_addr); 4979 pos = urtwn_get_multi_pos(dl); 4980 4981 mfilt[pos / 32] |= (1 << (pos % 32)); 4982 } 4983 if_maddr_runlock(ifp); 4984 } 4985 } else 4986 mfilt[0] = mfilt[1] = ~0; 4987 4988 4989 urtwn_write_4(sc, R92C_MAR + 0, mfilt[0]); 4990 urtwn_write_4(sc, R92C_MAR + 4, mfilt[1]); 4991 4992 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s: MC filter %08x:%08x\n", 4993 __func__, mfilt[0], mfilt[1]); 4994} 4995 4996static void 4997urtwn_set_promisc(struct urtwn_softc *sc) 4998{ 4999 struct ieee80211com *ic = &sc->sc_ic; 5000 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5001 uint32_t rcr, mask1, mask2; 5002 5003 URTWN_ASSERT_LOCKED(sc); 5004 5005 if (vap->iv_opmode == IEEE80211_M_MONITOR) 5006 return; 5007 5008 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 5009 mask2 = R92C_RCR_APM; 5010 5011 if (vap->iv_state == IEEE80211_S_RUN) { 5012 switch (vap->iv_opmode) { 5013 case IEEE80211_M_STA: 5014 mask2 |= R92C_RCR_CBSSID_BCN; 5015 /* FALLTHROUGH */ 5016 case IEEE80211_M_IBSS: 5017 mask2 |= R92C_RCR_CBSSID_DATA; 5018 break; 5019 case IEEE80211_M_HOSTAP: 5020 break; 5021 default: 5022 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 5023 __func__, vap->iv_opmode); 5024 return; 5025 } 5026 } 5027 5028 rcr = urtwn_read_4(sc, R92C_RCR); 5029 if (ic->ic_promisc == 0) 5030 rcr = (rcr & ~mask1) | mask2; 5031 else 5032 rcr = (rcr & ~mask2) | mask1; 5033 urtwn_write_4(sc, R92C_RCR, rcr); 5034} 5035 5036static void 5037urtwn_update_promisc(struct ieee80211com *ic) 5038{ 5039 struct urtwn_softc *sc = ic->ic_softc; 5040 5041 URTWN_LOCK(sc); 5042 if (sc->sc_flags & URTWN_RUNNING) 5043 urtwn_set_promisc(sc); 5044 URTWN_UNLOCK(sc); 5045} 5046 5047static void 5048urtwn_update_mcast(struct ieee80211com *ic) 5049{ 5050 struct urtwn_softc *sc = ic->ic_softc; 5051 5052 URTWN_LOCK(sc); 5053 if (sc->sc_flags & URTWN_RUNNING) 5054 urtwn_set_multi(sc); 5055 URTWN_UNLOCK(sc); 5056} 5057 5058static struct ieee80211_node * 5059urtwn_node_alloc(struct ieee80211vap *vap, 5060 const uint8_t mac[IEEE80211_ADDR_LEN]) 5061{ 5062 struct urtwn_node *un; 5063 5064 un = malloc(sizeof (struct urtwn_node), M_80211_NODE, 5065 M_NOWAIT | M_ZERO); 5066 5067 if (un == NULL) 5068 return NULL; 5069 5070 un->id = URTWN_MACID_UNDEFINED; 5071 5072 return &un->ni; 5073} 5074 5075static void 5076urtwn_newassoc(struct ieee80211_node *ni, int isnew) 5077{ 5078 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 5079 struct urtwn_node *un = URTWN_NODE(ni); 5080 uint8_t id; 5081 5082 /* Only do this bit for R88E chips */ 5083 if (! (sc->chip & URTWN_CHIP_88E)) 5084 return; 5085 5086 if (!isnew) 5087 return; 5088 5089 URTWN_NT_LOCK(sc); 5090 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 5091 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 5092 un->id = id; 5093 sc->node_list[id] = ni; 5094 break; 5095 } 5096 } 5097 URTWN_NT_UNLOCK(sc); 5098 5099 if (id > URTWN_MACID_MAX(sc)) { 5100 device_printf(sc->sc_dev, "%s: node table is full\n", 5101 __func__); 5102 } 5103} 5104 5105static void 5106urtwn_node_free(struct ieee80211_node *ni) 5107{ 5108 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 5109 struct urtwn_node *un = URTWN_NODE(ni); 5110 5111 URTWN_NT_LOCK(sc); 5112 if (un->id != URTWN_MACID_UNDEFINED) 5113 sc->node_list[un->id] = NULL; 5114 URTWN_NT_UNLOCK(sc); 5115 5116 sc->sc_node_free(ni); 5117} 5118 5119static void 5120urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 5121 struct ieee80211_channel *extc) 5122{ 5123 struct ieee80211com *ic = &sc->sc_ic; 5124 uint32_t reg; 5125 u_int chan; 5126 int i; 5127 5128 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 5129 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 5130 device_printf(sc->sc_dev, 5131 "%s: invalid channel %x\n", __func__, chan); 5132 return; 5133 } 5134 5135 /* Set Tx power for this new channel. */ 5136 urtwn_set_txpower(sc, c, extc); 5137 5138 for (i = 0; i < sc->nrxchains; i++) { 5139 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 5140 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 5141 } 5142#ifndef IEEE80211_NO_HT 5143 if (extc != NULL) { 5144 /* Is secondary channel below or above primary? */ 5145 int prichlo = c->ic_freq < extc->ic_freq; 5146 5147 urtwn_write_1(sc, R92C_BWOPMODE, 5148 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 5149 5150 reg = urtwn_read_1(sc, R92C_RRSR + 2); 5151 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 5152 urtwn_write_1(sc, R92C_RRSR + 2, reg); 5153 5154 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5155 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 5156 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5157 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 5158 5159 /* Set CCK side band. */ 5160 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 5161 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 5162 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 5163 5164 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 5165 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 5166 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 5167 5168 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5169 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 5170 ~R92C_FPGA0_ANAPARAM2_CBW20); 5171 5172 reg = urtwn_bb_read(sc, 0x818); 5173 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 5174 urtwn_bb_write(sc, 0x818, reg); 5175 5176 /* Select 40MHz bandwidth. */ 5177 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5178 (sc->rf_chnlbw[0] & ~0xfff) | chan); 5179 } else 5180#endif 5181 { 5182 urtwn_write_1(sc, R92C_BWOPMODE, 5183 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 5184 5185 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5186 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 5187 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5188 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 5189 5190 if (!(sc->chip & URTWN_CHIP_88E)) { 5191 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5192 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 5193 R92C_FPGA0_ANAPARAM2_CBW20); 5194 } 5195 5196 /* Select 20MHz bandwidth. */ 5197 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5198 (sc->rf_chnlbw[0] & ~0xfff) | chan | 5199 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 5200 R92C_RF_CHNLBW_BW20)); 5201 } 5202} 5203 5204static void 5205urtwn_iq_calib(struct urtwn_softc *sc) 5206{ 5207 /* TODO */ 5208} 5209 5210static void 5211urtwn_lc_calib(struct urtwn_softc *sc) 5212{ 5213 uint32_t rf_ac[2]; 5214 uint8_t txmode; 5215 int i; 5216 5217 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 5218 if ((txmode & 0x70) != 0) { 5219 /* Disable all continuous Tx. */ 5220 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 5221 5222 /* Set RF mode to standby mode. */ 5223 for (i = 0; i < sc->nrxchains; i++) { 5224 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 5225 urtwn_rf_write(sc, i, R92C_RF_AC, 5226 RW(rf_ac[i], R92C_RF_AC_MODE, 5227 R92C_RF_AC_MODE_STANDBY)); 5228 } 5229 } else { 5230 /* Block all Tx queues. */ 5231 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 5232 } 5233 /* Start calibration. */ 5234 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5235 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 5236 5237 /* Give calibration the time to complete. */ 5238 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 5239 5240 /* Restore configuration. */ 5241 if ((txmode & 0x70) != 0) { 5242 /* Restore Tx mode. */ 5243 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 5244 /* Restore RF mode. */ 5245 for (i = 0; i < sc->nrxchains; i++) 5246 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 5247 } else { 5248 /* Unblock all Tx queues. */ 5249 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 5250 } 5251} 5252 5253static void 5254urtwn_temp_calib(struct urtwn_softc *sc) 5255{ 5256 uint8_t temp; 5257 5258 URTWN_ASSERT_LOCKED(sc); 5259 5260 if (!(sc->sc_flags & URTWN_TEMP_MEASURED)) { 5261 /* Start measuring temperature. */ 5262 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5263 "%s: start measuring temperature\n", __func__); 5264 if (sc->chip & URTWN_CHIP_88E) { 5265 urtwn_rf_write(sc, 0, R88E_RF_T_METER, 5266 R88E_RF_T_METER_START); 5267 } else { 5268 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 5269 R92C_RF_T_METER_START); 5270 } 5271 sc->sc_flags |= URTWN_TEMP_MEASURED; 5272 return; 5273 } 5274 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 5275 5276 /* Read measured temperature. */ 5277 if (sc->chip & URTWN_CHIP_88E) { 5278 temp = MS(urtwn_rf_read(sc, 0, R88E_RF_T_METER), 5279 R88E_RF_T_METER_VAL); 5280 } else { 5281 temp = MS(urtwn_rf_read(sc, 0, R92C_RF_T_METER), 5282 R92C_RF_T_METER_VAL); 5283 } 5284 if (temp == 0) { /* Read failed, skip. */ 5285 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5286 "%s: temperature read failed, skipping\n", __func__); 5287 return; 5288 } 5289 5290 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5291 "%s: temperature: previous %u, current %u\n", 5292 __func__, sc->thcal_lctemp, temp); 5293 5294 /* 5295 * Redo LC calibration if temperature changed significantly since 5296 * last calibration. 5297 */ 5298 if (sc->thcal_lctemp == 0) { 5299 /* First LC calibration is performed in urtwn_init(). */ 5300 sc->thcal_lctemp = temp; 5301 } else if (abs(temp - sc->thcal_lctemp) > 1) { 5302 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5303 "%s: LC calib triggered by temp: %u -> %u\n", 5304 __func__, sc->thcal_lctemp, temp); 5305 urtwn_lc_calib(sc); 5306 /* Record temperature of last LC calibration. */ 5307 sc->thcal_lctemp = temp; 5308 } 5309} 5310 5311static void 5312urtwn_setup_static_keys(struct urtwn_softc *sc, struct urtwn_vap *uvp) 5313{ 5314 int i; 5315 5316 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 5317 const struct ieee80211_key *k = uvp->keys[i]; 5318 if (k != NULL) { 5319 urtwn_cmd_sleepable(sc, k, sizeof(*k), 5320 urtwn_key_set_cb); 5321 } 5322 } 5323} 5324 5325static int 5326urtwn_init(struct urtwn_softc *sc) 5327{ 5328 struct ieee80211com *ic = &sc->sc_ic; 5329 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5330 uint8_t macaddr[IEEE80211_ADDR_LEN]; 5331 uint32_t reg; 5332 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 5333 int error; 5334 5335 URTWN_LOCK(sc); 5336 if (sc->sc_flags & URTWN_RUNNING) { 5337 URTWN_UNLOCK(sc); 5338 return (0); 5339 } 5340 5341 /* Init firmware commands ring. */ 5342 sc->fwcur = 0; 5343 5344 /* Allocate Tx/Rx buffers. */ 5345 error = urtwn_alloc_rx_list(sc); 5346 if (error != 0) 5347 goto fail; 5348 5349 error = urtwn_alloc_tx_list(sc); 5350 if (error != 0) 5351 goto fail; 5352 5353 /* Power on adapter. */ 5354 error = urtwn_power_on(sc); 5355 if (error != 0) 5356 goto fail; 5357 5358 /* Initialize DMA. */ 5359 error = urtwn_dma_init(sc); 5360 if (error != 0) 5361 goto fail; 5362 5363 /* Set info size in Rx descriptors (in 64-bit words). */ 5364 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 5365 5366 /* Init interrupts. */ 5367 if (sc->chip & URTWN_CHIP_88E) { 5368 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 5369 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5370 goto fail; 5371 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 5372 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 5373 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5374 goto fail; 5375 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 5376 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 5377 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5378 goto fail; 5379 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5380 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5381 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 5382 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5383 goto fail; 5384 } else { 5385 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 5386 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5387 goto fail; 5388 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 5389 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5390 goto fail; 5391 } 5392 5393 /* Set MAC address. */ 5394 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 5395 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 5396 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5397 goto fail; 5398 5399 /* Set initial network type. */ 5400 urtwn_set_mode(sc, R92C_MSR_INFRA); 5401 5402 /* Initialize Rx filter. */ 5403 urtwn_rxfilter_init(sc); 5404 5405 /* Set response rate. */ 5406 reg = urtwn_read_4(sc, R92C_RRSR); 5407 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5408 urtwn_write_4(sc, R92C_RRSR, reg); 5409 5410 /* Set short/long retry limits. */ 5411 urtwn_write_2(sc, R92C_RL, 5412 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5413 5414 /* Initialize EDCA parameters. */ 5415 urtwn_edca_init(sc); 5416 5417 /* Setup rate fallback. */ 5418 if (!(sc->chip & URTWN_CHIP_88E)) { 5419 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5420 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5421 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5422 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5423 } 5424 5425 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5426 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5427 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5428 /* Set ACK timeout. */ 5429 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5430 5431 /* Setup USB aggregation. */ 5432 reg = urtwn_read_4(sc, R92C_TDECTRL); 5433 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5434 urtwn_write_4(sc, R92C_TDECTRL, reg); 5435 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5436 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5437 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5438 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5439 if (sc->chip & URTWN_CHIP_88E) 5440 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5441 else { 5442 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5443 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5444 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5445 R92C_USB_SPECIAL_OPTION_AGG_EN); 5446 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 5447 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 5448 } 5449 5450 /* Initialize beacon parameters. */ 5451 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5452 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5453 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 5454 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 5455 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5456 5457 if (!(sc->chip & URTWN_CHIP_88E)) { 5458 /* Setup AMPDU aggregation. */ 5459 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5460 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5461 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 5462 5463 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5464 } 5465 5466#ifndef URTWN_WITHOUT_UCODE 5467 /* Load 8051 microcode. */ 5468 error = urtwn_load_firmware(sc); 5469 if (error == 0) 5470 sc->sc_flags |= URTWN_FW_LOADED; 5471#endif 5472 5473 /* Initialize MAC/BB/RF blocks. */ 5474 error = urtwn_mac_init(sc); 5475 if (error != 0) { 5476 device_printf(sc->sc_dev, 5477 "%s: error while initializing MAC block\n", __func__); 5478 goto fail; 5479 } 5480 urtwn_bb_init(sc); 5481 urtwn_rf_init(sc); 5482 5483 /* Reinitialize Rx filter (D3845 is not committed yet). */ 5484 urtwn_rxfilter_init(sc); 5485 5486 if (sc->chip & URTWN_CHIP_88E) { 5487 urtwn_write_2(sc, R92C_CR, 5488 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5489 R92C_CR_MACRXEN); 5490 } 5491 5492 /* Turn CCK and OFDM blocks on. */ 5493 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5494 reg |= R92C_RFMOD_CCK_EN; 5495 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5496 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5497 goto fail; 5498 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5499 reg |= R92C_RFMOD_OFDM_EN; 5500 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5501 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5502 goto fail; 5503 5504 /* Clear per-station keys table. */ 5505 urtwn_cam_init(sc); 5506 5507 /* Enable decryption / encryption. */ 5508 urtwn_write_2(sc, R92C_SECCFG, 5509 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 5510 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA | 5511 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 5512 5513 /* Enable hardware sequence numbering. */ 5514 urtwn_write_1(sc, R92C_HWSEQ_CTRL, R92C_TX_QUEUE_ALL); 5515 5516 /* Enable per-packet TX report. */ 5517 if (sc->chip & URTWN_CHIP_88E) { 5518 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 5519 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 5520 } 5521 5522 /* Perform LO and IQ calibrations. */ 5523 urtwn_iq_calib(sc); 5524 /* Perform LC calibration. */ 5525 urtwn_lc_calib(sc); 5526 5527 /* Fix USB interference issue. */ 5528 if (!(sc->chip & URTWN_CHIP_88E)) { 5529 urtwn_write_1(sc, 0xfe40, 0xe0); 5530 urtwn_write_1(sc, 0xfe41, 0x8d); 5531 urtwn_write_1(sc, 0xfe42, 0x80); 5532 5533 urtwn_pa_bias_init(sc); 5534 } 5535 5536 /* Initialize GPIO setting. */ 5537 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5538 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5539 5540 /* Fix for lower temperature. */ 5541 if (!(sc->chip & URTWN_CHIP_88E)) 5542 urtwn_write_1(sc, 0x15, 0xe9); 5543 5544 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 5545 5546 sc->sc_flags |= URTWN_RUNNING; 5547 5548 /* 5549 * Install static keys (if any). 5550 * Must be called after urtwn_cam_init(). 5551 */ 5552 if (vap != NULL) 5553 urtwn_setup_static_keys(sc, URTWN_VAP(vap)); 5554 5555 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5556fail: 5557 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5558 error = EIO; 5559 5560 URTWN_UNLOCK(sc); 5561 5562 return (error); 5563} 5564 5565static void 5566urtwn_stop(struct urtwn_softc *sc) 5567{ 5568 5569 URTWN_LOCK(sc); 5570 if (!(sc->sc_flags & URTWN_RUNNING)) { 5571 URTWN_UNLOCK(sc); 5572 return; 5573 } 5574 5575 sc->sc_flags &= ~(URTWN_RUNNING | URTWN_FW_LOADED | 5576 URTWN_TEMP_MEASURED); 5577 sc->thcal_lctemp = 0; 5578 callout_stop(&sc->sc_watchdog_ch); 5579 5580 urtwn_abort_xfers(sc); 5581 urtwn_drain_mbufq(sc); 5582 urtwn_power_off(sc); 5583 URTWN_UNLOCK(sc); 5584} 5585 5586static void 5587urtwn_abort_xfers(struct urtwn_softc *sc) 5588{ 5589 int i; 5590 5591 URTWN_ASSERT_LOCKED(sc); 5592 5593 /* abort any pending transfers */ 5594 for (i = 0; i < URTWN_N_TRANSFER; i++) 5595 usbd_transfer_stop(sc->sc_xfer[i]); 5596} 5597 5598static int 5599urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5600 const struct ieee80211_bpf_params *params) 5601{ 5602 struct ieee80211com *ic = ni->ni_ic; 5603 struct urtwn_softc *sc = ic->ic_softc; 5604 struct urtwn_data *bf; 5605 int error; 5606 5607 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n", 5608 __func__, 5609 m); 5610 5611 /* prevent management frames from being sent if we're not ready */ 5612 URTWN_LOCK(sc); 5613 if (!(sc->sc_flags & URTWN_RUNNING)) { 5614 error = ENETDOWN; 5615 goto end; 5616 } 5617 5618 bf = urtwn_getbuf(sc); 5619 if (bf == NULL) { 5620 error = ENOBUFS; 5621 goto end; 5622 } 5623 5624 if (params == NULL) { 5625 /* 5626 * Legacy path; interpret frame contents to decide 5627 * precisely how to send the frame. 5628 */ 5629 error = urtwn_tx_data(sc, ni, m, bf); 5630 } else { 5631 /* 5632 * Caller supplied explicit parameters to use in 5633 * sending the frame. 5634 */ 5635 error = urtwn_tx_raw(sc, ni, m, bf, params); 5636 } 5637 if (error != 0) { 5638 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 5639 goto end; 5640 } 5641 5642 sc->sc_txtimer = 5; 5643 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5644 5645end: 5646 if (error != 0) 5647 m_freem(m); 5648 5649 URTWN_UNLOCK(sc); 5650 5651 return (error); 5652} 5653 5654static void 5655urtwn_ms_delay(struct urtwn_softc *sc) 5656{ 5657 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 5658} 5659 5660static device_method_t urtwn_methods[] = { 5661 /* Device interface */ 5662 DEVMETHOD(device_probe, urtwn_match), 5663 DEVMETHOD(device_attach, urtwn_attach), 5664 DEVMETHOD(device_detach, urtwn_detach), 5665 5666 DEVMETHOD_END 5667}; 5668 5669static driver_t urtwn_driver = { 5670 "urtwn", 5671 urtwn_methods, 5672 sizeof(struct urtwn_softc) 5673}; 5674 5675static devclass_t urtwn_devclass; 5676 5677DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 5678MODULE_DEPEND(urtwn, usb, 1, 1, 1); 5679MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 5680#ifndef URTWN_WITHOUT_UCODE 5681MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 5682#endif 5683MODULE_VERSION(urtwn, 1); 5684USB_PNP_HOST_INFO(urtwn_devs); 5685