if_urtwn.c revision 297175
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2015 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#include <sys/cdefs.h> 22__FBSDID("$FreeBSD: head/sys/dev/urtwn/if_urtwn.c 297175 2016-03-22 01:09:15Z adrian $"); 23 24/* 25 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 26 */ 27 28#include "opt_wlan.h" 29#include "opt_urtwn.h" 30 31#include <sys/param.h> 32#include <sys/sockio.h> 33#include <sys/sysctl.h> 34#include <sys/lock.h> 35#include <sys/mutex.h> 36#include <sys/condvar.h> 37#include <sys/mbuf.h> 38#include <sys/kernel.h> 39#include <sys/socket.h> 40#include <sys/systm.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/bus.h> 44#include <sys/endian.h> 45#include <sys/linker.h> 46#include <sys/firmware.h> 47#include <sys/kdb.h> 48 49#include <machine/bus.h> 50#include <machine/resource.h> 51#include <sys/rman.h> 52 53#include <net/bpf.h> 54#include <net/if.h> 55#include <net/if_var.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61 62#include <netinet/in.h> 63#include <netinet/in_systm.h> 64#include <netinet/in_var.h> 65#include <netinet/if_ether.h> 66#include <netinet/ip.h> 67 68#include <net80211/ieee80211_var.h> 69#include <net80211/ieee80211_input.h> 70#include <net80211/ieee80211_regdomain.h> 71#include <net80211/ieee80211_radiotap.h> 72#include <net80211/ieee80211_ratectl.h> 73 74#include <dev/usb/usb.h> 75#include <dev/usb/usbdi.h> 76#include <dev/usb/usb_device.h> 77#include "usbdevs.h" 78 79#include <dev/usb/usb_debug.h> 80 81#include <dev/urtwn/if_urtwnreg.h> 82#include <dev/urtwn/if_urtwnvar.h> 83 84#ifdef USB_DEBUG 85enum { 86 URTWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 87 URTWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 88 URTWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 89 URTWN_DEBUG_RA = 0x00000008, /* f/w rate adaptation setup */ 90 URTWN_DEBUG_USB = 0x00000010, /* usb requests */ 91 URTWN_DEBUG_FIRMWARE = 0x00000020, /* firmware(9) loading debug */ 92 URTWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 93 URTWN_DEBUG_INTR = 0x00000080, /* ISR */ 94 URTWN_DEBUG_TEMP = 0x00000100, /* temperature calibration */ 95 URTWN_DEBUG_ROM = 0x00000200, /* various ROM info */ 96 URTWN_DEBUG_KEY = 0x00000400, /* crypto keys management */ 97 URTWN_DEBUG_TXPWR = 0x00000800, /* dump Tx power values */ 98 URTWN_DEBUG_RSSI = 0x00001000, /* dump RSSI lookups */ 99 URTWN_DEBUG_ANY = 0xffffffff 100}; 101 102#define URTWN_DPRINTF(_sc, _m, ...) do { \ 103 if ((_sc)->sc_debug & (_m)) \ 104 device_printf((_sc)->sc_dev, __VA_ARGS__); \ 105} while(0) 106 107#else 108#define URTWN_DPRINTF(_sc, _m, ...) do { (void) sc; } while (0) 109#endif 110 111#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 112 113static int urtwn_enable_11n = 1; 114TUNABLE_INT("hw.usb.urtwn.enable_11n", &urtwn_enable_11n); 115 116/* various supported device vendors/products */ 117static const STRUCT_USB_HOST_ID urtwn_devs[] = { 118#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 119#define URTWN_RTL8188E_DEV(v,p) \ 120 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 121#define URTWN_RTL8188E 1 122 URTWN_DEV(ABOCOM, RTL8188CU_1), 123 URTWN_DEV(ABOCOM, RTL8188CU_2), 124 URTWN_DEV(ABOCOM, RTL8192CU), 125 URTWN_DEV(ASUS, RTL8192CU), 126 URTWN_DEV(ASUS, USBN10NANO), 127 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 128 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 129 URTWN_DEV(AZUREWAVE, RTL8188CU), 130 URTWN_DEV(BELKIN, F7D2102), 131 URTWN_DEV(BELKIN, RTL8188CU), 132 URTWN_DEV(BELKIN, RTL8192CU), 133 URTWN_DEV(CHICONY, RTL8188CUS_1), 134 URTWN_DEV(CHICONY, RTL8188CUS_2), 135 URTWN_DEV(CHICONY, RTL8188CUS_3), 136 URTWN_DEV(CHICONY, RTL8188CUS_4), 137 URTWN_DEV(CHICONY, RTL8188CUS_5), 138 URTWN_DEV(COREGA, RTL8192CU), 139 URTWN_DEV(DLINK, RTL8188CU), 140 URTWN_DEV(DLINK, RTL8192CU_1), 141 URTWN_DEV(DLINK, RTL8192CU_2), 142 URTWN_DEV(DLINK, RTL8192CU_3), 143 URTWN_DEV(DLINK, DWA131B), 144 URTWN_DEV(EDIMAX, EW7811UN), 145 URTWN_DEV(EDIMAX, RTL8192CU), 146 URTWN_DEV(FEIXUN, RTL8188CU), 147 URTWN_DEV(FEIXUN, RTL8192CU), 148 URTWN_DEV(GUILLEMOT, HWNUP150), 149 URTWN_DEV(HAWKING, RTL8192CU), 150 URTWN_DEV(HP3, RTL8188CU), 151 URTWN_DEV(NETGEAR, WNA1000M), 152 URTWN_DEV(NETGEAR, RTL8192CU), 153 URTWN_DEV(NETGEAR4, RTL8188CU), 154 URTWN_DEV(NOVATECH, RTL8188CU), 155 URTWN_DEV(PLANEX2, RTL8188CU_1), 156 URTWN_DEV(PLANEX2, RTL8188CU_2), 157 URTWN_DEV(PLANEX2, RTL8188CU_3), 158 URTWN_DEV(PLANEX2, RTL8188CU_4), 159 URTWN_DEV(PLANEX2, RTL8188CUS), 160 URTWN_DEV(PLANEX2, RTL8192CU), 161 URTWN_DEV(REALTEK, RTL8188CE_0), 162 URTWN_DEV(REALTEK, RTL8188CE_1), 163 URTWN_DEV(REALTEK, RTL8188CTV), 164 URTWN_DEV(REALTEK, RTL8188CU_0), 165 URTWN_DEV(REALTEK, RTL8188CU_1), 166 URTWN_DEV(REALTEK, RTL8188CU_2), 167 URTWN_DEV(REALTEK, RTL8188CU_3), 168 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 169 URTWN_DEV(REALTEK, RTL8188CUS), 170 URTWN_DEV(REALTEK, RTL8188RU_1), 171 URTWN_DEV(REALTEK, RTL8188RU_2), 172 URTWN_DEV(REALTEK, RTL8188RU_3), 173 URTWN_DEV(REALTEK, RTL8191CU), 174 URTWN_DEV(REALTEK, RTL8192CE), 175 URTWN_DEV(REALTEK, RTL8192CU), 176 URTWN_DEV(SITECOMEU, RTL8188CU_1), 177 URTWN_DEV(SITECOMEU, RTL8188CU_2), 178 URTWN_DEV(SITECOMEU, RTL8192CU), 179 URTWN_DEV(TRENDNET, RTL8188CU), 180 URTWN_DEV(TRENDNET, RTL8192CU), 181 URTWN_DEV(ZYXEL, RTL8192CU), 182 /* URTWN_RTL8188E */ 183 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 184 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 185 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 186 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 187 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 188 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 189#undef URTWN_RTL8188E_DEV 190#undef URTWN_DEV 191}; 192 193static device_probe_t urtwn_match; 194static device_attach_t urtwn_attach; 195static device_detach_t urtwn_detach; 196 197static usb_callback_t urtwn_bulk_tx_callback; 198static usb_callback_t urtwn_bulk_rx_callback; 199 200static void urtwn_sysctlattach(struct urtwn_softc *); 201static void urtwn_drain_mbufq(struct urtwn_softc *); 202static usb_error_t urtwn_do_request(struct urtwn_softc *, 203 struct usb_device_request *, void *); 204static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 205 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 206 const uint8_t [IEEE80211_ADDR_LEN], 207 const uint8_t [IEEE80211_ADDR_LEN]); 208static void urtwn_vap_delete(struct ieee80211vap *); 209static struct mbuf * urtwn_rx_copy_to_mbuf(struct urtwn_softc *, 210 struct r92c_rx_stat *, int); 211static struct mbuf * urtwn_report_intr(struct usb_xfer *, 212 struct urtwn_data *); 213static struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int); 214static void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 215 void *); 216static struct ieee80211_node *urtwn_rx_frame(struct urtwn_softc *, 217 struct mbuf *, int8_t *); 218static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 219 int); 220static int urtwn_alloc_list(struct urtwn_softc *, 221 struct urtwn_data[], int, int); 222static int urtwn_alloc_rx_list(struct urtwn_softc *); 223static int urtwn_alloc_tx_list(struct urtwn_softc *); 224static void urtwn_free_list(struct urtwn_softc *, 225 struct urtwn_data data[], int); 226static void urtwn_free_rx_list(struct urtwn_softc *); 227static void urtwn_free_tx_list(struct urtwn_softc *); 228static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 229static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 230static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 231 uint8_t *, int); 232static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 233static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 234static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 235static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 236 uint8_t *, int); 237static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 238static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 239static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 240static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 241 const void *, int); 242static void urtwn_cmdq_cb(void *, int); 243static int urtwn_cmd_sleepable(struct urtwn_softc *, const void *, 244 size_t, CMD_FUNC_PROTO); 245static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 246 uint8_t, uint32_t); 247static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 248 uint8_t, uint32_t); 249static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 250static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 251 uint32_t); 252static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 253static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 254 uint8_t, uint8_t); 255#ifdef USB_DEBUG 256static void urtwn_dump_rom_contents(struct urtwn_softc *, 257 uint8_t *, uint16_t); 258#endif 259static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 260 uint16_t); 261static int urtwn_efuse_switch_power(struct urtwn_softc *); 262static int urtwn_read_chipid(struct urtwn_softc *); 263static int urtwn_read_rom(struct urtwn_softc *); 264static int urtwn_r88e_read_rom(struct urtwn_softc *); 265static int urtwn_ra_init(struct urtwn_softc *); 266static void urtwn_init_beacon(struct urtwn_softc *, 267 struct urtwn_vap *); 268static int urtwn_setup_beacon(struct urtwn_softc *, 269 struct ieee80211_node *); 270static void urtwn_update_beacon(struct ieee80211vap *, int); 271static int urtwn_tx_beacon(struct urtwn_softc *sc, 272 struct urtwn_vap *); 273static int urtwn_key_alloc(struct ieee80211vap *, 274 struct ieee80211_key *, ieee80211_keyix *, 275 ieee80211_keyix *); 276static void urtwn_key_set_cb(struct urtwn_softc *, 277 union sec_param *); 278static void urtwn_key_del_cb(struct urtwn_softc *, 279 union sec_param *); 280static int urtwn_key_set(struct ieee80211vap *, 281 const struct ieee80211_key *); 282static int urtwn_key_delete(struct ieee80211vap *, 283 const struct ieee80211_key *); 284static void urtwn_tsf_task_adhoc(void *, int); 285static void urtwn_tsf_sync_enable(struct urtwn_softc *, 286 struct ieee80211vap *); 287static void urtwn_get_tsf(struct urtwn_softc *, uint64_t *); 288static void urtwn_set_led(struct urtwn_softc *, int, int); 289static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 290static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 291 struct mbuf *, int, 292 const struct ieee80211_rx_stats *, int, int); 293static int urtwn_newstate(struct ieee80211vap *, 294 enum ieee80211_state, int); 295static void urtwn_calib_to(void *); 296static void urtwn_calib_cb(struct urtwn_softc *, 297 union sec_param *); 298static void urtwn_watchdog(void *); 299static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 300static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 301static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 302static int urtwn_tx_data(struct urtwn_softc *, 303 struct ieee80211_node *, struct mbuf *, 304 struct urtwn_data *); 305static int urtwn_tx_raw(struct urtwn_softc *, 306 struct ieee80211_node *, struct mbuf *, 307 struct urtwn_data *, 308 const struct ieee80211_bpf_params *); 309static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 310 uint8_t, struct urtwn_data *); 311static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 312static void urtwn_start(struct urtwn_softc *); 313static void urtwn_parent(struct ieee80211com *); 314static int urtwn_r92c_power_on(struct urtwn_softc *); 315static int urtwn_r88e_power_on(struct urtwn_softc *); 316static void urtwn_r92c_power_off(struct urtwn_softc *); 317static void urtwn_r88e_power_off(struct urtwn_softc *); 318static int urtwn_llt_init(struct urtwn_softc *); 319#ifndef URTWN_WITHOUT_UCODE 320static void urtwn_fw_reset(struct urtwn_softc *); 321static void urtwn_r88e_fw_reset(struct urtwn_softc *); 322static int urtwn_fw_loadpage(struct urtwn_softc *, int, 323 const uint8_t *, int); 324static int urtwn_load_firmware(struct urtwn_softc *); 325#endif 326static int urtwn_dma_init(struct urtwn_softc *); 327static int urtwn_mac_init(struct urtwn_softc *); 328static void urtwn_bb_init(struct urtwn_softc *); 329static void urtwn_rf_init(struct urtwn_softc *); 330static void urtwn_cam_init(struct urtwn_softc *); 331static int urtwn_cam_write(struct urtwn_softc *, uint32_t, 332 uint32_t); 333static void urtwn_pa_bias_init(struct urtwn_softc *); 334static void urtwn_rxfilter_init(struct urtwn_softc *); 335static void urtwn_edca_init(struct urtwn_softc *); 336static void urtwn_write_txpower(struct urtwn_softc *, int, 337 uint16_t[]); 338static void urtwn_get_txpower(struct urtwn_softc *, int, 339 struct ieee80211_channel *, 340 struct ieee80211_channel *, uint16_t[]); 341static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 342 struct ieee80211_channel *, 343 struct ieee80211_channel *, uint16_t[]); 344static void urtwn_set_txpower(struct urtwn_softc *, 345 struct ieee80211_channel *, 346 struct ieee80211_channel *); 347static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 348static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 349static void urtwn_scan_start(struct ieee80211com *); 350static void urtwn_scan_end(struct ieee80211com *); 351static void urtwn_set_channel(struct ieee80211com *); 352static int urtwn_wme_update(struct ieee80211com *); 353static void urtwn_update_slot(struct ieee80211com *); 354static void urtwn_update_slot_cb(struct urtwn_softc *, 355 union sec_param *); 356static void urtwn_update_aifs(struct urtwn_softc *, uint8_t); 357static void urtwn_set_promisc(struct urtwn_softc *); 358static void urtwn_update_promisc(struct ieee80211com *); 359static void urtwn_update_mcast(struct ieee80211com *); 360static struct ieee80211_node *urtwn_r88e_node_alloc(struct ieee80211vap *, 361 const uint8_t mac[IEEE80211_ADDR_LEN]); 362static void urtwn_r88e_newassoc(struct ieee80211_node *, int); 363static void urtwn_r88e_node_free(struct ieee80211_node *); 364static void urtwn_set_chan(struct urtwn_softc *, 365 struct ieee80211_channel *, 366 struct ieee80211_channel *); 367static void urtwn_iq_calib(struct urtwn_softc *); 368static void urtwn_lc_calib(struct urtwn_softc *); 369static void urtwn_temp_calib(struct urtwn_softc *); 370static int urtwn_init(struct urtwn_softc *); 371static void urtwn_stop(struct urtwn_softc *); 372static void urtwn_abort_xfers(struct urtwn_softc *); 373static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 374 const struct ieee80211_bpf_params *); 375static void urtwn_ms_delay(struct urtwn_softc *); 376 377/* Aliases. */ 378#define urtwn_bb_write urtwn_write_4 379#define urtwn_bb_read urtwn_read_4 380 381static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 382 [URTWN_BULK_RX] = { 383 .type = UE_BULK, 384 .endpoint = UE_ADDR_ANY, 385 .direction = UE_DIR_IN, 386 .bufsize = URTWN_RXBUFSZ, 387 .flags = { 388 .pipe_bof = 1, 389 .short_xfer_ok = 1 390 }, 391 .callback = urtwn_bulk_rx_callback, 392 }, 393 [URTWN_BULK_TX_BE] = { 394 .type = UE_BULK, 395 .endpoint = 0x03, 396 .direction = UE_DIR_OUT, 397 .bufsize = URTWN_TXBUFSZ, 398 .flags = { 399 .ext_buffer = 1, 400 .pipe_bof = 1, 401 .force_short_xfer = 1 402 }, 403 .callback = urtwn_bulk_tx_callback, 404 .timeout = URTWN_TX_TIMEOUT, /* ms */ 405 }, 406 [URTWN_BULK_TX_BK] = { 407 .type = UE_BULK, 408 .endpoint = 0x03, 409 .direction = UE_DIR_OUT, 410 .bufsize = URTWN_TXBUFSZ, 411 .flags = { 412 .ext_buffer = 1, 413 .pipe_bof = 1, 414 .force_short_xfer = 1, 415 }, 416 .callback = urtwn_bulk_tx_callback, 417 .timeout = URTWN_TX_TIMEOUT, /* ms */ 418 }, 419 [URTWN_BULK_TX_VI] = { 420 .type = UE_BULK, 421 .endpoint = 0x02, 422 .direction = UE_DIR_OUT, 423 .bufsize = URTWN_TXBUFSZ, 424 .flags = { 425 .ext_buffer = 1, 426 .pipe_bof = 1, 427 .force_short_xfer = 1 428 }, 429 .callback = urtwn_bulk_tx_callback, 430 .timeout = URTWN_TX_TIMEOUT, /* ms */ 431 }, 432 [URTWN_BULK_TX_VO] = { 433 .type = UE_BULK, 434 .endpoint = 0x02, 435 .direction = UE_DIR_OUT, 436 .bufsize = URTWN_TXBUFSZ, 437 .flags = { 438 .ext_buffer = 1, 439 .pipe_bof = 1, 440 .force_short_xfer = 1 441 }, 442 .callback = urtwn_bulk_tx_callback, 443 .timeout = URTWN_TX_TIMEOUT, /* ms */ 444 }, 445}; 446 447static const struct wme_to_queue { 448 uint16_t reg; 449 uint8_t qid; 450} wme2queue[WME_NUM_AC] = { 451 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 452 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 453 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 454 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 455}; 456 457static int 458urtwn_match(device_t self) 459{ 460 struct usb_attach_arg *uaa = device_get_ivars(self); 461 462 if (uaa->usb_mode != USB_MODE_HOST) 463 return (ENXIO); 464 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 465 return (ENXIO); 466 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 467 return (ENXIO); 468 469 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 470} 471 472static void 473urtwn_update_chw(struct ieee80211com *ic) 474{ 475} 476 477static int 478urtwn_ampdu_enable(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 479{ 480 481 /* We're driving this ourselves (eventually); don't involve net80211 */ 482 return (0); 483} 484 485static int 486urtwn_attach(device_t self) 487{ 488 struct usb_attach_arg *uaa = device_get_ivars(self); 489 struct urtwn_softc *sc = device_get_softc(self); 490 struct ieee80211com *ic = &sc->sc_ic; 491 uint8_t bands[howmany(IEEE80211_MODE_MAX, 8)]; 492 int error; 493 494 device_set_usb_desc(self); 495 sc->sc_udev = uaa->device; 496 sc->sc_dev = self; 497 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 498 sc->chip |= URTWN_CHIP_88E; 499 500#ifdef USB_DEBUG 501 int debug; 502 if (resource_int_value(device_get_name(sc->sc_dev), 503 device_get_unit(sc->sc_dev), "debug", &debug) == 0) 504 sc->sc_debug = debug; 505#endif 506 507 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 508 MTX_NETWORK_LOCK, MTX_DEF); 509 URTWN_CMDQ_LOCK_INIT(sc); 510 URTWN_NT_LOCK_INIT(sc); 511 callout_init(&sc->sc_calib_to, 0); 512 callout_init(&sc->sc_watchdog_ch, 0); 513 mbufq_init(&sc->sc_snd, ifqmaxlen); 514 515 sc->sc_iface_index = URTWN_IFACE_INDEX; 516 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 517 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 518 if (error) { 519 device_printf(self, "could not allocate USB transfers, " 520 "err=%s\n", usbd_errstr(error)); 521 goto detach; 522 } 523 524 URTWN_LOCK(sc); 525 526 error = urtwn_read_chipid(sc); 527 if (error) { 528 device_printf(sc->sc_dev, "unsupported test chip\n"); 529 URTWN_UNLOCK(sc); 530 goto detach; 531 } 532 533 /* Determine number of Tx/Rx chains. */ 534 if (sc->chip & URTWN_CHIP_92C) { 535 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 536 sc->nrxchains = 2; 537 } else { 538 sc->ntxchains = 1; 539 sc->nrxchains = 1; 540 } 541 542 if (sc->chip & URTWN_CHIP_88E) 543 error = urtwn_r88e_read_rom(sc); 544 else 545 error = urtwn_read_rom(sc); 546 if (error != 0) { 547 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 548 __func__, error); 549 URTWN_UNLOCK(sc); 550 goto detach; 551 } 552 553 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 554 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 555 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 556 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 557 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 558 "8188CUS", sc->ntxchains, sc->nrxchains); 559 560 URTWN_UNLOCK(sc); 561 562 ic->ic_softc = sc; 563 ic->ic_name = device_get_nameunit(self); 564 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 565 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 566 567 /* set device capabilities */ 568 ic->ic_caps = 569 IEEE80211_C_STA /* station mode */ 570 | IEEE80211_C_MONITOR /* monitor mode */ 571 | IEEE80211_C_IBSS /* adhoc mode */ 572 | IEEE80211_C_HOSTAP /* hostap mode */ 573 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 574 | IEEE80211_C_SHSLOT /* short slot time supported */ 575#if 0 576 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 577#endif 578 | IEEE80211_C_WPA /* 802.11i */ 579 | IEEE80211_C_WME /* 802.11e */ 580 ; 581 582 ic->ic_cryptocaps = 583 IEEE80211_CRYPTO_WEP | 584 IEEE80211_CRYPTO_TKIP | 585 IEEE80211_CRYPTO_AES_CCM; 586 587 /* Assume they're all 11n capable for now */ 588 if (urtwn_enable_11n) { 589 device_printf(self, "enabling 11n\n"); 590 ic->ic_htcaps = IEEE80211_HTC_HT | 591 IEEE80211_HTC_AMPDU | 592 IEEE80211_HTC_AMSDU | 593 IEEE80211_HTCAP_MAXAMSDU_3839 | 594 IEEE80211_HTCAP_SMPS_OFF; 595 /* no HT40 just yet */ 596 // ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40; 597 598 /* XXX TODO: verify chains versus streams for urtwn */ 599 ic->ic_txstream = sc->ntxchains; 600 ic->ic_rxstream = sc->nrxchains; 601 } 602 603 memset(bands, 0, sizeof(bands)); 604 setbit(bands, IEEE80211_MODE_11B); 605 setbit(bands, IEEE80211_MODE_11G); 606 if (urtwn_enable_11n) 607 setbit(bands, IEEE80211_MODE_11NG); 608 ieee80211_init_channels(ic, NULL, bands); 609 610 ieee80211_ifattach(ic); 611 ic->ic_raw_xmit = urtwn_raw_xmit; 612 ic->ic_scan_start = urtwn_scan_start; 613 ic->ic_scan_end = urtwn_scan_end; 614 ic->ic_set_channel = urtwn_set_channel; 615 ic->ic_transmit = urtwn_transmit; 616 ic->ic_parent = urtwn_parent; 617 ic->ic_vap_create = urtwn_vap_create; 618 ic->ic_vap_delete = urtwn_vap_delete; 619 ic->ic_wme.wme_update = urtwn_wme_update; 620 ic->ic_updateslot = urtwn_update_slot; 621 ic->ic_update_promisc = urtwn_update_promisc; 622 ic->ic_update_mcast = urtwn_update_mcast; 623 if (sc->chip & URTWN_CHIP_88E) { 624 ic->ic_node_alloc = urtwn_r88e_node_alloc; 625 ic->ic_newassoc = urtwn_r88e_newassoc; 626 sc->sc_node_free = ic->ic_node_free; 627 ic->ic_node_free = urtwn_r88e_node_free; 628 } 629 ic->ic_update_chw = urtwn_update_chw; 630 ic->ic_ampdu_enable = urtwn_ampdu_enable; 631 632 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 633 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 634 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 635 URTWN_RX_RADIOTAP_PRESENT); 636 637 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc); 638 639 urtwn_sysctlattach(sc); 640 641 if (bootverbose) 642 ieee80211_announce(ic); 643 644 return (0); 645 646detach: 647 urtwn_detach(self); 648 return (ENXIO); /* failure */ 649} 650 651static void 652urtwn_sysctlattach(struct urtwn_softc *sc) 653{ 654#ifdef USB_DEBUG 655 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 656 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 657 658 SYSCTL_ADD_U32(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 659 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 660 "control debugging printfs"); 661#endif 662} 663 664static int 665urtwn_detach(device_t self) 666{ 667 struct urtwn_softc *sc = device_get_softc(self); 668 struct ieee80211com *ic = &sc->sc_ic; 669 unsigned int x; 670 671 /* Prevent further ioctls. */ 672 URTWN_LOCK(sc); 673 sc->sc_flags |= URTWN_DETACHED; 674 URTWN_UNLOCK(sc); 675 676 urtwn_stop(sc); 677 678 callout_drain(&sc->sc_watchdog_ch); 679 callout_drain(&sc->sc_calib_to); 680 681 /* stop all USB transfers */ 682 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 683 684 /* Prevent further allocations from RX/TX data lists. */ 685 URTWN_LOCK(sc); 686 STAILQ_INIT(&sc->sc_tx_active); 687 STAILQ_INIT(&sc->sc_tx_inactive); 688 STAILQ_INIT(&sc->sc_tx_pending); 689 690 STAILQ_INIT(&sc->sc_rx_active); 691 STAILQ_INIT(&sc->sc_rx_inactive); 692 URTWN_UNLOCK(sc); 693 694 /* drain USB transfers */ 695 for (x = 0; x != URTWN_N_TRANSFER; x++) 696 usbd_transfer_drain(sc->sc_xfer[x]); 697 698 /* Free data buffers. */ 699 URTWN_LOCK(sc); 700 urtwn_free_tx_list(sc); 701 urtwn_free_rx_list(sc); 702 URTWN_UNLOCK(sc); 703 704 if (ic->ic_softc == sc) { 705 ieee80211_draintask(ic, &sc->cmdq_task); 706 ieee80211_ifdetach(ic); 707 } 708 709 URTWN_NT_LOCK_DESTROY(sc); 710 URTWN_CMDQ_LOCK_DESTROY(sc); 711 mtx_destroy(&sc->sc_mtx); 712 713 return (0); 714} 715 716static void 717urtwn_drain_mbufq(struct urtwn_softc *sc) 718{ 719 struct mbuf *m; 720 struct ieee80211_node *ni; 721 URTWN_ASSERT_LOCKED(sc); 722 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 723 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 724 m->m_pkthdr.rcvif = NULL; 725 ieee80211_free_node(ni); 726 m_freem(m); 727 } 728} 729 730static usb_error_t 731urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 732 void *data) 733{ 734 usb_error_t err; 735 int ntries = 10; 736 737 URTWN_ASSERT_LOCKED(sc); 738 739 while (ntries--) { 740 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 741 req, data, 0, NULL, 250 /* ms */); 742 if (err == 0) 743 break; 744 745 URTWN_DPRINTF(sc, URTWN_DEBUG_USB, 746 "%s: control request failed, %s (retries left: %d)\n", 747 __func__, usbd_errstr(err), ntries); 748 usb_pause_mtx(&sc->sc_mtx, hz / 100); 749 } 750 return (err); 751} 752 753static struct ieee80211vap * 754urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 755 enum ieee80211_opmode opmode, int flags, 756 const uint8_t bssid[IEEE80211_ADDR_LEN], 757 const uint8_t mac[IEEE80211_ADDR_LEN]) 758{ 759 struct urtwn_softc *sc = ic->ic_softc; 760 struct urtwn_vap *uvp; 761 struct ieee80211vap *vap; 762 763 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 764 return (NULL); 765 766 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 767 vap = &uvp->vap; 768 /* enable s/w bmiss handling for sta mode */ 769 770 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 771 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 772 /* out of memory */ 773 free(uvp, M_80211_VAP); 774 return (NULL); 775 } 776 777 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 778 urtwn_init_beacon(sc, uvp); 779 780 /* override state transition machine */ 781 uvp->newstate = vap->iv_newstate; 782 vap->iv_newstate = urtwn_newstate; 783 vap->iv_update_beacon = urtwn_update_beacon; 784 vap->iv_key_alloc = urtwn_key_alloc; 785 vap->iv_key_set = urtwn_key_set; 786 vap->iv_key_delete = urtwn_key_delete; 787 if (opmode == IEEE80211_M_IBSS) { 788 uvp->recv_mgmt = vap->iv_recv_mgmt; 789 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 790 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 791 } 792 793 if (URTWN_CHIP_HAS_RATECTL(sc)) 794 ieee80211_ratectl_init(vap); 795 /* complete setup */ 796 ieee80211_vap_attach(vap, ieee80211_media_change, 797 ieee80211_media_status, mac); 798 ic->ic_opmode = opmode; 799 return (vap); 800} 801 802static void 803urtwn_vap_delete(struct ieee80211vap *vap) 804{ 805 struct ieee80211com *ic = vap->iv_ic; 806 struct urtwn_softc *sc = ic->ic_softc; 807 struct urtwn_vap *uvp = URTWN_VAP(vap); 808 809 if (uvp->bcn_mbuf != NULL) 810 m_freem(uvp->bcn_mbuf); 811 if (vap->iv_opmode == IEEE80211_M_IBSS) 812 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 813 if (URTWN_CHIP_HAS_RATECTL(sc)) 814 ieee80211_ratectl_deinit(vap); 815 ieee80211_vap_detach(vap); 816 free(uvp, M_80211_VAP); 817} 818 819static struct mbuf * 820urtwn_rx_copy_to_mbuf(struct urtwn_softc *sc, struct r92c_rx_stat *stat, 821 int totlen) 822{ 823 struct ieee80211com *ic = &sc->sc_ic; 824 struct mbuf *m; 825 uint32_t rxdw0; 826 int pktlen; 827 828 /* 829 * don't pass packets to the ieee80211 framework if the driver isn't 830 * RUNNING. 831 */ 832 if (!(sc->sc_flags & URTWN_RUNNING)) 833 return (NULL); 834 835 rxdw0 = le32toh(stat->rxdw0); 836 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 837 /* 838 * This should not happen since we setup our Rx filter 839 * to not receive these frames. 840 */ 841 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 842 "%s: RX flags error (%s)\n", __func__, 843 rxdw0 & R92C_RXDW0_CRCERR ? "CRC" : "ICV"); 844 goto fail; 845 } 846 847 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 848 if (pktlen < sizeof(struct ieee80211_frame_ack)) { 849 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 850 "%s: frame is too short: %d\n", __func__, pktlen); 851 goto fail; 852 } 853 854 if (__predict_false(totlen > MCLBYTES)) { 855 /* convert to m_getjcl if this happens */ 856 device_printf(sc->sc_dev, "%s: frame too long: %d (%d)\n", 857 __func__, pktlen, totlen); 858 goto fail; 859 } 860 861 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 862 if (__predict_false(m == NULL)) { 863 device_printf(sc->sc_dev, "%s: could not allocate RX mbuf\n", 864 __func__); 865 goto fail; 866 } 867 868 /* Finalize mbuf. */ 869 memcpy(mtod(m, uint8_t *), (uint8_t *)stat, totlen); 870 m->m_pkthdr.len = m->m_len = totlen; 871 872 return (m); 873fail: 874 counter_u64_add(ic->ic_ierrors, 1); 875 return (NULL); 876} 877 878static struct mbuf * 879urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data) 880{ 881 struct urtwn_softc *sc = data->sc; 882 struct ieee80211com *ic = &sc->sc_ic; 883 struct r92c_rx_stat *stat; 884 uint8_t *buf; 885 int len; 886 887 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 888 889 if (len < sizeof(*stat)) { 890 counter_u64_add(ic->ic_ierrors, 1); 891 return (NULL); 892 } 893 894 buf = data->buf; 895 stat = (struct r92c_rx_stat *)buf; 896 897 if (sc->chip & URTWN_CHIP_88E) { 898 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 899 900 switch (report_sel) { 901 case R88E_RXDW3_RPT_RX: 902 return (urtwn_rxeof(sc, buf, len)); 903 case R88E_RXDW3_RPT_TX1: 904 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 905 break; 906 default: 907 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, 908 "%s: case %d was not handled\n", __func__, 909 report_sel); 910 break; 911 } 912 } else 913 return (urtwn_rxeof(sc, buf, len)); 914 915 return (NULL); 916} 917 918static struct mbuf * 919urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len) 920{ 921 struct r92c_rx_stat *stat; 922 struct mbuf *m, *m0 = NULL, *prevm = NULL; 923 uint32_t rxdw0; 924 int totlen, pktlen, infosz, npkts; 925 926 /* Get the number of encapsulated frames. */ 927 stat = (struct r92c_rx_stat *)buf; 928 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 929 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 930 "%s: Rx %d frames in one chunk\n", __func__, npkts); 931 932 /* Process all of them. */ 933 while (npkts-- > 0) { 934 if (len < sizeof(*stat)) 935 break; 936 stat = (struct r92c_rx_stat *)buf; 937 rxdw0 = le32toh(stat->rxdw0); 938 939 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 940 if (pktlen == 0) 941 break; 942 943 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 944 945 /* Make sure everything fits in xfer. */ 946 totlen = sizeof(*stat) + infosz + pktlen; 947 if (totlen > len) 948 break; 949 950 m = urtwn_rx_copy_to_mbuf(sc, stat, totlen); 951 if (m0 == NULL) 952 m0 = m; 953 if (prevm == NULL) 954 prevm = m; 955 else { 956 prevm->m_next = m; 957 prevm = m; 958 } 959 960 /* Next chunk is 128-byte aligned. */ 961 totlen = (totlen + 127) & ~127; 962 buf += totlen; 963 len -= totlen; 964 } 965 966 return (m0); 967} 968 969static void 970urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 971{ 972 struct r88e_tx_rpt_ccx *rpt = arg; 973 struct ieee80211vap *vap; 974 struct ieee80211_node *ni; 975 uint8_t macid; 976 int ntries; 977 978 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 979 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 980 981 URTWN_NT_LOCK(sc); 982 ni = sc->node_list[macid]; 983 if (ni != NULL) { 984 vap = ni->ni_vap; 985 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: frame for macid %d was" 986 "%s sent (%d retries)\n", __func__, macid, 987 (rpt->rptb1 & R88E_RPTB1_PKT_OK) ? "" : " not", 988 ntries); 989 990 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 991 ieee80211_ratectl_tx_complete(vap, ni, 992 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 993 } else { 994 ieee80211_ratectl_tx_complete(vap, ni, 995 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 996 } 997 } else { 998 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: macid %d, ni is NULL\n", 999 __func__, macid); 1000 } 1001 URTWN_NT_UNLOCK(sc); 1002} 1003 1004static struct ieee80211_node * 1005urtwn_rx_frame(struct urtwn_softc *sc, struct mbuf *m, int8_t *rssi_p) 1006{ 1007 struct ieee80211com *ic = &sc->sc_ic; 1008 struct ieee80211_frame_min *wh; 1009 struct r92c_rx_stat *stat; 1010 uint32_t rxdw0, rxdw3; 1011 uint8_t rate, cipher; 1012 int8_t rssi = URTWN_NOISE_FLOOR + 1; 1013 int infosz; 1014 1015 stat = mtod(m, struct r92c_rx_stat *); 1016 rxdw0 = le32toh(stat->rxdw0); 1017 rxdw3 = le32toh(stat->rxdw3); 1018 1019 rate = MS(rxdw3, R92C_RXDW3_RATE); 1020 cipher = MS(rxdw0, R92C_RXDW0_CIPHER); 1021 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1022 1023 /* Get RSSI from PHY status descriptor if present. */ 1024 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1025 if (sc->chip & URTWN_CHIP_88E) 1026 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 1027 else 1028 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 1029 /* Update our average RSSI. */ 1030 urtwn_update_avgrssi(sc, rate, rssi); 1031 } 1032 1033 if (ieee80211_radiotap_active(ic)) { 1034 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1035 1036 tap->wr_flags = 0; 1037 1038 urtwn_get_tsf(sc, &tap->wr_tsft); 1039 if (__predict_false(le32toh((uint32_t)tap->wr_tsft) < 1040 le32toh(stat->rxdw5))) { 1041 tap->wr_tsft = le32toh(tap->wr_tsft >> 32) - 1; 1042 tap->wr_tsft = (uint64_t)htole32(tap->wr_tsft) << 32; 1043 } else 1044 tap->wr_tsft &= 0xffffffff00000000; 1045 tap->wr_tsft += stat->rxdw5; 1046 1047 /* XXX 20/40? */ 1048 /* XXX shortgi? */ 1049 1050 /* Map HW rate index to 802.11 rate. */ 1051 if (!(rxdw3 & R92C_RXDW3_HT)) { 1052 tap->wr_rate = ridx2rate[rate]; 1053 } else if (rate >= 12) { /* MCS0~15. */ 1054 /* Bit 7 set means HT MCS instead of rate. */ 1055 tap->wr_rate = 0x80 | (rate - 12); 1056 } 1057 tap->wr_dbm_antsignal = rssi; 1058 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 1059 } 1060 1061 *rssi_p = rssi; 1062 1063 /* Drop descriptor. */ 1064 m_adj(m, sizeof(*stat) + infosz); 1065 wh = mtod(m, struct ieee80211_frame_min *); 1066 1067 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1068 cipher != R92C_CAM_ALGO_NONE) { 1069 m->m_flags |= M_WEP; 1070 } 1071 1072 if (m->m_len >= sizeof(*wh)) 1073 return (ieee80211_find_rxnode(ic, wh)); 1074 1075 return (NULL); 1076} 1077 1078static void 1079urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 1080{ 1081 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1082 struct ieee80211com *ic = &sc->sc_ic; 1083 struct ieee80211_node *ni; 1084 struct mbuf *m = NULL, *next; 1085 struct urtwn_data *data; 1086 int8_t nf, rssi; 1087 1088 URTWN_ASSERT_LOCKED(sc); 1089 1090 switch (USB_GET_STATE(xfer)) { 1091 case USB_ST_TRANSFERRED: 1092 data = STAILQ_FIRST(&sc->sc_rx_active); 1093 if (data == NULL) 1094 goto tr_setup; 1095 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1096 m = urtwn_report_intr(xfer, data); 1097 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1098 /* FALLTHROUGH */ 1099 case USB_ST_SETUP: 1100tr_setup: 1101 data = STAILQ_FIRST(&sc->sc_rx_inactive); 1102 if (data == NULL) { 1103 KASSERT(m == NULL, ("mbuf isn't NULL")); 1104 return; 1105 } 1106 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 1107 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 1108 usbd_xfer_set_frame_data(xfer, 0, data->buf, 1109 usbd_xfer_max_len(xfer)); 1110 usbd_transfer_submit(xfer); 1111 1112 /* 1113 * To avoid LOR we should unlock our private mutex here to call 1114 * ieee80211_input() because here is at the end of a USB 1115 * callback and safe to unlock. 1116 */ 1117 while (m != NULL) { 1118 next = m->m_next; 1119 m->m_next = NULL; 1120 1121 ni = urtwn_rx_frame(sc, m, &rssi); 1122 URTWN_UNLOCK(sc); 1123 1124 nf = URTWN_NOISE_FLOOR; 1125 if (ni != NULL) { 1126 if (ni->ni_flags & IEEE80211_NODE_HT) 1127 m->m_flags |= M_AMPDU; 1128 (void)ieee80211_input(ni, m, rssi - nf, nf); 1129 ieee80211_free_node(ni); 1130 } else { 1131 (void)ieee80211_input_all(ic, m, rssi - nf, 1132 nf); 1133 } 1134 1135 URTWN_LOCK(sc); 1136 m = next; 1137 } 1138 break; 1139 default: 1140 /* needs it to the inactive queue due to a error. */ 1141 data = STAILQ_FIRST(&sc->sc_rx_active); 1142 if (data != NULL) { 1143 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1144 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1145 } 1146 if (error != USB_ERR_CANCELLED) { 1147 usbd_xfer_set_stall(xfer); 1148 counter_u64_add(ic->ic_ierrors, 1); 1149 goto tr_setup; 1150 } 1151 break; 1152 } 1153} 1154 1155static void 1156urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 1157{ 1158 1159 URTWN_ASSERT_LOCKED(sc); 1160 1161 if (data->ni != NULL) /* not a beacon frame */ 1162 ieee80211_tx_complete(data->ni, data->m, status); 1163 1164 data->ni = NULL; 1165 data->m = NULL; 1166 1167 sc->sc_txtimer = 0; 1168 1169 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 1170} 1171 1172static int 1173urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1174 int ndata, int maxsz) 1175{ 1176 int i, error; 1177 1178 for (i = 0; i < ndata; i++) { 1179 struct urtwn_data *dp = &data[i]; 1180 dp->sc = sc; 1181 dp->m = NULL; 1182 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1183 if (dp->buf == NULL) { 1184 device_printf(sc->sc_dev, 1185 "could not allocate buffer\n"); 1186 error = ENOMEM; 1187 goto fail; 1188 } 1189 dp->ni = NULL; 1190 } 1191 1192 return (0); 1193fail: 1194 urtwn_free_list(sc, data, ndata); 1195 return (error); 1196} 1197 1198static int 1199urtwn_alloc_rx_list(struct urtwn_softc *sc) 1200{ 1201 int error, i; 1202 1203 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1204 URTWN_RXBUFSZ); 1205 if (error != 0) 1206 return (error); 1207 1208 STAILQ_INIT(&sc->sc_rx_active); 1209 STAILQ_INIT(&sc->sc_rx_inactive); 1210 1211 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1212 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1213 1214 return (0); 1215} 1216 1217static int 1218urtwn_alloc_tx_list(struct urtwn_softc *sc) 1219{ 1220 int error, i; 1221 1222 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1223 URTWN_TXBUFSZ); 1224 if (error != 0) 1225 return (error); 1226 1227 STAILQ_INIT(&sc->sc_tx_active); 1228 STAILQ_INIT(&sc->sc_tx_inactive); 1229 STAILQ_INIT(&sc->sc_tx_pending); 1230 1231 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1232 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1233 1234 return (0); 1235} 1236 1237static void 1238urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1239{ 1240 int i; 1241 1242 for (i = 0; i < ndata; i++) { 1243 struct urtwn_data *dp = &data[i]; 1244 1245 if (dp->buf != NULL) { 1246 free(dp->buf, M_USBDEV); 1247 dp->buf = NULL; 1248 } 1249 if (dp->ni != NULL) { 1250 ieee80211_free_node(dp->ni); 1251 dp->ni = NULL; 1252 } 1253 } 1254} 1255 1256static void 1257urtwn_free_rx_list(struct urtwn_softc *sc) 1258{ 1259 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1260} 1261 1262static void 1263urtwn_free_tx_list(struct urtwn_softc *sc) 1264{ 1265 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1266} 1267 1268static void 1269urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1270{ 1271 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1272 struct urtwn_data *data; 1273 1274 URTWN_ASSERT_LOCKED(sc); 1275 1276 switch (USB_GET_STATE(xfer)){ 1277 case USB_ST_TRANSFERRED: 1278 data = STAILQ_FIRST(&sc->sc_tx_active); 1279 if (data == NULL) 1280 goto tr_setup; 1281 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1282 urtwn_txeof(sc, data, 0); 1283 /* FALLTHROUGH */ 1284 case USB_ST_SETUP: 1285tr_setup: 1286 data = STAILQ_FIRST(&sc->sc_tx_pending); 1287 if (data == NULL) { 1288 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1289 "%s: empty pending queue\n", __func__); 1290 goto finish; 1291 } 1292 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1293 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1294 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1295 usbd_transfer_submit(xfer); 1296 break; 1297 default: 1298 data = STAILQ_FIRST(&sc->sc_tx_active); 1299 if (data == NULL) 1300 goto tr_setup; 1301 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1302 urtwn_txeof(sc, data, 1); 1303 if (error != USB_ERR_CANCELLED) { 1304 usbd_xfer_set_stall(xfer); 1305 goto tr_setup; 1306 } 1307 break; 1308 } 1309finish: 1310 /* Kick-start more transmit */ 1311 urtwn_start(sc); 1312} 1313 1314static struct urtwn_data * 1315_urtwn_getbuf(struct urtwn_softc *sc) 1316{ 1317 struct urtwn_data *bf; 1318 1319 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1320 if (bf != NULL) 1321 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1322 else { 1323 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1324 "%s: out of xmit buffers\n", __func__); 1325 } 1326 return (bf); 1327} 1328 1329static struct urtwn_data * 1330urtwn_getbuf(struct urtwn_softc *sc) 1331{ 1332 struct urtwn_data *bf; 1333 1334 URTWN_ASSERT_LOCKED(sc); 1335 1336 bf = _urtwn_getbuf(sc); 1337 if (bf == NULL) { 1338 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: stop queue\n", 1339 __func__); 1340 } 1341 return (bf); 1342} 1343 1344static usb_error_t 1345urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1346 int len) 1347{ 1348 usb_device_request_t req; 1349 1350 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1351 req.bRequest = R92C_REQ_REGS; 1352 USETW(req.wValue, addr); 1353 USETW(req.wIndex, 0); 1354 USETW(req.wLength, len); 1355 return (urtwn_do_request(sc, &req, buf)); 1356} 1357 1358static usb_error_t 1359urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1360{ 1361 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1362} 1363 1364static usb_error_t 1365urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1366{ 1367 val = htole16(val); 1368 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1369} 1370 1371static usb_error_t 1372urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1373{ 1374 val = htole32(val); 1375 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1376} 1377 1378static usb_error_t 1379urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1380 int len) 1381{ 1382 usb_device_request_t req; 1383 1384 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1385 req.bRequest = R92C_REQ_REGS; 1386 USETW(req.wValue, addr); 1387 USETW(req.wIndex, 0); 1388 USETW(req.wLength, len); 1389 return (urtwn_do_request(sc, &req, buf)); 1390} 1391 1392static uint8_t 1393urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1394{ 1395 uint8_t val; 1396 1397 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1398 return (0xff); 1399 return (val); 1400} 1401 1402static uint16_t 1403urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1404{ 1405 uint16_t val; 1406 1407 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1408 return (0xffff); 1409 return (le16toh(val)); 1410} 1411 1412static uint32_t 1413urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1414{ 1415 uint32_t val; 1416 1417 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1418 return (0xffffffff); 1419 return (le32toh(val)); 1420} 1421 1422static int 1423urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1424{ 1425 struct r92c_fw_cmd cmd; 1426 usb_error_t error; 1427 int ntries; 1428 1429 if (!(sc->sc_flags & URTWN_FW_LOADED)) { 1430 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, "%s: firmware " 1431 "was not loaded; command (id %d) will be discarded\n", 1432 __func__, id); 1433 return (0); 1434 } 1435 1436 /* Wait for current FW box to be empty. */ 1437 for (ntries = 0; ntries < 100; ntries++) { 1438 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1439 break; 1440 urtwn_ms_delay(sc); 1441 } 1442 if (ntries == 100) { 1443 device_printf(sc->sc_dev, 1444 "could not send firmware command\n"); 1445 return (ETIMEDOUT); 1446 } 1447 memset(&cmd, 0, sizeof(cmd)); 1448 cmd.id = id; 1449 if (len > 3) 1450 cmd.id |= R92C_CMD_FLAG_EXT; 1451 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1452 memcpy(cmd.msg, buf, len); 1453 1454 /* Write the first word last since that will trigger the FW. */ 1455 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1456 (uint8_t *)&cmd + 4, 2); 1457 if (error != USB_ERR_NORMAL_COMPLETION) 1458 return (EIO); 1459 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1460 (uint8_t *)&cmd + 0, 4); 1461 if (error != USB_ERR_NORMAL_COMPLETION) 1462 return (EIO); 1463 1464 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1465 return (0); 1466} 1467 1468static void 1469urtwn_cmdq_cb(void *arg, int pending) 1470{ 1471 struct urtwn_softc *sc = arg; 1472 struct urtwn_cmdq *item; 1473 1474 /* 1475 * Device must be powered on (via urtwn_power_on()) 1476 * before any command may be sent. 1477 */ 1478 URTWN_LOCK(sc); 1479 if (!(sc->sc_flags & URTWN_RUNNING)) { 1480 URTWN_UNLOCK(sc); 1481 return; 1482 } 1483 1484 URTWN_CMDQ_LOCK(sc); 1485 while (sc->cmdq[sc->cmdq_first].func != NULL) { 1486 item = &sc->cmdq[sc->cmdq_first]; 1487 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE; 1488 URTWN_CMDQ_UNLOCK(sc); 1489 1490 item->func(sc, &item->data); 1491 1492 URTWN_CMDQ_LOCK(sc); 1493 memset(item, 0, sizeof (*item)); 1494 } 1495 URTWN_CMDQ_UNLOCK(sc); 1496 URTWN_UNLOCK(sc); 1497} 1498 1499static int 1500urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len, 1501 CMD_FUNC_PROTO) 1502{ 1503 struct ieee80211com *ic = &sc->sc_ic; 1504 1505 KASSERT(len <= sizeof(union sec_param), ("buffer overflow")); 1506 1507 URTWN_CMDQ_LOCK(sc); 1508 if (sc->cmdq[sc->cmdq_last].func != NULL) { 1509 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__); 1510 URTWN_CMDQ_UNLOCK(sc); 1511 1512 return (EAGAIN); 1513 } 1514 1515 if (ptr != NULL) 1516 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len); 1517 sc->cmdq[sc->cmdq_last].func = func; 1518 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE; 1519 URTWN_CMDQ_UNLOCK(sc); 1520 1521 ieee80211_runtask(ic, &sc->cmdq_task); 1522 1523 return (0); 1524} 1525 1526static __inline void 1527urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1528{ 1529 1530 sc->sc_rf_write(sc, chain, addr, val); 1531} 1532 1533static void 1534urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1535 uint32_t val) 1536{ 1537 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1538 SM(R92C_LSSI_PARAM_ADDR, addr) | 1539 SM(R92C_LSSI_PARAM_DATA, val)); 1540} 1541 1542static void 1543urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1544uint32_t val) 1545{ 1546 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1547 SM(R88E_LSSI_PARAM_ADDR, addr) | 1548 SM(R92C_LSSI_PARAM_DATA, val)); 1549} 1550 1551static uint32_t 1552urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1553{ 1554 uint32_t reg[R92C_MAX_CHAINS], val; 1555 1556 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1557 if (chain != 0) 1558 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1559 1560 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1561 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1562 urtwn_ms_delay(sc); 1563 1564 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1565 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1566 R92C_HSSI_PARAM2_READ_EDGE); 1567 urtwn_ms_delay(sc); 1568 1569 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1570 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1571 urtwn_ms_delay(sc); 1572 1573 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1574 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1575 else 1576 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1577 return (MS(val, R92C_LSSI_READBACK_DATA)); 1578} 1579 1580static int 1581urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1582{ 1583 usb_error_t error; 1584 int ntries; 1585 1586 error = urtwn_write_4(sc, R92C_LLT_INIT, 1587 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1588 SM(R92C_LLT_INIT_ADDR, addr) | 1589 SM(R92C_LLT_INIT_DATA, data)); 1590 if (error != USB_ERR_NORMAL_COMPLETION) 1591 return (EIO); 1592 /* Wait for write operation to complete. */ 1593 for (ntries = 0; ntries < 20; ntries++) { 1594 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1595 R92C_LLT_INIT_OP_NO_ACTIVE) 1596 return (0); 1597 urtwn_ms_delay(sc); 1598 } 1599 return (ETIMEDOUT); 1600} 1601 1602static int 1603urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1604{ 1605 uint32_t reg; 1606 usb_error_t error; 1607 int ntries; 1608 1609 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1610 return (EFAULT); 1611 1612 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1613 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1614 reg &= ~R92C_EFUSE_CTRL_VALID; 1615 1616 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1617 if (error != USB_ERR_NORMAL_COMPLETION) 1618 return (EIO); 1619 /* Wait for read operation to complete. */ 1620 for (ntries = 0; ntries < 100; ntries++) { 1621 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1622 if (reg & R92C_EFUSE_CTRL_VALID) 1623 break; 1624 urtwn_ms_delay(sc); 1625 } 1626 if (ntries == 100) { 1627 device_printf(sc->sc_dev, 1628 "could not read efuse byte at address 0x%x\n", 1629 sc->last_rom_addr); 1630 return (ETIMEDOUT); 1631 } 1632 1633 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1634 sc->last_rom_addr++; 1635 1636 return (0); 1637} 1638 1639static int 1640urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1641 uint8_t msk) 1642{ 1643 uint8_t reg; 1644 int i, error; 1645 1646 for (i = 0; i < 4; i++) { 1647 if (msk & (1 << i)) 1648 continue; 1649 error = urtwn_efuse_read_next(sc, ®); 1650 if (error != 0) 1651 return (error); 1652 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1653 off * 8 + i * 2, reg); 1654 rom[off * 8 + i * 2 + 0] = reg; 1655 1656 error = urtwn_efuse_read_next(sc, ®); 1657 if (error != 0) 1658 return (error); 1659 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1660 off * 8 + i * 2 + 1, reg); 1661 rom[off * 8 + i * 2 + 1] = reg; 1662 } 1663 1664 return (0); 1665} 1666 1667#ifdef USB_DEBUG 1668static void 1669urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1670{ 1671 int i; 1672 1673 /* Dump ROM contents. */ 1674 device_printf(sc->sc_dev, "%s:", __func__); 1675 for (i = 0; i < size; i++) { 1676 if (i % 32 == 0) 1677 printf("\n%03X: ", i); 1678 else if (i % 4 == 0) 1679 printf(" "); 1680 1681 printf("%02X", rom[i]); 1682 } 1683 printf("\n"); 1684} 1685#endif 1686 1687static int 1688urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1689{ 1690#define URTWN_CHK(res) do { \ 1691 if ((error = res) != 0) \ 1692 goto end; \ 1693} while(0) 1694 uint8_t msk, off, reg; 1695 int error; 1696 1697 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1698 1699 /* Read full ROM image. */ 1700 sc->last_rom_addr = 0; 1701 memset(rom, 0xff, size); 1702 1703 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1704 while (reg != 0xff) { 1705 /* check for extended header */ 1706 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1707 off = reg >> 5; 1708 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1709 1710 if ((reg & 0x0f) != 0x0f) 1711 off = ((reg & 0xf0) >> 1) | off; 1712 else 1713 continue; 1714 } else 1715 off = reg >> 4; 1716 msk = reg & 0xf; 1717 1718 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1719 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1720 } 1721 1722end: 1723 1724#ifdef USB_DEBUG 1725 if (sc->sc_debug & URTWN_DEBUG_ROM) 1726 urtwn_dump_rom_contents(sc, rom, size); 1727#endif 1728 1729 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1730 1731 if (error != 0) { 1732 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1733 __func__); 1734 } 1735 1736 return (error); 1737#undef URTWN_CHK 1738} 1739 1740static int 1741urtwn_efuse_switch_power(struct urtwn_softc *sc) 1742{ 1743 usb_error_t error; 1744 uint32_t reg; 1745 1746 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1747 if (error != USB_ERR_NORMAL_COMPLETION) 1748 return (EIO); 1749 1750 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1751 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1752 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1753 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1754 if (error != USB_ERR_NORMAL_COMPLETION) 1755 return (EIO); 1756 } 1757 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1758 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1759 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1760 reg | R92C_SYS_FUNC_EN_ELDR); 1761 if (error != USB_ERR_NORMAL_COMPLETION) 1762 return (EIO); 1763 } 1764 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1765 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1766 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1767 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1768 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1769 if (error != USB_ERR_NORMAL_COMPLETION) 1770 return (EIO); 1771 } 1772 1773 return (0); 1774} 1775 1776static int 1777urtwn_read_chipid(struct urtwn_softc *sc) 1778{ 1779 uint32_t reg; 1780 1781 if (sc->chip & URTWN_CHIP_88E) 1782 return (0); 1783 1784 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1785 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1786 return (EIO); 1787 1788 if (reg & R92C_SYS_CFG_TYPE_92C) { 1789 sc->chip |= URTWN_CHIP_92C; 1790 /* Check if it is a castrated 8192C. */ 1791 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1792 R92C_HPON_FSM_CHIP_BONDING_ID) == 1793 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1794 sc->chip |= URTWN_CHIP_92C_1T2R; 1795 } 1796 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1797 sc->chip |= URTWN_CHIP_UMC; 1798 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1799 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1800 } 1801 return (0); 1802} 1803 1804static int 1805urtwn_read_rom(struct urtwn_softc *sc) 1806{ 1807 struct r92c_rom *rom = &sc->rom.r92c_rom; 1808 int error; 1809 1810 /* Read full ROM image. */ 1811 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1812 if (error != 0) 1813 return (error); 1814 1815 /* XXX Weird but this is what the vendor driver does. */ 1816 sc->last_rom_addr = 0x1fa; 1817 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1818 if (error != 0) 1819 return (error); 1820 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: PA setting=0x%x\n", __func__, 1821 sc->pa_setting); 1822 1823 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1824 1825 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1826 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type=%d\n", 1827 __func__, sc->regulatory); 1828 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1829 1830 sc->sc_rf_write = urtwn_r92c_rf_write; 1831 sc->sc_power_on = urtwn_r92c_power_on; 1832 sc->sc_power_off = urtwn_r92c_power_off; 1833 1834 return (0); 1835} 1836 1837static int 1838urtwn_r88e_read_rom(struct urtwn_softc *sc) 1839{ 1840 struct r88e_rom *rom = &sc->rom.r88e_rom; 1841 int error; 1842 1843 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(sc->rom.r88e_rom)); 1844 if (error != 0) 1845 return (error); 1846 1847 sc->bw20_tx_pwr_diff = (rom->tx_pwr_diff >> 4); 1848 if (sc->bw20_tx_pwr_diff & 0x08) 1849 sc->bw20_tx_pwr_diff |= 0xf0; 1850 sc->ofdm_tx_pwr_diff = (rom->tx_pwr_diff & 0xf); 1851 if (sc->ofdm_tx_pwr_diff & 0x08) 1852 sc->ofdm_tx_pwr_diff |= 0xf0; 1853 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 1854 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type %d\n", 1855 __func__,sc->regulatory); 1856 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1857 1858 sc->sc_rf_write = urtwn_r88e_rf_write; 1859 sc->sc_power_on = urtwn_r88e_power_on; 1860 sc->sc_power_off = urtwn_r88e_power_off; 1861 1862 return (0); 1863} 1864 1865/* 1866 * Initialize rate adaptation in firmware. 1867 */ 1868static int 1869urtwn_ra_init(struct urtwn_softc *sc) 1870{ 1871 struct ieee80211com *ic = &sc->sc_ic; 1872 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1873 struct ieee80211_node *ni; 1874 struct ieee80211_rateset *rs, *rs_ht; 1875 struct r92c_fw_cmd_macid_cfg cmd; 1876 uint32_t rates, basicrates; 1877 uint8_t mode; 1878 int maxrate, maxbasicrate, error, i, j; 1879 1880 ni = ieee80211_ref_node(vap->iv_bss); 1881 rs = &ni->ni_rates; 1882 rs_ht = (struct ieee80211_rateset *) &ni->ni_htrates; 1883 1884 /* Get normal and basic rates mask. */ 1885 rates = basicrates = 0; 1886 maxrate = maxbasicrate = 0; 1887 1888 /* This is for 11bg */ 1889 for (i = 0; i < rs->rs_nrates; i++) { 1890 /* Convert 802.11 rate to HW rate index. */ 1891 for (j = 0; j < nitems(ridx2rate); j++) 1892 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1893 ridx2rate[j]) 1894 break; 1895 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1896 continue; 1897 rates |= 1 << j; 1898 if (j > maxrate) 1899 maxrate = j; 1900 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1901 basicrates |= 1 << j; 1902 if (j > maxbasicrate) 1903 maxbasicrate = j; 1904 } 1905 } 1906 1907 /* If we're doing 11n, enable 11n rates */ 1908 if (ni->ni_flags & IEEE80211_NODE_HT) { 1909 for (i = 0; i < rs_ht->rs_nrates; i++) { 1910 if ((rs_ht->rs_rates[i] & 0x7f) > 0xf) 1911 continue; 1912 /* 11n rates start at index 12 */ 1913 j = ((rs_ht->rs_rates[i]) & 0xf) + 12; 1914 rates |= (1 << j); 1915 1916 /* Guard against the rate table being oddly ordered */ 1917 if (j > maxrate) 1918 maxrate = j; 1919 } 1920 } 1921 1922#if 0 1923 if (ic->ic_curmode == IEEE80211_MODE_11NG) 1924 raid = R92C_RAID_11GN; 1925#endif 1926 /* NB: group addressed frames are done at 11bg rates for now */ 1927 if (ic->ic_curmode == IEEE80211_MODE_11B) 1928 mode = R92C_RAID_11B; 1929 else 1930 mode = R92C_RAID_11BG; 1931 /* XXX misleading 'mode' value here for unicast frames */ 1932 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, 1933 "%s: mode 0x%x, rates 0x%08x, basicrates 0x%08x\n", __func__, 1934 mode, rates, basicrates); 1935 1936 /* Set rates mask for group addressed frames. */ 1937 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1938 cmd.mask = htole32(mode << 28 | basicrates); 1939 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1940 if (error != 0) { 1941 ieee80211_free_node(ni); 1942 device_printf(sc->sc_dev, 1943 "could not add broadcast station\n"); 1944 return (error); 1945 } 1946 1947 /* Set initial MRR rate. */ 1948 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxbasicrate %d\n", __func__, 1949 maxbasicrate); 1950 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1951 maxbasicrate); 1952 1953 /* Set rates mask for unicast frames. */ 1954 if (ni->ni_flags & IEEE80211_NODE_HT) 1955 mode = R92C_RAID_11GN; 1956 else if (ic->ic_curmode == IEEE80211_MODE_11B) 1957 mode = R92C_RAID_11B; 1958 else 1959 mode = R92C_RAID_11BG; 1960 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1961 cmd.mask = htole32(mode << 28 | rates); 1962 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1963 if (error != 0) { 1964 ieee80211_free_node(ni); 1965 device_printf(sc->sc_dev, "could not add BSS station\n"); 1966 return (error); 1967 } 1968 /* Set initial MRR rate. */ 1969 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxrate %d\n", __func__, 1970 maxrate); 1971 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1972 maxrate); 1973 1974 /* Indicate highest supported rate. */ 1975 if (ni->ni_flags & IEEE80211_NODE_HT) 1976 ni->ni_txrate = rs_ht->rs_rates[rs_ht->rs_nrates - 1] 1977 | IEEE80211_RATE_MCS; 1978 else 1979 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1980 ieee80211_free_node(ni); 1981 1982 return (0); 1983} 1984 1985static void 1986urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1987{ 1988 struct r92c_tx_desc *txd = &uvp->bcn_desc; 1989 1990 txd->txdw0 = htole32( 1991 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 1992 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1993 txd->txdw1 = htole32( 1994 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 1995 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1996 1997 if (sc->chip & URTWN_CHIP_88E) { 1998 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 1999 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 2000 } else { 2001 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 2002 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2003 } 2004 2005 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 2006 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 2007} 2008 2009static int 2010urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 2011{ 2012 struct ieee80211vap *vap = ni->ni_vap; 2013 struct urtwn_vap *uvp = URTWN_VAP(vap); 2014 struct mbuf *m; 2015 int error; 2016 2017 URTWN_ASSERT_LOCKED(sc); 2018 2019 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 2020 return (EINVAL); 2021 2022 m = ieee80211_beacon_alloc(ni); 2023 if (m == NULL) { 2024 device_printf(sc->sc_dev, 2025 "%s: could not allocate beacon frame\n", __func__); 2026 return (ENOMEM); 2027 } 2028 2029 if (uvp->bcn_mbuf != NULL) 2030 m_freem(uvp->bcn_mbuf); 2031 2032 uvp->bcn_mbuf = m; 2033 2034 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 2035 return (error); 2036 2037 /* XXX bcnq stuck workaround */ 2038 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 2039 return (error); 2040 2041 URTWN_DPRINTF(sc, URTWN_DEBUG_BEACON, "%s: beacon was %srecognized\n", 2042 __func__, urtwn_read_1(sc, R92C_TDECTRL + 2) & 2043 (R92C_TDECTRL_BCN_VALID >> 16) ? "" : "not "); 2044 2045 return (0); 2046} 2047 2048static void 2049urtwn_update_beacon(struct ieee80211vap *vap, int item) 2050{ 2051 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2052 struct urtwn_vap *uvp = URTWN_VAP(vap); 2053 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 2054 struct ieee80211_node *ni = vap->iv_bss; 2055 int mcast = 0; 2056 2057 URTWN_LOCK(sc); 2058 if (uvp->bcn_mbuf == NULL) { 2059 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 2060 if (uvp->bcn_mbuf == NULL) { 2061 device_printf(sc->sc_dev, 2062 "%s: could not allocate beacon frame\n", __func__); 2063 URTWN_UNLOCK(sc); 2064 return; 2065 } 2066 } 2067 URTWN_UNLOCK(sc); 2068 2069 if (item == IEEE80211_BEACON_TIM) 2070 mcast = 1; /* XXX */ 2071 2072 setbit(bo->bo_flags, item); 2073 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 2074 2075 URTWN_LOCK(sc); 2076 urtwn_tx_beacon(sc, uvp); 2077 URTWN_UNLOCK(sc); 2078} 2079 2080/* 2081 * Push a beacon frame into the chip. Beacon will 2082 * be repeated by the chip every R92C_BCN_INTERVAL. 2083 */ 2084static int 2085urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2086{ 2087 struct r92c_tx_desc *desc = &uvp->bcn_desc; 2088 struct urtwn_data *bf; 2089 2090 URTWN_ASSERT_LOCKED(sc); 2091 2092 bf = urtwn_getbuf(sc); 2093 if (bf == NULL) 2094 return (ENOMEM); 2095 2096 memcpy(bf->buf, desc, sizeof(*desc)); 2097 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 2098 2099 sc->sc_txtimer = 5; 2100 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2101 2102 return (0); 2103} 2104 2105static int 2106urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2107 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2108{ 2109 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2110 uint8_t i; 2111 2112 if (!(&vap->iv_nw_keys[0] <= k && 2113 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2114 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2115 URTWN_LOCK(sc); 2116 /* 2117 * First 4 slots for group keys, 2118 * what is left - for pairwise. 2119 * XXX incompatible with IBSS RSN. 2120 */ 2121 for (i = IEEE80211_WEP_NKID; 2122 i < R92C_CAM_ENTRY_COUNT; i++) { 2123 if ((sc->keys_bmap & (1 << i)) == 0) { 2124 sc->keys_bmap |= 1 << i; 2125 *keyix = i; 2126 break; 2127 } 2128 } 2129 URTWN_UNLOCK(sc); 2130 if (i == R92C_CAM_ENTRY_COUNT) { 2131 device_printf(sc->sc_dev, 2132 "%s: no free space in the key table\n", 2133 __func__); 2134 return 0; 2135 } 2136 } else 2137 *keyix = 0; 2138 } else { 2139 *keyix = k - vap->iv_nw_keys; 2140 } 2141 *rxkeyix = *keyix; 2142 return 1; 2143} 2144 2145static void 2146urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data) 2147{ 2148 struct ieee80211_key *k = &data->key; 2149 uint8_t algo, keyid; 2150 int i, error; 2151 2152 if (k->wk_keyix < IEEE80211_WEP_NKID) 2153 keyid = k->wk_keyix; 2154 else 2155 keyid = 0; 2156 2157 /* Map net80211 cipher to HW crypto algorithm. */ 2158 switch (k->wk_cipher->ic_cipher) { 2159 case IEEE80211_CIPHER_WEP: 2160 if (k->wk_keylen < 8) 2161 algo = R92C_CAM_ALGO_WEP40; 2162 else 2163 algo = R92C_CAM_ALGO_WEP104; 2164 break; 2165 case IEEE80211_CIPHER_TKIP: 2166 algo = R92C_CAM_ALGO_TKIP; 2167 break; 2168 case IEEE80211_CIPHER_AES_CCM: 2169 algo = R92C_CAM_ALGO_AES; 2170 break; 2171 default: 2172 device_printf(sc->sc_dev, "%s: undefined cipher %d\n", 2173 __func__, k->wk_cipher->ic_cipher); 2174 return; 2175 } 2176 2177 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2178 "%s: keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, " 2179 "macaddr %s\n", __func__, k->wk_keyix, keyid, 2180 k->wk_cipher->ic_cipher, algo, k->wk_flags, k->wk_keylen, 2181 ether_sprintf(k->wk_macaddr)); 2182 2183 /* Write key. */ 2184 for (i = 0; i < 4; i++) { 2185 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 2186 LE_READ_4(&k->wk_key[i * 4])); 2187 if (error != 0) 2188 goto fail; 2189 } 2190 2191 /* Write CTL0 last since that will validate the CAM entry. */ 2192 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 2193 LE_READ_4(&k->wk_macaddr[2])); 2194 if (error != 0) 2195 goto fail; 2196 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 2197 SM(R92C_CAM_ALGO, algo) | 2198 SM(R92C_CAM_KEYID, keyid) | 2199 SM(R92C_CAM_MACLO, LE_READ_2(&k->wk_macaddr[0])) | 2200 R92C_CAM_VALID); 2201 if (error != 0) 2202 goto fail; 2203 2204 return; 2205 2206fail: 2207 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error); 2208} 2209 2210static void 2211urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data) 2212{ 2213 struct ieee80211_key *k = &data->key; 2214 int i; 2215 2216 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2217 "%s: keyix %d, flags %04X, macaddr %s\n", __func__, 2218 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr)); 2219 2220 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0); 2221 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0); 2222 2223 /* Clear key. */ 2224 for (i = 0; i < 4; i++) 2225 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0); 2226 sc->keys_bmap &= ~(1 << k->wk_keyix); 2227} 2228 2229static int 2230urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 2231{ 2232 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2233 2234 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2235 /* Not for us. */ 2236 return (1); 2237 } 2238 2239 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb)); 2240} 2241 2242static int 2243urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2244{ 2245 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2246 2247 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2248 /* Not for us. */ 2249 return (1); 2250 } 2251 2252 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb)); 2253} 2254 2255static void 2256urtwn_tsf_task_adhoc(void *arg, int pending) 2257{ 2258 struct ieee80211vap *vap = arg; 2259 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2260 struct ieee80211_node *ni; 2261 uint32_t reg; 2262 2263 URTWN_LOCK(sc); 2264 ni = ieee80211_ref_node(vap->iv_bss); 2265 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 2266 2267 /* Accept beacons with the same BSSID. */ 2268 urtwn_set_rx_bssid_all(sc, 0); 2269 2270 /* Enable synchronization. */ 2271 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 2272 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2273 2274 /* Synchronize. */ 2275 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 2276 2277 /* Disable synchronization. */ 2278 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 2279 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2280 2281 /* Remove beacon filter. */ 2282 urtwn_set_rx_bssid_all(sc, 1); 2283 2284 /* Enable beaconing. */ 2285 urtwn_write_1(sc, R92C_MBID_NUM, 2286 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2287 reg |= R92C_BCN_CTRL_EN_BCN; 2288 2289 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2290 ieee80211_free_node(ni); 2291 URTWN_UNLOCK(sc); 2292} 2293 2294static void 2295urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 2296{ 2297 struct ieee80211com *ic = &sc->sc_ic; 2298 struct urtwn_vap *uvp = URTWN_VAP(vap); 2299 2300 /* Reset TSF. */ 2301 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2302 2303 switch (vap->iv_opmode) { 2304 case IEEE80211_M_STA: 2305 /* Enable TSF synchronization. */ 2306 urtwn_write_1(sc, R92C_BCN_CTRL, 2307 urtwn_read_1(sc, R92C_BCN_CTRL) & 2308 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 2309 break; 2310 case IEEE80211_M_IBSS: 2311 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 2312 break; 2313 case IEEE80211_M_HOSTAP: 2314 /* Enable beaconing. */ 2315 urtwn_write_1(sc, R92C_MBID_NUM, 2316 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2317 urtwn_write_1(sc, R92C_BCN_CTRL, 2318 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 2319 break; 2320 default: 2321 device_printf(sc->sc_dev, "undefined opmode %d\n", 2322 vap->iv_opmode); 2323 return; 2324 } 2325} 2326 2327static void 2328urtwn_get_tsf(struct urtwn_softc *sc, uint64_t *buf) 2329{ 2330 urtwn_read_region_1(sc, R92C_TSFTR, (uint8_t *)buf, sizeof(*buf)); 2331} 2332 2333static void 2334urtwn_set_led(struct urtwn_softc *sc, int led, int on) 2335{ 2336 uint8_t reg; 2337 2338 if (led == URTWN_LED_LINK) { 2339 if (sc->chip & URTWN_CHIP_88E) { 2340 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 2341 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 2342 if (!on) { 2343 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 2344 urtwn_write_1(sc, R92C_LEDCFG2, 2345 reg | R92C_LEDCFG0_DIS); 2346 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 2347 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 2348 0xfe); 2349 } 2350 } else { 2351 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 2352 if (!on) 2353 reg |= R92C_LEDCFG0_DIS; 2354 urtwn_write_1(sc, R92C_LEDCFG0, reg); 2355 } 2356 sc->ledlink = on; /* Save LED state. */ 2357 } 2358} 2359 2360static void 2361urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 2362{ 2363 uint8_t reg; 2364 2365 reg = urtwn_read_1(sc, R92C_MSR); 2366 reg = (reg & ~R92C_MSR_MASK) | mode; 2367 urtwn_write_1(sc, R92C_MSR, reg); 2368} 2369 2370static void 2371urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 2372 const struct ieee80211_rx_stats *rxs, 2373 int rssi, int nf) 2374{ 2375 struct ieee80211vap *vap = ni->ni_vap; 2376 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2377 struct urtwn_vap *uvp = URTWN_VAP(vap); 2378 uint64_t ni_tstamp, curr_tstamp; 2379 2380 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 2381 2382 if (vap->iv_state == IEEE80211_S_RUN && 2383 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 2384 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 2385 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 2386 URTWN_LOCK(sc); 2387 urtwn_get_tsf(sc, &curr_tstamp); 2388 URTWN_UNLOCK(sc); 2389 curr_tstamp = le64toh(curr_tstamp); 2390 2391 if (ni_tstamp >= curr_tstamp) 2392 (void) ieee80211_ibss_merge(ni); 2393 } 2394} 2395 2396static int 2397urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2398{ 2399 struct urtwn_vap *uvp = URTWN_VAP(vap); 2400 struct ieee80211com *ic = vap->iv_ic; 2401 struct urtwn_softc *sc = ic->ic_softc; 2402 struct ieee80211_node *ni; 2403 enum ieee80211_state ostate; 2404 uint32_t reg; 2405 uint8_t mode; 2406 int error = 0; 2407 2408 ostate = vap->iv_state; 2409 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s -> %s\n", 2410 ieee80211_state_name[ostate], ieee80211_state_name[nstate]); 2411 2412 IEEE80211_UNLOCK(ic); 2413 URTWN_LOCK(sc); 2414 callout_stop(&sc->sc_watchdog_ch); 2415 2416 if (ostate == IEEE80211_S_RUN) { 2417 /* Stop calibration. */ 2418 callout_stop(&sc->sc_calib_to); 2419 2420 /* Turn link LED off. */ 2421 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2422 2423 /* Set media status to 'No Link'. */ 2424 urtwn_set_mode(sc, R92C_MSR_NOLINK); 2425 2426 /* Stop Rx of data frames. */ 2427 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2428 2429 /* Disable TSF synchronization. */ 2430 urtwn_write_1(sc, R92C_BCN_CTRL, 2431 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 2432 R92C_BCN_CTRL_DIS_TSF_UDT0); 2433 2434 /* Disable beaconing. */ 2435 urtwn_write_1(sc, R92C_MBID_NUM, 2436 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 2437 2438 /* Reset TSF. */ 2439 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2440 2441 /* Reset EDCA parameters. */ 2442 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2443 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2444 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2445 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2446 } 2447 2448 switch (nstate) { 2449 case IEEE80211_S_INIT: 2450 /* Turn link LED off. */ 2451 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2452 break; 2453 case IEEE80211_S_SCAN: 2454 /* Pause AC Tx queues. */ 2455 urtwn_write_1(sc, R92C_TXPAUSE, 2456 urtwn_read_1(sc, R92C_TXPAUSE) | R92C_TX_QUEUE_AC); 2457 break; 2458 case IEEE80211_S_AUTH: 2459 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2460 break; 2461 case IEEE80211_S_RUN: 2462 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2463 /* Turn link LED on. */ 2464 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2465 break; 2466 } 2467 2468 ni = ieee80211_ref_node(vap->iv_bss); 2469 2470 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2471 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2472 device_printf(sc->sc_dev, 2473 "%s: could not move to RUN state\n", __func__); 2474 error = EINVAL; 2475 goto end_run; 2476 } 2477 2478 switch (vap->iv_opmode) { 2479 case IEEE80211_M_STA: 2480 mode = R92C_MSR_INFRA; 2481 break; 2482 case IEEE80211_M_IBSS: 2483 mode = R92C_MSR_ADHOC; 2484 break; 2485 case IEEE80211_M_HOSTAP: 2486 mode = R92C_MSR_AP; 2487 break; 2488 default: 2489 device_printf(sc->sc_dev, "undefined opmode %d\n", 2490 vap->iv_opmode); 2491 error = EINVAL; 2492 goto end_run; 2493 } 2494 2495 /* Set media status to 'Associated'. */ 2496 urtwn_set_mode(sc, mode); 2497 2498 /* Set BSSID. */ 2499 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2500 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2501 2502 if (ic->ic_curmode == IEEE80211_MODE_11B) 2503 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2504 else /* 802.11b/g */ 2505 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2506 2507 /* Enable Rx of data frames. */ 2508 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2509 2510 /* Flush all AC queues. */ 2511 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2512 2513 /* Set beacon interval. */ 2514 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2515 2516 /* Allow Rx from our BSSID only. */ 2517 if (ic->ic_promisc == 0) { 2518 reg = urtwn_read_4(sc, R92C_RCR); 2519 2520 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 2521 reg |= R92C_RCR_CBSSID_DATA; 2522 if (vap->iv_opmode != IEEE80211_M_IBSS) 2523 reg |= R92C_RCR_CBSSID_BCN; 2524 2525 urtwn_write_4(sc, R92C_RCR, reg); 2526 } 2527 2528 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2529 vap->iv_opmode == IEEE80211_M_IBSS) { 2530 error = urtwn_setup_beacon(sc, ni); 2531 if (error != 0) { 2532 device_printf(sc->sc_dev, 2533 "unable to push beacon into the chip, " 2534 "error %d\n", error); 2535 goto end_run; 2536 } 2537 } 2538 2539 /* Enable TSF synchronization. */ 2540 urtwn_tsf_sync_enable(sc, vap); 2541 2542 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2543 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2544 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2545 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2546 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2547 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2548 2549 /* Intialize rate adaptation. */ 2550 if (!(sc->chip & URTWN_CHIP_88E)) 2551 urtwn_ra_init(sc); 2552 /* Turn link LED on. */ 2553 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2554 2555 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2556 /* Reset temperature calibration state machine. */ 2557 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 2558 sc->thcal_lctemp = 0; 2559 /* Start periodic calibration. */ 2560 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2561 2562end_run: 2563 ieee80211_free_node(ni); 2564 break; 2565 default: 2566 break; 2567 } 2568 2569 URTWN_UNLOCK(sc); 2570 IEEE80211_LOCK(ic); 2571 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2572} 2573 2574static void 2575urtwn_calib_to(void *arg) 2576{ 2577 struct urtwn_softc *sc = arg; 2578 2579 /* Do it in a process context. */ 2580 urtwn_cmd_sleepable(sc, NULL, 0, urtwn_calib_cb); 2581} 2582 2583static void 2584urtwn_calib_cb(struct urtwn_softc *sc, union sec_param *data) 2585{ 2586 /* Do temperature compensation. */ 2587 urtwn_temp_calib(sc); 2588 2589 if ((urtwn_read_1(sc, R92C_MSR) & R92C_MSR_MASK) != R92C_MSR_NOLINK) 2590 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2591} 2592 2593static void 2594urtwn_watchdog(void *arg) 2595{ 2596 struct urtwn_softc *sc = arg; 2597 2598 if (sc->sc_txtimer > 0) { 2599 if (--sc->sc_txtimer == 0) { 2600 device_printf(sc->sc_dev, "device timeout\n"); 2601 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2602 return; 2603 } 2604 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2605 } 2606} 2607 2608static void 2609urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2610{ 2611 int pwdb; 2612 2613 /* Convert antenna signal to percentage. */ 2614 if (rssi <= -100 || rssi >= 20) 2615 pwdb = 0; 2616 else if (rssi >= 0) 2617 pwdb = 100; 2618 else 2619 pwdb = 100 + rssi; 2620 if (!(sc->chip & URTWN_CHIP_88E)) { 2621 if (rate <= URTWN_RIDX_CCK11) { 2622 /* CCK gain is smaller than OFDM/MCS gain. */ 2623 pwdb += 6; 2624 if (pwdb > 100) 2625 pwdb = 100; 2626 if (pwdb <= 14) 2627 pwdb -= 4; 2628 else if (pwdb <= 26) 2629 pwdb -= 8; 2630 else if (pwdb <= 34) 2631 pwdb -= 6; 2632 else if (pwdb <= 42) 2633 pwdb -= 2; 2634 } 2635 } 2636 if (sc->avg_pwdb == -1) /* Init. */ 2637 sc->avg_pwdb = pwdb; 2638 else if (sc->avg_pwdb < pwdb) 2639 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2640 else 2641 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2642 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: PWDB %d, EMA %d\n", __func__, 2643 pwdb, sc->avg_pwdb); 2644} 2645 2646static int8_t 2647urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2648{ 2649 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2650 struct r92c_rx_phystat *phy; 2651 struct r92c_rx_cck *cck; 2652 uint8_t rpt; 2653 int8_t rssi; 2654 2655 if (rate <= URTWN_RIDX_CCK11) { 2656 cck = (struct r92c_rx_cck *)physt; 2657 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2658 rpt = (cck->agc_rpt >> 5) & 0x3; 2659 rssi = (cck->agc_rpt & 0x1f) << 1; 2660 } else { 2661 rpt = (cck->agc_rpt >> 6) & 0x3; 2662 rssi = cck->agc_rpt & 0x3e; 2663 } 2664 rssi = cckoff[rpt] - rssi; 2665 } else { /* OFDM/HT. */ 2666 phy = (struct r92c_rx_phystat *)physt; 2667 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2668 } 2669 return (rssi); 2670} 2671 2672static int8_t 2673urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2674{ 2675 struct r92c_rx_phystat *phy; 2676 struct r88e_rx_cck *cck; 2677 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2678 int8_t rssi; 2679 2680 rssi = 0; 2681 if (rate <= URTWN_RIDX_CCK11) { 2682 cck = (struct r88e_rx_cck *)physt; 2683 cck_agc_rpt = cck->agc_rpt; 2684 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2685 vga_idx = cck_agc_rpt & 0x1f; 2686 switch (lna_idx) { 2687 case 7: 2688 if (vga_idx <= 27) 2689 rssi = -100 + 2* (27 - vga_idx); 2690 else 2691 rssi = -100; 2692 break; 2693 case 6: 2694 rssi = -48 + 2 * (2 - vga_idx); 2695 break; 2696 case 5: 2697 rssi = -42 + 2 * (7 - vga_idx); 2698 break; 2699 case 4: 2700 rssi = -36 + 2 * (7 - vga_idx); 2701 break; 2702 case 3: 2703 rssi = -24 + 2 * (7 - vga_idx); 2704 break; 2705 case 2: 2706 rssi = -12 + 2 * (5 - vga_idx); 2707 break; 2708 case 1: 2709 rssi = 8 - (2 * vga_idx); 2710 break; 2711 case 0: 2712 rssi = 14 - (2 * vga_idx); 2713 break; 2714 } 2715 rssi += 6; 2716 } else { /* OFDM/HT. */ 2717 phy = (struct r92c_rx_phystat *)physt; 2718 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2719 } 2720 return (rssi); 2721} 2722 2723static __inline uint8_t 2724rate2ridx(uint8_t rate) 2725{ 2726 if (rate & IEEE80211_RATE_MCS) { 2727 /* 11n rates start at idx 12 */ 2728 return ((rate & 0xf) + 12); 2729 } 2730 switch (rate) { 2731 /* 11g */ 2732 case 12: return 4; 2733 case 18: return 5; 2734 case 24: return 6; 2735 case 36: return 7; 2736 case 48: return 8; 2737 case 72: return 9; 2738 case 96: return 10; 2739 case 108: return 11; 2740 /* 11b */ 2741 case 2: return 0; 2742 case 4: return 1; 2743 case 11: return 2; 2744 case 22: return 3; 2745 default: return 0; 2746 } 2747} 2748 2749static int 2750urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2751 struct mbuf *m, struct urtwn_data *data) 2752{ 2753 const struct ieee80211_txparam *tp; 2754 struct ieee80211com *ic = &sc->sc_ic; 2755 struct ieee80211vap *vap = ni->ni_vap; 2756 struct ieee80211_key *k = NULL; 2757 struct ieee80211_channel *chan; 2758 struct ieee80211_frame *wh; 2759 struct r92c_tx_desc *txd; 2760 uint8_t macid, raid, rate, ridx, subtype, type, tid, qsel; 2761 int hasqos, ismcast; 2762 2763 URTWN_ASSERT_LOCKED(sc); 2764 2765 /* 2766 * Software crypto. 2767 */ 2768 wh = mtod(m, struct ieee80211_frame *); 2769 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2770 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2771 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2772 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2773 2774 /* Select TX ring for this frame. */ 2775 if (hasqos) { 2776 tid = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2777 tid &= IEEE80211_QOS_TID; 2778 } else 2779 tid = 0; 2780 2781 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2782 ni->ni_chan : ic->ic_curchan; 2783 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2784 2785 /* Choose a TX rate index. */ 2786 if (type == IEEE80211_FC0_TYPE_MGT) 2787 rate = tp->mgmtrate; 2788 else if (ismcast) 2789 rate = tp->mcastrate; 2790 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2791 rate = tp->ucastrate; 2792 else if (m->m_flags & M_EAPOL) 2793 rate = tp->mgmtrate; 2794 else { 2795 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2796 /* XXX pass pktlen */ 2797 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2798 rate = ni->ni_txrate; 2799 } else { 2800 /* XXX TODO: drop the default rate for 11b/11g? */ 2801 if (ni->ni_flags & IEEE80211_NODE_HT) 2802 rate = IEEE80211_RATE_MCS | 0x4; /* MCS4 */ 2803 else if (ic->ic_curmode != IEEE80211_MODE_11B) 2804 rate = 108; 2805 else 2806 rate = 22; 2807 } 2808 } 2809 2810 /* 2811 * XXX TODO: this should be per-node, for 11b versus 11bg 2812 * nodes in hostap mode 2813 */ 2814 ridx = rate2ridx(rate); 2815 if (ni->ni_flags & IEEE80211_NODE_HT) 2816 raid = R92C_RAID_11GN; 2817 else if (ic->ic_curmode != IEEE80211_MODE_11B) 2818 raid = R92C_RAID_11BG; 2819 else 2820 raid = R92C_RAID_11B; 2821 2822 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2823 k = ieee80211_crypto_encap(ni, m); 2824 if (k == NULL) { 2825 device_printf(sc->sc_dev, 2826 "ieee80211_crypto_encap returns NULL.\n"); 2827 return (ENOBUFS); 2828 } 2829 2830 /* in case packet header moved, reset pointer */ 2831 wh = mtod(m, struct ieee80211_frame *); 2832 } 2833 2834 /* Fill Tx descriptor. */ 2835 txd = (struct r92c_tx_desc *)data->buf; 2836 memset(txd, 0, sizeof(*txd)); 2837 2838 txd->txdw0 |= htole32( 2839 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2840 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2841 if (ismcast) 2842 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2843 2844 if (!ismcast) { 2845 if (sc->chip & URTWN_CHIP_88E) { 2846 struct urtwn_node *un = URTWN_NODE(ni); 2847 macid = un->id; 2848 } else 2849 macid = URTWN_MACID_BSS; 2850 2851 if (type == IEEE80211_FC0_TYPE_DATA) { 2852 qsel = tid % URTWN_MAX_TID; 2853 2854 if (sc->chip & URTWN_CHIP_88E) { 2855 txd->txdw2 |= htole32( 2856 R88E_TXDW2_AGGBK | 2857 R88E_TXDW2_CCX_RPT); 2858 } else 2859 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2860 2861 /* protmode, non-HT */ 2862 /* XXX TODO: noack frames? */ 2863 if ((rate & 0x80) == 0 && 2864 (ic->ic_flags & IEEE80211_F_USEPROT)) { 2865 switch (ic->ic_protmode) { 2866 case IEEE80211_PROT_CTSONLY: 2867 txd->txdw4 |= htole32( 2868 R92C_TXDW4_CTS2SELF | 2869 R92C_TXDW4_HWRTSEN); 2870 break; 2871 case IEEE80211_PROT_RTSCTS: 2872 txd->txdw4 |= htole32( 2873 R92C_TXDW4_RTSEN | 2874 R92C_TXDW4_HWRTSEN); 2875 break; 2876 default: 2877 break; 2878 } 2879 } 2880 2881 /* protmode, HT */ 2882 /* XXX TODO: noack frames? */ 2883 if ((rate & 0x80) && 2884 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) { 2885 txd->txdw4 |= htole32( 2886 R92C_TXDW4_RTSEN | 2887 R92C_TXDW4_HWRTSEN); 2888 } 2889 2890 /* XXX TODO: rtsrate is configurable? 24mbit may 2891 * be a bit high for RTS rate? */ 2892 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2893 URTWN_RIDX_OFDM24)); 2894 2895 txd->txdw5 |= htole32(0x0001ff00); 2896 } else /* IEEE80211_FC0_TYPE_MGT */ 2897 qsel = R92C_TXDW1_QSEL_MGNT; 2898 } else { 2899 macid = URTWN_MACID_BC; 2900 qsel = R92C_TXDW1_QSEL_MGNT; 2901 } 2902 2903 txd->txdw1 |= htole32( 2904 SM(R92C_TXDW1_QSEL, qsel) | 2905 SM(R92C_TXDW1_RAID, raid)); 2906 2907 /* XXX TODO: 40MHZ flag? */ 2908 /* XXX TODO: AMPDU flag? (AGG_ENABLE or AGG_BREAK?) Density shift? */ 2909 /* XXX Short preamble? */ 2910 /* XXX Short-GI? */ 2911 2912 if (sc->chip & URTWN_CHIP_88E) 2913 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 2914 else 2915 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 2916 2917 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2918 2919 /* Force this rate if needed. */ 2920 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 2921 (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) || 2922 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 2923 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2924 2925 if (!hasqos) { 2926 /* Use HW sequence numbering for non-QoS frames. */ 2927 if (sc->chip & URTWN_CHIP_88E) 2928 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2929 else 2930 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2931 } else { 2932 /* Set sequence number. */ 2933 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2934 } 2935 2936 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2937 uint8_t cipher; 2938 2939 switch (k->wk_cipher->ic_cipher) { 2940 case IEEE80211_CIPHER_WEP: 2941 case IEEE80211_CIPHER_TKIP: 2942 cipher = R92C_TXDW1_CIPHER_RC4; 2943 break; 2944 case IEEE80211_CIPHER_AES_CCM: 2945 cipher = R92C_TXDW1_CIPHER_AES; 2946 break; 2947 default: 2948 device_printf(sc->sc_dev, "%s: unknown cipher %d\n", 2949 __func__, k->wk_cipher->ic_cipher); 2950 return (EINVAL); 2951 } 2952 2953 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 2954 } 2955 2956 if (ieee80211_radiotap_active_vap(vap)) { 2957 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2958 2959 tap->wt_flags = 0; 2960 if (k != NULL) 2961 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2962 ieee80211_radiotap_tx(vap, m); 2963 } 2964 2965 data->ni = ni; 2966 2967 urtwn_tx_start(sc, m, type, data); 2968 2969 return (0); 2970} 2971 2972static int 2973urtwn_tx_raw(struct urtwn_softc *sc, struct ieee80211_node *ni, 2974 struct mbuf *m, struct urtwn_data *data, 2975 const struct ieee80211_bpf_params *params) 2976{ 2977 struct ieee80211vap *vap = ni->ni_vap; 2978 struct ieee80211_key *k = NULL; 2979 struct ieee80211_frame *wh; 2980 struct r92c_tx_desc *txd; 2981 uint8_t cipher, ridx, type; 2982 2983 /* Encrypt the frame if need be. */ 2984 cipher = R92C_TXDW1_CIPHER_NONE; 2985 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 2986 /* Retrieve key for TX. */ 2987 k = ieee80211_crypto_encap(ni, m); 2988 if (k == NULL) 2989 return (ENOBUFS); 2990 2991 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2992 switch (k->wk_cipher->ic_cipher) { 2993 case IEEE80211_CIPHER_WEP: 2994 case IEEE80211_CIPHER_TKIP: 2995 cipher = R92C_TXDW1_CIPHER_RC4; 2996 break; 2997 case IEEE80211_CIPHER_AES_CCM: 2998 cipher = R92C_TXDW1_CIPHER_AES; 2999 break; 3000 default: 3001 device_printf(sc->sc_dev, 3002 "%s: unknown cipher %d\n", 3003 __func__, k->wk_cipher->ic_cipher); 3004 return (EINVAL); 3005 } 3006 } 3007 } 3008 3009 /* XXX TODO: 11n checks, matching urtwn_tx_data() */ 3010 3011 wh = mtod(m, struct ieee80211_frame *); 3012 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3013 3014 /* Fill Tx descriptor. */ 3015 txd = (struct r92c_tx_desc *)data->buf; 3016 memset(txd, 0, sizeof(*txd)); 3017 3018 txd->txdw0 |= htole32( 3019 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 3020 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 3021 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3022 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 3023 3024 if (params->ibp_flags & IEEE80211_BPF_RTS) 3025 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN); 3026 if (params->ibp_flags & IEEE80211_BPF_CTS) 3027 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF); 3028 if (txd->txdw4 & htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_CTS2SELF)) { 3029 txd->txdw4 |= htole32(R92C_TXDW4_HWRTSEN); 3030 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 3031 URTWN_RIDX_OFDM24)); 3032 } 3033 3034 if (sc->chip & URTWN_CHIP_88E) 3035 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 3036 else 3037 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 3038 3039 /* XXX TODO: rate index/config (RAID) for 11n? */ 3040 txd->txdw1 |= htole32(SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT)); 3041 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 3042 3043 /* Choose a TX rate index. */ 3044 ridx = rate2ridx(params->ibp_rate0); 3045 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 3046 txd->txdw5 |= htole32(0x0001ff00); 3047 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3048 3049 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 3050 /* Use HW sequence numbering for non-QoS frames. */ 3051 if (sc->chip & URTWN_CHIP_88E) 3052 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 3053 else 3054 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 3055 } else { 3056 /* Set sequence number. */ 3057 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 3058 } 3059 3060 if (ieee80211_radiotap_active_vap(vap)) { 3061 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3062 3063 tap->wt_flags = 0; 3064 if (k != NULL) 3065 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3066 ieee80211_radiotap_tx(vap, m); 3067 } 3068 3069 data->ni = ni; 3070 3071 urtwn_tx_start(sc, m, type, data); 3072 3073 return (0); 3074} 3075 3076static void 3077urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 3078 struct urtwn_data *data) 3079{ 3080 struct usb_xfer *xfer; 3081 struct r92c_tx_desc *txd; 3082 uint16_t ac, sum; 3083 int i, xferlen; 3084 3085 URTWN_ASSERT_LOCKED(sc); 3086 3087 ac = M_WME_GETAC(m); 3088 3089 switch (type) { 3090 case IEEE80211_FC0_TYPE_CTL: 3091 case IEEE80211_FC0_TYPE_MGT: 3092 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 3093 break; 3094 default: 3095 xfer = sc->sc_xfer[wme2queue[ac].qid]; 3096 break; 3097 } 3098 3099 txd = (struct r92c_tx_desc *)data->buf; 3100 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 3101 3102 /* Compute Tx descriptor checksum. */ 3103 sum = 0; 3104 for (i = 0; i < sizeof(*txd) / 2; i++) 3105 sum ^= ((uint16_t *)txd)[i]; 3106 txd->txdsum = sum; /* NB: already little endian. */ 3107 3108 xferlen = sizeof(*txd) + m->m_pkthdr.len; 3109 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 3110 3111 data->buflen = xferlen; 3112 data->m = m; 3113 3114 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 3115 usbd_transfer_start(xfer); 3116} 3117 3118static int 3119urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 3120{ 3121 struct urtwn_softc *sc = ic->ic_softc; 3122 int error; 3123 3124 URTWN_LOCK(sc); 3125 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 3126 URTWN_UNLOCK(sc); 3127 return (ENXIO); 3128 } 3129 error = mbufq_enqueue(&sc->sc_snd, m); 3130 if (error) { 3131 URTWN_UNLOCK(sc); 3132 return (error); 3133 } 3134 urtwn_start(sc); 3135 URTWN_UNLOCK(sc); 3136 3137 return (0); 3138} 3139 3140static void 3141urtwn_start(struct urtwn_softc *sc) 3142{ 3143 struct ieee80211_node *ni; 3144 struct mbuf *m; 3145 struct urtwn_data *bf; 3146 3147 URTWN_ASSERT_LOCKED(sc); 3148 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 3149 bf = urtwn_getbuf(sc); 3150 if (bf == NULL) { 3151 mbufq_prepend(&sc->sc_snd, m); 3152 break; 3153 } 3154 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3155 m->m_pkthdr.rcvif = NULL; 3156 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 3157 if_inc_counter(ni->ni_vap->iv_ifp, 3158 IFCOUNTER_OERRORS, 1); 3159 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3160 m_freem(m); 3161 ieee80211_free_node(ni); 3162 break; 3163 } 3164 sc->sc_txtimer = 5; 3165 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3166 } 3167} 3168 3169static void 3170urtwn_parent(struct ieee80211com *ic) 3171{ 3172 struct urtwn_softc *sc = ic->ic_softc; 3173 3174 URTWN_LOCK(sc); 3175 if (sc->sc_flags & URTWN_DETACHED) { 3176 URTWN_UNLOCK(sc); 3177 return; 3178 } 3179 URTWN_UNLOCK(sc); 3180 3181 if (ic->ic_nrunning > 0) { 3182 if (urtwn_init(sc) != 0) { 3183 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3184 if (vap != NULL) 3185 ieee80211_stop(vap); 3186 } else 3187 ieee80211_start_all(ic); 3188 } else 3189 urtwn_stop(sc); 3190} 3191 3192static __inline int 3193urtwn_power_on(struct urtwn_softc *sc) 3194{ 3195 3196 return sc->sc_power_on(sc); 3197} 3198 3199static int 3200urtwn_r92c_power_on(struct urtwn_softc *sc) 3201{ 3202 uint32_t reg; 3203 usb_error_t error; 3204 int ntries; 3205 3206 /* Wait for autoload done bit. */ 3207 for (ntries = 0; ntries < 1000; ntries++) { 3208 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3209 break; 3210 urtwn_ms_delay(sc); 3211 } 3212 if (ntries == 1000) { 3213 device_printf(sc->sc_dev, 3214 "timeout waiting for chip autoload\n"); 3215 return (ETIMEDOUT); 3216 } 3217 3218 /* Unlock ISO/CLK/Power control register. */ 3219 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3220 if (error != USB_ERR_NORMAL_COMPLETION) 3221 return (EIO); 3222 /* Move SPS into PWM mode. */ 3223 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3224 if (error != USB_ERR_NORMAL_COMPLETION) 3225 return (EIO); 3226 urtwn_ms_delay(sc); 3227 3228 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3229 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3230 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3231 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3232 if (error != USB_ERR_NORMAL_COMPLETION) 3233 return (EIO); 3234 urtwn_ms_delay(sc); 3235 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3236 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3237 ~R92C_SYS_ISO_CTRL_MD2PP); 3238 if (error != USB_ERR_NORMAL_COMPLETION) 3239 return (EIO); 3240 } 3241 3242 /* Auto enable WLAN. */ 3243 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3244 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3245 if (error != USB_ERR_NORMAL_COMPLETION) 3246 return (EIO); 3247 for (ntries = 0; ntries < 1000; ntries++) { 3248 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3249 R92C_APS_FSMCO_APFM_ONMAC)) 3250 break; 3251 urtwn_ms_delay(sc); 3252 } 3253 if (ntries == 1000) { 3254 device_printf(sc->sc_dev, 3255 "timeout waiting for MAC auto ON\n"); 3256 return (ETIMEDOUT); 3257 } 3258 3259 /* Enable radio, GPIO and LED functions. */ 3260 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3261 R92C_APS_FSMCO_AFSM_HSUS | 3262 R92C_APS_FSMCO_PDN_EN | 3263 R92C_APS_FSMCO_PFM_ALDN); 3264 if (error != USB_ERR_NORMAL_COMPLETION) 3265 return (EIO); 3266 /* Release RF digital isolation. */ 3267 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3268 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3269 if (error != USB_ERR_NORMAL_COMPLETION) 3270 return (EIO); 3271 3272 /* Initialize MAC. */ 3273 error = urtwn_write_1(sc, R92C_APSD_CTRL, 3274 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3275 if (error != USB_ERR_NORMAL_COMPLETION) 3276 return (EIO); 3277 for (ntries = 0; ntries < 200; ntries++) { 3278 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3279 R92C_APSD_CTRL_OFF_STATUS)) 3280 break; 3281 urtwn_ms_delay(sc); 3282 } 3283 if (ntries == 200) { 3284 device_printf(sc->sc_dev, 3285 "timeout waiting for MAC initialization\n"); 3286 return (ETIMEDOUT); 3287 } 3288 3289 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3290 reg = urtwn_read_2(sc, R92C_CR); 3291 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3292 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3293 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3294 R92C_CR_ENSEC; 3295 error = urtwn_write_2(sc, R92C_CR, reg); 3296 if (error != USB_ERR_NORMAL_COMPLETION) 3297 return (EIO); 3298 3299 error = urtwn_write_1(sc, 0xfe10, 0x19); 3300 if (error != USB_ERR_NORMAL_COMPLETION) 3301 return (EIO); 3302 return (0); 3303} 3304 3305static int 3306urtwn_r88e_power_on(struct urtwn_softc *sc) 3307{ 3308 uint32_t reg; 3309 usb_error_t error; 3310 int ntries; 3311 3312 /* Wait for power ready bit. */ 3313 for (ntries = 0; ntries < 5000; ntries++) { 3314 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 3315 break; 3316 urtwn_ms_delay(sc); 3317 } 3318 if (ntries == 5000) { 3319 device_printf(sc->sc_dev, 3320 "timeout waiting for chip power up\n"); 3321 return (ETIMEDOUT); 3322 } 3323 3324 /* Reset BB. */ 3325 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3326 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3327 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3328 if (error != USB_ERR_NORMAL_COMPLETION) 3329 return (EIO); 3330 3331 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3332 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3333 if (error != USB_ERR_NORMAL_COMPLETION) 3334 return (EIO); 3335 3336 /* Disable HWPDN. */ 3337 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3338 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3339 if (error != USB_ERR_NORMAL_COMPLETION) 3340 return (EIO); 3341 3342 /* Disable WL suspend. */ 3343 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3344 urtwn_read_2(sc, R92C_APS_FSMCO) & 3345 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 3346 if (error != USB_ERR_NORMAL_COMPLETION) 3347 return (EIO); 3348 3349 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3350 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3351 if (error != USB_ERR_NORMAL_COMPLETION) 3352 return (EIO); 3353 for (ntries = 0; ntries < 5000; ntries++) { 3354 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3355 R92C_APS_FSMCO_APFM_ONMAC)) 3356 break; 3357 urtwn_ms_delay(sc); 3358 } 3359 if (ntries == 5000) 3360 return (ETIMEDOUT); 3361 3362 /* Enable LDO normal mode. */ 3363 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 3364 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~R92C_LPLDO_CTRL_SLEEP); 3365 if (error != USB_ERR_NORMAL_COMPLETION) 3366 return (EIO); 3367 3368 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3369 error = urtwn_write_2(sc, R92C_CR, 0); 3370 if (error != USB_ERR_NORMAL_COMPLETION) 3371 return (EIO); 3372 reg = urtwn_read_2(sc, R92C_CR); 3373 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3374 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3375 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3376 error = urtwn_write_2(sc, R92C_CR, reg); 3377 if (error != USB_ERR_NORMAL_COMPLETION) 3378 return (EIO); 3379 3380 return (0); 3381} 3382 3383static __inline void 3384urtwn_power_off(struct urtwn_softc *sc) 3385{ 3386 3387 return sc->sc_power_off(sc); 3388} 3389 3390static void 3391urtwn_r92c_power_off(struct urtwn_softc *sc) 3392{ 3393 uint32_t reg; 3394 3395 /* Block all Tx queues. */ 3396 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3397 3398 /* Disable RF */ 3399 urtwn_rf_write(sc, 0, 0, 0); 3400 3401 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3402 3403 /* Reset BB state machine */ 3404 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3405 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA | 3406 R92C_SYS_FUNC_EN_BB_GLB_RST); 3407 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3408 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3409 3410 /* 3411 * Reset digital sequence 3412 */ 3413#ifndef URTWN_WITHOUT_UCODE 3414 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3415 /* Reset MCU ready status */ 3416 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3417 3418 /* If firmware in ram code, do reset */ 3419 urtwn_fw_reset(sc); 3420 } 3421#endif 3422 3423 /* Reset MAC and Enable 8051 */ 3424 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 3425 (R92C_SYS_FUNC_EN_CPUEN | 3426 R92C_SYS_FUNC_EN_ELDR | 3427 R92C_SYS_FUNC_EN_HWPDN) >> 8); 3428 3429 /* Reset MCU ready status */ 3430 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3431 3432 /* Disable MAC clock */ 3433 urtwn_write_2(sc, R92C_SYS_CLKR, 3434 R92C_SYS_CLKR_ANAD16V_EN | 3435 R92C_SYS_CLKR_ANA8M | 3436 R92C_SYS_CLKR_LOADER_EN | 3437 R92C_SYS_CLKR_80M_SSC_DIS | 3438 R92C_SYS_CLKR_SYS_EN | 3439 R92C_SYS_CLKR_RING_EN | 3440 0x4000); 3441 3442 /* Disable AFE PLL */ 3443 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3444 3445 /* Gated AFE DIG_CLOCK */ 3446 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3447 3448 /* Isolated digital to PON */ 3449 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3450 R92C_SYS_ISO_CTRL_MD2PP | 3451 R92C_SYS_ISO_CTRL_PA2PCIE | 3452 R92C_SYS_ISO_CTRL_PD2CORE | 3453 R92C_SYS_ISO_CTRL_IP2MAC | 3454 R92C_SYS_ISO_CTRL_DIOP | 3455 R92C_SYS_ISO_CTRL_DIOE); 3456 3457 /* 3458 * Pull GPIO PIN to balance level and LED control 3459 */ 3460 /* 1. Disable GPIO[7:0] */ 3461 urtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000); 3462 3463 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3464 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3465 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3466 3467 /* Disable GPIO[10:8] */ 3468 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x00); 3469 3470 reg = urtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0; 3471 reg |= (((reg & 0x000f) << 4) | 0x0780); 3472 urtwn_write_2(sc, R92C_GPIO_IO_SEL, reg); 3473 3474 /* Disable LED0 & 1 */ 3475 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3476 3477 /* 3478 * Reset digital sequence 3479 */ 3480 /* Disable ELDR clock */ 3481 urtwn_write_2(sc, R92C_SYS_CLKR, 3482 R92C_SYS_CLKR_ANAD16V_EN | 3483 R92C_SYS_CLKR_ANA8M | 3484 R92C_SYS_CLKR_LOADER_EN | 3485 R92C_SYS_CLKR_80M_SSC_DIS | 3486 R92C_SYS_CLKR_SYS_EN | 3487 R92C_SYS_CLKR_RING_EN | 3488 0x4000); 3489 3490 /* Isolated ELDR to PON */ 3491 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 3492 (R92C_SYS_ISO_CTRL_DIOR | 3493 R92C_SYS_ISO_CTRL_PWC_EV12V) >> 8); 3494 3495 /* 3496 * Disable analog sequence 3497 */ 3498 /* Disable A15 power */ 3499 urtwn_write_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_OBUF); 3500 /* Disable digital core power */ 3501 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3502 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3503 ~R92C_LDOV12D_CTRL_LDV12_EN); 3504 3505 /* Enter PFM mode */ 3506 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3507 3508 /* Set USB suspend */ 3509 urtwn_write_2(sc, R92C_APS_FSMCO, 3510 R92C_APS_FSMCO_APDM_HOST | 3511 R92C_APS_FSMCO_AFSM_HSUS | 3512 R92C_APS_FSMCO_PFM_ALDN); 3513 3514 /* Lock ISO/CLK/Power control register. */ 3515 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 3516} 3517 3518static void 3519urtwn_r88e_power_off(struct urtwn_softc *sc) 3520{ 3521 uint8_t reg; 3522 int ntries; 3523 3524 /* Disable any kind of TX reports. */ 3525 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 3526 urtwn_read_1(sc, R88E_TX_RPT_CTRL) & 3527 ~(R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA)); 3528 3529 /* Stop Rx. */ 3530 urtwn_write_1(sc, R92C_CR, 0); 3531 3532 /* Move card to Low Power State. */ 3533 /* Block all Tx queues. */ 3534 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3535 3536 for (ntries = 0; ntries < 20; ntries++) { 3537 /* Should be zero if no packet is transmitting. */ 3538 if (urtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 3539 break; 3540 3541 urtwn_ms_delay(sc); 3542 } 3543 if (ntries == 20) { 3544 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 3545 __func__); 3546 return; 3547 } 3548 3549 /* CCK and OFDM are disabled, and clock are gated. */ 3550 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3551 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_BBRSTB); 3552 3553 urtwn_ms_delay(sc); 3554 3555 /* Reset MAC TRX */ 3556 urtwn_write_1(sc, R92C_CR, 3557 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3558 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | 3559 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN); 3560 3561 /* check if removed later */ 3562 urtwn_write_1(sc, R92C_CR + 1, 3563 urtwn_read_1(sc, R92C_CR + 1) & ~(R92C_CR_ENSEC >> 8)); 3564 3565 /* Respond TxOK to scheduler */ 3566 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 3567 urtwn_read_1(sc, R92C_DUAL_TSF_RST) | 0x20); 3568 3569 /* If firmware in ram code, do reset. */ 3570#ifndef URTWN_WITHOUT_UCODE 3571 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) 3572 urtwn_r88e_fw_reset(sc); 3573#endif 3574 3575 /* Reset MCU ready status. */ 3576 urtwn_write_1(sc, R92C_MCUFWDL, 0x00); 3577 3578 /* Disable 32k. */ 3579 urtwn_write_1(sc, R88E_32K_CTRL, 3580 urtwn_read_1(sc, R88E_32K_CTRL) & ~0x01); 3581 3582 /* Move card to Disabled state. */ 3583 /* Turn off RF. */ 3584 urtwn_write_1(sc, R92C_RF_CTRL, 0); 3585 3586 /* LDO Sleep mode. */ 3587 urtwn_write_1(sc, R92C_LPLDO_CTRL, 3588 urtwn_read_1(sc, R92C_LPLDO_CTRL) | R92C_LPLDO_CTRL_SLEEP); 3589 3590 /* Turn off MAC by HW state machine */ 3591 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3592 urtwn_read_1(sc, R92C_APS_FSMCO + 1) | 3593 (R92C_APS_FSMCO_APFM_OFF >> 8)); 3594 3595 for (ntries = 0; ntries < 20; ntries++) { 3596 /* Wait until it will be disabled. */ 3597 if ((urtwn_read_1(sc, R92C_APS_FSMCO + 1) & 3598 (R92C_APS_FSMCO_APFM_OFF >> 8)) == 0) 3599 break; 3600 3601 urtwn_ms_delay(sc); 3602 } 3603 if (ntries == 20) { 3604 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 3605 __func__); 3606 return; 3607 } 3608 3609 /* schmit trigger */ 3610 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3611 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3612 3613 /* Enable WL suspend. */ 3614 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3615 (urtwn_read_1(sc, R92C_APS_FSMCO + 1) & ~0x10) | 0x08); 3616 3617 /* Enable bandgap mbias in suspend. */ 3618 urtwn_write_1(sc, R92C_APS_FSMCO + 3, 0); 3619 3620 /* Clear SIC_EN register. */ 3621 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 1, 3622 urtwn_read_1(sc, R92C_GPIO_MUXCFG + 1) & ~0x10); 3623 3624 /* Set USB suspend enable local register */ 3625 urtwn_write_1(sc, R92C_USB_SUSPEND, 3626 urtwn_read_1(sc, R92C_USB_SUSPEND) | 0x10); 3627 3628 /* Reset MCU IO Wrapper. */ 3629 reg = urtwn_read_1(sc, R92C_RSV_CTRL + 1); 3630 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08); 3631 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08); 3632 3633 /* marked as 'For Power Consumption' code. */ 3634 urtwn_write_1(sc, R92C_GPIO_OUT, urtwn_read_1(sc, R92C_GPIO_IN)); 3635 urtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff); 3636 3637 urtwn_write_1(sc, R92C_GPIO_IO_SEL, 3638 urtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4); 3639 urtwn_write_1(sc, R92C_GPIO_MOD, 3640 urtwn_read_1(sc, R92C_GPIO_MOD) | 0x0f); 3641 3642 /* Set LNA, TRSW, EX_PA Pin to output mode. */ 3643 urtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808); 3644} 3645 3646static int 3647urtwn_llt_init(struct urtwn_softc *sc) 3648{ 3649 int i, error, page_count, pktbuf_count; 3650 3651 page_count = (sc->chip & URTWN_CHIP_88E) ? 3652 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 3653 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 3654 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 3655 3656 /* Reserve pages [0; page_count]. */ 3657 for (i = 0; i < page_count; i++) { 3658 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3659 return (error); 3660 } 3661 /* NB: 0xff indicates end-of-list. */ 3662 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3663 return (error); 3664 /* 3665 * Use pages [page_count + 1; pktbuf_count - 1] 3666 * as ring buffer. 3667 */ 3668 for (++i; i < pktbuf_count - 1; i++) { 3669 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3670 return (error); 3671 } 3672 /* Make the last page point to the beginning of the ring buffer. */ 3673 error = urtwn_llt_write(sc, i, page_count + 1); 3674 return (error); 3675} 3676 3677#ifndef URTWN_WITHOUT_UCODE 3678static void 3679urtwn_fw_reset(struct urtwn_softc *sc) 3680{ 3681 uint16_t reg; 3682 int ntries; 3683 3684 /* Tell 8051 to reset itself. */ 3685 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3686 3687 /* Wait until 8051 resets by itself. */ 3688 for (ntries = 0; ntries < 100; ntries++) { 3689 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3690 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3691 return; 3692 urtwn_ms_delay(sc); 3693 } 3694 /* Force 8051 reset. */ 3695 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3696} 3697 3698static void 3699urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3700{ 3701 uint16_t reg; 3702 3703 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3704 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3705 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3706} 3707 3708static int 3709urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 3710{ 3711 uint32_t reg; 3712 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 3713 int off, mlen; 3714 3715 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3716 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3717 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3718 3719 off = R92C_FW_START_ADDR; 3720 while (len > 0) { 3721 if (len > 196) 3722 mlen = 196; 3723 else if (len > 4) 3724 mlen = 4; 3725 else 3726 mlen = 1; 3727 /* XXX fix this deconst */ 3728 error = urtwn_write_region_1(sc, off, 3729 __DECONST(uint8_t *, buf), mlen); 3730 if (error != USB_ERR_NORMAL_COMPLETION) 3731 break; 3732 off += mlen; 3733 buf += mlen; 3734 len -= mlen; 3735 } 3736 return (error); 3737} 3738 3739static int 3740urtwn_load_firmware(struct urtwn_softc *sc) 3741{ 3742 const struct firmware *fw; 3743 const struct r92c_fw_hdr *hdr; 3744 const char *imagename; 3745 const u_char *ptr; 3746 size_t len; 3747 uint32_t reg; 3748 int mlen, ntries, page, error; 3749 3750 URTWN_UNLOCK(sc); 3751 /* Read firmware image from the filesystem. */ 3752 if (sc->chip & URTWN_CHIP_88E) 3753 imagename = "urtwn-rtl8188eufw"; 3754 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3755 URTWN_CHIP_UMC_A_CUT) 3756 imagename = "urtwn-rtl8192cfwU"; 3757 else 3758 imagename = "urtwn-rtl8192cfwT"; 3759 3760 fw = firmware_get(imagename); 3761 URTWN_LOCK(sc); 3762 if (fw == NULL) { 3763 device_printf(sc->sc_dev, 3764 "failed loadfirmware of file %s\n", imagename); 3765 return (ENOENT); 3766 } 3767 3768 len = fw->datasize; 3769 3770 if (len < sizeof(*hdr)) { 3771 device_printf(sc->sc_dev, "firmware too short\n"); 3772 error = EINVAL; 3773 goto fail; 3774 } 3775 ptr = fw->data; 3776 hdr = (const struct r92c_fw_hdr *)ptr; 3777 /* Check if there is a valid FW header and skip it. */ 3778 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3779 (le16toh(hdr->signature) >> 4) == 0x88e || 3780 (le16toh(hdr->signature) >> 4) == 0x92c) { 3781 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, 3782 "FW V%d.%d %02d-%02d %02d:%02d\n", 3783 le16toh(hdr->version), le16toh(hdr->subversion), 3784 hdr->month, hdr->date, hdr->hour, hdr->minute); 3785 ptr += sizeof(*hdr); 3786 len -= sizeof(*hdr); 3787 } 3788 3789 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3790 if (sc->chip & URTWN_CHIP_88E) 3791 urtwn_r88e_fw_reset(sc); 3792 else 3793 urtwn_fw_reset(sc); 3794 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3795 } 3796 3797 if (!(sc->chip & URTWN_CHIP_88E)) { 3798 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3799 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3800 R92C_SYS_FUNC_EN_CPUEN); 3801 } 3802 urtwn_write_1(sc, R92C_MCUFWDL, 3803 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3804 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3805 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3806 3807 /* Reset the FWDL checksum. */ 3808 urtwn_write_1(sc, R92C_MCUFWDL, 3809 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3810 3811 for (page = 0; len > 0; page++) { 3812 mlen = min(len, R92C_FW_PAGE_SIZE); 3813 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3814 if (error != 0) { 3815 device_printf(sc->sc_dev, 3816 "could not load firmware page\n"); 3817 goto fail; 3818 } 3819 ptr += mlen; 3820 len -= mlen; 3821 } 3822 urtwn_write_1(sc, R92C_MCUFWDL, 3823 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3824 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3825 3826 /* Wait for checksum report. */ 3827 for (ntries = 0; ntries < 1000; ntries++) { 3828 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3829 break; 3830 urtwn_ms_delay(sc); 3831 } 3832 if (ntries == 1000) { 3833 device_printf(sc->sc_dev, 3834 "timeout waiting for checksum report\n"); 3835 error = ETIMEDOUT; 3836 goto fail; 3837 } 3838 3839 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3840 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3841 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3842 if (sc->chip & URTWN_CHIP_88E) 3843 urtwn_r88e_fw_reset(sc); 3844 /* Wait for firmware readiness. */ 3845 for (ntries = 0; ntries < 1000; ntries++) { 3846 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3847 break; 3848 urtwn_ms_delay(sc); 3849 } 3850 if (ntries == 1000) { 3851 device_printf(sc->sc_dev, 3852 "timeout waiting for firmware readiness\n"); 3853 error = ETIMEDOUT; 3854 goto fail; 3855 } 3856fail: 3857 firmware_put(fw, FIRMWARE_UNLOAD); 3858 return (error); 3859} 3860#endif 3861 3862static int 3863urtwn_dma_init(struct urtwn_softc *sc) 3864{ 3865 struct usb_endpoint *ep, *ep_end; 3866 usb_error_t usb_err; 3867 uint32_t reg; 3868 int hashq, hasnq, haslq, nqueues, ntx; 3869 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 3870 3871 /* Initialize LLT table. */ 3872 error = urtwn_llt_init(sc); 3873 if (error != 0) 3874 return (error); 3875 3876 /* Determine the number of bulk-out pipes. */ 3877 ntx = 0; 3878 ep = sc->sc_udev->endpoints; 3879 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 3880 for (; ep != ep_end; ep++) { 3881 if ((ep->edesc == NULL) || 3882 (ep->iface_index != sc->sc_iface_index)) 3883 continue; 3884 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 3885 ntx++; 3886 } 3887 if (ntx == 0) { 3888 device_printf(sc->sc_dev, 3889 "%d: invalid number of Tx bulk pipes\n", ntx); 3890 return (EIO); 3891 } 3892 3893 /* Get Tx queues to USB endpoints mapping. */ 3894 hashq = hasnq = haslq = nqueues = 0; 3895 switch (ntx) { 3896 case 1: hashq = 1; break; 3897 case 2: hashq = hasnq = 1; break; 3898 case 3: case 4: hashq = hasnq = haslq = 1; break; 3899 } 3900 nqueues = hashq + hasnq + haslq; 3901 if (nqueues == 0) 3902 return (EIO); 3903 3904 npubqpages = nqpages = nrempages = pagecount = 0; 3905 if (sc->chip & URTWN_CHIP_88E) 3906 tx_boundary = R88E_TX_PAGE_BOUNDARY; 3907 else { 3908 pagecount = R92C_TX_PAGE_COUNT; 3909 npubqpages = R92C_PUBQ_NPAGES; 3910 tx_boundary = R92C_TX_PAGE_BOUNDARY; 3911 } 3912 3913 /* Set number of pages for normal priority queue. */ 3914 if (sc->chip & URTWN_CHIP_88E) { 3915 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 3916 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3917 return (EIO); 3918 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3919 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3920 return (EIO); 3921 } else { 3922 /* Get the number of pages for each queue. */ 3923 nqpages = (pagecount - npubqpages) / nqueues; 3924 /* 3925 * The remaining pages are assigned to the high priority 3926 * queue. 3927 */ 3928 nrempages = (pagecount - npubqpages) % nqueues; 3929 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3930 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3931 return (EIO); 3932 usb_err = urtwn_write_4(sc, R92C_RQPN, 3933 /* Set number of pages for public queue. */ 3934 SM(R92C_RQPN_PUBQ, npubqpages) | 3935 /* Set number of pages for high priority queue. */ 3936 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3937 /* Set number of pages for low priority queue. */ 3938 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3939 /* Load values. */ 3940 R92C_RQPN_LD); 3941 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3942 return (EIO); 3943 } 3944 3945 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 3946 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3947 return (EIO); 3948 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 3949 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3950 return (EIO); 3951 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 3952 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3953 return (EIO); 3954 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 3955 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3956 return (EIO); 3957 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 3958 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3959 return (EIO); 3960 3961 /* Set queue to USB pipe mapping. */ 3962 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3963 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3964 if (nqueues == 1) { 3965 if (hashq) 3966 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3967 else if (hasnq) 3968 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3969 else 3970 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3971 } else if (nqueues == 2) { 3972 /* 3973 * All 2-endpoints configs have high and normal 3974 * priority queues. 3975 */ 3976 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3977 } else 3978 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3979 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3980 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3981 return (EIO); 3982 3983 /* Set Tx/Rx transfer page boundary. */ 3984 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 3985 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 3986 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3987 return (EIO); 3988 3989 /* Set Tx/Rx transfer page size. */ 3990 usb_err = urtwn_write_1(sc, R92C_PBP, 3991 SM(R92C_PBP_PSRX, R92C_PBP_128) | 3992 SM(R92C_PBP_PSTX, R92C_PBP_128)); 3993 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3994 return (EIO); 3995 3996 return (0); 3997} 3998 3999static int 4000urtwn_mac_init(struct urtwn_softc *sc) 4001{ 4002 usb_error_t error; 4003 int i; 4004 4005 /* Write MAC initialization values. */ 4006 if (sc->chip & URTWN_CHIP_88E) { 4007 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 4008 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 4009 rtl8188eu_mac[i].val); 4010 if (error != USB_ERR_NORMAL_COMPLETION) 4011 return (EIO); 4012 } 4013 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 4014 } else { 4015 for (i = 0; i < nitems(rtl8192cu_mac); i++) 4016 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 4017 rtl8192cu_mac[i].val); 4018 if (error != USB_ERR_NORMAL_COMPLETION) 4019 return (EIO); 4020 } 4021 4022 return (0); 4023} 4024 4025static void 4026urtwn_bb_init(struct urtwn_softc *sc) 4027{ 4028 const struct urtwn_bb_prog *prog; 4029 uint32_t reg; 4030 uint8_t crystalcap; 4031 int i; 4032 4033 /* Enable BB and RF. */ 4034 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4035 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4036 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 4037 R92C_SYS_FUNC_EN_DIO_RF); 4038 4039 if (!(sc->chip & URTWN_CHIP_88E)) 4040 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 4041 4042 urtwn_write_1(sc, R92C_RF_CTRL, 4043 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 4044 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4045 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 4046 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 4047 4048 if (!(sc->chip & URTWN_CHIP_88E)) { 4049 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 4050 urtwn_write_1(sc, 0x15, 0xe9); 4051 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 4052 } 4053 4054 /* Select BB programming based on board type. */ 4055 if (sc->chip & URTWN_CHIP_88E) 4056 prog = &rtl8188eu_bb_prog; 4057 else if (!(sc->chip & URTWN_CHIP_92C)) { 4058 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4059 prog = &rtl8188ce_bb_prog; 4060 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4061 prog = &rtl8188ru_bb_prog; 4062 else 4063 prog = &rtl8188cu_bb_prog; 4064 } else { 4065 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4066 prog = &rtl8192ce_bb_prog; 4067 else 4068 prog = &rtl8192cu_bb_prog; 4069 } 4070 /* Write BB initialization values. */ 4071 for (i = 0; i < prog->count; i++) { 4072 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 4073 urtwn_ms_delay(sc); 4074 } 4075 4076 if (sc->chip & URTWN_CHIP_92C_1T2R) { 4077 /* 8192C 1T only configuration. */ 4078 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 4079 reg = (reg & ~0x00000003) | 0x2; 4080 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 4081 4082 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 4083 reg = (reg & ~0x00300033) | 0x00200022; 4084 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 4085 4086 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 4087 reg = (reg & ~0xff000000) | 0x45 << 24; 4088 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 4089 4090 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4091 reg = (reg & ~0x000000ff) | 0x23; 4092 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 4093 4094 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 4095 reg = (reg & ~0x00000030) | 1 << 4; 4096 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 4097 4098 reg = urtwn_bb_read(sc, 0xe74); 4099 reg = (reg & ~0x0c000000) | 2 << 26; 4100 urtwn_bb_write(sc, 0xe74, reg); 4101 reg = urtwn_bb_read(sc, 0xe78); 4102 reg = (reg & ~0x0c000000) | 2 << 26; 4103 urtwn_bb_write(sc, 0xe78, reg); 4104 reg = urtwn_bb_read(sc, 0xe7c); 4105 reg = (reg & ~0x0c000000) | 2 << 26; 4106 urtwn_bb_write(sc, 0xe7c, reg); 4107 reg = urtwn_bb_read(sc, 0xe80); 4108 reg = (reg & ~0x0c000000) | 2 << 26; 4109 urtwn_bb_write(sc, 0xe80, reg); 4110 reg = urtwn_bb_read(sc, 0xe88); 4111 reg = (reg & ~0x0c000000) | 2 << 26; 4112 urtwn_bb_write(sc, 0xe88, reg); 4113 } 4114 4115 /* Write AGC values. */ 4116 for (i = 0; i < prog->agccount; i++) { 4117 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 4118 prog->agcvals[i]); 4119 urtwn_ms_delay(sc); 4120 } 4121 4122 if (sc->chip & URTWN_CHIP_88E) { 4123 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4124 urtwn_ms_delay(sc); 4125 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4126 urtwn_ms_delay(sc); 4127 4128 crystalcap = sc->rom.r88e_rom.crystalcap; 4129 if (crystalcap == 0xff) 4130 crystalcap = 0x20; 4131 crystalcap &= 0x3f; 4132 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4133 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4134 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4135 crystalcap | crystalcap << 6)); 4136 } else { 4137 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4138 R92C_HSSI_PARAM2_CCK_HIPWR) 4139 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 4140 } 4141} 4142 4143static void 4144urtwn_rf_init(struct urtwn_softc *sc) 4145{ 4146 const struct urtwn_rf_prog *prog; 4147 uint32_t reg, type; 4148 int i, j, idx, off; 4149 4150 /* Select RF programming based on board type. */ 4151 if (sc->chip & URTWN_CHIP_88E) 4152 prog = rtl8188eu_rf_prog; 4153 else if (!(sc->chip & URTWN_CHIP_92C)) { 4154 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4155 prog = rtl8188ce_rf_prog; 4156 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4157 prog = rtl8188ru_rf_prog; 4158 else 4159 prog = rtl8188cu_rf_prog; 4160 } else 4161 prog = rtl8192ce_rf_prog; 4162 4163 for (i = 0; i < sc->nrxchains; i++) { 4164 /* Save RF_ENV control type. */ 4165 idx = i / 2; 4166 off = (i % 2) * 16; 4167 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4168 type = (reg >> off) & 0x10; 4169 4170 /* Set RF_ENV enable. */ 4171 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4172 reg |= 0x100000; 4173 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4174 urtwn_ms_delay(sc); 4175 /* Set RF_ENV output high. */ 4176 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4177 reg |= 0x10; 4178 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4179 urtwn_ms_delay(sc); 4180 /* Set address and data lengths of RF registers. */ 4181 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4182 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4183 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4184 urtwn_ms_delay(sc); 4185 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4186 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4187 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4188 urtwn_ms_delay(sc); 4189 4190 /* Write RF initialization values for this chain. */ 4191 for (j = 0; j < prog[i].count; j++) { 4192 if (prog[i].regs[j] >= 0xf9 && 4193 prog[i].regs[j] <= 0xfe) { 4194 /* 4195 * These are fake RF registers offsets that 4196 * indicate a delay is required. 4197 */ 4198 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 4199 continue; 4200 } 4201 urtwn_rf_write(sc, i, prog[i].regs[j], 4202 prog[i].vals[j]); 4203 urtwn_ms_delay(sc); 4204 } 4205 4206 /* Restore RF_ENV control type. */ 4207 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4208 reg &= ~(0x10 << off) | (type << off); 4209 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 4210 4211 /* Cache RF register CHNLBW. */ 4212 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4213 } 4214 4215 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4216 URTWN_CHIP_UMC_A_CUT) { 4217 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4218 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4219 } 4220} 4221 4222static void 4223urtwn_cam_init(struct urtwn_softc *sc) 4224{ 4225 /* Invalidate all CAM entries. */ 4226 urtwn_write_4(sc, R92C_CAMCMD, 4227 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4228} 4229 4230static int 4231urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 4232{ 4233 usb_error_t error; 4234 4235 error = urtwn_write_4(sc, R92C_CAMWRITE, data); 4236 if (error != USB_ERR_NORMAL_COMPLETION) 4237 return (EIO); 4238 error = urtwn_write_4(sc, R92C_CAMCMD, 4239 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 4240 SM(R92C_CAMCMD_ADDR, addr)); 4241 if (error != USB_ERR_NORMAL_COMPLETION) 4242 return (EIO); 4243 4244 return (0); 4245} 4246 4247static void 4248urtwn_pa_bias_init(struct urtwn_softc *sc) 4249{ 4250 uint8_t reg; 4251 int i; 4252 4253 for (i = 0; i < sc->nrxchains; i++) { 4254 if (sc->pa_setting & (1 << i)) 4255 continue; 4256 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4257 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4258 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4259 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4260 } 4261 if (!(sc->pa_setting & 0x10)) { 4262 reg = urtwn_read_1(sc, 0x16); 4263 reg = (reg & ~0xf0) | 0x90; 4264 urtwn_write_1(sc, 0x16, reg); 4265 } 4266} 4267 4268static void 4269urtwn_rxfilter_init(struct urtwn_softc *sc) 4270{ 4271 struct ieee80211com *ic = &sc->sc_ic; 4272 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4273 uint32_t rcr; 4274 uint16_t filter; 4275 4276 URTWN_ASSERT_LOCKED(sc); 4277 4278 /* Accept all multicast frames. */ 4279 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4280 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4281 4282 /* Filter for management frames. */ 4283 filter = 0x7f3f; 4284 switch (vap->iv_opmode) { 4285 case IEEE80211_M_STA: 4286 filter &= ~( 4287 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 4288 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 4289 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 4290 break; 4291 case IEEE80211_M_HOSTAP: 4292 filter &= ~( 4293 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 4294 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP)); 4295 break; 4296 case IEEE80211_M_MONITOR: 4297 case IEEE80211_M_IBSS: 4298 break; 4299 default: 4300 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4301 __func__, vap->iv_opmode); 4302 break; 4303 } 4304 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 4305 4306 /* Reject all control frames. */ 4307 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4308 4309 /* Reject all data frames. */ 4310 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 4311 4312 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 4313 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 4314 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 4315 4316 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 4317 /* Accept all frames. */ 4318 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 4319 R92C_RCR_AAP; 4320 } 4321 4322 /* Set Rx filter. */ 4323 urtwn_write_4(sc, R92C_RCR, rcr); 4324 4325 if (ic->ic_promisc != 0) { 4326 /* Update Rx filter. */ 4327 urtwn_set_promisc(sc); 4328 } 4329} 4330 4331static void 4332urtwn_edca_init(struct urtwn_softc *sc) 4333{ 4334 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4335 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4336 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4337 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4338 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4339 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4340 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4341 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4342} 4343 4344static void 4345urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4346 uint16_t power[URTWN_RIDX_COUNT]) 4347{ 4348 uint32_t reg; 4349 4350 /* Write per-CCK rate Tx power. */ 4351 if (chain == 0) { 4352 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4353 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4354 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4355 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4356 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4357 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4358 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4359 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4360 } else { 4361 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4362 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4363 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4364 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4365 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4366 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4367 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4368 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4369 } 4370 /* Write per-OFDM rate Tx power. */ 4371 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4372 SM(R92C_TXAGC_RATE06, power[ 4]) | 4373 SM(R92C_TXAGC_RATE09, power[ 5]) | 4374 SM(R92C_TXAGC_RATE12, power[ 6]) | 4375 SM(R92C_TXAGC_RATE18, power[ 7])); 4376 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4377 SM(R92C_TXAGC_RATE24, power[ 8]) | 4378 SM(R92C_TXAGC_RATE36, power[ 9]) | 4379 SM(R92C_TXAGC_RATE48, power[10]) | 4380 SM(R92C_TXAGC_RATE54, power[11])); 4381 /* Write per-MCS Tx power. */ 4382 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4383 SM(R92C_TXAGC_MCS00, power[12]) | 4384 SM(R92C_TXAGC_MCS01, power[13]) | 4385 SM(R92C_TXAGC_MCS02, power[14]) | 4386 SM(R92C_TXAGC_MCS03, power[15])); 4387 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4388 SM(R92C_TXAGC_MCS04, power[16]) | 4389 SM(R92C_TXAGC_MCS05, power[17]) | 4390 SM(R92C_TXAGC_MCS06, power[18]) | 4391 SM(R92C_TXAGC_MCS07, power[19])); 4392 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4393 SM(R92C_TXAGC_MCS08, power[20]) | 4394 SM(R92C_TXAGC_MCS09, power[21]) | 4395 SM(R92C_TXAGC_MCS10, power[22]) | 4396 SM(R92C_TXAGC_MCS11, power[23])); 4397 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4398 SM(R92C_TXAGC_MCS12, power[24]) | 4399 SM(R92C_TXAGC_MCS13, power[25]) | 4400 SM(R92C_TXAGC_MCS14, power[26]) | 4401 SM(R92C_TXAGC_MCS15, power[27])); 4402} 4403 4404static void 4405urtwn_get_txpower(struct urtwn_softc *sc, int chain, 4406 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4407 uint16_t power[URTWN_RIDX_COUNT]) 4408{ 4409 struct ieee80211com *ic = &sc->sc_ic; 4410 struct r92c_rom *rom = &sc->rom.r92c_rom; 4411 uint16_t cckpow, ofdmpow, htpow, diff, max; 4412 const struct urtwn_txpwr *base; 4413 int ridx, chan, group; 4414 4415 /* Determine channel group. */ 4416 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4417 if (chan <= 3) 4418 group = 0; 4419 else if (chan <= 9) 4420 group = 1; 4421 else 4422 group = 2; 4423 4424 /* Get original Tx power based on board type and RF chain. */ 4425 if (!(sc->chip & URTWN_CHIP_92C)) { 4426 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4427 base = &rtl8188ru_txagc[chain]; 4428 else 4429 base = &rtl8192cu_txagc[chain]; 4430 } else 4431 base = &rtl8192cu_txagc[chain]; 4432 4433 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4434 if (sc->regulatory == 0) { 4435 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4436 power[ridx] = base->pwr[0][ridx]; 4437 } 4438 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4439 if (sc->regulatory == 3) { 4440 power[ridx] = base->pwr[0][ridx]; 4441 /* Apply vendor limits. */ 4442 if (extc != NULL) 4443 max = rom->ht40_max_pwr[group]; 4444 else 4445 max = rom->ht20_max_pwr[group]; 4446 max = (max >> (chain * 4)) & 0xf; 4447 if (power[ridx] > max) 4448 power[ridx] = max; 4449 } else if (sc->regulatory == 1) { 4450 if (extc == NULL) 4451 power[ridx] = base->pwr[group][ridx]; 4452 } else if (sc->regulatory != 2) 4453 power[ridx] = base->pwr[0][ridx]; 4454 } 4455 4456 /* Compute per-CCK rate Tx power. */ 4457 cckpow = rom->cck_tx_pwr[chain][group]; 4458 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4459 power[ridx] += cckpow; 4460 if (power[ridx] > R92C_MAX_TX_PWR) 4461 power[ridx] = R92C_MAX_TX_PWR; 4462 } 4463 4464 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4465 if (sc->ntxchains > 1) { 4466 /* Apply reduction for 2 spatial streams. */ 4467 diff = rom->ht40_2s_tx_pwr_diff[group]; 4468 diff = (diff >> (chain * 4)) & 0xf; 4469 htpow = (htpow > diff) ? htpow - diff : 0; 4470 } 4471 4472 /* Compute per-OFDM rate Tx power. */ 4473 diff = rom->ofdm_tx_pwr_diff[group]; 4474 diff = (diff >> (chain * 4)) & 0xf; 4475 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4476 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4477 power[ridx] += ofdmpow; 4478 if (power[ridx] > R92C_MAX_TX_PWR) 4479 power[ridx] = R92C_MAX_TX_PWR; 4480 } 4481 4482 /* Compute per-MCS Tx power. */ 4483 if (extc == NULL) { 4484 diff = rom->ht20_tx_pwr_diff[group]; 4485 diff = (diff >> (chain * 4)) & 0xf; 4486 htpow += diff; /* HT40->HT20 correction. */ 4487 } 4488 for (ridx = 12; ridx <= 27; ridx++) { 4489 power[ridx] += htpow; 4490 if (power[ridx] > R92C_MAX_TX_PWR) 4491 power[ridx] = R92C_MAX_TX_PWR; 4492 } 4493#ifdef USB_DEBUG 4494 if (sc->sc_debug & URTWN_DEBUG_TXPWR) { 4495 /* Dump per-rate Tx power values. */ 4496 printf("Tx power for chain %d:\n", chain); 4497 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 4498 printf("Rate %d = %u\n", ridx, power[ridx]); 4499 } 4500#endif 4501} 4502 4503static void 4504urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 4505 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4506 uint16_t power[URTWN_RIDX_COUNT]) 4507{ 4508 struct ieee80211com *ic = &sc->sc_ic; 4509 struct r88e_rom *rom = &sc->rom.r88e_rom; 4510 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4511 const struct urtwn_r88e_txpwr *base; 4512 int ridx, chan, group; 4513 4514 /* Determine channel group. */ 4515 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4516 if (chan <= 2) 4517 group = 0; 4518 else if (chan <= 5) 4519 group = 1; 4520 else if (chan <= 8) 4521 group = 2; 4522 else if (chan <= 11) 4523 group = 3; 4524 else if (chan <= 13) 4525 group = 4; 4526 else 4527 group = 5; 4528 4529 /* Get original Tx power based on board type and RF chain. */ 4530 base = &rtl8188eu_txagc[chain]; 4531 4532 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4533 if (sc->regulatory == 0) { 4534 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4535 power[ridx] = base->pwr[0][ridx]; 4536 } 4537 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4538 if (sc->regulatory == 3) 4539 power[ridx] = base->pwr[0][ridx]; 4540 else if (sc->regulatory == 1) { 4541 if (extc == NULL) 4542 power[ridx] = base->pwr[group][ridx]; 4543 } else if (sc->regulatory != 2) 4544 power[ridx] = base->pwr[0][ridx]; 4545 } 4546 4547 /* Compute per-CCK rate Tx power. */ 4548 cckpow = rom->cck_tx_pwr[group]; 4549 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4550 power[ridx] += cckpow; 4551 if (power[ridx] > R92C_MAX_TX_PWR) 4552 power[ridx] = R92C_MAX_TX_PWR; 4553 } 4554 4555 htpow = rom->ht40_tx_pwr[group]; 4556 4557 /* Compute per-OFDM rate Tx power. */ 4558 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4559 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4560 power[ridx] += ofdmpow; 4561 if (power[ridx] > R92C_MAX_TX_PWR) 4562 power[ridx] = R92C_MAX_TX_PWR; 4563 } 4564 4565 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4566 for (ridx = 12; ridx <= 27; ridx++) { 4567 power[ridx] += bw20pow; 4568 if (power[ridx] > R92C_MAX_TX_PWR) 4569 power[ridx] = R92C_MAX_TX_PWR; 4570 } 4571} 4572 4573static void 4574urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 4575 struct ieee80211_channel *extc) 4576{ 4577 uint16_t power[URTWN_RIDX_COUNT]; 4578 int i; 4579 4580 for (i = 0; i < sc->ntxchains; i++) { 4581 /* Compute per-rate Tx power values. */ 4582 if (sc->chip & URTWN_CHIP_88E) 4583 urtwn_r88e_get_txpower(sc, i, c, extc, power); 4584 else 4585 urtwn_get_txpower(sc, i, c, extc, power); 4586 /* Write per-rate Tx power values to hardware. */ 4587 urtwn_write_txpower(sc, i, power); 4588 } 4589} 4590 4591static void 4592urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 4593{ 4594 uint32_t reg; 4595 4596 reg = urtwn_read_4(sc, R92C_RCR); 4597 if (enable) 4598 reg &= ~R92C_RCR_CBSSID_BCN; 4599 else 4600 reg |= R92C_RCR_CBSSID_BCN; 4601 urtwn_write_4(sc, R92C_RCR, reg); 4602} 4603 4604static void 4605urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 4606{ 4607 uint32_t reg; 4608 4609 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 4610 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4611 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 4612 4613 if (!(sc->chip & URTWN_CHIP_88E)) { 4614 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 4615 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4616 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 4617 } 4618} 4619 4620static void 4621urtwn_scan_start(struct ieee80211com *ic) 4622{ 4623 struct urtwn_softc *sc = ic->ic_softc; 4624 4625 URTWN_LOCK(sc); 4626 /* Receive beacons / probe responses from any BSSID. */ 4627 if (ic->ic_opmode != IEEE80211_M_IBSS) 4628 urtwn_set_rx_bssid_all(sc, 1); 4629 4630 /* Set gain for scanning. */ 4631 urtwn_set_gain(sc, 0x20); 4632 URTWN_UNLOCK(sc); 4633} 4634 4635static void 4636urtwn_scan_end(struct ieee80211com *ic) 4637{ 4638 struct urtwn_softc *sc = ic->ic_softc; 4639 4640 URTWN_LOCK(sc); 4641 /* Restore limitations. */ 4642 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 4643 urtwn_set_rx_bssid_all(sc, 0); 4644 4645 /* Set gain under link. */ 4646 urtwn_set_gain(sc, 0x32); 4647 URTWN_UNLOCK(sc); 4648} 4649 4650static void 4651urtwn_set_channel(struct ieee80211com *ic) 4652{ 4653 struct urtwn_softc *sc = ic->ic_softc; 4654 struct ieee80211_channel *c = ic->ic_curchan; 4655 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4656 4657 URTWN_LOCK(sc); 4658 if (vap->iv_state == IEEE80211_S_SCAN) { 4659 /* Make link LED blink during scan. */ 4660 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 4661 } 4662 urtwn_set_chan(sc, c, NULL); 4663 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 4664 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 4665 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 4666 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 4667 URTWN_UNLOCK(sc); 4668} 4669 4670static int 4671urtwn_wme_update(struct ieee80211com *ic) 4672{ 4673 const struct wmeParams *wmep = 4674 ic->ic_wme.wme_chanParams.cap_wmeParams; 4675 struct urtwn_softc *sc = ic->ic_softc; 4676 uint8_t aifs, acm, slottime; 4677 int ac; 4678 4679 acm = 0; 4680 slottime = IEEE80211_GET_SLOTTIME(ic); 4681 4682 URTWN_LOCK(sc); 4683 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4684 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4685 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4686 urtwn_write_4(sc, wme2queue[ac].reg, 4687 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 4688 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 4689 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 4690 SM(R92C_EDCA_PARAM_AIFS, aifs)); 4691 if (ac != WME_AC_BE) 4692 acm |= wmep[ac].wmep_acm << ac; 4693 } 4694 4695 if (acm != 0) 4696 acm |= R92C_ACMHWCTRL_EN; 4697 urtwn_write_1(sc, R92C_ACMHWCTRL, 4698 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 4699 acm); 4700 4701 URTWN_UNLOCK(sc); 4702 4703 return 0; 4704} 4705 4706static void 4707urtwn_update_slot(struct ieee80211com *ic) 4708{ 4709 urtwn_cmd_sleepable(ic->ic_softc, NULL, 0, urtwn_update_slot_cb); 4710} 4711 4712static void 4713urtwn_update_slot_cb(struct urtwn_softc *sc, union sec_param *data) 4714{ 4715 struct ieee80211com *ic = &sc->sc_ic; 4716 uint8_t slottime; 4717 4718 slottime = IEEE80211_GET_SLOTTIME(ic); 4719 4720 URTWN_DPRINTF(sc, URTWN_DEBUG_ANY, "%s: setting slot time to %uus\n", 4721 __func__, slottime); 4722 4723 urtwn_write_1(sc, R92C_SLOT, slottime); 4724 urtwn_update_aifs(sc, slottime); 4725} 4726 4727static void 4728urtwn_update_aifs(struct urtwn_softc *sc, uint8_t slottime) 4729{ 4730 const struct wmeParams *wmep = 4731 sc->sc_ic.ic_wme.wme_chanParams.cap_wmeParams; 4732 uint8_t aifs, ac; 4733 4734 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4735 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4736 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4737 urtwn_write_1(sc, wme2queue[ac].reg, aifs); 4738 } 4739} 4740 4741static void 4742urtwn_set_promisc(struct urtwn_softc *sc) 4743{ 4744 struct ieee80211com *ic = &sc->sc_ic; 4745 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4746 uint32_t rcr, mask1, mask2; 4747 4748 URTWN_ASSERT_LOCKED(sc); 4749 4750 if (vap->iv_opmode == IEEE80211_M_MONITOR) 4751 return; 4752 4753 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 4754 mask2 = R92C_RCR_APM; 4755 4756 if (vap->iv_state == IEEE80211_S_RUN) { 4757 switch (vap->iv_opmode) { 4758 case IEEE80211_M_STA: 4759 mask2 |= R92C_RCR_CBSSID_DATA; 4760 /* FALLTHROUGH */ 4761 case IEEE80211_M_HOSTAP: 4762 mask2 |= R92C_RCR_CBSSID_BCN; 4763 break; 4764 case IEEE80211_M_IBSS: 4765 mask2 |= R92C_RCR_CBSSID_DATA; 4766 break; 4767 default: 4768 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4769 __func__, vap->iv_opmode); 4770 return; 4771 } 4772 } 4773 4774 rcr = urtwn_read_4(sc, R92C_RCR); 4775 if (ic->ic_promisc == 0) 4776 rcr = (rcr & ~mask1) | mask2; 4777 else 4778 rcr = (rcr & ~mask2) | mask1; 4779 urtwn_write_4(sc, R92C_RCR, rcr); 4780} 4781 4782static void 4783urtwn_update_promisc(struct ieee80211com *ic) 4784{ 4785 struct urtwn_softc *sc = ic->ic_softc; 4786 4787 URTWN_LOCK(sc); 4788 if (sc->sc_flags & URTWN_RUNNING) 4789 urtwn_set_promisc(sc); 4790 URTWN_UNLOCK(sc); 4791} 4792 4793static void 4794urtwn_update_mcast(struct ieee80211com *ic) 4795{ 4796 /* XXX do nothing? */ 4797} 4798 4799static struct ieee80211_node * 4800urtwn_r88e_node_alloc(struct ieee80211vap *vap, 4801 const uint8_t mac[IEEE80211_ADDR_LEN]) 4802{ 4803 struct urtwn_node *un; 4804 4805 un = malloc(sizeof (struct urtwn_node), M_80211_NODE, 4806 M_NOWAIT | M_ZERO); 4807 4808 if (un == NULL) 4809 return NULL; 4810 4811 un->id = URTWN_MACID_UNDEFINED; 4812 4813 return &un->ni; 4814} 4815 4816static void 4817urtwn_r88e_newassoc(struct ieee80211_node *ni, int isnew) 4818{ 4819 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4820 struct urtwn_node *un = URTWN_NODE(ni); 4821 uint8_t id; 4822 4823 if (!isnew) 4824 return; 4825 4826 URTWN_NT_LOCK(sc); 4827 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 4828 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 4829 un->id = id; 4830 sc->node_list[id] = ni; 4831 break; 4832 } 4833 } 4834 URTWN_NT_UNLOCK(sc); 4835 4836 if (id > URTWN_MACID_MAX(sc)) { 4837 device_printf(sc->sc_dev, "%s: node table is full\n", 4838 __func__); 4839 } 4840} 4841 4842static void 4843urtwn_r88e_node_free(struct ieee80211_node *ni) 4844{ 4845 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4846 struct urtwn_node *un = URTWN_NODE(ni); 4847 4848 URTWN_NT_LOCK(sc); 4849 if (un->id != URTWN_MACID_UNDEFINED) 4850 sc->node_list[un->id] = NULL; 4851 URTWN_NT_UNLOCK(sc); 4852 4853 sc->sc_node_free(ni); 4854} 4855 4856static void 4857urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 4858 struct ieee80211_channel *extc) 4859{ 4860 struct ieee80211com *ic = &sc->sc_ic; 4861 uint32_t reg; 4862 u_int chan; 4863 int i; 4864 4865 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4866 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 4867 device_printf(sc->sc_dev, 4868 "%s: invalid channel %x\n", __func__, chan); 4869 return; 4870 } 4871 4872 /* Set Tx power for this new channel. */ 4873 urtwn_set_txpower(sc, c, extc); 4874 4875 for (i = 0; i < sc->nrxchains; i++) { 4876 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4877 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4878 } 4879#ifndef IEEE80211_NO_HT 4880 if (extc != NULL) { 4881 /* Is secondary channel below or above primary? */ 4882 int prichlo = c->ic_freq < extc->ic_freq; 4883 4884 urtwn_write_1(sc, R92C_BWOPMODE, 4885 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4886 4887 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4888 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4889 urtwn_write_1(sc, R92C_RRSR + 2, reg); 4890 4891 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4892 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4893 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4894 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4895 4896 /* Set CCK side band. */ 4897 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4898 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4899 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4900 4901 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4902 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4903 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4904 4905 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4906 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4907 ~R92C_FPGA0_ANAPARAM2_CBW20); 4908 4909 reg = urtwn_bb_read(sc, 0x818); 4910 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4911 urtwn_bb_write(sc, 0x818, reg); 4912 4913 /* Select 40MHz bandwidth. */ 4914 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4915 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4916 } else 4917#endif 4918 { 4919 urtwn_write_1(sc, R92C_BWOPMODE, 4920 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4921 4922 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4923 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4924 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4925 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4926 4927 if (!(sc->chip & URTWN_CHIP_88E)) { 4928 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4929 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4930 R92C_FPGA0_ANAPARAM2_CBW20); 4931 } 4932 4933 /* Select 20MHz bandwidth. */ 4934 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4935 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4936 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 4937 R92C_RF_CHNLBW_BW20)); 4938 } 4939} 4940 4941static void 4942urtwn_iq_calib(struct urtwn_softc *sc) 4943{ 4944 /* TODO */ 4945} 4946 4947static void 4948urtwn_lc_calib(struct urtwn_softc *sc) 4949{ 4950 uint32_t rf_ac[2]; 4951 uint8_t txmode; 4952 int i; 4953 4954 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4955 if ((txmode & 0x70) != 0) { 4956 /* Disable all continuous Tx. */ 4957 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4958 4959 /* Set RF mode to standby mode. */ 4960 for (i = 0; i < sc->nrxchains; i++) { 4961 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4962 urtwn_rf_write(sc, i, R92C_RF_AC, 4963 RW(rf_ac[i], R92C_RF_AC_MODE, 4964 R92C_RF_AC_MODE_STANDBY)); 4965 } 4966 } else { 4967 /* Block all Tx queues. */ 4968 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 4969 } 4970 /* Start calibration. */ 4971 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4972 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4973 4974 /* Give calibration the time to complete. */ 4975 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 4976 4977 /* Restore configuration. */ 4978 if ((txmode & 0x70) != 0) { 4979 /* Restore Tx mode. */ 4980 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4981 /* Restore RF mode. */ 4982 for (i = 0; i < sc->nrxchains; i++) 4983 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4984 } else { 4985 /* Unblock all Tx queues. */ 4986 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4987 } 4988} 4989 4990static void 4991urtwn_temp_calib(struct urtwn_softc *sc) 4992{ 4993 uint8_t temp; 4994 4995 URTWN_ASSERT_LOCKED(sc); 4996 4997 if (!(sc->sc_flags & URTWN_TEMP_MEASURED)) { 4998 /* Start measuring temperature. */ 4999 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5000 "%s: start measuring temperature\n", __func__); 5001 if (sc->chip & URTWN_CHIP_88E) { 5002 urtwn_rf_write(sc, 0, R88E_RF_T_METER, 5003 R88E_RF_T_METER_START); 5004 } else { 5005 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 5006 R92C_RF_T_METER_START); 5007 } 5008 sc->sc_flags |= URTWN_TEMP_MEASURED; 5009 return; 5010 } 5011 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 5012 5013 /* Read measured temperature. */ 5014 if (sc->chip & URTWN_CHIP_88E) { 5015 temp = MS(urtwn_rf_read(sc, 0, R88E_RF_T_METER), 5016 R88E_RF_T_METER_VAL); 5017 } else { 5018 temp = MS(urtwn_rf_read(sc, 0, R92C_RF_T_METER), 5019 R92C_RF_T_METER_VAL); 5020 } 5021 if (temp == 0) { /* Read failed, skip. */ 5022 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5023 "%s: temperature read failed, skipping\n", __func__); 5024 return; 5025 } 5026 5027 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5028 "%s: temperature: previous %u, current %u\n", 5029 __func__, sc->thcal_lctemp, temp); 5030 5031 /* 5032 * Redo LC calibration if temperature changed significantly since 5033 * last calibration. 5034 */ 5035 if (sc->thcal_lctemp == 0) { 5036 /* First LC calibration is performed in urtwn_init(). */ 5037 sc->thcal_lctemp = temp; 5038 } else if (abs(temp - sc->thcal_lctemp) > 1) { 5039 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5040 "%s: LC calib triggered by temp: %u -> %u\n", 5041 __func__, sc->thcal_lctemp, temp); 5042 urtwn_lc_calib(sc); 5043 /* Record temperature of last LC calibration. */ 5044 sc->thcal_lctemp = temp; 5045 } 5046} 5047 5048static int 5049urtwn_init(struct urtwn_softc *sc) 5050{ 5051 struct ieee80211com *ic = &sc->sc_ic; 5052 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5053 uint8_t macaddr[IEEE80211_ADDR_LEN]; 5054 uint32_t reg; 5055 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 5056 int error; 5057 5058 URTWN_LOCK(sc); 5059 if (sc->sc_flags & URTWN_RUNNING) { 5060 URTWN_UNLOCK(sc); 5061 return (0); 5062 } 5063 5064 /* Init firmware commands ring. */ 5065 sc->fwcur = 0; 5066 5067 /* Allocate Tx/Rx buffers. */ 5068 error = urtwn_alloc_rx_list(sc); 5069 if (error != 0) 5070 goto fail; 5071 5072 error = urtwn_alloc_tx_list(sc); 5073 if (error != 0) 5074 goto fail; 5075 5076 /* Power on adapter. */ 5077 error = urtwn_power_on(sc); 5078 if (error != 0) 5079 goto fail; 5080 5081 /* Initialize DMA. */ 5082 error = urtwn_dma_init(sc); 5083 if (error != 0) 5084 goto fail; 5085 5086 /* Set info size in Rx descriptors (in 64-bit words). */ 5087 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 5088 5089 /* Init interrupts. */ 5090 if (sc->chip & URTWN_CHIP_88E) { 5091 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 5092 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5093 goto fail; 5094 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 5095 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 5096 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5097 goto fail; 5098 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 5099 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 5100 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5101 goto fail; 5102 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5103 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5104 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 5105 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5106 goto fail; 5107 } else { 5108 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 5109 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5110 goto fail; 5111 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 5112 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5113 goto fail; 5114 } 5115 5116 /* Set MAC address. */ 5117 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 5118 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 5119 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5120 goto fail; 5121 5122 /* Set initial network type. */ 5123 urtwn_set_mode(sc, R92C_MSR_INFRA); 5124 5125 /* Initialize Rx filter. */ 5126 urtwn_rxfilter_init(sc); 5127 5128 /* Set response rate. */ 5129 reg = urtwn_read_4(sc, R92C_RRSR); 5130 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5131 urtwn_write_4(sc, R92C_RRSR, reg); 5132 5133 /* Set short/long retry limits. */ 5134 urtwn_write_2(sc, R92C_RL, 5135 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5136 5137 /* Initialize EDCA parameters. */ 5138 urtwn_edca_init(sc); 5139 5140 /* Setup rate fallback. */ 5141 if (!(sc->chip & URTWN_CHIP_88E)) { 5142 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5143 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5144 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5145 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5146 } 5147 5148 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5149 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5150 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5151 /* Set ACK timeout. */ 5152 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5153 5154 /* Setup USB aggregation. */ 5155 reg = urtwn_read_4(sc, R92C_TDECTRL); 5156 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5157 urtwn_write_4(sc, R92C_TDECTRL, reg); 5158 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5159 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5160 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5161 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5162 if (sc->chip & URTWN_CHIP_88E) 5163 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5164 else { 5165 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5166 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5167 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5168 R92C_USB_SPECIAL_OPTION_AGG_EN); 5169 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 5170 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 5171 } 5172 5173 /* Initialize beacon parameters. */ 5174 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5175 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5176 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 5177 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 5178 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5179 5180 if (!(sc->chip & URTWN_CHIP_88E)) { 5181 /* Setup AMPDU aggregation. */ 5182 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5183 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5184 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 5185 5186 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5187 } 5188 5189#ifndef URTWN_WITHOUT_UCODE 5190 /* Load 8051 microcode. */ 5191 error = urtwn_load_firmware(sc); 5192 if (error == 0) 5193 sc->sc_flags |= URTWN_FW_LOADED; 5194#endif 5195 5196 /* Initialize MAC/BB/RF blocks. */ 5197 error = urtwn_mac_init(sc); 5198 if (error != 0) { 5199 device_printf(sc->sc_dev, 5200 "%s: error while initializing MAC block\n", __func__); 5201 goto fail; 5202 } 5203 urtwn_bb_init(sc); 5204 urtwn_rf_init(sc); 5205 5206 /* Reinitialize Rx filter (D3845 is not committed yet). */ 5207 urtwn_rxfilter_init(sc); 5208 5209 if (sc->chip & URTWN_CHIP_88E) { 5210 urtwn_write_2(sc, R92C_CR, 5211 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5212 R92C_CR_MACRXEN); 5213 } 5214 5215 /* Turn CCK and OFDM blocks on. */ 5216 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5217 reg |= R92C_RFMOD_CCK_EN; 5218 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5219 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5220 goto fail; 5221 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5222 reg |= R92C_RFMOD_OFDM_EN; 5223 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5224 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5225 goto fail; 5226 5227 /* Clear per-station keys table. */ 5228 urtwn_cam_init(sc); 5229 5230 /* Enable decryption / encryption. */ 5231 urtwn_write_2(sc, R92C_SECCFG, 5232 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 5233 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA | 5234 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 5235 5236 /* 5237 * Install static keys (if any). 5238 * Must be called after urtwn_cam_init(). 5239 */ 5240 ieee80211_runtask(ic, &sc->cmdq_task); 5241 5242 /* Enable hardware sequence numbering. */ 5243 urtwn_write_1(sc, R92C_HWSEQ_CTRL, R92C_TX_QUEUE_ALL); 5244 5245 /* Enable per-packet TX report. */ 5246 if (sc->chip & URTWN_CHIP_88E) { 5247 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 5248 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 5249 } 5250 5251 /* Perform LO and IQ calibrations. */ 5252 urtwn_iq_calib(sc); 5253 /* Perform LC calibration. */ 5254 urtwn_lc_calib(sc); 5255 5256 /* Fix USB interference issue. */ 5257 if (!(sc->chip & URTWN_CHIP_88E)) { 5258 urtwn_write_1(sc, 0xfe40, 0xe0); 5259 urtwn_write_1(sc, 0xfe41, 0x8d); 5260 urtwn_write_1(sc, 0xfe42, 0x80); 5261 5262 urtwn_pa_bias_init(sc); 5263 } 5264 5265 /* Initialize GPIO setting. */ 5266 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5267 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5268 5269 /* Fix for lower temperature. */ 5270 if (!(sc->chip & URTWN_CHIP_88E)) 5271 urtwn_write_1(sc, 0x15, 0xe9); 5272 5273 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 5274 5275 sc->sc_flags |= URTWN_RUNNING; 5276 5277 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5278fail: 5279 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5280 error = EIO; 5281 5282 URTWN_UNLOCK(sc); 5283 5284 return (error); 5285} 5286 5287static void 5288urtwn_stop(struct urtwn_softc *sc) 5289{ 5290 5291 URTWN_LOCK(sc); 5292 if (!(sc->sc_flags & URTWN_RUNNING)) { 5293 URTWN_UNLOCK(sc); 5294 return; 5295 } 5296 5297 sc->sc_flags &= ~(URTWN_RUNNING | URTWN_FW_LOADED | 5298 URTWN_TEMP_MEASURED); 5299 sc->thcal_lctemp = 0; 5300 callout_stop(&sc->sc_watchdog_ch); 5301 5302 urtwn_abort_xfers(sc); 5303 urtwn_drain_mbufq(sc); 5304 urtwn_power_off(sc); 5305 URTWN_UNLOCK(sc); 5306} 5307 5308static void 5309urtwn_abort_xfers(struct urtwn_softc *sc) 5310{ 5311 int i; 5312 5313 URTWN_ASSERT_LOCKED(sc); 5314 5315 /* abort any pending transfers */ 5316 for (i = 0; i < URTWN_N_TRANSFER; i++) 5317 usbd_transfer_stop(sc->sc_xfer[i]); 5318} 5319 5320static int 5321urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5322 const struct ieee80211_bpf_params *params) 5323{ 5324 struct ieee80211com *ic = ni->ni_ic; 5325 struct urtwn_softc *sc = ic->ic_softc; 5326 struct urtwn_data *bf; 5327 int error; 5328 5329 /* prevent management frames from being sent if we're not ready */ 5330 URTWN_LOCK(sc); 5331 if (!(sc->sc_flags & URTWN_RUNNING)) { 5332 error = ENETDOWN; 5333 goto end; 5334 } 5335 5336 bf = urtwn_getbuf(sc); 5337 if (bf == NULL) { 5338 error = ENOBUFS; 5339 goto end; 5340 } 5341 5342 if (params == NULL) { 5343 /* 5344 * Legacy path; interpret frame contents to decide 5345 * precisely how to send the frame. 5346 */ 5347 error = urtwn_tx_data(sc, ni, m, bf); 5348 } else { 5349 /* 5350 * Caller supplied explicit parameters to use in 5351 * sending the frame. 5352 */ 5353 error = urtwn_tx_raw(sc, ni, m, bf, params); 5354 } 5355 if (error != 0) { 5356 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 5357 goto end; 5358 } 5359 5360 sc->sc_txtimer = 5; 5361 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5362 5363end: 5364 if (error != 0) 5365 m_freem(m); 5366 5367 URTWN_UNLOCK(sc); 5368 5369 return (error); 5370} 5371 5372static void 5373urtwn_ms_delay(struct urtwn_softc *sc) 5374{ 5375 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 5376} 5377 5378static device_method_t urtwn_methods[] = { 5379 /* Device interface */ 5380 DEVMETHOD(device_probe, urtwn_match), 5381 DEVMETHOD(device_attach, urtwn_attach), 5382 DEVMETHOD(device_detach, urtwn_detach), 5383 5384 DEVMETHOD_END 5385}; 5386 5387static driver_t urtwn_driver = { 5388 "urtwn", 5389 urtwn_methods, 5390 sizeof(struct urtwn_softc) 5391}; 5392 5393static devclass_t urtwn_devclass; 5394 5395DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 5396MODULE_DEPEND(urtwn, usb, 1, 1, 1); 5397MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 5398#ifndef URTWN_WITHOUT_UCODE 5399MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 5400#endif 5401MODULE_VERSION(urtwn, 1); 5402USB_PNP_HOST_INFO(urtwn_devs); 5403