if_urtwn.c revision 292207
1119418Sobrien/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2154704Smjacob 3154704Smjacob/*- 499756Smjacob * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 599756Smjacob * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 699756Smjacob * Copyright (c) 2015 Andriy Voskoboinyk <avos@FreeBSD.org> 799756Smjacob * 899756Smjacob * Permission to use, copy, modify, and distribute this software for any 999756Smjacob * purpose with or without fee is hereby granted, provided that the above 1099756Smjacob * copyright notice and this permission notice appear in all copies. 1199756Smjacob * 1299756Smjacob * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1399756Smjacob * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1499756Smjacob * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1599756Smjacob * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1699756Smjacob * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1799756Smjacob * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1899756Smjacob * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1999756Smjacob */ 2099756Smjacob 2199756Smjacob#include <sys/cdefs.h> 2299756Smjacob__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 292207 2015-12-14 13:05:16Z avos $"); 2399756Smjacob 2499756Smjacob/* 2599756Smjacob * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 26160410Smjacob */ 27160410Smjacob 28160410Smjacob#include "opt_wlan.h" 29160410Smjacob 3099756Smjacob#include <sys/param.h> 31119418Sobrien#include <sys/sockio.h> 32119418Sobrien#include <sys/sysctl.h> 3399756Smjacob#include <sys/lock.h> 3499756Smjacob#include <sys/mutex.h> 3599756Smjacob#include <sys/condvar.h> 36160212Smjacob#include <sys/mbuf.h> 37160212Smjacob#include <sys/kernel.h> 3899756Smjacob#include <sys/socket.h> 3999756Smjacob#include <sys/systm.h> 40130026Sphk#include <sys/malloc.h> 4199756Smjacob#include <sys/module.h> 42133589Smarius#include <sys/bus.h> 43133589Smarius#include <sys/endian.h> 44207579Smarius#include <sys/linker.h> 45133589Smarius#include <sys/firmware.h> 4699756Smjacob#include <sys/kdb.h> 47207579Smarius 4899756Smjacob#include <machine/bus.h> 4999756Smjacob#include <machine/resource.h> 5099756Smjacob#include <sys/rman.h> 5199756Smjacob 5299756Smjacob#include <net/bpf.h> 5399756Smjacob#include <net/if.h> 54196008Smjacob#include <net/if_var.h> 55196008Smjacob#include <net/if_arp.h> 56196008Smjacob#include <net/ethernet.h> 57157943Smjacob#include <net/if_dl.h> 58196008Smjacob#include <net/if_media.h> 5999756Smjacob#include <net/if_types.h> 60196008Smjacob 61165269Smjacob#include <netinet/in.h> 62157943Smjacob#include <netinet/in_systm.h> 63157943Smjacob#include <netinet/in_var.h> 6499756Smjacob#include <netinet/if_ether.h> 6599756Smjacob#include <netinet/ip.h> 6699756Smjacob 6799756Smjacob#include <net80211/ieee80211_var.h> 6899756Smjacob#include <net80211/ieee80211_input.h> 6999756Smjacob#include <net80211/ieee80211_regdomain.h> 7099756Smjacob#include <net80211/ieee80211_radiotap.h> 71169292Smjacob#include <net80211/ieee80211_ratectl.h> 72165269Smjacob 7399756Smjacob#include <dev/usb/usb.h> 7499756Smjacob#include <dev/usb/usbdi.h> 7599756Smjacob#include <dev/usb/usb_device.h> 7699756Smjacob#include "usbdevs.h" 7799756Smjacob 7899756Smjacob#define USB_DEBUG_VAR urtwn_debug 7999756Smjacob#include <dev/usb/usb_debug.h> 8099756Smjacob 81240025Smjacob#include <dev/usb/wlan/if_urtwnreg.h> 8299756Smjacob#include <dev/usb/wlan/if_urtwnvar.h> 8399756Smjacob 84169459Smjacob#ifdef USB_DEBUG 8599756Smjacobstatic int urtwn_debug = 0; 86157943Smjacob 8799756SmjacobSYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 88240025SmjacobSYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 89240025Smjacob "Debug level"); 90240025Smjacob#endif 91240025Smjacob 9299756Smjacob#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 9399756Smjacob 9499756Smjacob/* various supported device vendors/products */ 95196008Smjacobstatic const STRUCT_USB_HOST_ID urtwn_devs[] = { 9699756Smjacob#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 9799756Smjacob#define URTWN_RTL8188E_DEV(v,p) \ 9899756Smjacob { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 9999756Smjacob#define URTWN_RTL8188E 1 10099756Smjacob URTWN_DEV(ABOCOM, RTL8188CU_1), 10199756Smjacob URTWN_DEV(ABOCOM, RTL8188CU_2), 10299756Smjacob URTWN_DEV(ABOCOM, RTL8192CU), 10399756Smjacob URTWN_DEV(ASUS, RTL8192CU), 104240025Smjacob URTWN_DEV(ASUS, USBN10NANO), 10599756Smjacob URTWN_DEV(AZUREWAVE, RTL8188CE_1), 10699756Smjacob URTWN_DEV(AZUREWAVE, RTL8188CE_2), 10799756Smjacob URTWN_DEV(AZUREWAVE, RTL8188CU), 10899756Smjacob URTWN_DEV(BELKIN, F7D2102), 10999756Smjacob URTWN_DEV(BELKIN, RTL8188CU), 11099756Smjacob URTWN_DEV(BELKIN, RTL8192CU), 11199756Smjacob URTWN_DEV(CHICONY, RTL8188CUS_1), 11299756Smjacob URTWN_DEV(CHICONY, RTL8188CUS_2), 113236655Seadler URTWN_DEV(CHICONY, RTL8188CUS_3), 114236655Seadler URTWN_DEV(CHICONY, RTL8188CUS_4), 11599756Smjacob URTWN_DEV(CHICONY, RTL8188CUS_5), 11699756Smjacob URTWN_DEV(COREGA, RTL8192CU), 11799756Smjacob URTWN_DEV(DLINK, RTL8188CU), 11899756Smjacob URTWN_DEV(DLINK, RTL8192CU_1), 11999756Smjacob URTWN_DEV(DLINK, RTL8192CU_2), 120133589Smarius URTWN_DEV(DLINK, RTL8192CU_3), 12199756Smjacob URTWN_DEV(DLINK, DWA131B), 12299756Smjacob URTWN_DEV(EDIMAX, EW7811UN), 12399756Smjacob URTWN_DEV(EDIMAX, RTL8192CU), 12499756Smjacob URTWN_DEV(FEIXUN, RTL8188CU), 12599756Smjacob URTWN_DEV(FEIXUN, RTL8192CU), 12699756Smjacob URTWN_DEV(GUILLEMOT, HWNUP150), 12799756Smjacob URTWN_DEV(HAWKING, RTL8192CU), 12899756Smjacob URTWN_DEV(HP3, RTL8188CU), 12999756Smjacob URTWN_DEV(NETGEAR, WNA1000M), 13099756Smjacob URTWN_DEV(NETGEAR, RTL8192CU), 13199756Smjacob URTWN_DEV(NETGEAR4, RTL8188CU), 13299756Smjacob URTWN_DEV(NOVATECH, RTL8188CU), 13399756Smjacob URTWN_DEV(PLANEX2, RTL8188CU_1), 13499756Smjacob URTWN_DEV(PLANEX2, RTL8188CU_2), 13599756Smjacob URTWN_DEV(PLANEX2, RTL8188CU_3), 13699756Smjacob URTWN_DEV(PLANEX2, RTL8188CU_4), 13799756Smjacob URTWN_DEV(PLANEX2, RTL8188CUS), 13899756Smjacob URTWN_DEV(PLANEX2, RTL8192CU), 13999756Smjacob URTWN_DEV(REALTEK, RTL8188CE_0), 14099756Smjacob URTWN_DEV(REALTEK, RTL8188CE_1), 14199756Smjacob URTWN_DEV(REALTEK, RTL8188CTV), 14299756Smjacob URTWN_DEV(REALTEK, RTL8188CU_0), 143240025Smjacob URTWN_DEV(REALTEK, RTL8188CU_1), 14499756Smjacob URTWN_DEV(REALTEK, RTL8188CU_2), 145157943Smjacob URTWN_DEV(REALTEK, RTL8188CU_3), 14699756Smjacob URTWN_DEV(REALTEK, RTL8188CU_COMBO), 147163899Smjacob URTWN_DEV(REALTEK, RTL8188CUS), 14899756Smjacob URTWN_DEV(REALTEK, RTL8188RU_1), 149240025Smjacob URTWN_DEV(REALTEK, RTL8188RU_2), 150240025Smjacob URTWN_DEV(REALTEK, RTL8188RU_3), 151240025Smjacob URTWN_DEV(REALTEK, RTL8191CU), 152240025Smjacob URTWN_DEV(REALTEK, RTL8192CE), 153240025Smjacob URTWN_DEV(REALTEK, RTL8192CU), 154240025Smjacob URTWN_DEV(SITECOMEU, RTL8188CU_1), 155240025Smjacob URTWN_DEV(SITECOMEU, RTL8188CU_2), 156240025Smjacob URTWN_DEV(SITECOMEU, RTL8192CU), 157240025Smjacob URTWN_DEV(TRENDNET, RTL8188CU), 15899756Smjacob URTWN_DEV(TRENDNET, RTL8192CU), 15999756Smjacob URTWN_DEV(ZYXEL, RTL8192CU), 16099756Smjacob /* URTWN_RTL8188E */ 16199756Smjacob URTWN_RTL8188E_DEV(DLINK, DWA123D1), 16299756Smjacob URTWN_RTL8188E_DEV(DLINK, DWA125D1), 16399756Smjacob URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 16499756Smjacob URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 16599756Smjacob URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 16699756Smjacob#undef URTWN_RTL8188E_DEV 16799756Smjacob#undef URTWN_DEV 16899756Smjacob}; 16999756Smjacob 17099756Smjacobstatic device_probe_t urtwn_match; 17199756Smjacobstatic device_attach_t urtwn_attach; 17299756Smjacobstatic device_detach_t urtwn_detach; 17399756Smjacob 17499756Smjacobstatic usb_callback_t urtwn_bulk_tx_callback; 17599756Smjacobstatic usb_callback_t urtwn_bulk_rx_callback; 17699756Smjacob 17799756Smjacobstatic void urtwn_drain_mbufq(struct urtwn_softc *sc); 17899756Smjacobstatic usb_error_t urtwn_do_request(struct urtwn_softc *, 17999756Smjacob struct usb_device_request *, void *); 180240025Smjacobstatic struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 181240025Smjacob const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 18299756Smjacob const uint8_t [IEEE80211_ADDR_LEN], 183240025Smjacob const uint8_t [IEEE80211_ADDR_LEN]); 184240025Smjacobstatic void urtwn_vap_delete(struct ieee80211vap *); 185240025Smjacobstatic struct mbuf * urtwn_rx_copy_to_mbuf(struct urtwn_softc *, 18699756Smjacob struct r92c_rx_stat *, int); 18799756Smjacobstatic struct mbuf * urtwn_report_intr(struct usb_xfer *, 18899756Smjacob struct urtwn_data *); 18999756Smjacobstatic struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int); 19099756Smjacobstatic void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 19199756Smjacob void *); 19299756Smjacobstatic struct ieee80211_node *urtwn_rx_frame(struct urtwn_softc *, 19399756Smjacob struct mbuf *, int8_t *); 19499756Smjacobstatic void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 19599756Smjacob int); 196240025Smjacobstatic int urtwn_alloc_list(struct urtwn_softc *, 197240025Smjacob struct urtwn_data[], int, int); 19899756Smjacobstatic int urtwn_alloc_rx_list(struct urtwn_softc *); 19999756Smjacobstatic int urtwn_alloc_tx_list(struct urtwn_softc *); 20099756Smjacobstatic void urtwn_free_list(struct urtwn_softc *, 20199756Smjacob struct urtwn_data data[], int); 202196008Smjacobstatic void urtwn_free_rx_list(struct urtwn_softc *); 20399756Smjacobstatic void urtwn_free_tx_list(struct urtwn_softc *); 204198822Smjacobstatic struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 205198822Smjacobstatic struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 206205236Smjacobstatic usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 20799756Smjacob uint8_t *, int); 208155251Smariusstatic usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 209155251Smariusstatic usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 210155251Smariusstatic usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 211155251Smariusstatic usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 212155251Smarius uint8_t *, int); 213155251Smariusstatic uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 21499756Smjacobstatic uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 21599756Smjacobstatic uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 21699756Smjacobstatic int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 21799756Smjacob const void *, int); 21899756Smjacobstatic void urtwn_cmdq_cb(void *, int); 21999756Smjacobstatic int urtwn_cmd_sleepable(struct urtwn_softc *, const void *, 22099756Smjacob size_t, CMD_FUNC_PROTO); 22199756Smjacobstatic void urtwn_r92c_rf_write(struct urtwn_softc *, int, 22299756Smjacob uint8_t, uint32_t); 22399756Smjacobstatic void urtwn_r88e_rf_write(struct urtwn_softc *, int, 22499756Smjacob uint8_t, uint32_t); 22599756Smjacobstatic uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 22699756Smjacobstatic int urtwn_llt_write(struct urtwn_softc *, uint32_t, 22799756Smjacob uint32_t); 22899756Smjacobstatic int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 22999756Smjacobstatic int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 23099756Smjacob uint8_t, uint8_t); 23199756Smjacob#ifdef URTWN_DEBUG 23299756Smjacobstatic void urtwn_dump_rom_contents(struct urtwn_softc *, 23399756Smjacob uint8_t *, uint16_t); 23499756Smjacob#endif 23599756Smjacobstatic int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 23699756Smjacob uint16_t); 23799756Smjacobstatic int urtwn_efuse_switch_power(struct urtwn_softc *); 23899756Smjacobstatic int urtwn_read_chipid(struct urtwn_softc *); 239163899Smjacobstatic int urtwn_read_rom(struct urtwn_softc *); 24099756Smjacobstatic int urtwn_r88e_read_rom(struct urtwn_softc *); 241163899Smjacobstatic int urtwn_ra_init(struct urtwn_softc *); 242163899Smjacobstatic void urtwn_init_beacon(struct urtwn_softc *, 243163899Smjacob struct urtwn_vap *); 244163899Smjacobstatic int urtwn_setup_beacon(struct urtwn_softc *, 245163899Smjacob struct ieee80211_node *); 246133589Smariusstatic void urtwn_update_beacon(struct ieee80211vap *, int); 247133589Smariusstatic int urtwn_tx_beacon(struct urtwn_softc *sc, 248196008Smjacob struct urtwn_vap *); 24999756Smjacobstatic int urtwn_key_alloc(struct ieee80211vap *, 250100690Smjacob struct ieee80211_key *, ieee80211_keyix *, 251160212Smjacob ieee80211_keyix *); 252160212Smjacobstatic void urtwn_key_set_cb(struct urtwn_softc *, 253160212Smjacob union sec_param *); 254160212Smjacobstatic void urtwn_key_del_cb(struct urtwn_softc *, 255160212Smjacob union sec_param *); 256160212Smjacobstatic int urtwn_key_set(struct ieee80211vap *, 257160212Smjacob const struct ieee80211_key *); 258160212Smjacobstatic int urtwn_key_delete(struct ieee80211vap *, 259160212Smjacob const struct ieee80211_key *); 26099756Smjacobstatic void urtwn_tsf_task_adhoc(void *, int); 26199756Smjacobstatic void urtwn_tsf_sync_enable(struct urtwn_softc *, 26299756Smjacob struct ieee80211vap *); 26399756Smjacobstatic void urtwn_get_tsf(struct urtwn_softc *, uint64_t *); 26499756Smjacobstatic void urtwn_set_led(struct urtwn_softc *, int, int); 26599756Smjacobstatic void urtwn_set_mode(struct urtwn_softc *, uint8_t); 266100690Smjacobstatic void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 267196008Smjacob struct mbuf *, int, 268100690Smjacob const struct ieee80211_rx_stats *, int, int); 269100690Smjacobstatic int urtwn_newstate(struct ieee80211vap *, 270196008Smjacob enum ieee80211_state, int); 271100690Smjacobstatic void urtwn_watchdog(void *); 27299756Smjacobstatic void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 273196008Smjacobstatic int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 274207579Smariusstatic int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 275100690Smjacobstatic int urtwn_tx_data(struct urtwn_softc *, 276196008Smjacob struct ieee80211_node *, struct mbuf *, 27799756Smjacob struct urtwn_data *); 27899756Smjacobstatic void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 27999756Smjacob uint8_t, struct urtwn_data *); 28099756Smjacobstatic int urtwn_transmit(struct ieee80211com *, struct mbuf *); 28199756Smjacobstatic void urtwn_start(struct urtwn_softc *); 28299756Smjacobstatic void urtwn_parent(struct ieee80211com *); 28399756Smjacobstatic int urtwn_r92c_power_on(struct urtwn_softc *); 28499756Smjacobstatic int urtwn_r88e_power_on(struct urtwn_softc *); 28599756Smjacobstatic int urtwn_llt_init(struct urtwn_softc *); 286240025Smjacobstatic void urtwn_fw_reset(struct urtwn_softc *); 287163899Smjacobstatic void urtwn_r88e_fw_reset(struct urtwn_softc *); 288240025Smjacobstatic int urtwn_fw_loadpage(struct urtwn_softc *, int, 289163899Smjacob const uint8_t *, int); 290163899Smjacobstatic int urtwn_load_firmware(struct urtwn_softc *); 291163899Smjacobstatic int urtwn_dma_init(struct urtwn_softc *); 292163899Smjacobstatic int urtwn_mac_init(struct urtwn_softc *); 293240025Smjacobstatic void urtwn_bb_init(struct urtwn_softc *); 294240025Smjacobstatic void urtwn_rf_init(struct urtwn_softc *); 29599756Smjacobstatic void urtwn_cam_init(struct urtwn_softc *); 29699756Smjacobstatic int urtwn_cam_write(struct urtwn_softc *, uint32_t, 29799756Smjacob uint32_t); 298163899Smjacobstatic void urtwn_pa_bias_init(struct urtwn_softc *); 29999756Smjacobstatic void urtwn_rxfilter_init(struct urtwn_softc *); 30099756Smjacobstatic void urtwn_edca_init(struct urtwn_softc *); 30199756Smjacobstatic void urtwn_write_txpower(struct urtwn_softc *, int, 30299756Smjacob uint16_t[]); 30399756Smjacobstatic void urtwn_get_txpower(struct urtwn_softc *, int, 30499756Smjacob struct ieee80211_channel *, 30599756Smjacob struct ieee80211_channel *, uint16_t[]); 30699756Smjacobstatic void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 30799756Smjacob struct ieee80211_channel *, 308163899Smjacob struct ieee80211_channel *, uint16_t[]); 30999756Smjacobstatic void urtwn_set_txpower(struct urtwn_softc *, 310163899Smjacob struct ieee80211_channel *, 31199756Smjacob struct ieee80211_channel *); 31299756Smjacobstatic void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 31399756Smjacobstatic void urtwn_set_gain(struct urtwn_softc *, uint8_t); 31499756Smjacobstatic void urtwn_scan_start(struct ieee80211com *); 315173359Sscottlstatic void urtwn_scan_end(struct ieee80211com *); 316196008Smjacobstatic void urtwn_set_channel(struct ieee80211com *); 31799756Smjacobstatic int urtwn_wme_update(struct ieee80211com *); 318163899Smjacobstatic void urtwn_set_promisc(struct urtwn_softc *); 319173359Sscottlstatic void urtwn_update_promisc(struct ieee80211com *); 32099756Smjacobstatic void urtwn_update_mcast(struct ieee80211com *); 32199756Smjacobstatic struct ieee80211_node *urtwn_r88e_node_alloc(struct ieee80211vap *, 32299756Smjacob const uint8_t mac[IEEE80211_ADDR_LEN]); 323198822Smjacobstatic void urtwn_r88e_newassoc(struct ieee80211_node *, int); 324198822Smjacobstatic void urtwn_r88e_node_free(struct ieee80211_node *); 32599756Smjacobstatic void urtwn_set_chan(struct urtwn_softc *, 326198822Smjacob struct ieee80211_channel *, 327198822Smjacob struct ieee80211_channel *); 328198822Smjacobstatic void urtwn_iq_calib(struct urtwn_softc *); 32999756Smjacobstatic void urtwn_lc_calib(struct urtwn_softc *); 330173359Sscottlstatic int urtwn_init(struct urtwn_softc *); 33199756Smjacobstatic void urtwn_stop(struct urtwn_softc *); 33299756Smjacobstatic void urtwn_abort_xfers(struct urtwn_softc *); 33399756Smjacobstatic int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 33499756Smjacob const struct ieee80211_bpf_params *); 33599756Smjacobstatic void urtwn_ms_delay(struct urtwn_softc *); 33699756Smjacob 337163899Smjacob/* Aliases. */ 338240025Smjacob#define urtwn_bb_write urtwn_write_4 33999756Smjacob#define urtwn_bb_read urtwn_read_4 34099756Smjacob 341240025Smjacobstatic const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 342240025Smjacob [URTWN_BULK_RX] = { 34399756Smjacob .type = UE_BULK, 34499756Smjacob .endpoint = UE_ADDR_ANY, 345163899Smjacob .direction = UE_DIR_IN, 346163899Smjacob .bufsize = URTWN_RXBUFSZ, 347163899Smjacob .flags = { 34899756Smjacob .pipe_bof = 1, 349240025Smjacob .short_xfer_ok = 1 350240025Smjacob }, 351240025Smjacob .callback = urtwn_bulk_rx_callback, 35299756Smjacob }, 353240025Smjacob [URTWN_BULK_TX_BE] = { 354240025Smjacob .type = UE_BULK, 35599756Smjacob .endpoint = 0x03, 356240025Smjacob .direction = UE_DIR_OUT, 357240025Smjacob .bufsize = URTWN_TXBUFSZ, 358240025Smjacob .flags = { 359240025Smjacob .ext_buffer = 1, 360240025Smjacob .pipe_bof = 1, 361240025Smjacob .force_short_xfer = 1 362240025Smjacob }, 363240025Smjacob .callback = urtwn_bulk_tx_callback, 364240025Smjacob .timeout = URTWN_TX_TIMEOUT, /* ms */ 365240025Smjacob }, 36699756Smjacob [URTWN_BULK_TX_BK] = { 367240025Smjacob .type = UE_BULK, 368240025Smjacob .endpoint = 0x03, 369240025Smjacob .direction = UE_DIR_OUT, 370240025Smjacob .bufsize = URTWN_TXBUFSZ, 371240025Smjacob .flags = { 372240025Smjacob .ext_buffer = 1, 373240025Smjacob .pipe_bof = 1, 374240025Smjacob .force_short_xfer = 1, 375240025Smjacob }, 376240025Smjacob .callback = urtwn_bulk_tx_callback, 377240025Smjacob .timeout = URTWN_TX_TIMEOUT, /* ms */ 378240025Smjacob }, 379240025Smjacob [URTWN_BULK_TX_VI] = { 380240025Smjacob .type = UE_BULK, 38199756Smjacob .endpoint = 0x02, 38299756Smjacob .direction = UE_DIR_OUT, 38399756Smjacob .bufsize = URTWN_TXBUFSZ, 38499756Smjacob .flags = { 38599756Smjacob .ext_buffer = 1, 38699756Smjacob .pipe_bof = 1, 38799756Smjacob .force_short_xfer = 1 388167501Smjacob }, 38999756Smjacob .callback = urtwn_bulk_tx_callback, 39099756Smjacob .timeout = URTWN_TX_TIMEOUT, /* ms */ 391163899Smjacob }, 39299756Smjacob [URTWN_BULK_TX_VO] = { 393155704Smjacob .type = UE_BULK, 39499756Smjacob .endpoint = 0x02, 39599756Smjacob .direction = UE_DIR_OUT, 39699756Smjacob .bufsize = URTWN_TXBUFSZ, 39799756Smjacob .flags = { 39899756Smjacob .ext_buffer = 1, 39999756Smjacob .pipe_bof = 1, 40099756Smjacob .force_short_xfer = 1 40199756Smjacob }, 40299756Smjacob .callback = urtwn_bulk_tx_callback, 40399756Smjacob .timeout = URTWN_TX_TIMEOUT, /* ms */ 40499756Smjacob }, 40599756Smjacob}; 40699756Smjacob 40799756Smjacobstatic const struct wme_to_queue { 40899756Smjacob uint16_t reg; 40999756Smjacob uint8_t qid; 410163899Smjacob} wme2queue[WME_NUM_AC] = { 411157943Smjacob { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 41299756Smjacob { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 413155704Smjacob { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 41499756Smjacob { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 41599756Smjacob}; 41699756Smjacob 417167501Smjacobstatic int 41899756Smjacoburtwn_match(device_t self) 41999756Smjacob{ 42099756Smjacob struct usb_attach_arg *uaa = device_get_ivars(self); 42199756Smjacob 42299756Smjacob if (uaa->usb_mode != USB_MODE_HOST) 42399756Smjacob return (ENXIO); 424163899Smjacob if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 42599756Smjacob return (ENXIO); 42699756Smjacob if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 42799756Smjacob return (ENXIO); 42899756Smjacob 42999756Smjacob return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 43099756Smjacob} 431167501Smjacob 432218691Smariusstatic int 43399756Smjacoburtwn_attach(device_t self) 43499756Smjacob{ 43599756Smjacob struct usb_attach_arg *uaa = device_get_ivars(self); 436157943Smjacob struct urtwn_softc *sc = device_get_softc(self); 43799756Smjacob struct ieee80211com *ic = &sc->sc_ic; 43899756Smjacob uint8_t bands; 43999756Smjacob int error; 44099756Smjacob 44199756Smjacob device_set_usb_desc(self); 44299756Smjacob sc->sc_udev = uaa->device; 44399756Smjacob sc->sc_dev = self; 44499756Smjacob if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 44599756Smjacob sc->chip |= URTWN_CHIP_88E; 44699756Smjacob 44799756Smjacob mtx_init(&sc->sc_mtx, device_get_nameunit(self), 44899756Smjacob MTX_NETWORK_LOCK, MTX_DEF); 449157943Smjacob URTWN_CMDQ_LOCK_INIT(sc); 45099756Smjacob URTWN_NT_LOCK_INIT(sc); 45199756Smjacob callout_init(&sc->sc_watchdog_ch, 0); 45299756Smjacob mbufq_init(&sc->sc_snd, ifqmaxlen); 45399756Smjacob 45499756Smjacob sc->sc_iface_index = URTWN_IFACE_INDEX; 45599756Smjacob error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 45699756Smjacob sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 45799756Smjacob if (error) { 45899756Smjacob device_printf(self, "could not allocate USB transfers, " 459157943Smjacob "err=%s\n", usbd_errstr(error)); 46099756Smjacob goto detach; 46199756Smjacob } 462155704Smjacob 463242920Smjacob URTWN_LOCK(sc); 46499756Smjacob 46599756Smjacob error = urtwn_read_chipid(sc); 46699756Smjacob if (error) { 46799756Smjacob device_printf(sc->sc_dev, "unsupported test chip\n"); 46899756Smjacob URTWN_UNLOCK(sc); 46999756Smjacob goto detach; 47099756Smjacob } 47199756Smjacob 47299756Smjacob /* Determine number of Tx/Rx chains. */ 473100680Smjacob if (sc->chip & URTWN_CHIP_92C) { 47499756Smjacob sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 475169292Smjacob sc->nrxchains = 2; 476169292Smjacob } else { 477169292Smjacob sc->ntxchains = 1; 478169292Smjacob sc->nrxchains = 1; 479169292Smjacob } 480100680Smjacob 481169292Smjacob if (sc->chip & URTWN_CHIP_88E) 48299756Smjacob error = urtwn_r88e_read_rom(sc); 48399756Smjacob else 484203444Smjacob error = urtwn_read_rom(sc); 485203444Smjacob if (error != 0) { 48699756Smjacob device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 48799756Smjacob __func__, error); 488100680Smjacob URTWN_UNLOCK(sc); 48999756Smjacob goto detach; 49099756Smjacob } 491203444Smjacob 492203444Smjacob device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 493203444Smjacob (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 494203444Smjacob (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 49599756Smjacob (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 496169292Smjacob (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 497169472Smjacob "8188CUS", sc->ntxchains, sc->nrxchains); 498169292Smjacob 499169292Smjacob URTWN_UNLOCK(sc); 500240717Smjacob 501169292Smjacob ic->ic_softc = sc; 502169292Smjacob ic->ic_name = device_get_nameunit(self); 50399756Smjacob ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 504100680Smjacob ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 505169292Smjacob 50699756Smjacob /* set device capabilities */ 50799756Smjacob ic->ic_caps = 50899756Smjacob IEEE80211_C_STA /* station mode */ 50999756Smjacob | IEEE80211_C_MONITOR /* monitor mode */ 51099756Smjacob | IEEE80211_C_IBSS /* adhoc mode */ 51199756Smjacob | IEEE80211_C_HOSTAP /* hostap mode */ 51299756Smjacob | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 51399756Smjacob | IEEE80211_C_SHSLOT /* short slot time supported */ 514169292Smjacob | IEEE80211_C_BGSCAN /* capable of bg scanning */ 515169292Smjacob | IEEE80211_C_WPA /* 802.11i */ 516242920Smjacob | IEEE80211_C_WME /* 802.11e */ 517196008Smjacob ; 51899756Smjacob 51999756Smjacob ic->ic_cryptocaps = 520169292Smjacob IEEE80211_CRYPTO_WEP | 52199756Smjacob IEEE80211_CRYPTO_TKIP | 522100680Smjacob IEEE80211_CRYPTO_AES_CCM; 52399756Smjacob 52499756Smjacob bands = 0; 52599756Smjacob setbit(&bands, IEEE80211_MODE_11B); 526218691Smarius setbit(&bands, IEEE80211_MODE_11G); 527196008Smjacob ieee80211_init_channels(ic, NULL, &bands); 52899756Smjacob 52999756Smjacob ieee80211_ifattach(ic); 530196008Smjacob ic->ic_raw_xmit = urtwn_raw_xmit; 531169292Smjacob ic->ic_scan_start = urtwn_scan_start; 53299756Smjacob ic->ic_scan_end = urtwn_scan_end; 533100680Smjacob ic->ic_set_channel = urtwn_set_channel; 53499756Smjacob ic->ic_transmit = urtwn_transmit; 53599756Smjacob ic->ic_parent = urtwn_parent; 53699756Smjacob ic->ic_vap_create = urtwn_vap_create; 53799756Smjacob ic->ic_vap_delete = urtwn_vap_delete; 538169292Smjacob ic->ic_wme.wme_update = urtwn_wme_update; 539169292Smjacob ic->ic_update_promisc = urtwn_update_promisc; 54099756Smjacob ic->ic_update_mcast = urtwn_update_mcast; 54199756Smjacob if (sc->chip & URTWN_CHIP_88E) { 54299756Smjacob ic->ic_node_alloc = urtwn_r88e_node_alloc; 54399756Smjacob ic->ic_newassoc = urtwn_r88e_newassoc; 544169292Smjacob sc->sc_node_free = ic->ic_node_free; 545169292Smjacob ic->ic_node_free = urtwn_r88e_node_free; 54699756Smjacob } 54799756Smjacob 54899756Smjacob ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 549196008Smjacob sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 550169292Smjacob &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 551169292Smjacob URTWN_RX_RADIOTAP_PRESENT); 552169292Smjacob 553169292Smjacob TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc); 554169292Smjacob 55599756Smjacob if (bootverbose) 556169292Smjacob ieee80211_announce(ic); 55799756Smjacob 55899756Smjacob return (0); 55999756Smjacob 560196008Smjacobdetach: 56199756Smjacob urtwn_detach(self); 56299756Smjacob return (ENXIO); /* failure */ 56399756Smjacob} 56499756Smjacob 56599756Smjacobstatic int 56699756Smjacoburtwn_detach(device_t self) 56799756Smjacob{ 56899756Smjacob struct urtwn_softc *sc = device_get_softc(self); 569169292Smjacob struct ieee80211com *ic = &sc->sc_ic; 570100680Smjacob unsigned int x; 57199756Smjacob 57299756Smjacob /* Prevent further ioctls. */ 57399756Smjacob URTWN_LOCK(sc); 574196008Smjacob sc->sc_flags |= URTWN_DETACHED; 575196008Smjacob URTWN_UNLOCK(sc); 57699756Smjacob 577169292Smjacob urtwn_stop(sc); 578169292Smjacob 579100680Smjacob callout_drain(&sc->sc_watchdog_ch); 58099756Smjacob 58199756Smjacob /* stop all USB transfers */ 58299756Smjacob usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 58399756Smjacob 584157943Smjacob /* Prevent further allocations from RX/TX data lists. */ 58599756Smjacob URTWN_LOCK(sc); 586196008Smjacob STAILQ_INIT(&sc->sc_tx_active); 587155704Smjacob STAILQ_INIT(&sc->sc_tx_inactive); 588196008Smjacob STAILQ_INIT(&sc->sc_tx_pending); 58999756Smjacob 59099756Smjacob STAILQ_INIT(&sc->sc_rx_active); 59199756Smjacob STAILQ_INIT(&sc->sc_rx_inactive); 59299756Smjacob URTWN_UNLOCK(sc); 59399756Smjacob 59499756Smjacob /* drain USB transfers */ 59599756Smjacob for (x = 0; x != URTWN_N_TRANSFER; x++) 59699756Smjacob usbd_transfer_drain(sc->sc_xfer[x]); 59799756Smjacob 59899756Smjacob /* Free data buffers. */ 599157943Smjacob URTWN_LOCK(sc); 60099756Smjacob urtwn_free_tx_list(sc); 601196008Smjacob urtwn_free_rx_list(sc); 60299756Smjacob URTWN_UNLOCK(sc); 60399756Smjacob 60499756Smjacob if (ic->ic_softc == sc) { 60599756Smjacob ieee80211_draintask(ic, &sc->cmdq_task); 60699756Smjacob ieee80211_ifdetach(ic); 60799756Smjacob } 60899756Smjacob 60999756Smjacob URTWN_NT_LOCK_DESTROY(sc); 61099756Smjacob URTWN_CMDQ_LOCK_DESTROY(sc); 61199756Smjacob mtx_destroy(&sc->sc_mtx); 612196008Smjacob 613196008Smjacob return (0); 614196008Smjacob} 615196008Smjacob 616196008Smjacobstatic void 617196008Smjacoburtwn_drain_mbufq(struct urtwn_softc *sc) 618196008Smjacob{ 619196008Smjacob struct mbuf *m; 620196008Smjacob struct ieee80211_node *ni; 621196008Smjacob URTWN_ASSERT_LOCKED(sc); 62299756Smjacob while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 623196008Smjacob ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 624196008Smjacob m->m_pkthdr.rcvif = NULL; 625196008Smjacob ieee80211_free_node(ni); 62699756Smjacob m_freem(m); 62799756Smjacob } 628240022Smjacob} 629196008Smjacob 63099756Smjacobstatic usb_error_t 63199756Smjacoburtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 63299756Smjacob void *data) 63399756Smjacob{ 634196008Smjacob usb_error_t err; 63599756Smjacob int ntries = 10; 63699756Smjacob 63799756Smjacob URTWN_ASSERT_LOCKED(sc); 638251874Sscottl 63999756Smjacob while (ntries--) { 64099756Smjacob err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 64199756Smjacob req, data, 0, NULL, 250 /* ms */); 64299756Smjacob if (err == 0) 643196008Smjacob break; 64499756Smjacob 645196008Smjacob DPRINTFN(1, "Control request failed, %s (retrying)\n", 64699756Smjacob usbd_errstr(err)); 647196008Smjacob usb_pause_mtx(&sc->sc_mtx, hz / 100); 648196008Smjacob } 649251874Sscottl return (err); 650251874Sscottl} 651251874Sscottl 652251874Sscottlstatic struct ieee80211vap * 653251874Sscottlurtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 654251874Sscottl enum ieee80211_opmode opmode, int flags, 655251874Sscottl const uint8_t bssid[IEEE80211_ADDR_LEN], 656251874Sscottl const uint8_t mac[IEEE80211_ADDR_LEN]) 65799756Smjacob{ 658251874Sscottl struct urtwn_softc *sc = ic->ic_softc; 65999756Smjacob struct urtwn_vap *uvp; 660251874Sscottl struct ieee80211vap *vap; 66199756Smjacob 66299756Smjacob if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 66399756Smjacob return (NULL); 66499756Smjacob 66599756Smjacob uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 66699756Smjacob vap = &uvp->vap; 66799756Smjacob /* enable s/w bmiss handling for sta mode */ 66899756Smjacob 66999756Smjacob if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 67099756Smjacob flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 67199756Smjacob /* out of memory */ 67299756Smjacob free(uvp, M_80211_VAP); 67399756Smjacob return (NULL); 67499756Smjacob } 67599756Smjacob 67699756Smjacob if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 67799756Smjacob urtwn_init_beacon(sc, uvp); 67899756Smjacob 679165269Smjacob /* override state transition machine */ 680165269Smjacob uvp->newstate = vap->iv_newstate; 681165269Smjacob vap->iv_newstate = urtwn_newstate; 682165269Smjacob vap->iv_update_beacon = urtwn_update_beacon; 683165269Smjacob vap->iv_key_alloc = urtwn_key_alloc; 684165269Smjacob vap->iv_key_set = urtwn_key_set; 685157943Smjacob vap->iv_key_delete = urtwn_key_delete; 68699756Smjacob if (opmode == IEEE80211_M_IBSS) { 687163899Smjacob uvp->recv_mgmt = vap->iv_recv_mgmt; 68899756Smjacob vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 68999756Smjacob TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 69099756Smjacob } 691157943Smjacob 69299756Smjacob if (URTWN_CHIP_HAS_RATECTL(sc)) 69399756Smjacob ieee80211_ratectl_init(vap); 69499756Smjacob /* complete setup */ 69599756Smjacob ieee80211_vap_attach(vap, ieee80211_media_change, 69699756Smjacob ieee80211_media_status, mac); 69799756Smjacob ic->ic_opmode = opmode; 69899756Smjacob return (vap); 69999756Smjacob} 70099756Smjacob 70199756Smjacobstatic void 70299756Smjacoburtwn_vap_delete(struct ieee80211vap *vap) 70399756Smjacob{ 70499756Smjacob struct ieee80211com *ic = vap->iv_ic; 70599756Smjacob struct urtwn_softc *sc = ic->ic_softc; 70699756Smjacob struct urtwn_vap *uvp = URTWN_VAP(vap); 70799756Smjacob 70899756Smjacob if (uvp->bcn_mbuf != NULL) 70999756Smjacob m_freem(uvp->bcn_mbuf); 71099756Smjacob if (vap->iv_opmode == IEEE80211_M_IBSS) 71199756Smjacob ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 71299756Smjacob if (URTWN_CHIP_HAS_RATECTL(sc)) 71399756Smjacob ieee80211_ratectl_deinit(vap); 71499756Smjacob ieee80211_vap_detach(vap); 71599756Smjacob free(uvp, M_80211_VAP); 71699756Smjacob} 71799756Smjacob 71899756Smjacobstatic struct mbuf * 71999756Smjacoburtwn_rx_copy_to_mbuf(struct urtwn_softc *sc, struct r92c_rx_stat *stat, 720 int totlen) 721{ 722 struct ieee80211com *ic = &sc->sc_ic; 723 struct mbuf *m; 724 uint32_t rxdw0; 725 int pktlen; 726 727 /* 728 * don't pass packets to the ieee80211 framework if the driver isn't 729 * RUNNING. 730 */ 731 if (!(sc->sc_flags & URTWN_RUNNING)) 732 return (NULL); 733 734 rxdw0 = le32toh(stat->rxdw0); 735 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 736 /* 737 * This should not happen since we setup our Rx filter 738 * to not receive these frames. 739 */ 740 DPRINTFN(6, "RX flags error (%s)\n", 741 rxdw0 & R92C_RXDW0_CRCERR ? "CRC" : "ICV"); 742 goto fail; 743 } 744 745 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 746 if (pktlen < sizeof(struct ieee80211_frame_ack)) { 747 DPRINTFN(6, "frame too short: %d\n", pktlen); 748 goto fail; 749 } 750 751 if (__predict_false(totlen > MCLBYTES)) { 752 /* convert to m_getjcl if this happens */ 753 device_printf(sc->sc_dev, "%s: frame too long: %d (%d)\n", 754 __func__, pktlen, totlen); 755 goto fail; 756 } 757 758 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 759 if (__predict_false(m == NULL)) { 760 device_printf(sc->sc_dev, "%s: could not allocate RX mbuf\n", 761 __func__); 762 goto fail; 763 } 764 765 /* Finalize mbuf. */ 766 memcpy(mtod(m, uint8_t *), (uint8_t *)stat, totlen); 767 m->m_pkthdr.len = m->m_len = totlen; 768 769 return (m); 770fail: 771 counter_u64_add(ic->ic_ierrors, 1); 772 return (NULL); 773} 774 775static struct mbuf * 776urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data) 777{ 778 struct urtwn_softc *sc = data->sc; 779 struct ieee80211com *ic = &sc->sc_ic; 780 struct r92c_rx_stat *stat; 781 uint8_t *buf; 782 int len; 783 784 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 785 786 if (len < sizeof(*stat)) { 787 counter_u64_add(ic->ic_ierrors, 1); 788 return (NULL); 789 } 790 791 buf = data->buf; 792 stat = (struct r92c_rx_stat *)buf; 793 794 if (sc->chip & URTWN_CHIP_88E) { 795 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 796 797 switch (report_sel) { 798 case R88E_RXDW3_RPT_RX: 799 return (urtwn_rxeof(sc, buf, len)); 800 case R88E_RXDW3_RPT_TX1: 801 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 802 break; 803 default: 804 DPRINTFN(7, "case %d was not handled\n", report_sel); 805 break; 806 } 807 } else 808 return (urtwn_rxeof(sc, buf, len)); 809 810 return (NULL); 811} 812 813static struct mbuf * 814urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len) 815{ 816 struct r92c_rx_stat *stat; 817 struct mbuf *m, *m0 = NULL, *prevm = NULL; 818 uint32_t rxdw0; 819 int totlen, pktlen, infosz, npkts; 820 821 /* Get the number of encapsulated frames. */ 822 stat = (struct r92c_rx_stat *)buf; 823 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 824 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 825 826 /* Process all of them. */ 827 while (npkts-- > 0) { 828 if (len < sizeof(*stat)) 829 break; 830 stat = (struct r92c_rx_stat *)buf; 831 rxdw0 = le32toh(stat->rxdw0); 832 833 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 834 if (pktlen == 0) 835 break; 836 837 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 838 839 /* Make sure everything fits in xfer. */ 840 totlen = sizeof(*stat) + infosz + pktlen; 841 if (totlen > len) 842 break; 843 844 m = urtwn_rx_copy_to_mbuf(sc, stat, totlen); 845 if (m0 == NULL) 846 m0 = m; 847 if (prevm == NULL) 848 prevm = m; 849 else { 850 prevm->m_next = m; 851 prevm = m; 852 } 853 854 /* Next chunk is 128-byte aligned. */ 855 totlen = (totlen + 127) & ~127; 856 buf += totlen; 857 len -= totlen; 858 } 859 860 return (m0); 861} 862 863static void 864urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 865{ 866 struct r88e_tx_rpt_ccx *rpt = arg; 867 struct ieee80211vap *vap; 868 struct ieee80211_node *ni; 869 uint8_t macid; 870 int ntries; 871 872 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 873 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 874 875 URTWN_NT_LOCK(sc); 876 ni = sc->node_list[macid]; 877 if (ni != NULL) { 878 vap = ni->ni_vap; 879 880 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 881 ieee80211_ratectl_tx_complete(vap, ni, 882 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 883 } else { 884 ieee80211_ratectl_tx_complete(vap, ni, 885 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 886 } 887 } else 888 DPRINTFN(8, "macid %d, ni is NULL\n", macid); 889 URTWN_NT_UNLOCK(sc); 890} 891 892static struct ieee80211_node * 893urtwn_rx_frame(struct urtwn_softc *sc, struct mbuf *m, int8_t *rssi_p) 894{ 895 struct ieee80211com *ic = &sc->sc_ic; 896 struct ieee80211_frame_min *wh; 897 struct r92c_rx_stat *stat; 898 uint32_t rxdw0, rxdw3; 899 uint8_t rate, cipher; 900 int8_t rssi = URTWN_NOISE_FLOOR + 1; 901 int infosz; 902 903 stat = mtod(m, struct r92c_rx_stat *); 904 rxdw0 = le32toh(stat->rxdw0); 905 rxdw3 = le32toh(stat->rxdw3); 906 907 rate = MS(rxdw3, R92C_RXDW3_RATE); 908 cipher = MS(rxdw0, R92C_RXDW0_CIPHER); 909 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 910 911 /* Get RSSI from PHY status descriptor if present. */ 912 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 913 if (sc->chip & URTWN_CHIP_88E) 914 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 915 else 916 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 917 /* Update our average RSSI. */ 918 urtwn_update_avgrssi(sc, rate, rssi); 919 } 920 921 if (ieee80211_radiotap_active(ic)) { 922 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 923 924 tap->wr_flags = 0; 925 926 urtwn_get_tsf(sc, &tap->wr_tsft); 927 if (__predict_false(le32toh((uint32_t)tap->wr_tsft) < 928 le32toh(stat->rxdw5))) { 929 tap->wr_tsft = le32toh(tap->wr_tsft >> 32) - 1; 930 tap->wr_tsft = (uint64_t)htole32(tap->wr_tsft) << 32; 931 } else 932 tap->wr_tsft &= 0xffffffff00000000; 933 tap->wr_tsft += stat->rxdw5; 934 935 /* Map HW rate index to 802.11 rate. */ 936 if (!(rxdw3 & R92C_RXDW3_HT)) { 937 tap->wr_rate = ridx2rate[rate]; 938 } else if (rate >= 12) { /* MCS0~15. */ 939 /* Bit 7 set means HT MCS instead of rate. */ 940 tap->wr_rate = 0x80 | (rate - 12); 941 } 942 tap->wr_dbm_antsignal = rssi; 943 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 944 } 945 946 *rssi_p = rssi; 947 948 /* Drop descriptor. */ 949 m_adj(m, sizeof(*stat) + infosz); 950 wh = mtod(m, struct ieee80211_frame_min *); 951 952 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 953 cipher != R92C_CAM_ALGO_NONE) { 954 m->m_flags |= M_WEP; 955 } 956 957 if (m->m_len >= sizeof(*wh)) 958 return (ieee80211_find_rxnode(ic, wh)); 959 960 return (NULL); 961} 962 963static void 964urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 965{ 966 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 967 struct ieee80211com *ic = &sc->sc_ic; 968 struct ieee80211_node *ni; 969 struct mbuf *m = NULL, *next; 970 struct urtwn_data *data; 971 int8_t nf, rssi; 972 973 URTWN_ASSERT_LOCKED(sc); 974 975 switch (USB_GET_STATE(xfer)) { 976 case USB_ST_TRANSFERRED: 977 data = STAILQ_FIRST(&sc->sc_rx_active); 978 if (data == NULL) 979 goto tr_setup; 980 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 981 m = urtwn_report_intr(xfer, data); 982 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 983 /* FALLTHROUGH */ 984 case USB_ST_SETUP: 985tr_setup: 986 data = STAILQ_FIRST(&sc->sc_rx_inactive); 987 if (data == NULL) { 988 KASSERT(m == NULL, ("mbuf isn't NULL")); 989 return; 990 } 991 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 992 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 993 usbd_xfer_set_frame_data(xfer, 0, data->buf, 994 usbd_xfer_max_len(xfer)); 995 usbd_transfer_submit(xfer); 996 997 /* 998 * To avoid LOR we should unlock our private mutex here to call 999 * ieee80211_input() because here is at the end of a USB 1000 * callback and safe to unlock. 1001 */ 1002 while (m != NULL) { 1003 next = m->m_next; 1004 m->m_next = NULL; 1005 1006 ni = urtwn_rx_frame(sc, m, &rssi); 1007 URTWN_UNLOCK(sc); 1008 1009 nf = URTWN_NOISE_FLOOR; 1010 if (ni != NULL) { 1011 (void)ieee80211_input(ni, m, rssi - nf, nf); 1012 ieee80211_free_node(ni); 1013 } else { 1014 (void)ieee80211_input_all(ic, m, rssi - nf, 1015 nf); 1016 } 1017 1018 URTWN_LOCK(sc); 1019 m = next; 1020 } 1021 break; 1022 default: 1023 /* needs it to the inactive queue due to a error. */ 1024 data = STAILQ_FIRST(&sc->sc_rx_active); 1025 if (data != NULL) { 1026 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1027 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1028 } 1029 if (error != USB_ERR_CANCELLED) { 1030 usbd_xfer_set_stall(xfer); 1031 counter_u64_add(ic->ic_ierrors, 1); 1032 goto tr_setup; 1033 } 1034 break; 1035 } 1036} 1037 1038static void 1039urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 1040{ 1041 1042 URTWN_ASSERT_LOCKED(sc); 1043 1044 if (data->ni != NULL) /* not a beacon frame */ 1045 ieee80211_tx_complete(data->ni, data->m, status); 1046 1047 data->ni = NULL; 1048 data->m = NULL; 1049 1050 sc->sc_txtimer = 0; 1051 1052 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 1053} 1054 1055static int 1056urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1057 int ndata, int maxsz) 1058{ 1059 int i, error; 1060 1061 for (i = 0; i < ndata; i++) { 1062 struct urtwn_data *dp = &data[i]; 1063 dp->sc = sc; 1064 dp->m = NULL; 1065 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1066 if (dp->buf == NULL) { 1067 device_printf(sc->sc_dev, 1068 "could not allocate buffer\n"); 1069 error = ENOMEM; 1070 goto fail; 1071 } 1072 dp->ni = NULL; 1073 } 1074 1075 return (0); 1076fail: 1077 urtwn_free_list(sc, data, ndata); 1078 return (error); 1079} 1080 1081static int 1082urtwn_alloc_rx_list(struct urtwn_softc *sc) 1083{ 1084 int error, i; 1085 1086 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1087 URTWN_RXBUFSZ); 1088 if (error != 0) 1089 return (error); 1090 1091 STAILQ_INIT(&sc->sc_rx_active); 1092 STAILQ_INIT(&sc->sc_rx_inactive); 1093 1094 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1095 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1096 1097 return (0); 1098} 1099 1100static int 1101urtwn_alloc_tx_list(struct urtwn_softc *sc) 1102{ 1103 int error, i; 1104 1105 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1106 URTWN_TXBUFSZ); 1107 if (error != 0) 1108 return (error); 1109 1110 STAILQ_INIT(&sc->sc_tx_active); 1111 STAILQ_INIT(&sc->sc_tx_inactive); 1112 STAILQ_INIT(&sc->sc_tx_pending); 1113 1114 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1115 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1116 1117 return (0); 1118} 1119 1120static void 1121urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1122{ 1123 int i; 1124 1125 for (i = 0; i < ndata; i++) { 1126 struct urtwn_data *dp = &data[i]; 1127 1128 if (dp->buf != NULL) { 1129 free(dp->buf, M_USBDEV); 1130 dp->buf = NULL; 1131 } 1132 if (dp->ni != NULL) { 1133 ieee80211_free_node(dp->ni); 1134 dp->ni = NULL; 1135 } 1136 } 1137} 1138 1139static void 1140urtwn_free_rx_list(struct urtwn_softc *sc) 1141{ 1142 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1143} 1144 1145static void 1146urtwn_free_tx_list(struct urtwn_softc *sc) 1147{ 1148 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1149} 1150 1151static void 1152urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1153{ 1154 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1155 struct urtwn_data *data; 1156 1157 URTWN_ASSERT_LOCKED(sc); 1158 1159 switch (USB_GET_STATE(xfer)){ 1160 case USB_ST_TRANSFERRED: 1161 data = STAILQ_FIRST(&sc->sc_tx_active); 1162 if (data == NULL) 1163 goto tr_setup; 1164 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1165 urtwn_txeof(sc, data, 0); 1166 /* FALLTHROUGH */ 1167 case USB_ST_SETUP: 1168tr_setup: 1169 data = STAILQ_FIRST(&sc->sc_tx_pending); 1170 if (data == NULL) { 1171 DPRINTF("%s: empty pending queue\n", __func__); 1172 goto finish; 1173 } 1174 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1175 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1176 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1177 usbd_transfer_submit(xfer); 1178 break; 1179 default: 1180 data = STAILQ_FIRST(&sc->sc_tx_active); 1181 if (data == NULL) 1182 goto tr_setup; 1183 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1184 urtwn_txeof(sc, data, 1); 1185 if (error != USB_ERR_CANCELLED) { 1186 usbd_xfer_set_stall(xfer); 1187 goto tr_setup; 1188 } 1189 break; 1190 } 1191finish: 1192 /* Kick-start more transmit */ 1193 urtwn_start(sc); 1194} 1195 1196static struct urtwn_data * 1197_urtwn_getbuf(struct urtwn_softc *sc) 1198{ 1199 struct urtwn_data *bf; 1200 1201 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1202 if (bf != NULL) 1203 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1204 else 1205 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 1206 return (bf); 1207} 1208 1209static struct urtwn_data * 1210urtwn_getbuf(struct urtwn_softc *sc) 1211{ 1212 struct urtwn_data *bf; 1213 1214 URTWN_ASSERT_LOCKED(sc); 1215 1216 bf = _urtwn_getbuf(sc); 1217 if (bf == NULL) 1218 DPRINTF("%s: stop queue\n", __func__); 1219 return (bf); 1220} 1221 1222static usb_error_t 1223urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1224 int len) 1225{ 1226 usb_device_request_t req; 1227 1228 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1229 req.bRequest = R92C_REQ_REGS; 1230 USETW(req.wValue, addr); 1231 USETW(req.wIndex, 0); 1232 USETW(req.wLength, len); 1233 return (urtwn_do_request(sc, &req, buf)); 1234} 1235 1236static usb_error_t 1237urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1238{ 1239 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1240} 1241 1242static usb_error_t 1243urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1244{ 1245 val = htole16(val); 1246 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1247} 1248 1249static usb_error_t 1250urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1251{ 1252 val = htole32(val); 1253 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1254} 1255 1256static usb_error_t 1257urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1258 int len) 1259{ 1260 usb_device_request_t req; 1261 1262 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1263 req.bRequest = R92C_REQ_REGS; 1264 USETW(req.wValue, addr); 1265 USETW(req.wIndex, 0); 1266 USETW(req.wLength, len); 1267 return (urtwn_do_request(sc, &req, buf)); 1268} 1269 1270static uint8_t 1271urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1272{ 1273 uint8_t val; 1274 1275 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1276 return (0xff); 1277 return (val); 1278} 1279 1280static uint16_t 1281urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1282{ 1283 uint16_t val; 1284 1285 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1286 return (0xffff); 1287 return (le16toh(val)); 1288} 1289 1290static uint32_t 1291urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1292{ 1293 uint32_t val; 1294 1295 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1296 return (0xffffffff); 1297 return (le32toh(val)); 1298} 1299 1300static int 1301urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1302{ 1303 struct r92c_fw_cmd cmd; 1304 usb_error_t error; 1305 int ntries; 1306 1307 /* Wait for current FW box to be empty. */ 1308 for (ntries = 0; ntries < 100; ntries++) { 1309 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1310 break; 1311 urtwn_ms_delay(sc); 1312 } 1313 if (ntries == 100) { 1314 device_printf(sc->sc_dev, 1315 "could not send firmware command\n"); 1316 return (ETIMEDOUT); 1317 } 1318 memset(&cmd, 0, sizeof(cmd)); 1319 cmd.id = id; 1320 if (len > 3) 1321 cmd.id |= R92C_CMD_FLAG_EXT; 1322 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1323 memcpy(cmd.msg, buf, len); 1324 1325 /* Write the first word last since that will trigger the FW. */ 1326 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1327 (uint8_t *)&cmd + 4, 2); 1328 if (error != USB_ERR_NORMAL_COMPLETION) 1329 return (EIO); 1330 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1331 (uint8_t *)&cmd + 0, 4); 1332 if (error != USB_ERR_NORMAL_COMPLETION) 1333 return (EIO); 1334 1335 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1336 return (0); 1337} 1338 1339static void 1340urtwn_cmdq_cb(void *arg, int pending) 1341{ 1342 struct urtwn_softc *sc = arg; 1343 struct urtwn_cmdq *item; 1344 1345 /* 1346 * Device must be powered on (via urtwn_power_on()) 1347 * before any command may be sent. 1348 */ 1349 URTWN_LOCK(sc); 1350 if (!(sc->sc_flags & URTWN_RUNNING)) { 1351 URTWN_UNLOCK(sc); 1352 return; 1353 } 1354 1355 URTWN_CMDQ_LOCK(sc); 1356 while (sc->cmdq[sc->cmdq_first].func != NULL) { 1357 item = &sc->cmdq[sc->cmdq_first]; 1358 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE; 1359 URTWN_CMDQ_UNLOCK(sc); 1360 1361 item->func(sc, &item->data); 1362 1363 URTWN_CMDQ_LOCK(sc); 1364 memset(item, 0, sizeof (*item)); 1365 } 1366 URTWN_CMDQ_UNLOCK(sc); 1367 URTWN_UNLOCK(sc); 1368} 1369 1370static int 1371urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len, 1372 CMD_FUNC_PROTO) 1373{ 1374 struct ieee80211com *ic = &sc->sc_ic; 1375 1376 KASSERT(len <= sizeof(union sec_param), ("buffer overflow")); 1377 1378 URTWN_CMDQ_LOCK(sc); 1379 if (sc->cmdq[sc->cmdq_last].func != NULL) { 1380 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__); 1381 URTWN_CMDQ_UNLOCK(sc); 1382 1383 return (EAGAIN); 1384 } 1385 1386 if (ptr != NULL) 1387 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len); 1388 sc->cmdq[sc->cmdq_last].func = func; 1389 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE; 1390 URTWN_CMDQ_UNLOCK(sc); 1391 1392 ieee80211_runtask(ic, &sc->cmdq_task); 1393 1394 return (0); 1395} 1396 1397static __inline void 1398urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1399{ 1400 1401 sc->sc_rf_write(sc, chain, addr, val); 1402} 1403 1404static void 1405urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1406 uint32_t val) 1407{ 1408 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1409 SM(R92C_LSSI_PARAM_ADDR, addr) | 1410 SM(R92C_LSSI_PARAM_DATA, val)); 1411} 1412 1413static void 1414urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1415uint32_t val) 1416{ 1417 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1418 SM(R88E_LSSI_PARAM_ADDR, addr) | 1419 SM(R92C_LSSI_PARAM_DATA, val)); 1420} 1421 1422static uint32_t 1423urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1424{ 1425 uint32_t reg[R92C_MAX_CHAINS], val; 1426 1427 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1428 if (chain != 0) 1429 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1430 1431 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1432 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1433 urtwn_ms_delay(sc); 1434 1435 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1436 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1437 R92C_HSSI_PARAM2_READ_EDGE); 1438 urtwn_ms_delay(sc); 1439 1440 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1441 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1442 urtwn_ms_delay(sc); 1443 1444 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1445 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1446 else 1447 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1448 return (MS(val, R92C_LSSI_READBACK_DATA)); 1449} 1450 1451static int 1452urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1453{ 1454 usb_error_t error; 1455 int ntries; 1456 1457 error = urtwn_write_4(sc, R92C_LLT_INIT, 1458 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1459 SM(R92C_LLT_INIT_ADDR, addr) | 1460 SM(R92C_LLT_INIT_DATA, data)); 1461 if (error != USB_ERR_NORMAL_COMPLETION) 1462 return (EIO); 1463 /* Wait for write operation to complete. */ 1464 for (ntries = 0; ntries < 20; ntries++) { 1465 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1466 R92C_LLT_INIT_OP_NO_ACTIVE) 1467 return (0); 1468 urtwn_ms_delay(sc); 1469 } 1470 return (ETIMEDOUT); 1471} 1472 1473static int 1474urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1475{ 1476 uint32_t reg; 1477 usb_error_t error; 1478 int ntries; 1479 1480 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1481 return (EFAULT); 1482 1483 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1484 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1485 reg &= ~R92C_EFUSE_CTRL_VALID; 1486 1487 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1488 if (error != USB_ERR_NORMAL_COMPLETION) 1489 return (EIO); 1490 /* Wait for read operation to complete. */ 1491 for (ntries = 0; ntries < 100; ntries++) { 1492 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1493 if (reg & R92C_EFUSE_CTRL_VALID) 1494 break; 1495 urtwn_ms_delay(sc); 1496 } 1497 if (ntries == 100) { 1498 device_printf(sc->sc_dev, 1499 "could not read efuse byte at address 0x%x\n", 1500 sc->last_rom_addr); 1501 return (ETIMEDOUT); 1502 } 1503 1504 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1505 sc->last_rom_addr++; 1506 1507 return (0); 1508} 1509 1510static int 1511urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1512 uint8_t msk) 1513{ 1514 uint8_t reg; 1515 int i, error; 1516 1517 for (i = 0; i < 4; i++) { 1518 if (msk & (1 << i)) 1519 continue; 1520 error = urtwn_efuse_read_next(sc, ®); 1521 if (error != 0) 1522 return (error); 1523 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2, reg); 1524 rom[off * 8 + i * 2 + 0] = reg; 1525 1526 error = urtwn_efuse_read_next(sc, ®); 1527 if (error != 0) 1528 return (error); 1529 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2 + 1, reg); 1530 rom[off * 8 + i * 2 + 1] = reg; 1531 } 1532 1533 return (0); 1534} 1535 1536#ifdef URTWN_DEBUG 1537static void 1538urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1539{ 1540 int i; 1541 1542 /* Dump ROM contents. */ 1543 device_printf(sc->sc_dev, "%s:", __func__); 1544 for (i = 0; i < size; i++) { 1545 if (i % 32 == 0) 1546 printf("\n%03X: ", i); 1547 else if (i % 4 == 0) 1548 printf(" "); 1549 1550 printf("%02X", rom[i]); 1551 } 1552 printf("\n"); 1553} 1554#endif 1555 1556static int 1557urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1558{ 1559#define URTWN_CHK(res) do { \ 1560 if ((error = res) != 0) \ 1561 goto end; \ 1562} while(0) 1563 uint8_t msk, off, reg; 1564 int error; 1565 1566 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1567 1568 /* Read full ROM image. */ 1569 sc->last_rom_addr = 0; 1570 memset(rom, 0xff, size); 1571 1572 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1573 while (reg != 0xff) { 1574 /* check for extended header */ 1575 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1576 off = reg >> 5; 1577 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1578 1579 if ((reg & 0x0f) != 0x0f) 1580 off = ((reg & 0xf0) >> 1) | off; 1581 else 1582 continue; 1583 } else 1584 off = reg >> 4; 1585 msk = reg & 0xf; 1586 1587 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1588 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1589 } 1590 1591end: 1592 1593#ifdef URTWN_DEBUG 1594 if (urtwn_debug >= 2) 1595 urtwn_dump_rom_contents(sc, rom, size); 1596#endif 1597 1598 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1599 1600 if (error != 0) { 1601 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1602 __func__); 1603 } 1604 1605 return (error); 1606#undef URTWN_CHK 1607} 1608 1609static int 1610urtwn_efuse_switch_power(struct urtwn_softc *sc) 1611{ 1612 usb_error_t error; 1613 uint32_t reg; 1614 1615 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1616 if (error != USB_ERR_NORMAL_COMPLETION) 1617 return (EIO); 1618 1619 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1620 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1621 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1622 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1623 if (error != USB_ERR_NORMAL_COMPLETION) 1624 return (EIO); 1625 } 1626 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1627 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1628 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1629 reg | R92C_SYS_FUNC_EN_ELDR); 1630 if (error != USB_ERR_NORMAL_COMPLETION) 1631 return (EIO); 1632 } 1633 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1634 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1635 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1636 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1637 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1638 if (error != USB_ERR_NORMAL_COMPLETION) 1639 return (EIO); 1640 } 1641 1642 return (0); 1643} 1644 1645static int 1646urtwn_read_chipid(struct urtwn_softc *sc) 1647{ 1648 uint32_t reg; 1649 1650 if (sc->chip & URTWN_CHIP_88E) 1651 return (0); 1652 1653 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1654 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1655 return (EIO); 1656 1657 if (reg & R92C_SYS_CFG_TYPE_92C) { 1658 sc->chip |= URTWN_CHIP_92C; 1659 /* Check if it is a castrated 8192C. */ 1660 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1661 R92C_HPON_FSM_CHIP_BONDING_ID) == 1662 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1663 sc->chip |= URTWN_CHIP_92C_1T2R; 1664 } 1665 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1666 sc->chip |= URTWN_CHIP_UMC; 1667 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1668 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1669 } 1670 return (0); 1671} 1672 1673static int 1674urtwn_read_rom(struct urtwn_softc *sc) 1675{ 1676 struct r92c_rom *rom = &sc->rom.r92c_rom; 1677 int error; 1678 1679 /* Read full ROM image. */ 1680 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1681 if (error != 0) 1682 return (error); 1683 1684 /* XXX Weird but this is what the vendor driver does. */ 1685 sc->last_rom_addr = 0x1fa; 1686 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1687 if (error != 0) 1688 return (error); 1689 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1690 1691 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1692 1693 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1694 DPRINTF("regulatory type=%d\n", sc->regulatory); 1695 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1696 1697 sc->sc_rf_write = urtwn_r92c_rf_write; 1698 sc->sc_power_on = urtwn_r92c_power_on; 1699 1700 return (0); 1701} 1702 1703static int 1704urtwn_r88e_read_rom(struct urtwn_softc *sc) 1705{ 1706 uint8_t *rom = sc->rom.r88e_rom; 1707 uint16_t addr; 1708 int error, i; 1709 1710 error = urtwn_efuse_read(sc, rom, sizeof(sc->rom.r88e_rom)); 1711 if (error != 0) 1712 return (error); 1713 1714 addr = 0x10; 1715 for (i = 0; i < 6; i++) 1716 sc->cck_tx_pwr[i] = rom[addr++]; 1717 for (i = 0; i < 5; i++) 1718 sc->ht40_tx_pwr[i] = rom[addr++]; 1719 sc->bw20_tx_pwr_diff = (rom[addr] & 0xf0) >> 4; 1720 if (sc->bw20_tx_pwr_diff & 0x08) 1721 sc->bw20_tx_pwr_diff |= 0xf0; 1722 sc->ofdm_tx_pwr_diff = (rom[addr] & 0xf); 1723 if (sc->ofdm_tx_pwr_diff & 0x08) 1724 sc->ofdm_tx_pwr_diff |= 0xf0; 1725 sc->regulatory = MS(rom[0xc1], R92C_ROM_RF1_REGULATORY); 1726 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &rom[0xd7]); 1727 1728 sc->sc_rf_write = urtwn_r88e_rf_write; 1729 sc->sc_power_on = urtwn_r88e_power_on; 1730 1731 return (0); 1732} 1733 1734/* 1735 * Initialize rate adaptation in firmware. 1736 */ 1737static int 1738urtwn_ra_init(struct urtwn_softc *sc) 1739{ 1740 struct ieee80211com *ic = &sc->sc_ic; 1741 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1742 struct ieee80211_node *ni; 1743 struct ieee80211_rateset *rs; 1744 struct r92c_fw_cmd_macid_cfg cmd; 1745 uint32_t rates, basicrates; 1746 uint8_t mode; 1747 int maxrate, maxbasicrate, error, i, j; 1748 1749 ni = ieee80211_ref_node(vap->iv_bss); 1750 rs = &ni->ni_rates; 1751 1752 /* Get normal and basic rates mask. */ 1753 rates = basicrates = 0; 1754 maxrate = maxbasicrate = 0; 1755 for (i = 0; i < rs->rs_nrates; i++) { 1756 /* Convert 802.11 rate to HW rate index. */ 1757 for (j = 0; j < nitems(ridx2rate); j++) 1758 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1759 ridx2rate[j]) 1760 break; 1761 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1762 continue; 1763 rates |= 1 << j; 1764 if (j > maxrate) 1765 maxrate = j; 1766 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1767 basicrates |= 1 << j; 1768 if (j > maxbasicrate) 1769 maxbasicrate = j; 1770 } 1771 } 1772 if (ic->ic_curmode == IEEE80211_MODE_11B) 1773 mode = R92C_RAID_11B; 1774 else 1775 mode = R92C_RAID_11BG; 1776 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1777 mode, rates, basicrates); 1778 1779 /* Set rates mask for group addressed frames. */ 1780 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1781 cmd.mask = htole32(mode << 28 | basicrates); 1782 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1783 if (error != 0) { 1784 ieee80211_free_node(ni); 1785 device_printf(sc->sc_dev, 1786 "could not add broadcast station\n"); 1787 return (error); 1788 } 1789 /* Set initial MRR rate. */ 1790 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1791 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1792 maxbasicrate); 1793 1794 /* Set rates mask for unicast frames. */ 1795 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1796 cmd.mask = htole32(mode << 28 | rates); 1797 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1798 if (error != 0) { 1799 ieee80211_free_node(ni); 1800 device_printf(sc->sc_dev, "could not add BSS station\n"); 1801 return (error); 1802 } 1803 /* Set initial MRR rate. */ 1804 DPRINTF("maxrate=%d\n", maxrate); 1805 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1806 maxrate); 1807 1808 /* Indicate highest supported rate. */ 1809 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1810 ieee80211_free_node(ni); 1811 1812 return (0); 1813} 1814 1815static void 1816urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1817{ 1818 struct r92c_tx_desc *txd = &uvp->bcn_desc; 1819 1820 txd->txdw0 = htole32( 1821 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 1822 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1823 txd->txdw1 = htole32( 1824 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 1825 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1826 1827 if (sc->chip & URTWN_CHIP_88E) { 1828 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 1829 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 1830 } else { 1831 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 1832 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 1833 } 1834 1835 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 1836 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 1837} 1838 1839static int 1840urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 1841{ 1842 struct ieee80211vap *vap = ni->ni_vap; 1843 struct urtwn_vap *uvp = URTWN_VAP(vap); 1844 struct mbuf *m; 1845 int error; 1846 1847 URTWN_ASSERT_LOCKED(sc); 1848 1849 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 1850 return (EINVAL); 1851 1852 m = ieee80211_beacon_alloc(ni); 1853 if (m == NULL) { 1854 device_printf(sc->sc_dev, 1855 "%s: could not allocate beacon frame\n", __func__); 1856 return (ENOMEM); 1857 } 1858 1859 if (uvp->bcn_mbuf != NULL) 1860 m_freem(uvp->bcn_mbuf); 1861 1862 uvp->bcn_mbuf = m; 1863 1864 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1865 return (error); 1866 1867 /* XXX bcnq stuck workaround */ 1868 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1869 return (error); 1870 1871 return (0); 1872} 1873 1874static void 1875urtwn_update_beacon(struct ieee80211vap *vap, int item) 1876{ 1877 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1878 struct urtwn_vap *uvp = URTWN_VAP(vap); 1879 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 1880 struct ieee80211_node *ni = vap->iv_bss; 1881 int mcast = 0; 1882 1883 URTWN_LOCK(sc); 1884 if (uvp->bcn_mbuf == NULL) { 1885 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 1886 if (uvp->bcn_mbuf == NULL) { 1887 device_printf(sc->sc_dev, 1888 "%s: could not allocate beacon frame\n", __func__); 1889 URTWN_UNLOCK(sc); 1890 return; 1891 } 1892 } 1893 URTWN_UNLOCK(sc); 1894 1895 if (item == IEEE80211_BEACON_TIM) 1896 mcast = 1; /* XXX */ 1897 1898 setbit(bo->bo_flags, item); 1899 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 1900 1901 URTWN_LOCK(sc); 1902 urtwn_tx_beacon(sc, uvp); 1903 URTWN_UNLOCK(sc); 1904} 1905 1906/* 1907 * Push a beacon frame into the chip. Beacon will 1908 * be repeated by the chip every R92C_BCN_INTERVAL. 1909 */ 1910static int 1911urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1912{ 1913 struct r92c_tx_desc *desc = &uvp->bcn_desc; 1914 struct urtwn_data *bf; 1915 1916 URTWN_ASSERT_LOCKED(sc); 1917 1918 bf = urtwn_getbuf(sc); 1919 if (bf == NULL) 1920 return (ENOMEM); 1921 1922 memcpy(bf->buf, desc, sizeof(*desc)); 1923 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 1924 1925 sc->sc_txtimer = 5; 1926 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1927 1928 return (0); 1929} 1930 1931static int 1932urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 1933 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1934{ 1935 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1936 uint8_t i; 1937 1938 if (!(&vap->iv_nw_keys[0] <= k && 1939 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 1940 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 1941 URTWN_LOCK(sc); 1942 /* 1943 * First 4 slots for group keys, 1944 * what is left - for pairwise. 1945 * XXX incompatible with IBSS RSN. 1946 */ 1947 for (i = IEEE80211_WEP_NKID; 1948 i < R92C_CAM_ENTRY_COUNT; i++) { 1949 if ((sc->keys_bmap & (1 << i)) == 0) { 1950 sc->keys_bmap |= 1 << i; 1951 *keyix = i; 1952 break; 1953 } 1954 } 1955 URTWN_UNLOCK(sc); 1956 if (i == R92C_CAM_ENTRY_COUNT) { 1957 device_printf(sc->sc_dev, 1958 "%s: no free space in the key table\n", 1959 __func__); 1960 return 0; 1961 } 1962 } else 1963 *keyix = 0; 1964 } else { 1965 *keyix = k - vap->iv_nw_keys; 1966 } 1967 *rxkeyix = *keyix; 1968 return 1; 1969} 1970 1971static void 1972urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data) 1973{ 1974 struct ieee80211_key *k = &data->key; 1975 uint8_t algo, keyid; 1976 int i, error; 1977 1978 if (k->wk_keyix < IEEE80211_WEP_NKID) 1979 keyid = k->wk_keyix; 1980 else 1981 keyid = 0; 1982 1983 /* Map net80211 cipher to HW crypto algorithm. */ 1984 switch (k->wk_cipher->ic_cipher) { 1985 case IEEE80211_CIPHER_WEP: 1986 if (k->wk_keylen < 8) 1987 algo = R92C_CAM_ALGO_WEP40; 1988 else 1989 algo = R92C_CAM_ALGO_WEP104; 1990 break; 1991 case IEEE80211_CIPHER_TKIP: 1992 algo = R92C_CAM_ALGO_TKIP; 1993 break; 1994 case IEEE80211_CIPHER_AES_CCM: 1995 algo = R92C_CAM_ALGO_AES; 1996 break; 1997 default: 1998 device_printf(sc->sc_dev, "%s: undefined cipher %d\n", 1999 __func__, k->wk_cipher->ic_cipher); 2000 return; 2001 } 2002 2003 DPRINTFN(9, "keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, " 2004 "macaddr %s\n", k->wk_keyix, keyid, k->wk_cipher->ic_cipher, algo, 2005 k->wk_flags, k->wk_keylen, ether_sprintf(k->wk_macaddr)); 2006 2007 /* Write key. */ 2008 for (i = 0; i < 4; i++) { 2009 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 2010 LE_READ_4(&k->wk_key[i * 4])); 2011 if (error != 0) 2012 goto fail; 2013 } 2014 2015 /* Write CTL0 last since that will validate the CAM entry. */ 2016 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 2017 LE_READ_4(&k->wk_macaddr[2])); 2018 if (error != 0) 2019 goto fail; 2020 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 2021 SM(R92C_CAM_ALGO, algo) | 2022 SM(R92C_CAM_KEYID, keyid) | 2023 SM(R92C_CAM_MACLO, LE_READ_2(&k->wk_macaddr[0])) | 2024 R92C_CAM_VALID); 2025 if (error != 0) 2026 goto fail; 2027 2028 return; 2029 2030fail: 2031 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error); 2032} 2033 2034static void 2035urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data) 2036{ 2037 struct ieee80211_key *k = &data->key; 2038 int i; 2039 2040 DPRINTFN(9, "keyix %d, flags %04X, macaddr %s\n", 2041 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr)); 2042 2043 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0); 2044 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0); 2045 2046 /* Clear key. */ 2047 for (i = 0; i < 4; i++) 2048 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0); 2049 sc->keys_bmap &= ~(1 << k->wk_keyix); 2050} 2051 2052static int 2053urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 2054{ 2055 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2056 2057 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2058 /* Not for us. */ 2059 return (1); 2060 } 2061 2062 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb)); 2063} 2064 2065static int 2066urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2067{ 2068 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2069 2070 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2071 /* Not for us. */ 2072 return (1); 2073 } 2074 2075 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb)); 2076} 2077 2078static void 2079urtwn_tsf_task_adhoc(void *arg, int pending) 2080{ 2081 struct ieee80211vap *vap = arg; 2082 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2083 struct ieee80211_node *ni; 2084 uint32_t reg; 2085 2086 URTWN_LOCK(sc); 2087 ni = ieee80211_ref_node(vap->iv_bss); 2088 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 2089 2090 /* Accept beacons with the same BSSID. */ 2091 urtwn_set_rx_bssid_all(sc, 0); 2092 2093 /* Enable synchronization. */ 2094 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 2095 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2096 2097 /* Synchronize. */ 2098 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 2099 2100 /* Disable synchronization. */ 2101 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 2102 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2103 2104 /* Remove beacon filter. */ 2105 urtwn_set_rx_bssid_all(sc, 1); 2106 2107 /* Enable beaconing. */ 2108 urtwn_write_1(sc, R92C_MBID_NUM, 2109 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2110 reg |= R92C_BCN_CTRL_EN_BCN; 2111 2112 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2113 ieee80211_free_node(ni); 2114 URTWN_UNLOCK(sc); 2115} 2116 2117static void 2118urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 2119{ 2120 struct ieee80211com *ic = &sc->sc_ic; 2121 struct urtwn_vap *uvp = URTWN_VAP(vap); 2122 2123 /* Reset TSF. */ 2124 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2125 2126 switch (vap->iv_opmode) { 2127 case IEEE80211_M_STA: 2128 /* Enable TSF synchronization. */ 2129 urtwn_write_1(sc, R92C_BCN_CTRL, 2130 urtwn_read_1(sc, R92C_BCN_CTRL) & 2131 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 2132 break; 2133 case IEEE80211_M_IBSS: 2134 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 2135 break; 2136 case IEEE80211_M_HOSTAP: 2137 /* Enable beaconing. */ 2138 urtwn_write_1(sc, R92C_MBID_NUM, 2139 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2140 urtwn_write_1(sc, R92C_BCN_CTRL, 2141 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 2142 break; 2143 default: 2144 device_printf(sc->sc_dev, "undefined opmode %d\n", 2145 vap->iv_opmode); 2146 return; 2147 } 2148} 2149 2150static void 2151urtwn_get_tsf(struct urtwn_softc *sc, uint64_t *buf) 2152{ 2153 urtwn_read_region_1(sc, R92C_TSFTR, (uint8_t *)buf, sizeof(*buf)); 2154} 2155 2156static void 2157urtwn_set_led(struct urtwn_softc *sc, int led, int on) 2158{ 2159 uint8_t reg; 2160 2161 if (led == URTWN_LED_LINK) { 2162 if (sc->chip & URTWN_CHIP_88E) { 2163 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 2164 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 2165 if (!on) { 2166 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 2167 urtwn_write_1(sc, R92C_LEDCFG2, 2168 reg | R92C_LEDCFG0_DIS); 2169 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 2170 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 2171 0xfe); 2172 } 2173 } else { 2174 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 2175 if (!on) 2176 reg |= R92C_LEDCFG0_DIS; 2177 urtwn_write_1(sc, R92C_LEDCFG0, reg); 2178 } 2179 sc->ledlink = on; /* Save LED state. */ 2180 } 2181} 2182 2183static void 2184urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 2185{ 2186 uint8_t reg; 2187 2188 reg = urtwn_read_1(sc, R92C_MSR); 2189 reg = (reg & ~R92C_MSR_MASK) | mode; 2190 urtwn_write_1(sc, R92C_MSR, reg); 2191} 2192 2193static void 2194urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 2195 const struct ieee80211_rx_stats *rxs, 2196 int rssi, int nf) 2197{ 2198 struct ieee80211vap *vap = ni->ni_vap; 2199 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2200 struct urtwn_vap *uvp = URTWN_VAP(vap); 2201 uint64_t ni_tstamp, curr_tstamp; 2202 2203 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 2204 2205 if (vap->iv_state == IEEE80211_S_RUN && 2206 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 2207 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 2208 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 2209 URTWN_LOCK(sc); 2210 urtwn_get_tsf(sc, &curr_tstamp); 2211 URTWN_UNLOCK(sc); 2212 curr_tstamp = le64toh(curr_tstamp); 2213 2214 if (ni_tstamp >= curr_tstamp) 2215 (void) ieee80211_ibss_merge(ni); 2216 } 2217} 2218 2219static int 2220urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2221{ 2222 struct urtwn_vap *uvp = URTWN_VAP(vap); 2223 struct ieee80211com *ic = vap->iv_ic; 2224 struct urtwn_softc *sc = ic->ic_softc; 2225 struct ieee80211_node *ni; 2226 enum ieee80211_state ostate; 2227 uint32_t reg; 2228 uint8_t mode; 2229 int error = 0; 2230 2231 ostate = vap->iv_state; 2232 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 2233 ieee80211_state_name[nstate]); 2234 2235 IEEE80211_UNLOCK(ic); 2236 URTWN_LOCK(sc); 2237 callout_stop(&sc->sc_watchdog_ch); 2238 2239 if (ostate == IEEE80211_S_RUN) { 2240 /* Turn link LED off. */ 2241 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2242 2243 /* Set media status to 'No Link'. */ 2244 urtwn_set_mode(sc, R92C_MSR_NOLINK); 2245 2246 /* Stop Rx of data frames. */ 2247 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2248 2249 /* Disable TSF synchronization. */ 2250 urtwn_write_1(sc, R92C_BCN_CTRL, 2251 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 2252 R92C_BCN_CTRL_DIS_TSF_UDT0); 2253 2254 /* Disable beaconing. */ 2255 urtwn_write_1(sc, R92C_MBID_NUM, 2256 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 2257 2258 /* Reset TSF. */ 2259 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2260 2261 /* Reset EDCA parameters. */ 2262 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2263 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2264 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2265 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2266 } 2267 2268 switch (nstate) { 2269 case IEEE80211_S_INIT: 2270 /* Turn link LED off. */ 2271 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2272 break; 2273 case IEEE80211_S_SCAN: 2274 /* Pause AC Tx queues. */ 2275 urtwn_write_1(sc, R92C_TXPAUSE, 2276 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2277 break; 2278 case IEEE80211_S_AUTH: 2279 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2280 break; 2281 case IEEE80211_S_RUN: 2282 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2283 /* Turn link LED on. */ 2284 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2285 break; 2286 } 2287 2288 ni = ieee80211_ref_node(vap->iv_bss); 2289 2290 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2291 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2292 device_printf(sc->sc_dev, 2293 "%s: could not move to RUN state\n", __func__); 2294 error = EINVAL; 2295 goto end_run; 2296 } 2297 2298 switch (vap->iv_opmode) { 2299 case IEEE80211_M_STA: 2300 mode = R92C_MSR_INFRA; 2301 break; 2302 case IEEE80211_M_IBSS: 2303 mode = R92C_MSR_ADHOC; 2304 break; 2305 case IEEE80211_M_HOSTAP: 2306 mode = R92C_MSR_AP; 2307 break; 2308 default: 2309 device_printf(sc->sc_dev, "undefined opmode %d\n", 2310 vap->iv_opmode); 2311 error = EINVAL; 2312 goto end_run; 2313 } 2314 2315 /* Set media status to 'Associated'. */ 2316 urtwn_set_mode(sc, mode); 2317 2318 /* Set BSSID. */ 2319 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2320 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2321 2322 if (ic->ic_curmode == IEEE80211_MODE_11B) 2323 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2324 else /* 802.11b/g */ 2325 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2326 2327 /* Enable Rx of data frames. */ 2328 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2329 2330 /* Flush all AC queues. */ 2331 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2332 2333 /* Set beacon interval. */ 2334 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2335 2336 /* Allow Rx from our BSSID only. */ 2337 if (ic->ic_promisc == 0) { 2338 reg = urtwn_read_4(sc, R92C_RCR); 2339 2340 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 2341 reg |= R92C_RCR_CBSSID_DATA; 2342 if (vap->iv_opmode != IEEE80211_M_IBSS) 2343 reg |= R92C_RCR_CBSSID_BCN; 2344 2345 urtwn_write_4(sc, R92C_RCR, reg); 2346 } 2347 2348 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2349 vap->iv_opmode == IEEE80211_M_IBSS) { 2350 error = urtwn_setup_beacon(sc, ni); 2351 if (error != 0) { 2352 device_printf(sc->sc_dev, 2353 "unable to push beacon into the chip, " 2354 "error %d\n", error); 2355 goto end_run; 2356 } 2357 } 2358 2359 /* Enable TSF synchronization. */ 2360 urtwn_tsf_sync_enable(sc, vap); 2361 2362 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2363 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2364 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2365 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2366 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2367 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2368 2369 /* Intialize rate adaptation. */ 2370 if (!(sc->chip & URTWN_CHIP_88E)) 2371 urtwn_ra_init(sc); 2372 /* Turn link LED on. */ 2373 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2374 2375 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2376 /* Reset temperature calibration state machine. */ 2377 sc->thcal_state = 0; 2378 sc->thcal_lctemp = 0; 2379 2380end_run: 2381 ieee80211_free_node(ni); 2382 break; 2383 default: 2384 break; 2385 } 2386 2387 URTWN_UNLOCK(sc); 2388 IEEE80211_LOCK(ic); 2389 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2390} 2391 2392static void 2393urtwn_watchdog(void *arg) 2394{ 2395 struct urtwn_softc *sc = arg; 2396 2397 if (sc->sc_txtimer > 0) { 2398 if (--sc->sc_txtimer == 0) { 2399 device_printf(sc->sc_dev, "device timeout\n"); 2400 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2401 return; 2402 } 2403 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2404 } 2405} 2406 2407static void 2408urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2409{ 2410 int pwdb; 2411 2412 /* Convert antenna signal to percentage. */ 2413 if (rssi <= -100 || rssi >= 20) 2414 pwdb = 0; 2415 else if (rssi >= 0) 2416 pwdb = 100; 2417 else 2418 pwdb = 100 + rssi; 2419 if (!(sc->chip & URTWN_CHIP_88E)) { 2420 if (rate <= URTWN_RIDX_CCK11) { 2421 /* CCK gain is smaller than OFDM/MCS gain. */ 2422 pwdb += 6; 2423 if (pwdb > 100) 2424 pwdb = 100; 2425 if (pwdb <= 14) 2426 pwdb -= 4; 2427 else if (pwdb <= 26) 2428 pwdb -= 8; 2429 else if (pwdb <= 34) 2430 pwdb -= 6; 2431 else if (pwdb <= 42) 2432 pwdb -= 2; 2433 } 2434 } 2435 if (sc->avg_pwdb == -1) /* Init. */ 2436 sc->avg_pwdb = pwdb; 2437 else if (sc->avg_pwdb < pwdb) 2438 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2439 else 2440 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2441 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 2442} 2443 2444static int8_t 2445urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2446{ 2447 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2448 struct r92c_rx_phystat *phy; 2449 struct r92c_rx_cck *cck; 2450 uint8_t rpt; 2451 int8_t rssi; 2452 2453 if (rate <= URTWN_RIDX_CCK11) { 2454 cck = (struct r92c_rx_cck *)physt; 2455 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2456 rpt = (cck->agc_rpt >> 5) & 0x3; 2457 rssi = (cck->agc_rpt & 0x1f) << 1; 2458 } else { 2459 rpt = (cck->agc_rpt >> 6) & 0x3; 2460 rssi = cck->agc_rpt & 0x3e; 2461 } 2462 rssi = cckoff[rpt] - rssi; 2463 } else { /* OFDM/HT. */ 2464 phy = (struct r92c_rx_phystat *)physt; 2465 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2466 } 2467 return (rssi); 2468} 2469 2470static int8_t 2471urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2472{ 2473 struct r92c_rx_phystat *phy; 2474 struct r88e_rx_cck *cck; 2475 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2476 int8_t rssi; 2477 2478 rssi = 0; 2479 if (rate <= URTWN_RIDX_CCK11) { 2480 cck = (struct r88e_rx_cck *)physt; 2481 cck_agc_rpt = cck->agc_rpt; 2482 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2483 vga_idx = cck_agc_rpt & 0x1f; 2484 switch (lna_idx) { 2485 case 7: 2486 if (vga_idx <= 27) 2487 rssi = -100 + 2* (27 - vga_idx); 2488 else 2489 rssi = -100; 2490 break; 2491 case 6: 2492 rssi = -48 + 2 * (2 - vga_idx); 2493 break; 2494 case 5: 2495 rssi = -42 + 2 * (7 - vga_idx); 2496 break; 2497 case 4: 2498 rssi = -36 + 2 * (7 - vga_idx); 2499 break; 2500 case 3: 2501 rssi = -24 + 2 * (7 - vga_idx); 2502 break; 2503 case 2: 2504 rssi = -12 + 2 * (5 - vga_idx); 2505 break; 2506 case 1: 2507 rssi = 8 - (2 * vga_idx); 2508 break; 2509 case 0: 2510 rssi = 14 - (2 * vga_idx); 2511 break; 2512 } 2513 rssi += 6; 2514 } else { /* OFDM/HT. */ 2515 phy = (struct r92c_rx_phystat *)physt; 2516 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2517 } 2518 return (rssi); 2519} 2520 2521static __inline uint8_t 2522rate2ridx(uint8_t rate) 2523{ 2524 switch (rate) { 2525 case 12: return 4; 2526 case 18: return 5; 2527 case 24: return 6; 2528 case 36: return 7; 2529 case 48: return 8; 2530 case 72: return 9; 2531 case 96: return 10; 2532 case 108: return 11; 2533 case 2: return 0; 2534 case 4: return 1; 2535 case 11: return 2; 2536 case 22: return 3; 2537 default: return 0; 2538 } 2539} 2540 2541static int 2542urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2543 struct mbuf *m, struct urtwn_data *data) 2544{ 2545 const struct ieee80211_txparam *tp; 2546 struct ieee80211com *ic = &sc->sc_ic; 2547 struct ieee80211vap *vap = ni->ni_vap; 2548 struct ieee80211_key *k = NULL; 2549 struct ieee80211_channel *chan; 2550 struct ieee80211_frame *wh; 2551 struct r92c_tx_desc *txd; 2552 uint8_t macid, raid, rate, ridx, subtype, type, tid, qsel; 2553 int hasqos, ismcast; 2554 2555 URTWN_ASSERT_LOCKED(sc); 2556 2557 /* 2558 * Software crypto. 2559 */ 2560 wh = mtod(m, struct ieee80211_frame *); 2561 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2562 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2563 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2564 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2565 2566 /* Select TX ring for this frame. */ 2567 if (hasqos) { 2568 tid = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2569 tid &= IEEE80211_QOS_TID; 2570 } else 2571 tid = 0; 2572 2573 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2574 ni->ni_chan : ic->ic_curchan; 2575 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2576 2577 /* Choose a TX rate index. */ 2578 if (type == IEEE80211_FC0_TYPE_MGT) 2579 rate = tp->mgmtrate; 2580 else if (ismcast) 2581 rate = tp->mcastrate; 2582 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2583 rate = tp->ucastrate; 2584 else if (m->m_flags & M_EAPOL) 2585 rate = tp->mgmtrate; 2586 else { 2587 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2588 /* XXX pass pktlen */ 2589 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2590 rate = ni->ni_txrate; 2591 } else { 2592 if (ic->ic_curmode != IEEE80211_MODE_11B) 2593 rate = 108; 2594 else 2595 rate = 22; 2596 } 2597 } 2598 2599 ridx = rate2ridx(rate); 2600 if (ic->ic_curmode != IEEE80211_MODE_11B) 2601 raid = R92C_RAID_11BG; 2602 else 2603 raid = R92C_RAID_11B; 2604 2605 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2606 k = ieee80211_crypto_encap(ni, m); 2607 if (k == NULL) { 2608 device_printf(sc->sc_dev, 2609 "ieee80211_crypto_encap returns NULL.\n"); 2610 return (ENOBUFS); 2611 } 2612 2613 /* in case packet header moved, reset pointer */ 2614 wh = mtod(m, struct ieee80211_frame *); 2615 } 2616 2617 /* Fill Tx descriptor. */ 2618 txd = (struct r92c_tx_desc *)data->buf; 2619 memset(txd, 0, sizeof(*txd)); 2620 2621 txd->txdw0 |= htole32( 2622 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2623 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2624 if (ismcast) 2625 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2626 2627 if (!ismcast) { 2628 if (sc->chip & URTWN_CHIP_88E) { 2629 struct urtwn_node *un = URTWN_NODE(ni); 2630 macid = un->id; 2631 } else 2632 macid = URTWN_MACID_BSS; 2633 2634 if (type == IEEE80211_FC0_TYPE_DATA) { 2635 qsel = tid % URTWN_MAX_TID; 2636 2637 if (sc->chip & URTWN_CHIP_88E) { 2638 txd->txdw2 |= htole32( 2639 R88E_TXDW2_AGGBK | 2640 R88E_TXDW2_CCX_RPT); 2641 } else 2642 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2643 2644 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2645 switch (ic->ic_protmode) { 2646 case IEEE80211_PROT_CTSONLY: 2647 txd->txdw4 |= htole32( 2648 R92C_TXDW4_CTS2SELF | 2649 R92C_TXDW4_HWRTSEN); 2650 break; 2651 case IEEE80211_PROT_RTSCTS: 2652 txd->txdw4 |= htole32( 2653 R92C_TXDW4_RTSEN | 2654 R92C_TXDW4_HWRTSEN); 2655 break; 2656 default: 2657 break; 2658 } 2659 } 2660 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2661 URTWN_RIDX_OFDM24)); 2662 txd->txdw5 |= htole32(0x0001ff00); 2663 } else /* IEEE80211_FC0_TYPE_MGT */ 2664 qsel = R92C_TXDW1_QSEL_MGNT; 2665 } else { 2666 macid = URTWN_MACID_BC; 2667 qsel = R92C_TXDW1_QSEL_MGNT; 2668 } 2669 2670 txd->txdw1 |= htole32( 2671 SM(R92C_TXDW1_QSEL, qsel) | 2672 SM(R92C_TXDW1_RAID, raid)); 2673 2674 if (sc->chip & URTWN_CHIP_88E) 2675 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 2676 else 2677 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 2678 2679 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2680 /* Force this rate if needed. */ 2681 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 2682 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 2683 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2684 2685 if (!hasqos) { 2686 /* Use HW sequence numbering for non-QoS frames. */ 2687 if (sc->chip & URTWN_CHIP_88E) 2688 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2689 else 2690 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2691 } else { 2692 /* Set sequence number. */ 2693 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2694 } 2695 2696 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2697 uint8_t cipher; 2698 2699 switch (k->wk_cipher->ic_cipher) { 2700 case IEEE80211_CIPHER_WEP: 2701 case IEEE80211_CIPHER_TKIP: 2702 cipher = R92C_TXDW1_CIPHER_RC4; 2703 break; 2704 case IEEE80211_CIPHER_AES_CCM: 2705 cipher = R92C_TXDW1_CIPHER_AES; 2706 break; 2707 default: 2708 device_printf(sc->sc_dev, "%s: unknown cipher %d\n", 2709 __func__, k->wk_cipher->ic_cipher); 2710 return (EINVAL); 2711 } 2712 2713 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 2714 } 2715 2716 if (ieee80211_radiotap_active_vap(vap)) { 2717 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2718 2719 tap->wt_flags = 0; 2720 if (k != NULL) 2721 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2722 ieee80211_radiotap_tx(vap, m); 2723 } 2724 2725 data->ni = ni; 2726 2727 urtwn_tx_start(sc, m, type, data); 2728 2729 return (0); 2730} 2731 2732static void 2733urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 2734 struct urtwn_data *data) 2735{ 2736 struct usb_xfer *xfer; 2737 struct r92c_tx_desc *txd; 2738 uint16_t ac, sum; 2739 int i, xferlen; 2740 2741 URTWN_ASSERT_LOCKED(sc); 2742 2743 ac = M_WME_GETAC(m); 2744 2745 switch (type) { 2746 case IEEE80211_FC0_TYPE_CTL: 2747 case IEEE80211_FC0_TYPE_MGT: 2748 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 2749 break; 2750 default: 2751 xfer = sc->sc_xfer[wme2queue[ac].qid]; 2752 break; 2753 } 2754 2755 txd = (struct r92c_tx_desc *)data->buf; 2756 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 2757 2758 /* Compute Tx descriptor checksum. */ 2759 sum = 0; 2760 for (i = 0; i < sizeof(*txd) / 2; i++) 2761 sum ^= ((uint16_t *)txd)[i]; 2762 txd->txdsum = sum; /* NB: already little endian. */ 2763 2764 xferlen = sizeof(*txd) + m->m_pkthdr.len; 2765 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 2766 2767 data->buflen = xferlen; 2768 data->m = m; 2769 2770 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 2771 usbd_transfer_start(xfer); 2772} 2773 2774static int 2775urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 2776{ 2777 struct urtwn_softc *sc = ic->ic_softc; 2778 int error; 2779 2780 URTWN_LOCK(sc); 2781 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2782 URTWN_UNLOCK(sc); 2783 return (ENXIO); 2784 } 2785 error = mbufq_enqueue(&sc->sc_snd, m); 2786 if (error) { 2787 URTWN_UNLOCK(sc); 2788 return (error); 2789 } 2790 urtwn_start(sc); 2791 URTWN_UNLOCK(sc); 2792 2793 return (0); 2794} 2795 2796static void 2797urtwn_start(struct urtwn_softc *sc) 2798{ 2799 struct ieee80211_node *ni; 2800 struct mbuf *m; 2801 struct urtwn_data *bf; 2802 2803 URTWN_ASSERT_LOCKED(sc); 2804 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2805 bf = urtwn_getbuf(sc); 2806 if (bf == NULL) { 2807 mbufq_prepend(&sc->sc_snd, m); 2808 break; 2809 } 2810 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2811 m->m_pkthdr.rcvif = NULL; 2812 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 2813 if_inc_counter(ni->ni_vap->iv_ifp, 2814 IFCOUNTER_OERRORS, 1); 2815 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2816 m_freem(m); 2817 ieee80211_free_node(ni); 2818 break; 2819 } 2820 sc->sc_txtimer = 5; 2821 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2822 } 2823} 2824 2825static void 2826urtwn_parent(struct ieee80211com *ic) 2827{ 2828 struct urtwn_softc *sc = ic->ic_softc; 2829 2830 URTWN_LOCK(sc); 2831 if (sc->sc_flags & URTWN_DETACHED) { 2832 URTWN_UNLOCK(sc); 2833 return; 2834 } 2835 URTWN_UNLOCK(sc); 2836 2837 if (ic->ic_nrunning > 0) { 2838 if (urtwn_init(sc) != 0) { 2839 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2840 if (vap != NULL) 2841 ieee80211_stop(vap); 2842 } else 2843 ieee80211_start_all(ic); 2844 } else 2845 urtwn_stop(sc); 2846} 2847 2848static __inline int 2849urtwn_power_on(struct urtwn_softc *sc) 2850{ 2851 2852 return sc->sc_power_on(sc); 2853} 2854 2855static int 2856urtwn_r92c_power_on(struct urtwn_softc *sc) 2857{ 2858 uint32_t reg; 2859 usb_error_t error; 2860 int ntries; 2861 2862 /* Wait for autoload done bit. */ 2863 for (ntries = 0; ntries < 1000; ntries++) { 2864 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2865 break; 2866 urtwn_ms_delay(sc); 2867 } 2868 if (ntries == 1000) { 2869 device_printf(sc->sc_dev, 2870 "timeout waiting for chip autoload\n"); 2871 return (ETIMEDOUT); 2872 } 2873 2874 /* Unlock ISO/CLK/Power control register. */ 2875 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2876 if (error != USB_ERR_NORMAL_COMPLETION) 2877 return (EIO); 2878 /* Move SPS into PWM mode. */ 2879 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2880 if (error != USB_ERR_NORMAL_COMPLETION) 2881 return (EIO); 2882 urtwn_ms_delay(sc); 2883 2884 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2885 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2886 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2887 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2888 if (error != USB_ERR_NORMAL_COMPLETION) 2889 return (EIO); 2890 urtwn_ms_delay(sc); 2891 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2892 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2893 ~R92C_SYS_ISO_CTRL_MD2PP); 2894 if (error != USB_ERR_NORMAL_COMPLETION) 2895 return (EIO); 2896 } 2897 2898 /* Auto enable WLAN. */ 2899 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2900 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2901 if (error != USB_ERR_NORMAL_COMPLETION) 2902 return (EIO); 2903 for (ntries = 0; ntries < 1000; ntries++) { 2904 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2905 R92C_APS_FSMCO_APFM_ONMAC)) 2906 break; 2907 urtwn_ms_delay(sc); 2908 } 2909 if (ntries == 1000) { 2910 device_printf(sc->sc_dev, 2911 "timeout waiting for MAC auto ON\n"); 2912 return (ETIMEDOUT); 2913 } 2914 2915 /* Enable radio, GPIO and LED functions. */ 2916 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2917 R92C_APS_FSMCO_AFSM_HSUS | 2918 R92C_APS_FSMCO_PDN_EN | 2919 R92C_APS_FSMCO_PFM_ALDN); 2920 if (error != USB_ERR_NORMAL_COMPLETION) 2921 return (EIO); 2922 /* Release RF digital isolation. */ 2923 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2924 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2925 if (error != USB_ERR_NORMAL_COMPLETION) 2926 return (EIO); 2927 2928 /* Initialize MAC. */ 2929 error = urtwn_write_1(sc, R92C_APSD_CTRL, 2930 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2931 if (error != USB_ERR_NORMAL_COMPLETION) 2932 return (EIO); 2933 for (ntries = 0; ntries < 200; ntries++) { 2934 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2935 R92C_APSD_CTRL_OFF_STATUS)) 2936 break; 2937 urtwn_ms_delay(sc); 2938 } 2939 if (ntries == 200) { 2940 device_printf(sc->sc_dev, 2941 "timeout waiting for MAC initialization\n"); 2942 return (ETIMEDOUT); 2943 } 2944 2945 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2946 reg = urtwn_read_2(sc, R92C_CR); 2947 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2948 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2949 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2950 R92C_CR_ENSEC; 2951 error = urtwn_write_2(sc, R92C_CR, reg); 2952 if (error != USB_ERR_NORMAL_COMPLETION) 2953 return (EIO); 2954 2955 error = urtwn_write_1(sc, 0xfe10, 0x19); 2956 if (error != USB_ERR_NORMAL_COMPLETION) 2957 return (EIO); 2958 return (0); 2959} 2960 2961static int 2962urtwn_r88e_power_on(struct urtwn_softc *sc) 2963{ 2964 uint32_t reg; 2965 usb_error_t error; 2966 int ntries; 2967 2968 /* Wait for power ready bit. */ 2969 for (ntries = 0; ntries < 5000; ntries++) { 2970 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2971 break; 2972 urtwn_ms_delay(sc); 2973 } 2974 if (ntries == 5000) { 2975 device_printf(sc->sc_dev, 2976 "timeout waiting for chip power up\n"); 2977 return (ETIMEDOUT); 2978 } 2979 2980 /* Reset BB. */ 2981 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2982 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2983 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2984 if (error != USB_ERR_NORMAL_COMPLETION) 2985 return (EIO); 2986 2987 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2988 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2989 if (error != USB_ERR_NORMAL_COMPLETION) 2990 return (EIO); 2991 2992 /* Disable HWPDN. */ 2993 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2994 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2995 if (error != USB_ERR_NORMAL_COMPLETION) 2996 return (EIO); 2997 2998 /* Disable WL suspend. */ 2999 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3000 urtwn_read_2(sc, R92C_APS_FSMCO) & 3001 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 3002 if (error != USB_ERR_NORMAL_COMPLETION) 3003 return (EIO); 3004 3005 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3006 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3007 if (error != USB_ERR_NORMAL_COMPLETION) 3008 return (EIO); 3009 for (ntries = 0; ntries < 5000; ntries++) { 3010 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3011 R92C_APS_FSMCO_APFM_ONMAC)) 3012 break; 3013 urtwn_ms_delay(sc); 3014 } 3015 if (ntries == 5000) 3016 return (ETIMEDOUT); 3017 3018 /* Enable LDO normal mode. */ 3019 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 3020 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 3021 if (error != USB_ERR_NORMAL_COMPLETION) 3022 return (EIO); 3023 3024 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3025 error = urtwn_write_2(sc, R92C_CR, 0); 3026 if (error != USB_ERR_NORMAL_COMPLETION) 3027 return (EIO); 3028 reg = urtwn_read_2(sc, R92C_CR); 3029 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3030 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3031 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3032 error = urtwn_write_2(sc, R92C_CR, reg); 3033 if (error != USB_ERR_NORMAL_COMPLETION) 3034 return (EIO); 3035 3036 return (0); 3037} 3038 3039static int 3040urtwn_llt_init(struct urtwn_softc *sc) 3041{ 3042 int i, error, page_count, pktbuf_count; 3043 3044 page_count = (sc->chip & URTWN_CHIP_88E) ? 3045 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 3046 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 3047 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 3048 3049 /* Reserve pages [0; page_count]. */ 3050 for (i = 0; i < page_count; i++) { 3051 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3052 return (error); 3053 } 3054 /* NB: 0xff indicates end-of-list. */ 3055 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3056 return (error); 3057 /* 3058 * Use pages [page_count + 1; pktbuf_count - 1] 3059 * as ring buffer. 3060 */ 3061 for (++i; i < pktbuf_count - 1; i++) { 3062 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3063 return (error); 3064 } 3065 /* Make the last page point to the beginning of the ring buffer. */ 3066 error = urtwn_llt_write(sc, i, page_count + 1); 3067 return (error); 3068} 3069 3070static void 3071urtwn_fw_reset(struct urtwn_softc *sc) 3072{ 3073 uint16_t reg; 3074 int ntries; 3075 3076 /* Tell 8051 to reset itself. */ 3077 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3078 3079 /* Wait until 8051 resets by itself. */ 3080 for (ntries = 0; ntries < 100; ntries++) { 3081 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3082 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3083 return; 3084 urtwn_ms_delay(sc); 3085 } 3086 /* Force 8051 reset. */ 3087 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3088} 3089 3090static void 3091urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3092{ 3093 uint16_t reg; 3094 3095 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3096 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3097 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3098} 3099 3100static int 3101urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 3102{ 3103 uint32_t reg; 3104 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 3105 int off, mlen; 3106 3107 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3108 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3109 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3110 3111 off = R92C_FW_START_ADDR; 3112 while (len > 0) { 3113 if (len > 196) 3114 mlen = 196; 3115 else if (len > 4) 3116 mlen = 4; 3117 else 3118 mlen = 1; 3119 /* XXX fix this deconst */ 3120 error = urtwn_write_region_1(sc, off, 3121 __DECONST(uint8_t *, buf), mlen); 3122 if (error != USB_ERR_NORMAL_COMPLETION) 3123 break; 3124 off += mlen; 3125 buf += mlen; 3126 len -= mlen; 3127 } 3128 return (error); 3129} 3130 3131static int 3132urtwn_load_firmware(struct urtwn_softc *sc) 3133{ 3134 const struct firmware *fw; 3135 const struct r92c_fw_hdr *hdr; 3136 const char *imagename; 3137 const u_char *ptr; 3138 size_t len; 3139 uint32_t reg; 3140 int mlen, ntries, page, error; 3141 3142 URTWN_UNLOCK(sc); 3143 /* Read firmware image from the filesystem. */ 3144 if (sc->chip & URTWN_CHIP_88E) 3145 imagename = "urtwn-rtl8188eufw"; 3146 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3147 URTWN_CHIP_UMC_A_CUT) 3148 imagename = "urtwn-rtl8192cfwU"; 3149 else 3150 imagename = "urtwn-rtl8192cfwT"; 3151 3152 fw = firmware_get(imagename); 3153 URTWN_LOCK(sc); 3154 if (fw == NULL) { 3155 device_printf(sc->sc_dev, 3156 "failed loadfirmware of file %s\n", imagename); 3157 return (ENOENT); 3158 } 3159 3160 len = fw->datasize; 3161 3162 if (len < sizeof(*hdr)) { 3163 device_printf(sc->sc_dev, "firmware too short\n"); 3164 error = EINVAL; 3165 goto fail; 3166 } 3167 ptr = fw->data; 3168 hdr = (const struct r92c_fw_hdr *)ptr; 3169 /* Check if there is a valid FW header and skip it. */ 3170 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3171 (le16toh(hdr->signature) >> 4) == 0x88e || 3172 (le16toh(hdr->signature) >> 4) == 0x92c) { 3173 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 3174 le16toh(hdr->version), le16toh(hdr->subversion), 3175 hdr->month, hdr->date, hdr->hour, hdr->minute); 3176 ptr += sizeof(*hdr); 3177 len -= sizeof(*hdr); 3178 } 3179 3180 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3181 if (sc->chip & URTWN_CHIP_88E) 3182 urtwn_r88e_fw_reset(sc); 3183 else 3184 urtwn_fw_reset(sc); 3185 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3186 } 3187 3188 if (!(sc->chip & URTWN_CHIP_88E)) { 3189 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3190 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3191 R92C_SYS_FUNC_EN_CPUEN); 3192 } 3193 urtwn_write_1(sc, R92C_MCUFWDL, 3194 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3195 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3196 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3197 3198 /* Reset the FWDL checksum. */ 3199 urtwn_write_1(sc, R92C_MCUFWDL, 3200 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3201 3202 for (page = 0; len > 0; page++) { 3203 mlen = min(len, R92C_FW_PAGE_SIZE); 3204 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3205 if (error != 0) { 3206 device_printf(sc->sc_dev, 3207 "could not load firmware page\n"); 3208 goto fail; 3209 } 3210 ptr += mlen; 3211 len -= mlen; 3212 } 3213 urtwn_write_1(sc, R92C_MCUFWDL, 3214 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3215 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3216 3217 /* Wait for checksum report. */ 3218 for (ntries = 0; ntries < 1000; ntries++) { 3219 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3220 break; 3221 urtwn_ms_delay(sc); 3222 } 3223 if (ntries == 1000) { 3224 device_printf(sc->sc_dev, 3225 "timeout waiting for checksum report\n"); 3226 error = ETIMEDOUT; 3227 goto fail; 3228 } 3229 3230 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3231 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3232 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3233 if (sc->chip & URTWN_CHIP_88E) 3234 urtwn_r88e_fw_reset(sc); 3235 /* Wait for firmware readiness. */ 3236 for (ntries = 0; ntries < 1000; ntries++) { 3237 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3238 break; 3239 urtwn_ms_delay(sc); 3240 } 3241 if (ntries == 1000) { 3242 device_printf(sc->sc_dev, 3243 "timeout waiting for firmware readiness\n"); 3244 error = ETIMEDOUT; 3245 goto fail; 3246 } 3247fail: 3248 firmware_put(fw, FIRMWARE_UNLOAD); 3249 return (error); 3250} 3251 3252static int 3253urtwn_dma_init(struct urtwn_softc *sc) 3254{ 3255 struct usb_endpoint *ep, *ep_end; 3256 usb_error_t usb_err; 3257 uint32_t reg; 3258 int hashq, hasnq, haslq, nqueues, ntx; 3259 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 3260 3261 /* Initialize LLT table. */ 3262 error = urtwn_llt_init(sc); 3263 if (error != 0) 3264 return (error); 3265 3266 /* Determine the number of bulk-out pipes. */ 3267 ntx = 0; 3268 ep = sc->sc_udev->endpoints; 3269 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 3270 for (; ep != ep_end; ep++) { 3271 if ((ep->edesc == NULL) || 3272 (ep->iface_index != sc->sc_iface_index)) 3273 continue; 3274 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 3275 ntx++; 3276 } 3277 if (ntx == 0) { 3278 device_printf(sc->sc_dev, 3279 "%d: invalid number of Tx bulk pipes\n", ntx); 3280 return (EIO); 3281 } 3282 3283 /* Get Tx queues to USB endpoints mapping. */ 3284 hashq = hasnq = haslq = nqueues = 0; 3285 switch (ntx) { 3286 case 1: hashq = 1; break; 3287 case 2: hashq = hasnq = 1; break; 3288 case 3: case 4: hashq = hasnq = haslq = 1; break; 3289 } 3290 nqueues = hashq + hasnq + haslq; 3291 if (nqueues == 0) 3292 return (EIO); 3293 3294 npubqpages = nqpages = nrempages = pagecount = 0; 3295 if (sc->chip & URTWN_CHIP_88E) 3296 tx_boundary = R88E_TX_PAGE_BOUNDARY; 3297 else { 3298 pagecount = R92C_TX_PAGE_COUNT; 3299 npubqpages = R92C_PUBQ_NPAGES; 3300 tx_boundary = R92C_TX_PAGE_BOUNDARY; 3301 } 3302 3303 /* Set number of pages for normal priority queue. */ 3304 if (sc->chip & URTWN_CHIP_88E) { 3305 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 3306 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3307 return (EIO); 3308 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3309 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3310 return (EIO); 3311 } else { 3312 /* Get the number of pages for each queue. */ 3313 nqpages = (pagecount - npubqpages) / nqueues; 3314 /* 3315 * The remaining pages are assigned to the high priority 3316 * queue. 3317 */ 3318 nrempages = (pagecount - npubqpages) % nqueues; 3319 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3320 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3321 return (EIO); 3322 usb_err = urtwn_write_4(sc, R92C_RQPN, 3323 /* Set number of pages for public queue. */ 3324 SM(R92C_RQPN_PUBQ, npubqpages) | 3325 /* Set number of pages for high priority queue. */ 3326 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3327 /* Set number of pages for low priority queue. */ 3328 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3329 /* Load values. */ 3330 R92C_RQPN_LD); 3331 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3332 return (EIO); 3333 } 3334 3335 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 3336 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3337 return (EIO); 3338 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 3339 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3340 return (EIO); 3341 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 3342 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3343 return (EIO); 3344 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 3345 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3346 return (EIO); 3347 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 3348 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3349 return (EIO); 3350 3351 /* Set queue to USB pipe mapping. */ 3352 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3353 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3354 if (nqueues == 1) { 3355 if (hashq) 3356 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3357 else if (hasnq) 3358 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3359 else 3360 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3361 } else if (nqueues == 2) { 3362 /* 3363 * All 2-endpoints configs have high and normal 3364 * priority queues. 3365 */ 3366 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3367 } else 3368 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3369 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3370 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3371 return (EIO); 3372 3373 /* Set Tx/Rx transfer page boundary. */ 3374 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 3375 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 3376 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3377 return (EIO); 3378 3379 /* Set Tx/Rx transfer page size. */ 3380 usb_err = urtwn_write_1(sc, R92C_PBP, 3381 SM(R92C_PBP_PSRX, R92C_PBP_128) | 3382 SM(R92C_PBP_PSTX, R92C_PBP_128)); 3383 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3384 return (EIO); 3385 3386 return (0); 3387} 3388 3389static int 3390urtwn_mac_init(struct urtwn_softc *sc) 3391{ 3392 usb_error_t error; 3393 int i; 3394 3395 /* Write MAC initialization values. */ 3396 if (sc->chip & URTWN_CHIP_88E) { 3397 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 3398 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3399 rtl8188eu_mac[i].val); 3400 if (error != USB_ERR_NORMAL_COMPLETION) 3401 return (EIO); 3402 } 3403 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 3404 } else { 3405 for (i = 0; i < nitems(rtl8192cu_mac); i++) 3406 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3407 rtl8192cu_mac[i].val); 3408 if (error != USB_ERR_NORMAL_COMPLETION) 3409 return (EIO); 3410 } 3411 3412 return (0); 3413} 3414 3415static void 3416urtwn_bb_init(struct urtwn_softc *sc) 3417{ 3418 const struct urtwn_bb_prog *prog; 3419 uint32_t reg; 3420 uint8_t crystalcap; 3421 int i; 3422 3423 /* Enable BB and RF. */ 3424 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3425 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3426 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3427 R92C_SYS_FUNC_EN_DIO_RF); 3428 3429 if (!(sc->chip & URTWN_CHIP_88E)) 3430 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 3431 3432 urtwn_write_1(sc, R92C_RF_CTRL, 3433 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3434 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3435 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3436 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3437 3438 if (!(sc->chip & URTWN_CHIP_88E)) { 3439 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3440 urtwn_write_1(sc, 0x15, 0xe9); 3441 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3442 } 3443 3444 /* Select BB programming based on board type. */ 3445 if (sc->chip & URTWN_CHIP_88E) 3446 prog = &rtl8188eu_bb_prog; 3447 else if (!(sc->chip & URTWN_CHIP_92C)) { 3448 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3449 prog = &rtl8188ce_bb_prog; 3450 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3451 prog = &rtl8188ru_bb_prog; 3452 else 3453 prog = &rtl8188cu_bb_prog; 3454 } else { 3455 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3456 prog = &rtl8192ce_bb_prog; 3457 else 3458 prog = &rtl8192cu_bb_prog; 3459 } 3460 /* Write BB initialization values. */ 3461 for (i = 0; i < prog->count; i++) { 3462 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3463 urtwn_ms_delay(sc); 3464 } 3465 3466 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3467 /* 8192C 1T only configuration. */ 3468 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3469 reg = (reg & ~0x00000003) | 0x2; 3470 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3471 3472 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3473 reg = (reg & ~0x00300033) | 0x00200022; 3474 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3475 3476 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3477 reg = (reg & ~0xff000000) | 0x45 << 24; 3478 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3479 3480 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3481 reg = (reg & ~0x000000ff) | 0x23; 3482 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3483 3484 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3485 reg = (reg & ~0x00000030) | 1 << 4; 3486 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3487 3488 reg = urtwn_bb_read(sc, 0xe74); 3489 reg = (reg & ~0x0c000000) | 2 << 26; 3490 urtwn_bb_write(sc, 0xe74, reg); 3491 reg = urtwn_bb_read(sc, 0xe78); 3492 reg = (reg & ~0x0c000000) | 2 << 26; 3493 urtwn_bb_write(sc, 0xe78, reg); 3494 reg = urtwn_bb_read(sc, 0xe7c); 3495 reg = (reg & ~0x0c000000) | 2 << 26; 3496 urtwn_bb_write(sc, 0xe7c, reg); 3497 reg = urtwn_bb_read(sc, 0xe80); 3498 reg = (reg & ~0x0c000000) | 2 << 26; 3499 urtwn_bb_write(sc, 0xe80, reg); 3500 reg = urtwn_bb_read(sc, 0xe88); 3501 reg = (reg & ~0x0c000000) | 2 << 26; 3502 urtwn_bb_write(sc, 0xe88, reg); 3503 } 3504 3505 /* Write AGC values. */ 3506 for (i = 0; i < prog->agccount; i++) { 3507 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 3508 prog->agcvals[i]); 3509 urtwn_ms_delay(sc); 3510 } 3511 3512 if (sc->chip & URTWN_CHIP_88E) { 3513 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3514 urtwn_ms_delay(sc); 3515 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3516 urtwn_ms_delay(sc); 3517 3518 crystalcap = sc->rom.r88e_rom[0xb9]; 3519 if (crystalcap == 0xff) 3520 crystalcap = 0x20; 3521 crystalcap &= 0x3f; 3522 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3523 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3524 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3525 crystalcap | crystalcap << 6)); 3526 } else { 3527 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3528 R92C_HSSI_PARAM2_CCK_HIPWR) 3529 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 3530 } 3531} 3532 3533static void 3534urtwn_rf_init(struct urtwn_softc *sc) 3535{ 3536 const struct urtwn_rf_prog *prog; 3537 uint32_t reg, type; 3538 int i, j, idx, off; 3539 3540 /* Select RF programming based on board type. */ 3541 if (sc->chip & URTWN_CHIP_88E) 3542 prog = rtl8188eu_rf_prog; 3543 else if (!(sc->chip & URTWN_CHIP_92C)) { 3544 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3545 prog = rtl8188ce_rf_prog; 3546 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3547 prog = rtl8188ru_rf_prog; 3548 else 3549 prog = rtl8188cu_rf_prog; 3550 } else 3551 prog = rtl8192ce_rf_prog; 3552 3553 for (i = 0; i < sc->nrxchains; i++) { 3554 /* Save RF_ENV control type. */ 3555 idx = i / 2; 3556 off = (i % 2) * 16; 3557 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3558 type = (reg >> off) & 0x10; 3559 3560 /* Set RF_ENV enable. */ 3561 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3562 reg |= 0x100000; 3563 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3564 urtwn_ms_delay(sc); 3565 /* Set RF_ENV output high. */ 3566 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3567 reg |= 0x10; 3568 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3569 urtwn_ms_delay(sc); 3570 /* Set address and data lengths of RF registers. */ 3571 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3572 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3573 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3574 urtwn_ms_delay(sc); 3575 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3576 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3577 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3578 urtwn_ms_delay(sc); 3579 3580 /* Write RF initialization values for this chain. */ 3581 for (j = 0; j < prog[i].count; j++) { 3582 if (prog[i].regs[j] >= 0xf9 && 3583 prog[i].regs[j] <= 0xfe) { 3584 /* 3585 * These are fake RF registers offsets that 3586 * indicate a delay is required. 3587 */ 3588 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 3589 continue; 3590 } 3591 urtwn_rf_write(sc, i, prog[i].regs[j], 3592 prog[i].vals[j]); 3593 urtwn_ms_delay(sc); 3594 } 3595 3596 /* Restore RF_ENV control type. */ 3597 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3598 reg &= ~(0x10 << off) | (type << off); 3599 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 3600 3601 /* Cache RF register CHNLBW. */ 3602 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3603 } 3604 3605 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3606 URTWN_CHIP_UMC_A_CUT) { 3607 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3608 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3609 } 3610} 3611 3612static void 3613urtwn_cam_init(struct urtwn_softc *sc) 3614{ 3615 /* Invalidate all CAM entries. */ 3616 urtwn_write_4(sc, R92C_CAMCMD, 3617 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3618} 3619 3620static int 3621urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 3622{ 3623 usb_error_t error; 3624 3625 error = urtwn_write_4(sc, R92C_CAMWRITE, data); 3626 if (error != USB_ERR_NORMAL_COMPLETION) 3627 return (EIO); 3628 error = urtwn_write_4(sc, R92C_CAMCMD, 3629 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 3630 SM(R92C_CAMCMD_ADDR, addr)); 3631 if (error != USB_ERR_NORMAL_COMPLETION) 3632 return (EIO); 3633 3634 return (0); 3635} 3636 3637static void 3638urtwn_pa_bias_init(struct urtwn_softc *sc) 3639{ 3640 uint8_t reg; 3641 int i; 3642 3643 for (i = 0; i < sc->nrxchains; i++) { 3644 if (sc->pa_setting & (1 << i)) 3645 continue; 3646 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3647 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3648 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3649 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3650 } 3651 if (!(sc->pa_setting & 0x10)) { 3652 reg = urtwn_read_1(sc, 0x16); 3653 reg = (reg & ~0xf0) | 0x90; 3654 urtwn_write_1(sc, 0x16, reg); 3655 } 3656} 3657 3658static void 3659urtwn_rxfilter_init(struct urtwn_softc *sc) 3660{ 3661 struct ieee80211com *ic = &sc->sc_ic; 3662 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3663 uint32_t rcr; 3664 uint16_t filter; 3665 3666 URTWN_ASSERT_LOCKED(sc); 3667 3668 /* Accept all multicast frames. */ 3669 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3670 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3671 3672 /* Filter for management frames. */ 3673 filter = 0x7f3f; 3674 switch (vap->iv_opmode) { 3675 case IEEE80211_M_STA: 3676 filter &= ~( 3677 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 3678 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 3679 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 3680 break; 3681 case IEEE80211_M_HOSTAP: 3682 filter &= ~( 3683 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 3684 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP) | 3685 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_BEACON)); 3686 break; 3687 case IEEE80211_M_MONITOR: 3688 case IEEE80211_M_IBSS: 3689 break; 3690 default: 3691 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3692 __func__, vap->iv_opmode); 3693 break; 3694 } 3695 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 3696 3697 /* Reject all control frames. */ 3698 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3699 3700 /* Reject all data frames. */ 3701 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 3702 3703 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 3704 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 3705 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 3706 3707 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 3708 /* Accept all frames. */ 3709 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 3710 R92C_RCR_AAP; 3711 } 3712 3713 /* Set Rx filter. */ 3714 urtwn_write_4(sc, R92C_RCR, rcr); 3715 3716 if (ic->ic_promisc != 0) { 3717 /* Update Rx filter. */ 3718 urtwn_set_promisc(sc); 3719 } 3720} 3721 3722static void 3723urtwn_edca_init(struct urtwn_softc *sc) 3724{ 3725 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3726 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3727 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3728 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3729 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3730 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3731 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3732 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3733} 3734 3735static void 3736urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3737 uint16_t power[URTWN_RIDX_COUNT]) 3738{ 3739 uint32_t reg; 3740 3741 /* Write per-CCK rate Tx power. */ 3742 if (chain == 0) { 3743 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3744 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3745 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3746 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3747 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3748 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3749 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3750 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3751 } else { 3752 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3753 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3754 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3755 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3756 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3757 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3758 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3759 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3760 } 3761 /* Write per-OFDM rate Tx power. */ 3762 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3763 SM(R92C_TXAGC_RATE06, power[ 4]) | 3764 SM(R92C_TXAGC_RATE09, power[ 5]) | 3765 SM(R92C_TXAGC_RATE12, power[ 6]) | 3766 SM(R92C_TXAGC_RATE18, power[ 7])); 3767 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3768 SM(R92C_TXAGC_RATE24, power[ 8]) | 3769 SM(R92C_TXAGC_RATE36, power[ 9]) | 3770 SM(R92C_TXAGC_RATE48, power[10]) | 3771 SM(R92C_TXAGC_RATE54, power[11])); 3772 /* Write per-MCS Tx power. */ 3773 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3774 SM(R92C_TXAGC_MCS00, power[12]) | 3775 SM(R92C_TXAGC_MCS01, power[13]) | 3776 SM(R92C_TXAGC_MCS02, power[14]) | 3777 SM(R92C_TXAGC_MCS03, power[15])); 3778 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3779 SM(R92C_TXAGC_MCS04, power[16]) | 3780 SM(R92C_TXAGC_MCS05, power[17]) | 3781 SM(R92C_TXAGC_MCS06, power[18]) | 3782 SM(R92C_TXAGC_MCS07, power[19])); 3783 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3784 SM(R92C_TXAGC_MCS08, power[20]) | 3785 SM(R92C_TXAGC_MCS09, power[21]) | 3786 SM(R92C_TXAGC_MCS10, power[22]) | 3787 SM(R92C_TXAGC_MCS11, power[23])); 3788 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3789 SM(R92C_TXAGC_MCS12, power[24]) | 3790 SM(R92C_TXAGC_MCS13, power[25]) | 3791 SM(R92C_TXAGC_MCS14, power[26]) | 3792 SM(R92C_TXAGC_MCS15, power[27])); 3793} 3794 3795static void 3796urtwn_get_txpower(struct urtwn_softc *sc, int chain, 3797 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3798 uint16_t power[URTWN_RIDX_COUNT]) 3799{ 3800 struct ieee80211com *ic = &sc->sc_ic; 3801 struct r92c_rom *rom = &sc->rom.r92c_rom; 3802 uint16_t cckpow, ofdmpow, htpow, diff, max; 3803 const struct urtwn_txpwr *base; 3804 int ridx, chan, group; 3805 3806 /* Determine channel group. */ 3807 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3808 if (chan <= 3) 3809 group = 0; 3810 else if (chan <= 9) 3811 group = 1; 3812 else 3813 group = 2; 3814 3815 /* Get original Tx power based on board type and RF chain. */ 3816 if (!(sc->chip & URTWN_CHIP_92C)) { 3817 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3818 base = &rtl8188ru_txagc[chain]; 3819 else 3820 base = &rtl8192cu_txagc[chain]; 3821 } else 3822 base = &rtl8192cu_txagc[chain]; 3823 3824 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3825 if (sc->regulatory == 0) { 3826 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3827 power[ridx] = base->pwr[0][ridx]; 3828 } 3829 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3830 if (sc->regulatory == 3) { 3831 power[ridx] = base->pwr[0][ridx]; 3832 /* Apply vendor limits. */ 3833 if (extc != NULL) 3834 max = rom->ht40_max_pwr[group]; 3835 else 3836 max = rom->ht20_max_pwr[group]; 3837 max = (max >> (chain * 4)) & 0xf; 3838 if (power[ridx] > max) 3839 power[ridx] = max; 3840 } else if (sc->regulatory == 1) { 3841 if (extc == NULL) 3842 power[ridx] = base->pwr[group][ridx]; 3843 } else if (sc->regulatory != 2) 3844 power[ridx] = base->pwr[0][ridx]; 3845 } 3846 3847 /* Compute per-CCK rate Tx power. */ 3848 cckpow = rom->cck_tx_pwr[chain][group]; 3849 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3850 power[ridx] += cckpow; 3851 if (power[ridx] > R92C_MAX_TX_PWR) 3852 power[ridx] = R92C_MAX_TX_PWR; 3853 } 3854 3855 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3856 if (sc->ntxchains > 1) { 3857 /* Apply reduction for 2 spatial streams. */ 3858 diff = rom->ht40_2s_tx_pwr_diff[group]; 3859 diff = (diff >> (chain * 4)) & 0xf; 3860 htpow = (htpow > diff) ? htpow - diff : 0; 3861 } 3862 3863 /* Compute per-OFDM rate Tx power. */ 3864 diff = rom->ofdm_tx_pwr_diff[group]; 3865 diff = (diff >> (chain * 4)) & 0xf; 3866 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3867 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3868 power[ridx] += ofdmpow; 3869 if (power[ridx] > R92C_MAX_TX_PWR) 3870 power[ridx] = R92C_MAX_TX_PWR; 3871 } 3872 3873 /* Compute per-MCS Tx power. */ 3874 if (extc == NULL) { 3875 diff = rom->ht20_tx_pwr_diff[group]; 3876 diff = (diff >> (chain * 4)) & 0xf; 3877 htpow += diff; /* HT40->HT20 correction. */ 3878 } 3879 for (ridx = 12; ridx <= 27; ridx++) { 3880 power[ridx] += htpow; 3881 if (power[ridx] > R92C_MAX_TX_PWR) 3882 power[ridx] = R92C_MAX_TX_PWR; 3883 } 3884#ifdef URTWN_DEBUG 3885 if (urtwn_debug >= 4) { 3886 /* Dump per-rate Tx power values. */ 3887 printf("Tx power for chain %d:\n", chain); 3888 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 3889 printf("Rate %d = %u\n", ridx, power[ridx]); 3890 } 3891#endif 3892} 3893 3894static void 3895urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3896 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3897 uint16_t power[URTWN_RIDX_COUNT]) 3898{ 3899 struct ieee80211com *ic = &sc->sc_ic; 3900 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3901 const struct urtwn_r88e_txpwr *base; 3902 int ridx, chan, group; 3903 3904 /* Determine channel group. */ 3905 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3906 if (chan <= 2) 3907 group = 0; 3908 else if (chan <= 5) 3909 group = 1; 3910 else if (chan <= 8) 3911 group = 2; 3912 else if (chan <= 11) 3913 group = 3; 3914 else if (chan <= 13) 3915 group = 4; 3916 else 3917 group = 5; 3918 3919 /* Get original Tx power based on board type and RF chain. */ 3920 base = &rtl8188eu_txagc[chain]; 3921 3922 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3923 if (sc->regulatory == 0) { 3924 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3925 power[ridx] = base->pwr[0][ridx]; 3926 } 3927 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3928 if (sc->regulatory == 3) 3929 power[ridx] = base->pwr[0][ridx]; 3930 else if (sc->regulatory == 1) { 3931 if (extc == NULL) 3932 power[ridx] = base->pwr[group][ridx]; 3933 } else if (sc->regulatory != 2) 3934 power[ridx] = base->pwr[0][ridx]; 3935 } 3936 3937 /* Compute per-CCK rate Tx power. */ 3938 cckpow = sc->cck_tx_pwr[group]; 3939 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3940 power[ridx] += cckpow; 3941 if (power[ridx] > R92C_MAX_TX_PWR) 3942 power[ridx] = R92C_MAX_TX_PWR; 3943 } 3944 3945 htpow = sc->ht40_tx_pwr[group]; 3946 3947 /* Compute per-OFDM rate Tx power. */ 3948 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3949 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3950 power[ridx] += ofdmpow; 3951 if (power[ridx] > R92C_MAX_TX_PWR) 3952 power[ridx] = R92C_MAX_TX_PWR; 3953 } 3954 3955 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3956 for (ridx = 12; ridx <= 27; ridx++) { 3957 power[ridx] += bw20pow; 3958 if (power[ridx] > R92C_MAX_TX_PWR) 3959 power[ridx] = R92C_MAX_TX_PWR; 3960 } 3961} 3962 3963static void 3964urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3965 struct ieee80211_channel *extc) 3966{ 3967 uint16_t power[URTWN_RIDX_COUNT]; 3968 int i; 3969 3970 for (i = 0; i < sc->ntxchains; i++) { 3971 /* Compute per-rate Tx power values. */ 3972 if (sc->chip & URTWN_CHIP_88E) 3973 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3974 else 3975 urtwn_get_txpower(sc, i, c, extc, power); 3976 /* Write per-rate Tx power values to hardware. */ 3977 urtwn_write_txpower(sc, i, power); 3978 } 3979} 3980 3981static void 3982urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 3983{ 3984 uint32_t reg; 3985 3986 reg = urtwn_read_4(sc, R92C_RCR); 3987 if (enable) 3988 reg &= ~R92C_RCR_CBSSID_BCN; 3989 else 3990 reg |= R92C_RCR_CBSSID_BCN; 3991 urtwn_write_4(sc, R92C_RCR, reg); 3992} 3993 3994static void 3995urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 3996{ 3997 uint32_t reg; 3998 3999 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 4000 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4001 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 4002 4003 if (!(sc->chip & URTWN_CHIP_88E)) { 4004 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 4005 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4006 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 4007 } 4008} 4009 4010static void 4011urtwn_scan_start(struct ieee80211com *ic) 4012{ 4013 struct urtwn_softc *sc = ic->ic_softc; 4014 4015 URTWN_LOCK(sc); 4016 /* Receive beacons / probe responses from any BSSID. */ 4017 if (ic->ic_opmode != IEEE80211_M_IBSS) 4018 urtwn_set_rx_bssid_all(sc, 1); 4019 4020 /* Set gain for scanning. */ 4021 urtwn_set_gain(sc, 0x20); 4022 URTWN_UNLOCK(sc); 4023} 4024 4025static void 4026urtwn_scan_end(struct ieee80211com *ic) 4027{ 4028 struct urtwn_softc *sc = ic->ic_softc; 4029 4030 URTWN_LOCK(sc); 4031 /* Restore limitations. */ 4032 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 4033 urtwn_set_rx_bssid_all(sc, 0); 4034 4035 /* Set gain under link. */ 4036 urtwn_set_gain(sc, 0x32); 4037 URTWN_UNLOCK(sc); 4038} 4039 4040static void 4041urtwn_set_channel(struct ieee80211com *ic) 4042{ 4043 struct urtwn_softc *sc = ic->ic_softc; 4044 struct ieee80211_channel *c = ic->ic_curchan; 4045 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4046 4047 URTWN_LOCK(sc); 4048 if (vap->iv_state == IEEE80211_S_SCAN) { 4049 /* Make link LED blink during scan. */ 4050 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 4051 } 4052 urtwn_set_chan(sc, c, NULL); 4053 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 4054 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 4055 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 4056 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 4057 URTWN_UNLOCK(sc); 4058} 4059 4060static int 4061urtwn_wme_update(struct ieee80211com *ic) 4062{ 4063 const struct wmeParams *wmep = 4064 ic->ic_wme.wme_chanParams.cap_wmeParams; 4065 struct urtwn_softc *sc = ic->ic_softc; 4066 uint8_t aifs, acm, slottime; 4067 int ac; 4068 4069 acm = 0; 4070 slottime = IEEE80211_GET_SLOTTIME(ic); 4071 4072 URTWN_LOCK(sc); 4073 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4074 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4075 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4076 urtwn_write_4(sc, wme2queue[ac].reg, 4077 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 4078 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 4079 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 4080 SM(R92C_EDCA_PARAM_AIFS, aifs)); 4081 if (ac != WME_AC_BE) 4082 acm |= wmep[ac].wmep_acm << ac; 4083 } 4084 4085 if (acm != 0) 4086 acm |= R92C_ACMHWCTRL_EN; 4087 urtwn_write_1(sc, R92C_ACMHWCTRL, 4088 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 4089 acm); 4090 4091 URTWN_UNLOCK(sc); 4092 4093 return 0; 4094} 4095 4096static void 4097urtwn_set_promisc(struct urtwn_softc *sc) 4098{ 4099 struct ieee80211com *ic = &sc->sc_ic; 4100 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4101 uint32_t rcr, mask1, mask2; 4102 4103 URTWN_ASSERT_LOCKED(sc); 4104 4105 if (vap->iv_opmode == IEEE80211_M_MONITOR) 4106 return; 4107 4108 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 4109 mask2 = R92C_RCR_APM; 4110 4111 if (vap->iv_state == IEEE80211_S_RUN) { 4112 switch (vap->iv_opmode) { 4113 case IEEE80211_M_STA: 4114 mask2 |= R92C_RCR_CBSSID_DATA; 4115 /* FALLTHROUGH */ 4116 case IEEE80211_M_HOSTAP: 4117 mask2 |= R92C_RCR_CBSSID_BCN; 4118 break; 4119 case IEEE80211_M_IBSS: 4120 mask2 |= R92C_RCR_CBSSID_DATA; 4121 break; 4122 default: 4123 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4124 __func__, vap->iv_opmode); 4125 return; 4126 } 4127 } 4128 4129 rcr = urtwn_read_4(sc, R92C_RCR); 4130 if (ic->ic_promisc == 0) 4131 rcr = (rcr & ~mask1) | mask2; 4132 else 4133 rcr = (rcr & ~mask2) | mask1; 4134 urtwn_write_4(sc, R92C_RCR, rcr); 4135} 4136 4137static void 4138urtwn_update_promisc(struct ieee80211com *ic) 4139{ 4140 struct urtwn_softc *sc = ic->ic_softc; 4141 4142 URTWN_LOCK(sc); 4143 if (sc->sc_flags & URTWN_RUNNING) 4144 urtwn_set_promisc(sc); 4145 URTWN_UNLOCK(sc); 4146} 4147 4148static void 4149urtwn_update_mcast(struct ieee80211com *ic) 4150{ 4151 /* XXX do nothing? */ 4152} 4153 4154static struct ieee80211_node * 4155urtwn_r88e_node_alloc(struct ieee80211vap *vap, 4156 const uint8_t mac[IEEE80211_ADDR_LEN]) 4157{ 4158 struct urtwn_node *un; 4159 4160 un = malloc(sizeof (struct urtwn_node), M_80211_NODE, 4161 M_NOWAIT | M_ZERO); 4162 4163 if (un == NULL) 4164 return NULL; 4165 4166 un->id = URTWN_MACID_UNDEFINED; 4167 4168 return &un->ni; 4169} 4170 4171static void 4172urtwn_r88e_newassoc(struct ieee80211_node *ni, int isnew) 4173{ 4174 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4175 struct urtwn_node *un = URTWN_NODE(ni); 4176 uint8_t id; 4177 4178 if (!isnew) 4179 return; 4180 4181 URTWN_NT_LOCK(sc); 4182 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 4183 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 4184 un->id = id; 4185 sc->node_list[id] = ni; 4186 break; 4187 } 4188 } 4189 URTWN_NT_UNLOCK(sc); 4190 4191 if (id > URTWN_MACID_MAX(sc)) { 4192 device_printf(sc->sc_dev, "%s: node table is full\n", 4193 __func__); 4194 } 4195} 4196 4197static void 4198urtwn_r88e_node_free(struct ieee80211_node *ni) 4199{ 4200 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4201 struct urtwn_node *un = URTWN_NODE(ni); 4202 4203 URTWN_NT_LOCK(sc); 4204 if (un->id != URTWN_MACID_UNDEFINED) 4205 sc->node_list[un->id] = NULL; 4206 URTWN_NT_UNLOCK(sc); 4207 4208 sc->sc_node_free(ni); 4209} 4210 4211static void 4212urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 4213 struct ieee80211_channel *extc) 4214{ 4215 struct ieee80211com *ic = &sc->sc_ic; 4216 uint32_t reg; 4217 u_int chan; 4218 int i; 4219 4220 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4221 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 4222 device_printf(sc->sc_dev, 4223 "%s: invalid channel %x\n", __func__, chan); 4224 return; 4225 } 4226 4227 /* Set Tx power for this new channel. */ 4228 urtwn_set_txpower(sc, c, extc); 4229 4230 for (i = 0; i < sc->nrxchains; i++) { 4231 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4232 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4233 } 4234#ifndef IEEE80211_NO_HT 4235 if (extc != NULL) { 4236 /* Is secondary channel below or above primary? */ 4237 int prichlo = c->ic_freq < extc->ic_freq; 4238 4239 urtwn_write_1(sc, R92C_BWOPMODE, 4240 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4241 4242 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4243 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4244 urtwn_write_1(sc, R92C_RRSR + 2, reg); 4245 4246 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4247 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4248 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4249 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4250 4251 /* Set CCK side band. */ 4252 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4253 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4254 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4255 4256 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4257 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4258 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4259 4260 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4261 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4262 ~R92C_FPGA0_ANAPARAM2_CBW20); 4263 4264 reg = urtwn_bb_read(sc, 0x818); 4265 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4266 urtwn_bb_write(sc, 0x818, reg); 4267 4268 /* Select 40MHz bandwidth. */ 4269 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4270 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4271 } else 4272#endif 4273 { 4274 urtwn_write_1(sc, R92C_BWOPMODE, 4275 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4276 4277 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4278 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4279 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4280 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4281 4282 if (!(sc->chip & URTWN_CHIP_88E)) { 4283 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4284 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4285 R92C_FPGA0_ANAPARAM2_CBW20); 4286 } 4287 4288 /* Select 20MHz bandwidth. */ 4289 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4290 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4291 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 4292 R92C_RF_CHNLBW_BW20)); 4293 } 4294} 4295 4296static void 4297urtwn_iq_calib(struct urtwn_softc *sc) 4298{ 4299 /* TODO */ 4300} 4301 4302static void 4303urtwn_lc_calib(struct urtwn_softc *sc) 4304{ 4305 uint32_t rf_ac[2]; 4306 uint8_t txmode; 4307 int i; 4308 4309 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4310 if ((txmode & 0x70) != 0) { 4311 /* Disable all continuous Tx. */ 4312 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4313 4314 /* Set RF mode to standby mode. */ 4315 for (i = 0; i < sc->nrxchains; i++) { 4316 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4317 urtwn_rf_write(sc, i, R92C_RF_AC, 4318 RW(rf_ac[i], R92C_RF_AC_MODE, 4319 R92C_RF_AC_MODE_STANDBY)); 4320 } 4321 } else { 4322 /* Block all Tx queues. */ 4323 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4324 } 4325 /* Start calibration. */ 4326 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4327 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4328 4329 /* Give calibration the time to complete. */ 4330 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 4331 4332 /* Restore configuration. */ 4333 if ((txmode & 0x70) != 0) { 4334 /* Restore Tx mode. */ 4335 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4336 /* Restore RF mode. */ 4337 for (i = 0; i < sc->nrxchains; i++) 4338 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4339 } else { 4340 /* Unblock all Tx queues. */ 4341 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4342 } 4343} 4344 4345static int 4346urtwn_init(struct urtwn_softc *sc) 4347{ 4348 struct ieee80211com *ic = &sc->sc_ic; 4349 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4350 uint8_t macaddr[IEEE80211_ADDR_LEN]; 4351 uint32_t reg; 4352 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 4353 int error; 4354 4355 URTWN_LOCK(sc); 4356 if (sc->sc_flags & URTWN_RUNNING) { 4357 URTWN_UNLOCK(sc); 4358 return (0); 4359 } 4360 4361 /* Init firmware commands ring. */ 4362 sc->fwcur = 0; 4363 4364 /* Allocate Tx/Rx buffers. */ 4365 error = urtwn_alloc_rx_list(sc); 4366 if (error != 0) 4367 goto fail; 4368 4369 error = urtwn_alloc_tx_list(sc); 4370 if (error != 0) 4371 goto fail; 4372 4373 /* Power on adapter. */ 4374 error = urtwn_power_on(sc); 4375 if (error != 0) 4376 goto fail; 4377 4378 /* Initialize DMA. */ 4379 error = urtwn_dma_init(sc); 4380 if (error != 0) 4381 goto fail; 4382 4383 /* Set info size in Rx descriptors (in 64-bit words). */ 4384 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4385 4386 /* Init interrupts. */ 4387 if (sc->chip & URTWN_CHIP_88E) { 4388 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4389 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4390 goto fail; 4391 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4392 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4393 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4394 goto fail; 4395 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4396 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4397 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4398 goto fail; 4399 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4400 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4401 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4402 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4403 goto fail; 4404 } else { 4405 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4406 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4407 goto fail; 4408 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4409 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4410 goto fail; 4411 } 4412 4413 /* Set MAC address. */ 4414 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 4415 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 4416 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4417 goto fail; 4418 4419 /* Set initial network type. */ 4420 urtwn_set_mode(sc, R92C_MSR_INFRA); 4421 4422 /* Initialize Rx filter. */ 4423 urtwn_rxfilter_init(sc); 4424 4425 /* Set response rate. */ 4426 reg = urtwn_read_4(sc, R92C_RRSR); 4427 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4428 urtwn_write_4(sc, R92C_RRSR, reg); 4429 4430 /* Set short/long retry limits. */ 4431 urtwn_write_2(sc, R92C_RL, 4432 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4433 4434 /* Initialize EDCA parameters. */ 4435 urtwn_edca_init(sc); 4436 4437 /* Setup rate fallback. */ 4438 if (!(sc->chip & URTWN_CHIP_88E)) { 4439 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4440 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4441 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4442 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4443 } 4444 4445 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4446 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4447 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4448 /* Set ACK timeout. */ 4449 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4450 4451 /* Setup USB aggregation. */ 4452 reg = urtwn_read_4(sc, R92C_TDECTRL); 4453 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4454 urtwn_write_4(sc, R92C_TDECTRL, reg); 4455 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4456 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4457 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4458 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4459 if (sc->chip & URTWN_CHIP_88E) 4460 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4461 else { 4462 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4463 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4464 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4465 R92C_USB_SPECIAL_OPTION_AGG_EN); 4466 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 4467 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 4468 } 4469 4470 /* Initialize beacon parameters. */ 4471 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4472 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4473 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 4474 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 4475 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4476 4477 if (!(sc->chip & URTWN_CHIP_88E)) { 4478 /* Setup AMPDU aggregation. */ 4479 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4480 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4481 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 4482 4483 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4484 } 4485 4486 /* Load 8051 microcode. */ 4487 error = urtwn_load_firmware(sc); 4488 if (error != 0) 4489 goto fail; 4490 4491 /* Initialize MAC/BB/RF blocks. */ 4492 error = urtwn_mac_init(sc); 4493 if (error != 0) { 4494 device_printf(sc->sc_dev, 4495 "%s: error while initializing MAC block\n", __func__); 4496 goto fail; 4497 } 4498 urtwn_bb_init(sc); 4499 urtwn_rf_init(sc); 4500 4501 /* Reinitialize Rx filter (D3845 is not committed yet). */ 4502 urtwn_rxfilter_init(sc); 4503 4504 if (sc->chip & URTWN_CHIP_88E) { 4505 urtwn_write_2(sc, R92C_CR, 4506 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4507 R92C_CR_MACRXEN); 4508 } 4509 4510 /* Turn CCK and OFDM blocks on. */ 4511 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4512 reg |= R92C_RFMOD_CCK_EN; 4513 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4514 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4515 goto fail; 4516 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4517 reg |= R92C_RFMOD_OFDM_EN; 4518 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4519 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4520 goto fail; 4521 4522 /* Clear per-station keys table. */ 4523 urtwn_cam_init(sc); 4524 4525 /* Enable decryption / encryption. */ 4526 urtwn_write_2(sc, R92C_SECCFG, 4527 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 4528 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA | 4529 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 4530 4531 /* 4532 * Install static keys (if any). 4533 * Must be called after urtwn_cam_init(). 4534 */ 4535 ieee80211_runtask(ic, &sc->cmdq_task); 4536 4537 /* Enable hardware sequence numbering. */ 4538 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4539 4540 /* Enable per-packet TX report. */ 4541 if (sc->chip & URTWN_CHIP_88E) { 4542 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 4543 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 4544 } 4545 4546 /* Perform LO and IQ calibrations. */ 4547 urtwn_iq_calib(sc); 4548 /* Perform LC calibration. */ 4549 urtwn_lc_calib(sc); 4550 4551 /* Fix USB interference issue. */ 4552 if (!(sc->chip & URTWN_CHIP_88E)) { 4553 urtwn_write_1(sc, 0xfe40, 0xe0); 4554 urtwn_write_1(sc, 0xfe41, 0x8d); 4555 urtwn_write_1(sc, 0xfe42, 0x80); 4556 4557 urtwn_pa_bias_init(sc); 4558 } 4559 4560 /* Initialize GPIO setting. */ 4561 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4562 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4563 4564 /* Fix for lower temperature. */ 4565 if (!(sc->chip & URTWN_CHIP_88E)) 4566 urtwn_write_1(sc, 0x15, 0xe9); 4567 4568 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 4569 4570 sc->sc_flags |= URTWN_RUNNING; 4571 4572 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4573fail: 4574 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4575 error = EIO; 4576 4577 URTWN_UNLOCK(sc); 4578 4579 return (error); 4580} 4581 4582static void 4583urtwn_stop(struct urtwn_softc *sc) 4584{ 4585 4586 URTWN_LOCK(sc); 4587 if (!(sc->sc_flags & URTWN_RUNNING)) { 4588 URTWN_UNLOCK(sc); 4589 return; 4590 } 4591 4592 sc->sc_flags &= ~URTWN_RUNNING; 4593 callout_stop(&sc->sc_watchdog_ch); 4594 urtwn_abort_xfers(sc); 4595 4596 urtwn_drain_mbufq(sc); 4597 URTWN_UNLOCK(sc); 4598} 4599 4600static void 4601urtwn_abort_xfers(struct urtwn_softc *sc) 4602{ 4603 int i; 4604 4605 URTWN_ASSERT_LOCKED(sc); 4606 4607 /* abort any pending transfers */ 4608 for (i = 0; i < URTWN_N_TRANSFER; i++) 4609 usbd_transfer_stop(sc->sc_xfer[i]); 4610} 4611 4612static int 4613urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4614 const struct ieee80211_bpf_params *params) 4615{ 4616 struct ieee80211com *ic = ni->ni_ic; 4617 struct urtwn_softc *sc = ic->ic_softc; 4618 struct urtwn_data *bf; 4619 int error; 4620 4621 /* prevent management frames from being sent if we're not ready */ 4622 URTWN_LOCK(sc); 4623 if (!(sc->sc_flags & URTWN_RUNNING)) { 4624 error = ENETDOWN; 4625 goto end; 4626 } 4627 4628 bf = urtwn_getbuf(sc); 4629 if (bf == NULL) { 4630 error = ENOBUFS; 4631 goto end; 4632 } 4633 4634 if ((error = urtwn_tx_data(sc, ni, m, bf)) != 0) { 4635 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 4636 goto end; 4637 } 4638 4639 sc->sc_txtimer = 5; 4640 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4641 4642end: 4643 if (error != 0) 4644 m_freem(m); 4645 4646 URTWN_UNLOCK(sc); 4647 4648 return (error); 4649} 4650 4651static void 4652urtwn_ms_delay(struct urtwn_softc *sc) 4653{ 4654 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 4655} 4656 4657static device_method_t urtwn_methods[] = { 4658 /* Device interface */ 4659 DEVMETHOD(device_probe, urtwn_match), 4660 DEVMETHOD(device_attach, urtwn_attach), 4661 DEVMETHOD(device_detach, urtwn_detach), 4662 4663 DEVMETHOD_END 4664}; 4665 4666static driver_t urtwn_driver = { 4667 "urtwn", 4668 urtwn_methods, 4669 sizeof(struct urtwn_softc) 4670}; 4671 4672static devclass_t urtwn_devclass; 4673 4674DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 4675MODULE_DEPEND(urtwn, usb, 1, 1, 1); 4676MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 4677MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 4678MODULE_VERSION(urtwn, 1); 4679USB_PNP_HOST_INFO(urtwn_devs); 4680