if_urtwn.c revision 292176
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2015 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#include <sys/cdefs.h> 22__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 292176 2015-12-13 22:08:27Z avos $"); 23 24/* 25 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 26 */ 27 28#include "opt_wlan.h" 29 30#include <sys/param.h> 31#include <sys/sockio.h> 32#include <sys/sysctl.h> 33#include <sys/lock.h> 34#include <sys/mutex.h> 35#include <sys/condvar.h> 36#include <sys/mbuf.h> 37#include <sys/kernel.h> 38#include <sys/socket.h> 39#include <sys/systm.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/linker.h> 45#include <sys/firmware.h> 46#include <sys/kdb.h> 47 48#include <machine/bus.h> 49#include <machine/resource.h> 50#include <sys/rman.h> 51 52#include <net/bpf.h> 53#include <net/if.h> 54#include <net/if_var.h> 55#include <net/if_arp.h> 56#include <net/ethernet.h> 57#include <net/if_dl.h> 58#include <net/if_media.h> 59#include <net/if_types.h> 60 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/in_var.h> 64#include <netinet/if_ether.h> 65#include <netinet/ip.h> 66 67#include <net80211/ieee80211_var.h> 68#include <net80211/ieee80211_input.h> 69#include <net80211/ieee80211_regdomain.h> 70#include <net80211/ieee80211_radiotap.h> 71#include <net80211/ieee80211_ratectl.h> 72 73#include <dev/usb/usb.h> 74#include <dev/usb/usbdi.h> 75#include <dev/usb/usb_device.h> 76#include "usbdevs.h" 77 78#define USB_DEBUG_VAR urtwn_debug 79#include <dev/usb/usb_debug.h> 80 81#include <dev/usb/wlan/if_urtwnreg.h> 82#include <dev/usb/wlan/if_urtwnvar.h> 83 84#ifdef USB_DEBUG 85static int urtwn_debug = 0; 86 87SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 88SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 89 "Debug level"); 90#endif 91 92#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 93 94/* various supported device vendors/products */ 95static const STRUCT_USB_HOST_ID urtwn_devs[] = { 96#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 97#define URTWN_RTL8188E_DEV(v,p) \ 98 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 99#define URTWN_RTL8188E 1 100 URTWN_DEV(ABOCOM, RTL8188CU_1), 101 URTWN_DEV(ABOCOM, RTL8188CU_2), 102 URTWN_DEV(ABOCOM, RTL8192CU), 103 URTWN_DEV(ASUS, RTL8192CU), 104 URTWN_DEV(ASUS, USBN10NANO), 105 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 106 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 107 URTWN_DEV(AZUREWAVE, RTL8188CU), 108 URTWN_DEV(BELKIN, F7D2102), 109 URTWN_DEV(BELKIN, RTL8188CU), 110 URTWN_DEV(BELKIN, RTL8192CU), 111 URTWN_DEV(CHICONY, RTL8188CUS_1), 112 URTWN_DEV(CHICONY, RTL8188CUS_2), 113 URTWN_DEV(CHICONY, RTL8188CUS_3), 114 URTWN_DEV(CHICONY, RTL8188CUS_4), 115 URTWN_DEV(CHICONY, RTL8188CUS_5), 116 URTWN_DEV(COREGA, RTL8192CU), 117 URTWN_DEV(DLINK, RTL8188CU), 118 URTWN_DEV(DLINK, RTL8192CU_1), 119 URTWN_DEV(DLINK, RTL8192CU_2), 120 URTWN_DEV(DLINK, RTL8192CU_3), 121 URTWN_DEV(DLINK, DWA131B), 122 URTWN_DEV(EDIMAX, EW7811UN), 123 URTWN_DEV(EDIMAX, RTL8192CU), 124 URTWN_DEV(FEIXUN, RTL8188CU), 125 URTWN_DEV(FEIXUN, RTL8192CU), 126 URTWN_DEV(GUILLEMOT, HWNUP150), 127 URTWN_DEV(HAWKING, RTL8192CU), 128 URTWN_DEV(HP3, RTL8188CU), 129 URTWN_DEV(NETGEAR, WNA1000M), 130 URTWN_DEV(NETGEAR, RTL8192CU), 131 URTWN_DEV(NETGEAR4, RTL8188CU), 132 URTWN_DEV(NOVATECH, RTL8188CU), 133 URTWN_DEV(PLANEX2, RTL8188CU_1), 134 URTWN_DEV(PLANEX2, RTL8188CU_2), 135 URTWN_DEV(PLANEX2, RTL8188CU_3), 136 URTWN_DEV(PLANEX2, RTL8188CU_4), 137 URTWN_DEV(PLANEX2, RTL8188CUS), 138 URTWN_DEV(PLANEX2, RTL8192CU), 139 URTWN_DEV(REALTEK, RTL8188CE_0), 140 URTWN_DEV(REALTEK, RTL8188CE_1), 141 URTWN_DEV(REALTEK, RTL8188CTV), 142 URTWN_DEV(REALTEK, RTL8188CU_0), 143 URTWN_DEV(REALTEK, RTL8188CU_1), 144 URTWN_DEV(REALTEK, RTL8188CU_2), 145 URTWN_DEV(REALTEK, RTL8188CU_3), 146 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 147 URTWN_DEV(REALTEK, RTL8188CUS), 148 URTWN_DEV(REALTEK, RTL8188RU_1), 149 URTWN_DEV(REALTEK, RTL8188RU_2), 150 URTWN_DEV(REALTEK, RTL8188RU_3), 151 URTWN_DEV(REALTEK, RTL8191CU), 152 URTWN_DEV(REALTEK, RTL8192CE), 153 URTWN_DEV(REALTEK, RTL8192CU), 154 URTWN_DEV(SITECOMEU, RTL8188CU_1), 155 URTWN_DEV(SITECOMEU, RTL8188CU_2), 156 URTWN_DEV(SITECOMEU, RTL8192CU), 157 URTWN_DEV(TRENDNET, RTL8188CU), 158 URTWN_DEV(TRENDNET, RTL8192CU), 159 URTWN_DEV(ZYXEL, RTL8192CU), 160 /* URTWN_RTL8188E */ 161 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 162 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 163 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 164 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 165 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 166#undef URTWN_RTL8188E_DEV 167#undef URTWN_DEV 168}; 169 170static device_probe_t urtwn_match; 171static device_attach_t urtwn_attach; 172static device_detach_t urtwn_detach; 173 174static usb_callback_t urtwn_bulk_tx_callback; 175static usb_callback_t urtwn_bulk_rx_callback; 176 177static void urtwn_drain_mbufq(struct urtwn_softc *sc); 178static usb_error_t urtwn_do_request(struct urtwn_softc *, 179 struct usb_device_request *, void *); 180static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 181 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 182 const uint8_t [IEEE80211_ADDR_LEN], 183 const uint8_t [IEEE80211_ADDR_LEN]); 184static void urtwn_vap_delete(struct ieee80211vap *); 185static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 186 int *); 187static struct mbuf * urtwn_report_intr(struct usb_xfer *, struct urtwn_data *, 188 int *, int8_t *); 189static struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int, 190 int *, int8_t *); 191static void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 192 void *); 193static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 194 int); 195static int urtwn_alloc_list(struct urtwn_softc *, 196 struct urtwn_data[], int, int); 197static int urtwn_alloc_rx_list(struct urtwn_softc *); 198static int urtwn_alloc_tx_list(struct urtwn_softc *); 199static void urtwn_free_list(struct urtwn_softc *, 200 struct urtwn_data data[], int); 201static void urtwn_free_rx_list(struct urtwn_softc *); 202static void urtwn_free_tx_list(struct urtwn_softc *); 203static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 204static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 205static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 206 uint8_t *, int); 207static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 208static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 209static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 210static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 211 uint8_t *, int); 212static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 213static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 214static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 215static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 216 const void *, int); 217static void urtwn_cmdq_cb(void *, int); 218static int urtwn_cmd_sleepable(struct urtwn_softc *, const void *, 219 size_t, CMD_FUNC_PROTO); 220static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 221 uint8_t, uint32_t); 222static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 223 uint8_t, uint32_t); 224static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 225static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 226 uint32_t); 227static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 228static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 229 uint8_t, uint8_t); 230#ifdef URTWN_DEBUG 231static void urtwn_dump_rom_contents(struct urtwn_softc *, 232 uint8_t *, uint16_t); 233#endif 234static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 235 uint16_t); 236static int urtwn_efuse_switch_power(struct urtwn_softc *); 237static int urtwn_read_chipid(struct urtwn_softc *); 238static int urtwn_read_rom(struct urtwn_softc *); 239static int urtwn_r88e_read_rom(struct urtwn_softc *); 240static int urtwn_ra_init(struct urtwn_softc *); 241static void urtwn_init_beacon(struct urtwn_softc *, 242 struct urtwn_vap *); 243static int urtwn_setup_beacon(struct urtwn_softc *, 244 struct ieee80211_node *); 245static void urtwn_update_beacon(struct ieee80211vap *, int); 246static int urtwn_tx_beacon(struct urtwn_softc *sc, 247 struct urtwn_vap *); 248static int urtwn_key_alloc(struct ieee80211vap *, 249 struct ieee80211_key *, ieee80211_keyix *, 250 ieee80211_keyix *); 251static void urtwn_key_set_cb(struct urtwn_softc *, 252 union sec_param *); 253static void urtwn_key_del_cb(struct urtwn_softc *, 254 union sec_param *); 255static int urtwn_key_set(struct ieee80211vap *, 256 const struct ieee80211_key *); 257static int urtwn_key_delete(struct ieee80211vap *, 258 const struct ieee80211_key *); 259static void urtwn_tsf_task_adhoc(void *, int); 260static void urtwn_tsf_sync_enable(struct urtwn_softc *, 261 struct ieee80211vap *); 262static void urtwn_set_led(struct urtwn_softc *, int, int); 263static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 264static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 265 struct mbuf *, int, 266 const struct ieee80211_rx_stats *, int, int); 267static int urtwn_newstate(struct ieee80211vap *, 268 enum ieee80211_state, int); 269static void urtwn_watchdog(void *); 270static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 271static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 272static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 273static int urtwn_tx_data(struct urtwn_softc *, 274 struct ieee80211_node *, struct mbuf *, 275 struct urtwn_data *); 276static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 277 uint8_t, struct urtwn_data *); 278static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 279static void urtwn_start(struct urtwn_softc *); 280static void urtwn_parent(struct ieee80211com *); 281static int urtwn_r92c_power_on(struct urtwn_softc *); 282static int urtwn_r88e_power_on(struct urtwn_softc *); 283static int urtwn_llt_init(struct urtwn_softc *); 284static void urtwn_fw_reset(struct urtwn_softc *); 285static void urtwn_r88e_fw_reset(struct urtwn_softc *); 286static int urtwn_fw_loadpage(struct urtwn_softc *, int, 287 const uint8_t *, int); 288static int urtwn_load_firmware(struct urtwn_softc *); 289static int urtwn_dma_init(struct urtwn_softc *); 290static int urtwn_mac_init(struct urtwn_softc *); 291static void urtwn_bb_init(struct urtwn_softc *); 292static void urtwn_rf_init(struct urtwn_softc *); 293static void urtwn_cam_init(struct urtwn_softc *); 294static int urtwn_cam_write(struct urtwn_softc *, uint32_t, 295 uint32_t); 296static void urtwn_pa_bias_init(struct urtwn_softc *); 297static void urtwn_rxfilter_init(struct urtwn_softc *); 298static void urtwn_edca_init(struct urtwn_softc *); 299static void urtwn_write_txpower(struct urtwn_softc *, int, 300 uint16_t[]); 301static void urtwn_get_txpower(struct urtwn_softc *, int, 302 struct ieee80211_channel *, 303 struct ieee80211_channel *, uint16_t[]); 304static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 305 struct ieee80211_channel *, 306 struct ieee80211_channel *, uint16_t[]); 307static void urtwn_set_txpower(struct urtwn_softc *, 308 struct ieee80211_channel *, 309 struct ieee80211_channel *); 310static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 311static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 312static void urtwn_scan_start(struct ieee80211com *); 313static void urtwn_scan_end(struct ieee80211com *); 314static void urtwn_set_channel(struct ieee80211com *); 315static int urtwn_wme_update(struct ieee80211com *); 316static void urtwn_set_promisc(struct urtwn_softc *); 317static void urtwn_update_promisc(struct ieee80211com *); 318static void urtwn_update_mcast(struct ieee80211com *); 319static struct ieee80211_node *urtwn_r88e_node_alloc(struct ieee80211vap *, 320 const uint8_t mac[IEEE80211_ADDR_LEN]); 321static void urtwn_r88e_newassoc(struct ieee80211_node *, int); 322static void urtwn_r88e_node_free(struct ieee80211_node *); 323static void urtwn_set_chan(struct urtwn_softc *, 324 struct ieee80211_channel *, 325 struct ieee80211_channel *); 326static void urtwn_iq_calib(struct urtwn_softc *); 327static void urtwn_lc_calib(struct urtwn_softc *); 328static int urtwn_init(struct urtwn_softc *); 329static void urtwn_stop(struct urtwn_softc *); 330static void urtwn_abort_xfers(struct urtwn_softc *); 331static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 332 const struct ieee80211_bpf_params *); 333static void urtwn_ms_delay(struct urtwn_softc *); 334 335/* Aliases. */ 336#define urtwn_bb_write urtwn_write_4 337#define urtwn_bb_read urtwn_read_4 338 339static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 340 [URTWN_BULK_RX] = { 341 .type = UE_BULK, 342 .endpoint = UE_ADDR_ANY, 343 .direction = UE_DIR_IN, 344 .bufsize = URTWN_RXBUFSZ, 345 .flags = { 346 .pipe_bof = 1, 347 .short_xfer_ok = 1 348 }, 349 .callback = urtwn_bulk_rx_callback, 350 }, 351 [URTWN_BULK_TX_BE] = { 352 .type = UE_BULK, 353 .endpoint = 0x03, 354 .direction = UE_DIR_OUT, 355 .bufsize = URTWN_TXBUFSZ, 356 .flags = { 357 .ext_buffer = 1, 358 .pipe_bof = 1, 359 .force_short_xfer = 1 360 }, 361 .callback = urtwn_bulk_tx_callback, 362 .timeout = URTWN_TX_TIMEOUT, /* ms */ 363 }, 364 [URTWN_BULK_TX_BK] = { 365 .type = UE_BULK, 366 .endpoint = 0x03, 367 .direction = UE_DIR_OUT, 368 .bufsize = URTWN_TXBUFSZ, 369 .flags = { 370 .ext_buffer = 1, 371 .pipe_bof = 1, 372 .force_short_xfer = 1, 373 }, 374 .callback = urtwn_bulk_tx_callback, 375 .timeout = URTWN_TX_TIMEOUT, /* ms */ 376 }, 377 [URTWN_BULK_TX_VI] = { 378 .type = UE_BULK, 379 .endpoint = 0x02, 380 .direction = UE_DIR_OUT, 381 .bufsize = URTWN_TXBUFSZ, 382 .flags = { 383 .ext_buffer = 1, 384 .pipe_bof = 1, 385 .force_short_xfer = 1 386 }, 387 .callback = urtwn_bulk_tx_callback, 388 .timeout = URTWN_TX_TIMEOUT, /* ms */ 389 }, 390 [URTWN_BULK_TX_VO] = { 391 .type = UE_BULK, 392 .endpoint = 0x02, 393 .direction = UE_DIR_OUT, 394 .bufsize = URTWN_TXBUFSZ, 395 .flags = { 396 .ext_buffer = 1, 397 .pipe_bof = 1, 398 .force_short_xfer = 1 399 }, 400 .callback = urtwn_bulk_tx_callback, 401 .timeout = URTWN_TX_TIMEOUT, /* ms */ 402 }, 403}; 404 405static const struct wme_to_queue { 406 uint16_t reg; 407 uint8_t qid; 408} wme2queue[WME_NUM_AC] = { 409 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 410 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 411 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 412 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 413}; 414 415static int 416urtwn_match(device_t self) 417{ 418 struct usb_attach_arg *uaa = device_get_ivars(self); 419 420 if (uaa->usb_mode != USB_MODE_HOST) 421 return (ENXIO); 422 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 423 return (ENXIO); 424 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 425 return (ENXIO); 426 427 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 428} 429 430static int 431urtwn_attach(device_t self) 432{ 433 struct usb_attach_arg *uaa = device_get_ivars(self); 434 struct urtwn_softc *sc = device_get_softc(self); 435 struct ieee80211com *ic = &sc->sc_ic; 436 uint8_t bands; 437 int error; 438 439 device_set_usb_desc(self); 440 sc->sc_udev = uaa->device; 441 sc->sc_dev = self; 442 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 443 sc->chip |= URTWN_CHIP_88E; 444 445 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 446 MTX_NETWORK_LOCK, MTX_DEF); 447 URTWN_CMDQ_LOCK_INIT(sc); 448 URTWN_NT_LOCK_INIT(sc); 449 callout_init(&sc->sc_watchdog_ch, 0); 450 mbufq_init(&sc->sc_snd, ifqmaxlen); 451 452 sc->sc_iface_index = URTWN_IFACE_INDEX; 453 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 454 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 455 if (error) { 456 device_printf(self, "could not allocate USB transfers, " 457 "err=%s\n", usbd_errstr(error)); 458 goto detach; 459 } 460 461 URTWN_LOCK(sc); 462 463 error = urtwn_read_chipid(sc); 464 if (error) { 465 device_printf(sc->sc_dev, "unsupported test chip\n"); 466 URTWN_UNLOCK(sc); 467 goto detach; 468 } 469 470 /* Determine number of Tx/Rx chains. */ 471 if (sc->chip & URTWN_CHIP_92C) { 472 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 473 sc->nrxchains = 2; 474 } else { 475 sc->ntxchains = 1; 476 sc->nrxchains = 1; 477 } 478 479 if (sc->chip & URTWN_CHIP_88E) 480 error = urtwn_r88e_read_rom(sc); 481 else 482 error = urtwn_read_rom(sc); 483 if (error != 0) { 484 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 485 __func__, error); 486 URTWN_UNLOCK(sc); 487 goto detach; 488 } 489 490 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 491 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 492 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 493 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 494 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 495 "8188CUS", sc->ntxchains, sc->nrxchains); 496 497 URTWN_UNLOCK(sc); 498 499 ic->ic_softc = sc; 500 ic->ic_name = device_get_nameunit(self); 501 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 502 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 503 504 /* set device capabilities */ 505 ic->ic_caps = 506 IEEE80211_C_STA /* station mode */ 507 | IEEE80211_C_MONITOR /* monitor mode */ 508 | IEEE80211_C_IBSS /* adhoc mode */ 509 | IEEE80211_C_HOSTAP /* hostap mode */ 510 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 511 | IEEE80211_C_SHSLOT /* short slot time supported */ 512 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 513 | IEEE80211_C_WPA /* 802.11i */ 514 | IEEE80211_C_WME /* 802.11e */ 515 ; 516 517 ic->ic_cryptocaps = 518 IEEE80211_CRYPTO_WEP | 519 IEEE80211_CRYPTO_TKIP | 520 IEEE80211_CRYPTO_AES_CCM; 521 522 bands = 0; 523 setbit(&bands, IEEE80211_MODE_11B); 524 setbit(&bands, IEEE80211_MODE_11G); 525 ieee80211_init_channels(ic, NULL, &bands); 526 527 ieee80211_ifattach(ic); 528 ic->ic_raw_xmit = urtwn_raw_xmit; 529 ic->ic_scan_start = urtwn_scan_start; 530 ic->ic_scan_end = urtwn_scan_end; 531 ic->ic_set_channel = urtwn_set_channel; 532 ic->ic_transmit = urtwn_transmit; 533 ic->ic_parent = urtwn_parent; 534 ic->ic_vap_create = urtwn_vap_create; 535 ic->ic_vap_delete = urtwn_vap_delete; 536 ic->ic_wme.wme_update = urtwn_wme_update; 537 ic->ic_update_promisc = urtwn_update_promisc; 538 ic->ic_update_mcast = urtwn_update_mcast; 539 if (sc->chip & URTWN_CHIP_88E) { 540 ic->ic_node_alloc = urtwn_r88e_node_alloc; 541 ic->ic_newassoc = urtwn_r88e_newassoc; 542 sc->sc_node_free = ic->ic_node_free; 543 ic->ic_node_free = urtwn_r88e_node_free; 544 } 545 546 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 547 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 548 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 549 URTWN_RX_RADIOTAP_PRESENT); 550 551 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc); 552 553 if (bootverbose) 554 ieee80211_announce(ic); 555 556 return (0); 557 558detach: 559 urtwn_detach(self); 560 return (ENXIO); /* failure */ 561} 562 563static int 564urtwn_detach(device_t self) 565{ 566 struct urtwn_softc *sc = device_get_softc(self); 567 struct ieee80211com *ic = &sc->sc_ic; 568 unsigned int x; 569 570 /* Prevent further ioctls. */ 571 URTWN_LOCK(sc); 572 sc->sc_flags |= URTWN_DETACHED; 573 URTWN_UNLOCK(sc); 574 575 urtwn_stop(sc); 576 577 callout_drain(&sc->sc_watchdog_ch); 578 579 /* stop all USB transfers */ 580 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 581 582 /* Prevent further allocations from RX/TX data lists. */ 583 URTWN_LOCK(sc); 584 STAILQ_INIT(&sc->sc_tx_active); 585 STAILQ_INIT(&sc->sc_tx_inactive); 586 STAILQ_INIT(&sc->sc_tx_pending); 587 588 STAILQ_INIT(&sc->sc_rx_active); 589 STAILQ_INIT(&sc->sc_rx_inactive); 590 URTWN_UNLOCK(sc); 591 592 /* drain USB transfers */ 593 for (x = 0; x != URTWN_N_TRANSFER; x++) 594 usbd_transfer_drain(sc->sc_xfer[x]); 595 596 /* Free data buffers. */ 597 URTWN_LOCK(sc); 598 urtwn_free_tx_list(sc); 599 urtwn_free_rx_list(sc); 600 URTWN_UNLOCK(sc); 601 602 if (ic->ic_softc == sc) { 603 ieee80211_draintask(ic, &sc->cmdq_task); 604 ieee80211_ifdetach(ic); 605 } 606 607 URTWN_NT_LOCK_DESTROY(sc); 608 URTWN_CMDQ_LOCK_DESTROY(sc); 609 mtx_destroy(&sc->sc_mtx); 610 611 return (0); 612} 613 614static void 615urtwn_drain_mbufq(struct urtwn_softc *sc) 616{ 617 struct mbuf *m; 618 struct ieee80211_node *ni; 619 URTWN_ASSERT_LOCKED(sc); 620 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 621 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 622 m->m_pkthdr.rcvif = NULL; 623 ieee80211_free_node(ni); 624 m_freem(m); 625 } 626} 627 628static usb_error_t 629urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 630 void *data) 631{ 632 usb_error_t err; 633 int ntries = 10; 634 635 URTWN_ASSERT_LOCKED(sc); 636 637 while (ntries--) { 638 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 639 req, data, 0, NULL, 250 /* ms */); 640 if (err == 0) 641 break; 642 643 DPRINTFN(1, "Control request failed, %s (retrying)\n", 644 usbd_errstr(err)); 645 usb_pause_mtx(&sc->sc_mtx, hz / 100); 646 } 647 return (err); 648} 649 650static struct ieee80211vap * 651urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 652 enum ieee80211_opmode opmode, int flags, 653 const uint8_t bssid[IEEE80211_ADDR_LEN], 654 const uint8_t mac[IEEE80211_ADDR_LEN]) 655{ 656 struct urtwn_softc *sc = ic->ic_softc; 657 struct urtwn_vap *uvp; 658 struct ieee80211vap *vap; 659 660 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 661 return (NULL); 662 663 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 664 vap = &uvp->vap; 665 /* enable s/w bmiss handling for sta mode */ 666 667 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 668 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 669 /* out of memory */ 670 free(uvp, M_80211_VAP); 671 return (NULL); 672 } 673 674 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 675 urtwn_init_beacon(sc, uvp); 676 677 /* override state transition machine */ 678 uvp->newstate = vap->iv_newstate; 679 vap->iv_newstate = urtwn_newstate; 680 vap->iv_update_beacon = urtwn_update_beacon; 681 vap->iv_key_alloc = urtwn_key_alloc; 682 vap->iv_key_set = urtwn_key_set; 683 vap->iv_key_delete = urtwn_key_delete; 684 if (opmode == IEEE80211_M_IBSS) { 685 uvp->recv_mgmt = vap->iv_recv_mgmt; 686 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 687 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 688 } 689 690 if (URTWN_CHIP_HAS_RATECTL(sc)) 691 ieee80211_ratectl_init(vap); 692 /* complete setup */ 693 ieee80211_vap_attach(vap, ieee80211_media_change, 694 ieee80211_media_status, mac); 695 ic->ic_opmode = opmode; 696 return (vap); 697} 698 699static void 700urtwn_vap_delete(struct ieee80211vap *vap) 701{ 702 struct ieee80211com *ic = vap->iv_ic; 703 struct urtwn_softc *sc = ic->ic_softc; 704 struct urtwn_vap *uvp = URTWN_VAP(vap); 705 706 if (uvp->bcn_mbuf != NULL) 707 m_freem(uvp->bcn_mbuf); 708 if (vap->iv_opmode == IEEE80211_M_IBSS) 709 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 710 if (URTWN_CHIP_HAS_RATECTL(sc)) 711 ieee80211_ratectl_deinit(vap); 712 ieee80211_vap_detach(vap); 713 free(uvp, M_80211_VAP); 714} 715 716static struct mbuf * 717urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 718{ 719 struct ieee80211com *ic = &sc->sc_ic; 720 struct ieee80211_frame *wh; 721 struct mbuf *m; 722 struct r92c_rx_stat *stat; 723 uint32_t rxdw0, rxdw3; 724 uint8_t rate, cipher; 725 int8_t rssi = 0; 726 int infosz; 727 728 /* 729 * don't pass packets to the ieee80211 framework if the driver isn't 730 * RUNNING. 731 */ 732 if (!(sc->sc_flags & URTWN_RUNNING)) 733 return (NULL); 734 735 stat = (struct r92c_rx_stat *)buf; 736 rxdw0 = le32toh(stat->rxdw0); 737 rxdw3 = le32toh(stat->rxdw3); 738 739 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 740 /* 741 * This should not happen since we setup our Rx filter 742 * to not receive these frames. 743 */ 744 counter_u64_add(ic->ic_ierrors, 1); 745 return (NULL); 746 } 747 if (pktlen < sizeof(struct ieee80211_frame_ack) || 748 pktlen > MCLBYTES) { 749 counter_u64_add(ic->ic_ierrors, 1); 750 return (NULL); 751 } 752 753 rate = MS(rxdw3, R92C_RXDW3_RATE); 754 cipher = MS(rxdw0, R92C_RXDW0_CIPHER); 755 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 756 757 /* Get RSSI from PHY status descriptor if present. */ 758 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 759 if (sc->chip & URTWN_CHIP_88E) 760 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 761 else 762 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 763 /* Update our average RSSI. */ 764 urtwn_update_avgrssi(sc, rate, rssi); 765 } 766 767 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 768 if (m == NULL) { 769 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 770 return (NULL); 771 } 772 773 /* Finalize mbuf. */ 774 memcpy(mtod(m, uint8_t *), (uint8_t *)&stat[1] + infosz, pktlen); 775 m->m_pkthdr.len = m->m_len = pktlen; 776 wh = mtod(m, struct ieee80211_frame *); 777 778 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 779 cipher != R92C_CAM_ALGO_NONE) { 780 m->m_flags |= M_WEP; 781 } 782 783 if (ieee80211_radiotap_active(ic)) { 784 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 785 786 tap->wr_flags = 0; 787 /* Map HW rate index to 802.11 rate. */ 788 if (!(rxdw3 & R92C_RXDW3_HT)) { 789 tap->wr_rate = ridx2rate[rate]; 790 } else if (rate >= 12) { /* MCS0~15. */ 791 /* Bit 7 set means HT MCS instead of rate. */ 792 tap->wr_rate = 0x80 | (rate - 12); 793 } 794 tap->wr_dbm_antsignal = rssi; 795 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 796 } 797 798 *rssi_p = rssi; 799 800 return (m); 801} 802 803static struct mbuf * 804urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 805 int8_t *nf) 806{ 807 struct urtwn_softc *sc = data->sc; 808 struct ieee80211com *ic = &sc->sc_ic; 809 struct r92c_rx_stat *stat; 810 uint8_t *buf; 811 int len; 812 813 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 814 815 if (len < sizeof(*stat)) { 816 counter_u64_add(ic->ic_ierrors, 1); 817 return (NULL); 818 } 819 820 buf = data->buf; 821 stat = (struct r92c_rx_stat *)buf; 822 823 if (sc->chip & URTWN_CHIP_88E) { 824 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 825 826 switch (report_sel) { 827 case R88E_RXDW3_RPT_RX: 828 return (urtwn_rxeof(sc, buf, len, rssi, nf)); 829 case R88E_RXDW3_RPT_TX1: 830 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 831 break; 832 default: 833 DPRINTFN(7, "case %d was not handled\n", report_sel); 834 break; 835 } 836 } else 837 return (urtwn_rxeof(sc, buf, len, rssi, nf)); 838 839 return (NULL); 840} 841 842static struct mbuf * 843urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len, int *rssi, 844 int8_t *nf) 845{ 846 struct r92c_rx_stat *stat; 847 struct mbuf *m, *m0 = NULL, *prevm = NULL; 848 uint32_t rxdw0; 849 int totlen, pktlen, infosz, npkts; 850 851 /* Get the number of encapsulated frames. */ 852 stat = (struct r92c_rx_stat *)buf; 853 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 854 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 855 856 /* Process all of them. */ 857 while (npkts-- > 0) { 858 if (len < sizeof(*stat)) 859 break; 860 stat = (struct r92c_rx_stat *)buf; 861 rxdw0 = le32toh(stat->rxdw0); 862 863 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 864 if (pktlen == 0) 865 break; 866 867 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 868 869 /* Make sure everything fits in xfer. */ 870 totlen = sizeof(*stat) + infosz + pktlen; 871 if (totlen > len) 872 break; 873 874 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 875 if (m0 == NULL) 876 m0 = m; 877 if (prevm == NULL) 878 prevm = m; 879 else { 880 prevm->m_next = m; 881 prevm = m; 882 } 883 884 /* Next chunk is 128-byte aligned. */ 885 totlen = (totlen + 127) & ~127; 886 buf += totlen; 887 len -= totlen; 888 } 889 890 return (m0); 891} 892 893static void 894urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 895{ 896 struct r88e_tx_rpt_ccx *rpt = arg; 897 struct ieee80211vap *vap; 898 struct ieee80211_node *ni; 899 uint8_t macid; 900 int ntries; 901 902 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 903 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 904 905 URTWN_NT_LOCK(sc); 906 ni = sc->node_list[macid]; 907 if (ni != NULL) { 908 vap = ni->ni_vap; 909 910 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 911 ieee80211_ratectl_tx_complete(vap, ni, 912 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 913 } else { 914 ieee80211_ratectl_tx_complete(vap, ni, 915 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 916 } 917 } else 918 DPRINTFN(8, "macid %d, ni is NULL\n", macid); 919 URTWN_NT_UNLOCK(sc); 920} 921 922static void 923urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 924{ 925 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 926 struct ieee80211com *ic = &sc->sc_ic; 927 struct ieee80211_frame_min *wh; 928 struct ieee80211_node *ni; 929 struct mbuf *m = NULL, *next; 930 struct urtwn_data *data; 931 int8_t nf; 932 int rssi = 1; 933 934 URTWN_ASSERT_LOCKED(sc); 935 936 switch (USB_GET_STATE(xfer)) { 937 case USB_ST_TRANSFERRED: 938 data = STAILQ_FIRST(&sc->sc_rx_active); 939 if (data == NULL) 940 goto tr_setup; 941 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 942 m = urtwn_report_intr(xfer, data, &rssi, &nf); 943 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 944 /* FALLTHROUGH */ 945 case USB_ST_SETUP: 946tr_setup: 947 data = STAILQ_FIRST(&sc->sc_rx_inactive); 948 if (data == NULL) { 949 KASSERT(m == NULL, ("mbuf isn't NULL")); 950 return; 951 } 952 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 953 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 954 usbd_xfer_set_frame_data(xfer, 0, data->buf, 955 usbd_xfer_max_len(xfer)); 956 usbd_transfer_submit(xfer); 957 958 /* 959 * To avoid LOR we should unlock our private mutex here to call 960 * ieee80211_input() because here is at the end of a USB 961 * callback and safe to unlock. 962 */ 963 URTWN_UNLOCK(sc); 964 while (m != NULL) { 965 next = m->m_next; 966 m->m_next = NULL; 967 wh = mtod(m, struct ieee80211_frame_min *); 968 if (m->m_len >= sizeof(*wh)) 969 ni = ieee80211_find_rxnode(ic, wh); 970 else 971 ni = NULL; 972 nf = URTWN_NOISE_FLOOR; 973 if (ni != NULL) { 974 (void)ieee80211_input(ni, m, rssi - nf, nf); 975 ieee80211_free_node(ni); 976 } else { 977 (void)ieee80211_input_all(ic, m, rssi - nf, 978 nf); 979 } 980 m = next; 981 } 982 URTWN_LOCK(sc); 983 break; 984 default: 985 /* needs it to the inactive queue due to a error. */ 986 data = STAILQ_FIRST(&sc->sc_rx_active); 987 if (data != NULL) { 988 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 989 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 990 } 991 if (error != USB_ERR_CANCELLED) { 992 usbd_xfer_set_stall(xfer); 993 counter_u64_add(ic->ic_ierrors, 1); 994 goto tr_setup; 995 } 996 break; 997 } 998} 999 1000static void 1001urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 1002{ 1003 1004 URTWN_ASSERT_LOCKED(sc); 1005 1006 if (data->ni != NULL) /* not a beacon frame */ 1007 ieee80211_tx_complete(data->ni, data->m, status); 1008 1009 data->ni = NULL; 1010 data->m = NULL; 1011 1012 sc->sc_txtimer = 0; 1013 1014 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 1015} 1016 1017static int 1018urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1019 int ndata, int maxsz) 1020{ 1021 int i, error; 1022 1023 for (i = 0; i < ndata; i++) { 1024 struct urtwn_data *dp = &data[i]; 1025 dp->sc = sc; 1026 dp->m = NULL; 1027 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1028 if (dp->buf == NULL) { 1029 device_printf(sc->sc_dev, 1030 "could not allocate buffer\n"); 1031 error = ENOMEM; 1032 goto fail; 1033 } 1034 dp->ni = NULL; 1035 } 1036 1037 return (0); 1038fail: 1039 urtwn_free_list(sc, data, ndata); 1040 return (error); 1041} 1042 1043static int 1044urtwn_alloc_rx_list(struct urtwn_softc *sc) 1045{ 1046 int error, i; 1047 1048 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1049 URTWN_RXBUFSZ); 1050 if (error != 0) 1051 return (error); 1052 1053 STAILQ_INIT(&sc->sc_rx_active); 1054 STAILQ_INIT(&sc->sc_rx_inactive); 1055 1056 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1057 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1058 1059 return (0); 1060} 1061 1062static int 1063urtwn_alloc_tx_list(struct urtwn_softc *sc) 1064{ 1065 int error, i; 1066 1067 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1068 URTWN_TXBUFSZ); 1069 if (error != 0) 1070 return (error); 1071 1072 STAILQ_INIT(&sc->sc_tx_active); 1073 STAILQ_INIT(&sc->sc_tx_inactive); 1074 STAILQ_INIT(&sc->sc_tx_pending); 1075 1076 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1077 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1078 1079 return (0); 1080} 1081 1082static void 1083urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1084{ 1085 int i; 1086 1087 for (i = 0; i < ndata; i++) { 1088 struct urtwn_data *dp = &data[i]; 1089 1090 if (dp->buf != NULL) { 1091 free(dp->buf, M_USBDEV); 1092 dp->buf = NULL; 1093 } 1094 if (dp->ni != NULL) { 1095 ieee80211_free_node(dp->ni); 1096 dp->ni = NULL; 1097 } 1098 } 1099} 1100 1101static void 1102urtwn_free_rx_list(struct urtwn_softc *sc) 1103{ 1104 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1105} 1106 1107static void 1108urtwn_free_tx_list(struct urtwn_softc *sc) 1109{ 1110 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1111} 1112 1113static void 1114urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1115{ 1116 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1117 struct urtwn_data *data; 1118 1119 URTWN_ASSERT_LOCKED(sc); 1120 1121 switch (USB_GET_STATE(xfer)){ 1122 case USB_ST_TRANSFERRED: 1123 data = STAILQ_FIRST(&sc->sc_tx_active); 1124 if (data == NULL) 1125 goto tr_setup; 1126 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1127 urtwn_txeof(sc, data, 0); 1128 /* FALLTHROUGH */ 1129 case USB_ST_SETUP: 1130tr_setup: 1131 data = STAILQ_FIRST(&sc->sc_tx_pending); 1132 if (data == NULL) { 1133 DPRINTF("%s: empty pending queue\n", __func__); 1134 goto finish; 1135 } 1136 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1137 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1138 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1139 usbd_transfer_submit(xfer); 1140 break; 1141 default: 1142 data = STAILQ_FIRST(&sc->sc_tx_active); 1143 if (data == NULL) 1144 goto tr_setup; 1145 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1146 urtwn_txeof(sc, data, 1); 1147 if (error != USB_ERR_CANCELLED) { 1148 usbd_xfer_set_stall(xfer); 1149 goto tr_setup; 1150 } 1151 break; 1152 } 1153finish: 1154 /* Kick-start more transmit */ 1155 urtwn_start(sc); 1156} 1157 1158static struct urtwn_data * 1159_urtwn_getbuf(struct urtwn_softc *sc) 1160{ 1161 struct urtwn_data *bf; 1162 1163 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1164 if (bf != NULL) 1165 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1166 else 1167 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 1168 return (bf); 1169} 1170 1171static struct urtwn_data * 1172urtwn_getbuf(struct urtwn_softc *sc) 1173{ 1174 struct urtwn_data *bf; 1175 1176 URTWN_ASSERT_LOCKED(sc); 1177 1178 bf = _urtwn_getbuf(sc); 1179 if (bf == NULL) 1180 DPRINTF("%s: stop queue\n", __func__); 1181 return (bf); 1182} 1183 1184static usb_error_t 1185urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1186 int len) 1187{ 1188 usb_device_request_t req; 1189 1190 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1191 req.bRequest = R92C_REQ_REGS; 1192 USETW(req.wValue, addr); 1193 USETW(req.wIndex, 0); 1194 USETW(req.wLength, len); 1195 return (urtwn_do_request(sc, &req, buf)); 1196} 1197 1198static usb_error_t 1199urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1200{ 1201 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1202} 1203 1204static usb_error_t 1205urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1206{ 1207 val = htole16(val); 1208 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1209} 1210 1211static usb_error_t 1212urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1213{ 1214 val = htole32(val); 1215 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1216} 1217 1218static usb_error_t 1219urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1220 int len) 1221{ 1222 usb_device_request_t req; 1223 1224 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1225 req.bRequest = R92C_REQ_REGS; 1226 USETW(req.wValue, addr); 1227 USETW(req.wIndex, 0); 1228 USETW(req.wLength, len); 1229 return (urtwn_do_request(sc, &req, buf)); 1230} 1231 1232static uint8_t 1233urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1234{ 1235 uint8_t val; 1236 1237 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1238 return (0xff); 1239 return (val); 1240} 1241 1242static uint16_t 1243urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1244{ 1245 uint16_t val; 1246 1247 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1248 return (0xffff); 1249 return (le16toh(val)); 1250} 1251 1252static uint32_t 1253urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1254{ 1255 uint32_t val; 1256 1257 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1258 return (0xffffffff); 1259 return (le32toh(val)); 1260} 1261 1262static int 1263urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1264{ 1265 struct r92c_fw_cmd cmd; 1266 usb_error_t error; 1267 int ntries; 1268 1269 /* Wait for current FW box to be empty. */ 1270 for (ntries = 0; ntries < 100; ntries++) { 1271 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1272 break; 1273 urtwn_ms_delay(sc); 1274 } 1275 if (ntries == 100) { 1276 device_printf(sc->sc_dev, 1277 "could not send firmware command\n"); 1278 return (ETIMEDOUT); 1279 } 1280 memset(&cmd, 0, sizeof(cmd)); 1281 cmd.id = id; 1282 if (len > 3) 1283 cmd.id |= R92C_CMD_FLAG_EXT; 1284 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1285 memcpy(cmd.msg, buf, len); 1286 1287 /* Write the first word last since that will trigger the FW. */ 1288 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1289 (uint8_t *)&cmd + 4, 2); 1290 if (error != USB_ERR_NORMAL_COMPLETION) 1291 return (EIO); 1292 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1293 (uint8_t *)&cmd + 0, 4); 1294 if (error != USB_ERR_NORMAL_COMPLETION) 1295 return (EIO); 1296 1297 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1298 return (0); 1299} 1300 1301static void 1302urtwn_cmdq_cb(void *arg, int pending) 1303{ 1304 struct urtwn_softc *sc = arg; 1305 struct urtwn_cmdq *item; 1306 1307 /* 1308 * Device must be powered on (via urtwn_power_on()) 1309 * before any command may be sent. 1310 */ 1311 URTWN_LOCK(sc); 1312 if (!(sc->sc_flags & URTWN_RUNNING)) { 1313 URTWN_UNLOCK(sc); 1314 return; 1315 } 1316 1317 URTWN_CMDQ_LOCK(sc); 1318 while (sc->cmdq[sc->cmdq_first].func != NULL) { 1319 item = &sc->cmdq[sc->cmdq_first]; 1320 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE; 1321 URTWN_CMDQ_UNLOCK(sc); 1322 1323 item->func(sc, &item->data); 1324 1325 URTWN_CMDQ_LOCK(sc); 1326 memset(item, 0, sizeof (*item)); 1327 } 1328 URTWN_CMDQ_UNLOCK(sc); 1329 URTWN_UNLOCK(sc); 1330} 1331 1332static int 1333urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len, 1334 CMD_FUNC_PROTO) 1335{ 1336 struct ieee80211com *ic = &sc->sc_ic; 1337 1338 KASSERT(len <= sizeof(union sec_param), ("buffer overflow")); 1339 1340 URTWN_CMDQ_LOCK(sc); 1341 if (sc->cmdq[sc->cmdq_last].func != NULL) { 1342 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__); 1343 URTWN_CMDQ_UNLOCK(sc); 1344 1345 return (EAGAIN); 1346 } 1347 1348 if (ptr != NULL) 1349 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len); 1350 sc->cmdq[sc->cmdq_last].func = func; 1351 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE; 1352 URTWN_CMDQ_UNLOCK(sc); 1353 1354 ieee80211_runtask(ic, &sc->cmdq_task); 1355 1356 return (0); 1357} 1358 1359static __inline void 1360urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1361{ 1362 1363 sc->sc_rf_write(sc, chain, addr, val); 1364} 1365 1366static void 1367urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1368 uint32_t val) 1369{ 1370 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1371 SM(R92C_LSSI_PARAM_ADDR, addr) | 1372 SM(R92C_LSSI_PARAM_DATA, val)); 1373} 1374 1375static void 1376urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1377uint32_t val) 1378{ 1379 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1380 SM(R88E_LSSI_PARAM_ADDR, addr) | 1381 SM(R92C_LSSI_PARAM_DATA, val)); 1382} 1383 1384static uint32_t 1385urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1386{ 1387 uint32_t reg[R92C_MAX_CHAINS], val; 1388 1389 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1390 if (chain != 0) 1391 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1392 1393 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1394 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1395 urtwn_ms_delay(sc); 1396 1397 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1398 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1399 R92C_HSSI_PARAM2_READ_EDGE); 1400 urtwn_ms_delay(sc); 1401 1402 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1403 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1404 urtwn_ms_delay(sc); 1405 1406 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1407 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1408 else 1409 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1410 return (MS(val, R92C_LSSI_READBACK_DATA)); 1411} 1412 1413static int 1414urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1415{ 1416 usb_error_t error; 1417 int ntries; 1418 1419 error = urtwn_write_4(sc, R92C_LLT_INIT, 1420 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1421 SM(R92C_LLT_INIT_ADDR, addr) | 1422 SM(R92C_LLT_INIT_DATA, data)); 1423 if (error != USB_ERR_NORMAL_COMPLETION) 1424 return (EIO); 1425 /* Wait for write operation to complete. */ 1426 for (ntries = 0; ntries < 20; ntries++) { 1427 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1428 R92C_LLT_INIT_OP_NO_ACTIVE) 1429 return (0); 1430 urtwn_ms_delay(sc); 1431 } 1432 return (ETIMEDOUT); 1433} 1434 1435static int 1436urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1437{ 1438 uint32_t reg; 1439 usb_error_t error; 1440 int ntries; 1441 1442 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1443 return (EFAULT); 1444 1445 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1446 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1447 reg &= ~R92C_EFUSE_CTRL_VALID; 1448 1449 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1450 if (error != USB_ERR_NORMAL_COMPLETION) 1451 return (EIO); 1452 /* Wait for read operation to complete. */ 1453 for (ntries = 0; ntries < 100; ntries++) { 1454 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1455 if (reg & R92C_EFUSE_CTRL_VALID) 1456 break; 1457 urtwn_ms_delay(sc); 1458 } 1459 if (ntries == 100) { 1460 device_printf(sc->sc_dev, 1461 "could not read efuse byte at address 0x%x\n", 1462 sc->last_rom_addr); 1463 return (ETIMEDOUT); 1464 } 1465 1466 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1467 sc->last_rom_addr++; 1468 1469 return (0); 1470} 1471 1472static int 1473urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1474 uint8_t msk) 1475{ 1476 uint8_t reg; 1477 int i, error; 1478 1479 for (i = 0; i < 4; i++) { 1480 if (msk & (1 << i)) 1481 continue; 1482 error = urtwn_efuse_read_next(sc, ®); 1483 if (error != 0) 1484 return (error); 1485 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2, reg); 1486 rom[off * 8 + i * 2 + 0] = reg; 1487 1488 error = urtwn_efuse_read_next(sc, ®); 1489 if (error != 0) 1490 return (error); 1491 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2 + 1, reg); 1492 rom[off * 8 + i * 2 + 1] = reg; 1493 } 1494 1495 return (0); 1496} 1497 1498#ifdef URTWN_DEBUG 1499static void 1500urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1501{ 1502 int i; 1503 1504 /* Dump ROM contents. */ 1505 device_printf(sc->sc_dev, "%s:", __func__); 1506 for (i = 0; i < size; i++) { 1507 if (i % 32 == 0) 1508 printf("\n%03X: ", i); 1509 else if (i % 4 == 0) 1510 printf(" "); 1511 1512 printf("%02X", rom[i]); 1513 } 1514 printf("\n"); 1515} 1516#endif 1517 1518static int 1519urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1520{ 1521#define URTWN_CHK(res) do { \ 1522 if ((error = res) != 0) \ 1523 goto end; \ 1524} while(0) 1525 uint8_t msk, off, reg; 1526 int error; 1527 1528 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1529 1530 /* Read full ROM image. */ 1531 sc->last_rom_addr = 0; 1532 memset(rom, 0xff, size); 1533 1534 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1535 while (reg != 0xff) { 1536 /* check for extended header */ 1537 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1538 off = reg >> 5; 1539 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1540 1541 if ((reg & 0x0f) != 0x0f) 1542 off = ((reg & 0xf0) >> 1) | off; 1543 else 1544 continue; 1545 } else 1546 off = reg >> 4; 1547 msk = reg & 0xf; 1548 1549 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1550 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1551 } 1552 1553end: 1554 1555#ifdef URTWN_DEBUG 1556 if (urtwn_debug >= 2) 1557 urtwn_dump_rom_contents(sc, rom, size); 1558#endif 1559 1560 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1561 1562 if (error != 0) { 1563 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1564 __func__); 1565 } 1566 1567 return (error); 1568#undef URTWN_CHK 1569} 1570 1571static int 1572urtwn_efuse_switch_power(struct urtwn_softc *sc) 1573{ 1574 usb_error_t error; 1575 uint32_t reg; 1576 1577 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1578 if (error != USB_ERR_NORMAL_COMPLETION) 1579 return (EIO); 1580 1581 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1582 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1583 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1584 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1585 if (error != USB_ERR_NORMAL_COMPLETION) 1586 return (EIO); 1587 } 1588 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1589 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1590 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1591 reg | R92C_SYS_FUNC_EN_ELDR); 1592 if (error != USB_ERR_NORMAL_COMPLETION) 1593 return (EIO); 1594 } 1595 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1596 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1597 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1598 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1599 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1600 if (error != USB_ERR_NORMAL_COMPLETION) 1601 return (EIO); 1602 } 1603 1604 return (0); 1605} 1606 1607static int 1608urtwn_read_chipid(struct urtwn_softc *sc) 1609{ 1610 uint32_t reg; 1611 1612 if (sc->chip & URTWN_CHIP_88E) 1613 return (0); 1614 1615 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1616 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1617 return (EIO); 1618 1619 if (reg & R92C_SYS_CFG_TYPE_92C) { 1620 sc->chip |= URTWN_CHIP_92C; 1621 /* Check if it is a castrated 8192C. */ 1622 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1623 R92C_HPON_FSM_CHIP_BONDING_ID) == 1624 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1625 sc->chip |= URTWN_CHIP_92C_1T2R; 1626 } 1627 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1628 sc->chip |= URTWN_CHIP_UMC; 1629 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1630 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1631 } 1632 return (0); 1633} 1634 1635static int 1636urtwn_read_rom(struct urtwn_softc *sc) 1637{ 1638 struct r92c_rom *rom = &sc->rom.r92c_rom; 1639 int error; 1640 1641 /* Read full ROM image. */ 1642 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1643 if (error != 0) 1644 return (error); 1645 1646 /* XXX Weird but this is what the vendor driver does. */ 1647 sc->last_rom_addr = 0x1fa; 1648 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1649 if (error != 0) 1650 return (error); 1651 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1652 1653 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1654 1655 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1656 DPRINTF("regulatory type=%d\n", sc->regulatory); 1657 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1658 1659 sc->sc_rf_write = urtwn_r92c_rf_write; 1660 sc->sc_power_on = urtwn_r92c_power_on; 1661 1662 return (0); 1663} 1664 1665static int 1666urtwn_r88e_read_rom(struct urtwn_softc *sc) 1667{ 1668 uint8_t *rom = sc->rom.r88e_rom; 1669 uint16_t addr; 1670 int error, i; 1671 1672 error = urtwn_efuse_read(sc, rom, sizeof(sc->rom.r88e_rom)); 1673 if (error != 0) 1674 return (error); 1675 1676 addr = 0x10; 1677 for (i = 0; i < 6; i++) 1678 sc->cck_tx_pwr[i] = rom[addr++]; 1679 for (i = 0; i < 5; i++) 1680 sc->ht40_tx_pwr[i] = rom[addr++]; 1681 sc->bw20_tx_pwr_diff = (rom[addr] & 0xf0) >> 4; 1682 if (sc->bw20_tx_pwr_diff & 0x08) 1683 sc->bw20_tx_pwr_diff |= 0xf0; 1684 sc->ofdm_tx_pwr_diff = (rom[addr] & 0xf); 1685 if (sc->ofdm_tx_pwr_diff & 0x08) 1686 sc->ofdm_tx_pwr_diff |= 0xf0; 1687 sc->regulatory = MS(rom[0xc1], R92C_ROM_RF1_REGULATORY); 1688 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &rom[0xd7]); 1689 1690 sc->sc_rf_write = urtwn_r88e_rf_write; 1691 sc->sc_power_on = urtwn_r88e_power_on; 1692 1693 return (0); 1694} 1695 1696/* 1697 * Initialize rate adaptation in firmware. 1698 */ 1699static int 1700urtwn_ra_init(struct urtwn_softc *sc) 1701{ 1702 struct ieee80211com *ic = &sc->sc_ic; 1703 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1704 struct ieee80211_node *ni; 1705 struct ieee80211_rateset *rs; 1706 struct r92c_fw_cmd_macid_cfg cmd; 1707 uint32_t rates, basicrates; 1708 uint8_t mode; 1709 int maxrate, maxbasicrate, error, i, j; 1710 1711 ni = ieee80211_ref_node(vap->iv_bss); 1712 rs = &ni->ni_rates; 1713 1714 /* Get normal and basic rates mask. */ 1715 rates = basicrates = 0; 1716 maxrate = maxbasicrate = 0; 1717 for (i = 0; i < rs->rs_nrates; i++) { 1718 /* Convert 802.11 rate to HW rate index. */ 1719 for (j = 0; j < nitems(ridx2rate); j++) 1720 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1721 ridx2rate[j]) 1722 break; 1723 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1724 continue; 1725 rates |= 1 << j; 1726 if (j > maxrate) 1727 maxrate = j; 1728 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1729 basicrates |= 1 << j; 1730 if (j > maxbasicrate) 1731 maxbasicrate = j; 1732 } 1733 } 1734 if (ic->ic_curmode == IEEE80211_MODE_11B) 1735 mode = R92C_RAID_11B; 1736 else 1737 mode = R92C_RAID_11BG; 1738 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1739 mode, rates, basicrates); 1740 1741 /* Set rates mask for group addressed frames. */ 1742 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1743 cmd.mask = htole32(mode << 28 | basicrates); 1744 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1745 if (error != 0) { 1746 ieee80211_free_node(ni); 1747 device_printf(sc->sc_dev, 1748 "could not add broadcast station\n"); 1749 return (error); 1750 } 1751 /* Set initial MRR rate. */ 1752 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1753 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1754 maxbasicrate); 1755 1756 /* Set rates mask for unicast frames. */ 1757 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1758 cmd.mask = htole32(mode << 28 | rates); 1759 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1760 if (error != 0) { 1761 ieee80211_free_node(ni); 1762 device_printf(sc->sc_dev, "could not add BSS station\n"); 1763 return (error); 1764 } 1765 /* Set initial MRR rate. */ 1766 DPRINTF("maxrate=%d\n", maxrate); 1767 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1768 maxrate); 1769 1770 /* Indicate highest supported rate. */ 1771 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1772 ieee80211_free_node(ni); 1773 1774 return (0); 1775} 1776 1777static void 1778urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1779{ 1780 struct r92c_tx_desc *txd = &uvp->bcn_desc; 1781 1782 txd->txdw0 = htole32( 1783 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 1784 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1785 txd->txdw1 = htole32( 1786 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 1787 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1788 1789 if (sc->chip & URTWN_CHIP_88E) { 1790 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 1791 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 1792 } else { 1793 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 1794 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 1795 } 1796 1797 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 1798 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 1799} 1800 1801static int 1802urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 1803{ 1804 struct ieee80211vap *vap = ni->ni_vap; 1805 struct urtwn_vap *uvp = URTWN_VAP(vap); 1806 struct mbuf *m; 1807 int error; 1808 1809 URTWN_ASSERT_LOCKED(sc); 1810 1811 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 1812 return (EINVAL); 1813 1814 m = ieee80211_beacon_alloc(ni); 1815 if (m == NULL) { 1816 device_printf(sc->sc_dev, 1817 "%s: could not allocate beacon frame\n", __func__); 1818 return (ENOMEM); 1819 } 1820 1821 if (uvp->bcn_mbuf != NULL) 1822 m_freem(uvp->bcn_mbuf); 1823 1824 uvp->bcn_mbuf = m; 1825 1826 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1827 return (error); 1828 1829 /* XXX bcnq stuck workaround */ 1830 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1831 return (error); 1832 1833 return (0); 1834} 1835 1836static void 1837urtwn_update_beacon(struct ieee80211vap *vap, int item) 1838{ 1839 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1840 struct urtwn_vap *uvp = URTWN_VAP(vap); 1841 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 1842 struct ieee80211_node *ni = vap->iv_bss; 1843 int mcast = 0; 1844 1845 URTWN_LOCK(sc); 1846 if (uvp->bcn_mbuf == NULL) { 1847 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 1848 if (uvp->bcn_mbuf == NULL) { 1849 device_printf(sc->sc_dev, 1850 "%s: could not allocate beacon frame\n", __func__); 1851 URTWN_UNLOCK(sc); 1852 return; 1853 } 1854 } 1855 URTWN_UNLOCK(sc); 1856 1857 if (item == IEEE80211_BEACON_TIM) 1858 mcast = 1; /* XXX */ 1859 1860 setbit(bo->bo_flags, item); 1861 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 1862 1863 URTWN_LOCK(sc); 1864 urtwn_tx_beacon(sc, uvp); 1865 URTWN_UNLOCK(sc); 1866} 1867 1868/* 1869 * Push a beacon frame into the chip. Beacon will 1870 * be repeated by the chip every R92C_BCN_INTERVAL. 1871 */ 1872static int 1873urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1874{ 1875 struct r92c_tx_desc *desc = &uvp->bcn_desc; 1876 struct urtwn_data *bf; 1877 1878 URTWN_ASSERT_LOCKED(sc); 1879 1880 bf = urtwn_getbuf(sc); 1881 if (bf == NULL) 1882 return (ENOMEM); 1883 1884 memcpy(bf->buf, desc, sizeof(*desc)); 1885 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 1886 1887 sc->sc_txtimer = 5; 1888 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1889 1890 return (0); 1891} 1892 1893static int 1894urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 1895 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1896{ 1897 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1898 uint8_t i; 1899 1900 if (!(&vap->iv_nw_keys[0] <= k && 1901 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 1902 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 1903 URTWN_LOCK(sc); 1904 /* 1905 * First 4 slots for group keys, 1906 * what is left - for pairwise. 1907 * XXX incompatible with IBSS RSN. 1908 */ 1909 for (i = IEEE80211_WEP_NKID; 1910 i < R92C_CAM_ENTRY_COUNT; i++) { 1911 if ((sc->keys_bmap & (1 << i)) == 0) { 1912 sc->keys_bmap |= 1 << i; 1913 *keyix = i; 1914 break; 1915 } 1916 } 1917 URTWN_UNLOCK(sc); 1918 if (i == R92C_CAM_ENTRY_COUNT) { 1919 device_printf(sc->sc_dev, 1920 "%s: no free space in the key table\n", 1921 __func__); 1922 return 0; 1923 } 1924 } else 1925 *keyix = 0; 1926 } else { 1927 *keyix = k - vap->iv_nw_keys; 1928 } 1929 *rxkeyix = *keyix; 1930 return 1; 1931} 1932 1933static void 1934urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data) 1935{ 1936 struct ieee80211_key *k = &data->key; 1937 uint8_t algo, keyid; 1938 int i, error; 1939 1940 if (k->wk_keyix < IEEE80211_WEP_NKID) 1941 keyid = k->wk_keyix; 1942 else 1943 keyid = 0; 1944 1945 /* Map net80211 cipher to HW crypto algorithm. */ 1946 switch (k->wk_cipher->ic_cipher) { 1947 case IEEE80211_CIPHER_WEP: 1948 if (k->wk_keylen < 8) 1949 algo = R92C_CAM_ALGO_WEP40; 1950 else 1951 algo = R92C_CAM_ALGO_WEP104; 1952 break; 1953 case IEEE80211_CIPHER_TKIP: 1954 algo = R92C_CAM_ALGO_TKIP; 1955 break; 1956 case IEEE80211_CIPHER_AES_CCM: 1957 algo = R92C_CAM_ALGO_AES; 1958 break; 1959 default: 1960 device_printf(sc->sc_dev, "%s: undefined cipher %d\n", 1961 __func__, k->wk_cipher->ic_cipher); 1962 return; 1963 } 1964 1965 DPRINTFN(9, "keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, " 1966 "macaddr %s\n", k->wk_keyix, keyid, k->wk_cipher->ic_cipher, algo, 1967 k->wk_flags, k->wk_keylen, ether_sprintf(k->wk_macaddr)); 1968 1969 /* Write key. */ 1970 for (i = 0; i < 4; i++) { 1971 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 1972 LE_READ_4(&k->wk_key[i * 4])); 1973 if (error != 0) 1974 goto fail; 1975 } 1976 1977 /* Write CTL0 last since that will validate the CAM entry. */ 1978 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 1979 LE_READ_4(&k->wk_macaddr[2])); 1980 if (error != 0) 1981 goto fail; 1982 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 1983 SM(R92C_CAM_ALGO, algo) | 1984 SM(R92C_CAM_KEYID, keyid) | 1985 SM(R92C_CAM_MACLO, LE_READ_2(&k->wk_macaddr[0])) | 1986 R92C_CAM_VALID); 1987 if (error != 0) 1988 goto fail; 1989 1990 return; 1991 1992fail: 1993 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error); 1994} 1995 1996static void 1997urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data) 1998{ 1999 struct ieee80211_key *k = &data->key; 2000 int i; 2001 2002 DPRINTFN(9, "keyix %d, flags %04X, macaddr %s\n", 2003 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr)); 2004 2005 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0); 2006 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0); 2007 2008 /* Clear key. */ 2009 for (i = 0; i < 4; i++) 2010 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0); 2011 sc->keys_bmap &= ~(1 << k->wk_keyix); 2012} 2013 2014static int 2015urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 2016{ 2017 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2018 2019 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2020 /* Not for us. */ 2021 return (1); 2022 } 2023 2024 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb)); 2025} 2026 2027static int 2028urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2029{ 2030 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2031 2032 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2033 /* Not for us. */ 2034 return (1); 2035 } 2036 2037 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb)); 2038} 2039 2040static void 2041urtwn_tsf_task_adhoc(void *arg, int pending) 2042{ 2043 struct ieee80211vap *vap = arg; 2044 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2045 struct ieee80211_node *ni; 2046 uint32_t reg; 2047 2048 URTWN_LOCK(sc); 2049 ni = ieee80211_ref_node(vap->iv_bss); 2050 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 2051 2052 /* Accept beacons with the same BSSID. */ 2053 urtwn_set_rx_bssid_all(sc, 0); 2054 2055 /* Enable synchronization. */ 2056 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 2057 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2058 2059 /* Synchronize. */ 2060 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 2061 2062 /* Disable synchronization. */ 2063 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 2064 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2065 2066 /* Remove beacon filter. */ 2067 urtwn_set_rx_bssid_all(sc, 1); 2068 2069 /* Enable beaconing. */ 2070 urtwn_write_1(sc, R92C_MBID_NUM, 2071 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2072 reg |= R92C_BCN_CTRL_EN_BCN; 2073 2074 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2075 ieee80211_free_node(ni); 2076 URTWN_UNLOCK(sc); 2077} 2078 2079static void 2080urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 2081{ 2082 struct ieee80211com *ic = &sc->sc_ic; 2083 struct urtwn_vap *uvp = URTWN_VAP(vap); 2084 2085 /* Reset TSF. */ 2086 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2087 2088 switch (vap->iv_opmode) { 2089 case IEEE80211_M_STA: 2090 /* Enable TSF synchronization. */ 2091 urtwn_write_1(sc, R92C_BCN_CTRL, 2092 urtwn_read_1(sc, R92C_BCN_CTRL) & 2093 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 2094 break; 2095 case IEEE80211_M_IBSS: 2096 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 2097 break; 2098 case IEEE80211_M_HOSTAP: 2099 /* Enable beaconing. */ 2100 urtwn_write_1(sc, R92C_MBID_NUM, 2101 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2102 urtwn_write_1(sc, R92C_BCN_CTRL, 2103 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 2104 break; 2105 default: 2106 device_printf(sc->sc_dev, "undefined opmode %d\n", 2107 vap->iv_opmode); 2108 return; 2109 } 2110} 2111 2112static void 2113urtwn_set_led(struct urtwn_softc *sc, int led, int on) 2114{ 2115 uint8_t reg; 2116 2117 if (led == URTWN_LED_LINK) { 2118 if (sc->chip & URTWN_CHIP_88E) { 2119 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 2120 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 2121 if (!on) { 2122 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 2123 urtwn_write_1(sc, R92C_LEDCFG2, 2124 reg | R92C_LEDCFG0_DIS); 2125 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 2126 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 2127 0xfe); 2128 } 2129 } else { 2130 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 2131 if (!on) 2132 reg |= R92C_LEDCFG0_DIS; 2133 urtwn_write_1(sc, R92C_LEDCFG0, reg); 2134 } 2135 sc->ledlink = on; /* Save LED state. */ 2136 } 2137} 2138 2139static void 2140urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 2141{ 2142 uint8_t reg; 2143 2144 reg = urtwn_read_1(sc, R92C_MSR); 2145 reg = (reg & ~R92C_MSR_MASK) | mode; 2146 urtwn_write_1(sc, R92C_MSR, reg); 2147} 2148 2149static void 2150urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 2151 const struct ieee80211_rx_stats *rxs, 2152 int rssi, int nf) 2153{ 2154 struct ieee80211vap *vap = ni->ni_vap; 2155 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2156 struct urtwn_vap *uvp = URTWN_VAP(vap); 2157 uint64_t ni_tstamp, curr_tstamp; 2158 2159 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 2160 2161 if (vap->iv_state == IEEE80211_S_RUN && 2162 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 2163 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 2164 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 2165#ifdef D3831 2166 URTWN_LOCK(sc); 2167 urtwn_get_tsf(sc, &curr_tstamp); 2168 URTWN_UNLOCK(sc); 2169 curr_tstamp = le64toh(curr_tstamp); 2170 2171 if (ni_tstamp >= curr_tstamp) 2172 (void) ieee80211_ibss_merge(ni); 2173#else 2174 (void) sc; 2175 (void) curr_tstamp; 2176#endif 2177 } 2178} 2179 2180static int 2181urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2182{ 2183 struct urtwn_vap *uvp = URTWN_VAP(vap); 2184 struct ieee80211com *ic = vap->iv_ic; 2185 struct urtwn_softc *sc = ic->ic_softc; 2186 struct ieee80211_node *ni; 2187 enum ieee80211_state ostate; 2188 uint32_t reg; 2189 uint8_t mode; 2190 int error = 0; 2191 2192 ostate = vap->iv_state; 2193 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 2194 ieee80211_state_name[nstate]); 2195 2196 IEEE80211_UNLOCK(ic); 2197 URTWN_LOCK(sc); 2198 callout_stop(&sc->sc_watchdog_ch); 2199 2200 if (ostate == IEEE80211_S_RUN) { 2201 /* Turn link LED off. */ 2202 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2203 2204 /* Set media status to 'No Link'. */ 2205 urtwn_set_mode(sc, R92C_MSR_NOLINK); 2206 2207 /* Stop Rx of data frames. */ 2208 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2209 2210 /* Disable TSF synchronization. */ 2211 urtwn_write_1(sc, R92C_BCN_CTRL, 2212 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 2213 R92C_BCN_CTRL_DIS_TSF_UDT0); 2214 2215 /* Disable beaconing. */ 2216 urtwn_write_1(sc, R92C_MBID_NUM, 2217 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 2218 2219 /* Reset TSF. */ 2220 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2221 2222 /* Reset EDCA parameters. */ 2223 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2224 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2225 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2226 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2227 } 2228 2229 switch (nstate) { 2230 case IEEE80211_S_INIT: 2231 /* Turn link LED off. */ 2232 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2233 break; 2234 case IEEE80211_S_SCAN: 2235 /* Pause AC Tx queues. */ 2236 urtwn_write_1(sc, R92C_TXPAUSE, 2237 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2238 break; 2239 case IEEE80211_S_AUTH: 2240 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2241 break; 2242 case IEEE80211_S_RUN: 2243 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2244 /* Turn link LED on. */ 2245 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2246 break; 2247 } 2248 2249 ni = ieee80211_ref_node(vap->iv_bss); 2250 2251 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2252 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2253 device_printf(sc->sc_dev, 2254 "%s: could not move to RUN state\n", __func__); 2255 error = EINVAL; 2256 goto end_run; 2257 } 2258 2259 switch (vap->iv_opmode) { 2260 case IEEE80211_M_STA: 2261 mode = R92C_MSR_INFRA; 2262 break; 2263 case IEEE80211_M_IBSS: 2264 mode = R92C_MSR_ADHOC; 2265 break; 2266 case IEEE80211_M_HOSTAP: 2267 mode = R92C_MSR_AP; 2268 break; 2269 default: 2270 device_printf(sc->sc_dev, "undefined opmode %d\n", 2271 vap->iv_opmode); 2272 error = EINVAL; 2273 goto end_run; 2274 } 2275 2276 /* Set media status to 'Associated'. */ 2277 urtwn_set_mode(sc, mode); 2278 2279 /* Set BSSID. */ 2280 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2281 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2282 2283 if (ic->ic_curmode == IEEE80211_MODE_11B) 2284 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2285 else /* 802.11b/g */ 2286 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2287 2288 /* Enable Rx of data frames. */ 2289 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2290 2291 /* Flush all AC queues. */ 2292 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2293 2294 /* Set beacon interval. */ 2295 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2296 2297 /* Allow Rx from our BSSID only. */ 2298 if (ic->ic_promisc == 0) { 2299 reg = urtwn_read_4(sc, R92C_RCR); 2300 2301 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 2302 reg |= R92C_RCR_CBSSID_DATA; 2303 if (vap->iv_opmode != IEEE80211_M_IBSS) 2304 reg |= R92C_RCR_CBSSID_BCN; 2305 2306 urtwn_write_4(sc, R92C_RCR, reg); 2307 } 2308 2309 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2310 vap->iv_opmode == IEEE80211_M_IBSS) { 2311 error = urtwn_setup_beacon(sc, ni); 2312 if (error != 0) { 2313 device_printf(sc->sc_dev, 2314 "unable to push beacon into the chip, " 2315 "error %d\n", error); 2316 goto end_run; 2317 } 2318 } 2319 2320 /* Enable TSF synchronization. */ 2321 urtwn_tsf_sync_enable(sc, vap); 2322 2323 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2324 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2325 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2326 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2327 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2328 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2329 2330 /* Intialize rate adaptation. */ 2331 if (!(sc->chip & URTWN_CHIP_88E)) 2332 urtwn_ra_init(sc); 2333 /* Turn link LED on. */ 2334 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2335 2336 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2337 /* Reset temperature calibration state machine. */ 2338 sc->thcal_state = 0; 2339 sc->thcal_lctemp = 0; 2340 2341end_run: 2342 ieee80211_free_node(ni); 2343 break; 2344 default: 2345 break; 2346 } 2347 2348 URTWN_UNLOCK(sc); 2349 IEEE80211_LOCK(ic); 2350 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2351} 2352 2353static void 2354urtwn_watchdog(void *arg) 2355{ 2356 struct urtwn_softc *sc = arg; 2357 2358 if (sc->sc_txtimer > 0) { 2359 if (--sc->sc_txtimer == 0) { 2360 device_printf(sc->sc_dev, "device timeout\n"); 2361 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2362 return; 2363 } 2364 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2365 } 2366} 2367 2368static void 2369urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2370{ 2371 int pwdb; 2372 2373 /* Convert antenna signal to percentage. */ 2374 if (rssi <= -100 || rssi >= 20) 2375 pwdb = 0; 2376 else if (rssi >= 0) 2377 pwdb = 100; 2378 else 2379 pwdb = 100 + rssi; 2380 if (!(sc->chip & URTWN_CHIP_88E)) { 2381 if (rate <= URTWN_RIDX_CCK11) { 2382 /* CCK gain is smaller than OFDM/MCS gain. */ 2383 pwdb += 6; 2384 if (pwdb > 100) 2385 pwdb = 100; 2386 if (pwdb <= 14) 2387 pwdb -= 4; 2388 else if (pwdb <= 26) 2389 pwdb -= 8; 2390 else if (pwdb <= 34) 2391 pwdb -= 6; 2392 else if (pwdb <= 42) 2393 pwdb -= 2; 2394 } 2395 } 2396 if (sc->avg_pwdb == -1) /* Init. */ 2397 sc->avg_pwdb = pwdb; 2398 else if (sc->avg_pwdb < pwdb) 2399 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2400 else 2401 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2402 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 2403} 2404 2405static int8_t 2406urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2407{ 2408 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2409 struct r92c_rx_phystat *phy; 2410 struct r92c_rx_cck *cck; 2411 uint8_t rpt; 2412 int8_t rssi; 2413 2414 if (rate <= URTWN_RIDX_CCK11) { 2415 cck = (struct r92c_rx_cck *)physt; 2416 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2417 rpt = (cck->agc_rpt >> 5) & 0x3; 2418 rssi = (cck->agc_rpt & 0x1f) << 1; 2419 } else { 2420 rpt = (cck->agc_rpt >> 6) & 0x3; 2421 rssi = cck->agc_rpt & 0x3e; 2422 } 2423 rssi = cckoff[rpt] - rssi; 2424 } else { /* OFDM/HT. */ 2425 phy = (struct r92c_rx_phystat *)physt; 2426 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2427 } 2428 return (rssi); 2429} 2430 2431static int8_t 2432urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2433{ 2434 struct r92c_rx_phystat *phy; 2435 struct r88e_rx_cck *cck; 2436 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2437 int8_t rssi; 2438 2439 rssi = 0; 2440 if (rate <= URTWN_RIDX_CCK11) { 2441 cck = (struct r88e_rx_cck *)physt; 2442 cck_agc_rpt = cck->agc_rpt; 2443 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2444 vga_idx = cck_agc_rpt & 0x1f; 2445 switch (lna_idx) { 2446 case 7: 2447 if (vga_idx <= 27) 2448 rssi = -100 + 2* (27 - vga_idx); 2449 else 2450 rssi = -100; 2451 break; 2452 case 6: 2453 rssi = -48 + 2 * (2 - vga_idx); 2454 break; 2455 case 5: 2456 rssi = -42 + 2 * (7 - vga_idx); 2457 break; 2458 case 4: 2459 rssi = -36 + 2 * (7 - vga_idx); 2460 break; 2461 case 3: 2462 rssi = -24 + 2 * (7 - vga_idx); 2463 break; 2464 case 2: 2465 rssi = -12 + 2 * (5 - vga_idx); 2466 break; 2467 case 1: 2468 rssi = 8 - (2 * vga_idx); 2469 break; 2470 case 0: 2471 rssi = 14 - (2 * vga_idx); 2472 break; 2473 } 2474 rssi += 6; 2475 } else { /* OFDM/HT. */ 2476 phy = (struct r92c_rx_phystat *)physt; 2477 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2478 } 2479 return (rssi); 2480} 2481 2482static __inline uint8_t 2483rate2ridx(uint8_t rate) 2484{ 2485 switch (rate) { 2486 case 12: return 4; 2487 case 18: return 5; 2488 case 24: return 6; 2489 case 36: return 7; 2490 case 48: return 8; 2491 case 72: return 9; 2492 case 96: return 10; 2493 case 108: return 11; 2494 case 2: return 0; 2495 case 4: return 1; 2496 case 11: return 2; 2497 case 22: return 3; 2498 default: return 0; 2499 } 2500} 2501 2502static int 2503urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2504 struct mbuf *m, struct urtwn_data *data) 2505{ 2506 const struct ieee80211_txparam *tp; 2507 struct ieee80211com *ic = &sc->sc_ic; 2508 struct ieee80211vap *vap = ni->ni_vap; 2509 struct ieee80211_key *k = NULL; 2510 struct ieee80211_channel *chan; 2511 struct ieee80211_frame *wh; 2512 struct r92c_tx_desc *txd; 2513 uint8_t macid, raid, rate, ridx, subtype, type, tid, qsel; 2514 int hasqos, ismcast; 2515 2516 URTWN_ASSERT_LOCKED(sc); 2517 2518 /* 2519 * Software crypto. 2520 */ 2521 wh = mtod(m, struct ieee80211_frame *); 2522 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2523 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2524 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2525 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2526 2527 /* Select TX ring for this frame. */ 2528 if (hasqos) { 2529 tid = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2530 tid &= IEEE80211_QOS_TID; 2531 } else 2532 tid = 0; 2533 2534 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2535 ni->ni_chan : ic->ic_curchan; 2536 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2537 2538 /* Choose a TX rate index. */ 2539 if (type == IEEE80211_FC0_TYPE_MGT) 2540 rate = tp->mgmtrate; 2541 else if (ismcast) 2542 rate = tp->mcastrate; 2543 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2544 rate = tp->ucastrate; 2545 else if (m->m_flags & M_EAPOL) 2546 rate = tp->mgmtrate; 2547 else { 2548 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2549 /* XXX pass pktlen */ 2550 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2551 rate = ni->ni_txrate; 2552 } else { 2553 if (ic->ic_curmode != IEEE80211_MODE_11B) 2554 rate = 108; 2555 else 2556 rate = 22; 2557 } 2558 } 2559 2560 ridx = rate2ridx(rate); 2561 if (ic->ic_curmode != IEEE80211_MODE_11B) 2562 raid = R92C_RAID_11BG; 2563 else 2564 raid = R92C_RAID_11B; 2565 2566 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2567 k = ieee80211_crypto_encap(ni, m); 2568 if (k == NULL) { 2569 device_printf(sc->sc_dev, 2570 "ieee80211_crypto_encap returns NULL.\n"); 2571 return (ENOBUFS); 2572 } 2573 2574 /* in case packet header moved, reset pointer */ 2575 wh = mtod(m, struct ieee80211_frame *); 2576 } 2577 2578 /* Fill Tx descriptor. */ 2579 txd = (struct r92c_tx_desc *)data->buf; 2580 memset(txd, 0, sizeof(*txd)); 2581 2582 txd->txdw0 |= htole32( 2583 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2584 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2585 if (ismcast) 2586 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2587 2588 if (!ismcast) { 2589 if (sc->chip & URTWN_CHIP_88E) { 2590 struct urtwn_node *un = URTWN_NODE(ni); 2591 macid = un->id; 2592 } else 2593 macid = URTWN_MACID_BSS; 2594 2595 if (type == IEEE80211_FC0_TYPE_DATA) { 2596 qsel = tid % URTWN_MAX_TID; 2597 2598 if (sc->chip & URTWN_CHIP_88E) { 2599 txd->txdw2 |= htole32( 2600 R88E_TXDW2_AGGBK | 2601 R88E_TXDW2_CCX_RPT); 2602 } else 2603 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2604 2605 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2606 switch (ic->ic_protmode) { 2607 case IEEE80211_PROT_CTSONLY: 2608 txd->txdw4 |= htole32( 2609 R92C_TXDW4_CTS2SELF | 2610 R92C_TXDW4_HWRTSEN); 2611 break; 2612 case IEEE80211_PROT_RTSCTS: 2613 txd->txdw4 |= htole32( 2614 R92C_TXDW4_RTSEN | 2615 R92C_TXDW4_HWRTSEN); 2616 break; 2617 default: 2618 break; 2619 } 2620 } 2621 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2622 URTWN_RIDX_OFDM24)); 2623 txd->txdw5 |= htole32(0x0001ff00); 2624 } else /* IEEE80211_FC0_TYPE_MGT */ 2625 qsel = R92C_TXDW1_QSEL_MGNT; 2626 } else { 2627 macid = URTWN_MACID_BC; 2628 qsel = R92C_TXDW1_QSEL_MGNT; 2629 } 2630 2631 txd->txdw1 |= htole32( 2632 SM(R92C_TXDW1_QSEL, qsel) | 2633 SM(R92C_TXDW1_RAID, raid)); 2634 2635 if (sc->chip & URTWN_CHIP_88E) 2636 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 2637 else 2638 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 2639 2640 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2641 /* Force this rate if needed. */ 2642 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 2643 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 2644 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2645 2646 if (!hasqos) { 2647 /* Use HW sequence numbering for non-QoS frames. */ 2648 if (sc->chip & URTWN_CHIP_88E) 2649 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2650 else 2651 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2652 } else { 2653 /* Set sequence number. */ 2654 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2655 } 2656 2657 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2658 uint8_t cipher; 2659 2660 switch (k->wk_cipher->ic_cipher) { 2661 case IEEE80211_CIPHER_WEP: 2662 case IEEE80211_CIPHER_TKIP: 2663 cipher = R92C_TXDW1_CIPHER_RC4; 2664 break; 2665 case IEEE80211_CIPHER_AES_CCM: 2666 cipher = R92C_TXDW1_CIPHER_AES; 2667 break; 2668 default: 2669 device_printf(sc->sc_dev, "%s: unknown cipher %d\n", 2670 __func__, k->wk_cipher->ic_cipher); 2671 return (EINVAL); 2672 } 2673 2674 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 2675 } 2676 2677 if (ieee80211_radiotap_active_vap(vap)) { 2678 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2679 2680 tap->wt_flags = 0; 2681 if (k != NULL) 2682 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2683 ieee80211_radiotap_tx(vap, m); 2684 } 2685 2686 data->ni = ni; 2687 2688 urtwn_tx_start(sc, m, type, data); 2689 2690 return (0); 2691} 2692 2693static void 2694urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 2695 struct urtwn_data *data) 2696{ 2697 struct usb_xfer *xfer; 2698 struct r92c_tx_desc *txd; 2699 uint16_t ac, sum; 2700 int i, xferlen; 2701 2702 URTWN_ASSERT_LOCKED(sc); 2703 2704 ac = M_WME_GETAC(m); 2705 2706 switch (type) { 2707 case IEEE80211_FC0_TYPE_CTL: 2708 case IEEE80211_FC0_TYPE_MGT: 2709 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 2710 break; 2711 default: 2712 xfer = sc->sc_xfer[wme2queue[ac].qid]; 2713 break; 2714 } 2715 2716 txd = (struct r92c_tx_desc *)data->buf; 2717 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 2718 2719 /* Compute Tx descriptor checksum. */ 2720 sum = 0; 2721 for (i = 0; i < sizeof(*txd) / 2; i++) 2722 sum ^= ((uint16_t *)txd)[i]; 2723 txd->txdsum = sum; /* NB: already little endian. */ 2724 2725 xferlen = sizeof(*txd) + m->m_pkthdr.len; 2726 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 2727 2728 data->buflen = xferlen; 2729 data->m = m; 2730 2731 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 2732 usbd_transfer_start(xfer); 2733} 2734 2735static int 2736urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 2737{ 2738 struct urtwn_softc *sc = ic->ic_softc; 2739 int error; 2740 2741 URTWN_LOCK(sc); 2742 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2743 URTWN_UNLOCK(sc); 2744 return (ENXIO); 2745 } 2746 error = mbufq_enqueue(&sc->sc_snd, m); 2747 if (error) { 2748 URTWN_UNLOCK(sc); 2749 return (error); 2750 } 2751 urtwn_start(sc); 2752 URTWN_UNLOCK(sc); 2753 2754 return (0); 2755} 2756 2757static void 2758urtwn_start(struct urtwn_softc *sc) 2759{ 2760 struct ieee80211_node *ni; 2761 struct mbuf *m; 2762 struct urtwn_data *bf; 2763 2764 URTWN_ASSERT_LOCKED(sc); 2765 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2766 bf = urtwn_getbuf(sc); 2767 if (bf == NULL) { 2768 mbufq_prepend(&sc->sc_snd, m); 2769 break; 2770 } 2771 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2772 m->m_pkthdr.rcvif = NULL; 2773 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 2774 if_inc_counter(ni->ni_vap->iv_ifp, 2775 IFCOUNTER_OERRORS, 1); 2776 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2777 m_freem(m); 2778 ieee80211_free_node(ni); 2779 break; 2780 } 2781 sc->sc_txtimer = 5; 2782 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2783 } 2784} 2785 2786static void 2787urtwn_parent(struct ieee80211com *ic) 2788{ 2789 struct urtwn_softc *sc = ic->ic_softc; 2790 2791 URTWN_LOCK(sc); 2792 if (sc->sc_flags & URTWN_DETACHED) { 2793 URTWN_UNLOCK(sc); 2794 return; 2795 } 2796 URTWN_UNLOCK(sc); 2797 2798 if (ic->ic_nrunning > 0) { 2799 if (urtwn_init(sc) != 0) { 2800 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2801 if (vap != NULL) 2802 ieee80211_stop(vap); 2803 } else 2804 ieee80211_start_all(ic); 2805 } else 2806 urtwn_stop(sc); 2807} 2808 2809static __inline int 2810urtwn_power_on(struct urtwn_softc *sc) 2811{ 2812 2813 return sc->sc_power_on(sc); 2814} 2815 2816static int 2817urtwn_r92c_power_on(struct urtwn_softc *sc) 2818{ 2819 uint32_t reg; 2820 usb_error_t error; 2821 int ntries; 2822 2823 /* Wait for autoload done bit. */ 2824 for (ntries = 0; ntries < 1000; ntries++) { 2825 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2826 break; 2827 urtwn_ms_delay(sc); 2828 } 2829 if (ntries == 1000) { 2830 device_printf(sc->sc_dev, 2831 "timeout waiting for chip autoload\n"); 2832 return (ETIMEDOUT); 2833 } 2834 2835 /* Unlock ISO/CLK/Power control register. */ 2836 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2837 if (error != USB_ERR_NORMAL_COMPLETION) 2838 return (EIO); 2839 /* Move SPS into PWM mode. */ 2840 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2841 if (error != USB_ERR_NORMAL_COMPLETION) 2842 return (EIO); 2843 urtwn_ms_delay(sc); 2844 2845 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2846 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2847 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2848 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2849 if (error != USB_ERR_NORMAL_COMPLETION) 2850 return (EIO); 2851 urtwn_ms_delay(sc); 2852 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2853 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2854 ~R92C_SYS_ISO_CTRL_MD2PP); 2855 if (error != USB_ERR_NORMAL_COMPLETION) 2856 return (EIO); 2857 } 2858 2859 /* Auto enable WLAN. */ 2860 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2861 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2862 if (error != USB_ERR_NORMAL_COMPLETION) 2863 return (EIO); 2864 for (ntries = 0; ntries < 1000; ntries++) { 2865 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2866 R92C_APS_FSMCO_APFM_ONMAC)) 2867 break; 2868 urtwn_ms_delay(sc); 2869 } 2870 if (ntries == 1000) { 2871 device_printf(sc->sc_dev, 2872 "timeout waiting for MAC auto ON\n"); 2873 return (ETIMEDOUT); 2874 } 2875 2876 /* Enable radio, GPIO and LED functions. */ 2877 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2878 R92C_APS_FSMCO_AFSM_HSUS | 2879 R92C_APS_FSMCO_PDN_EN | 2880 R92C_APS_FSMCO_PFM_ALDN); 2881 if (error != USB_ERR_NORMAL_COMPLETION) 2882 return (EIO); 2883 /* Release RF digital isolation. */ 2884 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2885 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2886 if (error != USB_ERR_NORMAL_COMPLETION) 2887 return (EIO); 2888 2889 /* Initialize MAC. */ 2890 error = urtwn_write_1(sc, R92C_APSD_CTRL, 2891 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2892 if (error != USB_ERR_NORMAL_COMPLETION) 2893 return (EIO); 2894 for (ntries = 0; ntries < 200; ntries++) { 2895 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2896 R92C_APSD_CTRL_OFF_STATUS)) 2897 break; 2898 urtwn_ms_delay(sc); 2899 } 2900 if (ntries == 200) { 2901 device_printf(sc->sc_dev, 2902 "timeout waiting for MAC initialization\n"); 2903 return (ETIMEDOUT); 2904 } 2905 2906 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2907 reg = urtwn_read_2(sc, R92C_CR); 2908 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2909 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2910 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2911 R92C_CR_ENSEC; 2912 error = urtwn_write_2(sc, R92C_CR, reg); 2913 if (error != USB_ERR_NORMAL_COMPLETION) 2914 return (EIO); 2915 2916 error = urtwn_write_1(sc, 0xfe10, 0x19); 2917 if (error != USB_ERR_NORMAL_COMPLETION) 2918 return (EIO); 2919 return (0); 2920} 2921 2922static int 2923urtwn_r88e_power_on(struct urtwn_softc *sc) 2924{ 2925 uint32_t reg; 2926 usb_error_t error; 2927 int ntries; 2928 2929 /* Wait for power ready bit. */ 2930 for (ntries = 0; ntries < 5000; ntries++) { 2931 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2932 break; 2933 urtwn_ms_delay(sc); 2934 } 2935 if (ntries == 5000) { 2936 device_printf(sc->sc_dev, 2937 "timeout waiting for chip power up\n"); 2938 return (ETIMEDOUT); 2939 } 2940 2941 /* Reset BB. */ 2942 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2943 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2944 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2945 if (error != USB_ERR_NORMAL_COMPLETION) 2946 return (EIO); 2947 2948 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2949 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2950 if (error != USB_ERR_NORMAL_COMPLETION) 2951 return (EIO); 2952 2953 /* Disable HWPDN. */ 2954 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2955 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2956 if (error != USB_ERR_NORMAL_COMPLETION) 2957 return (EIO); 2958 2959 /* Disable WL suspend. */ 2960 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2961 urtwn_read_2(sc, R92C_APS_FSMCO) & 2962 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2963 if (error != USB_ERR_NORMAL_COMPLETION) 2964 return (EIO); 2965 2966 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2967 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2968 if (error != USB_ERR_NORMAL_COMPLETION) 2969 return (EIO); 2970 for (ntries = 0; ntries < 5000; ntries++) { 2971 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2972 R92C_APS_FSMCO_APFM_ONMAC)) 2973 break; 2974 urtwn_ms_delay(sc); 2975 } 2976 if (ntries == 5000) 2977 return (ETIMEDOUT); 2978 2979 /* Enable LDO normal mode. */ 2980 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 2981 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2982 if (error != USB_ERR_NORMAL_COMPLETION) 2983 return (EIO); 2984 2985 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2986 error = urtwn_write_2(sc, R92C_CR, 0); 2987 if (error != USB_ERR_NORMAL_COMPLETION) 2988 return (EIO); 2989 reg = urtwn_read_2(sc, R92C_CR); 2990 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2991 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2992 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2993 error = urtwn_write_2(sc, R92C_CR, reg); 2994 if (error != USB_ERR_NORMAL_COMPLETION) 2995 return (EIO); 2996 2997 return (0); 2998} 2999 3000static int 3001urtwn_llt_init(struct urtwn_softc *sc) 3002{ 3003 int i, error, page_count, pktbuf_count; 3004 3005 page_count = (sc->chip & URTWN_CHIP_88E) ? 3006 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 3007 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 3008 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 3009 3010 /* Reserve pages [0; page_count]. */ 3011 for (i = 0; i < page_count; i++) { 3012 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3013 return (error); 3014 } 3015 /* NB: 0xff indicates end-of-list. */ 3016 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3017 return (error); 3018 /* 3019 * Use pages [page_count + 1; pktbuf_count - 1] 3020 * as ring buffer. 3021 */ 3022 for (++i; i < pktbuf_count - 1; i++) { 3023 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3024 return (error); 3025 } 3026 /* Make the last page point to the beginning of the ring buffer. */ 3027 error = urtwn_llt_write(sc, i, page_count + 1); 3028 return (error); 3029} 3030 3031static void 3032urtwn_fw_reset(struct urtwn_softc *sc) 3033{ 3034 uint16_t reg; 3035 int ntries; 3036 3037 /* Tell 8051 to reset itself. */ 3038 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3039 3040 /* Wait until 8051 resets by itself. */ 3041 for (ntries = 0; ntries < 100; ntries++) { 3042 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3043 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3044 return; 3045 urtwn_ms_delay(sc); 3046 } 3047 /* Force 8051 reset. */ 3048 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3049} 3050 3051static void 3052urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3053{ 3054 uint16_t reg; 3055 3056 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3057 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3058 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3059} 3060 3061static int 3062urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 3063{ 3064 uint32_t reg; 3065 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 3066 int off, mlen; 3067 3068 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3069 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3070 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3071 3072 off = R92C_FW_START_ADDR; 3073 while (len > 0) { 3074 if (len > 196) 3075 mlen = 196; 3076 else if (len > 4) 3077 mlen = 4; 3078 else 3079 mlen = 1; 3080 /* XXX fix this deconst */ 3081 error = urtwn_write_region_1(sc, off, 3082 __DECONST(uint8_t *, buf), mlen); 3083 if (error != USB_ERR_NORMAL_COMPLETION) 3084 break; 3085 off += mlen; 3086 buf += mlen; 3087 len -= mlen; 3088 } 3089 return (error); 3090} 3091 3092static int 3093urtwn_load_firmware(struct urtwn_softc *sc) 3094{ 3095 const struct firmware *fw; 3096 const struct r92c_fw_hdr *hdr; 3097 const char *imagename; 3098 const u_char *ptr; 3099 size_t len; 3100 uint32_t reg; 3101 int mlen, ntries, page, error; 3102 3103 URTWN_UNLOCK(sc); 3104 /* Read firmware image from the filesystem. */ 3105 if (sc->chip & URTWN_CHIP_88E) 3106 imagename = "urtwn-rtl8188eufw"; 3107 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3108 URTWN_CHIP_UMC_A_CUT) 3109 imagename = "urtwn-rtl8192cfwU"; 3110 else 3111 imagename = "urtwn-rtl8192cfwT"; 3112 3113 fw = firmware_get(imagename); 3114 URTWN_LOCK(sc); 3115 if (fw == NULL) { 3116 device_printf(sc->sc_dev, 3117 "failed loadfirmware of file %s\n", imagename); 3118 return (ENOENT); 3119 } 3120 3121 len = fw->datasize; 3122 3123 if (len < sizeof(*hdr)) { 3124 device_printf(sc->sc_dev, "firmware too short\n"); 3125 error = EINVAL; 3126 goto fail; 3127 } 3128 ptr = fw->data; 3129 hdr = (const struct r92c_fw_hdr *)ptr; 3130 /* Check if there is a valid FW header and skip it. */ 3131 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3132 (le16toh(hdr->signature) >> 4) == 0x88e || 3133 (le16toh(hdr->signature) >> 4) == 0x92c) { 3134 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 3135 le16toh(hdr->version), le16toh(hdr->subversion), 3136 hdr->month, hdr->date, hdr->hour, hdr->minute); 3137 ptr += sizeof(*hdr); 3138 len -= sizeof(*hdr); 3139 } 3140 3141 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3142 if (sc->chip & URTWN_CHIP_88E) 3143 urtwn_r88e_fw_reset(sc); 3144 else 3145 urtwn_fw_reset(sc); 3146 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3147 } 3148 3149 if (!(sc->chip & URTWN_CHIP_88E)) { 3150 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3151 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3152 R92C_SYS_FUNC_EN_CPUEN); 3153 } 3154 urtwn_write_1(sc, R92C_MCUFWDL, 3155 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3156 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3157 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3158 3159 /* Reset the FWDL checksum. */ 3160 urtwn_write_1(sc, R92C_MCUFWDL, 3161 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3162 3163 for (page = 0; len > 0; page++) { 3164 mlen = min(len, R92C_FW_PAGE_SIZE); 3165 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3166 if (error != 0) { 3167 device_printf(sc->sc_dev, 3168 "could not load firmware page\n"); 3169 goto fail; 3170 } 3171 ptr += mlen; 3172 len -= mlen; 3173 } 3174 urtwn_write_1(sc, R92C_MCUFWDL, 3175 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3176 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3177 3178 /* Wait for checksum report. */ 3179 for (ntries = 0; ntries < 1000; ntries++) { 3180 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3181 break; 3182 urtwn_ms_delay(sc); 3183 } 3184 if (ntries == 1000) { 3185 device_printf(sc->sc_dev, 3186 "timeout waiting for checksum report\n"); 3187 error = ETIMEDOUT; 3188 goto fail; 3189 } 3190 3191 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3192 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3193 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3194 if (sc->chip & URTWN_CHIP_88E) 3195 urtwn_r88e_fw_reset(sc); 3196 /* Wait for firmware readiness. */ 3197 for (ntries = 0; ntries < 1000; ntries++) { 3198 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3199 break; 3200 urtwn_ms_delay(sc); 3201 } 3202 if (ntries == 1000) { 3203 device_printf(sc->sc_dev, 3204 "timeout waiting for firmware readiness\n"); 3205 error = ETIMEDOUT; 3206 goto fail; 3207 } 3208fail: 3209 firmware_put(fw, FIRMWARE_UNLOAD); 3210 return (error); 3211} 3212 3213static int 3214urtwn_dma_init(struct urtwn_softc *sc) 3215{ 3216 struct usb_endpoint *ep, *ep_end; 3217 usb_error_t usb_err; 3218 uint32_t reg; 3219 int hashq, hasnq, haslq, nqueues, ntx; 3220 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 3221 3222 /* Initialize LLT table. */ 3223 error = urtwn_llt_init(sc); 3224 if (error != 0) 3225 return (error); 3226 3227 /* Determine the number of bulk-out pipes. */ 3228 ntx = 0; 3229 ep = sc->sc_udev->endpoints; 3230 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 3231 for (; ep != ep_end; ep++) { 3232 if ((ep->edesc == NULL) || 3233 (ep->iface_index != sc->sc_iface_index)) 3234 continue; 3235 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 3236 ntx++; 3237 } 3238 if (ntx == 0) { 3239 device_printf(sc->sc_dev, 3240 "%d: invalid number of Tx bulk pipes\n", ntx); 3241 return (EIO); 3242 } 3243 3244 /* Get Tx queues to USB endpoints mapping. */ 3245 hashq = hasnq = haslq = nqueues = 0; 3246 switch (ntx) { 3247 case 1: hashq = 1; break; 3248 case 2: hashq = hasnq = 1; break; 3249 case 3: case 4: hashq = hasnq = haslq = 1; break; 3250 } 3251 nqueues = hashq + hasnq + haslq; 3252 if (nqueues == 0) 3253 return (EIO); 3254 3255 npubqpages = nqpages = nrempages = pagecount = 0; 3256 if (sc->chip & URTWN_CHIP_88E) 3257 tx_boundary = R88E_TX_PAGE_BOUNDARY; 3258 else { 3259 pagecount = R92C_TX_PAGE_COUNT; 3260 npubqpages = R92C_PUBQ_NPAGES; 3261 tx_boundary = R92C_TX_PAGE_BOUNDARY; 3262 } 3263 3264 /* Set number of pages for normal priority queue. */ 3265 if (sc->chip & URTWN_CHIP_88E) { 3266 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 3267 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3268 return (EIO); 3269 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3270 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3271 return (EIO); 3272 } else { 3273 /* Get the number of pages for each queue. */ 3274 nqpages = (pagecount - npubqpages) / nqueues; 3275 /* 3276 * The remaining pages are assigned to the high priority 3277 * queue. 3278 */ 3279 nrempages = (pagecount - npubqpages) % nqueues; 3280 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3281 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3282 return (EIO); 3283 usb_err = urtwn_write_4(sc, R92C_RQPN, 3284 /* Set number of pages for public queue. */ 3285 SM(R92C_RQPN_PUBQ, npubqpages) | 3286 /* Set number of pages for high priority queue. */ 3287 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3288 /* Set number of pages for low priority queue. */ 3289 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3290 /* Load values. */ 3291 R92C_RQPN_LD); 3292 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3293 return (EIO); 3294 } 3295 3296 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 3297 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3298 return (EIO); 3299 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 3300 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3301 return (EIO); 3302 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 3303 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3304 return (EIO); 3305 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 3306 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3307 return (EIO); 3308 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 3309 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3310 return (EIO); 3311 3312 /* Set queue to USB pipe mapping. */ 3313 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3314 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3315 if (nqueues == 1) { 3316 if (hashq) 3317 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3318 else if (hasnq) 3319 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3320 else 3321 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3322 } else if (nqueues == 2) { 3323 /* 3324 * All 2-endpoints configs have high and normal 3325 * priority queues. 3326 */ 3327 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3328 } else 3329 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3330 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3331 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3332 return (EIO); 3333 3334 /* Set Tx/Rx transfer page boundary. */ 3335 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 3336 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 3337 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3338 return (EIO); 3339 3340 /* Set Tx/Rx transfer page size. */ 3341 usb_err = urtwn_write_1(sc, R92C_PBP, 3342 SM(R92C_PBP_PSRX, R92C_PBP_128) | 3343 SM(R92C_PBP_PSTX, R92C_PBP_128)); 3344 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3345 return (EIO); 3346 3347 return (0); 3348} 3349 3350static int 3351urtwn_mac_init(struct urtwn_softc *sc) 3352{ 3353 usb_error_t error; 3354 int i; 3355 3356 /* Write MAC initialization values. */ 3357 if (sc->chip & URTWN_CHIP_88E) { 3358 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 3359 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3360 rtl8188eu_mac[i].val); 3361 if (error != USB_ERR_NORMAL_COMPLETION) 3362 return (EIO); 3363 } 3364 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 3365 } else { 3366 for (i = 0; i < nitems(rtl8192cu_mac); i++) 3367 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3368 rtl8192cu_mac[i].val); 3369 if (error != USB_ERR_NORMAL_COMPLETION) 3370 return (EIO); 3371 } 3372 3373 return (0); 3374} 3375 3376static void 3377urtwn_bb_init(struct urtwn_softc *sc) 3378{ 3379 const struct urtwn_bb_prog *prog; 3380 uint32_t reg; 3381 uint8_t crystalcap; 3382 int i; 3383 3384 /* Enable BB and RF. */ 3385 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3386 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3387 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3388 R92C_SYS_FUNC_EN_DIO_RF); 3389 3390 if (!(sc->chip & URTWN_CHIP_88E)) 3391 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 3392 3393 urtwn_write_1(sc, R92C_RF_CTRL, 3394 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3395 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3396 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3397 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3398 3399 if (!(sc->chip & URTWN_CHIP_88E)) { 3400 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3401 urtwn_write_1(sc, 0x15, 0xe9); 3402 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3403 } 3404 3405 /* Select BB programming based on board type. */ 3406 if (sc->chip & URTWN_CHIP_88E) 3407 prog = &rtl8188eu_bb_prog; 3408 else if (!(sc->chip & URTWN_CHIP_92C)) { 3409 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3410 prog = &rtl8188ce_bb_prog; 3411 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3412 prog = &rtl8188ru_bb_prog; 3413 else 3414 prog = &rtl8188cu_bb_prog; 3415 } else { 3416 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3417 prog = &rtl8192ce_bb_prog; 3418 else 3419 prog = &rtl8192cu_bb_prog; 3420 } 3421 /* Write BB initialization values. */ 3422 for (i = 0; i < prog->count; i++) { 3423 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3424 urtwn_ms_delay(sc); 3425 } 3426 3427 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3428 /* 8192C 1T only configuration. */ 3429 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3430 reg = (reg & ~0x00000003) | 0x2; 3431 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3432 3433 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3434 reg = (reg & ~0x00300033) | 0x00200022; 3435 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3436 3437 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3438 reg = (reg & ~0xff000000) | 0x45 << 24; 3439 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3440 3441 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3442 reg = (reg & ~0x000000ff) | 0x23; 3443 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3444 3445 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3446 reg = (reg & ~0x00000030) | 1 << 4; 3447 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3448 3449 reg = urtwn_bb_read(sc, 0xe74); 3450 reg = (reg & ~0x0c000000) | 2 << 26; 3451 urtwn_bb_write(sc, 0xe74, reg); 3452 reg = urtwn_bb_read(sc, 0xe78); 3453 reg = (reg & ~0x0c000000) | 2 << 26; 3454 urtwn_bb_write(sc, 0xe78, reg); 3455 reg = urtwn_bb_read(sc, 0xe7c); 3456 reg = (reg & ~0x0c000000) | 2 << 26; 3457 urtwn_bb_write(sc, 0xe7c, reg); 3458 reg = urtwn_bb_read(sc, 0xe80); 3459 reg = (reg & ~0x0c000000) | 2 << 26; 3460 urtwn_bb_write(sc, 0xe80, reg); 3461 reg = urtwn_bb_read(sc, 0xe88); 3462 reg = (reg & ~0x0c000000) | 2 << 26; 3463 urtwn_bb_write(sc, 0xe88, reg); 3464 } 3465 3466 /* Write AGC values. */ 3467 for (i = 0; i < prog->agccount; i++) { 3468 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 3469 prog->agcvals[i]); 3470 urtwn_ms_delay(sc); 3471 } 3472 3473 if (sc->chip & URTWN_CHIP_88E) { 3474 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3475 urtwn_ms_delay(sc); 3476 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3477 urtwn_ms_delay(sc); 3478 3479 crystalcap = sc->rom.r88e_rom[0xb9]; 3480 if (crystalcap == 0xff) 3481 crystalcap = 0x20; 3482 crystalcap &= 0x3f; 3483 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3484 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3485 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3486 crystalcap | crystalcap << 6)); 3487 } else { 3488 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3489 R92C_HSSI_PARAM2_CCK_HIPWR) 3490 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 3491 } 3492} 3493 3494static void 3495urtwn_rf_init(struct urtwn_softc *sc) 3496{ 3497 const struct urtwn_rf_prog *prog; 3498 uint32_t reg, type; 3499 int i, j, idx, off; 3500 3501 /* Select RF programming based on board type. */ 3502 if (sc->chip & URTWN_CHIP_88E) 3503 prog = rtl8188eu_rf_prog; 3504 else if (!(sc->chip & URTWN_CHIP_92C)) { 3505 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3506 prog = rtl8188ce_rf_prog; 3507 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3508 prog = rtl8188ru_rf_prog; 3509 else 3510 prog = rtl8188cu_rf_prog; 3511 } else 3512 prog = rtl8192ce_rf_prog; 3513 3514 for (i = 0; i < sc->nrxchains; i++) { 3515 /* Save RF_ENV control type. */ 3516 idx = i / 2; 3517 off = (i % 2) * 16; 3518 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3519 type = (reg >> off) & 0x10; 3520 3521 /* Set RF_ENV enable. */ 3522 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3523 reg |= 0x100000; 3524 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3525 urtwn_ms_delay(sc); 3526 /* Set RF_ENV output high. */ 3527 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3528 reg |= 0x10; 3529 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3530 urtwn_ms_delay(sc); 3531 /* Set address and data lengths of RF registers. */ 3532 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3533 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3534 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3535 urtwn_ms_delay(sc); 3536 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3537 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3538 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3539 urtwn_ms_delay(sc); 3540 3541 /* Write RF initialization values for this chain. */ 3542 for (j = 0; j < prog[i].count; j++) { 3543 if (prog[i].regs[j] >= 0xf9 && 3544 prog[i].regs[j] <= 0xfe) { 3545 /* 3546 * These are fake RF registers offsets that 3547 * indicate a delay is required. 3548 */ 3549 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 3550 continue; 3551 } 3552 urtwn_rf_write(sc, i, prog[i].regs[j], 3553 prog[i].vals[j]); 3554 urtwn_ms_delay(sc); 3555 } 3556 3557 /* Restore RF_ENV control type. */ 3558 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3559 reg &= ~(0x10 << off) | (type << off); 3560 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 3561 3562 /* Cache RF register CHNLBW. */ 3563 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3564 } 3565 3566 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3567 URTWN_CHIP_UMC_A_CUT) { 3568 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3569 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3570 } 3571} 3572 3573static void 3574urtwn_cam_init(struct urtwn_softc *sc) 3575{ 3576 /* Invalidate all CAM entries. */ 3577 urtwn_write_4(sc, R92C_CAMCMD, 3578 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3579} 3580 3581static int 3582urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 3583{ 3584 usb_error_t error; 3585 3586 error = urtwn_write_4(sc, R92C_CAMWRITE, data); 3587 if (error != USB_ERR_NORMAL_COMPLETION) 3588 return (EIO); 3589 error = urtwn_write_4(sc, R92C_CAMCMD, 3590 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 3591 SM(R92C_CAMCMD_ADDR, addr)); 3592 if (error != USB_ERR_NORMAL_COMPLETION) 3593 return (EIO); 3594 3595 return (0); 3596} 3597 3598static void 3599urtwn_pa_bias_init(struct urtwn_softc *sc) 3600{ 3601 uint8_t reg; 3602 int i; 3603 3604 for (i = 0; i < sc->nrxchains; i++) { 3605 if (sc->pa_setting & (1 << i)) 3606 continue; 3607 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3608 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3609 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3610 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3611 } 3612 if (!(sc->pa_setting & 0x10)) { 3613 reg = urtwn_read_1(sc, 0x16); 3614 reg = (reg & ~0xf0) | 0x90; 3615 urtwn_write_1(sc, 0x16, reg); 3616 } 3617} 3618 3619static void 3620urtwn_rxfilter_init(struct urtwn_softc *sc) 3621{ 3622 struct ieee80211com *ic = &sc->sc_ic; 3623 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3624 uint32_t rcr; 3625 uint16_t filter; 3626 3627 URTWN_ASSERT_LOCKED(sc); 3628 3629 /* Accept all multicast frames. */ 3630 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3631 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3632 3633 /* Filter for management frames. */ 3634 filter = 0x7f3f; 3635 switch (vap->iv_opmode) { 3636 case IEEE80211_M_STA: 3637 filter &= ~( 3638 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 3639 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 3640 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 3641 break; 3642 case IEEE80211_M_HOSTAP: 3643 filter &= ~( 3644 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 3645 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP) | 3646 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_BEACON)); 3647 break; 3648 case IEEE80211_M_MONITOR: 3649 case IEEE80211_M_IBSS: 3650 break; 3651 default: 3652 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3653 __func__, vap->iv_opmode); 3654 break; 3655 } 3656 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 3657 3658 /* Reject all control frames. */ 3659 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3660 3661 /* Reject all data frames. */ 3662 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 3663 3664 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 3665 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 3666 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 3667 3668 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 3669 /* Accept all frames. */ 3670 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 3671 R92C_RCR_AAP; 3672 } 3673 3674 /* Set Rx filter. */ 3675 urtwn_write_4(sc, R92C_RCR, rcr); 3676 3677 if (ic->ic_promisc != 0) { 3678 /* Update Rx filter. */ 3679 urtwn_set_promisc(sc); 3680 } 3681} 3682 3683static void 3684urtwn_edca_init(struct urtwn_softc *sc) 3685{ 3686 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3687 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3688 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3689 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3690 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3691 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3692 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3693 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3694} 3695 3696static void 3697urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3698 uint16_t power[URTWN_RIDX_COUNT]) 3699{ 3700 uint32_t reg; 3701 3702 /* Write per-CCK rate Tx power. */ 3703 if (chain == 0) { 3704 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3705 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3706 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3707 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3708 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3709 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3710 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3711 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3712 } else { 3713 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3714 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3715 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3716 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3717 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3718 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3719 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3720 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3721 } 3722 /* Write per-OFDM rate Tx power. */ 3723 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3724 SM(R92C_TXAGC_RATE06, power[ 4]) | 3725 SM(R92C_TXAGC_RATE09, power[ 5]) | 3726 SM(R92C_TXAGC_RATE12, power[ 6]) | 3727 SM(R92C_TXAGC_RATE18, power[ 7])); 3728 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3729 SM(R92C_TXAGC_RATE24, power[ 8]) | 3730 SM(R92C_TXAGC_RATE36, power[ 9]) | 3731 SM(R92C_TXAGC_RATE48, power[10]) | 3732 SM(R92C_TXAGC_RATE54, power[11])); 3733 /* Write per-MCS Tx power. */ 3734 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3735 SM(R92C_TXAGC_MCS00, power[12]) | 3736 SM(R92C_TXAGC_MCS01, power[13]) | 3737 SM(R92C_TXAGC_MCS02, power[14]) | 3738 SM(R92C_TXAGC_MCS03, power[15])); 3739 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3740 SM(R92C_TXAGC_MCS04, power[16]) | 3741 SM(R92C_TXAGC_MCS05, power[17]) | 3742 SM(R92C_TXAGC_MCS06, power[18]) | 3743 SM(R92C_TXAGC_MCS07, power[19])); 3744 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3745 SM(R92C_TXAGC_MCS08, power[20]) | 3746 SM(R92C_TXAGC_MCS09, power[21]) | 3747 SM(R92C_TXAGC_MCS10, power[22]) | 3748 SM(R92C_TXAGC_MCS11, power[23])); 3749 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3750 SM(R92C_TXAGC_MCS12, power[24]) | 3751 SM(R92C_TXAGC_MCS13, power[25]) | 3752 SM(R92C_TXAGC_MCS14, power[26]) | 3753 SM(R92C_TXAGC_MCS15, power[27])); 3754} 3755 3756static void 3757urtwn_get_txpower(struct urtwn_softc *sc, int chain, 3758 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3759 uint16_t power[URTWN_RIDX_COUNT]) 3760{ 3761 struct ieee80211com *ic = &sc->sc_ic; 3762 struct r92c_rom *rom = &sc->rom.r92c_rom; 3763 uint16_t cckpow, ofdmpow, htpow, diff, max; 3764 const struct urtwn_txpwr *base; 3765 int ridx, chan, group; 3766 3767 /* Determine channel group. */ 3768 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3769 if (chan <= 3) 3770 group = 0; 3771 else if (chan <= 9) 3772 group = 1; 3773 else 3774 group = 2; 3775 3776 /* Get original Tx power based on board type and RF chain. */ 3777 if (!(sc->chip & URTWN_CHIP_92C)) { 3778 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3779 base = &rtl8188ru_txagc[chain]; 3780 else 3781 base = &rtl8192cu_txagc[chain]; 3782 } else 3783 base = &rtl8192cu_txagc[chain]; 3784 3785 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3786 if (sc->regulatory == 0) { 3787 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3788 power[ridx] = base->pwr[0][ridx]; 3789 } 3790 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3791 if (sc->regulatory == 3) { 3792 power[ridx] = base->pwr[0][ridx]; 3793 /* Apply vendor limits. */ 3794 if (extc != NULL) 3795 max = rom->ht40_max_pwr[group]; 3796 else 3797 max = rom->ht20_max_pwr[group]; 3798 max = (max >> (chain * 4)) & 0xf; 3799 if (power[ridx] > max) 3800 power[ridx] = max; 3801 } else if (sc->regulatory == 1) { 3802 if (extc == NULL) 3803 power[ridx] = base->pwr[group][ridx]; 3804 } else if (sc->regulatory != 2) 3805 power[ridx] = base->pwr[0][ridx]; 3806 } 3807 3808 /* Compute per-CCK rate Tx power. */ 3809 cckpow = rom->cck_tx_pwr[chain][group]; 3810 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3811 power[ridx] += cckpow; 3812 if (power[ridx] > R92C_MAX_TX_PWR) 3813 power[ridx] = R92C_MAX_TX_PWR; 3814 } 3815 3816 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3817 if (sc->ntxchains > 1) { 3818 /* Apply reduction for 2 spatial streams. */ 3819 diff = rom->ht40_2s_tx_pwr_diff[group]; 3820 diff = (diff >> (chain * 4)) & 0xf; 3821 htpow = (htpow > diff) ? htpow - diff : 0; 3822 } 3823 3824 /* Compute per-OFDM rate Tx power. */ 3825 diff = rom->ofdm_tx_pwr_diff[group]; 3826 diff = (diff >> (chain * 4)) & 0xf; 3827 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3828 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3829 power[ridx] += ofdmpow; 3830 if (power[ridx] > R92C_MAX_TX_PWR) 3831 power[ridx] = R92C_MAX_TX_PWR; 3832 } 3833 3834 /* Compute per-MCS Tx power. */ 3835 if (extc == NULL) { 3836 diff = rom->ht20_tx_pwr_diff[group]; 3837 diff = (diff >> (chain * 4)) & 0xf; 3838 htpow += diff; /* HT40->HT20 correction. */ 3839 } 3840 for (ridx = 12; ridx <= 27; ridx++) { 3841 power[ridx] += htpow; 3842 if (power[ridx] > R92C_MAX_TX_PWR) 3843 power[ridx] = R92C_MAX_TX_PWR; 3844 } 3845#ifdef URTWN_DEBUG 3846 if (urtwn_debug >= 4) { 3847 /* Dump per-rate Tx power values. */ 3848 printf("Tx power for chain %d:\n", chain); 3849 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 3850 printf("Rate %d = %u\n", ridx, power[ridx]); 3851 } 3852#endif 3853} 3854 3855static void 3856urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3857 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3858 uint16_t power[URTWN_RIDX_COUNT]) 3859{ 3860 struct ieee80211com *ic = &sc->sc_ic; 3861 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3862 const struct urtwn_r88e_txpwr *base; 3863 int ridx, chan, group; 3864 3865 /* Determine channel group. */ 3866 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3867 if (chan <= 2) 3868 group = 0; 3869 else if (chan <= 5) 3870 group = 1; 3871 else if (chan <= 8) 3872 group = 2; 3873 else if (chan <= 11) 3874 group = 3; 3875 else if (chan <= 13) 3876 group = 4; 3877 else 3878 group = 5; 3879 3880 /* Get original Tx power based on board type and RF chain. */ 3881 base = &rtl8188eu_txagc[chain]; 3882 3883 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3884 if (sc->regulatory == 0) { 3885 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3886 power[ridx] = base->pwr[0][ridx]; 3887 } 3888 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3889 if (sc->regulatory == 3) 3890 power[ridx] = base->pwr[0][ridx]; 3891 else if (sc->regulatory == 1) { 3892 if (extc == NULL) 3893 power[ridx] = base->pwr[group][ridx]; 3894 } else if (sc->regulatory != 2) 3895 power[ridx] = base->pwr[0][ridx]; 3896 } 3897 3898 /* Compute per-CCK rate Tx power. */ 3899 cckpow = sc->cck_tx_pwr[group]; 3900 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3901 power[ridx] += cckpow; 3902 if (power[ridx] > R92C_MAX_TX_PWR) 3903 power[ridx] = R92C_MAX_TX_PWR; 3904 } 3905 3906 htpow = sc->ht40_tx_pwr[group]; 3907 3908 /* Compute per-OFDM rate Tx power. */ 3909 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3910 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3911 power[ridx] += ofdmpow; 3912 if (power[ridx] > R92C_MAX_TX_PWR) 3913 power[ridx] = R92C_MAX_TX_PWR; 3914 } 3915 3916 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3917 for (ridx = 12; ridx <= 27; ridx++) { 3918 power[ridx] += bw20pow; 3919 if (power[ridx] > R92C_MAX_TX_PWR) 3920 power[ridx] = R92C_MAX_TX_PWR; 3921 } 3922} 3923 3924static void 3925urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3926 struct ieee80211_channel *extc) 3927{ 3928 uint16_t power[URTWN_RIDX_COUNT]; 3929 int i; 3930 3931 for (i = 0; i < sc->ntxchains; i++) { 3932 /* Compute per-rate Tx power values. */ 3933 if (sc->chip & URTWN_CHIP_88E) 3934 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3935 else 3936 urtwn_get_txpower(sc, i, c, extc, power); 3937 /* Write per-rate Tx power values to hardware. */ 3938 urtwn_write_txpower(sc, i, power); 3939 } 3940} 3941 3942static void 3943urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 3944{ 3945 uint32_t reg; 3946 3947 reg = urtwn_read_4(sc, R92C_RCR); 3948 if (enable) 3949 reg &= ~R92C_RCR_CBSSID_BCN; 3950 else 3951 reg |= R92C_RCR_CBSSID_BCN; 3952 urtwn_write_4(sc, R92C_RCR, reg); 3953} 3954 3955static void 3956urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 3957{ 3958 uint32_t reg; 3959 3960 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3961 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3962 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3963 3964 if (!(sc->chip & URTWN_CHIP_88E)) { 3965 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3966 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3967 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3968 } 3969} 3970 3971static void 3972urtwn_scan_start(struct ieee80211com *ic) 3973{ 3974 struct urtwn_softc *sc = ic->ic_softc; 3975 3976 URTWN_LOCK(sc); 3977 /* Receive beacons / probe responses from any BSSID. */ 3978 if (ic->ic_opmode != IEEE80211_M_IBSS) 3979 urtwn_set_rx_bssid_all(sc, 1); 3980 3981 /* Set gain for scanning. */ 3982 urtwn_set_gain(sc, 0x20); 3983 URTWN_UNLOCK(sc); 3984} 3985 3986static void 3987urtwn_scan_end(struct ieee80211com *ic) 3988{ 3989 struct urtwn_softc *sc = ic->ic_softc; 3990 3991 URTWN_LOCK(sc); 3992 /* Restore limitations. */ 3993 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 3994 urtwn_set_rx_bssid_all(sc, 0); 3995 3996 /* Set gain under link. */ 3997 urtwn_set_gain(sc, 0x32); 3998 URTWN_UNLOCK(sc); 3999} 4000 4001static void 4002urtwn_set_channel(struct ieee80211com *ic) 4003{ 4004 struct urtwn_softc *sc = ic->ic_softc; 4005 struct ieee80211_channel *c = ic->ic_curchan; 4006 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4007 4008 URTWN_LOCK(sc); 4009 if (vap->iv_state == IEEE80211_S_SCAN) { 4010 /* Make link LED blink during scan. */ 4011 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 4012 } 4013 urtwn_set_chan(sc, c, NULL); 4014 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 4015 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 4016 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 4017 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 4018 URTWN_UNLOCK(sc); 4019} 4020 4021static int 4022urtwn_wme_update(struct ieee80211com *ic) 4023{ 4024 const struct wmeParams *wmep = 4025 ic->ic_wme.wme_chanParams.cap_wmeParams; 4026 struct urtwn_softc *sc = ic->ic_softc; 4027 uint8_t aifs, acm, slottime; 4028 int ac; 4029 4030 acm = 0; 4031 slottime = IEEE80211_GET_SLOTTIME(ic); 4032 4033 URTWN_LOCK(sc); 4034 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4035 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4036 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4037 urtwn_write_4(sc, wme2queue[ac].reg, 4038 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 4039 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 4040 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 4041 SM(R92C_EDCA_PARAM_AIFS, aifs)); 4042 if (ac != WME_AC_BE) 4043 acm |= wmep[ac].wmep_acm << ac; 4044 } 4045 4046 if (acm != 0) 4047 acm |= R92C_ACMHWCTRL_EN; 4048 urtwn_write_1(sc, R92C_ACMHWCTRL, 4049 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 4050 acm); 4051 4052 URTWN_UNLOCK(sc); 4053 4054 return 0; 4055} 4056 4057static void 4058urtwn_set_promisc(struct urtwn_softc *sc) 4059{ 4060 struct ieee80211com *ic = &sc->sc_ic; 4061 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4062 uint32_t rcr, mask1, mask2; 4063 4064 URTWN_ASSERT_LOCKED(sc); 4065 4066 if (vap->iv_opmode == IEEE80211_M_MONITOR) 4067 return; 4068 4069 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 4070 mask2 = R92C_RCR_APM; 4071 4072 if (vap->iv_state == IEEE80211_S_RUN) { 4073 switch (vap->iv_opmode) { 4074 case IEEE80211_M_STA: 4075 mask2 |= R92C_RCR_CBSSID_DATA; 4076 /* FALLTHROUGH */ 4077 case IEEE80211_M_HOSTAP: 4078 mask2 |= R92C_RCR_CBSSID_BCN; 4079 break; 4080 case IEEE80211_M_IBSS: 4081 mask2 |= R92C_RCR_CBSSID_DATA; 4082 break; 4083 default: 4084 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4085 __func__, vap->iv_opmode); 4086 return; 4087 } 4088 } 4089 4090 rcr = urtwn_read_4(sc, R92C_RCR); 4091 if (ic->ic_promisc == 0) 4092 rcr = (rcr & ~mask1) | mask2; 4093 else 4094 rcr = (rcr & ~mask2) | mask1; 4095 urtwn_write_4(sc, R92C_RCR, rcr); 4096} 4097 4098static void 4099urtwn_update_promisc(struct ieee80211com *ic) 4100{ 4101 struct urtwn_softc *sc = ic->ic_softc; 4102 4103 URTWN_LOCK(sc); 4104 if (sc->sc_flags & URTWN_RUNNING) 4105 urtwn_set_promisc(sc); 4106 URTWN_UNLOCK(sc); 4107} 4108 4109static void 4110urtwn_update_mcast(struct ieee80211com *ic) 4111{ 4112 /* XXX do nothing? */ 4113} 4114 4115static struct ieee80211_node * 4116urtwn_r88e_node_alloc(struct ieee80211vap *vap, 4117 const uint8_t mac[IEEE80211_ADDR_LEN]) 4118{ 4119 struct urtwn_node *un; 4120 4121 un = malloc(sizeof (struct urtwn_node), M_80211_NODE, 4122 M_NOWAIT | M_ZERO); 4123 4124 if (un == NULL) 4125 return NULL; 4126 4127 un->id = URTWN_MACID_UNDEFINED; 4128 4129 return &un->ni; 4130} 4131 4132static void 4133urtwn_r88e_newassoc(struct ieee80211_node *ni, int isnew) 4134{ 4135 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4136 struct urtwn_node *un = URTWN_NODE(ni); 4137 uint8_t id; 4138 4139 if (!isnew) 4140 return; 4141 4142 URTWN_NT_LOCK(sc); 4143 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 4144 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 4145 un->id = id; 4146 sc->node_list[id] = ni; 4147 break; 4148 } 4149 } 4150 URTWN_NT_UNLOCK(sc); 4151 4152 if (id > URTWN_MACID_MAX(sc)) { 4153 device_printf(sc->sc_dev, "%s: node table is full\n", 4154 __func__); 4155 } 4156} 4157 4158static void 4159urtwn_r88e_node_free(struct ieee80211_node *ni) 4160{ 4161 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4162 struct urtwn_node *un = URTWN_NODE(ni); 4163 4164 URTWN_NT_LOCK(sc); 4165 if (un->id != URTWN_MACID_UNDEFINED) 4166 sc->node_list[un->id] = NULL; 4167 URTWN_NT_UNLOCK(sc); 4168 4169 sc->sc_node_free(ni); 4170} 4171 4172static void 4173urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 4174 struct ieee80211_channel *extc) 4175{ 4176 struct ieee80211com *ic = &sc->sc_ic; 4177 uint32_t reg; 4178 u_int chan; 4179 int i; 4180 4181 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4182 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 4183 device_printf(sc->sc_dev, 4184 "%s: invalid channel %x\n", __func__, chan); 4185 return; 4186 } 4187 4188 /* Set Tx power for this new channel. */ 4189 urtwn_set_txpower(sc, c, extc); 4190 4191 for (i = 0; i < sc->nrxchains; i++) { 4192 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4193 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4194 } 4195#ifndef IEEE80211_NO_HT 4196 if (extc != NULL) { 4197 /* Is secondary channel below or above primary? */ 4198 int prichlo = c->ic_freq < extc->ic_freq; 4199 4200 urtwn_write_1(sc, R92C_BWOPMODE, 4201 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4202 4203 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4204 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4205 urtwn_write_1(sc, R92C_RRSR + 2, reg); 4206 4207 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4208 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4209 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4210 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4211 4212 /* Set CCK side band. */ 4213 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4214 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4215 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4216 4217 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4218 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4219 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4220 4221 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4222 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4223 ~R92C_FPGA0_ANAPARAM2_CBW20); 4224 4225 reg = urtwn_bb_read(sc, 0x818); 4226 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4227 urtwn_bb_write(sc, 0x818, reg); 4228 4229 /* Select 40MHz bandwidth. */ 4230 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4231 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4232 } else 4233#endif 4234 { 4235 urtwn_write_1(sc, R92C_BWOPMODE, 4236 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4237 4238 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4239 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4240 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4241 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4242 4243 if (!(sc->chip & URTWN_CHIP_88E)) { 4244 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4245 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4246 R92C_FPGA0_ANAPARAM2_CBW20); 4247 } 4248 4249 /* Select 20MHz bandwidth. */ 4250 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4251 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4252 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 4253 R92C_RF_CHNLBW_BW20)); 4254 } 4255} 4256 4257static void 4258urtwn_iq_calib(struct urtwn_softc *sc) 4259{ 4260 /* TODO */ 4261} 4262 4263static void 4264urtwn_lc_calib(struct urtwn_softc *sc) 4265{ 4266 uint32_t rf_ac[2]; 4267 uint8_t txmode; 4268 int i; 4269 4270 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4271 if ((txmode & 0x70) != 0) { 4272 /* Disable all continuous Tx. */ 4273 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4274 4275 /* Set RF mode to standby mode. */ 4276 for (i = 0; i < sc->nrxchains; i++) { 4277 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4278 urtwn_rf_write(sc, i, R92C_RF_AC, 4279 RW(rf_ac[i], R92C_RF_AC_MODE, 4280 R92C_RF_AC_MODE_STANDBY)); 4281 } 4282 } else { 4283 /* Block all Tx queues. */ 4284 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4285 } 4286 /* Start calibration. */ 4287 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4288 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4289 4290 /* Give calibration the time to complete. */ 4291 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 4292 4293 /* Restore configuration. */ 4294 if ((txmode & 0x70) != 0) { 4295 /* Restore Tx mode. */ 4296 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4297 /* Restore RF mode. */ 4298 for (i = 0; i < sc->nrxchains; i++) 4299 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4300 } else { 4301 /* Unblock all Tx queues. */ 4302 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4303 } 4304} 4305 4306static int 4307urtwn_init(struct urtwn_softc *sc) 4308{ 4309 struct ieee80211com *ic = &sc->sc_ic; 4310 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4311 uint8_t macaddr[IEEE80211_ADDR_LEN]; 4312 uint32_t reg; 4313 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 4314 int error; 4315 4316 URTWN_LOCK(sc); 4317 if (sc->sc_flags & URTWN_RUNNING) { 4318 URTWN_UNLOCK(sc); 4319 return (0); 4320 } 4321 4322 /* Init firmware commands ring. */ 4323 sc->fwcur = 0; 4324 4325 /* Allocate Tx/Rx buffers. */ 4326 error = urtwn_alloc_rx_list(sc); 4327 if (error != 0) 4328 goto fail; 4329 4330 error = urtwn_alloc_tx_list(sc); 4331 if (error != 0) 4332 goto fail; 4333 4334 /* Power on adapter. */ 4335 error = urtwn_power_on(sc); 4336 if (error != 0) 4337 goto fail; 4338 4339 /* Initialize DMA. */ 4340 error = urtwn_dma_init(sc); 4341 if (error != 0) 4342 goto fail; 4343 4344 /* Set info size in Rx descriptors (in 64-bit words). */ 4345 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4346 4347 /* Init interrupts. */ 4348 if (sc->chip & URTWN_CHIP_88E) { 4349 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4350 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4351 goto fail; 4352 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4353 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4354 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4355 goto fail; 4356 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4357 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4358 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4359 goto fail; 4360 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4361 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4362 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4363 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4364 goto fail; 4365 } else { 4366 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4367 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4368 goto fail; 4369 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4370 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4371 goto fail; 4372 } 4373 4374 /* Set MAC address. */ 4375 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 4376 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 4377 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4378 goto fail; 4379 4380 /* Set initial network type. */ 4381 urtwn_set_mode(sc, R92C_MSR_INFRA); 4382 4383 /* Initialize Rx filter. */ 4384 urtwn_rxfilter_init(sc); 4385 4386 /* Set response rate. */ 4387 reg = urtwn_read_4(sc, R92C_RRSR); 4388 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4389 urtwn_write_4(sc, R92C_RRSR, reg); 4390 4391 /* Set short/long retry limits. */ 4392 urtwn_write_2(sc, R92C_RL, 4393 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4394 4395 /* Initialize EDCA parameters. */ 4396 urtwn_edca_init(sc); 4397 4398 /* Setup rate fallback. */ 4399 if (!(sc->chip & URTWN_CHIP_88E)) { 4400 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4401 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4402 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4403 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4404 } 4405 4406 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4407 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4408 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4409 /* Set ACK timeout. */ 4410 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4411 4412 /* Setup USB aggregation. */ 4413 reg = urtwn_read_4(sc, R92C_TDECTRL); 4414 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4415 urtwn_write_4(sc, R92C_TDECTRL, reg); 4416 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4417 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4418 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4419 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4420 if (sc->chip & URTWN_CHIP_88E) 4421 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4422 else { 4423 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4424 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4425 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4426 R92C_USB_SPECIAL_OPTION_AGG_EN); 4427 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 4428 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 4429 } 4430 4431 /* Initialize beacon parameters. */ 4432 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4433 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4434 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 4435 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 4436 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4437 4438 if (!(sc->chip & URTWN_CHIP_88E)) { 4439 /* Setup AMPDU aggregation. */ 4440 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4441 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4442 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 4443 4444 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4445 } 4446 4447 /* Load 8051 microcode. */ 4448 error = urtwn_load_firmware(sc); 4449 if (error != 0) 4450 goto fail; 4451 4452 /* Initialize MAC/BB/RF blocks. */ 4453 error = urtwn_mac_init(sc); 4454 if (error != 0) { 4455 device_printf(sc->sc_dev, 4456 "%s: error while initializing MAC block\n", __func__); 4457 goto fail; 4458 } 4459 urtwn_bb_init(sc); 4460 urtwn_rf_init(sc); 4461 4462 /* Reinitialize Rx filter (D3845 is not committed yet). */ 4463 urtwn_rxfilter_init(sc); 4464 4465 if (sc->chip & URTWN_CHIP_88E) { 4466 urtwn_write_2(sc, R92C_CR, 4467 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4468 R92C_CR_MACRXEN); 4469 } 4470 4471 /* Turn CCK and OFDM blocks on. */ 4472 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4473 reg |= R92C_RFMOD_CCK_EN; 4474 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4475 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4476 goto fail; 4477 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4478 reg |= R92C_RFMOD_OFDM_EN; 4479 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4480 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4481 goto fail; 4482 4483 /* Clear per-station keys table. */ 4484 urtwn_cam_init(sc); 4485 4486 /* Enable decryption / encryption. */ 4487 urtwn_write_2(sc, R92C_SECCFG, 4488 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 4489 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA | 4490 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 4491 4492 /* 4493 * Install static keys (if any). 4494 * Must be called after urtwn_cam_init(). 4495 */ 4496 ieee80211_runtask(ic, &sc->cmdq_task); 4497 4498 /* Enable hardware sequence numbering. */ 4499 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4500 4501 /* Enable per-packet TX report. */ 4502 if (sc->chip & URTWN_CHIP_88E) { 4503 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 4504 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 4505 } 4506 4507 /* Perform LO and IQ calibrations. */ 4508 urtwn_iq_calib(sc); 4509 /* Perform LC calibration. */ 4510 urtwn_lc_calib(sc); 4511 4512 /* Fix USB interference issue. */ 4513 if (!(sc->chip & URTWN_CHIP_88E)) { 4514 urtwn_write_1(sc, 0xfe40, 0xe0); 4515 urtwn_write_1(sc, 0xfe41, 0x8d); 4516 urtwn_write_1(sc, 0xfe42, 0x80); 4517 4518 urtwn_pa_bias_init(sc); 4519 } 4520 4521 /* Initialize GPIO setting. */ 4522 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4523 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4524 4525 /* Fix for lower temperature. */ 4526 if (!(sc->chip & URTWN_CHIP_88E)) 4527 urtwn_write_1(sc, 0x15, 0xe9); 4528 4529 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 4530 4531 sc->sc_flags |= URTWN_RUNNING; 4532 4533 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4534fail: 4535 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4536 error = EIO; 4537 4538 URTWN_UNLOCK(sc); 4539 4540 return (error); 4541} 4542 4543static void 4544urtwn_stop(struct urtwn_softc *sc) 4545{ 4546 4547 URTWN_LOCK(sc); 4548 if (!(sc->sc_flags & URTWN_RUNNING)) { 4549 URTWN_UNLOCK(sc); 4550 return; 4551 } 4552 4553 sc->sc_flags &= ~URTWN_RUNNING; 4554 callout_stop(&sc->sc_watchdog_ch); 4555 urtwn_abort_xfers(sc); 4556 4557 urtwn_drain_mbufq(sc); 4558 URTWN_UNLOCK(sc); 4559} 4560 4561static void 4562urtwn_abort_xfers(struct urtwn_softc *sc) 4563{ 4564 int i; 4565 4566 URTWN_ASSERT_LOCKED(sc); 4567 4568 /* abort any pending transfers */ 4569 for (i = 0; i < URTWN_N_TRANSFER; i++) 4570 usbd_transfer_stop(sc->sc_xfer[i]); 4571} 4572 4573static int 4574urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4575 const struct ieee80211_bpf_params *params) 4576{ 4577 struct ieee80211com *ic = ni->ni_ic; 4578 struct urtwn_softc *sc = ic->ic_softc; 4579 struct urtwn_data *bf; 4580 int error; 4581 4582 /* prevent management frames from being sent if we're not ready */ 4583 URTWN_LOCK(sc); 4584 if (!(sc->sc_flags & URTWN_RUNNING)) { 4585 error = ENETDOWN; 4586 goto end; 4587 } 4588 4589 bf = urtwn_getbuf(sc); 4590 if (bf == NULL) { 4591 error = ENOBUFS; 4592 goto end; 4593 } 4594 4595 if ((error = urtwn_tx_data(sc, ni, m, bf)) != 0) { 4596 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 4597 goto end; 4598 } 4599 4600 sc->sc_txtimer = 5; 4601 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4602 4603end: 4604 if (error != 0) 4605 m_freem(m); 4606 4607 URTWN_UNLOCK(sc); 4608 4609 return (error); 4610} 4611 4612static void 4613urtwn_ms_delay(struct urtwn_softc *sc) 4614{ 4615 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 4616} 4617 4618static device_method_t urtwn_methods[] = { 4619 /* Device interface */ 4620 DEVMETHOD(device_probe, urtwn_match), 4621 DEVMETHOD(device_attach, urtwn_attach), 4622 DEVMETHOD(device_detach, urtwn_detach), 4623 4624 DEVMETHOD_END 4625}; 4626 4627static driver_t urtwn_driver = { 4628 "urtwn", 4629 urtwn_methods, 4630 sizeof(struct urtwn_softc) 4631}; 4632 4633static devclass_t urtwn_devclass; 4634 4635DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 4636MODULE_DEPEND(urtwn, usb, 1, 1, 1); 4637MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 4638MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 4639MODULE_VERSION(urtwn, 1); 4640USB_PNP_HOST_INFO(urtwn_devs); 4641