if_urtwn.c revision 292175
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 292175 2015-12-13 22:00:19Z avos $"); 22 23/* 24 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25 */ 26 27#include "opt_wlan.h" 28 29#include <sys/param.h> 30#include <sys/sockio.h> 31#include <sys/sysctl.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/condvar.h> 35#include <sys/mbuf.h> 36#include <sys/kernel.h> 37#include <sys/socket.h> 38#include <sys/systm.h> 39#include <sys/malloc.h> 40#include <sys/module.h> 41#include <sys/bus.h> 42#include <sys/endian.h> 43#include <sys/linker.h> 44#include <sys/firmware.h> 45#include <sys/kdb.h> 46 47#include <machine/bus.h> 48#include <machine/resource.h> 49#include <sys/rman.h> 50 51#include <net/bpf.h> 52#include <net/if.h> 53#include <net/if_var.h> 54#include <net/if_arp.h> 55#include <net/ethernet.h> 56#include <net/if_dl.h> 57#include <net/if_media.h> 58#include <net/if_types.h> 59 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/in_var.h> 63#include <netinet/if_ether.h> 64#include <netinet/ip.h> 65 66#include <net80211/ieee80211_var.h> 67#include <net80211/ieee80211_input.h> 68#include <net80211/ieee80211_regdomain.h> 69#include <net80211/ieee80211_radiotap.h> 70#include <net80211/ieee80211_ratectl.h> 71 72#include <dev/usb/usb.h> 73#include <dev/usb/usbdi.h> 74#include <dev/usb/usb_device.h> 75#include "usbdevs.h" 76 77#define USB_DEBUG_VAR urtwn_debug 78#include <dev/usb/usb_debug.h> 79 80#include <dev/usb/wlan/if_urtwnreg.h> 81#include <dev/usb/wlan/if_urtwnvar.h> 82 83#ifdef USB_DEBUG 84static int urtwn_debug = 0; 85 86SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 87SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 88 "Debug level"); 89#endif 90 91#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 92 93/* various supported device vendors/products */ 94static const STRUCT_USB_HOST_ID urtwn_devs[] = { 95#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 96#define URTWN_RTL8188E_DEV(v,p) \ 97 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 98#define URTWN_RTL8188E 1 99 URTWN_DEV(ABOCOM, RTL8188CU_1), 100 URTWN_DEV(ABOCOM, RTL8188CU_2), 101 URTWN_DEV(ABOCOM, RTL8192CU), 102 URTWN_DEV(ASUS, RTL8192CU), 103 URTWN_DEV(ASUS, USBN10NANO), 104 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 105 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 106 URTWN_DEV(AZUREWAVE, RTL8188CU), 107 URTWN_DEV(BELKIN, F7D2102), 108 URTWN_DEV(BELKIN, RTL8188CU), 109 URTWN_DEV(BELKIN, RTL8192CU), 110 URTWN_DEV(CHICONY, RTL8188CUS_1), 111 URTWN_DEV(CHICONY, RTL8188CUS_2), 112 URTWN_DEV(CHICONY, RTL8188CUS_3), 113 URTWN_DEV(CHICONY, RTL8188CUS_4), 114 URTWN_DEV(CHICONY, RTL8188CUS_5), 115 URTWN_DEV(COREGA, RTL8192CU), 116 URTWN_DEV(DLINK, RTL8188CU), 117 URTWN_DEV(DLINK, RTL8192CU_1), 118 URTWN_DEV(DLINK, RTL8192CU_2), 119 URTWN_DEV(DLINK, RTL8192CU_3), 120 URTWN_DEV(DLINK, DWA131B), 121 URTWN_DEV(EDIMAX, EW7811UN), 122 URTWN_DEV(EDIMAX, RTL8192CU), 123 URTWN_DEV(FEIXUN, RTL8188CU), 124 URTWN_DEV(FEIXUN, RTL8192CU), 125 URTWN_DEV(GUILLEMOT, HWNUP150), 126 URTWN_DEV(HAWKING, RTL8192CU), 127 URTWN_DEV(HP3, RTL8188CU), 128 URTWN_DEV(NETGEAR, WNA1000M), 129 URTWN_DEV(NETGEAR, RTL8192CU), 130 URTWN_DEV(NETGEAR4, RTL8188CU), 131 URTWN_DEV(NOVATECH, RTL8188CU), 132 URTWN_DEV(PLANEX2, RTL8188CU_1), 133 URTWN_DEV(PLANEX2, RTL8188CU_2), 134 URTWN_DEV(PLANEX2, RTL8188CU_3), 135 URTWN_DEV(PLANEX2, RTL8188CU_4), 136 URTWN_DEV(PLANEX2, RTL8188CUS), 137 URTWN_DEV(PLANEX2, RTL8192CU), 138 URTWN_DEV(REALTEK, RTL8188CE_0), 139 URTWN_DEV(REALTEK, RTL8188CE_1), 140 URTWN_DEV(REALTEK, RTL8188CTV), 141 URTWN_DEV(REALTEK, RTL8188CU_0), 142 URTWN_DEV(REALTEK, RTL8188CU_1), 143 URTWN_DEV(REALTEK, RTL8188CU_2), 144 URTWN_DEV(REALTEK, RTL8188CU_3), 145 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 146 URTWN_DEV(REALTEK, RTL8188CUS), 147 URTWN_DEV(REALTEK, RTL8188RU_1), 148 URTWN_DEV(REALTEK, RTL8188RU_2), 149 URTWN_DEV(REALTEK, RTL8188RU_3), 150 URTWN_DEV(REALTEK, RTL8191CU), 151 URTWN_DEV(REALTEK, RTL8192CE), 152 URTWN_DEV(REALTEK, RTL8192CU), 153 URTWN_DEV(SITECOMEU, RTL8188CU_1), 154 URTWN_DEV(SITECOMEU, RTL8188CU_2), 155 URTWN_DEV(SITECOMEU, RTL8192CU), 156 URTWN_DEV(TRENDNET, RTL8188CU), 157 URTWN_DEV(TRENDNET, RTL8192CU), 158 URTWN_DEV(ZYXEL, RTL8192CU), 159 /* URTWN_RTL8188E */ 160 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 161 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 162 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 163 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 164 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 165#undef URTWN_RTL8188E_DEV 166#undef URTWN_DEV 167}; 168 169static device_probe_t urtwn_match; 170static device_attach_t urtwn_attach; 171static device_detach_t urtwn_detach; 172 173static usb_callback_t urtwn_bulk_tx_callback; 174static usb_callback_t urtwn_bulk_rx_callback; 175 176static void urtwn_drain_mbufq(struct urtwn_softc *sc); 177static usb_error_t urtwn_do_request(struct urtwn_softc *, 178 struct usb_device_request *, void *); 179static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 180 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 181 const uint8_t [IEEE80211_ADDR_LEN], 182 const uint8_t [IEEE80211_ADDR_LEN]); 183static void urtwn_vap_delete(struct ieee80211vap *); 184static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 185 int *); 186static struct mbuf * urtwn_report_intr(struct usb_xfer *, struct urtwn_data *, 187 int *, int8_t *); 188static struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int, 189 int *, int8_t *); 190static void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 191 void *); 192static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 193 int); 194static int urtwn_alloc_list(struct urtwn_softc *, 195 struct urtwn_data[], int, int); 196static int urtwn_alloc_rx_list(struct urtwn_softc *); 197static int urtwn_alloc_tx_list(struct urtwn_softc *); 198static void urtwn_free_list(struct urtwn_softc *, 199 struct urtwn_data data[], int); 200static void urtwn_free_rx_list(struct urtwn_softc *); 201static void urtwn_free_tx_list(struct urtwn_softc *); 202static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 203static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 204static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 205 uint8_t *, int); 206static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 207static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 208static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 209static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 210 uint8_t *, int); 211static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 212static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 213static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 214static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 215 const void *, int); 216static void urtwn_cmdq_cb(void *, int); 217static int urtwn_cmd_sleepable(struct urtwn_softc *, const void *, 218 size_t, CMD_FUNC_PROTO); 219static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 220 uint8_t, uint32_t); 221static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 222 uint8_t, uint32_t); 223static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 224static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 225 uint32_t); 226static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 227static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 228 uint8_t, uint8_t); 229#ifdef URTWN_DEBUG 230static void urtwn_dump_rom_contents(struct urtwn_softc *, 231 uint8_t *, uint16_t); 232#endif 233static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 234 uint16_t); 235static int urtwn_efuse_switch_power(struct urtwn_softc *); 236static int urtwn_read_chipid(struct urtwn_softc *); 237static int urtwn_read_rom(struct urtwn_softc *); 238static int urtwn_r88e_read_rom(struct urtwn_softc *); 239static int urtwn_ra_init(struct urtwn_softc *); 240static void urtwn_init_beacon(struct urtwn_softc *, 241 struct urtwn_vap *); 242static int urtwn_setup_beacon(struct urtwn_softc *, 243 struct ieee80211_node *); 244static void urtwn_update_beacon(struct ieee80211vap *, int); 245static int urtwn_tx_beacon(struct urtwn_softc *sc, 246 struct urtwn_vap *); 247static int urtwn_key_alloc(struct ieee80211vap *, 248 struct ieee80211_key *, ieee80211_keyix *, 249 ieee80211_keyix *); 250static void urtwn_key_set_cb(struct urtwn_softc *, 251 union sec_param *); 252static void urtwn_key_del_cb(struct urtwn_softc *, 253 union sec_param *); 254static int urtwn_key_set(struct ieee80211vap *, 255 const struct ieee80211_key *); 256static int urtwn_key_delete(struct ieee80211vap *, 257 const struct ieee80211_key *); 258static void urtwn_tsf_task_adhoc(void *, int); 259static void urtwn_tsf_sync_enable(struct urtwn_softc *, 260 struct ieee80211vap *); 261static void urtwn_set_led(struct urtwn_softc *, int, int); 262static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 263static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 264 struct mbuf *, int, 265 const struct ieee80211_rx_stats *, int, int); 266static int urtwn_newstate(struct ieee80211vap *, 267 enum ieee80211_state, int); 268static void urtwn_watchdog(void *); 269static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 270static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 271static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 272static int urtwn_tx_data(struct urtwn_softc *, 273 struct ieee80211_node *, struct mbuf *, 274 struct urtwn_data *); 275static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 276 uint8_t, struct urtwn_data *); 277static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 278static void urtwn_start(struct urtwn_softc *); 279static void urtwn_parent(struct ieee80211com *); 280static int urtwn_r92c_power_on(struct urtwn_softc *); 281static int urtwn_r88e_power_on(struct urtwn_softc *); 282static int urtwn_llt_init(struct urtwn_softc *); 283static void urtwn_fw_reset(struct urtwn_softc *); 284static void urtwn_r88e_fw_reset(struct urtwn_softc *); 285static int urtwn_fw_loadpage(struct urtwn_softc *, int, 286 const uint8_t *, int); 287static int urtwn_load_firmware(struct urtwn_softc *); 288static int urtwn_dma_init(struct urtwn_softc *); 289static int urtwn_mac_init(struct urtwn_softc *); 290static void urtwn_bb_init(struct urtwn_softc *); 291static void urtwn_rf_init(struct urtwn_softc *); 292static void urtwn_cam_init(struct urtwn_softc *); 293static int urtwn_cam_write(struct urtwn_softc *, uint32_t, 294 uint32_t); 295static void urtwn_pa_bias_init(struct urtwn_softc *); 296static void urtwn_rxfilter_init(struct urtwn_softc *); 297static void urtwn_edca_init(struct urtwn_softc *); 298static void urtwn_write_txpower(struct urtwn_softc *, int, 299 uint16_t[]); 300static void urtwn_get_txpower(struct urtwn_softc *, int, 301 struct ieee80211_channel *, 302 struct ieee80211_channel *, uint16_t[]); 303static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 304 struct ieee80211_channel *, 305 struct ieee80211_channel *, uint16_t[]); 306static void urtwn_set_txpower(struct urtwn_softc *, 307 struct ieee80211_channel *, 308 struct ieee80211_channel *); 309static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 310static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 311static void urtwn_scan_start(struct ieee80211com *); 312static void urtwn_scan_end(struct ieee80211com *); 313static void urtwn_set_channel(struct ieee80211com *); 314static int urtwn_wme_update(struct ieee80211com *); 315static void urtwn_set_promisc(struct urtwn_softc *); 316static void urtwn_update_promisc(struct ieee80211com *); 317static void urtwn_update_mcast(struct ieee80211com *); 318static struct ieee80211_node *urtwn_r88e_node_alloc(struct ieee80211vap *, 319 const uint8_t mac[IEEE80211_ADDR_LEN]); 320static void urtwn_r88e_newassoc(struct ieee80211_node *, int); 321static void urtwn_r88e_node_free(struct ieee80211_node *); 322static void urtwn_set_chan(struct urtwn_softc *, 323 struct ieee80211_channel *, 324 struct ieee80211_channel *); 325static void urtwn_iq_calib(struct urtwn_softc *); 326static void urtwn_lc_calib(struct urtwn_softc *); 327static int urtwn_init(struct urtwn_softc *); 328static void urtwn_stop(struct urtwn_softc *); 329static void urtwn_abort_xfers(struct urtwn_softc *); 330static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 331 const struct ieee80211_bpf_params *); 332static void urtwn_ms_delay(struct urtwn_softc *); 333 334/* Aliases. */ 335#define urtwn_bb_write urtwn_write_4 336#define urtwn_bb_read urtwn_read_4 337 338static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 339 [URTWN_BULK_RX] = { 340 .type = UE_BULK, 341 .endpoint = UE_ADDR_ANY, 342 .direction = UE_DIR_IN, 343 .bufsize = URTWN_RXBUFSZ, 344 .flags = { 345 .pipe_bof = 1, 346 .short_xfer_ok = 1 347 }, 348 .callback = urtwn_bulk_rx_callback, 349 }, 350 [URTWN_BULK_TX_BE] = { 351 .type = UE_BULK, 352 .endpoint = 0x03, 353 .direction = UE_DIR_OUT, 354 .bufsize = URTWN_TXBUFSZ, 355 .flags = { 356 .ext_buffer = 1, 357 .pipe_bof = 1, 358 .force_short_xfer = 1 359 }, 360 .callback = urtwn_bulk_tx_callback, 361 .timeout = URTWN_TX_TIMEOUT, /* ms */ 362 }, 363 [URTWN_BULK_TX_BK] = { 364 .type = UE_BULK, 365 .endpoint = 0x03, 366 .direction = UE_DIR_OUT, 367 .bufsize = URTWN_TXBUFSZ, 368 .flags = { 369 .ext_buffer = 1, 370 .pipe_bof = 1, 371 .force_short_xfer = 1, 372 }, 373 .callback = urtwn_bulk_tx_callback, 374 .timeout = URTWN_TX_TIMEOUT, /* ms */ 375 }, 376 [URTWN_BULK_TX_VI] = { 377 .type = UE_BULK, 378 .endpoint = 0x02, 379 .direction = UE_DIR_OUT, 380 .bufsize = URTWN_TXBUFSZ, 381 .flags = { 382 .ext_buffer = 1, 383 .pipe_bof = 1, 384 .force_short_xfer = 1 385 }, 386 .callback = urtwn_bulk_tx_callback, 387 .timeout = URTWN_TX_TIMEOUT, /* ms */ 388 }, 389 [URTWN_BULK_TX_VO] = { 390 .type = UE_BULK, 391 .endpoint = 0x02, 392 .direction = UE_DIR_OUT, 393 .bufsize = URTWN_TXBUFSZ, 394 .flags = { 395 .ext_buffer = 1, 396 .pipe_bof = 1, 397 .force_short_xfer = 1 398 }, 399 .callback = urtwn_bulk_tx_callback, 400 .timeout = URTWN_TX_TIMEOUT, /* ms */ 401 }, 402}; 403 404static const struct wme_to_queue { 405 uint16_t reg; 406 uint8_t qid; 407} wme2queue[WME_NUM_AC] = { 408 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 409 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 410 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 411 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 412}; 413 414static int 415urtwn_match(device_t self) 416{ 417 struct usb_attach_arg *uaa = device_get_ivars(self); 418 419 if (uaa->usb_mode != USB_MODE_HOST) 420 return (ENXIO); 421 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 422 return (ENXIO); 423 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 424 return (ENXIO); 425 426 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 427} 428 429static int 430urtwn_attach(device_t self) 431{ 432 struct usb_attach_arg *uaa = device_get_ivars(self); 433 struct urtwn_softc *sc = device_get_softc(self); 434 struct ieee80211com *ic = &sc->sc_ic; 435 uint8_t bands; 436 int error; 437 438 device_set_usb_desc(self); 439 sc->sc_udev = uaa->device; 440 sc->sc_dev = self; 441 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 442 sc->chip |= URTWN_CHIP_88E; 443 444 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 445 MTX_NETWORK_LOCK, MTX_DEF); 446 URTWN_CMDQ_LOCK_INIT(sc); 447 URTWN_NT_LOCK_INIT(sc); 448 callout_init(&sc->sc_watchdog_ch, 0); 449 mbufq_init(&sc->sc_snd, ifqmaxlen); 450 451 sc->sc_iface_index = URTWN_IFACE_INDEX; 452 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 453 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 454 if (error) { 455 device_printf(self, "could not allocate USB transfers, " 456 "err=%s\n", usbd_errstr(error)); 457 goto detach; 458 } 459 460 URTWN_LOCK(sc); 461 462 error = urtwn_read_chipid(sc); 463 if (error) { 464 device_printf(sc->sc_dev, "unsupported test chip\n"); 465 URTWN_UNLOCK(sc); 466 goto detach; 467 } 468 469 /* Determine number of Tx/Rx chains. */ 470 if (sc->chip & URTWN_CHIP_92C) { 471 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 472 sc->nrxchains = 2; 473 } else { 474 sc->ntxchains = 1; 475 sc->nrxchains = 1; 476 } 477 478 if (sc->chip & URTWN_CHIP_88E) 479 error = urtwn_r88e_read_rom(sc); 480 else 481 error = urtwn_read_rom(sc); 482 if (error != 0) { 483 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 484 __func__, error); 485 URTWN_UNLOCK(sc); 486 goto detach; 487 } 488 489 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 490 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 491 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 492 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 493 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 494 "8188CUS", sc->ntxchains, sc->nrxchains); 495 496 URTWN_UNLOCK(sc); 497 498 ic->ic_softc = sc; 499 ic->ic_name = device_get_nameunit(self); 500 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 501 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 502 503 /* set device capabilities */ 504 ic->ic_caps = 505 IEEE80211_C_STA /* station mode */ 506 | IEEE80211_C_MONITOR /* monitor mode */ 507 | IEEE80211_C_IBSS /* adhoc mode */ 508 | IEEE80211_C_HOSTAP /* hostap mode */ 509 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 510 | IEEE80211_C_SHSLOT /* short slot time supported */ 511 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 512 | IEEE80211_C_WPA /* 802.11i */ 513 | IEEE80211_C_WME /* 802.11e */ 514 ; 515 516 ic->ic_cryptocaps = 517 IEEE80211_CRYPTO_WEP | 518 IEEE80211_CRYPTO_TKIP | 519 IEEE80211_CRYPTO_AES_CCM; 520 521 bands = 0; 522 setbit(&bands, IEEE80211_MODE_11B); 523 setbit(&bands, IEEE80211_MODE_11G); 524 ieee80211_init_channels(ic, NULL, &bands); 525 526 ieee80211_ifattach(ic); 527 ic->ic_raw_xmit = urtwn_raw_xmit; 528 ic->ic_scan_start = urtwn_scan_start; 529 ic->ic_scan_end = urtwn_scan_end; 530 ic->ic_set_channel = urtwn_set_channel; 531 ic->ic_transmit = urtwn_transmit; 532 ic->ic_parent = urtwn_parent; 533 ic->ic_vap_create = urtwn_vap_create; 534 ic->ic_vap_delete = urtwn_vap_delete; 535 ic->ic_wme.wme_update = urtwn_wme_update; 536 ic->ic_update_promisc = urtwn_update_promisc; 537 ic->ic_update_mcast = urtwn_update_mcast; 538 if (sc->chip & URTWN_CHIP_88E) { 539 ic->ic_node_alloc = urtwn_r88e_node_alloc; 540 ic->ic_newassoc = urtwn_r88e_newassoc; 541 sc->sc_node_free = ic->ic_node_free; 542 ic->ic_node_free = urtwn_r88e_node_free; 543 } 544 545 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 546 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 547 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 548 URTWN_RX_RADIOTAP_PRESENT); 549 550 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc); 551 552 if (bootverbose) 553 ieee80211_announce(ic); 554 555 return (0); 556 557detach: 558 urtwn_detach(self); 559 return (ENXIO); /* failure */ 560} 561 562static int 563urtwn_detach(device_t self) 564{ 565 struct urtwn_softc *sc = device_get_softc(self); 566 struct ieee80211com *ic = &sc->sc_ic; 567 unsigned int x; 568 569 /* Prevent further ioctls. */ 570 URTWN_LOCK(sc); 571 sc->sc_flags |= URTWN_DETACHED; 572 URTWN_UNLOCK(sc); 573 574 urtwn_stop(sc); 575 576 callout_drain(&sc->sc_watchdog_ch); 577 578 /* stop all USB transfers */ 579 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 580 581 /* Prevent further allocations from RX/TX data lists. */ 582 URTWN_LOCK(sc); 583 STAILQ_INIT(&sc->sc_tx_active); 584 STAILQ_INIT(&sc->sc_tx_inactive); 585 STAILQ_INIT(&sc->sc_tx_pending); 586 587 STAILQ_INIT(&sc->sc_rx_active); 588 STAILQ_INIT(&sc->sc_rx_inactive); 589 URTWN_UNLOCK(sc); 590 591 /* drain USB transfers */ 592 for (x = 0; x != URTWN_N_TRANSFER; x++) 593 usbd_transfer_drain(sc->sc_xfer[x]); 594 595 /* Free data buffers. */ 596 URTWN_LOCK(sc); 597 urtwn_free_tx_list(sc); 598 urtwn_free_rx_list(sc); 599 URTWN_UNLOCK(sc); 600 601 if (ic->ic_softc == sc) { 602 ieee80211_draintask(ic, &sc->cmdq_task); 603 ieee80211_ifdetach(ic); 604 } 605 606 URTWN_NT_LOCK_DESTROY(sc); 607 URTWN_CMDQ_LOCK_DESTROY(sc); 608 mtx_destroy(&sc->sc_mtx); 609 610 return (0); 611} 612 613static void 614urtwn_drain_mbufq(struct urtwn_softc *sc) 615{ 616 struct mbuf *m; 617 struct ieee80211_node *ni; 618 URTWN_ASSERT_LOCKED(sc); 619 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 620 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 621 m->m_pkthdr.rcvif = NULL; 622 ieee80211_free_node(ni); 623 m_freem(m); 624 } 625} 626 627static usb_error_t 628urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 629 void *data) 630{ 631 usb_error_t err; 632 int ntries = 10; 633 634 URTWN_ASSERT_LOCKED(sc); 635 636 while (ntries--) { 637 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 638 req, data, 0, NULL, 250 /* ms */); 639 if (err == 0) 640 break; 641 642 DPRINTFN(1, "Control request failed, %s (retrying)\n", 643 usbd_errstr(err)); 644 usb_pause_mtx(&sc->sc_mtx, hz / 100); 645 } 646 return (err); 647} 648 649static struct ieee80211vap * 650urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 651 enum ieee80211_opmode opmode, int flags, 652 const uint8_t bssid[IEEE80211_ADDR_LEN], 653 const uint8_t mac[IEEE80211_ADDR_LEN]) 654{ 655 struct urtwn_softc *sc = ic->ic_softc; 656 struct urtwn_vap *uvp; 657 struct ieee80211vap *vap; 658 659 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 660 return (NULL); 661 662 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 663 vap = &uvp->vap; 664 /* enable s/w bmiss handling for sta mode */ 665 666 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 667 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 668 /* out of memory */ 669 free(uvp, M_80211_VAP); 670 return (NULL); 671 } 672 673 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 674 urtwn_init_beacon(sc, uvp); 675 676 /* override state transition machine */ 677 uvp->newstate = vap->iv_newstate; 678 vap->iv_newstate = urtwn_newstate; 679 vap->iv_update_beacon = urtwn_update_beacon; 680 vap->iv_key_alloc = urtwn_key_alloc; 681 vap->iv_key_set = urtwn_key_set; 682 vap->iv_key_delete = urtwn_key_delete; 683 if (opmode == IEEE80211_M_IBSS) { 684 uvp->recv_mgmt = vap->iv_recv_mgmt; 685 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 686 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 687 } 688 689 if (URTWN_CHIP_HAS_RATECTL(sc)) 690 ieee80211_ratectl_init(vap); 691 /* complete setup */ 692 ieee80211_vap_attach(vap, ieee80211_media_change, 693 ieee80211_media_status, mac); 694 ic->ic_opmode = opmode; 695 return (vap); 696} 697 698static void 699urtwn_vap_delete(struct ieee80211vap *vap) 700{ 701 struct ieee80211com *ic = vap->iv_ic; 702 struct urtwn_softc *sc = ic->ic_softc; 703 struct urtwn_vap *uvp = URTWN_VAP(vap); 704 705 if (uvp->bcn_mbuf != NULL) 706 m_freem(uvp->bcn_mbuf); 707 if (vap->iv_opmode == IEEE80211_M_IBSS) 708 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 709 if (URTWN_CHIP_HAS_RATECTL(sc)) 710 ieee80211_ratectl_deinit(vap); 711 ieee80211_vap_detach(vap); 712 free(uvp, M_80211_VAP); 713} 714 715static struct mbuf * 716urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 717{ 718 struct ieee80211com *ic = &sc->sc_ic; 719 struct ieee80211_frame *wh; 720 struct mbuf *m; 721 struct r92c_rx_stat *stat; 722 uint32_t rxdw0, rxdw3; 723 uint8_t rate, cipher; 724 int8_t rssi = 0; 725 int infosz; 726 727 /* 728 * don't pass packets to the ieee80211 framework if the driver isn't 729 * RUNNING. 730 */ 731 if (!(sc->sc_flags & URTWN_RUNNING)) 732 return (NULL); 733 734 stat = (struct r92c_rx_stat *)buf; 735 rxdw0 = le32toh(stat->rxdw0); 736 rxdw3 = le32toh(stat->rxdw3); 737 738 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 739 /* 740 * This should not happen since we setup our Rx filter 741 * to not receive these frames. 742 */ 743 counter_u64_add(ic->ic_ierrors, 1); 744 return (NULL); 745 } 746 if (pktlen < sizeof(struct ieee80211_frame_ack) || 747 pktlen > MCLBYTES) { 748 counter_u64_add(ic->ic_ierrors, 1); 749 return (NULL); 750 } 751 752 rate = MS(rxdw3, R92C_RXDW3_RATE); 753 cipher = MS(rxdw0, R92C_RXDW0_CIPHER); 754 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 755 756 /* Get RSSI from PHY status descriptor if present. */ 757 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 758 if (sc->chip & URTWN_CHIP_88E) 759 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 760 else 761 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 762 /* Update our average RSSI. */ 763 urtwn_update_avgrssi(sc, rate, rssi); 764 } 765 766 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 767 if (m == NULL) { 768 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 769 return (NULL); 770 } 771 772 /* Finalize mbuf. */ 773 memcpy(mtod(m, uint8_t *), (uint8_t *)&stat[1] + infosz, pktlen); 774 m->m_pkthdr.len = m->m_len = pktlen; 775 wh = mtod(m, struct ieee80211_frame *); 776 777 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 778 cipher != R92C_CAM_ALGO_NONE) { 779 m->m_flags |= M_WEP; 780 } 781 782 if (ieee80211_radiotap_active(ic)) { 783 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 784 785 tap->wr_flags = 0; 786 /* Map HW rate index to 802.11 rate. */ 787 if (!(rxdw3 & R92C_RXDW3_HT)) { 788 tap->wr_rate = ridx2rate[rate]; 789 } else if (rate >= 12) { /* MCS0~15. */ 790 /* Bit 7 set means HT MCS instead of rate. */ 791 tap->wr_rate = 0x80 | (rate - 12); 792 } 793 tap->wr_dbm_antsignal = rssi; 794 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 795 } 796 797 *rssi_p = rssi; 798 799 return (m); 800} 801 802static struct mbuf * 803urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 804 int8_t *nf) 805{ 806 struct urtwn_softc *sc = data->sc; 807 struct ieee80211com *ic = &sc->sc_ic; 808 struct r92c_rx_stat *stat; 809 uint8_t *buf; 810 int len; 811 812 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 813 814 if (len < sizeof(*stat)) { 815 counter_u64_add(ic->ic_ierrors, 1); 816 return (NULL); 817 } 818 819 buf = data->buf; 820 stat = (struct r92c_rx_stat *)buf; 821 822 if (sc->chip & URTWN_CHIP_88E) { 823 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 824 825 switch (report_sel) { 826 case R88E_RXDW3_RPT_RX: 827 return (urtwn_rxeof(sc, buf, len, rssi, nf)); 828 case R88E_RXDW3_RPT_TX1: 829 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 830 break; 831 default: 832 DPRINTFN(7, "case %d was not handled\n", report_sel); 833 break; 834 } 835 } else 836 return (urtwn_rxeof(sc, buf, len, rssi, nf)); 837 838 return (NULL); 839} 840 841static struct mbuf * 842urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len, int *rssi, 843 int8_t *nf) 844{ 845 struct r92c_rx_stat *stat; 846 struct mbuf *m, *m0 = NULL, *prevm = NULL; 847 uint32_t rxdw0; 848 int totlen, pktlen, infosz, npkts; 849 850 /* Get the number of encapsulated frames. */ 851 stat = (struct r92c_rx_stat *)buf; 852 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 853 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 854 855 /* Process all of them. */ 856 while (npkts-- > 0) { 857 if (len < sizeof(*stat)) 858 break; 859 stat = (struct r92c_rx_stat *)buf; 860 rxdw0 = le32toh(stat->rxdw0); 861 862 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 863 if (pktlen == 0) 864 break; 865 866 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 867 868 /* Make sure everything fits in xfer. */ 869 totlen = sizeof(*stat) + infosz + pktlen; 870 if (totlen > len) 871 break; 872 873 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 874 if (m0 == NULL) 875 m0 = m; 876 if (prevm == NULL) 877 prevm = m; 878 else { 879 prevm->m_next = m; 880 prevm = m; 881 } 882 883 /* Next chunk is 128-byte aligned. */ 884 totlen = (totlen + 127) & ~127; 885 buf += totlen; 886 len -= totlen; 887 } 888 889 return (m0); 890} 891 892static void 893urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 894{ 895 struct r88e_tx_rpt_ccx *rpt = arg; 896 struct ieee80211vap *vap; 897 struct ieee80211_node *ni; 898 uint8_t macid; 899 int ntries; 900 901 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 902 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 903 904 URTWN_NT_LOCK(sc); 905 ni = sc->node_list[macid]; 906 if (ni != NULL) { 907 vap = ni->ni_vap; 908 909 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 910 ieee80211_ratectl_tx_complete(vap, ni, 911 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 912 } else { 913 ieee80211_ratectl_tx_complete(vap, ni, 914 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 915 } 916 } else 917 DPRINTFN(8, "macid %d, ni is NULL\n", macid); 918 URTWN_NT_UNLOCK(sc); 919} 920 921static void 922urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 923{ 924 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 925 struct ieee80211com *ic = &sc->sc_ic; 926 struct ieee80211_frame_min *wh; 927 struct ieee80211_node *ni; 928 struct mbuf *m = NULL, *next; 929 struct urtwn_data *data; 930 int8_t nf; 931 int rssi = 1; 932 933 URTWN_ASSERT_LOCKED(sc); 934 935 switch (USB_GET_STATE(xfer)) { 936 case USB_ST_TRANSFERRED: 937 data = STAILQ_FIRST(&sc->sc_rx_active); 938 if (data == NULL) 939 goto tr_setup; 940 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 941 m = urtwn_report_intr(xfer, data, &rssi, &nf); 942 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 943 /* FALLTHROUGH */ 944 case USB_ST_SETUP: 945tr_setup: 946 data = STAILQ_FIRST(&sc->sc_rx_inactive); 947 if (data == NULL) { 948 KASSERT(m == NULL, ("mbuf isn't NULL")); 949 return; 950 } 951 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 952 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 953 usbd_xfer_set_frame_data(xfer, 0, data->buf, 954 usbd_xfer_max_len(xfer)); 955 usbd_transfer_submit(xfer); 956 957 /* 958 * To avoid LOR we should unlock our private mutex here to call 959 * ieee80211_input() because here is at the end of a USB 960 * callback and safe to unlock. 961 */ 962 URTWN_UNLOCK(sc); 963 while (m != NULL) { 964 next = m->m_next; 965 m->m_next = NULL; 966 wh = mtod(m, struct ieee80211_frame_min *); 967 if (m->m_len >= sizeof(*wh)) 968 ni = ieee80211_find_rxnode(ic, wh); 969 else 970 ni = NULL; 971 nf = URTWN_NOISE_FLOOR; 972 if (ni != NULL) { 973 (void)ieee80211_input(ni, m, rssi - nf, nf); 974 ieee80211_free_node(ni); 975 } else { 976 (void)ieee80211_input_all(ic, m, rssi - nf, 977 nf); 978 } 979 m = next; 980 } 981 URTWN_LOCK(sc); 982 break; 983 default: 984 /* needs it to the inactive queue due to a error. */ 985 data = STAILQ_FIRST(&sc->sc_rx_active); 986 if (data != NULL) { 987 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 988 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 989 } 990 if (error != USB_ERR_CANCELLED) { 991 usbd_xfer_set_stall(xfer); 992 counter_u64_add(ic->ic_ierrors, 1); 993 goto tr_setup; 994 } 995 break; 996 } 997} 998 999static void 1000urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 1001{ 1002 1003 URTWN_ASSERT_LOCKED(sc); 1004 1005 if (data->ni != NULL) /* not a beacon frame */ 1006 ieee80211_tx_complete(data->ni, data->m, status); 1007 1008 data->ni = NULL; 1009 data->m = NULL; 1010 1011 sc->sc_txtimer = 0; 1012 1013 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 1014} 1015 1016static int 1017urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1018 int ndata, int maxsz) 1019{ 1020 int i, error; 1021 1022 for (i = 0; i < ndata; i++) { 1023 struct urtwn_data *dp = &data[i]; 1024 dp->sc = sc; 1025 dp->m = NULL; 1026 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1027 if (dp->buf == NULL) { 1028 device_printf(sc->sc_dev, 1029 "could not allocate buffer\n"); 1030 error = ENOMEM; 1031 goto fail; 1032 } 1033 dp->ni = NULL; 1034 } 1035 1036 return (0); 1037fail: 1038 urtwn_free_list(sc, data, ndata); 1039 return (error); 1040} 1041 1042static int 1043urtwn_alloc_rx_list(struct urtwn_softc *sc) 1044{ 1045 int error, i; 1046 1047 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1048 URTWN_RXBUFSZ); 1049 if (error != 0) 1050 return (error); 1051 1052 STAILQ_INIT(&sc->sc_rx_active); 1053 STAILQ_INIT(&sc->sc_rx_inactive); 1054 1055 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1056 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1057 1058 return (0); 1059} 1060 1061static int 1062urtwn_alloc_tx_list(struct urtwn_softc *sc) 1063{ 1064 int error, i; 1065 1066 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1067 URTWN_TXBUFSZ); 1068 if (error != 0) 1069 return (error); 1070 1071 STAILQ_INIT(&sc->sc_tx_active); 1072 STAILQ_INIT(&sc->sc_tx_inactive); 1073 STAILQ_INIT(&sc->sc_tx_pending); 1074 1075 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1076 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1077 1078 return (0); 1079} 1080 1081static void 1082urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1083{ 1084 int i; 1085 1086 for (i = 0; i < ndata; i++) { 1087 struct urtwn_data *dp = &data[i]; 1088 1089 if (dp->buf != NULL) { 1090 free(dp->buf, M_USBDEV); 1091 dp->buf = NULL; 1092 } 1093 if (dp->ni != NULL) { 1094 ieee80211_free_node(dp->ni); 1095 dp->ni = NULL; 1096 } 1097 } 1098} 1099 1100static void 1101urtwn_free_rx_list(struct urtwn_softc *sc) 1102{ 1103 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1104} 1105 1106static void 1107urtwn_free_tx_list(struct urtwn_softc *sc) 1108{ 1109 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1110} 1111 1112static void 1113urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1114{ 1115 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1116 struct urtwn_data *data; 1117 1118 URTWN_ASSERT_LOCKED(sc); 1119 1120 switch (USB_GET_STATE(xfer)){ 1121 case USB_ST_TRANSFERRED: 1122 data = STAILQ_FIRST(&sc->sc_tx_active); 1123 if (data == NULL) 1124 goto tr_setup; 1125 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1126 urtwn_txeof(sc, data, 0); 1127 /* FALLTHROUGH */ 1128 case USB_ST_SETUP: 1129tr_setup: 1130 data = STAILQ_FIRST(&sc->sc_tx_pending); 1131 if (data == NULL) { 1132 DPRINTF("%s: empty pending queue\n", __func__); 1133 goto finish; 1134 } 1135 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1136 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1137 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1138 usbd_transfer_submit(xfer); 1139 break; 1140 default: 1141 data = STAILQ_FIRST(&sc->sc_tx_active); 1142 if (data == NULL) 1143 goto tr_setup; 1144 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1145 urtwn_txeof(sc, data, 1); 1146 if (error != USB_ERR_CANCELLED) { 1147 usbd_xfer_set_stall(xfer); 1148 goto tr_setup; 1149 } 1150 break; 1151 } 1152finish: 1153 /* Kick-start more transmit */ 1154 urtwn_start(sc); 1155} 1156 1157static struct urtwn_data * 1158_urtwn_getbuf(struct urtwn_softc *sc) 1159{ 1160 struct urtwn_data *bf; 1161 1162 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1163 if (bf != NULL) 1164 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1165 else 1166 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 1167 return (bf); 1168} 1169 1170static struct urtwn_data * 1171urtwn_getbuf(struct urtwn_softc *sc) 1172{ 1173 struct urtwn_data *bf; 1174 1175 URTWN_ASSERT_LOCKED(sc); 1176 1177 bf = _urtwn_getbuf(sc); 1178 if (bf == NULL) 1179 DPRINTF("%s: stop queue\n", __func__); 1180 return (bf); 1181} 1182 1183static usb_error_t 1184urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1185 int len) 1186{ 1187 usb_device_request_t req; 1188 1189 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1190 req.bRequest = R92C_REQ_REGS; 1191 USETW(req.wValue, addr); 1192 USETW(req.wIndex, 0); 1193 USETW(req.wLength, len); 1194 return (urtwn_do_request(sc, &req, buf)); 1195} 1196 1197static usb_error_t 1198urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1199{ 1200 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1201} 1202 1203static usb_error_t 1204urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1205{ 1206 val = htole16(val); 1207 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1208} 1209 1210static usb_error_t 1211urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1212{ 1213 val = htole32(val); 1214 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1215} 1216 1217static usb_error_t 1218urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1219 int len) 1220{ 1221 usb_device_request_t req; 1222 1223 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1224 req.bRequest = R92C_REQ_REGS; 1225 USETW(req.wValue, addr); 1226 USETW(req.wIndex, 0); 1227 USETW(req.wLength, len); 1228 return (urtwn_do_request(sc, &req, buf)); 1229} 1230 1231static uint8_t 1232urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1233{ 1234 uint8_t val; 1235 1236 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1237 return (0xff); 1238 return (val); 1239} 1240 1241static uint16_t 1242urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1243{ 1244 uint16_t val; 1245 1246 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1247 return (0xffff); 1248 return (le16toh(val)); 1249} 1250 1251static uint32_t 1252urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1253{ 1254 uint32_t val; 1255 1256 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1257 return (0xffffffff); 1258 return (le32toh(val)); 1259} 1260 1261static int 1262urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1263{ 1264 struct r92c_fw_cmd cmd; 1265 usb_error_t error; 1266 int ntries; 1267 1268 /* Wait for current FW box to be empty. */ 1269 for (ntries = 0; ntries < 100; ntries++) { 1270 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1271 break; 1272 urtwn_ms_delay(sc); 1273 } 1274 if (ntries == 100) { 1275 device_printf(sc->sc_dev, 1276 "could not send firmware command\n"); 1277 return (ETIMEDOUT); 1278 } 1279 memset(&cmd, 0, sizeof(cmd)); 1280 cmd.id = id; 1281 if (len > 3) 1282 cmd.id |= R92C_CMD_FLAG_EXT; 1283 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1284 memcpy(cmd.msg, buf, len); 1285 1286 /* Write the first word last since that will trigger the FW. */ 1287 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1288 (uint8_t *)&cmd + 4, 2); 1289 if (error != USB_ERR_NORMAL_COMPLETION) 1290 return (EIO); 1291 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1292 (uint8_t *)&cmd + 0, 4); 1293 if (error != USB_ERR_NORMAL_COMPLETION) 1294 return (EIO); 1295 1296 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1297 return (0); 1298} 1299 1300static void 1301urtwn_cmdq_cb(void *arg, int pending) 1302{ 1303 struct urtwn_softc *sc = arg; 1304 struct urtwn_cmdq *item; 1305 1306 /* 1307 * Device must be powered on (via urtwn_power_on()) 1308 * before any command may be sent. 1309 */ 1310 URTWN_LOCK(sc); 1311 if (!(sc->sc_flags & URTWN_RUNNING)) { 1312 URTWN_UNLOCK(sc); 1313 return; 1314 } 1315 1316 URTWN_CMDQ_LOCK(sc); 1317 while (sc->cmdq[sc->cmdq_first].func != NULL) { 1318 item = &sc->cmdq[sc->cmdq_first]; 1319 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE; 1320 URTWN_CMDQ_UNLOCK(sc); 1321 1322 item->func(sc, &item->data); 1323 1324 URTWN_CMDQ_LOCK(sc); 1325 memset(item, 0, sizeof (*item)); 1326 } 1327 URTWN_CMDQ_UNLOCK(sc); 1328 URTWN_UNLOCK(sc); 1329} 1330 1331static int 1332urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len, 1333 CMD_FUNC_PROTO) 1334{ 1335 struct ieee80211com *ic = &sc->sc_ic; 1336 1337 KASSERT(len <= sizeof(union sec_param), ("buffer overflow")); 1338 1339 URTWN_CMDQ_LOCK(sc); 1340 if (sc->cmdq[sc->cmdq_last].func != NULL) { 1341 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__); 1342 URTWN_CMDQ_UNLOCK(sc); 1343 1344 return (EAGAIN); 1345 } 1346 1347 if (ptr != NULL) 1348 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len); 1349 sc->cmdq[sc->cmdq_last].func = func; 1350 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE; 1351 URTWN_CMDQ_UNLOCK(sc); 1352 1353 ieee80211_runtask(ic, &sc->cmdq_task); 1354 1355 return (0); 1356} 1357 1358static __inline void 1359urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1360{ 1361 1362 sc->sc_rf_write(sc, chain, addr, val); 1363} 1364 1365static void 1366urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1367 uint32_t val) 1368{ 1369 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1370 SM(R92C_LSSI_PARAM_ADDR, addr) | 1371 SM(R92C_LSSI_PARAM_DATA, val)); 1372} 1373 1374static void 1375urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1376uint32_t val) 1377{ 1378 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1379 SM(R88E_LSSI_PARAM_ADDR, addr) | 1380 SM(R92C_LSSI_PARAM_DATA, val)); 1381} 1382 1383static uint32_t 1384urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1385{ 1386 uint32_t reg[R92C_MAX_CHAINS], val; 1387 1388 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1389 if (chain != 0) 1390 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1391 1392 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1393 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1394 urtwn_ms_delay(sc); 1395 1396 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1397 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1398 R92C_HSSI_PARAM2_READ_EDGE); 1399 urtwn_ms_delay(sc); 1400 1401 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1402 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1403 urtwn_ms_delay(sc); 1404 1405 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1406 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1407 else 1408 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1409 return (MS(val, R92C_LSSI_READBACK_DATA)); 1410} 1411 1412static int 1413urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1414{ 1415 usb_error_t error; 1416 int ntries; 1417 1418 error = urtwn_write_4(sc, R92C_LLT_INIT, 1419 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1420 SM(R92C_LLT_INIT_ADDR, addr) | 1421 SM(R92C_LLT_INIT_DATA, data)); 1422 if (error != USB_ERR_NORMAL_COMPLETION) 1423 return (EIO); 1424 /* Wait for write operation to complete. */ 1425 for (ntries = 0; ntries < 20; ntries++) { 1426 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1427 R92C_LLT_INIT_OP_NO_ACTIVE) 1428 return (0); 1429 urtwn_ms_delay(sc); 1430 } 1431 return (ETIMEDOUT); 1432} 1433 1434static int 1435urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1436{ 1437 uint32_t reg; 1438 usb_error_t error; 1439 int ntries; 1440 1441 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1442 return (EFAULT); 1443 1444 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1445 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1446 reg &= ~R92C_EFUSE_CTRL_VALID; 1447 1448 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1449 if (error != USB_ERR_NORMAL_COMPLETION) 1450 return (EIO); 1451 /* Wait for read operation to complete. */ 1452 for (ntries = 0; ntries < 100; ntries++) { 1453 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1454 if (reg & R92C_EFUSE_CTRL_VALID) 1455 break; 1456 urtwn_ms_delay(sc); 1457 } 1458 if (ntries == 100) { 1459 device_printf(sc->sc_dev, 1460 "could not read efuse byte at address 0x%x\n", 1461 sc->last_rom_addr); 1462 return (ETIMEDOUT); 1463 } 1464 1465 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1466 sc->last_rom_addr++; 1467 1468 return (0); 1469} 1470 1471static int 1472urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1473 uint8_t msk) 1474{ 1475 uint8_t reg; 1476 int i, error; 1477 1478 for (i = 0; i < 4; i++) { 1479 if (msk & (1 << i)) 1480 continue; 1481 error = urtwn_efuse_read_next(sc, ®); 1482 if (error != 0) 1483 return (error); 1484 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2, reg); 1485 rom[off * 8 + i * 2 + 0] = reg; 1486 1487 error = urtwn_efuse_read_next(sc, ®); 1488 if (error != 0) 1489 return (error); 1490 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2 + 1, reg); 1491 rom[off * 8 + i * 2 + 1] = reg; 1492 } 1493 1494 return (0); 1495} 1496 1497#ifdef URTWN_DEBUG 1498static void 1499urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1500{ 1501 int i; 1502 1503 /* Dump ROM contents. */ 1504 device_printf(sc->sc_dev, "%s:", __func__); 1505 for (i = 0; i < size; i++) { 1506 if (i % 32 == 0) 1507 printf("\n%03X: ", i); 1508 else if (i % 4 == 0) 1509 printf(" "); 1510 1511 printf("%02X", rom[i]); 1512 } 1513 printf("\n"); 1514} 1515#endif 1516 1517static int 1518urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1519{ 1520#define URTWN_CHK(res) do { \ 1521 if ((error = res) != 0) \ 1522 goto end; \ 1523} while(0) 1524 uint8_t msk, off, reg; 1525 int error; 1526 1527 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1528 1529 /* Read full ROM image. */ 1530 sc->last_rom_addr = 0; 1531 memset(rom, 0xff, size); 1532 1533 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1534 while (reg != 0xff) { 1535 /* check for extended header */ 1536 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1537 off = reg >> 5; 1538 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1539 1540 if ((reg & 0x0f) != 0x0f) 1541 off = ((reg & 0xf0) >> 1) | off; 1542 else 1543 continue; 1544 } else 1545 off = reg >> 4; 1546 msk = reg & 0xf; 1547 1548 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1549 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1550 } 1551 1552end: 1553 1554#ifdef URTWN_DEBUG 1555 if (urtwn_debug >= 2) 1556 urtwn_dump_rom_contents(sc, rom, size); 1557#endif 1558 1559 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1560 1561 if (error != 0) { 1562 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1563 __func__); 1564 } 1565 1566 return (error); 1567#undef URTWN_CHK 1568} 1569 1570static int 1571urtwn_efuse_switch_power(struct urtwn_softc *sc) 1572{ 1573 usb_error_t error; 1574 uint32_t reg; 1575 1576 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1577 if (error != USB_ERR_NORMAL_COMPLETION) 1578 return (EIO); 1579 1580 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1581 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1582 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1583 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1584 if (error != USB_ERR_NORMAL_COMPLETION) 1585 return (EIO); 1586 } 1587 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1588 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1589 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1590 reg | R92C_SYS_FUNC_EN_ELDR); 1591 if (error != USB_ERR_NORMAL_COMPLETION) 1592 return (EIO); 1593 } 1594 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1595 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1596 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1597 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1598 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1599 if (error != USB_ERR_NORMAL_COMPLETION) 1600 return (EIO); 1601 } 1602 1603 return (0); 1604} 1605 1606static int 1607urtwn_read_chipid(struct urtwn_softc *sc) 1608{ 1609 uint32_t reg; 1610 1611 if (sc->chip & URTWN_CHIP_88E) 1612 return (0); 1613 1614 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1615 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1616 return (EIO); 1617 1618 if (reg & R92C_SYS_CFG_TYPE_92C) { 1619 sc->chip |= URTWN_CHIP_92C; 1620 /* Check if it is a castrated 8192C. */ 1621 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1622 R92C_HPON_FSM_CHIP_BONDING_ID) == 1623 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1624 sc->chip |= URTWN_CHIP_92C_1T2R; 1625 } 1626 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1627 sc->chip |= URTWN_CHIP_UMC; 1628 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1629 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1630 } 1631 return (0); 1632} 1633 1634static int 1635urtwn_read_rom(struct urtwn_softc *sc) 1636{ 1637 struct r92c_rom *rom = &sc->rom.r92c_rom; 1638 int error; 1639 1640 /* Read full ROM image. */ 1641 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1642 if (error != 0) 1643 return (error); 1644 1645 /* XXX Weird but this is what the vendor driver does. */ 1646 sc->last_rom_addr = 0x1fa; 1647 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1648 if (error != 0) 1649 return (error); 1650 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1651 1652 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1653 1654 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1655 DPRINTF("regulatory type=%d\n", sc->regulatory); 1656 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1657 1658 sc->sc_rf_write = urtwn_r92c_rf_write; 1659 sc->sc_power_on = urtwn_r92c_power_on; 1660 1661 return (0); 1662} 1663 1664static int 1665urtwn_r88e_read_rom(struct urtwn_softc *sc) 1666{ 1667 uint8_t *rom = sc->rom.r88e_rom; 1668 uint16_t addr; 1669 int error, i; 1670 1671 error = urtwn_efuse_read(sc, rom, sizeof(sc->rom.r88e_rom)); 1672 if (error != 0) 1673 return (error); 1674 1675 addr = 0x10; 1676 for (i = 0; i < 6; i++) 1677 sc->cck_tx_pwr[i] = rom[addr++]; 1678 for (i = 0; i < 5; i++) 1679 sc->ht40_tx_pwr[i] = rom[addr++]; 1680 sc->bw20_tx_pwr_diff = (rom[addr] & 0xf0) >> 4; 1681 if (sc->bw20_tx_pwr_diff & 0x08) 1682 sc->bw20_tx_pwr_diff |= 0xf0; 1683 sc->ofdm_tx_pwr_diff = (rom[addr] & 0xf); 1684 if (sc->ofdm_tx_pwr_diff & 0x08) 1685 sc->ofdm_tx_pwr_diff |= 0xf0; 1686 sc->regulatory = MS(rom[0xc1], R92C_ROM_RF1_REGULATORY); 1687 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &rom[0xd7]); 1688 1689 sc->sc_rf_write = urtwn_r88e_rf_write; 1690 sc->sc_power_on = urtwn_r88e_power_on; 1691 1692 return (0); 1693} 1694 1695/* 1696 * Initialize rate adaptation in firmware. 1697 */ 1698static int 1699urtwn_ra_init(struct urtwn_softc *sc) 1700{ 1701 struct ieee80211com *ic = &sc->sc_ic; 1702 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1703 struct ieee80211_node *ni; 1704 struct ieee80211_rateset *rs; 1705 struct r92c_fw_cmd_macid_cfg cmd; 1706 uint32_t rates, basicrates; 1707 uint8_t mode; 1708 int maxrate, maxbasicrate, error, i, j; 1709 1710 ni = ieee80211_ref_node(vap->iv_bss); 1711 rs = &ni->ni_rates; 1712 1713 /* Get normal and basic rates mask. */ 1714 rates = basicrates = 0; 1715 maxrate = maxbasicrate = 0; 1716 for (i = 0; i < rs->rs_nrates; i++) { 1717 /* Convert 802.11 rate to HW rate index. */ 1718 for (j = 0; j < nitems(ridx2rate); j++) 1719 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1720 ridx2rate[j]) 1721 break; 1722 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1723 continue; 1724 rates |= 1 << j; 1725 if (j > maxrate) 1726 maxrate = j; 1727 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1728 basicrates |= 1 << j; 1729 if (j > maxbasicrate) 1730 maxbasicrate = j; 1731 } 1732 } 1733 if (ic->ic_curmode == IEEE80211_MODE_11B) 1734 mode = R92C_RAID_11B; 1735 else 1736 mode = R92C_RAID_11BG; 1737 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1738 mode, rates, basicrates); 1739 1740 /* Set rates mask for group addressed frames. */ 1741 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1742 cmd.mask = htole32(mode << 28 | basicrates); 1743 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1744 if (error != 0) { 1745 ieee80211_free_node(ni); 1746 device_printf(sc->sc_dev, 1747 "could not add broadcast station\n"); 1748 return (error); 1749 } 1750 /* Set initial MRR rate. */ 1751 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1752 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1753 maxbasicrate); 1754 1755 /* Set rates mask for unicast frames. */ 1756 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1757 cmd.mask = htole32(mode << 28 | rates); 1758 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1759 if (error != 0) { 1760 ieee80211_free_node(ni); 1761 device_printf(sc->sc_dev, "could not add BSS station\n"); 1762 return (error); 1763 } 1764 /* Set initial MRR rate. */ 1765 DPRINTF("maxrate=%d\n", maxrate); 1766 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1767 maxrate); 1768 1769 /* Indicate highest supported rate. */ 1770 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1771 ieee80211_free_node(ni); 1772 1773 return (0); 1774} 1775 1776static void 1777urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1778{ 1779 struct r92c_tx_desc *txd = &uvp->bcn_desc; 1780 1781 txd->txdw0 = htole32( 1782 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 1783 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1784 txd->txdw1 = htole32( 1785 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 1786 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1787 1788 if (sc->chip & URTWN_CHIP_88E) { 1789 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 1790 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 1791 } else { 1792 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 1793 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 1794 } 1795 1796 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 1797 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 1798} 1799 1800static int 1801urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 1802{ 1803 struct ieee80211vap *vap = ni->ni_vap; 1804 struct urtwn_vap *uvp = URTWN_VAP(vap); 1805 struct mbuf *m; 1806 int error; 1807 1808 URTWN_ASSERT_LOCKED(sc); 1809 1810 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 1811 return (EINVAL); 1812 1813 m = ieee80211_beacon_alloc(ni); 1814 if (m == NULL) { 1815 device_printf(sc->sc_dev, 1816 "%s: could not allocate beacon frame\n", __func__); 1817 return (ENOMEM); 1818 } 1819 1820 if (uvp->bcn_mbuf != NULL) 1821 m_freem(uvp->bcn_mbuf); 1822 1823 uvp->bcn_mbuf = m; 1824 1825 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1826 return (error); 1827 1828 /* XXX bcnq stuck workaround */ 1829 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1830 return (error); 1831 1832 return (0); 1833} 1834 1835static void 1836urtwn_update_beacon(struct ieee80211vap *vap, int item) 1837{ 1838 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1839 struct urtwn_vap *uvp = URTWN_VAP(vap); 1840 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 1841 struct ieee80211_node *ni = vap->iv_bss; 1842 int mcast = 0; 1843 1844 URTWN_LOCK(sc); 1845 if (uvp->bcn_mbuf == NULL) { 1846 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 1847 if (uvp->bcn_mbuf == NULL) { 1848 device_printf(sc->sc_dev, 1849 "%s: could not allocate beacon frame\n", __func__); 1850 URTWN_UNLOCK(sc); 1851 return; 1852 } 1853 } 1854 URTWN_UNLOCK(sc); 1855 1856 if (item == IEEE80211_BEACON_TIM) 1857 mcast = 1; /* XXX */ 1858 1859 setbit(bo->bo_flags, item); 1860 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 1861 1862 URTWN_LOCK(sc); 1863 urtwn_tx_beacon(sc, uvp); 1864 URTWN_UNLOCK(sc); 1865} 1866 1867/* 1868 * Push a beacon frame into the chip. Beacon will 1869 * be repeated by the chip every R92C_BCN_INTERVAL. 1870 */ 1871static int 1872urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1873{ 1874 struct r92c_tx_desc *desc = &uvp->bcn_desc; 1875 struct urtwn_data *bf; 1876 1877 URTWN_ASSERT_LOCKED(sc); 1878 1879 bf = urtwn_getbuf(sc); 1880 if (bf == NULL) 1881 return (ENOMEM); 1882 1883 memcpy(bf->buf, desc, sizeof(*desc)); 1884 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 1885 1886 sc->sc_txtimer = 5; 1887 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1888 1889 return (0); 1890} 1891 1892static int 1893urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 1894 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1895{ 1896 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1897 uint8_t i; 1898 1899 if (!(&vap->iv_nw_keys[0] <= k && 1900 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 1901 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 1902 URTWN_LOCK(sc); 1903 /* 1904 * First 4 slots for group keys, 1905 * what is left - for pairwise. 1906 * XXX incompatible with IBSS RSN. 1907 */ 1908 for (i = IEEE80211_WEP_NKID; 1909 i < R92C_CAM_ENTRY_COUNT; i++) { 1910 if ((sc->keys_bmap & (1 << i)) == 0) { 1911 sc->keys_bmap |= 1 << i; 1912 *keyix = i; 1913 break; 1914 } 1915 } 1916 URTWN_UNLOCK(sc); 1917 if (i == R92C_CAM_ENTRY_COUNT) { 1918 device_printf(sc->sc_dev, 1919 "%s: no free space in the key table\n", 1920 __func__); 1921 return 0; 1922 } 1923 } else 1924 *keyix = 0; 1925 } else { 1926 *keyix = k - vap->iv_nw_keys; 1927 } 1928 *rxkeyix = *keyix; 1929 return 1; 1930} 1931 1932static void 1933urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data) 1934{ 1935 struct ieee80211_key *k = &data->key; 1936 uint8_t algo, keyid; 1937 int i, error; 1938 1939 if (k->wk_keyix < IEEE80211_WEP_NKID) 1940 keyid = k->wk_keyix; 1941 else 1942 keyid = 0; 1943 1944 /* Map net80211 cipher to HW crypto algorithm. */ 1945 switch (k->wk_cipher->ic_cipher) { 1946 case IEEE80211_CIPHER_WEP: 1947 if (k->wk_keylen < 8) 1948 algo = R92C_CAM_ALGO_WEP40; 1949 else 1950 algo = R92C_CAM_ALGO_WEP104; 1951 break; 1952 case IEEE80211_CIPHER_TKIP: 1953 algo = R92C_CAM_ALGO_TKIP; 1954 break; 1955 case IEEE80211_CIPHER_AES_CCM: 1956 algo = R92C_CAM_ALGO_AES; 1957 break; 1958 default: 1959 device_printf(sc->sc_dev, "%s: undefined cipher %d\n", 1960 __func__, k->wk_cipher->ic_cipher); 1961 return; 1962 } 1963 1964 DPRINTFN(9, "keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, " 1965 "macaddr %s\n", k->wk_keyix, keyid, k->wk_cipher->ic_cipher, algo, 1966 k->wk_flags, k->wk_keylen, ether_sprintf(k->wk_macaddr)); 1967 1968 /* Write key. */ 1969 for (i = 0; i < 4; i++) { 1970 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 1971 LE_READ_4(&k->wk_key[i * 4])); 1972 if (error != 0) 1973 goto fail; 1974 } 1975 1976 /* Write CTL0 last since that will validate the CAM entry. */ 1977 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 1978 LE_READ_4(&k->wk_macaddr[2])); 1979 if (error != 0) 1980 goto fail; 1981 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 1982 SM(R92C_CAM_ALGO, algo) | 1983 SM(R92C_CAM_KEYID, keyid) | 1984 SM(R92C_CAM_MACLO, LE_READ_2(&k->wk_macaddr[0])) | 1985 R92C_CAM_VALID); 1986 if (error != 0) 1987 goto fail; 1988 1989 return; 1990 1991fail: 1992 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error); 1993} 1994 1995static void 1996urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data) 1997{ 1998 struct ieee80211_key *k = &data->key; 1999 int i; 2000 2001 DPRINTFN(9, "keyix %d, flags %04X, macaddr %s\n", 2002 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr)); 2003 2004 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0); 2005 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0); 2006 2007 /* Clear key. */ 2008 for (i = 0; i < 4; i++) 2009 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0); 2010 sc->keys_bmap &= ~(1 << k->wk_keyix); 2011} 2012 2013static int 2014urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 2015{ 2016 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2017 2018 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2019 /* Not for us. */ 2020 return (1); 2021 } 2022 2023 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb)); 2024} 2025 2026static int 2027urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2028{ 2029 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2030 2031 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2032 /* Not for us. */ 2033 return (1); 2034 } 2035 2036 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb)); 2037} 2038 2039static void 2040urtwn_tsf_task_adhoc(void *arg, int pending) 2041{ 2042 struct ieee80211vap *vap = arg; 2043 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2044 struct ieee80211_node *ni; 2045 uint32_t reg; 2046 2047 URTWN_LOCK(sc); 2048 ni = ieee80211_ref_node(vap->iv_bss); 2049 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 2050 2051 /* Accept beacons with the same BSSID. */ 2052 urtwn_set_rx_bssid_all(sc, 0); 2053 2054 /* Enable synchronization. */ 2055 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 2056 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2057 2058 /* Synchronize. */ 2059 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 2060 2061 /* Disable synchronization. */ 2062 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 2063 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2064 2065 /* Remove beacon filter. */ 2066 urtwn_set_rx_bssid_all(sc, 1); 2067 2068 /* Enable beaconing. */ 2069 urtwn_write_1(sc, R92C_MBID_NUM, 2070 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2071 reg |= R92C_BCN_CTRL_EN_BCN; 2072 2073 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2074 ieee80211_free_node(ni); 2075 URTWN_UNLOCK(sc); 2076} 2077 2078static void 2079urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 2080{ 2081 struct ieee80211com *ic = &sc->sc_ic; 2082 struct urtwn_vap *uvp = URTWN_VAP(vap); 2083 2084 /* Reset TSF. */ 2085 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2086 2087 switch (vap->iv_opmode) { 2088 case IEEE80211_M_STA: 2089 /* Enable TSF synchronization. */ 2090 urtwn_write_1(sc, R92C_BCN_CTRL, 2091 urtwn_read_1(sc, R92C_BCN_CTRL) & 2092 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 2093 break; 2094 case IEEE80211_M_IBSS: 2095 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 2096 break; 2097 case IEEE80211_M_HOSTAP: 2098 /* Enable beaconing. */ 2099 urtwn_write_1(sc, R92C_MBID_NUM, 2100 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2101 urtwn_write_1(sc, R92C_BCN_CTRL, 2102 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 2103 break; 2104 default: 2105 device_printf(sc->sc_dev, "undefined opmode %d\n", 2106 vap->iv_opmode); 2107 return; 2108 } 2109} 2110 2111static void 2112urtwn_set_led(struct urtwn_softc *sc, int led, int on) 2113{ 2114 uint8_t reg; 2115 2116 if (led == URTWN_LED_LINK) { 2117 if (sc->chip & URTWN_CHIP_88E) { 2118 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 2119 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 2120 if (!on) { 2121 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 2122 urtwn_write_1(sc, R92C_LEDCFG2, 2123 reg | R92C_LEDCFG0_DIS); 2124 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 2125 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 2126 0xfe); 2127 } 2128 } else { 2129 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 2130 if (!on) 2131 reg |= R92C_LEDCFG0_DIS; 2132 urtwn_write_1(sc, R92C_LEDCFG0, reg); 2133 } 2134 sc->ledlink = on; /* Save LED state. */ 2135 } 2136} 2137 2138static void 2139urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 2140{ 2141 uint8_t reg; 2142 2143 reg = urtwn_read_1(sc, R92C_MSR); 2144 reg = (reg & ~R92C_MSR_MASK) | mode; 2145 urtwn_write_1(sc, R92C_MSR, reg); 2146} 2147 2148static void 2149urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 2150 const struct ieee80211_rx_stats *rxs, 2151 int rssi, int nf) 2152{ 2153 struct ieee80211vap *vap = ni->ni_vap; 2154 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2155 struct urtwn_vap *uvp = URTWN_VAP(vap); 2156 uint64_t ni_tstamp, curr_tstamp; 2157 2158 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 2159 2160 if (vap->iv_state == IEEE80211_S_RUN && 2161 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 2162 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 2163 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 2164#ifdef D3831 2165 URTWN_LOCK(sc); 2166 urtwn_get_tsf(sc, &curr_tstamp); 2167 URTWN_UNLOCK(sc); 2168 curr_tstamp = le64toh(curr_tstamp); 2169 2170 if (ni_tstamp >= curr_tstamp) 2171 (void) ieee80211_ibss_merge(ni); 2172#else 2173 (void) sc; 2174 (void) curr_tstamp; 2175#endif 2176 } 2177} 2178 2179static int 2180urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2181{ 2182 struct urtwn_vap *uvp = URTWN_VAP(vap); 2183 struct ieee80211com *ic = vap->iv_ic; 2184 struct urtwn_softc *sc = ic->ic_softc; 2185 struct ieee80211_node *ni; 2186 enum ieee80211_state ostate; 2187 uint32_t reg; 2188 uint8_t mode; 2189 int error = 0; 2190 2191 ostate = vap->iv_state; 2192 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 2193 ieee80211_state_name[nstate]); 2194 2195 IEEE80211_UNLOCK(ic); 2196 URTWN_LOCK(sc); 2197 callout_stop(&sc->sc_watchdog_ch); 2198 2199 if (ostate == IEEE80211_S_RUN) { 2200 /* Turn link LED off. */ 2201 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2202 2203 /* Set media status to 'No Link'. */ 2204 urtwn_set_mode(sc, R92C_MSR_NOLINK); 2205 2206 /* Stop Rx of data frames. */ 2207 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2208 2209 /* Disable TSF synchronization. */ 2210 urtwn_write_1(sc, R92C_BCN_CTRL, 2211 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 2212 R92C_BCN_CTRL_DIS_TSF_UDT0); 2213 2214 /* Disable beaconing. */ 2215 urtwn_write_1(sc, R92C_MBID_NUM, 2216 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 2217 2218 /* Reset TSF. */ 2219 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2220 2221 /* Reset EDCA parameters. */ 2222 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2223 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2224 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2225 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2226 } 2227 2228 switch (nstate) { 2229 case IEEE80211_S_INIT: 2230 /* Turn link LED off. */ 2231 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2232 break; 2233 case IEEE80211_S_SCAN: 2234 /* Pause AC Tx queues. */ 2235 urtwn_write_1(sc, R92C_TXPAUSE, 2236 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2237 break; 2238 case IEEE80211_S_AUTH: 2239 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2240 break; 2241 case IEEE80211_S_RUN: 2242 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2243 /* Turn link LED on. */ 2244 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2245 break; 2246 } 2247 2248 ni = ieee80211_ref_node(vap->iv_bss); 2249 2250 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2251 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2252 device_printf(sc->sc_dev, 2253 "%s: could not move to RUN state\n", __func__); 2254 error = EINVAL; 2255 goto end_run; 2256 } 2257 2258 switch (vap->iv_opmode) { 2259 case IEEE80211_M_STA: 2260 mode = R92C_MSR_INFRA; 2261 break; 2262 case IEEE80211_M_IBSS: 2263 mode = R92C_MSR_ADHOC; 2264 break; 2265 case IEEE80211_M_HOSTAP: 2266 mode = R92C_MSR_AP; 2267 break; 2268 default: 2269 device_printf(sc->sc_dev, "undefined opmode %d\n", 2270 vap->iv_opmode); 2271 error = EINVAL; 2272 goto end_run; 2273 } 2274 2275 /* Set media status to 'Associated'. */ 2276 urtwn_set_mode(sc, mode); 2277 2278 /* Set BSSID. */ 2279 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2280 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2281 2282 if (ic->ic_curmode == IEEE80211_MODE_11B) 2283 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2284 else /* 802.11b/g */ 2285 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2286 2287 /* Enable Rx of data frames. */ 2288 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2289 2290 /* Flush all AC queues. */ 2291 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2292 2293 /* Set beacon interval. */ 2294 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2295 2296 /* Allow Rx from our BSSID only. */ 2297 if (ic->ic_promisc == 0) { 2298 reg = urtwn_read_4(sc, R92C_RCR); 2299 2300 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 2301 reg |= R92C_RCR_CBSSID_DATA; 2302 if (vap->iv_opmode != IEEE80211_M_IBSS) 2303 reg |= R92C_RCR_CBSSID_BCN; 2304 2305 urtwn_write_4(sc, R92C_RCR, reg); 2306 } 2307 2308 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2309 vap->iv_opmode == IEEE80211_M_IBSS) { 2310 error = urtwn_setup_beacon(sc, ni); 2311 if (error != 0) { 2312 device_printf(sc->sc_dev, 2313 "unable to push beacon into the chip, " 2314 "error %d\n", error); 2315 goto end_run; 2316 } 2317 } 2318 2319 /* Enable TSF synchronization. */ 2320 urtwn_tsf_sync_enable(sc, vap); 2321 2322 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2323 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2324 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2325 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2326 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2327 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2328 2329 /* Intialize rate adaptation. */ 2330 if (!(sc->chip & URTWN_CHIP_88E)) 2331 urtwn_ra_init(sc); 2332 /* Turn link LED on. */ 2333 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2334 2335 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2336 /* Reset temperature calibration state machine. */ 2337 sc->thcal_state = 0; 2338 sc->thcal_lctemp = 0; 2339 2340end_run: 2341 ieee80211_free_node(ni); 2342 break; 2343 default: 2344 break; 2345 } 2346 2347 URTWN_UNLOCK(sc); 2348 IEEE80211_LOCK(ic); 2349 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2350} 2351 2352static void 2353urtwn_watchdog(void *arg) 2354{ 2355 struct urtwn_softc *sc = arg; 2356 2357 if (sc->sc_txtimer > 0) { 2358 if (--sc->sc_txtimer == 0) { 2359 device_printf(sc->sc_dev, "device timeout\n"); 2360 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2361 return; 2362 } 2363 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2364 } 2365} 2366 2367static void 2368urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2369{ 2370 int pwdb; 2371 2372 /* Convert antenna signal to percentage. */ 2373 if (rssi <= -100 || rssi >= 20) 2374 pwdb = 0; 2375 else if (rssi >= 0) 2376 pwdb = 100; 2377 else 2378 pwdb = 100 + rssi; 2379 if (!(sc->chip & URTWN_CHIP_88E)) { 2380 if (rate <= URTWN_RIDX_CCK11) { 2381 /* CCK gain is smaller than OFDM/MCS gain. */ 2382 pwdb += 6; 2383 if (pwdb > 100) 2384 pwdb = 100; 2385 if (pwdb <= 14) 2386 pwdb -= 4; 2387 else if (pwdb <= 26) 2388 pwdb -= 8; 2389 else if (pwdb <= 34) 2390 pwdb -= 6; 2391 else if (pwdb <= 42) 2392 pwdb -= 2; 2393 } 2394 } 2395 if (sc->avg_pwdb == -1) /* Init. */ 2396 sc->avg_pwdb = pwdb; 2397 else if (sc->avg_pwdb < pwdb) 2398 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2399 else 2400 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2401 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 2402} 2403 2404static int8_t 2405urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2406{ 2407 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2408 struct r92c_rx_phystat *phy; 2409 struct r92c_rx_cck *cck; 2410 uint8_t rpt; 2411 int8_t rssi; 2412 2413 if (rate <= URTWN_RIDX_CCK11) { 2414 cck = (struct r92c_rx_cck *)physt; 2415 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2416 rpt = (cck->agc_rpt >> 5) & 0x3; 2417 rssi = (cck->agc_rpt & 0x1f) << 1; 2418 } else { 2419 rpt = (cck->agc_rpt >> 6) & 0x3; 2420 rssi = cck->agc_rpt & 0x3e; 2421 } 2422 rssi = cckoff[rpt] - rssi; 2423 } else { /* OFDM/HT. */ 2424 phy = (struct r92c_rx_phystat *)physt; 2425 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2426 } 2427 return (rssi); 2428} 2429 2430static int8_t 2431urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2432{ 2433 struct r92c_rx_phystat *phy; 2434 struct r88e_rx_cck *cck; 2435 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2436 int8_t rssi; 2437 2438 rssi = 0; 2439 if (rate <= URTWN_RIDX_CCK11) { 2440 cck = (struct r88e_rx_cck *)physt; 2441 cck_agc_rpt = cck->agc_rpt; 2442 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2443 vga_idx = cck_agc_rpt & 0x1f; 2444 switch (lna_idx) { 2445 case 7: 2446 if (vga_idx <= 27) 2447 rssi = -100 + 2* (27 - vga_idx); 2448 else 2449 rssi = -100; 2450 break; 2451 case 6: 2452 rssi = -48 + 2 * (2 - vga_idx); 2453 break; 2454 case 5: 2455 rssi = -42 + 2 * (7 - vga_idx); 2456 break; 2457 case 4: 2458 rssi = -36 + 2 * (7 - vga_idx); 2459 break; 2460 case 3: 2461 rssi = -24 + 2 * (7 - vga_idx); 2462 break; 2463 case 2: 2464 rssi = -12 + 2 * (5 - vga_idx); 2465 break; 2466 case 1: 2467 rssi = 8 - (2 * vga_idx); 2468 break; 2469 case 0: 2470 rssi = 14 - (2 * vga_idx); 2471 break; 2472 } 2473 rssi += 6; 2474 } else { /* OFDM/HT. */ 2475 phy = (struct r92c_rx_phystat *)physt; 2476 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2477 } 2478 return (rssi); 2479} 2480 2481static __inline uint8_t 2482rate2ridx(uint8_t rate) 2483{ 2484 switch (rate) { 2485 case 12: return 4; 2486 case 18: return 5; 2487 case 24: return 6; 2488 case 36: return 7; 2489 case 48: return 8; 2490 case 72: return 9; 2491 case 96: return 10; 2492 case 108: return 11; 2493 case 2: return 0; 2494 case 4: return 1; 2495 case 11: return 2; 2496 case 22: return 3; 2497 default: return 0; 2498 } 2499} 2500 2501static int 2502urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2503 struct mbuf *m, struct urtwn_data *data) 2504{ 2505 const struct ieee80211_txparam *tp; 2506 struct ieee80211com *ic = &sc->sc_ic; 2507 struct ieee80211vap *vap = ni->ni_vap; 2508 struct ieee80211_key *k = NULL; 2509 struct ieee80211_channel *chan; 2510 struct ieee80211_frame *wh; 2511 struct r92c_tx_desc *txd; 2512 uint8_t macid, raid, rate, ridx, subtype, type, tid, qsel; 2513 int hasqos, ismcast; 2514 2515 URTWN_ASSERT_LOCKED(sc); 2516 2517 /* 2518 * Software crypto. 2519 */ 2520 wh = mtod(m, struct ieee80211_frame *); 2521 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2522 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2523 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2524 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2525 2526 /* Select TX ring for this frame. */ 2527 if (hasqos) { 2528 tid = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2529 tid &= IEEE80211_QOS_TID; 2530 } else 2531 tid = 0; 2532 2533 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2534 ni->ni_chan : ic->ic_curchan; 2535 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2536 2537 /* Choose a TX rate index. */ 2538 if (type == IEEE80211_FC0_TYPE_MGT) 2539 rate = tp->mgmtrate; 2540 else if (ismcast) 2541 rate = tp->mcastrate; 2542 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2543 rate = tp->ucastrate; 2544 else if (m->m_flags & M_EAPOL) 2545 rate = tp->mgmtrate; 2546 else { 2547 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2548 /* XXX pass pktlen */ 2549 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2550 rate = ni->ni_txrate; 2551 } else { 2552 if (ic->ic_curmode != IEEE80211_MODE_11B) 2553 rate = 108; 2554 else 2555 rate = 22; 2556 } 2557 } 2558 2559 ridx = rate2ridx(rate); 2560 if (ic->ic_curmode != IEEE80211_MODE_11B) 2561 raid = R92C_RAID_11BG; 2562 else 2563 raid = R92C_RAID_11B; 2564 2565 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2566 k = ieee80211_crypto_encap(ni, m); 2567 if (k == NULL) { 2568 device_printf(sc->sc_dev, 2569 "ieee80211_crypto_encap returns NULL.\n"); 2570 return (ENOBUFS); 2571 } 2572 2573 /* in case packet header moved, reset pointer */ 2574 wh = mtod(m, struct ieee80211_frame *); 2575 } 2576 2577 /* Fill Tx descriptor. */ 2578 txd = (struct r92c_tx_desc *)data->buf; 2579 memset(txd, 0, sizeof(*txd)); 2580 2581 txd->txdw0 |= htole32( 2582 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2583 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2584 if (ismcast) 2585 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2586 2587 if (!ismcast) { 2588 if (sc->chip & URTWN_CHIP_88E) { 2589 struct urtwn_node *un = URTWN_NODE(ni); 2590 macid = un->id; 2591 } else 2592 macid = URTWN_MACID_BSS; 2593 2594 if (type == IEEE80211_FC0_TYPE_DATA) { 2595 qsel = tid % URTWN_MAX_TID; 2596 2597 if (sc->chip & URTWN_CHIP_88E) { 2598 txd->txdw2 |= htole32( 2599 R88E_TXDW2_AGGBK | 2600 R88E_TXDW2_CCX_RPT); 2601 } else 2602 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2603 2604 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2605 switch (ic->ic_protmode) { 2606 case IEEE80211_PROT_CTSONLY: 2607 txd->txdw4 |= htole32( 2608 R92C_TXDW4_CTS2SELF | 2609 R92C_TXDW4_HWRTSEN); 2610 break; 2611 case IEEE80211_PROT_RTSCTS: 2612 txd->txdw4 |= htole32( 2613 R92C_TXDW4_RTSEN | 2614 R92C_TXDW4_HWRTSEN); 2615 break; 2616 default: 2617 break; 2618 } 2619 } 2620 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2621 URTWN_RIDX_OFDM24)); 2622 txd->txdw5 |= htole32(0x0001ff00); 2623 } else /* IEEE80211_FC0_TYPE_MGT */ 2624 qsel = R92C_TXDW1_QSEL_MGNT; 2625 } else { 2626 macid = URTWN_MACID_BC; 2627 qsel = R92C_TXDW1_QSEL_MGNT; 2628 } 2629 2630 txd->txdw1 |= htole32( 2631 SM(R92C_TXDW1_QSEL, qsel) | 2632 SM(R92C_TXDW1_RAID, raid)); 2633 2634 if (sc->chip & URTWN_CHIP_88E) 2635 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 2636 else 2637 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 2638 2639 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2640 /* Force this rate if needed. */ 2641 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 2642 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 2643 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2644 2645 if (!hasqos) { 2646 /* Use HW sequence numbering for non-QoS frames. */ 2647 if (sc->chip & URTWN_CHIP_88E) 2648 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2649 else 2650 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2651 } else { 2652 /* Set sequence number. */ 2653 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2654 } 2655 2656 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2657 uint8_t cipher; 2658 2659 switch (k->wk_cipher->ic_cipher) { 2660 case IEEE80211_CIPHER_WEP: 2661 case IEEE80211_CIPHER_TKIP: 2662 cipher = R92C_TXDW1_CIPHER_RC4; 2663 break; 2664 case IEEE80211_CIPHER_AES_CCM: 2665 cipher = R92C_TXDW1_CIPHER_AES; 2666 break; 2667 default: 2668 device_printf(sc->sc_dev, "%s: unknown cipher %d\n", 2669 __func__, k->wk_cipher->ic_cipher); 2670 return (EINVAL); 2671 } 2672 2673 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 2674 } 2675 2676 if (ieee80211_radiotap_active_vap(vap)) { 2677 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2678 2679 tap->wt_flags = 0; 2680 if (k != NULL) 2681 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2682 ieee80211_radiotap_tx(vap, m); 2683 } 2684 2685 data->ni = ni; 2686 2687 urtwn_tx_start(sc, m, type, data); 2688 2689 return (0); 2690} 2691 2692static void 2693urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 2694 struct urtwn_data *data) 2695{ 2696 struct usb_xfer *xfer; 2697 struct r92c_tx_desc *txd; 2698 uint16_t ac, sum; 2699 int i, xferlen; 2700 2701 URTWN_ASSERT_LOCKED(sc); 2702 2703 ac = M_WME_GETAC(m); 2704 2705 switch (type) { 2706 case IEEE80211_FC0_TYPE_CTL: 2707 case IEEE80211_FC0_TYPE_MGT: 2708 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 2709 break; 2710 default: 2711 xfer = sc->sc_xfer[wme2queue[ac].qid]; 2712 break; 2713 } 2714 2715 txd = (struct r92c_tx_desc *)data->buf; 2716 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 2717 2718 /* Compute Tx descriptor checksum. */ 2719 sum = 0; 2720 for (i = 0; i < sizeof(*txd) / 2; i++) 2721 sum ^= ((uint16_t *)txd)[i]; 2722 txd->txdsum = sum; /* NB: already little endian. */ 2723 2724 xferlen = sizeof(*txd) + m->m_pkthdr.len; 2725 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 2726 2727 data->buflen = xferlen; 2728 data->m = m; 2729 2730 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 2731 usbd_transfer_start(xfer); 2732} 2733 2734static int 2735urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 2736{ 2737 struct urtwn_softc *sc = ic->ic_softc; 2738 int error; 2739 2740 URTWN_LOCK(sc); 2741 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2742 URTWN_UNLOCK(sc); 2743 return (ENXIO); 2744 } 2745 error = mbufq_enqueue(&sc->sc_snd, m); 2746 if (error) { 2747 URTWN_UNLOCK(sc); 2748 return (error); 2749 } 2750 urtwn_start(sc); 2751 URTWN_UNLOCK(sc); 2752 2753 return (0); 2754} 2755 2756static void 2757urtwn_start(struct urtwn_softc *sc) 2758{ 2759 struct ieee80211_node *ni; 2760 struct mbuf *m; 2761 struct urtwn_data *bf; 2762 2763 URTWN_ASSERT_LOCKED(sc); 2764 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2765 bf = urtwn_getbuf(sc); 2766 if (bf == NULL) { 2767 mbufq_prepend(&sc->sc_snd, m); 2768 break; 2769 } 2770 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2771 m->m_pkthdr.rcvif = NULL; 2772 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 2773 if_inc_counter(ni->ni_vap->iv_ifp, 2774 IFCOUNTER_OERRORS, 1); 2775 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2776 m_freem(m); 2777 ieee80211_free_node(ni); 2778 break; 2779 } 2780 sc->sc_txtimer = 5; 2781 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2782 } 2783} 2784 2785static void 2786urtwn_parent(struct ieee80211com *ic) 2787{ 2788 struct urtwn_softc *sc = ic->ic_softc; 2789 2790 URTWN_LOCK(sc); 2791 if (sc->sc_flags & URTWN_DETACHED) { 2792 URTWN_UNLOCK(sc); 2793 return; 2794 } 2795 URTWN_UNLOCK(sc); 2796 2797 if (ic->ic_nrunning > 0) { 2798 if (urtwn_init(sc) != 0) { 2799 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2800 if (vap != NULL) 2801 ieee80211_stop(vap); 2802 } else 2803 ieee80211_start_all(ic); 2804 } else 2805 urtwn_stop(sc); 2806} 2807 2808static __inline int 2809urtwn_power_on(struct urtwn_softc *sc) 2810{ 2811 2812 return sc->sc_power_on(sc); 2813} 2814 2815static int 2816urtwn_r92c_power_on(struct urtwn_softc *sc) 2817{ 2818 uint32_t reg; 2819 usb_error_t error; 2820 int ntries; 2821 2822 /* Wait for autoload done bit. */ 2823 for (ntries = 0; ntries < 1000; ntries++) { 2824 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2825 break; 2826 urtwn_ms_delay(sc); 2827 } 2828 if (ntries == 1000) { 2829 device_printf(sc->sc_dev, 2830 "timeout waiting for chip autoload\n"); 2831 return (ETIMEDOUT); 2832 } 2833 2834 /* Unlock ISO/CLK/Power control register. */ 2835 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2836 if (error != USB_ERR_NORMAL_COMPLETION) 2837 return (EIO); 2838 /* Move SPS into PWM mode. */ 2839 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2840 if (error != USB_ERR_NORMAL_COMPLETION) 2841 return (EIO); 2842 urtwn_ms_delay(sc); 2843 2844 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2845 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2846 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2847 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2848 if (error != USB_ERR_NORMAL_COMPLETION) 2849 return (EIO); 2850 urtwn_ms_delay(sc); 2851 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2852 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2853 ~R92C_SYS_ISO_CTRL_MD2PP); 2854 if (error != USB_ERR_NORMAL_COMPLETION) 2855 return (EIO); 2856 } 2857 2858 /* Auto enable WLAN. */ 2859 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2860 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2861 if (error != USB_ERR_NORMAL_COMPLETION) 2862 return (EIO); 2863 for (ntries = 0; ntries < 1000; ntries++) { 2864 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2865 R92C_APS_FSMCO_APFM_ONMAC)) 2866 break; 2867 urtwn_ms_delay(sc); 2868 } 2869 if (ntries == 1000) { 2870 device_printf(sc->sc_dev, 2871 "timeout waiting for MAC auto ON\n"); 2872 return (ETIMEDOUT); 2873 } 2874 2875 /* Enable radio, GPIO and LED functions. */ 2876 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2877 R92C_APS_FSMCO_AFSM_HSUS | 2878 R92C_APS_FSMCO_PDN_EN | 2879 R92C_APS_FSMCO_PFM_ALDN); 2880 if (error != USB_ERR_NORMAL_COMPLETION) 2881 return (EIO); 2882 /* Release RF digital isolation. */ 2883 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2884 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2885 if (error != USB_ERR_NORMAL_COMPLETION) 2886 return (EIO); 2887 2888 /* Initialize MAC. */ 2889 error = urtwn_write_1(sc, R92C_APSD_CTRL, 2890 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2891 if (error != USB_ERR_NORMAL_COMPLETION) 2892 return (EIO); 2893 for (ntries = 0; ntries < 200; ntries++) { 2894 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2895 R92C_APSD_CTRL_OFF_STATUS)) 2896 break; 2897 urtwn_ms_delay(sc); 2898 } 2899 if (ntries == 200) { 2900 device_printf(sc->sc_dev, 2901 "timeout waiting for MAC initialization\n"); 2902 return (ETIMEDOUT); 2903 } 2904 2905 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2906 reg = urtwn_read_2(sc, R92C_CR); 2907 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2908 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2909 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2910 R92C_CR_ENSEC; 2911 error = urtwn_write_2(sc, R92C_CR, reg); 2912 if (error != USB_ERR_NORMAL_COMPLETION) 2913 return (EIO); 2914 2915 error = urtwn_write_1(sc, 0xfe10, 0x19); 2916 if (error != USB_ERR_NORMAL_COMPLETION) 2917 return (EIO); 2918 return (0); 2919} 2920 2921static int 2922urtwn_r88e_power_on(struct urtwn_softc *sc) 2923{ 2924 uint32_t reg; 2925 usb_error_t error; 2926 int ntries; 2927 2928 /* Wait for power ready bit. */ 2929 for (ntries = 0; ntries < 5000; ntries++) { 2930 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2931 break; 2932 urtwn_ms_delay(sc); 2933 } 2934 if (ntries == 5000) { 2935 device_printf(sc->sc_dev, 2936 "timeout waiting for chip power up\n"); 2937 return (ETIMEDOUT); 2938 } 2939 2940 /* Reset BB. */ 2941 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2942 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2943 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2944 if (error != USB_ERR_NORMAL_COMPLETION) 2945 return (EIO); 2946 2947 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2948 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2949 if (error != USB_ERR_NORMAL_COMPLETION) 2950 return (EIO); 2951 2952 /* Disable HWPDN. */ 2953 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2954 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2955 if (error != USB_ERR_NORMAL_COMPLETION) 2956 return (EIO); 2957 2958 /* Disable WL suspend. */ 2959 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2960 urtwn_read_2(sc, R92C_APS_FSMCO) & 2961 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2962 if (error != USB_ERR_NORMAL_COMPLETION) 2963 return (EIO); 2964 2965 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2966 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2967 if (error != USB_ERR_NORMAL_COMPLETION) 2968 return (EIO); 2969 for (ntries = 0; ntries < 5000; ntries++) { 2970 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2971 R92C_APS_FSMCO_APFM_ONMAC)) 2972 break; 2973 urtwn_ms_delay(sc); 2974 } 2975 if (ntries == 5000) 2976 return (ETIMEDOUT); 2977 2978 /* Enable LDO normal mode. */ 2979 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 2980 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2981 if (error != USB_ERR_NORMAL_COMPLETION) 2982 return (EIO); 2983 2984 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2985 error = urtwn_write_2(sc, R92C_CR, 0); 2986 if (error != USB_ERR_NORMAL_COMPLETION) 2987 return (EIO); 2988 reg = urtwn_read_2(sc, R92C_CR); 2989 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2990 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2991 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2992 error = urtwn_write_2(sc, R92C_CR, reg); 2993 if (error != USB_ERR_NORMAL_COMPLETION) 2994 return (EIO); 2995 2996 return (0); 2997} 2998 2999static int 3000urtwn_llt_init(struct urtwn_softc *sc) 3001{ 3002 int i, error, page_count, pktbuf_count; 3003 3004 page_count = (sc->chip & URTWN_CHIP_88E) ? 3005 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 3006 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 3007 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 3008 3009 /* Reserve pages [0; page_count]. */ 3010 for (i = 0; i < page_count; i++) { 3011 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3012 return (error); 3013 } 3014 /* NB: 0xff indicates end-of-list. */ 3015 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3016 return (error); 3017 /* 3018 * Use pages [page_count + 1; pktbuf_count - 1] 3019 * as ring buffer. 3020 */ 3021 for (++i; i < pktbuf_count - 1; i++) { 3022 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3023 return (error); 3024 } 3025 /* Make the last page point to the beginning of the ring buffer. */ 3026 error = urtwn_llt_write(sc, i, page_count + 1); 3027 return (error); 3028} 3029 3030static void 3031urtwn_fw_reset(struct urtwn_softc *sc) 3032{ 3033 uint16_t reg; 3034 int ntries; 3035 3036 /* Tell 8051 to reset itself. */ 3037 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3038 3039 /* Wait until 8051 resets by itself. */ 3040 for (ntries = 0; ntries < 100; ntries++) { 3041 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3042 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3043 return; 3044 urtwn_ms_delay(sc); 3045 } 3046 /* Force 8051 reset. */ 3047 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3048} 3049 3050static void 3051urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3052{ 3053 uint16_t reg; 3054 3055 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3056 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3057 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3058} 3059 3060static int 3061urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 3062{ 3063 uint32_t reg; 3064 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 3065 int off, mlen; 3066 3067 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3068 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3069 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3070 3071 off = R92C_FW_START_ADDR; 3072 while (len > 0) { 3073 if (len > 196) 3074 mlen = 196; 3075 else if (len > 4) 3076 mlen = 4; 3077 else 3078 mlen = 1; 3079 /* XXX fix this deconst */ 3080 error = urtwn_write_region_1(sc, off, 3081 __DECONST(uint8_t *, buf), mlen); 3082 if (error != USB_ERR_NORMAL_COMPLETION) 3083 break; 3084 off += mlen; 3085 buf += mlen; 3086 len -= mlen; 3087 } 3088 return (error); 3089} 3090 3091static int 3092urtwn_load_firmware(struct urtwn_softc *sc) 3093{ 3094 const struct firmware *fw; 3095 const struct r92c_fw_hdr *hdr; 3096 const char *imagename; 3097 const u_char *ptr; 3098 size_t len; 3099 uint32_t reg; 3100 int mlen, ntries, page, error; 3101 3102 URTWN_UNLOCK(sc); 3103 /* Read firmware image from the filesystem. */ 3104 if (sc->chip & URTWN_CHIP_88E) 3105 imagename = "urtwn-rtl8188eufw"; 3106 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3107 URTWN_CHIP_UMC_A_CUT) 3108 imagename = "urtwn-rtl8192cfwU"; 3109 else 3110 imagename = "urtwn-rtl8192cfwT"; 3111 3112 fw = firmware_get(imagename); 3113 URTWN_LOCK(sc); 3114 if (fw == NULL) { 3115 device_printf(sc->sc_dev, 3116 "failed loadfirmware of file %s\n", imagename); 3117 return (ENOENT); 3118 } 3119 3120 len = fw->datasize; 3121 3122 if (len < sizeof(*hdr)) { 3123 device_printf(sc->sc_dev, "firmware too short\n"); 3124 error = EINVAL; 3125 goto fail; 3126 } 3127 ptr = fw->data; 3128 hdr = (const struct r92c_fw_hdr *)ptr; 3129 /* Check if there is a valid FW header and skip it. */ 3130 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3131 (le16toh(hdr->signature) >> 4) == 0x88e || 3132 (le16toh(hdr->signature) >> 4) == 0x92c) { 3133 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 3134 le16toh(hdr->version), le16toh(hdr->subversion), 3135 hdr->month, hdr->date, hdr->hour, hdr->minute); 3136 ptr += sizeof(*hdr); 3137 len -= sizeof(*hdr); 3138 } 3139 3140 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3141 if (sc->chip & URTWN_CHIP_88E) 3142 urtwn_r88e_fw_reset(sc); 3143 else 3144 urtwn_fw_reset(sc); 3145 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3146 } 3147 3148 if (!(sc->chip & URTWN_CHIP_88E)) { 3149 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3150 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3151 R92C_SYS_FUNC_EN_CPUEN); 3152 } 3153 urtwn_write_1(sc, R92C_MCUFWDL, 3154 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3155 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3156 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3157 3158 /* Reset the FWDL checksum. */ 3159 urtwn_write_1(sc, R92C_MCUFWDL, 3160 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3161 3162 for (page = 0; len > 0; page++) { 3163 mlen = min(len, R92C_FW_PAGE_SIZE); 3164 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3165 if (error != 0) { 3166 device_printf(sc->sc_dev, 3167 "could not load firmware page\n"); 3168 goto fail; 3169 } 3170 ptr += mlen; 3171 len -= mlen; 3172 } 3173 urtwn_write_1(sc, R92C_MCUFWDL, 3174 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3175 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3176 3177 /* Wait for checksum report. */ 3178 for (ntries = 0; ntries < 1000; ntries++) { 3179 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3180 break; 3181 urtwn_ms_delay(sc); 3182 } 3183 if (ntries == 1000) { 3184 device_printf(sc->sc_dev, 3185 "timeout waiting for checksum report\n"); 3186 error = ETIMEDOUT; 3187 goto fail; 3188 } 3189 3190 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3191 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3192 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3193 if (sc->chip & URTWN_CHIP_88E) 3194 urtwn_r88e_fw_reset(sc); 3195 /* Wait for firmware readiness. */ 3196 for (ntries = 0; ntries < 1000; ntries++) { 3197 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3198 break; 3199 urtwn_ms_delay(sc); 3200 } 3201 if (ntries == 1000) { 3202 device_printf(sc->sc_dev, 3203 "timeout waiting for firmware readiness\n"); 3204 error = ETIMEDOUT; 3205 goto fail; 3206 } 3207fail: 3208 firmware_put(fw, FIRMWARE_UNLOAD); 3209 return (error); 3210} 3211 3212static int 3213urtwn_dma_init(struct urtwn_softc *sc) 3214{ 3215 struct usb_endpoint *ep, *ep_end; 3216 usb_error_t usb_err; 3217 uint32_t reg; 3218 int hashq, hasnq, haslq, nqueues, ntx; 3219 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 3220 3221 /* Initialize LLT table. */ 3222 error = urtwn_llt_init(sc); 3223 if (error != 0) 3224 return (error); 3225 3226 /* Determine the number of bulk-out pipes. */ 3227 ntx = 0; 3228 ep = sc->sc_udev->endpoints; 3229 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 3230 for (; ep != ep_end; ep++) { 3231 if ((ep->edesc == NULL) || 3232 (ep->iface_index != sc->sc_iface_index)) 3233 continue; 3234 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 3235 ntx++; 3236 } 3237 if (ntx == 0) { 3238 device_printf(sc->sc_dev, 3239 "%d: invalid number of Tx bulk pipes\n", ntx); 3240 return (EIO); 3241 } 3242 3243 /* Get Tx queues to USB endpoints mapping. */ 3244 hashq = hasnq = haslq = nqueues = 0; 3245 switch (ntx) { 3246 case 1: hashq = 1; break; 3247 case 2: hashq = hasnq = 1; break; 3248 case 3: case 4: hashq = hasnq = haslq = 1; break; 3249 } 3250 nqueues = hashq + hasnq + haslq; 3251 if (nqueues == 0) 3252 return (EIO); 3253 3254 npubqpages = nqpages = nrempages = pagecount = 0; 3255 if (sc->chip & URTWN_CHIP_88E) 3256 tx_boundary = R88E_TX_PAGE_BOUNDARY; 3257 else { 3258 pagecount = R92C_TX_PAGE_COUNT; 3259 npubqpages = R92C_PUBQ_NPAGES; 3260 tx_boundary = R92C_TX_PAGE_BOUNDARY; 3261 } 3262 3263 /* Set number of pages for normal priority queue. */ 3264 if (sc->chip & URTWN_CHIP_88E) { 3265 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 3266 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3267 return (EIO); 3268 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3269 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3270 return (EIO); 3271 } else { 3272 /* Get the number of pages for each queue. */ 3273 nqpages = (pagecount - npubqpages) / nqueues; 3274 /* 3275 * The remaining pages are assigned to the high priority 3276 * queue. 3277 */ 3278 nrempages = (pagecount - npubqpages) % nqueues; 3279 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3280 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3281 return (EIO); 3282 usb_err = urtwn_write_4(sc, R92C_RQPN, 3283 /* Set number of pages for public queue. */ 3284 SM(R92C_RQPN_PUBQ, npubqpages) | 3285 /* Set number of pages for high priority queue. */ 3286 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3287 /* Set number of pages for low priority queue. */ 3288 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3289 /* Load values. */ 3290 R92C_RQPN_LD); 3291 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3292 return (EIO); 3293 } 3294 3295 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 3296 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3297 return (EIO); 3298 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 3299 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3300 return (EIO); 3301 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 3302 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3303 return (EIO); 3304 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 3305 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3306 return (EIO); 3307 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 3308 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3309 return (EIO); 3310 3311 /* Set queue to USB pipe mapping. */ 3312 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3313 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3314 if (nqueues == 1) { 3315 if (hashq) 3316 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3317 else if (hasnq) 3318 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3319 else 3320 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3321 } else if (nqueues == 2) { 3322 /* 3323 * All 2-endpoints configs have high and normal 3324 * priority queues. 3325 */ 3326 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3327 } else 3328 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3329 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3330 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3331 return (EIO); 3332 3333 /* Set Tx/Rx transfer page boundary. */ 3334 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 3335 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 3336 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3337 return (EIO); 3338 3339 /* Set Tx/Rx transfer page size. */ 3340 usb_err = urtwn_write_1(sc, R92C_PBP, 3341 SM(R92C_PBP_PSRX, R92C_PBP_128) | 3342 SM(R92C_PBP_PSTX, R92C_PBP_128)); 3343 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3344 return (EIO); 3345 3346 return (0); 3347} 3348 3349static int 3350urtwn_mac_init(struct urtwn_softc *sc) 3351{ 3352 usb_error_t error; 3353 int i; 3354 3355 /* Write MAC initialization values. */ 3356 if (sc->chip & URTWN_CHIP_88E) { 3357 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 3358 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3359 rtl8188eu_mac[i].val); 3360 if (error != USB_ERR_NORMAL_COMPLETION) 3361 return (EIO); 3362 } 3363 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 3364 } else { 3365 for (i = 0; i < nitems(rtl8192cu_mac); i++) 3366 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3367 rtl8192cu_mac[i].val); 3368 if (error != USB_ERR_NORMAL_COMPLETION) 3369 return (EIO); 3370 } 3371 3372 return (0); 3373} 3374 3375static void 3376urtwn_bb_init(struct urtwn_softc *sc) 3377{ 3378 const struct urtwn_bb_prog *prog; 3379 uint32_t reg; 3380 uint8_t crystalcap; 3381 int i; 3382 3383 /* Enable BB and RF. */ 3384 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3385 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3386 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3387 R92C_SYS_FUNC_EN_DIO_RF); 3388 3389 if (!(sc->chip & URTWN_CHIP_88E)) 3390 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 3391 3392 urtwn_write_1(sc, R92C_RF_CTRL, 3393 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3394 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3395 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3396 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3397 3398 if (!(sc->chip & URTWN_CHIP_88E)) { 3399 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3400 urtwn_write_1(sc, 0x15, 0xe9); 3401 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3402 } 3403 3404 /* Select BB programming based on board type. */ 3405 if (sc->chip & URTWN_CHIP_88E) 3406 prog = &rtl8188eu_bb_prog; 3407 else if (!(sc->chip & URTWN_CHIP_92C)) { 3408 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3409 prog = &rtl8188ce_bb_prog; 3410 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3411 prog = &rtl8188ru_bb_prog; 3412 else 3413 prog = &rtl8188cu_bb_prog; 3414 } else { 3415 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3416 prog = &rtl8192ce_bb_prog; 3417 else 3418 prog = &rtl8192cu_bb_prog; 3419 } 3420 /* Write BB initialization values. */ 3421 for (i = 0; i < prog->count; i++) { 3422 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3423 urtwn_ms_delay(sc); 3424 } 3425 3426 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3427 /* 8192C 1T only configuration. */ 3428 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3429 reg = (reg & ~0x00000003) | 0x2; 3430 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3431 3432 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3433 reg = (reg & ~0x00300033) | 0x00200022; 3434 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3435 3436 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3437 reg = (reg & ~0xff000000) | 0x45 << 24; 3438 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3439 3440 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3441 reg = (reg & ~0x000000ff) | 0x23; 3442 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3443 3444 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3445 reg = (reg & ~0x00000030) | 1 << 4; 3446 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3447 3448 reg = urtwn_bb_read(sc, 0xe74); 3449 reg = (reg & ~0x0c000000) | 2 << 26; 3450 urtwn_bb_write(sc, 0xe74, reg); 3451 reg = urtwn_bb_read(sc, 0xe78); 3452 reg = (reg & ~0x0c000000) | 2 << 26; 3453 urtwn_bb_write(sc, 0xe78, reg); 3454 reg = urtwn_bb_read(sc, 0xe7c); 3455 reg = (reg & ~0x0c000000) | 2 << 26; 3456 urtwn_bb_write(sc, 0xe7c, reg); 3457 reg = urtwn_bb_read(sc, 0xe80); 3458 reg = (reg & ~0x0c000000) | 2 << 26; 3459 urtwn_bb_write(sc, 0xe80, reg); 3460 reg = urtwn_bb_read(sc, 0xe88); 3461 reg = (reg & ~0x0c000000) | 2 << 26; 3462 urtwn_bb_write(sc, 0xe88, reg); 3463 } 3464 3465 /* Write AGC values. */ 3466 for (i = 0; i < prog->agccount; i++) { 3467 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 3468 prog->agcvals[i]); 3469 urtwn_ms_delay(sc); 3470 } 3471 3472 if (sc->chip & URTWN_CHIP_88E) { 3473 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3474 urtwn_ms_delay(sc); 3475 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3476 urtwn_ms_delay(sc); 3477 3478 crystalcap = sc->rom.r88e_rom[0xb9]; 3479 if (crystalcap == 0xff) 3480 crystalcap = 0x20; 3481 crystalcap &= 0x3f; 3482 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3483 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3484 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3485 crystalcap | crystalcap << 6)); 3486 } else { 3487 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3488 R92C_HSSI_PARAM2_CCK_HIPWR) 3489 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 3490 } 3491} 3492 3493static void 3494urtwn_rf_init(struct urtwn_softc *sc) 3495{ 3496 const struct urtwn_rf_prog *prog; 3497 uint32_t reg, type; 3498 int i, j, idx, off; 3499 3500 /* Select RF programming based on board type. */ 3501 if (sc->chip & URTWN_CHIP_88E) 3502 prog = rtl8188eu_rf_prog; 3503 else if (!(sc->chip & URTWN_CHIP_92C)) { 3504 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3505 prog = rtl8188ce_rf_prog; 3506 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3507 prog = rtl8188ru_rf_prog; 3508 else 3509 prog = rtl8188cu_rf_prog; 3510 } else 3511 prog = rtl8192ce_rf_prog; 3512 3513 for (i = 0; i < sc->nrxchains; i++) { 3514 /* Save RF_ENV control type. */ 3515 idx = i / 2; 3516 off = (i % 2) * 16; 3517 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3518 type = (reg >> off) & 0x10; 3519 3520 /* Set RF_ENV enable. */ 3521 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3522 reg |= 0x100000; 3523 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3524 urtwn_ms_delay(sc); 3525 /* Set RF_ENV output high. */ 3526 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3527 reg |= 0x10; 3528 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3529 urtwn_ms_delay(sc); 3530 /* Set address and data lengths of RF registers. */ 3531 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3532 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3533 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3534 urtwn_ms_delay(sc); 3535 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3536 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3537 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3538 urtwn_ms_delay(sc); 3539 3540 /* Write RF initialization values for this chain. */ 3541 for (j = 0; j < prog[i].count; j++) { 3542 if (prog[i].regs[j] >= 0xf9 && 3543 prog[i].regs[j] <= 0xfe) { 3544 /* 3545 * These are fake RF registers offsets that 3546 * indicate a delay is required. 3547 */ 3548 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 3549 continue; 3550 } 3551 urtwn_rf_write(sc, i, prog[i].regs[j], 3552 prog[i].vals[j]); 3553 urtwn_ms_delay(sc); 3554 } 3555 3556 /* Restore RF_ENV control type. */ 3557 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3558 reg &= ~(0x10 << off) | (type << off); 3559 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 3560 3561 /* Cache RF register CHNLBW. */ 3562 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3563 } 3564 3565 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3566 URTWN_CHIP_UMC_A_CUT) { 3567 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3568 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3569 } 3570} 3571 3572static void 3573urtwn_cam_init(struct urtwn_softc *sc) 3574{ 3575 /* Invalidate all CAM entries. */ 3576 urtwn_write_4(sc, R92C_CAMCMD, 3577 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3578} 3579 3580static int 3581urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 3582{ 3583 usb_error_t error; 3584 3585 error = urtwn_write_4(sc, R92C_CAMWRITE, data); 3586 if (error != USB_ERR_NORMAL_COMPLETION) 3587 return (EIO); 3588 error = urtwn_write_4(sc, R92C_CAMCMD, 3589 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 3590 SM(R92C_CAMCMD_ADDR, addr)); 3591 if (error != USB_ERR_NORMAL_COMPLETION) 3592 return (EIO); 3593 3594 return (0); 3595} 3596 3597static void 3598urtwn_pa_bias_init(struct urtwn_softc *sc) 3599{ 3600 uint8_t reg; 3601 int i; 3602 3603 for (i = 0; i < sc->nrxchains; i++) { 3604 if (sc->pa_setting & (1 << i)) 3605 continue; 3606 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3607 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3608 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3609 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3610 } 3611 if (!(sc->pa_setting & 0x10)) { 3612 reg = urtwn_read_1(sc, 0x16); 3613 reg = (reg & ~0xf0) | 0x90; 3614 urtwn_write_1(sc, 0x16, reg); 3615 } 3616} 3617 3618static void 3619urtwn_rxfilter_init(struct urtwn_softc *sc) 3620{ 3621 struct ieee80211com *ic = &sc->sc_ic; 3622 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3623 uint32_t rcr; 3624 uint16_t filter; 3625 3626 URTWN_ASSERT_LOCKED(sc); 3627 3628 /* Accept all multicast frames. */ 3629 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3630 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3631 3632 /* Filter for management frames. */ 3633 filter = 0x7f3f; 3634 switch (vap->iv_opmode) { 3635 case IEEE80211_M_STA: 3636 filter &= ~( 3637 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 3638 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 3639 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 3640 break; 3641 case IEEE80211_M_HOSTAP: 3642 filter &= ~( 3643 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 3644 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP) | 3645 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_BEACON)); 3646 break; 3647 case IEEE80211_M_MONITOR: 3648 case IEEE80211_M_IBSS: 3649 break; 3650 default: 3651 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3652 __func__, vap->iv_opmode); 3653 break; 3654 } 3655 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 3656 3657 /* Reject all control frames. */ 3658 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3659 3660 /* Reject all data frames. */ 3661 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 3662 3663 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 3664 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 3665 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 3666 3667 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 3668 /* Accept all frames. */ 3669 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 3670 R92C_RCR_AAP; 3671 } 3672 3673 /* Set Rx filter. */ 3674 urtwn_write_4(sc, R92C_RCR, rcr); 3675 3676 if (ic->ic_promisc != 0) { 3677 /* Update Rx filter. */ 3678 urtwn_set_promisc(sc); 3679 } 3680} 3681 3682static void 3683urtwn_edca_init(struct urtwn_softc *sc) 3684{ 3685 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3686 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3687 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3688 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3689 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3690 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3691 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3692 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3693} 3694 3695static void 3696urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3697 uint16_t power[URTWN_RIDX_COUNT]) 3698{ 3699 uint32_t reg; 3700 3701 /* Write per-CCK rate Tx power. */ 3702 if (chain == 0) { 3703 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3704 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3705 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3706 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3707 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3708 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3709 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3710 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3711 } else { 3712 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3713 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3714 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3715 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3716 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3717 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3718 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3719 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3720 } 3721 /* Write per-OFDM rate Tx power. */ 3722 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3723 SM(R92C_TXAGC_RATE06, power[ 4]) | 3724 SM(R92C_TXAGC_RATE09, power[ 5]) | 3725 SM(R92C_TXAGC_RATE12, power[ 6]) | 3726 SM(R92C_TXAGC_RATE18, power[ 7])); 3727 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3728 SM(R92C_TXAGC_RATE24, power[ 8]) | 3729 SM(R92C_TXAGC_RATE36, power[ 9]) | 3730 SM(R92C_TXAGC_RATE48, power[10]) | 3731 SM(R92C_TXAGC_RATE54, power[11])); 3732 /* Write per-MCS Tx power. */ 3733 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3734 SM(R92C_TXAGC_MCS00, power[12]) | 3735 SM(R92C_TXAGC_MCS01, power[13]) | 3736 SM(R92C_TXAGC_MCS02, power[14]) | 3737 SM(R92C_TXAGC_MCS03, power[15])); 3738 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3739 SM(R92C_TXAGC_MCS04, power[16]) | 3740 SM(R92C_TXAGC_MCS05, power[17]) | 3741 SM(R92C_TXAGC_MCS06, power[18]) | 3742 SM(R92C_TXAGC_MCS07, power[19])); 3743 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3744 SM(R92C_TXAGC_MCS08, power[20]) | 3745 SM(R92C_TXAGC_MCS09, power[21]) | 3746 SM(R92C_TXAGC_MCS10, power[22]) | 3747 SM(R92C_TXAGC_MCS11, power[23])); 3748 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3749 SM(R92C_TXAGC_MCS12, power[24]) | 3750 SM(R92C_TXAGC_MCS13, power[25]) | 3751 SM(R92C_TXAGC_MCS14, power[26]) | 3752 SM(R92C_TXAGC_MCS15, power[27])); 3753} 3754 3755static void 3756urtwn_get_txpower(struct urtwn_softc *sc, int chain, 3757 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3758 uint16_t power[URTWN_RIDX_COUNT]) 3759{ 3760 struct ieee80211com *ic = &sc->sc_ic; 3761 struct r92c_rom *rom = &sc->rom.r92c_rom; 3762 uint16_t cckpow, ofdmpow, htpow, diff, max; 3763 const struct urtwn_txpwr *base; 3764 int ridx, chan, group; 3765 3766 /* Determine channel group. */ 3767 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3768 if (chan <= 3) 3769 group = 0; 3770 else if (chan <= 9) 3771 group = 1; 3772 else 3773 group = 2; 3774 3775 /* Get original Tx power based on board type and RF chain. */ 3776 if (!(sc->chip & URTWN_CHIP_92C)) { 3777 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3778 base = &rtl8188ru_txagc[chain]; 3779 else 3780 base = &rtl8192cu_txagc[chain]; 3781 } else 3782 base = &rtl8192cu_txagc[chain]; 3783 3784 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3785 if (sc->regulatory == 0) { 3786 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3787 power[ridx] = base->pwr[0][ridx]; 3788 } 3789 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3790 if (sc->regulatory == 3) { 3791 power[ridx] = base->pwr[0][ridx]; 3792 /* Apply vendor limits. */ 3793 if (extc != NULL) 3794 max = rom->ht40_max_pwr[group]; 3795 else 3796 max = rom->ht20_max_pwr[group]; 3797 max = (max >> (chain * 4)) & 0xf; 3798 if (power[ridx] > max) 3799 power[ridx] = max; 3800 } else if (sc->regulatory == 1) { 3801 if (extc == NULL) 3802 power[ridx] = base->pwr[group][ridx]; 3803 } else if (sc->regulatory != 2) 3804 power[ridx] = base->pwr[0][ridx]; 3805 } 3806 3807 /* Compute per-CCK rate Tx power. */ 3808 cckpow = rom->cck_tx_pwr[chain][group]; 3809 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3810 power[ridx] += cckpow; 3811 if (power[ridx] > R92C_MAX_TX_PWR) 3812 power[ridx] = R92C_MAX_TX_PWR; 3813 } 3814 3815 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3816 if (sc->ntxchains > 1) { 3817 /* Apply reduction for 2 spatial streams. */ 3818 diff = rom->ht40_2s_tx_pwr_diff[group]; 3819 diff = (diff >> (chain * 4)) & 0xf; 3820 htpow = (htpow > diff) ? htpow - diff : 0; 3821 } 3822 3823 /* Compute per-OFDM rate Tx power. */ 3824 diff = rom->ofdm_tx_pwr_diff[group]; 3825 diff = (diff >> (chain * 4)) & 0xf; 3826 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3827 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3828 power[ridx] += ofdmpow; 3829 if (power[ridx] > R92C_MAX_TX_PWR) 3830 power[ridx] = R92C_MAX_TX_PWR; 3831 } 3832 3833 /* Compute per-MCS Tx power. */ 3834 if (extc == NULL) { 3835 diff = rom->ht20_tx_pwr_diff[group]; 3836 diff = (diff >> (chain * 4)) & 0xf; 3837 htpow += diff; /* HT40->HT20 correction. */ 3838 } 3839 for (ridx = 12; ridx <= 27; ridx++) { 3840 power[ridx] += htpow; 3841 if (power[ridx] > R92C_MAX_TX_PWR) 3842 power[ridx] = R92C_MAX_TX_PWR; 3843 } 3844#ifdef URTWN_DEBUG 3845 if (urtwn_debug >= 4) { 3846 /* Dump per-rate Tx power values. */ 3847 printf("Tx power for chain %d:\n", chain); 3848 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 3849 printf("Rate %d = %u\n", ridx, power[ridx]); 3850 } 3851#endif 3852} 3853 3854static void 3855urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3856 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3857 uint16_t power[URTWN_RIDX_COUNT]) 3858{ 3859 struct ieee80211com *ic = &sc->sc_ic; 3860 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3861 const struct urtwn_r88e_txpwr *base; 3862 int ridx, chan, group; 3863 3864 /* Determine channel group. */ 3865 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3866 if (chan <= 2) 3867 group = 0; 3868 else if (chan <= 5) 3869 group = 1; 3870 else if (chan <= 8) 3871 group = 2; 3872 else if (chan <= 11) 3873 group = 3; 3874 else if (chan <= 13) 3875 group = 4; 3876 else 3877 group = 5; 3878 3879 /* Get original Tx power based on board type and RF chain. */ 3880 base = &rtl8188eu_txagc[chain]; 3881 3882 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3883 if (sc->regulatory == 0) { 3884 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3885 power[ridx] = base->pwr[0][ridx]; 3886 } 3887 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3888 if (sc->regulatory == 3) 3889 power[ridx] = base->pwr[0][ridx]; 3890 else if (sc->regulatory == 1) { 3891 if (extc == NULL) 3892 power[ridx] = base->pwr[group][ridx]; 3893 } else if (sc->regulatory != 2) 3894 power[ridx] = base->pwr[0][ridx]; 3895 } 3896 3897 /* Compute per-CCK rate Tx power. */ 3898 cckpow = sc->cck_tx_pwr[group]; 3899 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3900 power[ridx] += cckpow; 3901 if (power[ridx] > R92C_MAX_TX_PWR) 3902 power[ridx] = R92C_MAX_TX_PWR; 3903 } 3904 3905 htpow = sc->ht40_tx_pwr[group]; 3906 3907 /* Compute per-OFDM rate Tx power. */ 3908 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3909 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3910 power[ridx] += ofdmpow; 3911 if (power[ridx] > R92C_MAX_TX_PWR) 3912 power[ridx] = R92C_MAX_TX_PWR; 3913 } 3914 3915 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3916 for (ridx = 12; ridx <= 27; ridx++) { 3917 power[ridx] += bw20pow; 3918 if (power[ridx] > R92C_MAX_TX_PWR) 3919 power[ridx] = R92C_MAX_TX_PWR; 3920 } 3921} 3922 3923static void 3924urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3925 struct ieee80211_channel *extc) 3926{ 3927 uint16_t power[URTWN_RIDX_COUNT]; 3928 int i; 3929 3930 for (i = 0; i < sc->ntxchains; i++) { 3931 /* Compute per-rate Tx power values. */ 3932 if (sc->chip & URTWN_CHIP_88E) 3933 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3934 else 3935 urtwn_get_txpower(sc, i, c, extc, power); 3936 /* Write per-rate Tx power values to hardware. */ 3937 urtwn_write_txpower(sc, i, power); 3938 } 3939} 3940 3941static void 3942urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 3943{ 3944 uint32_t reg; 3945 3946 reg = urtwn_read_4(sc, R92C_RCR); 3947 if (enable) 3948 reg &= ~R92C_RCR_CBSSID_BCN; 3949 else 3950 reg |= R92C_RCR_CBSSID_BCN; 3951 urtwn_write_4(sc, R92C_RCR, reg); 3952} 3953 3954static void 3955urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 3956{ 3957 uint32_t reg; 3958 3959 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3960 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3961 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3962 3963 if (!(sc->chip & URTWN_CHIP_88E)) { 3964 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3965 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3966 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3967 } 3968} 3969 3970static void 3971urtwn_scan_start(struct ieee80211com *ic) 3972{ 3973 struct urtwn_softc *sc = ic->ic_softc; 3974 3975 URTWN_LOCK(sc); 3976 /* Receive beacons / probe responses from any BSSID. */ 3977 if (ic->ic_opmode != IEEE80211_M_IBSS) 3978 urtwn_set_rx_bssid_all(sc, 1); 3979 3980 /* Set gain for scanning. */ 3981 urtwn_set_gain(sc, 0x20); 3982 URTWN_UNLOCK(sc); 3983} 3984 3985static void 3986urtwn_scan_end(struct ieee80211com *ic) 3987{ 3988 struct urtwn_softc *sc = ic->ic_softc; 3989 3990 URTWN_LOCK(sc); 3991 /* Restore limitations. */ 3992 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 3993 urtwn_set_rx_bssid_all(sc, 0); 3994 3995 /* Set gain under link. */ 3996 urtwn_set_gain(sc, 0x32); 3997 URTWN_UNLOCK(sc); 3998} 3999 4000static void 4001urtwn_set_channel(struct ieee80211com *ic) 4002{ 4003 struct urtwn_softc *sc = ic->ic_softc; 4004 struct ieee80211_channel *c = ic->ic_curchan; 4005 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4006 4007 URTWN_LOCK(sc); 4008 if (vap->iv_state == IEEE80211_S_SCAN) { 4009 /* Make link LED blink during scan. */ 4010 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 4011 } 4012 urtwn_set_chan(sc, c, NULL); 4013 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 4014 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 4015 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 4016 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 4017 URTWN_UNLOCK(sc); 4018} 4019 4020static int 4021urtwn_wme_update(struct ieee80211com *ic) 4022{ 4023 const struct wmeParams *wmep = 4024 ic->ic_wme.wme_chanParams.cap_wmeParams; 4025 struct urtwn_softc *sc = ic->ic_softc; 4026 uint8_t aifs, acm, slottime; 4027 int ac; 4028 4029 acm = 0; 4030 slottime = IEEE80211_GET_SLOTTIME(ic); 4031 4032 URTWN_LOCK(sc); 4033 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4034 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4035 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4036 urtwn_write_4(sc, wme2queue[ac].reg, 4037 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 4038 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 4039 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 4040 SM(R92C_EDCA_PARAM_AIFS, aifs)); 4041 if (ac != WME_AC_BE) 4042 acm |= wmep[ac].wmep_acm << ac; 4043 } 4044 4045 if (acm != 0) 4046 acm |= R92C_ACMHWCTRL_EN; 4047 urtwn_write_1(sc, R92C_ACMHWCTRL, 4048 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 4049 acm); 4050 4051 URTWN_UNLOCK(sc); 4052 4053 return 0; 4054} 4055 4056static void 4057urtwn_set_promisc(struct urtwn_softc *sc) 4058{ 4059 struct ieee80211com *ic = &sc->sc_ic; 4060 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4061 uint32_t rcr, mask1, mask2; 4062 4063 URTWN_ASSERT_LOCKED(sc); 4064 4065 if (vap->iv_opmode == IEEE80211_M_MONITOR) 4066 return; 4067 4068 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 4069 mask2 = R92C_RCR_APM; 4070 4071 if (vap->iv_state == IEEE80211_S_RUN) { 4072 switch (vap->iv_opmode) { 4073 case IEEE80211_M_STA: 4074 mask2 |= R92C_RCR_CBSSID_DATA; 4075 /* FALLTHROUGH */ 4076 case IEEE80211_M_HOSTAP: 4077 mask2 |= R92C_RCR_CBSSID_BCN; 4078 break; 4079 case IEEE80211_M_IBSS: 4080 mask2 |= R92C_RCR_CBSSID_DATA; 4081 break; 4082 default: 4083 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4084 __func__, vap->iv_opmode); 4085 return; 4086 } 4087 } 4088 4089 rcr = urtwn_read_4(sc, R92C_RCR); 4090 if (ic->ic_promisc == 0) 4091 rcr = (rcr & ~mask1) | mask2; 4092 else 4093 rcr = (rcr & ~mask2) | mask1; 4094 urtwn_write_4(sc, R92C_RCR, rcr); 4095} 4096 4097static void 4098urtwn_update_promisc(struct ieee80211com *ic) 4099{ 4100 struct urtwn_softc *sc = ic->ic_softc; 4101 4102 URTWN_LOCK(sc); 4103 if (sc->sc_flags & URTWN_RUNNING) 4104 urtwn_set_promisc(sc); 4105 URTWN_UNLOCK(sc); 4106} 4107 4108static void 4109urtwn_update_mcast(struct ieee80211com *ic) 4110{ 4111 /* XXX do nothing? */ 4112} 4113 4114static struct ieee80211_node * 4115urtwn_r88e_node_alloc(struct ieee80211vap *vap, 4116 const uint8_t mac[IEEE80211_ADDR_LEN]) 4117{ 4118 struct urtwn_node *un; 4119 4120 un = malloc(sizeof (struct urtwn_node), M_80211_NODE, 4121 M_NOWAIT | M_ZERO); 4122 4123 if (un == NULL) 4124 return NULL; 4125 4126 un->id = URTWN_MACID_UNDEFINED; 4127 4128 return &un->ni; 4129} 4130 4131static void 4132urtwn_r88e_newassoc(struct ieee80211_node *ni, int isnew) 4133{ 4134 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4135 struct urtwn_node *un = URTWN_NODE(ni); 4136 uint8_t id; 4137 4138 if (!isnew) 4139 return; 4140 4141 URTWN_NT_LOCK(sc); 4142 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 4143 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 4144 un->id = id; 4145 sc->node_list[id] = ni; 4146 break; 4147 } 4148 } 4149 URTWN_NT_UNLOCK(sc); 4150 4151 if (id > URTWN_MACID_MAX(sc)) { 4152 device_printf(sc->sc_dev, "%s: node table is full\n", 4153 __func__); 4154 } 4155} 4156 4157static void 4158urtwn_r88e_node_free(struct ieee80211_node *ni) 4159{ 4160 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4161 struct urtwn_node *un = URTWN_NODE(ni); 4162 4163 URTWN_NT_LOCK(sc); 4164 if (un->id != URTWN_MACID_UNDEFINED) 4165 sc->node_list[un->id] = NULL; 4166 URTWN_NT_UNLOCK(sc); 4167 4168 sc->sc_node_free(ni); 4169} 4170 4171static void 4172urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 4173 struct ieee80211_channel *extc) 4174{ 4175 struct ieee80211com *ic = &sc->sc_ic; 4176 uint32_t reg; 4177 u_int chan; 4178 int i; 4179 4180 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4181 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 4182 device_printf(sc->sc_dev, 4183 "%s: invalid channel %x\n", __func__, chan); 4184 return; 4185 } 4186 4187 /* Set Tx power for this new channel. */ 4188 urtwn_set_txpower(sc, c, extc); 4189 4190 for (i = 0; i < sc->nrxchains; i++) { 4191 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4192 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4193 } 4194#ifndef IEEE80211_NO_HT 4195 if (extc != NULL) { 4196 /* Is secondary channel below or above primary? */ 4197 int prichlo = c->ic_freq < extc->ic_freq; 4198 4199 urtwn_write_1(sc, R92C_BWOPMODE, 4200 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4201 4202 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4203 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4204 urtwn_write_1(sc, R92C_RRSR + 2, reg); 4205 4206 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4207 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4208 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4209 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4210 4211 /* Set CCK side band. */ 4212 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4213 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4214 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4215 4216 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4217 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4218 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4219 4220 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4221 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4222 ~R92C_FPGA0_ANAPARAM2_CBW20); 4223 4224 reg = urtwn_bb_read(sc, 0x818); 4225 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4226 urtwn_bb_write(sc, 0x818, reg); 4227 4228 /* Select 40MHz bandwidth. */ 4229 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4230 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4231 } else 4232#endif 4233 { 4234 urtwn_write_1(sc, R92C_BWOPMODE, 4235 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4236 4237 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4238 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4239 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4240 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4241 4242 if (!(sc->chip & URTWN_CHIP_88E)) { 4243 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4244 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4245 R92C_FPGA0_ANAPARAM2_CBW20); 4246 } 4247 4248 /* Select 20MHz bandwidth. */ 4249 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4250 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4251 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 4252 R92C_RF_CHNLBW_BW20)); 4253 } 4254} 4255 4256static void 4257urtwn_iq_calib(struct urtwn_softc *sc) 4258{ 4259 /* TODO */ 4260} 4261 4262static void 4263urtwn_lc_calib(struct urtwn_softc *sc) 4264{ 4265 uint32_t rf_ac[2]; 4266 uint8_t txmode; 4267 int i; 4268 4269 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4270 if ((txmode & 0x70) != 0) { 4271 /* Disable all continuous Tx. */ 4272 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4273 4274 /* Set RF mode to standby mode. */ 4275 for (i = 0; i < sc->nrxchains; i++) { 4276 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4277 urtwn_rf_write(sc, i, R92C_RF_AC, 4278 RW(rf_ac[i], R92C_RF_AC_MODE, 4279 R92C_RF_AC_MODE_STANDBY)); 4280 } 4281 } else { 4282 /* Block all Tx queues. */ 4283 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4284 } 4285 /* Start calibration. */ 4286 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4287 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4288 4289 /* Give calibration the time to complete. */ 4290 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 4291 4292 /* Restore configuration. */ 4293 if ((txmode & 0x70) != 0) { 4294 /* Restore Tx mode. */ 4295 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4296 /* Restore RF mode. */ 4297 for (i = 0; i < sc->nrxchains; i++) 4298 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4299 } else { 4300 /* Unblock all Tx queues. */ 4301 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4302 } 4303} 4304 4305static int 4306urtwn_init(struct urtwn_softc *sc) 4307{ 4308 struct ieee80211com *ic = &sc->sc_ic; 4309 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4310 uint8_t macaddr[IEEE80211_ADDR_LEN]; 4311 uint32_t reg; 4312 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 4313 int error; 4314 4315 URTWN_LOCK(sc); 4316 if (sc->sc_flags & URTWN_RUNNING) { 4317 URTWN_UNLOCK(sc); 4318 return (0); 4319 } 4320 4321 /* Init firmware commands ring. */ 4322 sc->fwcur = 0; 4323 4324 /* Allocate Tx/Rx buffers. */ 4325 error = urtwn_alloc_rx_list(sc); 4326 if (error != 0) 4327 goto fail; 4328 4329 error = urtwn_alloc_tx_list(sc); 4330 if (error != 0) 4331 goto fail; 4332 4333 /* Power on adapter. */ 4334 error = urtwn_power_on(sc); 4335 if (error != 0) 4336 goto fail; 4337 4338 /* Initialize DMA. */ 4339 error = urtwn_dma_init(sc); 4340 if (error != 0) 4341 goto fail; 4342 4343 /* Set info size in Rx descriptors (in 64-bit words). */ 4344 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4345 4346 /* Init interrupts. */ 4347 if (sc->chip & URTWN_CHIP_88E) { 4348 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4349 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4350 goto fail; 4351 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4352 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4353 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4354 goto fail; 4355 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4356 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4357 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4358 goto fail; 4359 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4360 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4361 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4362 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4363 goto fail; 4364 } else { 4365 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4366 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4367 goto fail; 4368 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4369 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4370 goto fail; 4371 } 4372 4373 /* Set MAC address. */ 4374 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 4375 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 4376 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4377 goto fail; 4378 4379 /* Set initial network type. */ 4380 urtwn_set_mode(sc, R92C_MSR_INFRA); 4381 4382 /* Initialize Rx filter. */ 4383 urtwn_rxfilter_init(sc); 4384 4385 /* Set response rate. */ 4386 reg = urtwn_read_4(sc, R92C_RRSR); 4387 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4388 urtwn_write_4(sc, R92C_RRSR, reg); 4389 4390 /* Set short/long retry limits. */ 4391 urtwn_write_2(sc, R92C_RL, 4392 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4393 4394 /* Initialize EDCA parameters. */ 4395 urtwn_edca_init(sc); 4396 4397 /* Setup rate fallback. */ 4398 if (!(sc->chip & URTWN_CHIP_88E)) { 4399 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4400 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4401 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4402 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4403 } 4404 4405 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4406 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4407 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4408 /* Set ACK timeout. */ 4409 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4410 4411 /* Setup USB aggregation. */ 4412 reg = urtwn_read_4(sc, R92C_TDECTRL); 4413 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4414 urtwn_write_4(sc, R92C_TDECTRL, reg); 4415 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4416 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4417 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4418 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4419 if (sc->chip & URTWN_CHIP_88E) 4420 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4421 else { 4422 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4423 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4424 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4425 R92C_USB_SPECIAL_OPTION_AGG_EN); 4426 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 4427 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 4428 } 4429 4430 /* Initialize beacon parameters. */ 4431 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4432 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4433 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 4434 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 4435 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4436 4437 if (!(sc->chip & URTWN_CHIP_88E)) { 4438 /* Setup AMPDU aggregation. */ 4439 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4440 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4441 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 4442 4443 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4444 } 4445 4446 /* Load 8051 microcode. */ 4447 error = urtwn_load_firmware(sc); 4448 if (error != 0) 4449 goto fail; 4450 4451 /* Initialize MAC/BB/RF blocks. */ 4452 error = urtwn_mac_init(sc); 4453 if (error != 0) { 4454 device_printf(sc->sc_dev, 4455 "%s: error while initializing MAC block\n", __func__); 4456 goto fail; 4457 } 4458 urtwn_bb_init(sc); 4459 urtwn_rf_init(sc); 4460 4461 /* Reinitialize Rx filter (D3845 is not committed yet). */ 4462 urtwn_rxfilter_init(sc); 4463 4464 if (sc->chip & URTWN_CHIP_88E) { 4465 urtwn_write_2(sc, R92C_CR, 4466 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4467 R92C_CR_MACRXEN); 4468 } 4469 4470 /* Turn CCK and OFDM blocks on. */ 4471 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4472 reg |= R92C_RFMOD_CCK_EN; 4473 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4474 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4475 goto fail; 4476 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4477 reg |= R92C_RFMOD_OFDM_EN; 4478 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4479 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4480 goto fail; 4481 4482 /* Clear per-station keys table. */ 4483 urtwn_cam_init(sc); 4484 4485 /* Enable decryption / encryption. */ 4486 urtwn_write_2(sc, R92C_SECCFG, 4487 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 4488 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA | 4489 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 4490 4491 /* 4492 * Install static keys (if any). 4493 * Must be called after urtwn_cam_init(). 4494 */ 4495 ieee80211_runtask(ic, &sc->cmdq_task); 4496 4497 /* Enable hardware sequence numbering. */ 4498 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4499 4500 /* Enable per-packet TX report. */ 4501 if (sc->chip & URTWN_CHIP_88E) { 4502 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 4503 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 4504 } 4505 4506 /* Perform LO and IQ calibrations. */ 4507 urtwn_iq_calib(sc); 4508 /* Perform LC calibration. */ 4509 urtwn_lc_calib(sc); 4510 4511 /* Fix USB interference issue. */ 4512 if (!(sc->chip & URTWN_CHIP_88E)) { 4513 urtwn_write_1(sc, 0xfe40, 0xe0); 4514 urtwn_write_1(sc, 0xfe41, 0x8d); 4515 urtwn_write_1(sc, 0xfe42, 0x80); 4516 4517 urtwn_pa_bias_init(sc); 4518 } 4519 4520 /* Initialize GPIO setting. */ 4521 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4522 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4523 4524 /* Fix for lower temperature. */ 4525 if (!(sc->chip & URTWN_CHIP_88E)) 4526 urtwn_write_1(sc, 0x15, 0xe9); 4527 4528 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 4529 4530 sc->sc_flags |= URTWN_RUNNING; 4531 4532 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4533fail: 4534 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4535 error = EIO; 4536 4537 URTWN_UNLOCK(sc); 4538 4539 return (error); 4540} 4541 4542static void 4543urtwn_stop(struct urtwn_softc *sc) 4544{ 4545 4546 URTWN_LOCK(sc); 4547 if (!(sc->sc_flags & URTWN_RUNNING)) { 4548 URTWN_UNLOCK(sc); 4549 return; 4550 } 4551 4552 sc->sc_flags &= ~URTWN_RUNNING; 4553 callout_stop(&sc->sc_watchdog_ch); 4554 urtwn_abort_xfers(sc); 4555 4556 urtwn_drain_mbufq(sc); 4557 URTWN_UNLOCK(sc); 4558} 4559 4560static void 4561urtwn_abort_xfers(struct urtwn_softc *sc) 4562{ 4563 int i; 4564 4565 URTWN_ASSERT_LOCKED(sc); 4566 4567 /* abort any pending transfers */ 4568 for (i = 0; i < URTWN_N_TRANSFER; i++) 4569 usbd_transfer_stop(sc->sc_xfer[i]); 4570} 4571 4572static int 4573urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4574 const struct ieee80211_bpf_params *params) 4575{ 4576 struct ieee80211com *ic = ni->ni_ic; 4577 struct urtwn_softc *sc = ic->ic_softc; 4578 struct urtwn_data *bf; 4579 int error; 4580 4581 /* prevent management frames from being sent if we're not ready */ 4582 URTWN_LOCK(sc); 4583 if (!(sc->sc_flags & URTWN_RUNNING)) { 4584 error = ENETDOWN; 4585 goto end; 4586 } 4587 4588 bf = urtwn_getbuf(sc); 4589 if (bf == NULL) { 4590 error = ENOBUFS; 4591 goto end; 4592 } 4593 4594 if ((error = urtwn_tx_data(sc, ni, m, bf)) != 0) { 4595 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 4596 goto end; 4597 } 4598 4599 sc->sc_txtimer = 5; 4600 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4601 4602end: 4603 if (error != 0) 4604 m_freem(m); 4605 4606 URTWN_UNLOCK(sc); 4607 4608 return (error); 4609} 4610 4611static void 4612urtwn_ms_delay(struct urtwn_softc *sc) 4613{ 4614 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 4615} 4616 4617static device_method_t urtwn_methods[] = { 4618 /* Device interface */ 4619 DEVMETHOD(device_probe, urtwn_match), 4620 DEVMETHOD(device_attach, urtwn_attach), 4621 DEVMETHOD(device_detach, urtwn_detach), 4622 4623 DEVMETHOD_END 4624}; 4625 4626static driver_t urtwn_driver = { 4627 "urtwn", 4628 urtwn_methods, 4629 sizeof(struct urtwn_softc) 4630}; 4631 4632static devclass_t urtwn_devclass; 4633 4634DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 4635MODULE_DEPEND(urtwn, usb, 1, 1, 1); 4636MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 4637MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 4638MODULE_VERSION(urtwn, 1); 4639USB_PNP_HOST_INFO(urtwn_devs); 4640