if_urtwn.c revision 291902
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 291902 2015-12-06 14:07:57Z kevlo $"); 22 23/* 24 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25 */ 26 27#include "opt_wlan.h" 28 29#include <sys/param.h> 30#include <sys/sockio.h> 31#include <sys/sysctl.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/condvar.h> 35#include <sys/mbuf.h> 36#include <sys/kernel.h> 37#include <sys/socket.h> 38#include <sys/systm.h> 39#include <sys/malloc.h> 40#include <sys/module.h> 41#include <sys/bus.h> 42#include <sys/endian.h> 43#include <sys/linker.h> 44#include <sys/firmware.h> 45#include <sys/kdb.h> 46 47#include <machine/bus.h> 48#include <machine/resource.h> 49#include <sys/rman.h> 50 51#include <net/bpf.h> 52#include <net/if.h> 53#include <net/if_var.h> 54#include <net/if_arp.h> 55#include <net/ethernet.h> 56#include <net/if_dl.h> 57#include <net/if_media.h> 58#include <net/if_types.h> 59 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/in_var.h> 63#include <netinet/if_ether.h> 64#include <netinet/ip.h> 65 66#include <net80211/ieee80211_var.h> 67#include <net80211/ieee80211_input.h> 68#include <net80211/ieee80211_regdomain.h> 69#include <net80211/ieee80211_radiotap.h> 70#include <net80211/ieee80211_ratectl.h> 71 72#include <dev/usb/usb.h> 73#include <dev/usb/usbdi.h> 74#include <dev/usb/usb_device.h> 75#include "usbdevs.h" 76 77#define USB_DEBUG_VAR urtwn_debug 78#include <dev/usb/usb_debug.h> 79 80#include <dev/usb/wlan/if_urtwnreg.h> 81#include <dev/usb/wlan/if_urtwnvar.h> 82 83#ifdef USB_DEBUG 84static int urtwn_debug = 0; 85 86SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 87SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 88 "Debug level"); 89#endif 90 91#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 92 93/* various supported device vendors/products */ 94static const STRUCT_USB_HOST_ID urtwn_devs[] = { 95#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 96#define URTWN_RTL8188E_DEV(v,p) \ 97 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 98#define URTWN_RTL8188E 1 99 URTWN_DEV(ABOCOM, RTL8188CU_1), 100 URTWN_DEV(ABOCOM, RTL8188CU_2), 101 URTWN_DEV(ABOCOM, RTL8192CU), 102 URTWN_DEV(ASUS, RTL8192CU), 103 URTWN_DEV(ASUS, USBN10NANO), 104 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 105 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 106 URTWN_DEV(AZUREWAVE, RTL8188CU), 107 URTWN_DEV(BELKIN, F7D2102), 108 URTWN_DEV(BELKIN, RTL8188CU), 109 URTWN_DEV(BELKIN, RTL8192CU), 110 URTWN_DEV(CHICONY, RTL8188CUS_1), 111 URTWN_DEV(CHICONY, RTL8188CUS_2), 112 URTWN_DEV(CHICONY, RTL8188CUS_3), 113 URTWN_DEV(CHICONY, RTL8188CUS_4), 114 URTWN_DEV(CHICONY, RTL8188CUS_5), 115 URTWN_DEV(COREGA, RTL8192CU), 116 URTWN_DEV(DLINK, RTL8188CU), 117 URTWN_DEV(DLINK, RTL8192CU_1), 118 URTWN_DEV(DLINK, RTL8192CU_2), 119 URTWN_DEV(DLINK, RTL8192CU_3), 120 URTWN_DEV(DLINK, DWA131B), 121 URTWN_DEV(EDIMAX, EW7811UN), 122 URTWN_DEV(EDIMAX, RTL8192CU), 123 URTWN_DEV(FEIXUN, RTL8188CU), 124 URTWN_DEV(FEIXUN, RTL8192CU), 125 URTWN_DEV(GUILLEMOT, HWNUP150), 126 URTWN_DEV(HAWKING, RTL8192CU), 127 URTWN_DEV(HP3, RTL8188CU), 128 URTWN_DEV(NETGEAR, WNA1000M), 129 URTWN_DEV(NETGEAR, RTL8192CU), 130 URTWN_DEV(NETGEAR4, RTL8188CU), 131 URTWN_DEV(NOVATECH, RTL8188CU), 132 URTWN_DEV(PLANEX2, RTL8188CU_1), 133 URTWN_DEV(PLANEX2, RTL8188CU_2), 134 URTWN_DEV(PLANEX2, RTL8188CU_3), 135 URTWN_DEV(PLANEX2, RTL8188CU_4), 136 URTWN_DEV(PLANEX2, RTL8188CUS), 137 URTWN_DEV(PLANEX2, RTL8192CU), 138 URTWN_DEV(REALTEK, RTL8188CE_0), 139 URTWN_DEV(REALTEK, RTL8188CE_1), 140 URTWN_DEV(REALTEK, RTL8188CTV), 141 URTWN_DEV(REALTEK, RTL8188CU_0), 142 URTWN_DEV(REALTEK, RTL8188CU_1), 143 URTWN_DEV(REALTEK, RTL8188CU_2), 144 URTWN_DEV(REALTEK, RTL8188CU_3), 145 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 146 URTWN_DEV(REALTEK, RTL8188CUS), 147 URTWN_DEV(REALTEK, RTL8188RU_1), 148 URTWN_DEV(REALTEK, RTL8188RU_2), 149 URTWN_DEV(REALTEK, RTL8188RU_3), 150 URTWN_DEV(REALTEK, RTL8191CU), 151 URTWN_DEV(REALTEK, RTL8192CE), 152 URTWN_DEV(REALTEK, RTL8192CU), 153 URTWN_DEV(SITECOMEU, RTL8188CU_1), 154 URTWN_DEV(SITECOMEU, RTL8188CU_2), 155 URTWN_DEV(SITECOMEU, RTL8192CU), 156 URTWN_DEV(TRENDNET, RTL8188CU), 157 URTWN_DEV(TRENDNET, RTL8192CU), 158 URTWN_DEV(ZYXEL, RTL8192CU), 159 /* URTWN_RTL8188E */ 160 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 161 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 162 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 163 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 164 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 165#undef URTWN_RTL8188E_DEV 166#undef URTWN_DEV 167}; 168 169static device_probe_t urtwn_match; 170static device_attach_t urtwn_attach; 171static device_detach_t urtwn_detach; 172 173static usb_callback_t urtwn_bulk_tx_callback; 174static usb_callback_t urtwn_bulk_rx_callback; 175 176static void urtwn_drain_mbufq(struct urtwn_softc *sc); 177static usb_error_t urtwn_do_request(struct urtwn_softc *, 178 struct usb_device_request *, void *); 179static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 180 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 181 const uint8_t [IEEE80211_ADDR_LEN], 182 const uint8_t [IEEE80211_ADDR_LEN]); 183static void urtwn_vap_delete(struct ieee80211vap *); 184static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 185 int *); 186static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 187 int *, int8_t *); 188static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 189 int); 190static int urtwn_alloc_list(struct urtwn_softc *, 191 struct urtwn_data[], int, int); 192static int urtwn_alloc_rx_list(struct urtwn_softc *); 193static int urtwn_alloc_tx_list(struct urtwn_softc *); 194static void urtwn_free_list(struct urtwn_softc *, 195 struct urtwn_data data[], int); 196static void urtwn_free_rx_list(struct urtwn_softc *); 197static void urtwn_free_tx_list(struct urtwn_softc *); 198static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 199static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 200static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 201 uint8_t *, int); 202static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 203static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 204static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 205static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 206 uint8_t *, int); 207static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 208static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 209static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 210static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 211 const void *, int); 212static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 213 uint8_t, uint32_t); 214static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 215 uint8_t, uint32_t); 216static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 217static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 218 uint32_t); 219static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 220static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 221 uint8_t, uint8_t); 222#ifdef URTWN_DEBUG 223static void urtwn_dump_rom_contents(struct urtwn_softc *, 224 uint8_t *, uint16_t); 225#endif 226static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 227 uint16_t); 228static int urtwn_efuse_switch_power(struct urtwn_softc *); 229static int urtwn_read_chipid(struct urtwn_softc *); 230static int urtwn_read_rom(struct urtwn_softc *); 231static int urtwn_r88e_read_rom(struct urtwn_softc *); 232static int urtwn_ra_init(struct urtwn_softc *); 233static void urtwn_init_beacon(struct urtwn_softc *, 234 struct urtwn_vap *); 235static int urtwn_setup_beacon(struct urtwn_softc *, 236 struct ieee80211_node *); 237static void urtwn_update_beacon(struct ieee80211vap *, int); 238static int urtwn_tx_beacon(struct urtwn_softc *sc, 239 struct urtwn_vap *); 240static void urtwn_tsf_task_adhoc(void *, int); 241static void urtwn_tsf_sync_enable(struct urtwn_softc *, 242 struct ieee80211vap *); 243static void urtwn_set_led(struct urtwn_softc *, int, int); 244static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 245static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 246 struct mbuf *, int, 247 const struct ieee80211_rx_stats *, int, int); 248static int urtwn_newstate(struct ieee80211vap *, 249 enum ieee80211_state, int); 250static void urtwn_watchdog(void *); 251static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 252static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 253static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 254static int urtwn_tx_data(struct urtwn_softc *, 255 struct ieee80211_node *, struct mbuf *, 256 struct urtwn_data *); 257static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 258 uint8_t, struct urtwn_data *); 259static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 260static void urtwn_start(struct urtwn_softc *); 261static void urtwn_parent(struct ieee80211com *); 262static int urtwn_r92c_power_on(struct urtwn_softc *); 263static int urtwn_r88e_power_on(struct urtwn_softc *); 264static int urtwn_llt_init(struct urtwn_softc *); 265static void urtwn_fw_reset(struct urtwn_softc *); 266static void urtwn_r88e_fw_reset(struct urtwn_softc *); 267static int urtwn_fw_loadpage(struct urtwn_softc *, int, 268 const uint8_t *, int); 269static int urtwn_load_firmware(struct urtwn_softc *); 270static int urtwn_dma_init(struct urtwn_softc *); 271static int urtwn_mac_init(struct urtwn_softc *); 272static void urtwn_bb_init(struct urtwn_softc *); 273static void urtwn_rf_init(struct urtwn_softc *); 274static void urtwn_cam_init(struct urtwn_softc *); 275static void urtwn_pa_bias_init(struct urtwn_softc *); 276static void urtwn_rxfilter_init(struct urtwn_softc *); 277static void urtwn_edca_init(struct urtwn_softc *); 278static void urtwn_write_txpower(struct urtwn_softc *, int, 279 uint16_t[]); 280static void urtwn_get_txpower(struct urtwn_softc *, int, 281 struct ieee80211_channel *, 282 struct ieee80211_channel *, uint16_t[]); 283static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 284 struct ieee80211_channel *, 285 struct ieee80211_channel *, uint16_t[]); 286static void urtwn_set_txpower(struct urtwn_softc *, 287 struct ieee80211_channel *, 288 struct ieee80211_channel *); 289static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 290static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 291static void urtwn_scan_start(struct ieee80211com *); 292static void urtwn_scan_end(struct ieee80211com *); 293static void urtwn_set_channel(struct ieee80211com *); 294static void urtwn_set_promisc(struct urtwn_softc *); 295static void urtwn_update_promisc(struct ieee80211com *); 296static void urtwn_update_mcast(struct ieee80211com *); 297static void urtwn_set_chan(struct urtwn_softc *, 298 struct ieee80211_channel *, 299 struct ieee80211_channel *); 300static void urtwn_iq_calib(struct urtwn_softc *); 301static void urtwn_lc_calib(struct urtwn_softc *); 302static int urtwn_init(struct urtwn_softc *); 303static void urtwn_stop(struct urtwn_softc *); 304static void urtwn_abort_xfers(struct urtwn_softc *); 305static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 306 const struct ieee80211_bpf_params *); 307static void urtwn_ms_delay(struct urtwn_softc *); 308 309/* Aliases. */ 310#define urtwn_bb_write urtwn_write_4 311#define urtwn_bb_read urtwn_read_4 312 313static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 314 [URTWN_BULK_RX] = { 315 .type = UE_BULK, 316 .endpoint = UE_ADDR_ANY, 317 .direction = UE_DIR_IN, 318 .bufsize = URTWN_RXBUFSZ, 319 .flags = { 320 .pipe_bof = 1, 321 .short_xfer_ok = 1 322 }, 323 .callback = urtwn_bulk_rx_callback, 324 }, 325 [URTWN_BULK_TX_BE] = { 326 .type = UE_BULK, 327 .endpoint = 0x03, 328 .direction = UE_DIR_OUT, 329 .bufsize = URTWN_TXBUFSZ, 330 .flags = { 331 .ext_buffer = 1, 332 .pipe_bof = 1, 333 .force_short_xfer = 1 334 }, 335 .callback = urtwn_bulk_tx_callback, 336 .timeout = URTWN_TX_TIMEOUT, /* ms */ 337 }, 338 [URTWN_BULK_TX_BK] = { 339 .type = UE_BULK, 340 .endpoint = 0x03, 341 .direction = UE_DIR_OUT, 342 .bufsize = URTWN_TXBUFSZ, 343 .flags = { 344 .ext_buffer = 1, 345 .pipe_bof = 1, 346 .force_short_xfer = 1, 347 }, 348 .callback = urtwn_bulk_tx_callback, 349 .timeout = URTWN_TX_TIMEOUT, /* ms */ 350 }, 351 [URTWN_BULK_TX_VI] = { 352 .type = UE_BULK, 353 .endpoint = 0x02, 354 .direction = UE_DIR_OUT, 355 .bufsize = URTWN_TXBUFSZ, 356 .flags = { 357 .ext_buffer = 1, 358 .pipe_bof = 1, 359 .force_short_xfer = 1 360 }, 361 .callback = urtwn_bulk_tx_callback, 362 .timeout = URTWN_TX_TIMEOUT, /* ms */ 363 }, 364 [URTWN_BULK_TX_VO] = { 365 .type = UE_BULK, 366 .endpoint = 0x02, 367 .direction = UE_DIR_OUT, 368 .bufsize = URTWN_TXBUFSZ, 369 .flags = { 370 .ext_buffer = 1, 371 .pipe_bof = 1, 372 .force_short_xfer = 1 373 }, 374 .callback = urtwn_bulk_tx_callback, 375 .timeout = URTWN_TX_TIMEOUT, /* ms */ 376 }, 377}; 378 379static int 380urtwn_match(device_t self) 381{ 382 struct usb_attach_arg *uaa = device_get_ivars(self); 383 384 if (uaa->usb_mode != USB_MODE_HOST) 385 return (ENXIO); 386 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 387 return (ENXIO); 388 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 389 return (ENXIO); 390 391 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 392} 393 394static int 395urtwn_attach(device_t self) 396{ 397 struct usb_attach_arg *uaa = device_get_ivars(self); 398 struct urtwn_softc *sc = device_get_softc(self); 399 struct ieee80211com *ic = &sc->sc_ic; 400 uint8_t bands; 401 int error; 402 403 device_set_usb_desc(self); 404 sc->sc_udev = uaa->device; 405 sc->sc_dev = self; 406 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 407 sc->chip |= URTWN_CHIP_88E; 408 409 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 410 MTX_NETWORK_LOCK, MTX_DEF); 411 callout_init(&sc->sc_watchdog_ch, 0); 412 mbufq_init(&sc->sc_snd, ifqmaxlen); 413 414 sc->sc_iface_index = URTWN_IFACE_INDEX; 415 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 416 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 417 if (error) { 418 device_printf(self, "could not allocate USB transfers, " 419 "err=%s\n", usbd_errstr(error)); 420 goto detach; 421 } 422 423 URTWN_LOCK(sc); 424 425 error = urtwn_read_chipid(sc); 426 if (error) { 427 device_printf(sc->sc_dev, "unsupported test chip\n"); 428 URTWN_UNLOCK(sc); 429 goto detach; 430 } 431 432 /* Determine number of Tx/Rx chains. */ 433 if (sc->chip & URTWN_CHIP_92C) { 434 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 435 sc->nrxchains = 2; 436 } else { 437 sc->ntxchains = 1; 438 sc->nrxchains = 1; 439 } 440 441 if (sc->chip & URTWN_CHIP_88E) 442 error = urtwn_r88e_read_rom(sc); 443 else 444 error = urtwn_read_rom(sc); 445 if (error != 0) { 446 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 447 __func__, error); 448 URTWN_UNLOCK(sc); 449 goto detach; 450 } 451 452 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 453 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 454 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 455 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 456 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 457 "8188CUS", sc->ntxchains, sc->nrxchains); 458 459 URTWN_UNLOCK(sc); 460 461 ic->ic_softc = sc; 462 ic->ic_name = device_get_nameunit(self); 463 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 464 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 465 466 /* set device capabilities */ 467 ic->ic_caps = 468 IEEE80211_C_STA /* station mode */ 469 | IEEE80211_C_MONITOR /* monitor mode */ 470 | IEEE80211_C_IBSS /* adhoc mode */ 471 | IEEE80211_C_HOSTAP /* hostap mode */ 472 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 473 | IEEE80211_C_SHSLOT /* short slot time supported */ 474 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 475 | IEEE80211_C_WPA /* 802.11i */ 476 ; 477 478 bands = 0; 479 setbit(&bands, IEEE80211_MODE_11B); 480 setbit(&bands, IEEE80211_MODE_11G); 481 ieee80211_init_channels(ic, NULL, &bands); 482 483 ieee80211_ifattach(ic); 484 ic->ic_raw_xmit = urtwn_raw_xmit; 485 ic->ic_scan_start = urtwn_scan_start; 486 ic->ic_scan_end = urtwn_scan_end; 487 ic->ic_set_channel = urtwn_set_channel; 488 ic->ic_transmit = urtwn_transmit; 489 ic->ic_parent = urtwn_parent; 490 ic->ic_vap_create = urtwn_vap_create; 491 ic->ic_vap_delete = urtwn_vap_delete; 492 ic->ic_update_promisc = urtwn_update_promisc; 493 ic->ic_update_mcast = urtwn_update_mcast; 494 495 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 496 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 497 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 498 URTWN_RX_RADIOTAP_PRESENT); 499 500 if (bootverbose) 501 ieee80211_announce(ic); 502 503 return (0); 504 505detach: 506 urtwn_detach(self); 507 return (ENXIO); /* failure */ 508} 509 510static int 511urtwn_detach(device_t self) 512{ 513 struct urtwn_softc *sc = device_get_softc(self); 514 struct ieee80211com *ic = &sc->sc_ic; 515 unsigned int x; 516 517 /* Prevent further ioctls. */ 518 URTWN_LOCK(sc); 519 sc->sc_flags |= URTWN_DETACHED; 520 URTWN_UNLOCK(sc); 521 522 urtwn_stop(sc); 523 524 callout_drain(&sc->sc_watchdog_ch); 525 526 /* stop all USB transfers */ 527 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 528 529 /* Prevent further allocations from RX/TX data lists. */ 530 URTWN_LOCK(sc); 531 STAILQ_INIT(&sc->sc_tx_active); 532 STAILQ_INIT(&sc->sc_tx_inactive); 533 STAILQ_INIT(&sc->sc_tx_pending); 534 535 STAILQ_INIT(&sc->sc_rx_active); 536 STAILQ_INIT(&sc->sc_rx_inactive); 537 URTWN_UNLOCK(sc); 538 539 /* drain USB transfers */ 540 for (x = 0; x != URTWN_N_TRANSFER; x++) 541 usbd_transfer_drain(sc->sc_xfer[x]); 542 543 /* Free data buffers. */ 544 URTWN_LOCK(sc); 545 urtwn_free_tx_list(sc); 546 urtwn_free_rx_list(sc); 547 URTWN_UNLOCK(sc); 548 549 ieee80211_ifdetach(ic); 550 mtx_destroy(&sc->sc_mtx); 551 552 return (0); 553} 554 555static void 556urtwn_drain_mbufq(struct urtwn_softc *sc) 557{ 558 struct mbuf *m; 559 struct ieee80211_node *ni; 560 URTWN_ASSERT_LOCKED(sc); 561 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 562 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 563 m->m_pkthdr.rcvif = NULL; 564 ieee80211_free_node(ni); 565 m_freem(m); 566 } 567} 568 569static usb_error_t 570urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 571 void *data) 572{ 573 usb_error_t err; 574 int ntries = 10; 575 576 URTWN_ASSERT_LOCKED(sc); 577 578 while (ntries--) { 579 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 580 req, data, 0, NULL, 250 /* ms */); 581 if (err == 0) 582 break; 583 584 DPRINTFN(1, "Control request failed, %s (retrying)\n", 585 usbd_errstr(err)); 586 usb_pause_mtx(&sc->sc_mtx, hz / 100); 587 } 588 return (err); 589} 590 591static struct ieee80211vap * 592urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 593 enum ieee80211_opmode opmode, int flags, 594 const uint8_t bssid[IEEE80211_ADDR_LEN], 595 const uint8_t mac[IEEE80211_ADDR_LEN]) 596{ 597 struct urtwn_softc *sc = ic->ic_softc; 598 struct urtwn_vap *uvp; 599 struct ieee80211vap *vap; 600 601 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 602 return (NULL); 603 604 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 605 vap = &uvp->vap; 606 /* enable s/w bmiss handling for sta mode */ 607 608 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 609 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 610 /* out of memory */ 611 free(uvp, M_80211_VAP); 612 return (NULL); 613 } 614 615 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 616 urtwn_init_beacon(sc, uvp); 617 618 /* override state transition machine */ 619 uvp->newstate = vap->iv_newstate; 620 vap->iv_newstate = urtwn_newstate; 621 vap->iv_update_beacon = urtwn_update_beacon; 622 if (opmode == IEEE80211_M_IBSS) { 623 uvp->recv_mgmt = vap->iv_recv_mgmt; 624 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 625 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 626 } 627 628 /* complete setup */ 629 ieee80211_vap_attach(vap, ieee80211_media_change, 630 ieee80211_media_status, mac); 631 ic->ic_opmode = opmode; 632 return (vap); 633} 634 635static void 636urtwn_vap_delete(struct ieee80211vap *vap) 637{ 638 struct ieee80211com *ic = vap->iv_ic; 639 struct urtwn_vap *uvp = URTWN_VAP(vap); 640 641 if (uvp->bcn_mbuf != NULL) 642 m_freem(uvp->bcn_mbuf); 643 if (vap->iv_opmode == IEEE80211_M_IBSS) 644 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 645 ieee80211_vap_detach(vap); 646 free(uvp, M_80211_VAP); 647} 648 649static struct mbuf * 650urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 651{ 652 struct ieee80211com *ic = &sc->sc_ic; 653 struct ieee80211_frame *wh; 654 struct mbuf *m; 655 struct r92c_rx_stat *stat; 656 uint32_t rxdw0, rxdw3; 657 uint8_t rate; 658 int8_t rssi = 0; 659 int infosz; 660 661 /* 662 * don't pass packets to the ieee80211 framework if the driver isn't 663 * RUNNING. 664 */ 665 if (!(sc->sc_flags & URTWN_RUNNING)) 666 return (NULL); 667 668 stat = (struct r92c_rx_stat *)buf; 669 rxdw0 = le32toh(stat->rxdw0); 670 rxdw3 = le32toh(stat->rxdw3); 671 672 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 673 /* 674 * This should not happen since we setup our Rx filter 675 * to not receive these frames. 676 */ 677 counter_u64_add(ic->ic_ierrors, 1); 678 return (NULL); 679 } 680 if (pktlen < sizeof(struct ieee80211_frame_ack) || 681 pktlen > MCLBYTES) { 682 counter_u64_add(ic->ic_ierrors, 1); 683 return (NULL); 684 } 685 686 rate = MS(rxdw3, R92C_RXDW3_RATE); 687 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 688 689 /* Get RSSI from PHY status descriptor if present. */ 690 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 691 if (sc->chip & URTWN_CHIP_88E) 692 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 693 else 694 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 695 /* Update our average RSSI. */ 696 urtwn_update_avgrssi(sc, rate, rssi); 697 } 698 699 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 700 if (m == NULL) { 701 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 702 return (NULL); 703 } 704 705 /* Finalize mbuf. */ 706 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 707 memcpy(mtod(m, uint8_t *), wh, pktlen); 708 m->m_pkthdr.len = m->m_len = pktlen; 709 710 if (ieee80211_radiotap_active(ic)) { 711 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 712 713 tap->wr_flags = 0; 714 /* Map HW rate index to 802.11 rate. */ 715 if (!(rxdw3 & R92C_RXDW3_HT)) { 716 tap->wr_rate = ridx2rate[rate]; 717 } else if (rate >= 12) { /* MCS0~15. */ 718 /* Bit 7 set means HT MCS instead of rate. */ 719 tap->wr_rate = 0x80 | (rate - 12); 720 } 721 tap->wr_dbm_antsignal = rssi; 722 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 723 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 724 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 725 } 726 727 *rssi_p = rssi; 728 729 return (m); 730} 731 732static struct mbuf * 733urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 734 int8_t *nf) 735{ 736 struct urtwn_softc *sc = data->sc; 737 struct ieee80211com *ic = &sc->sc_ic; 738 struct r92c_rx_stat *stat; 739 struct mbuf *m, *m0 = NULL, *prevm = NULL; 740 uint32_t rxdw0; 741 uint8_t *buf; 742 int len, totlen, pktlen, infosz, npkts; 743 744 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 745 746 if (len < sizeof(*stat)) { 747 counter_u64_add(ic->ic_ierrors, 1); 748 return (NULL); 749 } 750 751 buf = data->buf; 752 /* Get the number of encapsulated frames. */ 753 stat = (struct r92c_rx_stat *)buf; 754 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 755 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 756 757 /* Process all of them. */ 758 while (npkts-- > 0) { 759 if (len < sizeof(*stat)) 760 break; 761 stat = (struct r92c_rx_stat *)buf; 762 rxdw0 = le32toh(stat->rxdw0); 763 764 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 765 if (pktlen == 0) 766 break; 767 768 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 769 770 /* Make sure everything fits in xfer. */ 771 totlen = sizeof(*stat) + infosz + pktlen; 772 if (totlen > len) 773 break; 774 775 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 776 if (m0 == NULL) 777 m0 = m; 778 if (prevm == NULL) 779 prevm = m; 780 else { 781 prevm->m_next = m; 782 prevm = m; 783 } 784 785 /* Next chunk is 128-byte aligned. */ 786 totlen = (totlen + 127) & ~127; 787 buf += totlen; 788 len -= totlen; 789 } 790 791 return (m0); 792} 793 794static void 795urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 796{ 797 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 798 struct ieee80211com *ic = &sc->sc_ic; 799 struct ieee80211_frame_min *wh; 800 struct ieee80211_node *ni; 801 struct mbuf *m = NULL, *next; 802 struct urtwn_data *data; 803 int8_t nf; 804 int rssi = 1; 805 806 URTWN_ASSERT_LOCKED(sc); 807 808 switch (USB_GET_STATE(xfer)) { 809 case USB_ST_TRANSFERRED: 810 data = STAILQ_FIRST(&sc->sc_rx_active); 811 if (data == NULL) 812 goto tr_setup; 813 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 814 m = urtwn_rxeof(xfer, data, &rssi, &nf); 815 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 816 /* FALLTHROUGH */ 817 case USB_ST_SETUP: 818tr_setup: 819 data = STAILQ_FIRST(&sc->sc_rx_inactive); 820 if (data == NULL) { 821 KASSERT(m == NULL, ("mbuf isn't NULL")); 822 return; 823 } 824 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 825 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 826 usbd_xfer_set_frame_data(xfer, 0, data->buf, 827 usbd_xfer_max_len(xfer)); 828 usbd_transfer_submit(xfer); 829 830 /* 831 * To avoid LOR we should unlock our private mutex here to call 832 * ieee80211_input() because here is at the end of a USB 833 * callback and safe to unlock. 834 */ 835 URTWN_UNLOCK(sc); 836 while (m != NULL) { 837 next = m->m_next; 838 m->m_next = NULL; 839 wh = mtod(m, struct ieee80211_frame_min *); 840 if (m->m_len >= sizeof(*wh)) 841 ni = ieee80211_find_rxnode(ic, wh); 842 else 843 ni = NULL; 844 nf = URTWN_NOISE_FLOOR; 845 if (ni != NULL) { 846 (void)ieee80211_input(ni, m, rssi - nf, nf); 847 ieee80211_free_node(ni); 848 } else { 849 (void)ieee80211_input_all(ic, m, rssi - nf, 850 nf); 851 } 852 m = next; 853 } 854 URTWN_LOCK(sc); 855 break; 856 default: 857 /* needs it to the inactive queue due to a error. */ 858 data = STAILQ_FIRST(&sc->sc_rx_active); 859 if (data != NULL) { 860 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 861 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 862 } 863 if (error != USB_ERR_CANCELLED) { 864 usbd_xfer_set_stall(xfer); 865 counter_u64_add(ic->ic_ierrors, 1); 866 goto tr_setup; 867 } 868 break; 869 } 870} 871 872static void 873urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 874{ 875 876 URTWN_ASSERT_LOCKED(sc); 877 878 if (data->ni != NULL) /* not a beacon frame */ 879 ieee80211_tx_complete(data->ni, data->m, status); 880 881 data->ni = NULL; 882 data->m = NULL; 883 884 sc->sc_txtimer = 0; 885 886 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 887} 888 889static int 890urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 891 int ndata, int maxsz) 892{ 893 int i, error; 894 895 for (i = 0; i < ndata; i++) { 896 struct urtwn_data *dp = &data[i]; 897 dp->sc = sc; 898 dp->m = NULL; 899 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 900 if (dp->buf == NULL) { 901 device_printf(sc->sc_dev, 902 "could not allocate buffer\n"); 903 error = ENOMEM; 904 goto fail; 905 } 906 dp->ni = NULL; 907 } 908 909 return (0); 910fail: 911 urtwn_free_list(sc, data, ndata); 912 return (error); 913} 914 915static int 916urtwn_alloc_rx_list(struct urtwn_softc *sc) 917{ 918 int error, i; 919 920 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 921 URTWN_RXBUFSZ); 922 if (error != 0) 923 return (error); 924 925 STAILQ_INIT(&sc->sc_rx_active); 926 STAILQ_INIT(&sc->sc_rx_inactive); 927 928 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 929 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 930 931 return (0); 932} 933 934static int 935urtwn_alloc_tx_list(struct urtwn_softc *sc) 936{ 937 int error, i; 938 939 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 940 URTWN_TXBUFSZ); 941 if (error != 0) 942 return (error); 943 944 STAILQ_INIT(&sc->sc_tx_active); 945 STAILQ_INIT(&sc->sc_tx_inactive); 946 STAILQ_INIT(&sc->sc_tx_pending); 947 948 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 949 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 950 951 return (0); 952} 953 954static void 955urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 956{ 957 int i; 958 959 for (i = 0; i < ndata; i++) { 960 struct urtwn_data *dp = &data[i]; 961 962 if (dp->buf != NULL) { 963 free(dp->buf, M_USBDEV); 964 dp->buf = NULL; 965 } 966 if (dp->ni != NULL) { 967 ieee80211_free_node(dp->ni); 968 dp->ni = NULL; 969 } 970 } 971} 972 973static void 974urtwn_free_rx_list(struct urtwn_softc *sc) 975{ 976 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 977} 978 979static void 980urtwn_free_tx_list(struct urtwn_softc *sc) 981{ 982 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 983} 984 985static void 986urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 987{ 988 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 989 struct urtwn_data *data; 990 991 URTWN_ASSERT_LOCKED(sc); 992 993 switch (USB_GET_STATE(xfer)){ 994 case USB_ST_TRANSFERRED: 995 data = STAILQ_FIRST(&sc->sc_tx_active); 996 if (data == NULL) 997 goto tr_setup; 998 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 999 urtwn_txeof(sc, data, 0); 1000 /* FALLTHROUGH */ 1001 case USB_ST_SETUP: 1002tr_setup: 1003 data = STAILQ_FIRST(&sc->sc_tx_pending); 1004 if (data == NULL) { 1005 DPRINTF("%s: empty pending queue\n", __func__); 1006 goto finish; 1007 } 1008 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1009 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1010 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1011 usbd_transfer_submit(xfer); 1012 break; 1013 default: 1014 data = STAILQ_FIRST(&sc->sc_tx_active); 1015 if (data == NULL) 1016 goto tr_setup; 1017 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1018 urtwn_txeof(sc, data, 1); 1019 if (error != USB_ERR_CANCELLED) { 1020 usbd_xfer_set_stall(xfer); 1021 goto tr_setup; 1022 } 1023 break; 1024 } 1025finish: 1026 /* Kick-start more transmit */ 1027 urtwn_start(sc); 1028} 1029 1030static struct urtwn_data * 1031_urtwn_getbuf(struct urtwn_softc *sc) 1032{ 1033 struct urtwn_data *bf; 1034 1035 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1036 if (bf != NULL) 1037 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1038 else 1039 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 1040 return (bf); 1041} 1042 1043static struct urtwn_data * 1044urtwn_getbuf(struct urtwn_softc *sc) 1045{ 1046 struct urtwn_data *bf; 1047 1048 URTWN_ASSERT_LOCKED(sc); 1049 1050 bf = _urtwn_getbuf(sc); 1051 if (bf == NULL) 1052 DPRINTF("%s: stop queue\n", __func__); 1053 return (bf); 1054} 1055 1056static usb_error_t 1057urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1058 int len) 1059{ 1060 usb_device_request_t req; 1061 1062 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1063 req.bRequest = R92C_REQ_REGS; 1064 USETW(req.wValue, addr); 1065 USETW(req.wIndex, 0); 1066 USETW(req.wLength, len); 1067 return (urtwn_do_request(sc, &req, buf)); 1068} 1069 1070static usb_error_t 1071urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1072{ 1073 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1074} 1075 1076static usb_error_t 1077urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1078{ 1079 val = htole16(val); 1080 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1081} 1082 1083static usb_error_t 1084urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1085{ 1086 val = htole32(val); 1087 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1088} 1089 1090static usb_error_t 1091urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1092 int len) 1093{ 1094 usb_device_request_t req; 1095 1096 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1097 req.bRequest = R92C_REQ_REGS; 1098 USETW(req.wValue, addr); 1099 USETW(req.wIndex, 0); 1100 USETW(req.wLength, len); 1101 return (urtwn_do_request(sc, &req, buf)); 1102} 1103 1104static uint8_t 1105urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1106{ 1107 uint8_t val; 1108 1109 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1110 return (0xff); 1111 return (val); 1112} 1113 1114static uint16_t 1115urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1116{ 1117 uint16_t val; 1118 1119 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1120 return (0xffff); 1121 return (le16toh(val)); 1122} 1123 1124static uint32_t 1125urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1126{ 1127 uint32_t val; 1128 1129 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1130 return (0xffffffff); 1131 return (le32toh(val)); 1132} 1133 1134static int 1135urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1136{ 1137 struct r92c_fw_cmd cmd; 1138 usb_error_t error; 1139 int ntries; 1140 1141 /* Wait for current FW box to be empty. */ 1142 for (ntries = 0; ntries < 100; ntries++) { 1143 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1144 break; 1145 urtwn_ms_delay(sc); 1146 } 1147 if (ntries == 100) { 1148 device_printf(sc->sc_dev, 1149 "could not send firmware command\n"); 1150 return (ETIMEDOUT); 1151 } 1152 memset(&cmd, 0, sizeof(cmd)); 1153 cmd.id = id; 1154 if (len > 3) 1155 cmd.id |= R92C_CMD_FLAG_EXT; 1156 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1157 memcpy(cmd.msg, buf, len); 1158 1159 /* Write the first word last since that will trigger the FW. */ 1160 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1161 (uint8_t *)&cmd + 4, 2); 1162 if (error != USB_ERR_NORMAL_COMPLETION) 1163 return (EIO); 1164 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1165 (uint8_t *)&cmd + 0, 4); 1166 if (error != USB_ERR_NORMAL_COMPLETION) 1167 return (EIO); 1168 1169 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1170 return (0); 1171} 1172 1173static __inline void 1174urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1175{ 1176 1177 sc->sc_rf_write(sc, chain, addr, val); 1178} 1179 1180static void 1181urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1182 uint32_t val) 1183{ 1184 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1185 SM(R92C_LSSI_PARAM_ADDR, addr) | 1186 SM(R92C_LSSI_PARAM_DATA, val)); 1187} 1188 1189static void 1190urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1191uint32_t val) 1192{ 1193 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1194 SM(R88E_LSSI_PARAM_ADDR, addr) | 1195 SM(R92C_LSSI_PARAM_DATA, val)); 1196} 1197 1198static uint32_t 1199urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1200{ 1201 uint32_t reg[R92C_MAX_CHAINS], val; 1202 1203 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1204 if (chain != 0) 1205 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1206 1207 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1208 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1209 urtwn_ms_delay(sc); 1210 1211 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1212 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1213 R92C_HSSI_PARAM2_READ_EDGE); 1214 urtwn_ms_delay(sc); 1215 1216 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1217 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1218 urtwn_ms_delay(sc); 1219 1220 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1221 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1222 else 1223 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1224 return (MS(val, R92C_LSSI_READBACK_DATA)); 1225} 1226 1227static int 1228urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1229{ 1230 usb_error_t error; 1231 int ntries; 1232 1233 error = urtwn_write_4(sc, R92C_LLT_INIT, 1234 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1235 SM(R92C_LLT_INIT_ADDR, addr) | 1236 SM(R92C_LLT_INIT_DATA, data)); 1237 if (error != USB_ERR_NORMAL_COMPLETION) 1238 return (EIO); 1239 /* Wait for write operation to complete. */ 1240 for (ntries = 0; ntries < 20; ntries++) { 1241 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1242 R92C_LLT_INIT_OP_NO_ACTIVE) 1243 return (0); 1244 urtwn_ms_delay(sc); 1245 } 1246 return (ETIMEDOUT); 1247} 1248 1249static int 1250urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1251{ 1252 uint32_t reg; 1253 usb_error_t error; 1254 int ntries; 1255 1256 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1257 return (EFAULT); 1258 1259 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1260 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1261 reg &= ~R92C_EFUSE_CTRL_VALID; 1262 1263 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1264 if (error != USB_ERR_NORMAL_COMPLETION) 1265 return (EIO); 1266 /* Wait for read operation to complete. */ 1267 for (ntries = 0; ntries < 100; ntries++) { 1268 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1269 if (reg & R92C_EFUSE_CTRL_VALID) 1270 break; 1271 urtwn_ms_delay(sc); 1272 } 1273 if (ntries == 100) { 1274 device_printf(sc->sc_dev, 1275 "could not read efuse byte at address 0x%x\n", 1276 sc->last_rom_addr); 1277 return (ETIMEDOUT); 1278 } 1279 1280 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1281 sc->last_rom_addr++; 1282 1283 return (0); 1284} 1285 1286static int 1287urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1288 uint8_t msk) 1289{ 1290 uint8_t reg; 1291 int i, error; 1292 1293 for (i = 0; i < 4; i++) { 1294 if (msk & (1 << i)) 1295 continue; 1296 error = urtwn_efuse_read_next(sc, ®); 1297 if (error != 0) 1298 return (error); 1299 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2, reg); 1300 rom[off * 8 + i * 2 + 0] = reg; 1301 1302 error = urtwn_efuse_read_next(sc, ®); 1303 if (error != 0) 1304 return (error); 1305 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2 + 1, reg); 1306 rom[off * 8 + i * 2 + 1] = reg; 1307 } 1308 1309 return (0); 1310} 1311 1312#ifdef URTWN_DEBUG 1313static void 1314urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1315{ 1316 int i; 1317 1318 /* Dump ROM contents. */ 1319 device_printf(sc->sc_dev, "%s:", __func__); 1320 for (i = 0; i < size; i++) { 1321 if (i % 32 == 0) 1322 printf("\n%03X: ", i); 1323 else if (i % 4 == 0) 1324 printf(" "); 1325 1326 printf("%02X", rom[i]); 1327 } 1328 printf("\n"); 1329} 1330#endif 1331 1332static int 1333urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1334{ 1335#define URTWN_CHK(res) do { \ 1336 if ((error = res) != 0) \ 1337 goto end; \ 1338} while(0) 1339 uint8_t msk, off, reg; 1340 int error; 1341 1342 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1343 1344 /* Read full ROM image. */ 1345 sc->last_rom_addr = 0; 1346 memset(rom, 0xff, size); 1347 1348 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1349 while (reg != 0xff) { 1350 /* check for extended header */ 1351 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1352 off = reg >> 5; 1353 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1354 1355 if ((reg & 0x0f) != 0x0f) 1356 off = ((reg & 0xf0) >> 1) | off; 1357 else 1358 continue; 1359 } else 1360 off = reg >> 4; 1361 msk = reg & 0xf; 1362 1363 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1364 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1365 } 1366 1367end: 1368 1369#ifdef URTWN_DEBUG 1370 if (urtwn_debug >= 2) 1371 urtwn_dump_rom_contents(sc, rom, size); 1372#endif 1373 1374 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1375 1376 if (error != 0) { 1377 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1378 __func__); 1379 } 1380 1381 return (error); 1382#undef URTWN_CHK 1383} 1384 1385static int 1386urtwn_efuse_switch_power(struct urtwn_softc *sc) 1387{ 1388 usb_error_t error; 1389 uint32_t reg; 1390 1391 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1392 if (error != USB_ERR_NORMAL_COMPLETION) 1393 return (EIO); 1394 1395 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1396 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1397 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1398 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1399 if (error != USB_ERR_NORMAL_COMPLETION) 1400 return (EIO); 1401 } 1402 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1403 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1404 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1405 reg | R92C_SYS_FUNC_EN_ELDR); 1406 if (error != USB_ERR_NORMAL_COMPLETION) 1407 return (EIO); 1408 } 1409 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1410 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1411 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1412 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1413 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1414 if (error != USB_ERR_NORMAL_COMPLETION) 1415 return (EIO); 1416 } 1417 1418 return (0); 1419} 1420 1421static int 1422urtwn_read_chipid(struct urtwn_softc *sc) 1423{ 1424 uint32_t reg; 1425 1426 if (sc->chip & URTWN_CHIP_88E) 1427 return (0); 1428 1429 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1430 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1431 return (EIO); 1432 1433 if (reg & R92C_SYS_CFG_TYPE_92C) { 1434 sc->chip |= URTWN_CHIP_92C; 1435 /* Check if it is a castrated 8192C. */ 1436 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1437 R92C_HPON_FSM_CHIP_BONDING_ID) == 1438 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1439 sc->chip |= URTWN_CHIP_92C_1T2R; 1440 } 1441 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1442 sc->chip |= URTWN_CHIP_UMC; 1443 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1444 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1445 } 1446 return (0); 1447} 1448 1449static int 1450urtwn_read_rom(struct urtwn_softc *sc) 1451{ 1452 struct r92c_rom *rom = &sc->rom.r92c_rom; 1453 int error; 1454 1455 /* Read full ROM image. */ 1456 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1457 if (error != 0) 1458 return (error); 1459 1460 /* XXX Weird but this is what the vendor driver does. */ 1461 sc->last_rom_addr = 0x1fa; 1462 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1463 if (error != 0) 1464 return (error); 1465 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1466 1467 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1468 1469 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1470 DPRINTF("regulatory type=%d\n", sc->regulatory); 1471 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1472 1473 sc->sc_rf_write = urtwn_r92c_rf_write; 1474 sc->sc_power_on = urtwn_r92c_power_on; 1475 1476 return (0); 1477} 1478 1479static int 1480urtwn_r88e_read_rom(struct urtwn_softc *sc) 1481{ 1482 uint8_t *rom = sc->rom.r88e_rom; 1483 uint16_t addr; 1484 int error, i; 1485 1486 error = urtwn_efuse_read(sc, rom, sizeof(sc->rom.r88e_rom)); 1487 if (error != 0) 1488 return (error); 1489 1490 addr = 0x10; 1491 for (i = 0; i < 6; i++) 1492 sc->cck_tx_pwr[i] = rom[addr++]; 1493 for (i = 0; i < 5; i++) 1494 sc->ht40_tx_pwr[i] = rom[addr++]; 1495 sc->bw20_tx_pwr_diff = (rom[addr] & 0xf0) >> 4; 1496 if (sc->bw20_tx_pwr_diff & 0x08) 1497 sc->bw20_tx_pwr_diff |= 0xf0; 1498 sc->ofdm_tx_pwr_diff = (rom[addr] & 0xf); 1499 if (sc->ofdm_tx_pwr_diff & 0x08) 1500 sc->ofdm_tx_pwr_diff |= 0xf0; 1501 sc->regulatory = MS(rom[0xc1], R92C_ROM_RF1_REGULATORY); 1502 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &rom[0xd7]); 1503 1504 sc->sc_rf_write = urtwn_r88e_rf_write; 1505 sc->sc_power_on = urtwn_r88e_power_on; 1506 1507 return (0); 1508} 1509 1510/* 1511 * Initialize rate adaptation in firmware. 1512 */ 1513static int 1514urtwn_ra_init(struct urtwn_softc *sc) 1515{ 1516 struct ieee80211com *ic = &sc->sc_ic; 1517 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1518 struct ieee80211_node *ni; 1519 struct ieee80211_rateset *rs; 1520 struct r92c_fw_cmd_macid_cfg cmd; 1521 uint32_t rates, basicrates; 1522 uint8_t mode; 1523 int maxrate, maxbasicrate, error, i, j; 1524 1525 ni = ieee80211_ref_node(vap->iv_bss); 1526 rs = &ni->ni_rates; 1527 1528 /* Get normal and basic rates mask. */ 1529 rates = basicrates = 0; 1530 maxrate = maxbasicrate = 0; 1531 for (i = 0; i < rs->rs_nrates; i++) { 1532 /* Convert 802.11 rate to HW rate index. */ 1533 for (j = 0; j < nitems(ridx2rate); j++) 1534 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1535 ridx2rate[j]) 1536 break; 1537 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1538 continue; 1539 rates |= 1 << j; 1540 if (j > maxrate) 1541 maxrate = j; 1542 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1543 basicrates |= 1 << j; 1544 if (j > maxbasicrate) 1545 maxbasicrate = j; 1546 } 1547 } 1548 if (ic->ic_curmode == IEEE80211_MODE_11B) 1549 mode = R92C_RAID_11B; 1550 else 1551 mode = R92C_RAID_11BG; 1552 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1553 mode, rates, basicrates); 1554 1555 /* Set rates mask for group addressed frames. */ 1556 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1557 cmd.mask = htole32(mode << 28 | basicrates); 1558 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1559 if (error != 0) { 1560 ieee80211_free_node(ni); 1561 device_printf(sc->sc_dev, 1562 "could not add broadcast station\n"); 1563 return (error); 1564 } 1565 /* Set initial MRR rate. */ 1566 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1567 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1568 maxbasicrate); 1569 1570 /* Set rates mask for unicast frames. */ 1571 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1572 cmd.mask = htole32(mode << 28 | rates); 1573 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1574 if (error != 0) { 1575 ieee80211_free_node(ni); 1576 device_printf(sc->sc_dev, "could not add BSS station\n"); 1577 return (error); 1578 } 1579 /* Set initial MRR rate. */ 1580 DPRINTF("maxrate=%d\n", maxrate); 1581 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1582 maxrate); 1583 1584 /* Indicate highest supported rate. */ 1585 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1586 ieee80211_free_node(ni); 1587 1588 return (0); 1589} 1590 1591static void 1592urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1593{ 1594 struct r92c_tx_desc *txd = &uvp->bcn_desc; 1595 1596 txd->txdw0 = htole32( 1597 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 1598 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1599 txd->txdw1 = htole32( 1600 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 1601 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1602 1603 if (sc->chip & URTWN_CHIP_88E) { 1604 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 1605 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 1606 } else { 1607 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 1608 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 1609 } 1610 1611 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 1612 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 1613} 1614 1615static int 1616urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 1617{ 1618 struct ieee80211vap *vap = ni->ni_vap; 1619 struct urtwn_vap *uvp = URTWN_VAP(vap); 1620 struct mbuf *m; 1621 int error; 1622 1623 URTWN_ASSERT_LOCKED(sc); 1624 1625 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 1626 return (EINVAL); 1627 1628 m = ieee80211_beacon_alloc(ni); 1629 if (m == NULL) { 1630 device_printf(sc->sc_dev, 1631 "%s: could not allocate beacon frame\n", __func__); 1632 return (ENOMEM); 1633 } 1634 1635 if (uvp->bcn_mbuf != NULL) 1636 m_freem(uvp->bcn_mbuf); 1637 1638 uvp->bcn_mbuf = m; 1639 1640 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1641 return (error); 1642 1643 /* XXX bcnq stuck workaround */ 1644 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1645 return (error); 1646 1647 return (0); 1648} 1649 1650static void 1651urtwn_update_beacon(struct ieee80211vap *vap, int item) 1652{ 1653 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1654 struct urtwn_vap *uvp = URTWN_VAP(vap); 1655 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 1656 struct ieee80211_node *ni = vap->iv_bss; 1657 int mcast = 0; 1658 1659 URTWN_LOCK(sc); 1660 if (uvp->bcn_mbuf == NULL) { 1661 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 1662 if (uvp->bcn_mbuf == NULL) { 1663 device_printf(sc->sc_dev, 1664 "%s: could not allocate beacon frame\n", __func__); 1665 URTWN_UNLOCK(sc); 1666 return; 1667 } 1668 } 1669 URTWN_UNLOCK(sc); 1670 1671 if (item == IEEE80211_BEACON_TIM) 1672 mcast = 1; /* XXX */ 1673 1674 setbit(bo->bo_flags, item); 1675 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 1676 1677 URTWN_LOCK(sc); 1678 urtwn_tx_beacon(sc, uvp); 1679 URTWN_UNLOCK(sc); 1680} 1681 1682/* 1683 * Push a beacon frame into the chip. Beacon will 1684 * be repeated by the chip every R92C_BCN_INTERVAL. 1685 */ 1686static int 1687urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1688{ 1689 struct r92c_tx_desc *desc = &uvp->bcn_desc; 1690 struct urtwn_data *bf; 1691 1692 URTWN_ASSERT_LOCKED(sc); 1693 1694 bf = urtwn_getbuf(sc); 1695 if (bf == NULL) 1696 return (ENOMEM); 1697 1698 memcpy(bf->buf, desc, sizeof(*desc)); 1699 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 1700 1701 sc->sc_txtimer = 5; 1702 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1703 1704 return (0); 1705} 1706 1707static void 1708urtwn_tsf_task_adhoc(void *arg, int pending) 1709{ 1710 struct ieee80211vap *vap = arg; 1711 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1712 struct ieee80211_node *ni; 1713 uint32_t reg; 1714 1715 URTWN_LOCK(sc); 1716 ni = ieee80211_ref_node(vap->iv_bss); 1717 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 1718 1719 /* Accept beacons with the same BSSID. */ 1720 urtwn_set_rx_bssid_all(sc, 0); 1721 1722 /* Enable synchronization. */ 1723 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 1724 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1725 1726 /* Synchronize. */ 1727 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 1728 1729 /* Disable synchronization. */ 1730 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 1731 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1732 1733 /* Remove beacon filter. */ 1734 urtwn_set_rx_bssid_all(sc, 1); 1735 1736 /* Enable beaconing. */ 1737 urtwn_write_1(sc, R92C_MBID_NUM, 1738 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 1739 reg |= R92C_BCN_CTRL_EN_BCN; 1740 1741 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1742 ieee80211_free_node(ni); 1743 URTWN_UNLOCK(sc); 1744} 1745 1746static void 1747urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 1748{ 1749 struct ieee80211com *ic = &sc->sc_ic; 1750 struct urtwn_vap *uvp = URTWN_VAP(vap); 1751 1752 /* Reset TSF. */ 1753 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 1754 1755 switch (vap->iv_opmode) { 1756 case IEEE80211_M_STA: 1757 /* Enable TSF synchronization. */ 1758 urtwn_write_1(sc, R92C_BCN_CTRL, 1759 urtwn_read_1(sc, R92C_BCN_CTRL) & 1760 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1761 break; 1762 case IEEE80211_M_IBSS: 1763 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 1764 break; 1765 case IEEE80211_M_HOSTAP: 1766 /* Enable beaconing. */ 1767 urtwn_write_1(sc, R92C_MBID_NUM, 1768 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 1769 urtwn_write_1(sc, R92C_BCN_CTRL, 1770 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1771 break; 1772 default: 1773 device_printf(sc->sc_dev, "undefined opmode %d\n", 1774 vap->iv_opmode); 1775 return; 1776 } 1777} 1778 1779static void 1780urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1781{ 1782 uint8_t reg; 1783 1784 if (led == URTWN_LED_LINK) { 1785 if (sc->chip & URTWN_CHIP_88E) { 1786 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1787 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1788 if (!on) { 1789 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1790 urtwn_write_1(sc, R92C_LEDCFG2, 1791 reg | R92C_LEDCFG0_DIS); 1792 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1793 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1794 0xfe); 1795 } 1796 } else { 1797 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1798 if (!on) 1799 reg |= R92C_LEDCFG0_DIS; 1800 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1801 } 1802 sc->ledlink = on; /* Save LED state. */ 1803 } 1804} 1805 1806static void 1807urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 1808{ 1809 uint8_t reg; 1810 1811 reg = urtwn_read_1(sc, R92C_MSR); 1812 reg = (reg & ~R92C_MSR_MASK) | mode; 1813 urtwn_write_1(sc, R92C_MSR, reg); 1814} 1815 1816static void 1817urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 1818 const struct ieee80211_rx_stats *rxs, 1819 int rssi, int nf) 1820{ 1821 struct ieee80211vap *vap = ni->ni_vap; 1822 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1823 struct urtwn_vap *uvp = URTWN_VAP(vap); 1824 uint64_t ni_tstamp, curr_tstamp; 1825 1826 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 1827 1828 if (vap->iv_state == IEEE80211_S_RUN && 1829 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 1830 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 1831 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 1832#ifdef D3831 1833 URTWN_LOCK(sc); 1834 urtwn_get_tsf(sc, &curr_tstamp); 1835 URTWN_UNLOCK(sc); 1836 curr_tstamp = le64toh(curr_tstamp); 1837 1838 if (ni_tstamp >= curr_tstamp) 1839 (void) ieee80211_ibss_merge(ni); 1840#else 1841 (void) sc; 1842 (void) curr_tstamp; 1843#endif 1844 } 1845} 1846 1847static int 1848urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1849{ 1850 struct urtwn_vap *uvp = URTWN_VAP(vap); 1851 struct ieee80211com *ic = vap->iv_ic; 1852 struct urtwn_softc *sc = ic->ic_softc; 1853 struct ieee80211_node *ni; 1854 enum ieee80211_state ostate; 1855 uint32_t reg; 1856 uint8_t mode; 1857 int error = 0; 1858 1859 ostate = vap->iv_state; 1860 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1861 ieee80211_state_name[nstate]); 1862 1863 IEEE80211_UNLOCK(ic); 1864 URTWN_LOCK(sc); 1865 callout_stop(&sc->sc_watchdog_ch); 1866 1867 if (ostate == IEEE80211_S_RUN) { 1868 /* Turn link LED off. */ 1869 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1870 1871 /* Set media status to 'No Link'. */ 1872 urtwn_set_mode(sc, R92C_MSR_NOLINK); 1873 1874 /* Stop Rx of data frames. */ 1875 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1876 1877 /* Disable TSF synchronization. */ 1878 urtwn_write_1(sc, R92C_BCN_CTRL, 1879 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 1880 R92C_BCN_CTRL_DIS_TSF_UDT0); 1881 1882 /* Disable beaconing. */ 1883 urtwn_write_1(sc, R92C_MBID_NUM, 1884 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 1885 1886 /* Reset TSF. */ 1887 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 1888 1889 /* Reset EDCA parameters. */ 1890 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1891 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1892 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1893 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1894 } 1895 1896 switch (nstate) { 1897 case IEEE80211_S_INIT: 1898 /* Turn link LED off. */ 1899 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1900 break; 1901 case IEEE80211_S_SCAN: 1902 /* Pause AC Tx queues. */ 1903 urtwn_write_1(sc, R92C_TXPAUSE, 1904 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1905 break; 1906 case IEEE80211_S_AUTH: 1907 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1908 break; 1909 case IEEE80211_S_RUN: 1910 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1911 /* Turn link LED on. */ 1912 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1913 break; 1914 } 1915 1916 ni = ieee80211_ref_node(vap->iv_bss); 1917 1918 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 1919 ni->ni_chan == IEEE80211_CHAN_ANYC) { 1920 device_printf(sc->sc_dev, 1921 "%s: could not move to RUN state\n", __func__); 1922 error = EINVAL; 1923 goto end_run; 1924 } 1925 1926 switch (vap->iv_opmode) { 1927 case IEEE80211_M_STA: 1928 mode = R92C_MSR_INFRA; 1929 break; 1930 case IEEE80211_M_IBSS: 1931 mode = R92C_MSR_ADHOC; 1932 break; 1933 case IEEE80211_M_HOSTAP: 1934 mode = R92C_MSR_AP; 1935 break; 1936 default: 1937 device_printf(sc->sc_dev, "undefined opmode %d\n", 1938 vap->iv_opmode); 1939 error = EINVAL; 1940 goto end_run; 1941 } 1942 1943 /* Set media status to 'Associated'. */ 1944 urtwn_set_mode(sc, mode); 1945 1946 /* Set BSSID. */ 1947 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1948 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1949 1950 if (ic->ic_curmode == IEEE80211_MODE_11B) 1951 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1952 else /* 802.11b/g */ 1953 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1954 1955 /* Enable Rx of data frames. */ 1956 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1957 1958 /* Flush all AC queues. */ 1959 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1960 1961 /* Set beacon interval. */ 1962 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1963 1964 /* Allow Rx from our BSSID only. */ 1965 if (ic->ic_promisc == 0) { 1966 reg = urtwn_read_4(sc, R92C_RCR); 1967 1968 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 1969 reg |= R92C_RCR_CBSSID_DATA; 1970 if (vap->iv_opmode != IEEE80211_M_IBSS) 1971 reg |= R92C_RCR_CBSSID_BCN; 1972 1973 urtwn_write_4(sc, R92C_RCR, reg); 1974 } 1975 1976 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1977 vap->iv_opmode == IEEE80211_M_IBSS) { 1978 error = urtwn_setup_beacon(sc, ni); 1979 if (error != 0) { 1980 device_printf(sc->sc_dev, 1981 "unable to push beacon into the chip, " 1982 "error %d\n", error); 1983 goto end_run; 1984 } 1985 } 1986 1987 /* Enable TSF synchronization. */ 1988 urtwn_tsf_sync_enable(sc, vap); 1989 1990 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1991 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1992 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1993 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1994 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1995 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1996 1997 /* Intialize rate adaptation. */ 1998 if (sc->chip & URTWN_CHIP_88E) 1999 ni->ni_txrate = 2000 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 2001 else 2002 urtwn_ra_init(sc); 2003 /* Turn link LED on. */ 2004 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2005 2006 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2007 /* Reset temperature calibration state machine. */ 2008 sc->thcal_state = 0; 2009 sc->thcal_lctemp = 0; 2010 2011end_run: 2012 ieee80211_free_node(ni); 2013 break; 2014 default: 2015 break; 2016 } 2017 2018 URTWN_UNLOCK(sc); 2019 IEEE80211_LOCK(ic); 2020 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2021} 2022 2023static void 2024urtwn_watchdog(void *arg) 2025{ 2026 struct urtwn_softc *sc = arg; 2027 2028 if (sc->sc_txtimer > 0) { 2029 if (--sc->sc_txtimer == 0) { 2030 device_printf(sc->sc_dev, "device timeout\n"); 2031 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2032 return; 2033 } 2034 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2035 } 2036} 2037 2038static void 2039urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2040{ 2041 int pwdb; 2042 2043 /* Convert antenna signal to percentage. */ 2044 if (rssi <= -100 || rssi >= 20) 2045 pwdb = 0; 2046 else if (rssi >= 0) 2047 pwdb = 100; 2048 else 2049 pwdb = 100 + rssi; 2050 if (!(sc->chip & URTWN_CHIP_88E)) { 2051 if (rate <= URTWN_RIDX_CCK11) { 2052 /* CCK gain is smaller than OFDM/MCS gain. */ 2053 pwdb += 6; 2054 if (pwdb > 100) 2055 pwdb = 100; 2056 if (pwdb <= 14) 2057 pwdb -= 4; 2058 else if (pwdb <= 26) 2059 pwdb -= 8; 2060 else if (pwdb <= 34) 2061 pwdb -= 6; 2062 else if (pwdb <= 42) 2063 pwdb -= 2; 2064 } 2065 } 2066 if (sc->avg_pwdb == -1) /* Init. */ 2067 sc->avg_pwdb = pwdb; 2068 else if (sc->avg_pwdb < pwdb) 2069 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2070 else 2071 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2072 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 2073} 2074 2075static int8_t 2076urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2077{ 2078 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2079 struct r92c_rx_phystat *phy; 2080 struct r92c_rx_cck *cck; 2081 uint8_t rpt; 2082 int8_t rssi; 2083 2084 if (rate <= URTWN_RIDX_CCK11) { 2085 cck = (struct r92c_rx_cck *)physt; 2086 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2087 rpt = (cck->agc_rpt >> 5) & 0x3; 2088 rssi = (cck->agc_rpt & 0x1f) << 1; 2089 } else { 2090 rpt = (cck->agc_rpt >> 6) & 0x3; 2091 rssi = cck->agc_rpt & 0x3e; 2092 } 2093 rssi = cckoff[rpt] - rssi; 2094 } else { /* OFDM/HT. */ 2095 phy = (struct r92c_rx_phystat *)physt; 2096 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2097 } 2098 return (rssi); 2099} 2100 2101static int8_t 2102urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2103{ 2104 struct r92c_rx_phystat *phy; 2105 struct r88e_rx_cck *cck; 2106 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2107 int8_t rssi; 2108 2109 rssi = 0; 2110 if (rate <= URTWN_RIDX_CCK11) { 2111 cck = (struct r88e_rx_cck *)physt; 2112 cck_agc_rpt = cck->agc_rpt; 2113 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2114 vga_idx = cck_agc_rpt & 0x1f; 2115 switch (lna_idx) { 2116 case 7: 2117 if (vga_idx <= 27) 2118 rssi = -100 + 2* (27 - vga_idx); 2119 else 2120 rssi = -100; 2121 break; 2122 case 6: 2123 rssi = -48 + 2 * (2 - vga_idx); 2124 break; 2125 case 5: 2126 rssi = -42 + 2 * (7 - vga_idx); 2127 break; 2128 case 4: 2129 rssi = -36 + 2 * (7 - vga_idx); 2130 break; 2131 case 3: 2132 rssi = -24 + 2 * (7 - vga_idx); 2133 break; 2134 case 2: 2135 rssi = -12 + 2 * (5 - vga_idx); 2136 break; 2137 case 1: 2138 rssi = 8 - (2 * vga_idx); 2139 break; 2140 case 0: 2141 rssi = 14 - (2 * vga_idx); 2142 break; 2143 } 2144 rssi += 6; 2145 } else { /* OFDM/HT. */ 2146 phy = (struct r92c_rx_phystat *)physt; 2147 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2148 } 2149 return (rssi); 2150} 2151 2152static int 2153urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2154 struct mbuf *m, struct urtwn_data *data) 2155{ 2156 struct ieee80211_frame *wh; 2157 struct ieee80211_key *k = NULL; 2158 struct ieee80211com *ic = &sc->sc_ic; 2159 struct ieee80211vap *vap = ni->ni_vap; 2160 struct r92c_tx_desc *txd; 2161 uint8_t macid, raid, ridx, subtype, type, qsel; 2162 int ismcast; 2163 2164 URTWN_ASSERT_LOCKED(sc); 2165 2166 /* 2167 * Software crypto. 2168 */ 2169 wh = mtod(m, struct ieee80211_frame *); 2170 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2171 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2172 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2173 2174 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2175 k = ieee80211_crypto_encap(ni, m); 2176 if (k == NULL) { 2177 device_printf(sc->sc_dev, 2178 "ieee80211_crypto_encap returns NULL.\n"); 2179 return (ENOBUFS); 2180 } 2181 2182 /* in case packet header moved, reset pointer */ 2183 wh = mtod(m, struct ieee80211_frame *); 2184 } 2185 2186 /* Fill Tx descriptor. */ 2187 txd = (struct r92c_tx_desc *)data->buf; 2188 memset(txd, 0, sizeof(*txd)); 2189 2190 txd->txdw0 |= htole32( 2191 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2192 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2193 if (ismcast) 2194 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2195 2196 raid = R92C_RAID_11B; /* by default */ 2197 ridx = URTWN_RIDX_CCK1; 2198 if (!ismcast) { 2199 macid = URTWN_MACID_BSS; 2200 2201 if (type == IEEE80211_FC0_TYPE_DATA) { 2202 qsel = R92C_TXDW1_QSEL_BE; 2203 2204 if (!(m->m_flags & M_EAPOL)) { 2205 if (ic->ic_curmode != IEEE80211_MODE_11B) { 2206 raid = R92C_RAID_11BG; 2207 ridx = URTWN_RIDX_OFDM54; 2208 } else 2209 ridx = URTWN_RIDX_CCK11; 2210 } 2211 2212 if (sc->chip & URTWN_CHIP_88E) 2213 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2214 else 2215 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2216 2217 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2218 switch (ic->ic_protmode) { 2219 case IEEE80211_PROT_CTSONLY: 2220 txd->txdw4 |= htole32( 2221 R92C_TXDW4_CTS2SELF | 2222 R92C_TXDW4_HWRTSEN); 2223 break; 2224 case IEEE80211_PROT_RTSCTS: 2225 txd->txdw4 |= htole32( 2226 R92C_TXDW4_RTSEN | 2227 R92C_TXDW4_HWRTSEN); 2228 break; 2229 default: 2230 break; 2231 } 2232 } 2233 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2234 URTWN_RIDX_OFDM24)); 2235 txd->txdw5 |= htole32(0x0001ff00); 2236 } else /* IEEE80211_FC0_TYPE_MGT */ 2237 qsel = R92C_TXDW1_QSEL_MGNT; 2238 } else { 2239 macid = URTWN_MACID_BC; 2240 qsel = R92C_TXDW1_QSEL_MGNT; 2241 } 2242 2243 txd->txdw1 |= htole32( 2244 SM(R92C_TXDW1_QSEL, qsel) | 2245 SM(R92C_TXDW1_RAID, raid)); 2246 2247 if (sc->chip & URTWN_CHIP_88E) 2248 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 2249 else 2250 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 2251 2252 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2253 /* Force this rate if needed. */ 2254 if (ismcast || type != IEEE80211_FC0_TYPE_DATA || 2255 (m->m_flags & M_EAPOL)) 2256 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2257 2258 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 2259 /* Use HW sequence numbering for non-QoS frames. */ 2260 if (sc->chip & URTWN_CHIP_88E) 2261 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2262 else 2263 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2264 } else { 2265 /* Set sequence number. */ 2266 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2267 } 2268 2269 if (ieee80211_radiotap_active_vap(vap)) { 2270 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2271 2272 tap->wt_flags = 0; 2273 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2274 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2275 if (k != NULL) 2276 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2277 ieee80211_radiotap_tx(vap, m); 2278 } 2279 2280 data->ni = ni; 2281 2282 urtwn_tx_start(sc, m, type, data); 2283 2284 return (0); 2285} 2286 2287static void 2288urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 2289 struct urtwn_data *data) 2290{ 2291 struct usb_xfer *xfer; 2292 struct r92c_tx_desc *txd; 2293 uint16_t ac, sum; 2294 int i, xferlen; 2295 struct usb_xfer *urtwn_pipes[WME_NUM_AC] = { 2296 sc->sc_xfer[URTWN_BULK_TX_BE], 2297 sc->sc_xfer[URTWN_BULK_TX_BK], 2298 sc->sc_xfer[URTWN_BULK_TX_VI], 2299 sc->sc_xfer[URTWN_BULK_TX_VO] 2300 }; 2301 2302 URTWN_ASSERT_LOCKED(sc); 2303 2304 ac = M_WME_GETAC(m); 2305 2306 switch (type) { 2307 case IEEE80211_FC0_TYPE_CTL: 2308 case IEEE80211_FC0_TYPE_MGT: 2309 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 2310 break; 2311 default: 2312 xfer = urtwn_pipes[ac]; 2313 break; 2314 } 2315 2316 txd = (struct r92c_tx_desc *)data->buf; 2317 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 2318 2319 /* Compute Tx descriptor checksum. */ 2320 sum = 0; 2321 for (i = 0; i < sizeof(*txd) / 2; i++) 2322 sum ^= ((uint16_t *)txd)[i]; 2323 txd->txdsum = sum; /* NB: already little endian. */ 2324 2325 xferlen = sizeof(*txd) + m->m_pkthdr.len; 2326 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 2327 2328 data->buflen = xferlen; 2329 data->m = m; 2330 2331 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 2332 usbd_transfer_start(xfer); 2333} 2334 2335static int 2336urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 2337{ 2338 struct urtwn_softc *sc = ic->ic_softc; 2339 int error; 2340 2341 URTWN_LOCK(sc); 2342 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2343 URTWN_UNLOCK(sc); 2344 return (ENXIO); 2345 } 2346 error = mbufq_enqueue(&sc->sc_snd, m); 2347 if (error) { 2348 URTWN_UNLOCK(sc); 2349 return (error); 2350 } 2351 urtwn_start(sc); 2352 URTWN_UNLOCK(sc); 2353 2354 return (0); 2355} 2356 2357static void 2358urtwn_start(struct urtwn_softc *sc) 2359{ 2360 struct ieee80211_node *ni; 2361 struct mbuf *m; 2362 struct urtwn_data *bf; 2363 2364 URTWN_ASSERT_LOCKED(sc); 2365 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2366 bf = urtwn_getbuf(sc); 2367 if (bf == NULL) { 2368 mbufq_prepend(&sc->sc_snd, m); 2369 break; 2370 } 2371 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2372 m->m_pkthdr.rcvif = NULL; 2373 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 2374 if_inc_counter(ni->ni_vap->iv_ifp, 2375 IFCOUNTER_OERRORS, 1); 2376 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2377 m_freem(m); 2378 ieee80211_free_node(ni); 2379 break; 2380 } 2381 sc->sc_txtimer = 5; 2382 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2383 } 2384} 2385 2386static void 2387urtwn_parent(struct ieee80211com *ic) 2388{ 2389 struct urtwn_softc *sc = ic->ic_softc; 2390 2391 URTWN_LOCK(sc); 2392 if (sc->sc_flags & URTWN_DETACHED) { 2393 URTWN_UNLOCK(sc); 2394 return; 2395 } 2396 URTWN_UNLOCK(sc); 2397 2398 if (ic->ic_nrunning > 0) { 2399 if (urtwn_init(sc) != 0) { 2400 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2401 if (vap != NULL) 2402 ieee80211_stop(vap); 2403 } else 2404 ieee80211_start_all(ic); 2405 } else 2406 urtwn_stop(sc); 2407} 2408 2409static __inline int 2410urtwn_power_on(struct urtwn_softc *sc) 2411{ 2412 2413 return sc->sc_power_on(sc); 2414} 2415 2416static int 2417urtwn_r92c_power_on(struct urtwn_softc *sc) 2418{ 2419 uint32_t reg; 2420 usb_error_t error; 2421 int ntries; 2422 2423 /* Wait for autoload done bit. */ 2424 for (ntries = 0; ntries < 1000; ntries++) { 2425 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2426 break; 2427 urtwn_ms_delay(sc); 2428 } 2429 if (ntries == 1000) { 2430 device_printf(sc->sc_dev, 2431 "timeout waiting for chip autoload\n"); 2432 return (ETIMEDOUT); 2433 } 2434 2435 /* Unlock ISO/CLK/Power control register. */ 2436 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2437 if (error != USB_ERR_NORMAL_COMPLETION) 2438 return (EIO); 2439 /* Move SPS into PWM mode. */ 2440 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2441 if (error != USB_ERR_NORMAL_COMPLETION) 2442 return (EIO); 2443 urtwn_ms_delay(sc); 2444 2445 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2446 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2447 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2448 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2449 if (error != USB_ERR_NORMAL_COMPLETION) 2450 return (EIO); 2451 urtwn_ms_delay(sc); 2452 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2453 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2454 ~R92C_SYS_ISO_CTRL_MD2PP); 2455 if (error != USB_ERR_NORMAL_COMPLETION) 2456 return (EIO); 2457 } 2458 2459 /* Auto enable WLAN. */ 2460 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2461 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2462 if (error != USB_ERR_NORMAL_COMPLETION) 2463 return (EIO); 2464 for (ntries = 0; ntries < 1000; ntries++) { 2465 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2466 R92C_APS_FSMCO_APFM_ONMAC)) 2467 break; 2468 urtwn_ms_delay(sc); 2469 } 2470 if (ntries == 1000) { 2471 device_printf(sc->sc_dev, 2472 "timeout waiting for MAC auto ON\n"); 2473 return (ETIMEDOUT); 2474 } 2475 2476 /* Enable radio, GPIO and LED functions. */ 2477 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2478 R92C_APS_FSMCO_AFSM_HSUS | 2479 R92C_APS_FSMCO_PDN_EN | 2480 R92C_APS_FSMCO_PFM_ALDN); 2481 if (error != USB_ERR_NORMAL_COMPLETION) 2482 return (EIO); 2483 /* Release RF digital isolation. */ 2484 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2485 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2486 if (error != USB_ERR_NORMAL_COMPLETION) 2487 return (EIO); 2488 2489 /* Initialize MAC. */ 2490 error = urtwn_write_1(sc, R92C_APSD_CTRL, 2491 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2492 if (error != USB_ERR_NORMAL_COMPLETION) 2493 return (EIO); 2494 for (ntries = 0; ntries < 200; ntries++) { 2495 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2496 R92C_APSD_CTRL_OFF_STATUS)) 2497 break; 2498 urtwn_ms_delay(sc); 2499 } 2500 if (ntries == 200) { 2501 device_printf(sc->sc_dev, 2502 "timeout waiting for MAC initialization\n"); 2503 return (ETIMEDOUT); 2504 } 2505 2506 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2507 reg = urtwn_read_2(sc, R92C_CR); 2508 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2509 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2510 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2511 R92C_CR_ENSEC; 2512 error = urtwn_write_2(sc, R92C_CR, reg); 2513 if (error != USB_ERR_NORMAL_COMPLETION) 2514 return (EIO); 2515 2516 error = urtwn_write_1(sc, 0xfe10, 0x19); 2517 if (error != USB_ERR_NORMAL_COMPLETION) 2518 return (EIO); 2519 return (0); 2520} 2521 2522static int 2523urtwn_r88e_power_on(struct urtwn_softc *sc) 2524{ 2525 uint32_t reg; 2526 usb_error_t error; 2527 int ntries; 2528 2529 /* Wait for power ready bit. */ 2530 for (ntries = 0; ntries < 5000; ntries++) { 2531 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2532 break; 2533 urtwn_ms_delay(sc); 2534 } 2535 if (ntries == 5000) { 2536 device_printf(sc->sc_dev, 2537 "timeout waiting for chip power up\n"); 2538 return (ETIMEDOUT); 2539 } 2540 2541 /* Reset BB. */ 2542 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2543 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2544 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2545 if (error != USB_ERR_NORMAL_COMPLETION) 2546 return (EIO); 2547 2548 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2549 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2550 if (error != USB_ERR_NORMAL_COMPLETION) 2551 return (EIO); 2552 2553 /* Disable HWPDN. */ 2554 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2555 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2556 if (error != USB_ERR_NORMAL_COMPLETION) 2557 return (EIO); 2558 2559 /* Disable WL suspend. */ 2560 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2561 urtwn_read_2(sc, R92C_APS_FSMCO) & 2562 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2563 if (error != USB_ERR_NORMAL_COMPLETION) 2564 return (EIO); 2565 2566 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2567 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2568 if (error != USB_ERR_NORMAL_COMPLETION) 2569 return (EIO); 2570 for (ntries = 0; ntries < 5000; ntries++) { 2571 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2572 R92C_APS_FSMCO_APFM_ONMAC)) 2573 break; 2574 urtwn_ms_delay(sc); 2575 } 2576 if (ntries == 5000) 2577 return (ETIMEDOUT); 2578 2579 /* Enable LDO normal mode. */ 2580 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 2581 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2582 if (error != USB_ERR_NORMAL_COMPLETION) 2583 return (EIO); 2584 2585 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2586 error = urtwn_write_2(sc, R92C_CR, 0); 2587 if (error != USB_ERR_NORMAL_COMPLETION) 2588 return (EIO); 2589 reg = urtwn_read_2(sc, R92C_CR); 2590 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2591 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2592 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2593 error = urtwn_write_2(sc, R92C_CR, reg); 2594 if (error != USB_ERR_NORMAL_COMPLETION) 2595 return (EIO); 2596 2597 return (0); 2598} 2599 2600static int 2601urtwn_llt_init(struct urtwn_softc *sc) 2602{ 2603 int i, error, page_count, pktbuf_count; 2604 2605 page_count = (sc->chip & URTWN_CHIP_88E) ? 2606 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2607 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2608 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2609 2610 /* Reserve pages [0; page_count]. */ 2611 for (i = 0; i < page_count; i++) { 2612 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2613 return (error); 2614 } 2615 /* NB: 0xff indicates end-of-list. */ 2616 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2617 return (error); 2618 /* 2619 * Use pages [page_count + 1; pktbuf_count - 1] 2620 * as ring buffer. 2621 */ 2622 for (++i; i < pktbuf_count - 1; i++) { 2623 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2624 return (error); 2625 } 2626 /* Make the last page point to the beginning of the ring buffer. */ 2627 error = urtwn_llt_write(sc, i, page_count + 1); 2628 return (error); 2629} 2630 2631static void 2632urtwn_fw_reset(struct urtwn_softc *sc) 2633{ 2634 uint16_t reg; 2635 int ntries; 2636 2637 /* Tell 8051 to reset itself. */ 2638 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2639 2640 /* Wait until 8051 resets by itself. */ 2641 for (ntries = 0; ntries < 100; ntries++) { 2642 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2643 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2644 return; 2645 urtwn_ms_delay(sc); 2646 } 2647 /* Force 8051 reset. */ 2648 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2649} 2650 2651static void 2652urtwn_r88e_fw_reset(struct urtwn_softc *sc) 2653{ 2654 uint16_t reg; 2655 2656 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2657 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2658 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2659} 2660 2661static int 2662urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2663{ 2664 uint32_t reg; 2665 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 2666 int off, mlen; 2667 2668 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2669 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2670 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2671 2672 off = R92C_FW_START_ADDR; 2673 while (len > 0) { 2674 if (len > 196) 2675 mlen = 196; 2676 else if (len > 4) 2677 mlen = 4; 2678 else 2679 mlen = 1; 2680 /* XXX fix this deconst */ 2681 error = urtwn_write_region_1(sc, off, 2682 __DECONST(uint8_t *, buf), mlen); 2683 if (error != USB_ERR_NORMAL_COMPLETION) 2684 break; 2685 off += mlen; 2686 buf += mlen; 2687 len -= mlen; 2688 } 2689 return (error); 2690} 2691 2692static int 2693urtwn_load_firmware(struct urtwn_softc *sc) 2694{ 2695 const struct firmware *fw; 2696 const struct r92c_fw_hdr *hdr; 2697 const char *imagename; 2698 const u_char *ptr; 2699 size_t len; 2700 uint32_t reg; 2701 int mlen, ntries, page, error; 2702 2703 URTWN_UNLOCK(sc); 2704 /* Read firmware image from the filesystem. */ 2705 if (sc->chip & URTWN_CHIP_88E) 2706 imagename = "urtwn-rtl8188eufw"; 2707 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2708 URTWN_CHIP_UMC_A_CUT) 2709 imagename = "urtwn-rtl8192cfwU"; 2710 else 2711 imagename = "urtwn-rtl8192cfwT"; 2712 2713 fw = firmware_get(imagename); 2714 URTWN_LOCK(sc); 2715 if (fw == NULL) { 2716 device_printf(sc->sc_dev, 2717 "failed loadfirmware of file %s\n", imagename); 2718 return (ENOENT); 2719 } 2720 2721 len = fw->datasize; 2722 2723 if (len < sizeof(*hdr)) { 2724 device_printf(sc->sc_dev, "firmware too short\n"); 2725 error = EINVAL; 2726 goto fail; 2727 } 2728 ptr = fw->data; 2729 hdr = (const struct r92c_fw_hdr *)ptr; 2730 /* Check if there is a valid FW header and skip it. */ 2731 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2732 (le16toh(hdr->signature) >> 4) == 0x88e || 2733 (le16toh(hdr->signature) >> 4) == 0x92c) { 2734 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2735 le16toh(hdr->version), le16toh(hdr->subversion), 2736 hdr->month, hdr->date, hdr->hour, hdr->minute); 2737 ptr += sizeof(*hdr); 2738 len -= sizeof(*hdr); 2739 } 2740 2741 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2742 if (sc->chip & URTWN_CHIP_88E) 2743 urtwn_r88e_fw_reset(sc); 2744 else 2745 urtwn_fw_reset(sc); 2746 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2747 } 2748 2749 if (!(sc->chip & URTWN_CHIP_88E)) { 2750 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2751 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2752 R92C_SYS_FUNC_EN_CPUEN); 2753 } 2754 urtwn_write_1(sc, R92C_MCUFWDL, 2755 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2756 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2757 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2758 2759 /* Reset the FWDL checksum. */ 2760 urtwn_write_1(sc, R92C_MCUFWDL, 2761 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2762 2763 for (page = 0; len > 0; page++) { 2764 mlen = min(len, R92C_FW_PAGE_SIZE); 2765 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2766 if (error != 0) { 2767 device_printf(sc->sc_dev, 2768 "could not load firmware page\n"); 2769 goto fail; 2770 } 2771 ptr += mlen; 2772 len -= mlen; 2773 } 2774 urtwn_write_1(sc, R92C_MCUFWDL, 2775 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2776 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2777 2778 /* Wait for checksum report. */ 2779 for (ntries = 0; ntries < 1000; ntries++) { 2780 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2781 break; 2782 urtwn_ms_delay(sc); 2783 } 2784 if (ntries == 1000) { 2785 device_printf(sc->sc_dev, 2786 "timeout waiting for checksum report\n"); 2787 error = ETIMEDOUT; 2788 goto fail; 2789 } 2790 2791 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2792 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2793 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2794 if (sc->chip & URTWN_CHIP_88E) 2795 urtwn_r88e_fw_reset(sc); 2796 /* Wait for firmware readiness. */ 2797 for (ntries = 0; ntries < 1000; ntries++) { 2798 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2799 break; 2800 urtwn_ms_delay(sc); 2801 } 2802 if (ntries == 1000) { 2803 device_printf(sc->sc_dev, 2804 "timeout waiting for firmware readiness\n"); 2805 error = ETIMEDOUT; 2806 goto fail; 2807 } 2808fail: 2809 firmware_put(fw, FIRMWARE_UNLOAD); 2810 return (error); 2811} 2812 2813static int 2814urtwn_dma_init(struct urtwn_softc *sc) 2815{ 2816 struct usb_endpoint *ep, *ep_end; 2817 usb_error_t usb_err; 2818 uint32_t reg; 2819 int hashq, hasnq, haslq, nqueues, ntx; 2820 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 2821 2822 /* Initialize LLT table. */ 2823 error = urtwn_llt_init(sc); 2824 if (error != 0) 2825 return (error); 2826 2827 /* Determine the number of bulk-out pipes. */ 2828 ntx = 0; 2829 ep = sc->sc_udev->endpoints; 2830 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 2831 for (; ep != ep_end; ep++) { 2832 if ((ep->edesc == NULL) || 2833 (ep->iface_index != sc->sc_iface_index)) 2834 continue; 2835 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 2836 ntx++; 2837 } 2838 if (ntx == 0) { 2839 device_printf(sc->sc_dev, 2840 "%d: invalid number of Tx bulk pipes\n", ntx); 2841 return (EIO); 2842 } 2843 2844 /* Get Tx queues to USB endpoints mapping. */ 2845 hashq = hasnq = haslq = nqueues = 0; 2846 switch (ntx) { 2847 case 1: hashq = 1; break; 2848 case 2: hashq = hasnq = 1; break; 2849 case 3: case 4: hashq = hasnq = haslq = 1; break; 2850 } 2851 nqueues = hashq + hasnq + haslq; 2852 if (nqueues == 0) 2853 return (EIO); 2854 2855 npubqpages = nqpages = nrempages = pagecount = 0; 2856 if (sc->chip & URTWN_CHIP_88E) 2857 tx_boundary = R88E_TX_PAGE_BOUNDARY; 2858 else { 2859 pagecount = R92C_TX_PAGE_COUNT; 2860 npubqpages = R92C_PUBQ_NPAGES; 2861 tx_boundary = R92C_TX_PAGE_BOUNDARY; 2862 } 2863 2864 /* Set number of pages for normal priority queue. */ 2865 if (sc->chip & URTWN_CHIP_88E) { 2866 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 2867 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2868 return (EIO); 2869 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2870 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2871 return (EIO); 2872 } else { 2873 /* Get the number of pages for each queue. */ 2874 nqpages = (pagecount - npubqpages) / nqueues; 2875 /* 2876 * The remaining pages are assigned to the high priority 2877 * queue. 2878 */ 2879 nrempages = (pagecount - npubqpages) % nqueues; 2880 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2881 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2882 return (EIO); 2883 usb_err = urtwn_write_4(sc, R92C_RQPN, 2884 /* Set number of pages for public queue. */ 2885 SM(R92C_RQPN_PUBQ, npubqpages) | 2886 /* Set number of pages for high priority queue. */ 2887 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2888 /* Set number of pages for low priority queue. */ 2889 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2890 /* Load values. */ 2891 R92C_RQPN_LD); 2892 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2893 return (EIO); 2894 } 2895 2896 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 2897 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2898 return (EIO); 2899 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 2900 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2901 return (EIO); 2902 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 2903 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2904 return (EIO); 2905 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 2906 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2907 return (EIO); 2908 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 2909 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2910 return (EIO); 2911 2912 /* Set queue to USB pipe mapping. */ 2913 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2914 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2915 if (nqueues == 1) { 2916 if (hashq) 2917 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2918 else if (hasnq) 2919 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2920 else 2921 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2922 } else if (nqueues == 2) { 2923 /* All 2-endpoints configs have a high priority queue. */ 2924 if (!hashq) 2925 return (EIO); 2926 if (hasnq) 2927 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2928 else 2929 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2930 } else 2931 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2932 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2933 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2934 return (EIO); 2935 2936 /* Set Tx/Rx transfer page boundary. */ 2937 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 2938 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 2939 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2940 return (EIO); 2941 2942 /* Set Tx/Rx transfer page size. */ 2943 usb_err = urtwn_write_1(sc, R92C_PBP, 2944 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2945 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2946 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2947 return (EIO); 2948 2949 return (0); 2950} 2951 2952static int 2953urtwn_mac_init(struct urtwn_softc *sc) 2954{ 2955 usb_error_t error; 2956 int i; 2957 2958 /* Write MAC initialization values. */ 2959 if (sc->chip & URTWN_CHIP_88E) { 2960 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2961 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2962 rtl8188eu_mac[i].val); 2963 if (error != USB_ERR_NORMAL_COMPLETION) 2964 return (EIO); 2965 } 2966 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2967 } else { 2968 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2969 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2970 rtl8192cu_mac[i].val); 2971 if (error != USB_ERR_NORMAL_COMPLETION) 2972 return (EIO); 2973 } 2974 2975 return (0); 2976} 2977 2978static void 2979urtwn_bb_init(struct urtwn_softc *sc) 2980{ 2981 const struct urtwn_bb_prog *prog; 2982 uint32_t reg; 2983 uint8_t crystalcap; 2984 int i; 2985 2986 /* Enable BB and RF. */ 2987 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2988 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2989 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2990 R92C_SYS_FUNC_EN_DIO_RF); 2991 2992 if (!(sc->chip & URTWN_CHIP_88E)) 2993 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2994 2995 urtwn_write_1(sc, R92C_RF_CTRL, 2996 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2997 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2998 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2999 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3000 3001 if (!(sc->chip & URTWN_CHIP_88E)) { 3002 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3003 urtwn_write_1(sc, 0x15, 0xe9); 3004 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3005 } 3006 3007 /* Select BB programming based on board type. */ 3008 if (sc->chip & URTWN_CHIP_88E) 3009 prog = &rtl8188eu_bb_prog; 3010 else if (!(sc->chip & URTWN_CHIP_92C)) { 3011 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3012 prog = &rtl8188ce_bb_prog; 3013 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3014 prog = &rtl8188ru_bb_prog; 3015 else 3016 prog = &rtl8188cu_bb_prog; 3017 } else { 3018 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3019 prog = &rtl8192ce_bb_prog; 3020 else 3021 prog = &rtl8192cu_bb_prog; 3022 } 3023 /* Write BB initialization values. */ 3024 for (i = 0; i < prog->count; i++) { 3025 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3026 urtwn_ms_delay(sc); 3027 } 3028 3029 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3030 /* 8192C 1T only configuration. */ 3031 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3032 reg = (reg & ~0x00000003) | 0x2; 3033 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3034 3035 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3036 reg = (reg & ~0x00300033) | 0x00200022; 3037 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3038 3039 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3040 reg = (reg & ~0xff000000) | 0x45 << 24; 3041 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3042 3043 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3044 reg = (reg & ~0x000000ff) | 0x23; 3045 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3046 3047 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3048 reg = (reg & ~0x00000030) | 1 << 4; 3049 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3050 3051 reg = urtwn_bb_read(sc, 0xe74); 3052 reg = (reg & ~0x0c000000) | 2 << 26; 3053 urtwn_bb_write(sc, 0xe74, reg); 3054 reg = urtwn_bb_read(sc, 0xe78); 3055 reg = (reg & ~0x0c000000) | 2 << 26; 3056 urtwn_bb_write(sc, 0xe78, reg); 3057 reg = urtwn_bb_read(sc, 0xe7c); 3058 reg = (reg & ~0x0c000000) | 2 << 26; 3059 urtwn_bb_write(sc, 0xe7c, reg); 3060 reg = urtwn_bb_read(sc, 0xe80); 3061 reg = (reg & ~0x0c000000) | 2 << 26; 3062 urtwn_bb_write(sc, 0xe80, reg); 3063 reg = urtwn_bb_read(sc, 0xe88); 3064 reg = (reg & ~0x0c000000) | 2 << 26; 3065 urtwn_bb_write(sc, 0xe88, reg); 3066 } 3067 3068 /* Write AGC values. */ 3069 for (i = 0; i < prog->agccount; i++) { 3070 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 3071 prog->agcvals[i]); 3072 urtwn_ms_delay(sc); 3073 } 3074 3075 if (sc->chip & URTWN_CHIP_88E) { 3076 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3077 urtwn_ms_delay(sc); 3078 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3079 urtwn_ms_delay(sc); 3080 3081 crystalcap = sc->rom.r88e_rom[0xb9]; 3082 if (crystalcap == 0xff) 3083 crystalcap = 0x20; 3084 crystalcap &= 0x3f; 3085 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3086 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3087 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3088 crystalcap | crystalcap << 6)); 3089 } else { 3090 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3091 R92C_HSSI_PARAM2_CCK_HIPWR) 3092 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 3093 } 3094} 3095 3096static void 3097urtwn_rf_init(struct urtwn_softc *sc) 3098{ 3099 const struct urtwn_rf_prog *prog; 3100 uint32_t reg, type; 3101 int i, j, idx, off; 3102 3103 /* Select RF programming based on board type. */ 3104 if (sc->chip & URTWN_CHIP_88E) 3105 prog = rtl8188eu_rf_prog; 3106 else if (!(sc->chip & URTWN_CHIP_92C)) { 3107 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3108 prog = rtl8188ce_rf_prog; 3109 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3110 prog = rtl8188ru_rf_prog; 3111 else 3112 prog = rtl8188cu_rf_prog; 3113 } else 3114 prog = rtl8192ce_rf_prog; 3115 3116 for (i = 0; i < sc->nrxchains; i++) { 3117 /* Save RF_ENV control type. */ 3118 idx = i / 2; 3119 off = (i % 2) * 16; 3120 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3121 type = (reg >> off) & 0x10; 3122 3123 /* Set RF_ENV enable. */ 3124 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3125 reg |= 0x100000; 3126 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3127 urtwn_ms_delay(sc); 3128 /* Set RF_ENV output high. */ 3129 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3130 reg |= 0x10; 3131 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3132 urtwn_ms_delay(sc); 3133 /* Set address and data lengths of RF registers. */ 3134 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3135 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3136 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3137 urtwn_ms_delay(sc); 3138 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3139 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3140 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3141 urtwn_ms_delay(sc); 3142 3143 /* Write RF initialization values for this chain. */ 3144 for (j = 0; j < prog[i].count; j++) { 3145 if (prog[i].regs[j] >= 0xf9 && 3146 prog[i].regs[j] <= 0xfe) { 3147 /* 3148 * These are fake RF registers offsets that 3149 * indicate a delay is required. 3150 */ 3151 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 3152 continue; 3153 } 3154 urtwn_rf_write(sc, i, prog[i].regs[j], 3155 prog[i].vals[j]); 3156 urtwn_ms_delay(sc); 3157 } 3158 3159 /* Restore RF_ENV control type. */ 3160 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3161 reg &= ~(0x10 << off) | (type << off); 3162 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 3163 3164 /* Cache RF register CHNLBW. */ 3165 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3166 } 3167 3168 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3169 URTWN_CHIP_UMC_A_CUT) { 3170 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3171 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3172 } 3173} 3174 3175static void 3176urtwn_cam_init(struct urtwn_softc *sc) 3177{ 3178 /* Invalidate all CAM entries. */ 3179 urtwn_write_4(sc, R92C_CAMCMD, 3180 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3181} 3182 3183static void 3184urtwn_pa_bias_init(struct urtwn_softc *sc) 3185{ 3186 uint8_t reg; 3187 int i; 3188 3189 for (i = 0; i < sc->nrxchains; i++) { 3190 if (sc->pa_setting & (1 << i)) 3191 continue; 3192 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3193 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3194 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3195 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3196 } 3197 if (!(sc->pa_setting & 0x10)) { 3198 reg = urtwn_read_1(sc, 0x16); 3199 reg = (reg & ~0xf0) | 0x90; 3200 urtwn_write_1(sc, 0x16, reg); 3201 } 3202} 3203 3204static void 3205urtwn_rxfilter_init(struct urtwn_softc *sc) 3206{ 3207 struct ieee80211com *ic = &sc->sc_ic; 3208 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3209 uint32_t rcr; 3210 uint16_t filter; 3211 3212 URTWN_ASSERT_LOCKED(sc); 3213 3214 /* Accept all multicast frames. */ 3215 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3216 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3217 3218 /* Filter for management frames. */ 3219 filter = 0x7f3f; 3220 switch (vap->iv_opmode) { 3221 case IEEE80211_M_STA: 3222 filter &= ~( 3223 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 3224 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 3225 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 3226 break; 3227 case IEEE80211_M_HOSTAP: 3228 filter &= ~( 3229 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 3230 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP) | 3231 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_BEACON)); 3232 break; 3233 case IEEE80211_M_MONITOR: 3234 case IEEE80211_M_IBSS: 3235 break; 3236 default: 3237 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3238 __func__, vap->iv_opmode); 3239 break; 3240 } 3241 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 3242 3243 /* Reject all control frames. */ 3244 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3245 3246 /* Reject all data frames. */ 3247 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 3248 3249 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 3250 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 3251 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 3252 3253 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 3254 /* Accept all frames. */ 3255 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 3256 R92C_RCR_AAP; 3257 } 3258 3259 /* Set Rx filter. */ 3260 urtwn_write_4(sc, R92C_RCR, rcr); 3261 3262 if (ic->ic_promisc != 0) { 3263 /* Update Rx filter. */ 3264 urtwn_set_promisc(sc); 3265 } 3266} 3267 3268static void 3269urtwn_edca_init(struct urtwn_softc *sc) 3270{ 3271 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3272 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3273 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3274 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3275 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3276 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3277 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3278 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3279} 3280 3281static void 3282urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3283 uint16_t power[URTWN_RIDX_COUNT]) 3284{ 3285 uint32_t reg; 3286 3287 /* Write per-CCK rate Tx power. */ 3288 if (chain == 0) { 3289 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3290 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3291 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3292 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3293 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3294 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3295 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3296 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3297 } else { 3298 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3299 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3300 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3301 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3302 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3303 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3304 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3305 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3306 } 3307 /* Write per-OFDM rate Tx power. */ 3308 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3309 SM(R92C_TXAGC_RATE06, power[ 4]) | 3310 SM(R92C_TXAGC_RATE09, power[ 5]) | 3311 SM(R92C_TXAGC_RATE12, power[ 6]) | 3312 SM(R92C_TXAGC_RATE18, power[ 7])); 3313 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3314 SM(R92C_TXAGC_RATE24, power[ 8]) | 3315 SM(R92C_TXAGC_RATE36, power[ 9]) | 3316 SM(R92C_TXAGC_RATE48, power[10]) | 3317 SM(R92C_TXAGC_RATE54, power[11])); 3318 /* Write per-MCS Tx power. */ 3319 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3320 SM(R92C_TXAGC_MCS00, power[12]) | 3321 SM(R92C_TXAGC_MCS01, power[13]) | 3322 SM(R92C_TXAGC_MCS02, power[14]) | 3323 SM(R92C_TXAGC_MCS03, power[15])); 3324 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3325 SM(R92C_TXAGC_MCS04, power[16]) | 3326 SM(R92C_TXAGC_MCS05, power[17]) | 3327 SM(R92C_TXAGC_MCS06, power[18]) | 3328 SM(R92C_TXAGC_MCS07, power[19])); 3329 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3330 SM(R92C_TXAGC_MCS08, power[20]) | 3331 SM(R92C_TXAGC_MCS09, power[21]) | 3332 SM(R92C_TXAGC_MCS10, power[22]) | 3333 SM(R92C_TXAGC_MCS11, power[23])); 3334 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3335 SM(R92C_TXAGC_MCS12, power[24]) | 3336 SM(R92C_TXAGC_MCS13, power[25]) | 3337 SM(R92C_TXAGC_MCS14, power[26]) | 3338 SM(R92C_TXAGC_MCS15, power[27])); 3339} 3340 3341static void 3342urtwn_get_txpower(struct urtwn_softc *sc, int chain, 3343 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3344 uint16_t power[URTWN_RIDX_COUNT]) 3345{ 3346 struct ieee80211com *ic = &sc->sc_ic; 3347 struct r92c_rom *rom = &sc->rom.r92c_rom; 3348 uint16_t cckpow, ofdmpow, htpow, diff, max; 3349 const struct urtwn_txpwr *base; 3350 int ridx, chan, group; 3351 3352 /* Determine channel group. */ 3353 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3354 if (chan <= 3) 3355 group = 0; 3356 else if (chan <= 9) 3357 group = 1; 3358 else 3359 group = 2; 3360 3361 /* Get original Tx power based on board type and RF chain. */ 3362 if (!(sc->chip & URTWN_CHIP_92C)) { 3363 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3364 base = &rtl8188ru_txagc[chain]; 3365 else 3366 base = &rtl8192cu_txagc[chain]; 3367 } else 3368 base = &rtl8192cu_txagc[chain]; 3369 3370 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3371 if (sc->regulatory == 0) { 3372 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3373 power[ridx] = base->pwr[0][ridx]; 3374 } 3375 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3376 if (sc->regulatory == 3) { 3377 power[ridx] = base->pwr[0][ridx]; 3378 /* Apply vendor limits. */ 3379 if (extc != NULL) 3380 max = rom->ht40_max_pwr[group]; 3381 else 3382 max = rom->ht20_max_pwr[group]; 3383 max = (max >> (chain * 4)) & 0xf; 3384 if (power[ridx] > max) 3385 power[ridx] = max; 3386 } else if (sc->regulatory == 1) { 3387 if (extc == NULL) 3388 power[ridx] = base->pwr[group][ridx]; 3389 } else if (sc->regulatory != 2) 3390 power[ridx] = base->pwr[0][ridx]; 3391 } 3392 3393 /* Compute per-CCK rate Tx power. */ 3394 cckpow = rom->cck_tx_pwr[chain][group]; 3395 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3396 power[ridx] += cckpow; 3397 if (power[ridx] > R92C_MAX_TX_PWR) 3398 power[ridx] = R92C_MAX_TX_PWR; 3399 } 3400 3401 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3402 if (sc->ntxchains > 1) { 3403 /* Apply reduction for 2 spatial streams. */ 3404 diff = rom->ht40_2s_tx_pwr_diff[group]; 3405 diff = (diff >> (chain * 4)) & 0xf; 3406 htpow = (htpow > diff) ? htpow - diff : 0; 3407 } 3408 3409 /* Compute per-OFDM rate Tx power. */ 3410 diff = rom->ofdm_tx_pwr_diff[group]; 3411 diff = (diff >> (chain * 4)) & 0xf; 3412 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3413 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3414 power[ridx] += ofdmpow; 3415 if (power[ridx] > R92C_MAX_TX_PWR) 3416 power[ridx] = R92C_MAX_TX_PWR; 3417 } 3418 3419 /* Compute per-MCS Tx power. */ 3420 if (extc == NULL) { 3421 diff = rom->ht20_tx_pwr_diff[group]; 3422 diff = (diff >> (chain * 4)) & 0xf; 3423 htpow += diff; /* HT40->HT20 correction. */ 3424 } 3425 for (ridx = 12; ridx <= 27; ridx++) { 3426 power[ridx] += htpow; 3427 if (power[ridx] > R92C_MAX_TX_PWR) 3428 power[ridx] = R92C_MAX_TX_PWR; 3429 } 3430#ifdef URTWN_DEBUG 3431 if (urtwn_debug >= 4) { 3432 /* Dump per-rate Tx power values. */ 3433 printf("Tx power for chain %d:\n", chain); 3434 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 3435 printf("Rate %d = %u\n", ridx, power[ridx]); 3436 } 3437#endif 3438} 3439 3440static void 3441urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3442 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3443 uint16_t power[URTWN_RIDX_COUNT]) 3444{ 3445 struct ieee80211com *ic = &sc->sc_ic; 3446 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3447 const struct urtwn_r88e_txpwr *base; 3448 int ridx, chan, group; 3449 3450 /* Determine channel group. */ 3451 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3452 if (chan <= 2) 3453 group = 0; 3454 else if (chan <= 5) 3455 group = 1; 3456 else if (chan <= 8) 3457 group = 2; 3458 else if (chan <= 11) 3459 group = 3; 3460 else if (chan <= 13) 3461 group = 4; 3462 else 3463 group = 5; 3464 3465 /* Get original Tx power based on board type and RF chain. */ 3466 base = &rtl8188eu_txagc[chain]; 3467 3468 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3469 if (sc->regulatory == 0) { 3470 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3471 power[ridx] = base->pwr[0][ridx]; 3472 } 3473 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3474 if (sc->regulatory == 3) 3475 power[ridx] = base->pwr[0][ridx]; 3476 else if (sc->regulatory == 1) { 3477 if (extc == NULL) 3478 power[ridx] = base->pwr[group][ridx]; 3479 } else if (sc->regulatory != 2) 3480 power[ridx] = base->pwr[0][ridx]; 3481 } 3482 3483 /* Compute per-CCK rate Tx power. */ 3484 cckpow = sc->cck_tx_pwr[group]; 3485 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3486 power[ridx] += cckpow; 3487 if (power[ridx] > R92C_MAX_TX_PWR) 3488 power[ridx] = R92C_MAX_TX_PWR; 3489 } 3490 3491 htpow = sc->ht40_tx_pwr[group]; 3492 3493 /* Compute per-OFDM rate Tx power. */ 3494 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3495 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3496 power[ridx] += ofdmpow; 3497 if (power[ridx] > R92C_MAX_TX_PWR) 3498 power[ridx] = R92C_MAX_TX_PWR; 3499 } 3500 3501 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3502 for (ridx = 12; ridx <= 27; ridx++) { 3503 power[ridx] += bw20pow; 3504 if (power[ridx] > R92C_MAX_TX_PWR) 3505 power[ridx] = R92C_MAX_TX_PWR; 3506 } 3507} 3508 3509static void 3510urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3511 struct ieee80211_channel *extc) 3512{ 3513 uint16_t power[URTWN_RIDX_COUNT]; 3514 int i; 3515 3516 for (i = 0; i < sc->ntxchains; i++) { 3517 /* Compute per-rate Tx power values. */ 3518 if (sc->chip & URTWN_CHIP_88E) 3519 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3520 else 3521 urtwn_get_txpower(sc, i, c, extc, power); 3522 /* Write per-rate Tx power values to hardware. */ 3523 urtwn_write_txpower(sc, i, power); 3524 } 3525} 3526 3527static void 3528urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 3529{ 3530 uint32_t reg; 3531 3532 reg = urtwn_read_4(sc, R92C_RCR); 3533 if (enable) 3534 reg &= ~R92C_RCR_CBSSID_BCN; 3535 else 3536 reg |= R92C_RCR_CBSSID_BCN; 3537 urtwn_write_4(sc, R92C_RCR, reg); 3538} 3539 3540static void 3541urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 3542{ 3543 uint32_t reg; 3544 3545 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3546 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3547 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3548 3549 if (!(sc->chip & URTWN_CHIP_88E)) { 3550 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3551 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3552 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3553 } 3554} 3555 3556static void 3557urtwn_scan_start(struct ieee80211com *ic) 3558{ 3559 struct urtwn_softc *sc = ic->ic_softc; 3560 3561 URTWN_LOCK(sc); 3562 /* Receive beacons / probe responses from any BSSID. */ 3563 if (ic->ic_opmode != IEEE80211_M_IBSS) 3564 urtwn_set_rx_bssid_all(sc, 1); 3565 3566 /* Set gain for scanning. */ 3567 urtwn_set_gain(sc, 0x20); 3568 URTWN_UNLOCK(sc); 3569} 3570 3571static void 3572urtwn_scan_end(struct ieee80211com *ic) 3573{ 3574 struct urtwn_softc *sc = ic->ic_softc; 3575 3576 URTWN_LOCK(sc); 3577 /* Restore limitations. */ 3578 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 3579 urtwn_set_rx_bssid_all(sc, 0); 3580 3581 /* Set gain under link. */ 3582 urtwn_set_gain(sc, 0x32); 3583 URTWN_UNLOCK(sc); 3584} 3585 3586static void 3587urtwn_set_channel(struct ieee80211com *ic) 3588{ 3589 struct urtwn_softc *sc = ic->ic_softc; 3590 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3591 3592 URTWN_LOCK(sc); 3593 if (vap->iv_state == IEEE80211_S_SCAN) { 3594 /* Make link LED blink during scan. */ 3595 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3596 } 3597 urtwn_set_chan(sc, ic->ic_curchan, NULL); 3598 URTWN_UNLOCK(sc); 3599} 3600 3601static void 3602urtwn_set_promisc(struct urtwn_softc *sc) 3603{ 3604 struct ieee80211com *ic = &sc->sc_ic; 3605 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3606 uint32_t rcr, mask1, mask2; 3607 3608 URTWN_ASSERT_LOCKED(sc); 3609 3610 if (vap->iv_opmode == IEEE80211_M_MONITOR) 3611 return; 3612 3613 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 3614 mask2 = R92C_RCR_APM; 3615 3616 if (vap->iv_state == IEEE80211_S_RUN) { 3617 switch (vap->iv_opmode) { 3618 case IEEE80211_M_STA: 3619 mask2 |= R92C_RCR_CBSSID_DATA; 3620 /* FALLTHROUGH */ 3621 case IEEE80211_M_HOSTAP: 3622 mask2 |= R92C_RCR_CBSSID_BCN; 3623 break; 3624 case IEEE80211_M_IBSS: 3625 mask2 |= R92C_RCR_CBSSID_DATA; 3626 break; 3627 default: 3628 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3629 __func__, vap->iv_opmode); 3630 return; 3631 } 3632 } 3633 3634 rcr = urtwn_read_4(sc, R92C_RCR); 3635 if (ic->ic_promisc == 0) 3636 rcr = (rcr & ~mask1) | mask2; 3637 else 3638 rcr = (rcr & ~mask2) | mask1; 3639 urtwn_write_4(sc, R92C_RCR, rcr); 3640} 3641 3642static void 3643urtwn_update_promisc(struct ieee80211com *ic) 3644{ 3645 struct urtwn_softc *sc = ic->ic_softc; 3646 3647 URTWN_LOCK(sc); 3648 if (sc->sc_flags & URTWN_RUNNING) 3649 urtwn_set_promisc(sc); 3650 URTWN_UNLOCK(sc); 3651} 3652 3653static void 3654urtwn_update_mcast(struct ieee80211com *ic) 3655{ 3656 /* XXX do nothing? */ 3657} 3658 3659static void 3660urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3661 struct ieee80211_channel *extc) 3662{ 3663 struct ieee80211com *ic = &sc->sc_ic; 3664 uint32_t reg; 3665 u_int chan; 3666 int i; 3667 3668 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3669 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3670 device_printf(sc->sc_dev, 3671 "%s: invalid channel %x\n", __func__, chan); 3672 return; 3673 } 3674 3675 /* Set Tx power for this new channel. */ 3676 urtwn_set_txpower(sc, c, extc); 3677 3678 for (i = 0; i < sc->nrxchains; i++) { 3679 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3680 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3681 } 3682#ifndef IEEE80211_NO_HT 3683 if (extc != NULL) { 3684 /* Is secondary channel below or above primary? */ 3685 int prichlo = c->ic_freq < extc->ic_freq; 3686 3687 urtwn_write_1(sc, R92C_BWOPMODE, 3688 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3689 3690 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3691 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3692 urtwn_write_1(sc, R92C_RRSR + 2, reg); 3693 3694 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3695 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3696 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3697 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3698 3699 /* Set CCK side band. */ 3700 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3701 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3702 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3703 3704 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3705 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3706 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3707 3708 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3709 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3710 ~R92C_FPGA0_ANAPARAM2_CBW20); 3711 3712 reg = urtwn_bb_read(sc, 0x818); 3713 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3714 urtwn_bb_write(sc, 0x818, reg); 3715 3716 /* Select 40MHz bandwidth. */ 3717 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3718 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3719 } else 3720#endif 3721 { 3722 urtwn_write_1(sc, R92C_BWOPMODE, 3723 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3724 3725 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3726 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3727 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3728 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3729 3730 if (!(sc->chip & URTWN_CHIP_88E)) { 3731 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3732 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3733 R92C_FPGA0_ANAPARAM2_CBW20); 3734 } 3735 3736 /* Select 20MHz bandwidth. */ 3737 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3738 (sc->rf_chnlbw[0] & ~0xfff) | chan | 3739 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3740 R92C_RF_CHNLBW_BW20)); 3741 } 3742} 3743 3744static void 3745urtwn_iq_calib(struct urtwn_softc *sc) 3746{ 3747 /* TODO */ 3748} 3749 3750static void 3751urtwn_lc_calib(struct urtwn_softc *sc) 3752{ 3753 uint32_t rf_ac[2]; 3754 uint8_t txmode; 3755 int i; 3756 3757 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3758 if ((txmode & 0x70) != 0) { 3759 /* Disable all continuous Tx. */ 3760 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3761 3762 /* Set RF mode to standby mode. */ 3763 for (i = 0; i < sc->nrxchains; i++) { 3764 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3765 urtwn_rf_write(sc, i, R92C_RF_AC, 3766 RW(rf_ac[i], R92C_RF_AC_MODE, 3767 R92C_RF_AC_MODE_STANDBY)); 3768 } 3769 } else { 3770 /* Block all Tx queues. */ 3771 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3772 } 3773 /* Start calibration. */ 3774 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3775 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3776 3777 /* Give calibration the time to complete. */ 3778 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3779 3780 /* Restore configuration. */ 3781 if ((txmode & 0x70) != 0) { 3782 /* Restore Tx mode. */ 3783 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3784 /* Restore RF mode. */ 3785 for (i = 0; i < sc->nrxchains; i++) 3786 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3787 } else { 3788 /* Unblock all Tx queues. */ 3789 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3790 } 3791} 3792 3793static int 3794urtwn_init(struct urtwn_softc *sc) 3795{ 3796 struct ieee80211com *ic = &sc->sc_ic; 3797 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3798 uint8_t macaddr[IEEE80211_ADDR_LEN]; 3799 uint32_t reg; 3800 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 3801 int error; 3802 3803 URTWN_LOCK(sc); 3804 if (sc->sc_flags & URTWN_RUNNING) { 3805 URTWN_UNLOCK(sc); 3806 return (0); 3807 } 3808 3809 /* Init firmware commands ring. */ 3810 sc->fwcur = 0; 3811 3812 /* Allocate Tx/Rx buffers. */ 3813 error = urtwn_alloc_rx_list(sc); 3814 if (error != 0) 3815 goto fail; 3816 3817 error = urtwn_alloc_tx_list(sc); 3818 if (error != 0) 3819 goto fail; 3820 3821 /* Power on adapter. */ 3822 error = urtwn_power_on(sc); 3823 if (error != 0) 3824 goto fail; 3825 3826 /* Initialize DMA. */ 3827 error = urtwn_dma_init(sc); 3828 if (error != 0) 3829 goto fail; 3830 3831 /* Set info size in Rx descriptors (in 64-bit words). */ 3832 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3833 3834 /* Init interrupts. */ 3835 if (sc->chip & URTWN_CHIP_88E) { 3836 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3837 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3838 goto fail; 3839 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3840 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3841 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3842 goto fail; 3843 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3844 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3845 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3846 goto fail; 3847 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3848 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3849 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3850 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3851 goto fail; 3852 } else { 3853 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3854 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3855 goto fail; 3856 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3857 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3858 goto fail; 3859 } 3860 3861 /* Set MAC address. */ 3862 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3863 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3864 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3865 goto fail; 3866 3867 /* Set initial network type. */ 3868 urtwn_set_mode(sc, R92C_MSR_INFRA); 3869 3870 /* Initialize Rx filter. */ 3871 urtwn_rxfilter_init(sc); 3872 3873 /* Set response rate. */ 3874 reg = urtwn_read_4(sc, R92C_RRSR); 3875 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3876 urtwn_write_4(sc, R92C_RRSR, reg); 3877 3878 /* Set short/long retry limits. */ 3879 urtwn_write_2(sc, R92C_RL, 3880 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3881 3882 /* Initialize EDCA parameters. */ 3883 urtwn_edca_init(sc); 3884 3885 /* Setup rate fallback. */ 3886 if (!(sc->chip & URTWN_CHIP_88E)) { 3887 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3888 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3889 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3890 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3891 } 3892 3893 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3894 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3895 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3896 /* Set ACK timeout. */ 3897 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3898 3899 /* Setup USB aggregation. */ 3900 reg = urtwn_read_4(sc, R92C_TDECTRL); 3901 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3902 urtwn_write_4(sc, R92C_TDECTRL, reg); 3903 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3904 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3905 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3906 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3907 if (sc->chip & URTWN_CHIP_88E) 3908 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3909 else { 3910 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3911 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3912 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3913 R92C_USB_SPECIAL_OPTION_AGG_EN); 3914 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3915 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3916 } 3917 3918 /* Initialize beacon parameters. */ 3919 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3920 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3921 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3922 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3923 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3924 3925 if (!(sc->chip & URTWN_CHIP_88E)) { 3926 /* Setup AMPDU aggregation. */ 3927 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3928 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3929 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3930 3931 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3932 } 3933 3934 /* Load 8051 microcode. */ 3935 error = urtwn_load_firmware(sc); 3936 if (error != 0) 3937 goto fail; 3938 3939 /* Initialize MAC/BB/RF blocks. */ 3940 error = urtwn_mac_init(sc); 3941 if (error != 0) { 3942 device_printf(sc->sc_dev, 3943 "%s: error while initializing MAC block\n", __func__); 3944 goto fail; 3945 } 3946 urtwn_bb_init(sc); 3947 urtwn_rf_init(sc); 3948 3949 /* Reinitialize Rx filter (D3845 is not committed yet). */ 3950 urtwn_rxfilter_init(sc); 3951 3952 if (sc->chip & URTWN_CHIP_88E) { 3953 urtwn_write_2(sc, R92C_CR, 3954 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3955 R92C_CR_MACRXEN); 3956 } 3957 3958 /* Turn CCK and OFDM blocks on. */ 3959 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3960 reg |= R92C_RFMOD_CCK_EN; 3961 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3962 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3963 goto fail; 3964 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3965 reg |= R92C_RFMOD_OFDM_EN; 3966 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3967 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3968 goto fail; 3969 3970 /* Clear per-station keys table. */ 3971 urtwn_cam_init(sc); 3972 3973 /* Enable hardware sequence numbering. */ 3974 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3975 3976 /* Perform LO and IQ calibrations. */ 3977 urtwn_iq_calib(sc); 3978 /* Perform LC calibration. */ 3979 urtwn_lc_calib(sc); 3980 3981 /* Fix USB interference issue. */ 3982 if (!(sc->chip & URTWN_CHIP_88E)) { 3983 urtwn_write_1(sc, 0xfe40, 0xe0); 3984 urtwn_write_1(sc, 0xfe41, 0x8d); 3985 urtwn_write_1(sc, 0xfe42, 0x80); 3986 3987 urtwn_pa_bias_init(sc); 3988 } 3989 3990 /* Initialize GPIO setting. */ 3991 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3992 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3993 3994 /* Fix for lower temperature. */ 3995 if (!(sc->chip & URTWN_CHIP_88E)) 3996 urtwn_write_1(sc, 0x15, 0xe9); 3997 3998 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3999 4000 sc->sc_flags |= URTWN_RUNNING; 4001 4002 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4003fail: 4004 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4005 error = EIO; 4006 4007 URTWN_UNLOCK(sc); 4008 4009 return (error); 4010} 4011 4012static void 4013urtwn_stop(struct urtwn_softc *sc) 4014{ 4015 4016 URTWN_LOCK(sc); 4017 if (!(sc->sc_flags & URTWN_RUNNING)) { 4018 URTWN_UNLOCK(sc); 4019 return; 4020 } 4021 4022 sc->sc_flags &= ~URTWN_RUNNING; 4023 callout_stop(&sc->sc_watchdog_ch); 4024 urtwn_abort_xfers(sc); 4025 4026 urtwn_drain_mbufq(sc); 4027 URTWN_UNLOCK(sc); 4028} 4029 4030static void 4031urtwn_abort_xfers(struct urtwn_softc *sc) 4032{ 4033 int i; 4034 4035 URTWN_ASSERT_LOCKED(sc); 4036 4037 /* abort any pending transfers */ 4038 for (i = 0; i < URTWN_N_TRANSFER; i++) 4039 usbd_transfer_stop(sc->sc_xfer[i]); 4040} 4041 4042static int 4043urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4044 const struct ieee80211_bpf_params *params) 4045{ 4046 struct ieee80211com *ic = ni->ni_ic; 4047 struct urtwn_softc *sc = ic->ic_softc; 4048 struct urtwn_data *bf; 4049 int error; 4050 4051 /* prevent management frames from being sent if we're not ready */ 4052 URTWN_LOCK(sc); 4053 if (!(sc->sc_flags & URTWN_RUNNING)) { 4054 error = ENETDOWN; 4055 goto end; 4056 } 4057 4058 bf = urtwn_getbuf(sc); 4059 if (bf == NULL) { 4060 error = ENOBUFS; 4061 goto end; 4062 } 4063 4064 if ((error = urtwn_tx_data(sc, ni, m, bf)) != 0) { 4065 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 4066 goto end; 4067 } 4068 4069 sc->sc_txtimer = 5; 4070 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4071 4072end: 4073 if (error != 0) 4074 m_freem(m); 4075 4076 URTWN_UNLOCK(sc); 4077 4078 return (error); 4079} 4080 4081static void 4082urtwn_ms_delay(struct urtwn_softc *sc) 4083{ 4084 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 4085} 4086 4087static device_method_t urtwn_methods[] = { 4088 /* Device interface */ 4089 DEVMETHOD(device_probe, urtwn_match), 4090 DEVMETHOD(device_attach, urtwn_attach), 4091 DEVMETHOD(device_detach, urtwn_detach), 4092 4093 DEVMETHOD_END 4094}; 4095 4096static driver_t urtwn_driver = { 4097 "urtwn", 4098 urtwn_methods, 4099 sizeof(struct urtwn_softc) 4100}; 4101 4102static devclass_t urtwn_devclass; 4103 4104DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 4105MODULE_DEPEND(urtwn, usb, 1, 1, 1); 4106MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 4107MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 4108MODULE_VERSION(urtwn, 1); 4109