if_urtwn.c revision 291858
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 291858 2015-12-05 15:08:01Z avos $"); 22 23/* 24 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25 */ 26 27#include "opt_wlan.h" 28 29#include <sys/param.h> 30#include <sys/sockio.h> 31#include <sys/sysctl.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/mbuf.h> 35#include <sys/kernel.h> 36#include <sys/socket.h> 37#include <sys/systm.h> 38#include <sys/malloc.h> 39#include <sys/module.h> 40#include <sys/bus.h> 41#include <sys/endian.h> 42#include <sys/linker.h> 43#include <sys/firmware.h> 44#include <sys/kdb.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48#include <sys/rman.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_var.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/in_var.h> 62#include <netinet/if_ether.h> 63#include <netinet/ip.h> 64 65#include <net80211/ieee80211_var.h> 66#include <net80211/ieee80211_input.h> 67#include <net80211/ieee80211_regdomain.h> 68#include <net80211/ieee80211_radiotap.h> 69#include <net80211/ieee80211_ratectl.h> 70 71#include <dev/usb/usb.h> 72#include <dev/usb/usbdi.h> 73#include "usbdevs.h" 74 75#define USB_DEBUG_VAR urtwn_debug 76#include <dev/usb/usb_debug.h> 77 78#include <dev/usb/wlan/if_urtwnreg.h> 79#include <dev/usb/wlan/if_urtwnvar.h> 80 81#ifdef USB_DEBUG 82static int urtwn_debug = 0; 83 84SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 85SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 86 "Debug level"); 87#endif 88 89#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 90 91/* various supported device vendors/products */ 92static const STRUCT_USB_HOST_ID urtwn_devs[] = { 93#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 94#define URTWN_RTL8188E_DEV(v,p) \ 95 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 96#define URTWN_RTL8188E 1 97 URTWN_DEV(ABOCOM, RTL8188CU_1), 98 URTWN_DEV(ABOCOM, RTL8188CU_2), 99 URTWN_DEV(ABOCOM, RTL8192CU), 100 URTWN_DEV(ASUS, RTL8192CU), 101 URTWN_DEV(ASUS, USBN10NANO), 102 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 103 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 104 URTWN_DEV(AZUREWAVE, RTL8188CU), 105 URTWN_DEV(BELKIN, F7D2102), 106 URTWN_DEV(BELKIN, RTL8188CU), 107 URTWN_DEV(BELKIN, RTL8192CU), 108 URTWN_DEV(CHICONY, RTL8188CUS_1), 109 URTWN_DEV(CHICONY, RTL8188CUS_2), 110 URTWN_DEV(CHICONY, RTL8188CUS_3), 111 URTWN_DEV(CHICONY, RTL8188CUS_4), 112 URTWN_DEV(CHICONY, RTL8188CUS_5), 113 URTWN_DEV(COREGA, RTL8192CU), 114 URTWN_DEV(DLINK, RTL8188CU), 115 URTWN_DEV(DLINK, RTL8192CU_1), 116 URTWN_DEV(DLINK, RTL8192CU_2), 117 URTWN_DEV(DLINK, RTL8192CU_3), 118 URTWN_DEV(DLINK, DWA131B), 119 URTWN_DEV(EDIMAX, EW7811UN), 120 URTWN_DEV(EDIMAX, RTL8192CU), 121 URTWN_DEV(FEIXUN, RTL8188CU), 122 URTWN_DEV(FEIXUN, RTL8192CU), 123 URTWN_DEV(GUILLEMOT, HWNUP150), 124 URTWN_DEV(HAWKING, RTL8192CU), 125 URTWN_DEV(HP3, RTL8188CU), 126 URTWN_DEV(NETGEAR, WNA1000M), 127 URTWN_DEV(NETGEAR, RTL8192CU), 128 URTWN_DEV(NETGEAR4, RTL8188CU), 129 URTWN_DEV(NOVATECH, RTL8188CU), 130 URTWN_DEV(PLANEX2, RTL8188CU_1), 131 URTWN_DEV(PLANEX2, RTL8188CU_2), 132 URTWN_DEV(PLANEX2, RTL8188CU_3), 133 URTWN_DEV(PLANEX2, RTL8188CU_4), 134 URTWN_DEV(PLANEX2, RTL8188CUS), 135 URTWN_DEV(PLANEX2, RTL8192CU), 136 URTWN_DEV(REALTEK, RTL8188CE_0), 137 URTWN_DEV(REALTEK, RTL8188CE_1), 138 URTWN_DEV(REALTEK, RTL8188CTV), 139 URTWN_DEV(REALTEK, RTL8188CU_0), 140 URTWN_DEV(REALTEK, RTL8188CU_1), 141 URTWN_DEV(REALTEK, RTL8188CU_2), 142 URTWN_DEV(REALTEK, RTL8188CU_3), 143 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 144 URTWN_DEV(REALTEK, RTL8188CUS), 145 URTWN_DEV(REALTEK, RTL8188RU_1), 146 URTWN_DEV(REALTEK, RTL8188RU_2), 147 URTWN_DEV(REALTEK, RTL8188RU_3), 148 URTWN_DEV(REALTEK, RTL8191CU), 149 URTWN_DEV(REALTEK, RTL8192CE), 150 URTWN_DEV(REALTEK, RTL8192CU), 151 URTWN_DEV(SITECOMEU, RTL8188CU_1), 152 URTWN_DEV(SITECOMEU, RTL8188CU_2), 153 URTWN_DEV(SITECOMEU, RTL8192CU), 154 URTWN_DEV(TRENDNET, RTL8188CU), 155 URTWN_DEV(TRENDNET, RTL8192CU), 156 URTWN_DEV(ZYXEL, RTL8192CU), 157 /* URTWN_RTL8188E */ 158 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 159 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 160 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 161 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 162 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 163#undef URTWN_RTL8188E_DEV 164#undef URTWN_DEV 165}; 166 167static device_probe_t urtwn_match; 168static device_attach_t urtwn_attach; 169static device_detach_t urtwn_detach; 170 171static usb_callback_t urtwn_bulk_tx_callback; 172static usb_callback_t urtwn_bulk_rx_callback; 173 174static void urtwn_drain_mbufq(struct urtwn_softc *sc); 175static usb_error_t urtwn_do_request(struct urtwn_softc *, 176 struct usb_device_request *, void *); 177static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 178 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 179 const uint8_t [IEEE80211_ADDR_LEN], 180 const uint8_t [IEEE80211_ADDR_LEN]); 181static void urtwn_vap_delete(struct ieee80211vap *); 182static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 183 int *); 184static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 185 int *, int8_t *); 186static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 187 int); 188static int urtwn_alloc_list(struct urtwn_softc *, 189 struct urtwn_data[], int, int); 190static int urtwn_alloc_rx_list(struct urtwn_softc *); 191static int urtwn_alloc_tx_list(struct urtwn_softc *); 192static void urtwn_free_list(struct urtwn_softc *, 193 struct urtwn_data data[], int); 194static void urtwn_free_rx_list(struct urtwn_softc *); 195static void urtwn_free_tx_list(struct urtwn_softc *); 196static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 197static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 198static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 199 uint8_t *, int); 200static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 201static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 202static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 203static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 204 uint8_t *, int); 205static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 206static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 207static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 208static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 209 const void *, int); 210static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 211 uint8_t, uint32_t); 212static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 213 uint8_t, uint32_t); 214static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 215static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 216 uint32_t); 217static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 218static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 219 uint8_t, uint8_t); 220#ifdef URTWN_DEBUG 221static void urtwn_dump_rom_contents(struct urtwn_softc *, 222 uint8_t *, uint16_t); 223#endif 224static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 225 uint16_t); 226static int urtwn_efuse_switch_power(struct urtwn_softc *); 227static int urtwn_read_chipid(struct urtwn_softc *); 228static int urtwn_read_rom(struct urtwn_softc *); 229static int urtwn_r88e_read_rom(struct urtwn_softc *); 230static int urtwn_ra_init(struct urtwn_softc *); 231static void urtwn_init_beacon(struct urtwn_softc *, 232 struct urtwn_vap *); 233static int urtwn_setup_beacon(struct urtwn_softc *, 234 struct ieee80211_node *); 235static void urtwn_update_beacon(struct ieee80211vap *, int); 236static int urtwn_tx_beacon(struct urtwn_softc *sc, 237 struct urtwn_vap *); 238static void urtwn_tsf_task_adhoc(void *, int); 239static void urtwn_tsf_sync_enable(struct urtwn_softc *, 240 struct ieee80211vap *); 241static void urtwn_set_led(struct urtwn_softc *, int, int); 242static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 243static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 244 struct mbuf *, int, 245 const struct ieee80211_rx_stats *, int, int); 246static int urtwn_newstate(struct ieee80211vap *, 247 enum ieee80211_state, int); 248static void urtwn_watchdog(void *); 249static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 250static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 251static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 252static int urtwn_tx_data(struct urtwn_softc *, 253 struct ieee80211_node *, struct mbuf *, 254 struct urtwn_data *); 255static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 256 uint8_t, struct urtwn_data *); 257static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 258static void urtwn_start(struct urtwn_softc *); 259static void urtwn_parent(struct ieee80211com *); 260static int urtwn_r92c_power_on(struct urtwn_softc *); 261static int urtwn_r88e_power_on(struct urtwn_softc *); 262static int urtwn_llt_init(struct urtwn_softc *); 263static void urtwn_fw_reset(struct urtwn_softc *); 264static void urtwn_r88e_fw_reset(struct urtwn_softc *); 265static int urtwn_fw_loadpage(struct urtwn_softc *, int, 266 const uint8_t *, int); 267static int urtwn_load_firmware(struct urtwn_softc *); 268static int urtwn_r92c_dma_init(struct urtwn_softc *); 269static int urtwn_r88e_dma_init(struct urtwn_softc *); 270static int urtwn_mac_init(struct urtwn_softc *); 271static void urtwn_bb_init(struct urtwn_softc *); 272static void urtwn_rf_init(struct urtwn_softc *); 273static void urtwn_cam_init(struct urtwn_softc *); 274static void urtwn_pa_bias_init(struct urtwn_softc *); 275static void urtwn_rxfilter_init(struct urtwn_softc *); 276static void urtwn_edca_init(struct urtwn_softc *); 277static void urtwn_write_txpower(struct urtwn_softc *, int, 278 uint16_t[]); 279static void urtwn_get_txpower(struct urtwn_softc *, int, 280 struct ieee80211_channel *, 281 struct ieee80211_channel *, uint16_t[]); 282static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 283 struct ieee80211_channel *, 284 struct ieee80211_channel *, uint16_t[]); 285static void urtwn_set_txpower(struct urtwn_softc *, 286 struct ieee80211_channel *, 287 struct ieee80211_channel *); 288static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 289static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 290static void urtwn_scan_start(struct ieee80211com *); 291static void urtwn_scan_end(struct ieee80211com *); 292static void urtwn_set_channel(struct ieee80211com *); 293static void urtwn_set_promisc(struct urtwn_softc *); 294static void urtwn_update_promisc(struct ieee80211com *); 295static void urtwn_update_mcast(struct ieee80211com *); 296static void urtwn_set_chan(struct urtwn_softc *, 297 struct ieee80211_channel *, 298 struct ieee80211_channel *); 299static void urtwn_iq_calib(struct urtwn_softc *); 300static void urtwn_lc_calib(struct urtwn_softc *); 301static int urtwn_init(struct urtwn_softc *); 302static void urtwn_stop(struct urtwn_softc *); 303static void urtwn_abort_xfers(struct urtwn_softc *); 304static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 305 const struct ieee80211_bpf_params *); 306static void urtwn_ms_delay(struct urtwn_softc *); 307 308/* Aliases. */ 309#define urtwn_bb_write urtwn_write_4 310#define urtwn_bb_read urtwn_read_4 311 312static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 313 [URTWN_BULK_RX] = { 314 .type = UE_BULK, 315 .endpoint = UE_ADDR_ANY, 316 .direction = UE_DIR_IN, 317 .bufsize = URTWN_RXBUFSZ, 318 .flags = { 319 .pipe_bof = 1, 320 .short_xfer_ok = 1 321 }, 322 .callback = urtwn_bulk_rx_callback, 323 }, 324 [URTWN_BULK_TX_BE] = { 325 .type = UE_BULK, 326 .endpoint = 0x03, 327 .direction = UE_DIR_OUT, 328 .bufsize = URTWN_TXBUFSZ, 329 .flags = { 330 .ext_buffer = 1, 331 .pipe_bof = 1, 332 .force_short_xfer = 1 333 }, 334 .callback = urtwn_bulk_tx_callback, 335 .timeout = URTWN_TX_TIMEOUT, /* ms */ 336 }, 337 [URTWN_BULK_TX_BK] = { 338 .type = UE_BULK, 339 .endpoint = 0x03, 340 .direction = UE_DIR_OUT, 341 .bufsize = URTWN_TXBUFSZ, 342 .flags = { 343 .ext_buffer = 1, 344 .pipe_bof = 1, 345 .force_short_xfer = 1, 346 }, 347 .callback = urtwn_bulk_tx_callback, 348 .timeout = URTWN_TX_TIMEOUT, /* ms */ 349 }, 350 [URTWN_BULK_TX_VI] = { 351 .type = UE_BULK, 352 .endpoint = 0x02, 353 .direction = UE_DIR_OUT, 354 .bufsize = URTWN_TXBUFSZ, 355 .flags = { 356 .ext_buffer = 1, 357 .pipe_bof = 1, 358 .force_short_xfer = 1 359 }, 360 .callback = urtwn_bulk_tx_callback, 361 .timeout = URTWN_TX_TIMEOUT, /* ms */ 362 }, 363 [URTWN_BULK_TX_VO] = { 364 .type = UE_BULK, 365 .endpoint = 0x02, 366 .direction = UE_DIR_OUT, 367 .bufsize = URTWN_TXBUFSZ, 368 .flags = { 369 .ext_buffer = 1, 370 .pipe_bof = 1, 371 .force_short_xfer = 1 372 }, 373 .callback = urtwn_bulk_tx_callback, 374 .timeout = URTWN_TX_TIMEOUT, /* ms */ 375 }, 376}; 377 378static int 379urtwn_match(device_t self) 380{ 381 struct usb_attach_arg *uaa = device_get_ivars(self); 382 383 if (uaa->usb_mode != USB_MODE_HOST) 384 return (ENXIO); 385 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 386 return (ENXIO); 387 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 388 return (ENXIO); 389 390 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 391} 392 393static int 394urtwn_attach(device_t self) 395{ 396 struct usb_attach_arg *uaa = device_get_ivars(self); 397 struct urtwn_softc *sc = device_get_softc(self); 398 struct ieee80211com *ic = &sc->sc_ic; 399 uint8_t iface_index, bands; 400 int error; 401 402 device_set_usb_desc(self); 403 sc->sc_udev = uaa->device; 404 sc->sc_dev = self; 405 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 406 sc->chip |= URTWN_CHIP_88E; 407 408 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 409 MTX_NETWORK_LOCK, MTX_DEF); 410 callout_init(&sc->sc_watchdog_ch, 0); 411 mbufq_init(&sc->sc_snd, ifqmaxlen); 412 413 iface_index = URTWN_IFACE_INDEX; 414 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 415 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 416 if (error) { 417 device_printf(self, "could not allocate USB transfers, " 418 "err=%s\n", usbd_errstr(error)); 419 goto detach; 420 } 421 422 URTWN_LOCK(sc); 423 424 error = urtwn_read_chipid(sc); 425 if (error) { 426 device_printf(sc->sc_dev, "unsupported test chip\n"); 427 URTWN_UNLOCK(sc); 428 goto detach; 429 } 430 431 /* Determine number of Tx/Rx chains. */ 432 if (sc->chip & URTWN_CHIP_92C) { 433 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 434 sc->nrxchains = 2; 435 } else { 436 sc->ntxchains = 1; 437 sc->nrxchains = 1; 438 } 439 440 if (sc->chip & URTWN_CHIP_88E) 441 error = urtwn_r88e_read_rom(sc); 442 else 443 error = urtwn_read_rom(sc); 444 if (error != 0) { 445 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 446 __func__, error); 447 URTWN_UNLOCK(sc); 448 goto detach; 449 } 450 451 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 452 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 453 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 454 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 455 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 456 "8188CUS", sc->ntxchains, sc->nrxchains); 457 458 URTWN_UNLOCK(sc); 459 460 ic->ic_softc = sc; 461 ic->ic_name = device_get_nameunit(self); 462 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 463 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 464 465 /* set device capabilities */ 466 ic->ic_caps = 467 IEEE80211_C_STA /* station mode */ 468 | IEEE80211_C_MONITOR /* monitor mode */ 469 | IEEE80211_C_IBSS /* adhoc mode */ 470 | IEEE80211_C_HOSTAP /* hostap mode */ 471 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 472 | IEEE80211_C_SHSLOT /* short slot time supported */ 473 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 474 | IEEE80211_C_WPA /* 802.11i */ 475 ; 476 477 bands = 0; 478 setbit(&bands, IEEE80211_MODE_11B); 479 setbit(&bands, IEEE80211_MODE_11G); 480 ieee80211_init_channels(ic, NULL, &bands); 481 482 ieee80211_ifattach(ic); 483 ic->ic_raw_xmit = urtwn_raw_xmit; 484 ic->ic_scan_start = urtwn_scan_start; 485 ic->ic_scan_end = urtwn_scan_end; 486 ic->ic_set_channel = urtwn_set_channel; 487 ic->ic_transmit = urtwn_transmit; 488 ic->ic_parent = urtwn_parent; 489 ic->ic_vap_create = urtwn_vap_create; 490 ic->ic_vap_delete = urtwn_vap_delete; 491 ic->ic_update_promisc = urtwn_update_promisc; 492 ic->ic_update_mcast = urtwn_update_mcast; 493 494 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 495 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 496 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 497 URTWN_RX_RADIOTAP_PRESENT); 498 499 if (bootverbose) 500 ieee80211_announce(ic); 501 502 return (0); 503 504detach: 505 urtwn_detach(self); 506 return (ENXIO); /* failure */ 507} 508 509static int 510urtwn_detach(device_t self) 511{ 512 struct urtwn_softc *sc = device_get_softc(self); 513 struct ieee80211com *ic = &sc->sc_ic; 514 unsigned int x; 515 516 /* Prevent further ioctls. */ 517 URTWN_LOCK(sc); 518 sc->sc_flags |= URTWN_DETACHED; 519 URTWN_UNLOCK(sc); 520 521 urtwn_stop(sc); 522 523 callout_drain(&sc->sc_watchdog_ch); 524 525 /* stop all USB transfers */ 526 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 527 528 /* Prevent further allocations from RX/TX data lists. */ 529 URTWN_LOCK(sc); 530 STAILQ_INIT(&sc->sc_tx_active); 531 STAILQ_INIT(&sc->sc_tx_inactive); 532 STAILQ_INIT(&sc->sc_tx_pending); 533 534 STAILQ_INIT(&sc->sc_rx_active); 535 STAILQ_INIT(&sc->sc_rx_inactive); 536 URTWN_UNLOCK(sc); 537 538 /* drain USB transfers */ 539 for (x = 0; x != URTWN_N_TRANSFER; x++) 540 usbd_transfer_drain(sc->sc_xfer[x]); 541 542 /* Free data buffers. */ 543 URTWN_LOCK(sc); 544 urtwn_free_tx_list(sc); 545 urtwn_free_rx_list(sc); 546 URTWN_UNLOCK(sc); 547 548 ieee80211_ifdetach(ic); 549 mtx_destroy(&sc->sc_mtx); 550 551 return (0); 552} 553 554static void 555urtwn_drain_mbufq(struct urtwn_softc *sc) 556{ 557 struct mbuf *m; 558 struct ieee80211_node *ni; 559 URTWN_ASSERT_LOCKED(sc); 560 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 561 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 562 m->m_pkthdr.rcvif = NULL; 563 ieee80211_free_node(ni); 564 m_freem(m); 565 } 566} 567 568static usb_error_t 569urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 570 void *data) 571{ 572 usb_error_t err; 573 int ntries = 10; 574 575 URTWN_ASSERT_LOCKED(sc); 576 577 while (ntries--) { 578 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 579 req, data, 0, NULL, 250 /* ms */); 580 if (err == 0) 581 break; 582 583 DPRINTFN(1, "Control request failed, %s (retrying)\n", 584 usbd_errstr(err)); 585 usb_pause_mtx(&sc->sc_mtx, hz / 100); 586 } 587 return (err); 588} 589 590static struct ieee80211vap * 591urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 592 enum ieee80211_opmode opmode, int flags, 593 const uint8_t bssid[IEEE80211_ADDR_LEN], 594 const uint8_t mac[IEEE80211_ADDR_LEN]) 595{ 596 struct urtwn_softc *sc = ic->ic_softc; 597 struct urtwn_vap *uvp; 598 struct ieee80211vap *vap; 599 600 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 601 return (NULL); 602 603 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 604 vap = &uvp->vap; 605 /* enable s/w bmiss handling for sta mode */ 606 607 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 608 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 609 /* out of memory */ 610 free(uvp, M_80211_VAP); 611 return (NULL); 612 } 613 614 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 615 urtwn_init_beacon(sc, uvp); 616 617 /* override state transition machine */ 618 uvp->newstate = vap->iv_newstate; 619 vap->iv_newstate = urtwn_newstate; 620 vap->iv_update_beacon = urtwn_update_beacon; 621 if (opmode == IEEE80211_M_IBSS) { 622 uvp->recv_mgmt = vap->iv_recv_mgmt; 623 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 624 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 625 } 626 627 /* complete setup */ 628 ieee80211_vap_attach(vap, ieee80211_media_change, 629 ieee80211_media_status, mac); 630 ic->ic_opmode = opmode; 631 return (vap); 632} 633 634static void 635urtwn_vap_delete(struct ieee80211vap *vap) 636{ 637 struct ieee80211com *ic = vap->iv_ic; 638 struct urtwn_vap *uvp = URTWN_VAP(vap); 639 640 if (uvp->bcn_mbuf != NULL) 641 m_freem(uvp->bcn_mbuf); 642 if (vap->iv_opmode == IEEE80211_M_IBSS) 643 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 644 ieee80211_vap_detach(vap); 645 free(uvp, M_80211_VAP); 646} 647 648static struct mbuf * 649urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 650{ 651 struct ieee80211com *ic = &sc->sc_ic; 652 struct ieee80211_frame *wh; 653 struct mbuf *m; 654 struct r92c_rx_stat *stat; 655 uint32_t rxdw0, rxdw3; 656 uint8_t rate; 657 int8_t rssi = 0; 658 int infosz; 659 660 /* 661 * don't pass packets to the ieee80211 framework if the driver isn't 662 * RUNNING. 663 */ 664 if (!(sc->sc_flags & URTWN_RUNNING)) 665 return (NULL); 666 667 stat = (struct r92c_rx_stat *)buf; 668 rxdw0 = le32toh(stat->rxdw0); 669 rxdw3 = le32toh(stat->rxdw3); 670 671 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 672 /* 673 * This should not happen since we setup our Rx filter 674 * to not receive these frames. 675 */ 676 counter_u64_add(ic->ic_ierrors, 1); 677 return (NULL); 678 } 679 if (pktlen < sizeof(struct ieee80211_frame_ack) || 680 pktlen > MCLBYTES) { 681 counter_u64_add(ic->ic_ierrors, 1); 682 return (NULL); 683 } 684 685 rate = MS(rxdw3, R92C_RXDW3_RATE); 686 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 687 688 /* Get RSSI from PHY status descriptor if present. */ 689 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 690 if (sc->chip & URTWN_CHIP_88E) 691 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 692 else 693 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 694 /* Update our average RSSI. */ 695 urtwn_update_avgrssi(sc, rate, rssi); 696 } 697 698 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 699 if (m == NULL) { 700 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 701 return (NULL); 702 } 703 704 /* Finalize mbuf. */ 705 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 706 memcpy(mtod(m, uint8_t *), wh, pktlen); 707 m->m_pkthdr.len = m->m_len = pktlen; 708 709 if (ieee80211_radiotap_active(ic)) { 710 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 711 712 tap->wr_flags = 0; 713 /* Map HW rate index to 802.11 rate. */ 714 if (!(rxdw3 & R92C_RXDW3_HT)) { 715 tap->wr_rate = ridx2rate[rate]; 716 } else if (rate >= 12) { /* MCS0~15. */ 717 /* Bit 7 set means HT MCS instead of rate. */ 718 tap->wr_rate = 0x80 | (rate - 12); 719 } 720 tap->wr_dbm_antsignal = rssi; 721 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 722 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 723 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 724 } 725 726 *rssi_p = rssi; 727 728 return (m); 729} 730 731static struct mbuf * 732urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 733 int8_t *nf) 734{ 735 struct urtwn_softc *sc = data->sc; 736 struct ieee80211com *ic = &sc->sc_ic; 737 struct r92c_rx_stat *stat; 738 struct mbuf *m, *m0 = NULL, *prevm = NULL; 739 uint32_t rxdw0; 740 uint8_t *buf; 741 int len, totlen, pktlen, infosz, npkts; 742 743 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 744 745 if (len < sizeof(*stat)) { 746 counter_u64_add(ic->ic_ierrors, 1); 747 return (NULL); 748 } 749 750 buf = data->buf; 751 /* Get the number of encapsulated frames. */ 752 stat = (struct r92c_rx_stat *)buf; 753 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 754 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 755 756 /* Process all of them. */ 757 while (npkts-- > 0) { 758 if (len < sizeof(*stat)) 759 break; 760 stat = (struct r92c_rx_stat *)buf; 761 rxdw0 = le32toh(stat->rxdw0); 762 763 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 764 if (pktlen == 0) 765 break; 766 767 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 768 769 /* Make sure everything fits in xfer. */ 770 totlen = sizeof(*stat) + infosz + pktlen; 771 if (totlen > len) 772 break; 773 774 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 775 if (m0 == NULL) 776 m0 = m; 777 if (prevm == NULL) 778 prevm = m; 779 else { 780 prevm->m_next = m; 781 prevm = m; 782 } 783 784 /* Next chunk is 128-byte aligned. */ 785 totlen = (totlen + 127) & ~127; 786 buf += totlen; 787 len -= totlen; 788 } 789 790 return (m0); 791} 792 793static void 794urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 795{ 796 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 797 struct ieee80211com *ic = &sc->sc_ic; 798 struct ieee80211_frame_min *wh; 799 struct ieee80211_node *ni; 800 struct mbuf *m = NULL, *next; 801 struct urtwn_data *data; 802 int8_t nf; 803 int rssi = 1; 804 805 URTWN_ASSERT_LOCKED(sc); 806 807 switch (USB_GET_STATE(xfer)) { 808 case USB_ST_TRANSFERRED: 809 data = STAILQ_FIRST(&sc->sc_rx_active); 810 if (data == NULL) 811 goto tr_setup; 812 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 813 m = urtwn_rxeof(xfer, data, &rssi, &nf); 814 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 815 /* FALLTHROUGH */ 816 case USB_ST_SETUP: 817tr_setup: 818 data = STAILQ_FIRST(&sc->sc_rx_inactive); 819 if (data == NULL) { 820 KASSERT(m == NULL, ("mbuf isn't NULL")); 821 return; 822 } 823 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 824 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 825 usbd_xfer_set_frame_data(xfer, 0, data->buf, 826 usbd_xfer_max_len(xfer)); 827 usbd_transfer_submit(xfer); 828 829 /* 830 * To avoid LOR we should unlock our private mutex here to call 831 * ieee80211_input() because here is at the end of a USB 832 * callback and safe to unlock. 833 */ 834 URTWN_UNLOCK(sc); 835 while (m != NULL) { 836 next = m->m_next; 837 m->m_next = NULL; 838 wh = mtod(m, struct ieee80211_frame_min *); 839 if (m->m_len >= sizeof(*wh)) 840 ni = ieee80211_find_rxnode(ic, wh); 841 else 842 ni = NULL; 843 nf = URTWN_NOISE_FLOOR; 844 if (ni != NULL) { 845 (void)ieee80211_input(ni, m, rssi - nf, nf); 846 ieee80211_free_node(ni); 847 } else { 848 (void)ieee80211_input_all(ic, m, rssi - nf, 849 nf); 850 } 851 m = next; 852 } 853 URTWN_LOCK(sc); 854 break; 855 default: 856 /* needs it to the inactive queue due to a error. */ 857 data = STAILQ_FIRST(&sc->sc_rx_active); 858 if (data != NULL) { 859 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 860 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 861 } 862 if (error != USB_ERR_CANCELLED) { 863 usbd_xfer_set_stall(xfer); 864 counter_u64_add(ic->ic_ierrors, 1); 865 goto tr_setup; 866 } 867 break; 868 } 869} 870 871static void 872urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 873{ 874 875 URTWN_ASSERT_LOCKED(sc); 876 877 if (data->ni != NULL) /* not a beacon frame */ 878 ieee80211_tx_complete(data->ni, data->m, status); 879 880 data->ni = NULL; 881 data->m = NULL; 882 883 sc->sc_txtimer = 0; 884 885 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 886} 887 888static int 889urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 890 int ndata, int maxsz) 891{ 892 int i, error; 893 894 for (i = 0; i < ndata; i++) { 895 struct urtwn_data *dp = &data[i]; 896 dp->sc = sc; 897 dp->m = NULL; 898 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 899 if (dp->buf == NULL) { 900 device_printf(sc->sc_dev, 901 "could not allocate buffer\n"); 902 error = ENOMEM; 903 goto fail; 904 } 905 dp->ni = NULL; 906 } 907 908 return (0); 909fail: 910 urtwn_free_list(sc, data, ndata); 911 return (error); 912} 913 914static int 915urtwn_alloc_rx_list(struct urtwn_softc *sc) 916{ 917 int error, i; 918 919 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 920 URTWN_RXBUFSZ); 921 if (error != 0) 922 return (error); 923 924 STAILQ_INIT(&sc->sc_rx_active); 925 STAILQ_INIT(&sc->sc_rx_inactive); 926 927 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 928 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 929 930 return (0); 931} 932 933static int 934urtwn_alloc_tx_list(struct urtwn_softc *sc) 935{ 936 int error, i; 937 938 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 939 URTWN_TXBUFSZ); 940 if (error != 0) 941 return (error); 942 943 STAILQ_INIT(&sc->sc_tx_active); 944 STAILQ_INIT(&sc->sc_tx_inactive); 945 STAILQ_INIT(&sc->sc_tx_pending); 946 947 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 948 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 949 950 return (0); 951} 952 953static void 954urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 955{ 956 int i; 957 958 for (i = 0; i < ndata; i++) { 959 struct urtwn_data *dp = &data[i]; 960 961 if (dp->buf != NULL) { 962 free(dp->buf, M_USBDEV); 963 dp->buf = NULL; 964 } 965 if (dp->ni != NULL) { 966 ieee80211_free_node(dp->ni); 967 dp->ni = NULL; 968 } 969 } 970} 971 972static void 973urtwn_free_rx_list(struct urtwn_softc *sc) 974{ 975 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 976} 977 978static void 979urtwn_free_tx_list(struct urtwn_softc *sc) 980{ 981 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 982} 983 984static void 985urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 986{ 987 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 988 struct urtwn_data *data; 989 990 URTWN_ASSERT_LOCKED(sc); 991 992 switch (USB_GET_STATE(xfer)){ 993 case USB_ST_TRANSFERRED: 994 data = STAILQ_FIRST(&sc->sc_tx_active); 995 if (data == NULL) 996 goto tr_setup; 997 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 998 urtwn_txeof(sc, data, 0); 999 /* FALLTHROUGH */ 1000 case USB_ST_SETUP: 1001tr_setup: 1002 data = STAILQ_FIRST(&sc->sc_tx_pending); 1003 if (data == NULL) { 1004 DPRINTF("%s: empty pending queue\n", __func__); 1005 goto finish; 1006 } 1007 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1008 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1009 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1010 usbd_transfer_submit(xfer); 1011 break; 1012 default: 1013 data = STAILQ_FIRST(&sc->sc_tx_active); 1014 if (data == NULL) 1015 goto tr_setup; 1016 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1017 urtwn_txeof(sc, data, 1); 1018 if (error != USB_ERR_CANCELLED) { 1019 usbd_xfer_set_stall(xfer); 1020 goto tr_setup; 1021 } 1022 break; 1023 } 1024finish: 1025 /* Kick-start more transmit */ 1026 urtwn_start(sc); 1027} 1028 1029static struct urtwn_data * 1030_urtwn_getbuf(struct urtwn_softc *sc) 1031{ 1032 struct urtwn_data *bf; 1033 1034 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1035 if (bf != NULL) 1036 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1037 else 1038 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 1039 return (bf); 1040} 1041 1042static struct urtwn_data * 1043urtwn_getbuf(struct urtwn_softc *sc) 1044{ 1045 struct urtwn_data *bf; 1046 1047 URTWN_ASSERT_LOCKED(sc); 1048 1049 bf = _urtwn_getbuf(sc); 1050 if (bf == NULL) 1051 DPRINTF("%s: stop queue\n", __func__); 1052 return (bf); 1053} 1054 1055static usb_error_t 1056urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1057 int len) 1058{ 1059 usb_device_request_t req; 1060 1061 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1062 req.bRequest = R92C_REQ_REGS; 1063 USETW(req.wValue, addr); 1064 USETW(req.wIndex, 0); 1065 USETW(req.wLength, len); 1066 return (urtwn_do_request(sc, &req, buf)); 1067} 1068 1069static usb_error_t 1070urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1071{ 1072 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1073} 1074 1075static usb_error_t 1076urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1077{ 1078 val = htole16(val); 1079 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1080} 1081 1082static usb_error_t 1083urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1084{ 1085 val = htole32(val); 1086 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1087} 1088 1089static usb_error_t 1090urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1091 int len) 1092{ 1093 usb_device_request_t req; 1094 1095 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1096 req.bRequest = R92C_REQ_REGS; 1097 USETW(req.wValue, addr); 1098 USETW(req.wIndex, 0); 1099 USETW(req.wLength, len); 1100 return (urtwn_do_request(sc, &req, buf)); 1101} 1102 1103static uint8_t 1104urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1105{ 1106 uint8_t val; 1107 1108 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1109 return (0xff); 1110 return (val); 1111} 1112 1113static uint16_t 1114urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1115{ 1116 uint16_t val; 1117 1118 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1119 return (0xffff); 1120 return (le16toh(val)); 1121} 1122 1123static uint32_t 1124urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1125{ 1126 uint32_t val; 1127 1128 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1129 return (0xffffffff); 1130 return (le32toh(val)); 1131} 1132 1133static int 1134urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1135{ 1136 struct r92c_fw_cmd cmd; 1137 usb_error_t error; 1138 int ntries; 1139 1140 /* Wait for current FW box to be empty. */ 1141 for (ntries = 0; ntries < 100; ntries++) { 1142 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1143 break; 1144 urtwn_ms_delay(sc); 1145 } 1146 if (ntries == 100) { 1147 device_printf(sc->sc_dev, 1148 "could not send firmware command\n"); 1149 return (ETIMEDOUT); 1150 } 1151 memset(&cmd, 0, sizeof(cmd)); 1152 cmd.id = id; 1153 if (len > 3) 1154 cmd.id |= R92C_CMD_FLAG_EXT; 1155 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1156 memcpy(cmd.msg, buf, len); 1157 1158 /* Write the first word last since that will trigger the FW. */ 1159 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1160 (uint8_t *)&cmd + 4, 2); 1161 if (error != USB_ERR_NORMAL_COMPLETION) 1162 return (EIO); 1163 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1164 (uint8_t *)&cmd + 0, 4); 1165 if (error != USB_ERR_NORMAL_COMPLETION) 1166 return (EIO); 1167 1168 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1169 return (0); 1170} 1171 1172static __inline void 1173urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1174{ 1175 1176 sc->sc_rf_write(sc, chain, addr, val); 1177} 1178 1179static void 1180urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1181 uint32_t val) 1182{ 1183 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1184 SM(R92C_LSSI_PARAM_ADDR, addr) | 1185 SM(R92C_LSSI_PARAM_DATA, val)); 1186} 1187 1188static void 1189urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1190uint32_t val) 1191{ 1192 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1193 SM(R88E_LSSI_PARAM_ADDR, addr) | 1194 SM(R92C_LSSI_PARAM_DATA, val)); 1195} 1196 1197static uint32_t 1198urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1199{ 1200 uint32_t reg[R92C_MAX_CHAINS], val; 1201 1202 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1203 if (chain != 0) 1204 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1205 1206 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1207 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1208 urtwn_ms_delay(sc); 1209 1210 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1211 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1212 R92C_HSSI_PARAM2_READ_EDGE); 1213 urtwn_ms_delay(sc); 1214 1215 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1216 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1217 urtwn_ms_delay(sc); 1218 1219 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1220 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1221 else 1222 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1223 return (MS(val, R92C_LSSI_READBACK_DATA)); 1224} 1225 1226static int 1227urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1228{ 1229 usb_error_t error; 1230 int ntries; 1231 1232 error = urtwn_write_4(sc, R92C_LLT_INIT, 1233 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1234 SM(R92C_LLT_INIT_ADDR, addr) | 1235 SM(R92C_LLT_INIT_DATA, data)); 1236 if (error != USB_ERR_NORMAL_COMPLETION) 1237 return (EIO); 1238 /* Wait for write operation to complete. */ 1239 for (ntries = 0; ntries < 20; ntries++) { 1240 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1241 R92C_LLT_INIT_OP_NO_ACTIVE) 1242 return (0); 1243 urtwn_ms_delay(sc); 1244 } 1245 return (ETIMEDOUT); 1246} 1247 1248static int 1249urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1250{ 1251 uint32_t reg; 1252 usb_error_t error; 1253 int ntries; 1254 1255 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1256 return (EFAULT); 1257 1258 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1259 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1260 reg &= ~R92C_EFUSE_CTRL_VALID; 1261 1262 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1263 if (error != USB_ERR_NORMAL_COMPLETION) 1264 return (EIO); 1265 /* Wait for read operation to complete. */ 1266 for (ntries = 0; ntries < 100; ntries++) { 1267 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1268 if (reg & R92C_EFUSE_CTRL_VALID) 1269 break; 1270 urtwn_ms_delay(sc); 1271 } 1272 if (ntries == 100) { 1273 device_printf(sc->sc_dev, 1274 "could not read efuse byte at address 0x%x\n", 1275 sc->last_rom_addr); 1276 return (ETIMEDOUT); 1277 } 1278 1279 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1280 sc->last_rom_addr++; 1281 1282 return (0); 1283} 1284 1285static int 1286urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1287 uint8_t msk) 1288{ 1289 uint8_t reg; 1290 int i, error; 1291 1292 for (i = 0; i < 4; i++) { 1293 if (msk & (1 << i)) 1294 continue; 1295 error = urtwn_efuse_read_next(sc, ®); 1296 if (error != 0) 1297 return (error); 1298 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2, reg); 1299 rom[off * 8 + i * 2 + 0] = reg; 1300 1301 error = urtwn_efuse_read_next(sc, ®); 1302 if (error != 0) 1303 return (error); 1304 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2 + 1, reg); 1305 rom[off * 8 + i * 2 + 1] = reg; 1306 } 1307 1308 return (0); 1309} 1310 1311#ifdef URTWN_DEBUG 1312static void 1313urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1314{ 1315 int i; 1316 1317 /* Dump ROM contents. */ 1318 device_printf(sc->sc_dev, "%s:", __func__); 1319 for (i = 0; i < size; i++) { 1320 if (i % 32 == 0) 1321 printf("\n%03X: ", i); 1322 else if (i % 4 == 0) 1323 printf(" "); 1324 1325 printf("%02X", rom[i]); 1326 } 1327 printf("\n"); 1328} 1329#endif 1330 1331static int 1332urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1333{ 1334#define URTWN_CHK(res) do { \ 1335 if ((error = res) != 0) \ 1336 goto end; \ 1337} while(0) 1338 uint8_t msk, off, reg; 1339 int error; 1340 1341 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1342 1343 /* Read full ROM image. */ 1344 sc->last_rom_addr = 0; 1345 memset(rom, 0xff, size); 1346 1347 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1348 while (reg != 0xff) { 1349 /* check for extended header */ 1350 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1351 off = reg >> 5; 1352 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1353 1354 if ((reg & 0x0f) != 0x0f) 1355 off = ((reg & 0xf0) >> 1) | off; 1356 else 1357 continue; 1358 } else 1359 off = reg >> 4; 1360 msk = reg & 0xf; 1361 1362 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1363 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1364 } 1365 1366end: 1367 1368#ifdef URTWN_DEBUG 1369 if (urtwn_debug >= 2) 1370 urtwn_dump_rom_contents(sc, rom, size); 1371#endif 1372 1373 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1374 1375 if (error != 0) { 1376 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1377 __func__); 1378 } 1379 1380 return (error); 1381#undef URTWN_CHK 1382} 1383 1384static int 1385urtwn_efuse_switch_power(struct urtwn_softc *sc) 1386{ 1387 usb_error_t error; 1388 uint32_t reg; 1389 1390 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1391 if (error != USB_ERR_NORMAL_COMPLETION) 1392 return (EIO); 1393 1394 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1395 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1396 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1397 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1398 if (error != USB_ERR_NORMAL_COMPLETION) 1399 return (EIO); 1400 } 1401 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1402 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1403 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1404 reg | R92C_SYS_FUNC_EN_ELDR); 1405 if (error != USB_ERR_NORMAL_COMPLETION) 1406 return (EIO); 1407 } 1408 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1409 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1410 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1411 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1412 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1413 if (error != USB_ERR_NORMAL_COMPLETION) 1414 return (EIO); 1415 } 1416 1417 return (0); 1418} 1419 1420static int 1421urtwn_read_chipid(struct urtwn_softc *sc) 1422{ 1423 uint32_t reg; 1424 1425 if (sc->chip & URTWN_CHIP_88E) 1426 return (0); 1427 1428 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1429 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1430 return (EIO); 1431 1432 if (reg & R92C_SYS_CFG_TYPE_92C) { 1433 sc->chip |= URTWN_CHIP_92C; 1434 /* Check if it is a castrated 8192C. */ 1435 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1436 R92C_HPON_FSM_CHIP_BONDING_ID) == 1437 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1438 sc->chip |= URTWN_CHIP_92C_1T2R; 1439 } 1440 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1441 sc->chip |= URTWN_CHIP_UMC; 1442 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1443 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1444 } 1445 return (0); 1446} 1447 1448static int 1449urtwn_read_rom(struct urtwn_softc *sc) 1450{ 1451 struct r92c_rom *rom = &sc->rom.r92c_rom; 1452 int error; 1453 1454 /* Read full ROM image. */ 1455 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1456 if (error != 0) 1457 return (error); 1458 1459 /* XXX Weird but this is what the vendor driver does. */ 1460 sc->last_rom_addr = 0x1fa; 1461 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1462 if (error != 0) 1463 return (error); 1464 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1465 1466 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1467 1468 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1469 DPRINTF("regulatory type=%d\n", sc->regulatory); 1470 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1471 1472 sc->sc_rf_write = urtwn_r92c_rf_write; 1473 sc->sc_power_on = urtwn_r92c_power_on; 1474 sc->sc_dma_init = urtwn_r92c_dma_init; 1475 1476 return (0); 1477} 1478 1479static int 1480urtwn_r88e_read_rom(struct urtwn_softc *sc) 1481{ 1482 uint8_t *rom = sc->rom.r88e_rom; 1483 uint16_t addr; 1484 int error, i; 1485 1486 error = urtwn_efuse_read(sc, rom, sizeof(sc->rom.r88e_rom)); 1487 if (error != 0) 1488 return (error); 1489 1490 addr = 0x10; 1491 for (i = 0; i < 6; i++) 1492 sc->cck_tx_pwr[i] = rom[addr++]; 1493 for (i = 0; i < 5; i++) 1494 sc->ht40_tx_pwr[i] = rom[addr++]; 1495 sc->bw20_tx_pwr_diff = (rom[addr] & 0xf0) >> 4; 1496 if (sc->bw20_tx_pwr_diff & 0x08) 1497 sc->bw20_tx_pwr_diff |= 0xf0; 1498 sc->ofdm_tx_pwr_diff = (rom[addr] & 0xf); 1499 if (sc->ofdm_tx_pwr_diff & 0x08) 1500 sc->ofdm_tx_pwr_diff |= 0xf0; 1501 sc->regulatory = MS(rom[0xc1], R92C_ROM_RF1_REGULATORY); 1502 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &rom[0xd7]); 1503 1504 sc->sc_rf_write = urtwn_r88e_rf_write; 1505 sc->sc_power_on = urtwn_r88e_power_on; 1506 sc->sc_dma_init = urtwn_r88e_dma_init; 1507 1508 return (0); 1509} 1510 1511/* 1512 * Initialize rate adaptation in firmware. 1513 */ 1514static int 1515urtwn_ra_init(struct urtwn_softc *sc) 1516{ 1517 struct ieee80211com *ic = &sc->sc_ic; 1518 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1519 struct ieee80211_node *ni; 1520 struct ieee80211_rateset *rs; 1521 struct r92c_fw_cmd_macid_cfg cmd; 1522 uint32_t rates, basicrates; 1523 uint8_t mode; 1524 int maxrate, maxbasicrate, error, i, j; 1525 1526 ni = ieee80211_ref_node(vap->iv_bss); 1527 rs = &ni->ni_rates; 1528 1529 /* Get normal and basic rates mask. */ 1530 rates = basicrates = 0; 1531 maxrate = maxbasicrate = 0; 1532 for (i = 0; i < rs->rs_nrates; i++) { 1533 /* Convert 802.11 rate to HW rate index. */ 1534 for (j = 0; j < nitems(ridx2rate); j++) 1535 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1536 ridx2rate[j]) 1537 break; 1538 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1539 continue; 1540 rates |= 1 << j; 1541 if (j > maxrate) 1542 maxrate = j; 1543 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1544 basicrates |= 1 << j; 1545 if (j > maxbasicrate) 1546 maxbasicrate = j; 1547 } 1548 } 1549 if (ic->ic_curmode == IEEE80211_MODE_11B) 1550 mode = R92C_RAID_11B; 1551 else 1552 mode = R92C_RAID_11BG; 1553 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1554 mode, rates, basicrates); 1555 1556 /* Set rates mask for group addressed frames. */ 1557 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1558 cmd.mask = htole32(mode << 28 | basicrates); 1559 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1560 if (error != 0) { 1561 ieee80211_free_node(ni); 1562 device_printf(sc->sc_dev, 1563 "could not add broadcast station\n"); 1564 return (error); 1565 } 1566 /* Set initial MRR rate. */ 1567 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1568 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1569 maxbasicrate); 1570 1571 /* Set rates mask for unicast frames. */ 1572 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1573 cmd.mask = htole32(mode << 28 | rates); 1574 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1575 if (error != 0) { 1576 ieee80211_free_node(ni); 1577 device_printf(sc->sc_dev, "could not add BSS station\n"); 1578 return (error); 1579 } 1580 /* Set initial MRR rate. */ 1581 DPRINTF("maxrate=%d\n", maxrate); 1582 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1583 maxrate); 1584 1585 /* Indicate highest supported rate. */ 1586 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1587 ieee80211_free_node(ni); 1588 1589 return (0); 1590} 1591 1592static void 1593urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1594{ 1595 struct r92c_tx_desc *txd = &uvp->bcn_desc; 1596 1597 txd->txdw0 = htole32( 1598 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 1599 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1600 txd->txdw1 = htole32( 1601 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 1602 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1603 1604 if (sc->chip & URTWN_CHIP_88E) { 1605 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 1606 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 1607 } else { 1608 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 1609 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 1610 } 1611 1612 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 1613 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 1614} 1615 1616static int 1617urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 1618{ 1619 struct ieee80211vap *vap = ni->ni_vap; 1620 struct urtwn_vap *uvp = URTWN_VAP(vap); 1621 struct mbuf *m; 1622 int error; 1623 1624 URTWN_ASSERT_LOCKED(sc); 1625 1626 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 1627 return (EINVAL); 1628 1629 m = ieee80211_beacon_alloc(ni); 1630 if (m == NULL) { 1631 device_printf(sc->sc_dev, 1632 "%s: could not allocate beacon frame\n", __func__); 1633 return (ENOMEM); 1634 } 1635 1636 if (uvp->bcn_mbuf != NULL) 1637 m_freem(uvp->bcn_mbuf); 1638 1639 uvp->bcn_mbuf = m; 1640 1641 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1642 return (error); 1643 1644 /* XXX bcnq stuck workaround */ 1645 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1646 return (error); 1647 1648 return (0); 1649} 1650 1651static void 1652urtwn_update_beacon(struct ieee80211vap *vap, int item) 1653{ 1654 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1655 struct urtwn_vap *uvp = URTWN_VAP(vap); 1656 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 1657 struct ieee80211_node *ni = vap->iv_bss; 1658 int mcast = 0; 1659 1660 URTWN_LOCK(sc); 1661 if (uvp->bcn_mbuf == NULL) { 1662 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 1663 if (uvp->bcn_mbuf == NULL) { 1664 device_printf(sc->sc_dev, 1665 "%s: could not allocate beacon frame\n", __func__); 1666 URTWN_UNLOCK(sc); 1667 return; 1668 } 1669 } 1670 URTWN_UNLOCK(sc); 1671 1672 if (item == IEEE80211_BEACON_TIM) 1673 mcast = 1; /* XXX */ 1674 1675 setbit(bo->bo_flags, item); 1676 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 1677 1678 URTWN_LOCK(sc); 1679 urtwn_tx_beacon(sc, uvp); 1680 URTWN_UNLOCK(sc); 1681} 1682 1683/* 1684 * Push a beacon frame into the chip. Beacon will 1685 * be repeated by the chip every R92C_BCN_INTERVAL. 1686 */ 1687static int 1688urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1689{ 1690 struct r92c_tx_desc *desc = &uvp->bcn_desc; 1691 struct urtwn_data *bf; 1692 1693 URTWN_ASSERT_LOCKED(sc); 1694 1695 bf = urtwn_getbuf(sc); 1696 if (bf == NULL) 1697 return (ENOMEM); 1698 1699 memcpy(bf->buf, desc, sizeof(*desc)); 1700 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 1701 1702 sc->sc_txtimer = 5; 1703 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1704 1705 return (0); 1706} 1707 1708static void 1709urtwn_tsf_task_adhoc(void *arg, int pending) 1710{ 1711 struct ieee80211vap *vap = arg; 1712 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1713 struct ieee80211_node *ni; 1714 uint32_t reg; 1715 1716 URTWN_LOCK(sc); 1717 ni = ieee80211_ref_node(vap->iv_bss); 1718 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 1719 1720 /* Accept beacons with the same BSSID. */ 1721 urtwn_set_rx_bssid_all(sc, 0); 1722 1723 /* Enable synchronization. */ 1724 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 1725 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1726 1727 /* Synchronize. */ 1728 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 1729 1730 /* Disable synchronization. */ 1731 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 1732 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1733 1734 /* Remove beacon filter. */ 1735 urtwn_set_rx_bssid_all(sc, 1); 1736 1737 /* Enable beaconing. */ 1738 urtwn_write_1(sc, R92C_MBID_NUM, 1739 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 1740 reg |= R92C_BCN_CTRL_EN_BCN; 1741 1742 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1743 ieee80211_free_node(ni); 1744 URTWN_UNLOCK(sc); 1745} 1746 1747static void 1748urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 1749{ 1750 struct ieee80211com *ic = &sc->sc_ic; 1751 struct urtwn_vap *uvp = URTWN_VAP(vap); 1752 1753 /* Reset TSF. */ 1754 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 1755 1756 switch (vap->iv_opmode) { 1757 case IEEE80211_M_STA: 1758 /* Enable TSF synchronization. */ 1759 urtwn_write_1(sc, R92C_BCN_CTRL, 1760 urtwn_read_1(sc, R92C_BCN_CTRL) & 1761 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1762 break; 1763 case IEEE80211_M_IBSS: 1764 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 1765 break; 1766 case IEEE80211_M_HOSTAP: 1767 /* Enable beaconing. */ 1768 urtwn_write_1(sc, R92C_MBID_NUM, 1769 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 1770 urtwn_write_1(sc, R92C_BCN_CTRL, 1771 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1772 break; 1773 default: 1774 device_printf(sc->sc_dev, "undefined opmode %d\n", 1775 vap->iv_opmode); 1776 return; 1777 } 1778} 1779 1780static void 1781urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1782{ 1783 uint8_t reg; 1784 1785 if (led == URTWN_LED_LINK) { 1786 if (sc->chip & URTWN_CHIP_88E) { 1787 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1788 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1789 if (!on) { 1790 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1791 urtwn_write_1(sc, R92C_LEDCFG2, 1792 reg | R92C_LEDCFG0_DIS); 1793 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1794 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1795 0xfe); 1796 } 1797 } else { 1798 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1799 if (!on) 1800 reg |= R92C_LEDCFG0_DIS; 1801 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1802 } 1803 sc->ledlink = on; /* Save LED state. */ 1804 } 1805} 1806 1807static void 1808urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 1809{ 1810 uint8_t reg; 1811 1812 reg = urtwn_read_1(sc, R92C_MSR); 1813 reg = (reg & ~R92C_MSR_MASK) | mode; 1814 urtwn_write_1(sc, R92C_MSR, reg); 1815} 1816 1817static void 1818urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 1819 const struct ieee80211_rx_stats *rxs, 1820 int rssi, int nf) 1821{ 1822 struct ieee80211vap *vap = ni->ni_vap; 1823 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1824 struct urtwn_vap *uvp = URTWN_VAP(vap); 1825 uint64_t ni_tstamp, curr_tstamp; 1826 1827 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 1828 1829 if (vap->iv_state == IEEE80211_S_RUN && 1830 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 1831 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 1832 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 1833#ifdef D3831 1834 URTWN_LOCK(sc); 1835 urtwn_get_tsf(sc, &curr_tstamp); 1836 URTWN_UNLOCK(sc); 1837 curr_tstamp = le64toh(curr_tstamp); 1838 1839 if (ni_tstamp >= curr_tstamp) 1840 (void) ieee80211_ibss_merge(ni); 1841#else 1842 (void) sc; 1843 (void) curr_tstamp; 1844#endif 1845 } 1846} 1847 1848static int 1849urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1850{ 1851 struct urtwn_vap *uvp = URTWN_VAP(vap); 1852 struct ieee80211com *ic = vap->iv_ic; 1853 struct urtwn_softc *sc = ic->ic_softc; 1854 struct ieee80211_node *ni; 1855 enum ieee80211_state ostate; 1856 uint32_t reg; 1857 uint8_t mode; 1858 int error = 0; 1859 1860 ostate = vap->iv_state; 1861 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1862 ieee80211_state_name[nstate]); 1863 1864 IEEE80211_UNLOCK(ic); 1865 URTWN_LOCK(sc); 1866 callout_stop(&sc->sc_watchdog_ch); 1867 1868 if (ostate == IEEE80211_S_RUN) { 1869 /* Turn link LED off. */ 1870 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1871 1872 /* Set media status to 'No Link'. */ 1873 urtwn_set_mode(sc, R92C_MSR_NOLINK); 1874 1875 /* Stop Rx of data frames. */ 1876 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1877 1878 /* Disable TSF synchronization. */ 1879 urtwn_write_1(sc, R92C_BCN_CTRL, 1880 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 1881 R92C_BCN_CTRL_DIS_TSF_UDT0); 1882 1883 /* Disable beaconing. */ 1884 urtwn_write_1(sc, R92C_MBID_NUM, 1885 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 1886 1887 /* Reset TSF. */ 1888 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 1889 1890 /* Reset EDCA parameters. */ 1891 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1892 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1893 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1894 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1895 } 1896 1897 switch (nstate) { 1898 case IEEE80211_S_INIT: 1899 /* Turn link LED off. */ 1900 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1901 break; 1902 case IEEE80211_S_SCAN: 1903 /* Pause AC Tx queues. */ 1904 urtwn_write_1(sc, R92C_TXPAUSE, 1905 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1906 break; 1907 case IEEE80211_S_AUTH: 1908 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1909 break; 1910 case IEEE80211_S_RUN: 1911 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1912 /* Turn link LED on. */ 1913 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1914 break; 1915 } 1916 1917 ni = ieee80211_ref_node(vap->iv_bss); 1918 1919 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 1920 ni->ni_chan == IEEE80211_CHAN_ANYC) { 1921 device_printf(sc->sc_dev, 1922 "%s: could not move to RUN state\n", __func__); 1923 error = EINVAL; 1924 goto end_run; 1925 } 1926 1927 switch (vap->iv_opmode) { 1928 case IEEE80211_M_STA: 1929 mode = R92C_MSR_INFRA; 1930 break; 1931 case IEEE80211_M_IBSS: 1932 mode = R92C_MSR_ADHOC; 1933 break; 1934 case IEEE80211_M_HOSTAP: 1935 mode = R92C_MSR_AP; 1936 break; 1937 default: 1938 device_printf(sc->sc_dev, "undefined opmode %d\n", 1939 vap->iv_opmode); 1940 error = EINVAL; 1941 goto end_run; 1942 } 1943 1944 /* Set media status to 'Associated'. */ 1945 urtwn_set_mode(sc, mode); 1946 1947 /* Set BSSID. */ 1948 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1949 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1950 1951 if (ic->ic_curmode == IEEE80211_MODE_11B) 1952 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1953 else /* 802.11b/g */ 1954 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1955 1956 /* Enable Rx of data frames. */ 1957 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1958 1959 /* Flush all AC queues. */ 1960 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1961 1962 /* Set beacon interval. */ 1963 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1964 1965 /* Allow Rx from our BSSID only. */ 1966 if (ic->ic_promisc == 0) { 1967 reg = urtwn_read_4(sc, R92C_RCR); 1968 1969 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 1970 reg |= R92C_RCR_CBSSID_DATA; 1971 if (vap->iv_opmode != IEEE80211_M_IBSS) 1972 reg |= R92C_RCR_CBSSID_BCN; 1973 1974 urtwn_write_4(sc, R92C_RCR, reg); 1975 } 1976 1977 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1978 vap->iv_opmode == IEEE80211_M_IBSS) { 1979 error = urtwn_setup_beacon(sc, ni); 1980 if (error != 0) { 1981 device_printf(sc->sc_dev, 1982 "unable to push beacon into the chip, " 1983 "error %d\n", error); 1984 goto end_run; 1985 } 1986 } 1987 1988 /* Enable TSF synchronization. */ 1989 urtwn_tsf_sync_enable(sc, vap); 1990 1991 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1992 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1993 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1994 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1995 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1996 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1997 1998 /* Intialize rate adaptation. */ 1999 if (sc->chip & URTWN_CHIP_88E) 2000 ni->ni_txrate = 2001 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 2002 else 2003 urtwn_ra_init(sc); 2004 /* Turn link LED on. */ 2005 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2006 2007 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2008 /* Reset temperature calibration state machine. */ 2009 sc->thcal_state = 0; 2010 sc->thcal_lctemp = 0; 2011 2012end_run: 2013 ieee80211_free_node(ni); 2014 break; 2015 default: 2016 break; 2017 } 2018 2019 URTWN_UNLOCK(sc); 2020 IEEE80211_LOCK(ic); 2021 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2022} 2023 2024static void 2025urtwn_watchdog(void *arg) 2026{ 2027 struct urtwn_softc *sc = arg; 2028 2029 if (sc->sc_txtimer > 0) { 2030 if (--sc->sc_txtimer == 0) { 2031 device_printf(sc->sc_dev, "device timeout\n"); 2032 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2033 return; 2034 } 2035 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2036 } 2037} 2038 2039static void 2040urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2041{ 2042 int pwdb; 2043 2044 /* Convert antenna signal to percentage. */ 2045 if (rssi <= -100 || rssi >= 20) 2046 pwdb = 0; 2047 else if (rssi >= 0) 2048 pwdb = 100; 2049 else 2050 pwdb = 100 + rssi; 2051 if (!(sc->chip & URTWN_CHIP_88E)) { 2052 if (rate <= URTWN_RIDX_CCK11) { 2053 /* CCK gain is smaller than OFDM/MCS gain. */ 2054 pwdb += 6; 2055 if (pwdb > 100) 2056 pwdb = 100; 2057 if (pwdb <= 14) 2058 pwdb -= 4; 2059 else if (pwdb <= 26) 2060 pwdb -= 8; 2061 else if (pwdb <= 34) 2062 pwdb -= 6; 2063 else if (pwdb <= 42) 2064 pwdb -= 2; 2065 } 2066 } 2067 if (sc->avg_pwdb == -1) /* Init. */ 2068 sc->avg_pwdb = pwdb; 2069 else if (sc->avg_pwdb < pwdb) 2070 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2071 else 2072 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2073 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 2074} 2075 2076static int8_t 2077urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2078{ 2079 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2080 struct r92c_rx_phystat *phy; 2081 struct r92c_rx_cck *cck; 2082 uint8_t rpt; 2083 int8_t rssi; 2084 2085 if (rate <= URTWN_RIDX_CCK11) { 2086 cck = (struct r92c_rx_cck *)physt; 2087 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2088 rpt = (cck->agc_rpt >> 5) & 0x3; 2089 rssi = (cck->agc_rpt & 0x1f) << 1; 2090 } else { 2091 rpt = (cck->agc_rpt >> 6) & 0x3; 2092 rssi = cck->agc_rpt & 0x3e; 2093 } 2094 rssi = cckoff[rpt] - rssi; 2095 } else { /* OFDM/HT. */ 2096 phy = (struct r92c_rx_phystat *)physt; 2097 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2098 } 2099 return (rssi); 2100} 2101 2102static int8_t 2103urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2104{ 2105 struct r92c_rx_phystat *phy; 2106 struct r88e_rx_cck *cck; 2107 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2108 int8_t rssi; 2109 2110 rssi = 0; 2111 if (rate <= URTWN_RIDX_CCK11) { 2112 cck = (struct r88e_rx_cck *)physt; 2113 cck_agc_rpt = cck->agc_rpt; 2114 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2115 vga_idx = cck_agc_rpt & 0x1f; 2116 switch (lna_idx) { 2117 case 7: 2118 if (vga_idx <= 27) 2119 rssi = -100 + 2* (27 - vga_idx); 2120 else 2121 rssi = -100; 2122 break; 2123 case 6: 2124 rssi = -48 + 2 * (2 - vga_idx); 2125 break; 2126 case 5: 2127 rssi = -42 + 2 * (7 - vga_idx); 2128 break; 2129 case 4: 2130 rssi = -36 + 2 * (7 - vga_idx); 2131 break; 2132 case 3: 2133 rssi = -24 + 2 * (7 - vga_idx); 2134 break; 2135 case 2: 2136 rssi = -12 + 2 * (5 - vga_idx); 2137 break; 2138 case 1: 2139 rssi = 8 - (2 * vga_idx); 2140 break; 2141 case 0: 2142 rssi = 14 - (2 * vga_idx); 2143 break; 2144 } 2145 rssi += 6; 2146 } else { /* OFDM/HT. */ 2147 phy = (struct r92c_rx_phystat *)physt; 2148 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2149 } 2150 return (rssi); 2151} 2152 2153static int 2154urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2155 struct mbuf *m, struct urtwn_data *data) 2156{ 2157 struct ieee80211_frame *wh; 2158 struct ieee80211_key *k = NULL; 2159 struct ieee80211com *ic = &sc->sc_ic; 2160 struct ieee80211vap *vap = ni->ni_vap; 2161 struct r92c_tx_desc *txd; 2162 uint8_t macid, raid, ridx, subtype, type, qsel; 2163 int ismcast; 2164 2165 URTWN_ASSERT_LOCKED(sc); 2166 2167 /* 2168 * Software crypto. 2169 */ 2170 wh = mtod(m, struct ieee80211_frame *); 2171 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2172 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2173 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2174 2175 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2176 k = ieee80211_crypto_encap(ni, m); 2177 if (k == NULL) { 2178 device_printf(sc->sc_dev, 2179 "ieee80211_crypto_encap returns NULL.\n"); 2180 return (ENOBUFS); 2181 } 2182 2183 /* in case packet header moved, reset pointer */ 2184 wh = mtod(m, struct ieee80211_frame *); 2185 } 2186 2187 /* Fill Tx descriptor. */ 2188 txd = (struct r92c_tx_desc *)data->buf; 2189 memset(txd, 0, sizeof(*txd)); 2190 2191 txd->txdw0 |= htole32( 2192 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2193 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2194 if (ismcast) 2195 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2196 2197 raid = R92C_RAID_11B; /* by default */ 2198 ridx = URTWN_RIDX_CCK1; 2199 if (!ismcast) { 2200 macid = URTWN_MACID_BSS; 2201 2202 if (type == IEEE80211_FC0_TYPE_DATA) { 2203 qsel = R92C_TXDW1_QSEL_BE; 2204 2205 if (!(m->m_flags & M_EAPOL)) { 2206 if (ic->ic_curmode != IEEE80211_MODE_11B) { 2207 raid = R92C_RAID_11BG; 2208 ridx = URTWN_RIDX_OFDM54; 2209 } else 2210 ridx = URTWN_RIDX_CCK11; 2211 } 2212 2213 if (sc->chip & URTWN_CHIP_88E) 2214 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2215 else 2216 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2217 2218 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2219 switch (ic->ic_protmode) { 2220 case IEEE80211_PROT_CTSONLY: 2221 txd->txdw4 |= htole32( 2222 R92C_TXDW4_CTS2SELF | 2223 R92C_TXDW4_HWRTSEN); 2224 break; 2225 case IEEE80211_PROT_RTSCTS: 2226 txd->txdw4 |= htole32( 2227 R92C_TXDW4_RTSEN | 2228 R92C_TXDW4_HWRTSEN); 2229 break; 2230 default: 2231 break; 2232 } 2233 } 2234 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2235 URTWN_RIDX_OFDM24)); 2236 txd->txdw5 |= htole32(0x0001ff00); 2237 } else /* IEEE80211_FC0_TYPE_MGT */ 2238 qsel = R92C_TXDW1_QSEL_MGNT; 2239 } else { 2240 macid = URTWN_MACID_BC; 2241 qsel = R92C_TXDW1_QSEL_MGNT; 2242 } 2243 2244 txd->txdw1 |= htole32( 2245 SM(R92C_TXDW1_QSEL, qsel) | 2246 SM(R92C_TXDW1_RAID, raid)); 2247 2248 if (sc->chip & URTWN_CHIP_88E) 2249 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 2250 else 2251 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 2252 2253 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2254 /* Force this rate if needed. */ 2255 if (ismcast || type != IEEE80211_FC0_TYPE_DATA || 2256 (m->m_flags & M_EAPOL)) 2257 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2258 2259 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 2260 /* Use HW sequence numbering for non-QoS frames. */ 2261 if (sc->chip & URTWN_CHIP_88E) 2262 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2263 else 2264 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2265 } else { 2266 /* Set sequence number. */ 2267 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2268 } 2269 2270 if (ieee80211_radiotap_active_vap(vap)) { 2271 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2272 2273 tap->wt_flags = 0; 2274 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2275 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2276 if (k != NULL) 2277 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2278 ieee80211_radiotap_tx(vap, m); 2279 } 2280 2281 data->ni = ni; 2282 2283 urtwn_tx_start(sc, m, type, data); 2284 2285 return (0); 2286} 2287 2288static void 2289urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 2290 struct urtwn_data *data) 2291{ 2292 struct usb_xfer *xfer; 2293 struct r92c_tx_desc *txd; 2294 uint16_t ac, sum; 2295 int i, xferlen; 2296 struct usb_xfer *urtwn_pipes[WME_NUM_AC] = { 2297 sc->sc_xfer[URTWN_BULK_TX_BE], 2298 sc->sc_xfer[URTWN_BULK_TX_BK], 2299 sc->sc_xfer[URTWN_BULK_TX_VI], 2300 sc->sc_xfer[URTWN_BULK_TX_VO] 2301 }; 2302 2303 URTWN_ASSERT_LOCKED(sc); 2304 2305 ac = M_WME_GETAC(m); 2306 2307 switch (type) { 2308 case IEEE80211_FC0_TYPE_CTL: 2309 case IEEE80211_FC0_TYPE_MGT: 2310 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 2311 break; 2312 default: 2313 xfer = urtwn_pipes[ac]; 2314 break; 2315 } 2316 2317 txd = (struct r92c_tx_desc *)data->buf; 2318 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 2319 2320 /* Compute Tx descriptor checksum. */ 2321 sum = 0; 2322 for (i = 0; i < sizeof(*txd) / 2; i++) 2323 sum ^= ((uint16_t *)txd)[i]; 2324 txd->txdsum = sum; /* NB: already little endian. */ 2325 2326 xferlen = sizeof(*txd) + m->m_pkthdr.len; 2327 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 2328 2329 data->buflen = xferlen; 2330 data->m = m; 2331 2332 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 2333 usbd_transfer_start(xfer); 2334} 2335 2336static int 2337urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 2338{ 2339 struct urtwn_softc *sc = ic->ic_softc; 2340 int error; 2341 2342 URTWN_LOCK(sc); 2343 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2344 URTWN_UNLOCK(sc); 2345 return (ENXIO); 2346 } 2347 error = mbufq_enqueue(&sc->sc_snd, m); 2348 if (error) { 2349 URTWN_UNLOCK(sc); 2350 return (error); 2351 } 2352 urtwn_start(sc); 2353 URTWN_UNLOCK(sc); 2354 2355 return (0); 2356} 2357 2358static void 2359urtwn_start(struct urtwn_softc *sc) 2360{ 2361 struct ieee80211_node *ni; 2362 struct mbuf *m; 2363 struct urtwn_data *bf; 2364 2365 URTWN_ASSERT_LOCKED(sc); 2366 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2367 bf = urtwn_getbuf(sc); 2368 if (bf == NULL) { 2369 mbufq_prepend(&sc->sc_snd, m); 2370 break; 2371 } 2372 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2373 m->m_pkthdr.rcvif = NULL; 2374 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 2375 if_inc_counter(ni->ni_vap->iv_ifp, 2376 IFCOUNTER_OERRORS, 1); 2377 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2378 m_freem(m); 2379 ieee80211_free_node(ni); 2380 break; 2381 } 2382 sc->sc_txtimer = 5; 2383 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2384 } 2385} 2386 2387static void 2388urtwn_parent(struct ieee80211com *ic) 2389{ 2390 struct urtwn_softc *sc = ic->ic_softc; 2391 2392 URTWN_LOCK(sc); 2393 if (sc->sc_flags & URTWN_DETACHED) { 2394 URTWN_UNLOCK(sc); 2395 return; 2396 } 2397 URTWN_UNLOCK(sc); 2398 2399 if (ic->ic_nrunning > 0) { 2400 if (urtwn_init(sc) != 0) { 2401 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2402 if (vap != NULL) 2403 ieee80211_stop(vap); 2404 } else 2405 ieee80211_start_all(ic); 2406 } else 2407 urtwn_stop(sc); 2408} 2409 2410static __inline int 2411urtwn_power_on(struct urtwn_softc *sc) 2412{ 2413 2414 return sc->sc_power_on(sc); 2415} 2416 2417static int 2418urtwn_r92c_power_on(struct urtwn_softc *sc) 2419{ 2420 uint32_t reg; 2421 usb_error_t error; 2422 int ntries; 2423 2424 /* Wait for autoload done bit. */ 2425 for (ntries = 0; ntries < 1000; ntries++) { 2426 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2427 break; 2428 urtwn_ms_delay(sc); 2429 } 2430 if (ntries == 1000) { 2431 device_printf(sc->sc_dev, 2432 "timeout waiting for chip autoload\n"); 2433 return (ETIMEDOUT); 2434 } 2435 2436 /* Unlock ISO/CLK/Power control register. */ 2437 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2438 if (error != USB_ERR_NORMAL_COMPLETION) 2439 return (EIO); 2440 /* Move SPS into PWM mode. */ 2441 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2442 if (error != USB_ERR_NORMAL_COMPLETION) 2443 return (EIO); 2444 urtwn_ms_delay(sc); 2445 2446 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2447 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2448 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2449 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2450 if (error != USB_ERR_NORMAL_COMPLETION) 2451 return (EIO); 2452 urtwn_ms_delay(sc); 2453 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2454 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2455 ~R92C_SYS_ISO_CTRL_MD2PP); 2456 if (error != USB_ERR_NORMAL_COMPLETION) 2457 return (EIO); 2458 } 2459 2460 /* Auto enable WLAN. */ 2461 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2462 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2463 if (error != USB_ERR_NORMAL_COMPLETION) 2464 return (EIO); 2465 for (ntries = 0; ntries < 1000; ntries++) { 2466 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2467 R92C_APS_FSMCO_APFM_ONMAC)) 2468 break; 2469 urtwn_ms_delay(sc); 2470 } 2471 if (ntries == 1000) { 2472 device_printf(sc->sc_dev, 2473 "timeout waiting for MAC auto ON\n"); 2474 return (ETIMEDOUT); 2475 } 2476 2477 /* Enable radio, GPIO and LED functions. */ 2478 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2479 R92C_APS_FSMCO_AFSM_HSUS | 2480 R92C_APS_FSMCO_PDN_EN | 2481 R92C_APS_FSMCO_PFM_ALDN); 2482 if (error != USB_ERR_NORMAL_COMPLETION) 2483 return (EIO); 2484 /* Release RF digital isolation. */ 2485 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2486 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2487 if (error != USB_ERR_NORMAL_COMPLETION) 2488 return (EIO); 2489 2490 /* Initialize MAC. */ 2491 error = urtwn_write_1(sc, R92C_APSD_CTRL, 2492 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2493 if (error != USB_ERR_NORMAL_COMPLETION) 2494 return (EIO); 2495 for (ntries = 0; ntries < 200; ntries++) { 2496 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2497 R92C_APSD_CTRL_OFF_STATUS)) 2498 break; 2499 urtwn_ms_delay(sc); 2500 } 2501 if (ntries == 200) { 2502 device_printf(sc->sc_dev, 2503 "timeout waiting for MAC initialization\n"); 2504 return (ETIMEDOUT); 2505 } 2506 2507 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2508 reg = urtwn_read_2(sc, R92C_CR); 2509 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2510 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2511 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2512 R92C_CR_ENSEC; 2513 error = urtwn_write_2(sc, R92C_CR, reg); 2514 if (error != USB_ERR_NORMAL_COMPLETION) 2515 return (EIO); 2516 2517 error = urtwn_write_1(sc, 0xfe10, 0x19); 2518 if (error != USB_ERR_NORMAL_COMPLETION) 2519 return (EIO); 2520 return (0); 2521} 2522 2523static int 2524urtwn_r88e_power_on(struct urtwn_softc *sc) 2525{ 2526 uint32_t reg; 2527 usb_error_t error; 2528 int ntries; 2529 2530 /* Wait for power ready bit. */ 2531 for (ntries = 0; ntries < 5000; ntries++) { 2532 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2533 break; 2534 urtwn_ms_delay(sc); 2535 } 2536 if (ntries == 5000) { 2537 device_printf(sc->sc_dev, 2538 "timeout waiting for chip power up\n"); 2539 return (ETIMEDOUT); 2540 } 2541 2542 /* Reset BB. */ 2543 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2544 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2545 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2546 if (error != USB_ERR_NORMAL_COMPLETION) 2547 return (EIO); 2548 2549 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2550 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2551 if (error != USB_ERR_NORMAL_COMPLETION) 2552 return (EIO); 2553 2554 /* Disable HWPDN. */ 2555 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2556 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2557 if (error != USB_ERR_NORMAL_COMPLETION) 2558 return (EIO); 2559 2560 /* Disable WL suspend. */ 2561 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2562 urtwn_read_2(sc, R92C_APS_FSMCO) & 2563 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2564 if (error != USB_ERR_NORMAL_COMPLETION) 2565 return (EIO); 2566 2567 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2568 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2569 if (error != USB_ERR_NORMAL_COMPLETION) 2570 return (EIO); 2571 for (ntries = 0; ntries < 5000; ntries++) { 2572 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2573 R92C_APS_FSMCO_APFM_ONMAC)) 2574 break; 2575 urtwn_ms_delay(sc); 2576 } 2577 if (ntries == 5000) 2578 return (ETIMEDOUT); 2579 2580 /* Enable LDO normal mode. */ 2581 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 2582 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2583 if (error != USB_ERR_NORMAL_COMPLETION) 2584 return (EIO); 2585 2586 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2587 error = urtwn_write_2(sc, R92C_CR, 0); 2588 if (error != USB_ERR_NORMAL_COMPLETION) 2589 return (EIO); 2590 reg = urtwn_read_2(sc, R92C_CR); 2591 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2592 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2593 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2594 error = urtwn_write_2(sc, R92C_CR, reg); 2595 if (error != USB_ERR_NORMAL_COMPLETION) 2596 return (EIO); 2597 2598 return (0); 2599} 2600 2601static int 2602urtwn_llt_init(struct urtwn_softc *sc) 2603{ 2604 int i, error, page_count, pktbuf_count; 2605 2606 page_count = (sc->chip & URTWN_CHIP_88E) ? 2607 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2608 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2609 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2610 2611 /* Reserve pages [0; page_count]. */ 2612 for (i = 0; i < page_count; i++) { 2613 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2614 return (error); 2615 } 2616 /* NB: 0xff indicates end-of-list. */ 2617 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2618 return (error); 2619 /* 2620 * Use pages [page_count + 1; pktbuf_count - 1] 2621 * as ring buffer. 2622 */ 2623 for (++i; i < pktbuf_count - 1; i++) { 2624 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2625 return (error); 2626 } 2627 /* Make the last page point to the beginning of the ring buffer. */ 2628 error = urtwn_llt_write(sc, i, page_count + 1); 2629 return (error); 2630} 2631 2632static void 2633urtwn_fw_reset(struct urtwn_softc *sc) 2634{ 2635 uint16_t reg; 2636 int ntries; 2637 2638 /* Tell 8051 to reset itself. */ 2639 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2640 2641 /* Wait until 8051 resets by itself. */ 2642 for (ntries = 0; ntries < 100; ntries++) { 2643 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2644 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2645 return; 2646 urtwn_ms_delay(sc); 2647 } 2648 /* Force 8051 reset. */ 2649 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2650} 2651 2652static void 2653urtwn_r88e_fw_reset(struct urtwn_softc *sc) 2654{ 2655 uint16_t reg; 2656 2657 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2658 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2659 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2660} 2661 2662static int 2663urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2664{ 2665 uint32_t reg; 2666 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 2667 int off, mlen; 2668 2669 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2670 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2671 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2672 2673 off = R92C_FW_START_ADDR; 2674 while (len > 0) { 2675 if (len > 196) 2676 mlen = 196; 2677 else if (len > 4) 2678 mlen = 4; 2679 else 2680 mlen = 1; 2681 /* XXX fix this deconst */ 2682 error = urtwn_write_region_1(sc, off, 2683 __DECONST(uint8_t *, buf), mlen); 2684 if (error != USB_ERR_NORMAL_COMPLETION) 2685 break; 2686 off += mlen; 2687 buf += mlen; 2688 len -= mlen; 2689 } 2690 return (error); 2691} 2692 2693static int 2694urtwn_load_firmware(struct urtwn_softc *sc) 2695{ 2696 const struct firmware *fw; 2697 const struct r92c_fw_hdr *hdr; 2698 const char *imagename; 2699 const u_char *ptr; 2700 size_t len; 2701 uint32_t reg; 2702 int mlen, ntries, page, error; 2703 2704 URTWN_UNLOCK(sc); 2705 /* Read firmware image from the filesystem. */ 2706 if (sc->chip & URTWN_CHIP_88E) 2707 imagename = "urtwn-rtl8188eufw"; 2708 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2709 URTWN_CHIP_UMC_A_CUT) 2710 imagename = "urtwn-rtl8192cfwU"; 2711 else 2712 imagename = "urtwn-rtl8192cfwT"; 2713 2714 fw = firmware_get(imagename); 2715 URTWN_LOCK(sc); 2716 if (fw == NULL) { 2717 device_printf(sc->sc_dev, 2718 "failed loadfirmware of file %s\n", imagename); 2719 return (ENOENT); 2720 } 2721 2722 len = fw->datasize; 2723 2724 if (len < sizeof(*hdr)) { 2725 device_printf(sc->sc_dev, "firmware too short\n"); 2726 error = EINVAL; 2727 goto fail; 2728 } 2729 ptr = fw->data; 2730 hdr = (const struct r92c_fw_hdr *)ptr; 2731 /* Check if there is a valid FW header and skip it. */ 2732 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2733 (le16toh(hdr->signature) >> 4) == 0x88e || 2734 (le16toh(hdr->signature) >> 4) == 0x92c) { 2735 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2736 le16toh(hdr->version), le16toh(hdr->subversion), 2737 hdr->month, hdr->date, hdr->hour, hdr->minute); 2738 ptr += sizeof(*hdr); 2739 len -= sizeof(*hdr); 2740 } 2741 2742 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2743 if (sc->chip & URTWN_CHIP_88E) 2744 urtwn_r88e_fw_reset(sc); 2745 else 2746 urtwn_fw_reset(sc); 2747 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2748 } 2749 2750 if (!(sc->chip & URTWN_CHIP_88E)) { 2751 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2752 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2753 R92C_SYS_FUNC_EN_CPUEN); 2754 } 2755 urtwn_write_1(sc, R92C_MCUFWDL, 2756 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2757 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2758 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2759 2760 /* Reset the FWDL checksum. */ 2761 urtwn_write_1(sc, R92C_MCUFWDL, 2762 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2763 2764 for (page = 0; len > 0; page++) { 2765 mlen = min(len, R92C_FW_PAGE_SIZE); 2766 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2767 if (error != 0) { 2768 device_printf(sc->sc_dev, 2769 "could not load firmware page\n"); 2770 goto fail; 2771 } 2772 ptr += mlen; 2773 len -= mlen; 2774 } 2775 urtwn_write_1(sc, R92C_MCUFWDL, 2776 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2777 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2778 2779 /* Wait for checksum report. */ 2780 for (ntries = 0; ntries < 1000; ntries++) { 2781 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2782 break; 2783 urtwn_ms_delay(sc); 2784 } 2785 if (ntries == 1000) { 2786 device_printf(sc->sc_dev, 2787 "timeout waiting for checksum report\n"); 2788 error = ETIMEDOUT; 2789 goto fail; 2790 } 2791 2792 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2793 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2794 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2795 if (sc->chip & URTWN_CHIP_88E) 2796 urtwn_r88e_fw_reset(sc); 2797 /* Wait for firmware readiness. */ 2798 for (ntries = 0; ntries < 1000; ntries++) { 2799 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2800 break; 2801 urtwn_ms_delay(sc); 2802 } 2803 if (ntries == 1000) { 2804 device_printf(sc->sc_dev, 2805 "timeout waiting for firmware readiness\n"); 2806 error = ETIMEDOUT; 2807 goto fail; 2808 } 2809fail: 2810 firmware_put(fw, FIRMWARE_UNLOAD); 2811 return (error); 2812} 2813 2814static __inline int 2815urtwn_dma_init(struct urtwn_softc *sc) 2816{ 2817 usb_error_t usb_err; 2818 int error; 2819 2820 /* Initialize LLT table. */ 2821 error = urtwn_llt_init(sc); 2822 if (error != 0) 2823 return (error); 2824 2825 error = sc->sc_dma_init(sc); 2826 if (error != 0) 2827 return (error); 2828 2829 /* Set Tx/Rx transfer page size. */ 2830 usb_err = urtwn_write_1(sc, R92C_PBP, 2831 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2832 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2833 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2834 return (EIO); 2835 2836 return (0); 2837} 2838 2839static int 2840urtwn_r92c_dma_init(struct urtwn_softc *sc) 2841{ 2842 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2843 usb_error_t error; 2844 uint32_t reg; 2845 2846 /* Get Tx queues to USB endpoints mapping. */ 2847 hashq = hasnq = haslq = 0; 2848 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2849 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2850 if (MS(reg, R92C_USB_EP_HQ) != 0) 2851 hashq = 1; 2852 if (MS(reg, R92C_USB_EP_NQ) != 0) 2853 hasnq = 1; 2854 if (MS(reg, R92C_USB_EP_LQ) != 0) 2855 haslq = 1; 2856 nqueues = hashq + hasnq + haslq; 2857 if (nqueues == 0) 2858 return (EIO); 2859 /* Get the number of pages for each queue. */ 2860 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2861 /* The remaining pages are assigned to the high priority queue. */ 2862 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2863 2864 /* Set number of pages for normal priority queue. */ 2865 error = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2866 if (error != USB_ERR_NORMAL_COMPLETION) 2867 return (EIO); 2868 error = urtwn_write_4(sc, R92C_RQPN, 2869 /* Set number of pages for public queue. */ 2870 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2871 /* Set number of pages for high priority queue. */ 2872 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2873 /* Set number of pages for low priority queue. */ 2874 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2875 /* Load values. */ 2876 R92C_RQPN_LD); 2877 if (error != USB_ERR_NORMAL_COMPLETION) 2878 return (EIO); 2879 2880 error = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2881 if (error != USB_ERR_NORMAL_COMPLETION) 2882 return (EIO); 2883 error = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2884 if (error != USB_ERR_NORMAL_COMPLETION) 2885 return (EIO); 2886 error = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2887 if (error != USB_ERR_NORMAL_COMPLETION) 2888 return (EIO); 2889 error = urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2890 if (error != USB_ERR_NORMAL_COMPLETION) 2891 return (EIO); 2892 error = urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2893 if (error != USB_ERR_NORMAL_COMPLETION) 2894 return (EIO); 2895 2896 /* Set queue to USB pipe mapping. */ 2897 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2898 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2899 if (nqueues == 1) { 2900 if (hashq) 2901 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2902 else if (hasnq) 2903 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2904 else 2905 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2906 } else if (nqueues == 2) { 2907 /* All 2-endpoints configs have a high priority queue. */ 2908 if (!hashq) 2909 return (EIO); 2910 if (hasnq) 2911 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2912 else 2913 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2914 } else 2915 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2916 error = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2917 if (error != USB_ERR_NORMAL_COMPLETION) 2918 return (EIO); 2919 2920 /* Set Tx/Rx transfer page boundary. */ 2921 error = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2922 if (error != USB_ERR_NORMAL_COMPLETION) 2923 return (EIO); 2924 2925 return (0); 2926} 2927 2928static int 2929urtwn_r88e_dma_init(struct urtwn_softc *sc) 2930{ 2931 struct usb_interface *iface; 2932 uint32_t reg; 2933 usb_error_t error; 2934 int nqueues; 2935 2936 /* Get Tx queues to USB endpoints mapping. */ 2937 iface = usbd_get_iface(sc->sc_udev, 0); 2938 nqueues = iface->idesc->bNumEndpoints - 1; 2939 if (nqueues == 0) 2940 return (EIO); 2941 2942 /* Set number of pages for normal priority queue. */ 2943 error = urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2944 if (error != USB_ERR_NORMAL_COMPLETION) 2945 return (EIO); 2946 error = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2947 if (error != USB_ERR_NORMAL_COMPLETION) 2948 return (EIO); 2949 2950 error = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2951 if (error != USB_ERR_NORMAL_COMPLETION) 2952 return (EIO); 2953 error = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2954 if (error != USB_ERR_NORMAL_COMPLETION) 2955 return (EIO); 2956 error = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2957 if (error != USB_ERR_NORMAL_COMPLETION) 2958 return (EIO); 2959 error = urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2960 if (error != USB_ERR_NORMAL_COMPLETION) 2961 return (EIO); 2962 error = urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2963 if (error != USB_ERR_NORMAL_COMPLETION) 2964 return (EIO); 2965 2966 /* Set queue to USB pipe mapping. */ 2967 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2968 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2969 if (nqueues == 1) 2970 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2971 else if (nqueues == 2) 2972 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2973 else 2974 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2975 error = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2976 if (error != USB_ERR_NORMAL_COMPLETION) 2977 return (EIO); 2978 2979 /* Set Tx/Rx transfer page boundary. */ 2980 error = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2981 if (error != USB_ERR_NORMAL_COMPLETION) 2982 return (EIO); 2983 2984 return (0); 2985} 2986 2987static int 2988urtwn_mac_init(struct urtwn_softc *sc) 2989{ 2990 usb_error_t error; 2991 int i; 2992 2993 /* Write MAC initialization values. */ 2994 if (sc->chip & URTWN_CHIP_88E) { 2995 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2996 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2997 rtl8188eu_mac[i].val); 2998 if (error != USB_ERR_NORMAL_COMPLETION) 2999 return (EIO); 3000 } 3001 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 3002 } else { 3003 for (i = 0; i < nitems(rtl8192cu_mac); i++) 3004 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3005 rtl8192cu_mac[i].val); 3006 if (error != USB_ERR_NORMAL_COMPLETION) 3007 return (EIO); 3008 } 3009 3010 return (0); 3011} 3012 3013static void 3014urtwn_bb_init(struct urtwn_softc *sc) 3015{ 3016 const struct urtwn_bb_prog *prog; 3017 uint32_t reg; 3018 uint8_t crystalcap; 3019 int i; 3020 3021 /* Enable BB and RF. */ 3022 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3023 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3024 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3025 R92C_SYS_FUNC_EN_DIO_RF); 3026 3027 if (!(sc->chip & URTWN_CHIP_88E)) 3028 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 3029 3030 urtwn_write_1(sc, R92C_RF_CTRL, 3031 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3032 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3033 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3034 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3035 3036 if (!(sc->chip & URTWN_CHIP_88E)) { 3037 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3038 urtwn_write_1(sc, 0x15, 0xe9); 3039 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3040 } 3041 3042 /* Select BB programming based on board type. */ 3043 if (sc->chip & URTWN_CHIP_88E) 3044 prog = &rtl8188eu_bb_prog; 3045 else if (!(sc->chip & URTWN_CHIP_92C)) { 3046 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3047 prog = &rtl8188ce_bb_prog; 3048 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3049 prog = &rtl8188ru_bb_prog; 3050 else 3051 prog = &rtl8188cu_bb_prog; 3052 } else { 3053 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3054 prog = &rtl8192ce_bb_prog; 3055 else 3056 prog = &rtl8192cu_bb_prog; 3057 } 3058 /* Write BB initialization values. */ 3059 for (i = 0; i < prog->count; i++) { 3060 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3061 urtwn_ms_delay(sc); 3062 } 3063 3064 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3065 /* 8192C 1T only configuration. */ 3066 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3067 reg = (reg & ~0x00000003) | 0x2; 3068 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3069 3070 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3071 reg = (reg & ~0x00300033) | 0x00200022; 3072 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3073 3074 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3075 reg = (reg & ~0xff000000) | 0x45 << 24; 3076 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3077 3078 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3079 reg = (reg & ~0x000000ff) | 0x23; 3080 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3081 3082 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3083 reg = (reg & ~0x00000030) | 1 << 4; 3084 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3085 3086 reg = urtwn_bb_read(sc, 0xe74); 3087 reg = (reg & ~0x0c000000) | 2 << 26; 3088 urtwn_bb_write(sc, 0xe74, reg); 3089 reg = urtwn_bb_read(sc, 0xe78); 3090 reg = (reg & ~0x0c000000) | 2 << 26; 3091 urtwn_bb_write(sc, 0xe78, reg); 3092 reg = urtwn_bb_read(sc, 0xe7c); 3093 reg = (reg & ~0x0c000000) | 2 << 26; 3094 urtwn_bb_write(sc, 0xe7c, reg); 3095 reg = urtwn_bb_read(sc, 0xe80); 3096 reg = (reg & ~0x0c000000) | 2 << 26; 3097 urtwn_bb_write(sc, 0xe80, reg); 3098 reg = urtwn_bb_read(sc, 0xe88); 3099 reg = (reg & ~0x0c000000) | 2 << 26; 3100 urtwn_bb_write(sc, 0xe88, reg); 3101 } 3102 3103 /* Write AGC values. */ 3104 for (i = 0; i < prog->agccount; i++) { 3105 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 3106 prog->agcvals[i]); 3107 urtwn_ms_delay(sc); 3108 } 3109 3110 if (sc->chip & URTWN_CHIP_88E) { 3111 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3112 urtwn_ms_delay(sc); 3113 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3114 urtwn_ms_delay(sc); 3115 3116 crystalcap = sc->rom.r88e_rom[0xb9]; 3117 if (crystalcap == 0xff) 3118 crystalcap = 0x20; 3119 crystalcap &= 0x3f; 3120 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3121 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3122 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3123 crystalcap | crystalcap << 6)); 3124 } else { 3125 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3126 R92C_HSSI_PARAM2_CCK_HIPWR) 3127 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 3128 } 3129} 3130 3131static void 3132urtwn_rf_init(struct urtwn_softc *sc) 3133{ 3134 const struct urtwn_rf_prog *prog; 3135 uint32_t reg, type; 3136 int i, j, idx, off; 3137 3138 /* Select RF programming based on board type. */ 3139 if (sc->chip & URTWN_CHIP_88E) 3140 prog = rtl8188eu_rf_prog; 3141 else if (!(sc->chip & URTWN_CHIP_92C)) { 3142 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3143 prog = rtl8188ce_rf_prog; 3144 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3145 prog = rtl8188ru_rf_prog; 3146 else 3147 prog = rtl8188cu_rf_prog; 3148 } else 3149 prog = rtl8192ce_rf_prog; 3150 3151 for (i = 0; i < sc->nrxchains; i++) { 3152 /* Save RF_ENV control type. */ 3153 idx = i / 2; 3154 off = (i % 2) * 16; 3155 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3156 type = (reg >> off) & 0x10; 3157 3158 /* Set RF_ENV enable. */ 3159 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3160 reg |= 0x100000; 3161 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3162 urtwn_ms_delay(sc); 3163 /* Set RF_ENV output high. */ 3164 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3165 reg |= 0x10; 3166 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3167 urtwn_ms_delay(sc); 3168 /* Set address and data lengths of RF registers. */ 3169 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3170 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3171 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3172 urtwn_ms_delay(sc); 3173 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3174 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3175 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3176 urtwn_ms_delay(sc); 3177 3178 /* Write RF initialization values for this chain. */ 3179 for (j = 0; j < prog[i].count; j++) { 3180 if (prog[i].regs[j] >= 0xf9 && 3181 prog[i].regs[j] <= 0xfe) { 3182 /* 3183 * These are fake RF registers offsets that 3184 * indicate a delay is required. 3185 */ 3186 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 3187 continue; 3188 } 3189 urtwn_rf_write(sc, i, prog[i].regs[j], 3190 prog[i].vals[j]); 3191 urtwn_ms_delay(sc); 3192 } 3193 3194 /* Restore RF_ENV control type. */ 3195 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3196 reg &= ~(0x10 << off) | (type << off); 3197 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 3198 3199 /* Cache RF register CHNLBW. */ 3200 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3201 } 3202 3203 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3204 URTWN_CHIP_UMC_A_CUT) { 3205 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3206 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3207 } 3208} 3209 3210static void 3211urtwn_cam_init(struct urtwn_softc *sc) 3212{ 3213 /* Invalidate all CAM entries. */ 3214 urtwn_write_4(sc, R92C_CAMCMD, 3215 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3216} 3217 3218static void 3219urtwn_pa_bias_init(struct urtwn_softc *sc) 3220{ 3221 uint8_t reg; 3222 int i; 3223 3224 for (i = 0; i < sc->nrxchains; i++) { 3225 if (sc->pa_setting & (1 << i)) 3226 continue; 3227 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3228 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3229 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3230 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3231 } 3232 if (!(sc->pa_setting & 0x10)) { 3233 reg = urtwn_read_1(sc, 0x16); 3234 reg = (reg & ~0xf0) | 0x90; 3235 urtwn_write_1(sc, 0x16, reg); 3236 } 3237} 3238 3239static void 3240urtwn_rxfilter_init(struct urtwn_softc *sc) 3241{ 3242 struct ieee80211com *ic = &sc->sc_ic; 3243 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3244 uint32_t rcr; 3245 uint16_t filter; 3246 3247 URTWN_ASSERT_LOCKED(sc); 3248 3249 /* Accept all multicast frames. */ 3250 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3251 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3252 3253 /* Filter for management frames. */ 3254 filter = 0x7f3f; 3255 switch (vap->iv_opmode) { 3256 case IEEE80211_M_STA: 3257 filter &= ~( 3258 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 3259 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 3260 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 3261 break; 3262 case IEEE80211_M_HOSTAP: 3263 filter &= ~( 3264 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 3265 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP) | 3266 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_BEACON)); 3267 break; 3268 case IEEE80211_M_MONITOR: 3269 case IEEE80211_M_IBSS: 3270 break; 3271 default: 3272 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3273 __func__, vap->iv_opmode); 3274 break; 3275 } 3276 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 3277 3278 /* Reject all control frames. */ 3279 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3280 3281 /* Reject all data frames. */ 3282 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 3283 3284 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 3285 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 3286 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 3287 3288 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 3289 /* Accept all frames. */ 3290 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 3291 R92C_RCR_AAP; 3292 } 3293 3294 /* Set Rx filter. */ 3295 urtwn_write_4(sc, R92C_RCR, rcr); 3296 3297 if (ic->ic_promisc != 0) { 3298 /* Update Rx filter. */ 3299 urtwn_set_promisc(sc); 3300 } 3301} 3302 3303static void 3304urtwn_edca_init(struct urtwn_softc *sc) 3305{ 3306 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3307 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3308 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3309 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3310 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3311 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3312 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3313 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3314} 3315 3316static void 3317urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3318 uint16_t power[URTWN_RIDX_COUNT]) 3319{ 3320 uint32_t reg; 3321 3322 /* Write per-CCK rate Tx power. */ 3323 if (chain == 0) { 3324 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3325 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3326 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3327 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3328 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3329 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3330 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3331 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3332 } else { 3333 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3334 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3335 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3336 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3337 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3338 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3339 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3340 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3341 } 3342 /* Write per-OFDM rate Tx power. */ 3343 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3344 SM(R92C_TXAGC_RATE06, power[ 4]) | 3345 SM(R92C_TXAGC_RATE09, power[ 5]) | 3346 SM(R92C_TXAGC_RATE12, power[ 6]) | 3347 SM(R92C_TXAGC_RATE18, power[ 7])); 3348 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3349 SM(R92C_TXAGC_RATE24, power[ 8]) | 3350 SM(R92C_TXAGC_RATE36, power[ 9]) | 3351 SM(R92C_TXAGC_RATE48, power[10]) | 3352 SM(R92C_TXAGC_RATE54, power[11])); 3353 /* Write per-MCS Tx power. */ 3354 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3355 SM(R92C_TXAGC_MCS00, power[12]) | 3356 SM(R92C_TXAGC_MCS01, power[13]) | 3357 SM(R92C_TXAGC_MCS02, power[14]) | 3358 SM(R92C_TXAGC_MCS03, power[15])); 3359 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3360 SM(R92C_TXAGC_MCS04, power[16]) | 3361 SM(R92C_TXAGC_MCS05, power[17]) | 3362 SM(R92C_TXAGC_MCS06, power[18]) | 3363 SM(R92C_TXAGC_MCS07, power[19])); 3364 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3365 SM(R92C_TXAGC_MCS08, power[20]) | 3366 SM(R92C_TXAGC_MCS09, power[21]) | 3367 SM(R92C_TXAGC_MCS10, power[22]) | 3368 SM(R92C_TXAGC_MCS11, power[23])); 3369 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3370 SM(R92C_TXAGC_MCS12, power[24]) | 3371 SM(R92C_TXAGC_MCS13, power[25]) | 3372 SM(R92C_TXAGC_MCS14, power[26]) | 3373 SM(R92C_TXAGC_MCS15, power[27])); 3374} 3375 3376static void 3377urtwn_get_txpower(struct urtwn_softc *sc, int chain, 3378 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3379 uint16_t power[URTWN_RIDX_COUNT]) 3380{ 3381 struct ieee80211com *ic = &sc->sc_ic; 3382 struct r92c_rom *rom = &sc->rom.r92c_rom; 3383 uint16_t cckpow, ofdmpow, htpow, diff, max; 3384 const struct urtwn_txpwr *base; 3385 int ridx, chan, group; 3386 3387 /* Determine channel group. */ 3388 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3389 if (chan <= 3) 3390 group = 0; 3391 else if (chan <= 9) 3392 group = 1; 3393 else 3394 group = 2; 3395 3396 /* Get original Tx power based on board type and RF chain. */ 3397 if (!(sc->chip & URTWN_CHIP_92C)) { 3398 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3399 base = &rtl8188ru_txagc[chain]; 3400 else 3401 base = &rtl8192cu_txagc[chain]; 3402 } else 3403 base = &rtl8192cu_txagc[chain]; 3404 3405 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3406 if (sc->regulatory == 0) { 3407 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3408 power[ridx] = base->pwr[0][ridx]; 3409 } 3410 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3411 if (sc->regulatory == 3) { 3412 power[ridx] = base->pwr[0][ridx]; 3413 /* Apply vendor limits. */ 3414 if (extc != NULL) 3415 max = rom->ht40_max_pwr[group]; 3416 else 3417 max = rom->ht20_max_pwr[group]; 3418 max = (max >> (chain * 4)) & 0xf; 3419 if (power[ridx] > max) 3420 power[ridx] = max; 3421 } else if (sc->regulatory == 1) { 3422 if (extc == NULL) 3423 power[ridx] = base->pwr[group][ridx]; 3424 } else if (sc->regulatory != 2) 3425 power[ridx] = base->pwr[0][ridx]; 3426 } 3427 3428 /* Compute per-CCK rate Tx power. */ 3429 cckpow = rom->cck_tx_pwr[chain][group]; 3430 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3431 power[ridx] += cckpow; 3432 if (power[ridx] > R92C_MAX_TX_PWR) 3433 power[ridx] = R92C_MAX_TX_PWR; 3434 } 3435 3436 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3437 if (sc->ntxchains > 1) { 3438 /* Apply reduction for 2 spatial streams. */ 3439 diff = rom->ht40_2s_tx_pwr_diff[group]; 3440 diff = (diff >> (chain * 4)) & 0xf; 3441 htpow = (htpow > diff) ? htpow - diff : 0; 3442 } 3443 3444 /* Compute per-OFDM rate Tx power. */ 3445 diff = rom->ofdm_tx_pwr_diff[group]; 3446 diff = (diff >> (chain * 4)) & 0xf; 3447 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3448 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3449 power[ridx] += ofdmpow; 3450 if (power[ridx] > R92C_MAX_TX_PWR) 3451 power[ridx] = R92C_MAX_TX_PWR; 3452 } 3453 3454 /* Compute per-MCS Tx power. */ 3455 if (extc == NULL) { 3456 diff = rom->ht20_tx_pwr_diff[group]; 3457 diff = (diff >> (chain * 4)) & 0xf; 3458 htpow += diff; /* HT40->HT20 correction. */ 3459 } 3460 for (ridx = 12; ridx <= 27; ridx++) { 3461 power[ridx] += htpow; 3462 if (power[ridx] > R92C_MAX_TX_PWR) 3463 power[ridx] = R92C_MAX_TX_PWR; 3464 } 3465#ifdef URTWN_DEBUG 3466 if (urtwn_debug >= 4) { 3467 /* Dump per-rate Tx power values. */ 3468 printf("Tx power for chain %d:\n", chain); 3469 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 3470 printf("Rate %d = %u\n", ridx, power[ridx]); 3471 } 3472#endif 3473} 3474 3475static void 3476urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3477 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3478 uint16_t power[URTWN_RIDX_COUNT]) 3479{ 3480 struct ieee80211com *ic = &sc->sc_ic; 3481 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3482 const struct urtwn_r88e_txpwr *base; 3483 int ridx, chan, group; 3484 3485 /* Determine channel group. */ 3486 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3487 if (chan <= 2) 3488 group = 0; 3489 else if (chan <= 5) 3490 group = 1; 3491 else if (chan <= 8) 3492 group = 2; 3493 else if (chan <= 11) 3494 group = 3; 3495 else if (chan <= 13) 3496 group = 4; 3497 else 3498 group = 5; 3499 3500 /* Get original Tx power based on board type and RF chain. */ 3501 base = &rtl8188eu_txagc[chain]; 3502 3503 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3504 if (sc->regulatory == 0) { 3505 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3506 power[ridx] = base->pwr[0][ridx]; 3507 } 3508 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3509 if (sc->regulatory == 3) 3510 power[ridx] = base->pwr[0][ridx]; 3511 else if (sc->regulatory == 1) { 3512 if (extc == NULL) 3513 power[ridx] = base->pwr[group][ridx]; 3514 } else if (sc->regulatory != 2) 3515 power[ridx] = base->pwr[0][ridx]; 3516 } 3517 3518 /* Compute per-CCK rate Tx power. */ 3519 cckpow = sc->cck_tx_pwr[group]; 3520 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3521 power[ridx] += cckpow; 3522 if (power[ridx] > R92C_MAX_TX_PWR) 3523 power[ridx] = R92C_MAX_TX_PWR; 3524 } 3525 3526 htpow = sc->ht40_tx_pwr[group]; 3527 3528 /* Compute per-OFDM rate Tx power. */ 3529 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3530 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3531 power[ridx] += ofdmpow; 3532 if (power[ridx] > R92C_MAX_TX_PWR) 3533 power[ridx] = R92C_MAX_TX_PWR; 3534 } 3535 3536 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3537 for (ridx = 12; ridx <= 27; ridx++) { 3538 power[ridx] += bw20pow; 3539 if (power[ridx] > R92C_MAX_TX_PWR) 3540 power[ridx] = R92C_MAX_TX_PWR; 3541 } 3542} 3543 3544static void 3545urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3546 struct ieee80211_channel *extc) 3547{ 3548 uint16_t power[URTWN_RIDX_COUNT]; 3549 int i; 3550 3551 for (i = 0; i < sc->ntxchains; i++) { 3552 /* Compute per-rate Tx power values. */ 3553 if (sc->chip & URTWN_CHIP_88E) 3554 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3555 else 3556 urtwn_get_txpower(sc, i, c, extc, power); 3557 /* Write per-rate Tx power values to hardware. */ 3558 urtwn_write_txpower(sc, i, power); 3559 } 3560} 3561 3562static void 3563urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 3564{ 3565 uint32_t reg; 3566 3567 reg = urtwn_read_4(sc, R92C_RCR); 3568 if (enable) 3569 reg &= ~R92C_RCR_CBSSID_BCN; 3570 else 3571 reg |= R92C_RCR_CBSSID_BCN; 3572 urtwn_write_4(sc, R92C_RCR, reg); 3573} 3574 3575static void 3576urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 3577{ 3578 uint32_t reg; 3579 3580 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3581 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3582 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3583 3584 if (!(sc->chip & URTWN_CHIP_88E)) { 3585 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3586 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3587 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3588 } 3589} 3590 3591static void 3592urtwn_scan_start(struct ieee80211com *ic) 3593{ 3594 struct urtwn_softc *sc = ic->ic_softc; 3595 3596 URTWN_LOCK(sc); 3597 /* Receive beacons / probe responses from any BSSID. */ 3598 if (ic->ic_opmode != IEEE80211_M_IBSS) 3599 urtwn_set_rx_bssid_all(sc, 1); 3600 3601 /* Set gain for scanning. */ 3602 urtwn_set_gain(sc, 0x20); 3603 URTWN_UNLOCK(sc); 3604} 3605 3606static void 3607urtwn_scan_end(struct ieee80211com *ic) 3608{ 3609 struct urtwn_softc *sc = ic->ic_softc; 3610 3611 URTWN_LOCK(sc); 3612 /* Restore limitations. */ 3613 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 3614 urtwn_set_rx_bssid_all(sc, 0); 3615 3616 /* Set gain under link. */ 3617 urtwn_set_gain(sc, 0x32); 3618 URTWN_UNLOCK(sc); 3619} 3620 3621static void 3622urtwn_set_channel(struct ieee80211com *ic) 3623{ 3624 struct urtwn_softc *sc = ic->ic_softc; 3625 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3626 3627 URTWN_LOCK(sc); 3628 if (vap->iv_state == IEEE80211_S_SCAN) { 3629 /* Make link LED blink during scan. */ 3630 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3631 } 3632 urtwn_set_chan(sc, ic->ic_curchan, NULL); 3633 URTWN_UNLOCK(sc); 3634} 3635 3636static void 3637urtwn_set_promisc(struct urtwn_softc *sc) 3638{ 3639 struct ieee80211com *ic = &sc->sc_ic; 3640 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3641 uint32_t rcr, mask1, mask2; 3642 3643 URTWN_ASSERT_LOCKED(sc); 3644 3645 if (vap->iv_opmode == IEEE80211_M_MONITOR) 3646 return; 3647 3648 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 3649 mask2 = R92C_RCR_APM; 3650 3651 if (vap->iv_state == IEEE80211_S_RUN) { 3652 switch (vap->iv_opmode) { 3653 case IEEE80211_M_STA: 3654 mask2 |= R92C_RCR_CBSSID_DATA; 3655 /* FALLTHROUGH */ 3656 case IEEE80211_M_HOSTAP: 3657 mask2 |= R92C_RCR_CBSSID_BCN; 3658 break; 3659 case IEEE80211_M_IBSS: 3660 mask2 |= R92C_RCR_CBSSID_DATA; 3661 break; 3662 default: 3663 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3664 __func__, vap->iv_opmode); 3665 return; 3666 } 3667 } 3668 3669 rcr = urtwn_read_4(sc, R92C_RCR); 3670 if (ic->ic_promisc == 0) 3671 rcr = (rcr & ~mask1) | mask2; 3672 else 3673 rcr = (rcr & ~mask2) | mask1; 3674 urtwn_write_4(sc, R92C_RCR, rcr); 3675} 3676 3677static void 3678urtwn_update_promisc(struct ieee80211com *ic) 3679{ 3680 struct urtwn_softc *sc = ic->ic_softc; 3681 3682 URTWN_LOCK(sc); 3683 if (sc->sc_flags & URTWN_RUNNING) 3684 urtwn_set_promisc(sc); 3685 URTWN_UNLOCK(sc); 3686} 3687 3688static void 3689urtwn_update_mcast(struct ieee80211com *ic) 3690{ 3691 /* XXX do nothing? */ 3692} 3693 3694static void 3695urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3696 struct ieee80211_channel *extc) 3697{ 3698 struct ieee80211com *ic = &sc->sc_ic; 3699 uint32_t reg; 3700 u_int chan; 3701 int i; 3702 3703 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3704 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3705 device_printf(sc->sc_dev, 3706 "%s: invalid channel %x\n", __func__, chan); 3707 return; 3708 } 3709 3710 /* Set Tx power for this new channel. */ 3711 urtwn_set_txpower(sc, c, extc); 3712 3713 for (i = 0; i < sc->nrxchains; i++) { 3714 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3715 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3716 } 3717#ifndef IEEE80211_NO_HT 3718 if (extc != NULL) { 3719 /* Is secondary channel below or above primary? */ 3720 int prichlo = c->ic_freq < extc->ic_freq; 3721 3722 urtwn_write_1(sc, R92C_BWOPMODE, 3723 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3724 3725 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3726 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3727 urtwn_write_1(sc, R92C_RRSR + 2, reg); 3728 3729 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3730 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3731 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3732 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3733 3734 /* Set CCK side band. */ 3735 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3736 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3737 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3738 3739 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3740 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3741 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3742 3743 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3744 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3745 ~R92C_FPGA0_ANAPARAM2_CBW20); 3746 3747 reg = urtwn_bb_read(sc, 0x818); 3748 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3749 urtwn_bb_write(sc, 0x818, reg); 3750 3751 /* Select 40MHz bandwidth. */ 3752 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3753 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3754 } else 3755#endif 3756 { 3757 urtwn_write_1(sc, R92C_BWOPMODE, 3758 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3759 3760 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3761 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3762 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3763 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3764 3765 if (!(sc->chip & URTWN_CHIP_88E)) { 3766 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3767 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3768 R92C_FPGA0_ANAPARAM2_CBW20); 3769 } 3770 3771 /* Select 20MHz bandwidth. */ 3772 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3773 (sc->rf_chnlbw[0] & ~0xfff) | chan | 3774 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3775 R92C_RF_CHNLBW_BW20)); 3776 } 3777} 3778 3779static void 3780urtwn_iq_calib(struct urtwn_softc *sc) 3781{ 3782 /* TODO */ 3783} 3784 3785static void 3786urtwn_lc_calib(struct urtwn_softc *sc) 3787{ 3788 uint32_t rf_ac[2]; 3789 uint8_t txmode; 3790 int i; 3791 3792 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3793 if ((txmode & 0x70) != 0) { 3794 /* Disable all continuous Tx. */ 3795 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3796 3797 /* Set RF mode to standby mode. */ 3798 for (i = 0; i < sc->nrxchains; i++) { 3799 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3800 urtwn_rf_write(sc, i, R92C_RF_AC, 3801 RW(rf_ac[i], R92C_RF_AC_MODE, 3802 R92C_RF_AC_MODE_STANDBY)); 3803 } 3804 } else { 3805 /* Block all Tx queues. */ 3806 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3807 } 3808 /* Start calibration. */ 3809 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3810 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3811 3812 /* Give calibration the time to complete. */ 3813 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3814 3815 /* Restore configuration. */ 3816 if ((txmode & 0x70) != 0) { 3817 /* Restore Tx mode. */ 3818 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3819 /* Restore RF mode. */ 3820 for (i = 0; i < sc->nrxchains; i++) 3821 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3822 } else { 3823 /* Unblock all Tx queues. */ 3824 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3825 } 3826} 3827 3828static int 3829urtwn_init(struct urtwn_softc *sc) 3830{ 3831 struct ieee80211com *ic = &sc->sc_ic; 3832 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3833 uint8_t macaddr[IEEE80211_ADDR_LEN]; 3834 uint32_t reg; 3835 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 3836 int error; 3837 3838 URTWN_LOCK(sc); 3839 if (sc->sc_flags & URTWN_RUNNING) { 3840 URTWN_UNLOCK(sc); 3841 return (0); 3842 } 3843 3844 /* Init firmware commands ring. */ 3845 sc->fwcur = 0; 3846 3847 /* Allocate Tx/Rx buffers. */ 3848 error = urtwn_alloc_rx_list(sc); 3849 if (error != 0) 3850 goto fail; 3851 3852 error = urtwn_alloc_tx_list(sc); 3853 if (error != 0) 3854 goto fail; 3855 3856 /* Power on adapter. */ 3857 error = urtwn_power_on(sc); 3858 if (error != 0) 3859 goto fail; 3860 3861 /* Initialize DMA. */ 3862 error = urtwn_dma_init(sc); 3863 if (error != 0) 3864 goto fail; 3865 3866 /* Set info size in Rx descriptors (in 64-bit words). */ 3867 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3868 3869 /* Init interrupts. */ 3870 if (sc->chip & URTWN_CHIP_88E) { 3871 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3872 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3873 goto fail; 3874 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3875 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3876 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3877 goto fail; 3878 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3879 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3880 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3881 goto fail; 3882 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3883 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3884 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3885 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3886 goto fail; 3887 } else { 3888 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3889 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3890 goto fail; 3891 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3892 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3893 goto fail; 3894 } 3895 3896 /* Set MAC address. */ 3897 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3898 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3899 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3900 goto fail; 3901 3902 /* Set initial network type. */ 3903 urtwn_set_mode(sc, R92C_MSR_INFRA); 3904 3905 /* Initialize Rx filter. */ 3906 urtwn_rxfilter_init(sc); 3907 3908 /* Set response rate. */ 3909 reg = urtwn_read_4(sc, R92C_RRSR); 3910 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3911 urtwn_write_4(sc, R92C_RRSR, reg); 3912 3913 /* Set short/long retry limits. */ 3914 urtwn_write_2(sc, R92C_RL, 3915 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3916 3917 /* Initialize EDCA parameters. */ 3918 urtwn_edca_init(sc); 3919 3920 /* Setup rate fallback. */ 3921 if (!(sc->chip & URTWN_CHIP_88E)) { 3922 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3923 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3924 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3925 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3926 } 3927 3928 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3929 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3930 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3931 /* Set ACK timeout. */ 3932 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3933 3934 /* Setup USB aggregation. */ 3935 reg = urtwn_read_4(sc, R92C_TDECTRL); 3936 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3937 urtwn_write_4(sc, R92C_TDECTRL, reg); 3938 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3939 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3940 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3941 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3942 if (sc->chip & URTWN_CHIP_88E) 3943 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3944 else { 3945 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3946 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3947 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3948 R92C_USB_SPECIAL_OPTION_AGG_EN); 3949 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3950 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3951 } 3952 3953 /* Initialize beacon parameters. */ 3954 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3955 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3956 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3957 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3958 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3959 3960 if (!(sc->chip & URTWN_CHIP_88E)) { 3961 /* Setup AMPDU aggregation. */ 3962 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3963 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3964 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3965 3966 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3967 } 3968 3969 /* Load 8051 microcode. */ 3970 error = urtwn_load_firmware(sc); 3971 if (error != 0) 3972 goto fail; 3973 3974 /* Initialize MAC/BB/RF blocks. */ 3975 error = urtwn_mac_init(sc); 3976 if (error != 0) { 3977 device_printf(sc->sc_dev, 3978 "%s: error while initializing MAC block\n", __func__); 3979 goto fail; 3980 } 3981 urtwn_bb_init(sc); 3982 urtwn_rf_init(sc); 3983 3984 /* Reinitialize Rx filter (D3845 is not committed yet). */ 3985 urtwn_rxfilter_init(sc); 3986 3987 if (sc->chip & URTWN_CHIP_88E) { 3988 urtwn_write_2(sc, R92C_CR, 3989 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3990 R92C_CR_MACRXEN); 3991 } 3992 3993 /* Turn CCK and OFDM blocks on. */ 3994 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3995 reg |= R92C_RFMOD_CCK_EN; 3996 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3997 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3998 goto fail; 3999 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4000 reg |= R92C_RFMOD_OFDM_EN; 4001 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4002 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4003 goto fail; 4004 4005 /* Clear per-station keys table. */ 4006 urtwn_cam_init(sc); 4007 4008 /* Enable hardware sequence numbering. */ 4009 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4010 4011 /* Perform LO and IQ calibrations. */ 4012 urtwn_iq_calib(sc); 4013 /* Perform LC calibration. */ 4014 urtwn_lc_calib(sc); 4015 4016 /* Fix USB interference issue. */ 4017 if (!(sc->chip & URTWN_CHIP_88E)) { 4018 urtwn_write_1(sc, 0xfe40, 0xe0); 4019 urtwn_write_1(sc, 0xfe41, 0x8d); 4020 urtwn_write_1(sc, 0xfe42, 0x80); 4021 4022 urtwn_pa_bias_init(sc); 4023 } 4024 4025 /* Initialize GPIO setting. */ 4026 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4027 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4028 4029 /* Fix for lower temperature. */ 4030 if (!(sc->chip & URTWN_CHIP_88E)) 4031 urtwn_write_1(sc, 0x15, 0xe9); 4032 4033 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 4034 4035 sc->sc_flags |= URTWN_RUNNING; 4036 4037 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4038fail: 4039 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4040 error = EIO; 4041 4042 URTWN_UNLOCK(sc); 4043 4044 return (error); 4045} 4046 4047static void 4048urtwn_stop(struct urtwn_softc *sc) 4049{ 4050 4051 URTWN_LOCK(sc); 4052 if (!(sc->sc_flags & URTWN_RUNNING)) { 4053 URTWN_UNLOCK(sc); 4054 return; 4055 } 4056 4057 sc->sc_flags &= ~URTWN_RUNNING; 4058 callout_stop(&sc->sc_watchdog_ch); 4059 urtwn_abort_xfers(sc); 4060 4061 urtwn_drain_mbufq(sc); 4062 URTWN_UNLOCK(sc); 4063} 4064 4065static void 4066urtwn_abort_xfers(struct urtwn_softc *sc) 4067{ 4068 int i; 4069 4070 URTWN_ASSERT_LOCKED(sc); 4071 4072 /* abort any pending transfers */ 4073 for (i = 0; i < URTWN_N_TRANSFER; i++) 4074 usbd_transfer_stop(sc->sc_xfer[i]); 4075} 4076 4077static int 4078urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4079 const struct ieee80211_bpf_params *params) 4080{ 4081 struct ieee80211com *ic = ni->ni_ic; 4082 struct urtwn_softc *sc = ic->ic_softc; 4083 struct urtwn_data *bf; 4084 int error; 4085 4086 /* prevent management frames from being sent if we're not ready */ 4087 URTWN_LOCK(sc); 4088 if (!(sc->sc_flags & URTWN_RUNNING)) { 4089 error = ENETDOWN; 4090 goto end; 4091 } 4092 4093 bf = urtwn_getbuf(sc); 4094 if (bf == NULL) { 4095 error = ENOBUFS; 4096 goto end; 4097 } 4098 4099 if ((error = urtwn_tx_data(sc, ni, m, bf)) != 0) { 4100 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 4101 goto end; 4102 } 4103 4104 sc->sc_txtimer = 5; 4105 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4106 4107end: 4108 if (error != 0) 4109 m_freem(m); 4110 4111 URTWN_UNLOCK(sc); 4112 4113 return (error); 4114} 4115 4116static void 4117urtwn_ms_delay(struct urtwn_softc *sc) 4118{ 4119 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 4120} 4121 4122static device_method_t urtwn_methods[] = { 4123 /* Device interface */ 4124 DEVMETHOD(device_probe, urtwn_match), 4125 DEVMETHOD(device_attach, urtwn_attach), 4126 DEVMETHOD(device_detach, urtwn_detach), 4127 4128 DEVMETHOD_END 4129}; 4130 4131static driver_t urtwn_driver = { 4132 "urtwn", 4133 urtwn_methods, 4134 sizeof(struct urtwn_softc) 4135}; 4136 4137static devclass_t urtwn_devclass; 4138 4139DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 4140MODULE_DEPEND(urtwn, usb, 1, 1, 1); 4141MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 4142MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 4143MODULE_VERSION(urtwn, 1); 4144