if_urtwn.c revision 289891
198944Sobrien/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 298944Sobrien 398944Sobrien/*- 4130803Smarcel * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5130803Smarcel * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 698944Sobrien * 798944Sobrien * Permission to use, copy, modify, and distribute this software for any 898944Sobrien * purpose with or without fee is hereby granted, provided that the above 998944Sobrien * copyright notice and this permission notice appear in all copies. 1098944Sobrien * 1198944Sobrien * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1298944Sobrien * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1398944Sobrien * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1498944Sobrien * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1598944Sobrien * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1698944Sobrien * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1798944Sobrien * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1898944Sobrien */ 1998944Sobrien 2098944Sobrien#include <sys/cdefs.h> 2198944Sobrien__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 289891 2015-10-24 19:59:15Z avos $"); 2298944Sobrien 2398944Sobrien/* 2498944Sobrien * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 2598944Sobrien */ 26130803Smarcel 2798944Sobrien#include "opt_wlan.h" 2898944Sobrien 29130803Smarcel#include <sys/param.h> 3098944Sobrien#include <sys/sockio.h> 3198944Sobrien#include <sys/sysctl.h> 3298944Sobrien#include <sys/lock.h> 3398944Sobrien#include <sys/mutex.h> 3498944Sobrien#include <sys/mbuf.h> 3598944Sobrien#include <sys/kernel.h> 3698944Sobrien#include <sys/socket.h> 3798944Sobrien#include <sys/systm.h> 3898944Sobrien#include <sys/malloc.h> 3998944Sobrien#include <sys/module.h> 4098944Sobrien#include <sys/bus.h> 4198944Sobrien#include <sys/endian.h> 4298944Sobrien#include <sys/linker.h> 4398944Sobrien#include <sys/firmware.h> 4498944Sobrien#include <sys/kdb.h> 4598944Sobrien 4698944Sobrien#include <machine/bus.h> 4798944Sobrien#include <machine/resource.h> 4898944Sobrien#include <sys/rman.h> 4998944Sobrien 5098944Sobrien#include <net/bpf.h> 5198944Sobrien#include <net/if.h> 5298944Sobrien#include <net/if_var.h> 5398944Sobrien#include <net/if_arp.h> 5498944Sobrien#include <net/ethernet.h> 5598944Sobrien#include <net/if_dl.h> 5698944Sobrien#include <net/if_media.h> 5798944Sobrien#include <net/if_types.h> 5898944Sobrien 5998944Sobrien#include <netinet/in.h> 6098944Sobrien#include <netinet/in_systm.h> 6198944Sobrien#include <netinet/in_var.h> 6298944Sobrien#include <netinet/if_ether.h> 6398944Sobrien#include <netinet/ip.h> 6498944Sobrien 6598944Sobrien#include <net80211/ieee80211_var.h> 6698944Sobrien#include <net80211/ieee80211_input.h> 6798944Sobrien#include <net80211/ieee80211_regdomain.h> 6898944Sobrien#include <net80211/ieee80211_radiotap.h> 6998944Sobrien#include <net80211/ieee80211_ratectl.h> 7098944Sobrien 7198944Sobrien#include <dev/usb/usb.h> 7298944Sobrien#include <dev/usb/usbdi.h> 7398944Sobrien#include "usbdevs.h" 7498944Sobrien 7598944Sobrien#define USB_DEBUG_VAR urtwn_debug 7698944Sobrien#include <dev/usb/usb_debug.h> 7798944Sobrien 7898944Sobrien#include <dev/usb/wlan/if_urtwnreg.h> 7998944Sobrien#include <dev/usb/wlan/if_urtwnvar.h> 8098944Sobrien 8198944Sobrien#ifdef USB_DEBUG 8298944Sobrienstatic int urtwn_debug = 0; 8398944Sobrien 8498944SobrienSYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 8598944SobrienSYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 8698944Sobrien "Debug level"); 8798944Sobrien#endif 8898944Sobrien 8998944Sobrien#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 9098944Sobrien 9198944Sobrien/* various supported device vendors/products */ 9298944Sobrienstatic const STRUCT_USB_HOST_ID urtwn_devs[] = { 9398944Sobrien#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 9498944Sobrien#define URTWN_RTL8188E_DEV(v,p) \ 9598944Sobrien { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 9698944Sobrien#define URTWN_RTL8188E 1 9798944Sobrien URTWN_DEV(ABOCOM, RTL8188CU_1), 9898944Sobrien URTWN_DEV(ABOCOM, RTL8188CU_2), 9998944Sobrien URTWN_DEV(ABOCOM, RTL8192CU), 10098944Sobrien URTWN_DEV(ASUS, RTL8192CU), 10198944Sobrien URTWN_DEV(ASUS, USBN10NANO), 10298944Sobrien URTWN_DEV(AZUREWAVE, RTL8188CE_1), 10398944Sobrien URTWN_DEV(AZUREWAVE, RTL8188CE_2), 10498944Sobrien URTWN_DEV(AZUREWAVE, RTL8188CU), 10598944Sobrien URTWN_DEV(BELKIN, F7D2102), 10698944Sobrien URTWN_DEV(BELKIN, RTL8188CU), 10798944Sobrien URTWN_DEV(BELKIN, RTL8192CU), 10898944Sobrien URTWN_DEV(CHICONY, RTL8188CUS_1), 10998944Sobrien URTWN_DEV(CHICONY, RTL8188CUS_2), 11098944Sobrien URTWN_DEV(CHICONY, RTL8188CUS_3), 11198944Sobrien URTWN_DEV(CHICONY, RTL8188CUS_4), 11298944Sobrien URTWN_DEV(CHICONY, RTL8188CUS_5), 11398944Sobrien URTWN_DEV(COREGA, RTL8192CU), 11498944Sobrien URTWN_DEV(DLINK, RTL8188CU), 11598944Sobrien URTWN_DEV(DLINK, RTL8192CU_1), 11698944Sobrien URTWN_DEV(DLINK, RTL8192CU_2), 11798944Sobrien URTWN_DEV(DLINK, RTL8192CU_3), 11898944Sobrien URTWN_DEV(DLINK, DWA131B), 11998944Sobrien URTWN_DEV(EDIMAX, EW7811UN), 12098944Sobrien URTWN_DEV(EDIMAX, RTL8192CU), 12198944Sobrien URTWN_DEV(FEIXUN, RTL8188CU), 12298944Sobrien URTWN_DEV(FEIXUN, RTL8192CU), 12398944Sobrien URTWN_DEV(GUILLEMOT, HWNUP150), 12498944Sobrien URTWN_DEV(HAWKING, RTL8192CU), 12598944Sobrien URTWN_DEV(HP3, RTL8188CU), 12698944Sobrien URTWN_DEV(NETGEAR, WNA1000M), 12798944Sobrien URTWN_DEV(NETGEAR, RTL8192CU), 12898944Sobrien URTWN_DEV(NETGEAR4, RTL8188CU), 12998944Sobrien URTWN_DEV(NOVATECH, RTL8188CU), 13098944Sobrien URTWN_DEV(PLANEX2, RTL8188CU_1), 13198944Sobrien URTWN_DEV(PLANEX2, RTL8188CU_2), 13298944Sobrien URTWN_DEV(PLANEX2, RTL8188CU_3), 13398944Sobrien URTWN_DEV(PLANEX2, RTL8188CU_4), 13498944Sobrien URTWN_DEV(PLANEX2, RTL8188CUS), 13598944Sobrien URTWN_DEV(PLANEX2, RTL8192CU), 13698944Sobrien URTWN_DEV(REALTEK, RTL8188CE_0), 13798944Sobrien URTWN_DEV(REALTEK, RTL8188CE_1), 13898944Sobrien URTWN_DEV(REALTEK, RTL8188CTV), 13998944Sobrien URTWN_DEV(REALTEK, RTL8188CU_0), 14098944Sobrien URTWN_DEV(REALTEK, RTL8188CU_1), 14198944Sobrien URTWN_DEV(REALTEK, RTL8188CU_2), 14298944Sobrien URTWN_DEV(REALTEK, RTL8188CU_3), 14398944Sobrien URTWN_DEV(REALTEK, RTL8188CU_COMBO), 14498944Sobrien URTWN_DEV(REALTEK, RTL8188CUS), 14598944Sobrien URTWN_DEV(REALTEK, RTL8188RU_1), 14698944Sobrien URTWN_DEV(REALTEK, RTL8188RU_2), 14798944Sobrien URTWN_DEV(REALTEK, RTL8188RU_3), 14898944Sobrien URTWN_DEV(REALTEK, RTL8191CU), 14998944Sobrien URTWN_DEV(REALTEK, RTL8192CE), 15098944Sobrien URTWN_DEV(REALTEK, RTL8192CU), 15198944Sobrien URTWN_DEV(SITECOMEU, RTL8188CU_1), 15298944Sobrien URTWN_DEV(SITECOMEU, RTL8188CU_2), 15398944Sobrien URTWN_DEV(SITECOMEU, RTL8192CU), 15498944Sobrien URTWN_DEV(TRENDNET, RTL8188CU), 15598944Sobrien URTWN_DEV(TRENDNET, RTL8192CU), 15698944Sobrien URTWN_DEV(ZYXEL, RTL8192CU), 15798944Sobrien /* URTWN_RTL8188E */ 15898944Sobrien URTWN_RTL8188E_DEV(DLINK, DWA123D1), 15998944Sobrien URTWN_RTL8188E_DEV(DLINK, DWA125D1), 16098944Sobrien URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 16198944Sobrien URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 16298944Sobrien URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 16398944Sobrien#undef URTWN_RTL8188E_DEV 16498944Sobrien#undef URTWN_DEV 16598944Sobrien}; 16698944Sobrien 16798944Sobrienstatic device_probe_t urtwn_match; 16898944Sobrienstatic device_attach_t urtwn_attach; 16998944Sobrienstatic device_detach_t urtwn_detach; 17098944Sobrien 17198944Sobrienstatic usb_callback_t urtwn_bulk_tx_callback; 17298944Sobrienstatic usb_callback_t urtwn_bulk_rx_callback; 17398944Sobrien 17498944Sobrienstatic void urtwn_drain_mbufq(struct urtwn_softc *sc); 17598944Sobrienstatic usb_error_t urtwn_do_request(struct urtwn_softc *, 17698944Sobrien struct usb_device_request *, void *); 17798944Sobrienstatic struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 178130803Smarcel const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 17998944Sobrien const uint8_t [IEEE80211_ADDR_LEN], 180130803Smarcel const uint8_t [IEEE80211_ADDR_LEN]); 181130803Smarcelstatic void urtwn_vap_delete(struct ieee80211vap *); 18298944Sobrienstatic struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 18398944Sobrien int *); 18498944Sobrienstatic struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 18598944Sobrien int *, int8_t *); 18698944Sobrienstatic void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 18798944Sobrien int); 18898944Sobrienstatic int urtwn_alloc_list(struct urtwn_softc *, 18998944Sobrien struct urtwn_data[], int, int); 19098944Sobrienstatic int urtwn_alloc_rx_list(struct urtwn_softc *); 19198944Sobrienstatic int urtwn_alloc_tx_list(struct urtwn_softc *); 192130803Smarcelstatic void urtwn_free_list(struct urtwn_softc *, 193130803Smarcel struct urtwn_data data[], int); 19498944Sobrienstatic void urtwn_free_rx_list(struct urtwn_softc *); 19598944Sobrienstatic void urtwn_free_tx_list(struct urtwn_softc *); 19698944Sobrienstatic struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 19798944Sobrienstatic struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 19898944Sobrienstatic int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 19998944Sobrien uint8_t *, int); 20098944Sobrienstatic void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 20198944Sobrienstatic void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 20298944Sobrienstatic void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 20398944Sobrienstatic int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 20498944Sobrien uint8_t *, int); 20598944Sobrienstatic uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 20698944Sobrienstatic uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 20798944Sobrienstatic uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 20898944Sobrienstatic int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 20998944Sobrien const void *, int); 21098944Sobrienstatic void urtwn_r92c_rf_write(struct urtwn_softc *, int, 21198944Sobrien uint8_t, uint32_t); 21298944Sobrienstatic void urtwn_r88e_rf_write(struct urtwn_softc *, int, 21398944Sobrien uint8_t, uint32_t); 21498944Sobrienstatic uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 21598944Sobrienstatic int urtwn_llt_write(struct urtwn_softc *, uint32_t, 21698944Sobrien uint32_t); 21798944Sobrienstatic uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 21898944Sobrienstatic void urtwn_efuse_read(struct urtwn_softc *); 21998944Sobrienstatic void urtwn_efuse_switch_power(struct urtwn_softc *); 22098944Sobrienstatic int urtwn_read_chipid(struct urtwn_softc *); 22198944Sobrienstatic void urtwn_read_rom(struct urtwn_softc *); 22298944Sobrienstatic void urtwn_r88e_read_rom(struct urtwn_softc *); 22398944Sobrienstatic int urtwn_ra_init(struct urtwn_softc *); 22498944Sobrienstatic void urtwn_tsf_sync_enable(struct urtwn_softc *); 22598944Sobrienstatic void urtwn_set_led(struct urtwn_softc *, int, int); 22698944Sobrienstatic void urtwn_set_mode(struct urtwn_softc *, uint8_t); 22798944Sobrienstatic int urtwn_newstate(struct ieee80211vap *, 22898944Sobrien enum ieee80211_state, int); 22998944Sobrienstatic void urtwn_watchdog(void *); 23098944Sobrienstatic void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 23198944Sobrienstatic int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 23298944Sobrienstatic int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 23398944Sobrienstatic int urtwn_tx_start(struct urtwn_softc *, 23498944Sobrien struct ieee80211_node *, struct mbuf *, 23598944Sobrien struct urtwn_data *); 23698944Sobrienstatic int urtwn_transmit(struct ieee80211com *, struct mbuf *); 23798944Sobrienstatic void urtwn_start(struct urtwn_softc *); 23898944Sobrienstatic void urtwn_parent(struct ieee80211com *); 23998944Sobrienstatic int urtwn_r92c_power_on(struct urtwn_softc *); 24098944Sobrienstatic int urtwn_r88e_power_on(struct urtwn_softc *); 24198944Sobrienstatic int urtwn_llt_init(struct urtwn_softc *); 24298944Sobrienstatic void urtwn_fw_reset(struct urtwn_softc *); 24398944Sobrienstatic void urtwn_r88e_fw_reset(struct urtwn_softc *); 24498944Sobrienstatic int urtwn_fw_loadpage(struct urtwn_softc *, int, 24598944Sobrien const uint8_t *, int); 24698944Sobrienstatic int urtwn_load_firmware(struct urtwn_softc *); 24798944Sobrienstatic int urtwn_r92c_dma_init(struct urtwn_softc *); 248130803Smarcelstatic int urtwn_r88e_dma_init(struct urtwn_softc *); 249130803Smarcelstatic void urtwn_mac_init(struct urtwn_softc *); 250130803Smarcelstatic void urtwn_bb_init(struct urtwn_softc *); 251130803Smarcelstatic void urtwn_rf_init(struct urtwn_softc *); 252130803Smarcelstatic void urtwn_cam_init(struct urtwn_softc *); 253130803Smarcelstatic void urtwn_pa_bias_init(struct urtwn_softc *); 254130803Smarcelstatic void urtwn_rxfilter_init(struct urtwn_softc *); 25598944Sobrienstatic void urtwn_edca_init(struct urtwn_softc *); 25698944Sobrienstatic void urtwn_write_txpower(struct urtwn_softc *, int, 25798944Sobrien uint16_t[]); 258130803Smarcelstatic void urtwn_get_txpower(struct urtwn_softc *, int, 259130803Smarcel struct ieee80211_channel *, 260130803Smarcel struct ieee80211_channel *, uint16_t[]); 261130803Smarcelstatic void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 26298944Sobrien struct ieee80211_channel *, 26398944Sobrien struct ieee80211_channel *, uint16_t[]); 26498944Sobrienstatic void urtwn_set_txpower(struct urtwn_softc *, 26598944Sobrien struct ieee80211_channel *, 26698944Sobrien struct ieee80211_channel *); 26798944Sobrienstatic void urtwn_scan_start(struct ieee80211com *); 26898944Sobrienstatic void urtwn_scan_end(struct ieee80211com *); 26998944Sobrienstatic void urtwn_set_channel(struct ieee80211com *); 27098944Sobrienstatic void urtwn_update_mcast(struct ieee80211com *); 27198944Sobrienstatic void urtwn_set_chan(struct urtwn_softc *, 27298944Sobrien struct ieee80211_channel *, 27398944Sobrien struct ieee80211_channel *); 27498944Sobrienstatic void urtwn_iq_calib(struct urtwn_softc *); 27598944Sobrienstatic void urtwn_lc_calib(struct urtwn_softc *); 27698944Sobrienstatic void urtwn_init(struct urtwn_softc *); 27798944Sobrienstatic void urtwn_stop(struct urtwn_softc *); 27898944Sobrienstatic void urtwn_abort_xfers(struct urtwn_softc *); 27998944Sobrienstatic int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 28098944Sobrien const struct ieee80211_bpf_params *); 28198944Sobrienstatic void urtwn_ms_delay(struct urtwn_softc *); 28298944Sobrien 28398944Sobrien/* Aliases. */ 284130803Smarcel#define urtwn_bb_write urtwn_write_4 285130803Smarcel#define urtwn_bb_read urtwn_read_4 28698944Sobrien 28798944Sobrienstatic const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 28898944Sobrien [URTWN_BULK_RX] = { 28998944Sobrien .type = UE_BULK, 29098944Sobrien .endpoint = UE_ADDR_ANY, 29198944Sobrien .direction = UE_DIR_IN, 29298944Sobrien .bufsize = URTWN_RXBUFSZ, 29398944Sobrien .flags = { 29498944Sobrien .pipe_bof = 1, 29598944Sobrien .short_xfer_ok = 1 29698944Sobrien }, 29798944Sobrien .callback = urtwn_bulk_rx_callback, 29898944Sobrien }, 29998944Sobrien [URTWN_BULK_TX_BE] = { 30098944Sobrien .type = UE_BULK, 30198944Sobrien .endpoint = 0x03, 30298944Sobrien .direction = UE_DIR_OUT, 30398944Sobrien .bufsize = URTWN_TXBUFSZ, 30498944Sobrien .flags = { 30598944Sobrien .ext_buffer = 1, 30698944Sobrien .pipe_bof = 1, 30798944Sobrien .force_short_xfer = 1 30898944Sobrien }, 30998944Sobrien .callback = urtwn_bulk_tx_callback, 31098944Sobrien .timeout = URTWN_TX_TIMEOUT, /* ms */ 311130803Smarcel }, 312130803Smarcel [URTWN_BULK_TX_BK] = { 313130803Smarcel .type = UE_BULK, 31498944Sobrien .endpoint = 0x03, 31598944Sobrien .direction = UE_DIR_OUT, 31698944Sobrien .bufsize = URTWN_TXBUFSZ, 31798944Sobrien .flags = { 31898944Sobrien .ext_buffer = 1, 31998944Sobrien .pipe_bof = 1, 32098944Sobrien .force_short_xfer = 1, 32198944Sobrien }, 32298944Sobrien .callback = urtwn_bulk_tx_callback, 32398944Sobrien .timeout = URTWN_TX_TIMEOUT, /* ms */ 32498944Sobrien }, 32598944Sobrien [URTWN_BULK_TX_VI] = { 32698944Sobrien .type = UE_BULK, 32798944Sobrien .endpoint = 0x02, 32898944Sobrien .direction = UE_DIR_OUT, 32998944Sobrien .bufsize = URTWN_TXBUFSZ, 33098944Sobrien .flags = { 33198944Sobrien .ext_buffer = 1, 33298944Sobrien .pipe_bof = 1, 33398944Sobrien .force_short_xfer = 1 33498944Sobrien }, 33598944Sobrien .callback = urtwn_bulk_tx_callback, 33698944Sobrien .timeout = URTWN_TX_TIMEOUT, /* ms */ 33798944Sobrien }, 33898944Sobrien [URTWN_BULK_TX_VO] = { 33998944Sobrien .type = UE_BULK, 34098944Sobrien .endpoint = 0x02, 34198944Sobrien .direction = UE_DIR_OUT, 34298944Sobrien .bufsize = URTWN_TXBUFSZ, 34398944Sobrien .flags = { 34498944Sobrien .ext_buffer = 1, 34598944Sobrien .pipe_bof = 1, 34698944Sobrien .force_short_xfer = 1 34798944Sobrien }, 34898944Sobrien .callback = urtwn_bulk_tx_callback, 34998944Sobrien .timeout = URTWN_TX_TIMEOUT, /* ms */ 35098944Sobrien }, 35198944Sobrien}; 35298944Sobrien 35398944Sobrienstatic int 35498944Sobrienurtwn_match(device_t self) 35598944Sobrien{ 35698944Sobrien struct usb_attach_arg *uaa = device_get_ivars(self); 35798944Sobrien 35898944Sobrien if (uaa->usb_mode != USB_MODE_HOST) 359130803Smarcel return (ENXIO); 36098944Sobrien if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 36198944Sobrien return (ENXIO); 36298944Sobrien if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 363130803Smarcel return (ENXIO); 364130803Smarcel 365130803Smarcel return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 366130803Smarcel} 36798944Sobrien 36898944Sobrienstatic int 36998944Sobrienurtwn_attach(device_t self) 37098944Sobrien{ 37198944Sobrien struct usb_attach_arg *uaa = device_get_ivars(self); 37298944Sobrien struct urtwn_softc *sc = device_get_softc(self); 37398944Sobrien struct ieee80211com *ic = &sc->sc_ic; 37498944Sobrien uint8_t iface_index, bands; 37598944Sobrien int error; 37698944Sobrien 37798944Sobrien device_set_usb_desc(self); 37898944Sobrien sc->sc_udev = uaa->device; 37998944Sobrien sc->sc_dev = self; 38098944Sobrien if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 38198944Sobrien sc->chip |= URTWN_CHIP_88E; 38298944Sobrien 38398944Sobrien mtx_init(&sc->sc_mtx, device_get_nameunit(self), 38498944Sobrien MTX_NETWORK_LOCK, MTX_DEF); 38598944Sobrien callout_init(&sc->sc_watchdog_ch, 0); 38698944Sobrien mbufq_init(&sc->sc_snd, ifqmaxlen); 38798944Sobrien 38898944Sobrien iface_index = URTWN_IFACE_INDEX; 38998944Sobrien error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 39098944Sobrien urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 39198944Sobrien if (error) { 392130803Smarcel device_printf(self, "could not allocate USB transfers, " 393130803Smarcel "err=%s\n", usbd_errstr(error)); 394130803Smarcel goto detach; 395130803Smarcel } 396130803Smarcel 397130803Smarcel URTWN_LOCK(sc); 398130803Smarcel 399130803Smarcel error = urtwn_read_chipid(sc); 400130803Smarcel if (error) { 40198944Sobrien device_printf(sc->sc_dev, "unsupported test chip\n"); 402130803Smarcel URTWN_UNLOCK(sc); 403130803Smarcel goto detach; 404130803Smarcel } 40598944Sobrien 406130803Smarcel /* Determine number of Tx/Rx chains. */ 407130803Smarcel if (sc->chip & URTWN_CHIP_92C) { 408130803Smarcel sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 409130803Smarcel sc->nrxchains = 2; 410130803Smarcel } else { 411130803Smarcel sc->ntxchains = 1; 412130803Smarcel sc->nrxchains = 1; 41398944Sobrien } 41498944Sobrien 41598944Sobrien if (sc->chip & URTWN_CHIP_88E) 41698944Sobrien urtwn_r88e_read_rom(sc); 41798944Sobrien else 41898944Sobrien urtwn_read_rom(sc); 41998944Sobrien 42098944Sobrien device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 42198944Sobrien (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 42298944Sobrien (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 42398944Sobrien (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 42498944Sobrien (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 425130803Smarcel "8188CUS", sc->ntxchains, sc->nrxchains); 42698944Sobrien 42798944Sobrien URTWN_UNLOCK(sc); 42898944Sobrien 42998944Sobrien ic->ic_softc = sc; 43098944Sobrien ic->ic_name = device_get_nameunit(self); 43198944Sobrien ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 43298944Sobrien ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 43398944Sobrien 43498944Sobrien /* set device capabilities */ 43598944Sobrien ic->ic_caps = 43698944Sobrien IEEE80211_C_STA /* station mode */ 43798944Sobrien | IEEE80211_C_MONITOR /* monitor mode */ 43898944Sobrien | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 439130803Smarcel | IEEE80211_C_SHSLOT /* short slot time supported */ 44098944Sobrien | IEEE80211_C_BGSCAN /* capable of bg scanning */ 44198944Sobrien | IEEE80211_C_WPA /* 802.11i */ 44298944Sobrien ; 44398944Sobrien 44498944Sobrien bands = 0; 44598944Sobrien setbit(&bands, IEEE80211_MODE_11B); 446130803Smarcel setbit(&bands, IEEE80211_MODE_11G); 44798944Sobrien ieee80211_init_channels(ic, NULL, &bands); 448 449 ieee80211_ifattach(ic); 450 ic->ic_raw_xmit = urtwn_raw_xmit; 451 ic->ic_scan_start = urtwn_scan_start; 452 ic->ic_scan_end = urtwn_scan_end; 453 ic->ic_set_channel = urtwn_set_channel; 454 ic->ic_transmit = urtwn_transmit; 455 ic->ic_parent = urtwn_parent; 456 ic->ic_vap_create = urtwn_vap_create; 457 ic->ic_vap_delete = urtwn_vap_delete; 458 ic->ic_update_mcast = urtwn_update_mcast; 459 460 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 461 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 462 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 463 URTWN_RX_RADIOTAP_PRESENT); 464 465 if (bootverbose) 466 ieee80211_announce(ic); 467 468 return (0); 469 470detach: 471 urtwn_detach(self); 472 return (ENXIO); /* failure */ 473} 474 475static int 476urtwn_detach(device_t self) 477{ 478 struct urtwn_softc *sc = device_get_softc(self); 479 struct ieee80211com *ic = &sc->sc_ic; 480 unsigned int x; 481 482 /* Prevent further ioctls. */ 483 URTWN_LOCK(sc); 484 sc->sc_flags |= URTWN_DETACHED; 485 urtwn_stop(sc); 486 URTWN_UNLOCK(sc); 487 488 callout_drain(&sc->sc_watchdog_ch); 489 490 /* stop all USB transfers */ 491 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 492 493 /* Prevent further allocations from RX/TX data lists. */ 494 URTWN_LOCK(sc); 495 STAILQ_INIT(&sc->sc_tx_active); 496 STAILQ_INIT(&sc->sc_tx_inactive); 497 STAILQ_INIT(&sc->sc_tx_pending); 498 499 STAILQ_INIT(&sc->sc_rx_active); 500 STAILQ_INIT(&sc->sc_rx_inactive); 501 URTWN_UNLOCK(sc); 502 503 /* drain USB transfers */ 504 for (x = 0; x != URTWN_N_TRANSFER; x++) 505 usbd_transfer_drain(sc->sc_xfer[x]); 506 507 /* Free data buffers. */ 508 URTWN_LOCK(sc); 509 urtwn_free_tx_list(sc); 510 urtwn_free_rx_list(sc); 511 URTWN_UNLOCK(sc); 512 513 ieee80211_ifdetach(ic); 514 mtx_destroy(&sc->sc_mtx); 515 516 return (0); 517} 518 519static void 520urtwn_drain_mbufq(struct urtwn_softc *sc) 521{ 522 struct mbuf *m; 523 struct ieee80211_node *ni; 524 URTWN_ASSERT_LOCKED(sc); 525 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 526 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 527 m->m_pkthdr.rcvif = NULL; 528 ieee80211_free_node(ni); 529 m_freem(m); 530 } 531} 532 533static usb_error_t 534urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 535 void *data) 536{ 537 usb_error_t err; 538 int ntries = 10; 539 540 URTWN_ASSERT_LOCKED(sc); 541 542 while (ntries--) { 543 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 544 req, data, 0, NULL, 250 /* ms */); 545 if (err == 0) 546 break; 547 548 DPRINTFN(1, "Control request failed, %s (retrying)\n", 549 usbd_errstr(err)); 550 usb_pause_mtx(&sc->sc_mtx, hz / 100); 551 } 552 return (err); 553} 554 555static struct ieee80211vap * 556urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 557 enum ieee80211_opmode opmode, int flags, 558 const uint8_t bssid[IEEE80211_ADDR_LEN], 559 const uint8_t mac[IEEE80211_ADDR_LEN]) 560{ 561 struct urtwn_vap *uvp; 562 struct ieee80211vap *vap; 563 564 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 565 return (NULL); 566 567 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 568 vap = &uvp->vap; 569 /* enable s/w bmiss handling for sta mode */ 570 571 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 572 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 573 /* out of memory */ 574 free(uvp, M_80211_VAP); 575 return (NULL); 576 } 577 578 /* override state transition machine */ 579 uvp->newstate = vap->iv_newstate; 580 vap->iv_newstate = urtwn_newstate; 581 582 /* complete setup */ 583 ieee80211_vap_attach(vap, ieee80211_media_change, 584 ieee80211_media_status, mac); 585 ic->ic_opmode = opmode; 586 return (vap); 587} 588 589static void 590urtwn_vap_delete(struct ieee80211vap *vap) 591{ 592 struct urtwn_vap *uvp = URTWN_VAP(vap); 593 594 ieee80211_vap_detach(vap); 595 free(uvp, M_80211_VAP); 596} 597 598static struct mbuf * 599urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 600{ 601 struct ieee80211com *ic = &sc->sc_ic; 602 struct ieee80211_frame *wh; 603 struct mbuf *m; 604 struct r92c_rx_stat *stat; 605 uint32_t rxdw0, rxdw3; 606 uint8_t rate; 607 int8_t rssi = 0; 608 int infosz; 609 610 /* 611 * don't pass packets to the ieee80211 framework if the driver isn't 612 * RUNNING. 613 */ 614 if (!(sc->sc_flags & URTWN_RUNNING)) 615 return (NULL); 616 617 stat = (struct r92c_rx_stat *)buf; 618 rxdw0 = le32toh(stat->rxdw0); 619 rxdw3 = le32toh(stat->rxdw3); 620 621 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 622 /* 623 * This should not happen since we setup our Rx filter 624 * to not receive these frames. 625 */ 626 counter_u64_add(ic->ic_ierrors, 1); 627 return (NULL); 628 } 629 if (pktlen < sizeof(*wh) || pktlen > MCLBYTES) { 630 counter_u64_add(ic->ic_ierrors, 1); 631 return (NULL); 632 } 633 634 rate = MS(rxdw3, R92C_RXDW3_RATE); 635 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 636 637 /* Get RSSI from PHY status descriptor if present. */ 638 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 639 if (sc->chip & URTWN_CHIP_88E) 640 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 641 else 642 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 643 /* Update our average RSSI. */ 644 urtwn_update_avgrssi(sc, rate, rssi); 645 } 646 647 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 648 if (m == NULL) { 649 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 650 return (NULL); 651 } 652 653 /* Finalize mbuf. */ 654 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 655 memcpy(mtod(m, uint8_t *), wh, pktlen); 656 m->m_pkthdr.len = m->m_len = pktlen; 657 658 if (ieee80211_radiotap_active(ic)) { 659 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 660 661 tap->wr_flags = 0; 662 /* Map HW rate index to 802.11 rate. */ 663 if (!(rxdw3 & R92C_RXDW3_HT)) { 664 tap->wr_rate = ridx2rate[rate]; 665 } else if (rate >= 12) { /* MCS0~15. */ 666 /* Bit 7 set means HT MCS instead of rate. */ 667 tap->wr_rate = 0x80 | (rate - 12); 668 } 669 tap->wr_dbm_antsignal = rssi; 670 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 671 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 672 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 673 } 674 675 *rssi_p = rssi; 676 677 return (m); 678} 679 680static struct mbuf * 681urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 682 int8_t *nf) 683{ 684 struct urtwn_softc *sc = data->sc; 685 struct ieee80211com *ic = &sc->sc_ic; 686 struct r92c_rx_stat *stat; 687 struct mbuf *m, *m0 = NULL, *prevm = NULL; 688 uint32_t rxdw0; 689 uint8_t *buf; 690 int len, totlen, pktlen, infosz, npkts; 691 692 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 693 694 if (len < sizeof(*stat)) { 695 counter_u64_add(ic->ic_ierrors, 1); 696 return (NULL); 697 } 698 699 buf = data->buf; 700 /* Get the number of encapsulated frames. */ 701 stat = (struct r92c_rx_stat *)buf; 702 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 703 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 704 705 /* Process all of them. */ 706 while (npkts-- > 0) { 707 if (len < sizeof(*stat)) 708 break; 709 stat = (struct r92c_rx_stat *)buf; 710 rxdw0 = le32toh(stat->rxdw0); 711 712 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 713 if (pktlen == 0) 714 break; 715 716 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 717 718 /* Make sure everything fits in xfer. */ 719 totlen = sizeof(*stat) + infosz + pktlen; 720 if (totlen > len) 721 break; 722 723 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 724 if (m0 == NULL) 725 m0 = m; 726 if (prevm == NULL) 727 prevm = m; 728 else { 729 prevm->m_next = m; 730 prevm = m; 731 } 732 733 /* Next chunk is 128-byte aligned. */ 734 totlen = (totlen + 127) & ~127; 735 buf += totlen; 736 len -= totlen; 737 } 738 739 return (m0); 740} 741 742static void 743urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 744{ 745 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 746 struct ieee80211com *ic = &sc->sc_ic; 747 struct ieee80211_frame *wh; 748 struct ieee80211_node *ni; 749 struct mbuf *m = NULL, *next; 750 struct urtwn_data *data; 751 int8_t nf; 752 int rssi = 1; 753 754 URTWN_ASSERT_LOCKED(sc); 755 756 switch (USB_GET_STATE(xfer)) { 757 case USB_ST_TRANSFERRED: 758 data = STAILQ_FIRST(&sc->sc_rx_active); 759 if (data == NULL) 760 goto tr_setup; 761 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 762 m = urtwn_rxeof(xfer, data, &rssi, &nf); 763 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 764 /* FALLTHROUGH */ 765 case USB_ST_SETUP: 766tr_setup: 767 data = STAILQ_FIRST(&sc->sc_rx_inactive); 768 if (data == NULL) { 769 KASSERT(m == NULL, ("mbuf isn't NULL")); 770 return; 771 } 772 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 773 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 774 usbd_xfer_set_frame_data(xfer, 0, data->buf, 775 usbd_xfer_max_len(xfer)); 776 usbd_transfer_submit(xfer); 777 778 /* 779 * To avoid LOR we should unlock our private mutex here to call 780 * ieee80211_input() because here is at the end of a USB 781 * callback and safe to unlock. 782 */ 783 URTWN_UNLOCK(sc); 784 while (m != NULL) { 785 next = m->m_next; 786 m->m_next = NULL; 787 wh = mtod(m, struct ieee80211_frame *); 788 ni = ieee80211_find_rxnode(ic, 789 (struct ieee80211_frame_min *)wh); 790 nf = URTWN_NOISE_FLOOR; 791 if (ni != NULL) { 792 (void)ieee80211_input(ni, m, rssi - nf, nf); 793 ieee80211_free_node(ni); 794 } else { 795 (void)ieee80211_input_all(ic, m, rssi - nf, 796 nf); 797 } 798 m = next; 799 } 800 URTWN_LOCK(sc); 801 break; 802 default: 803 /* needs it to the inactive queue due to a error. */ 804 data = STAILQ_FIRST(&sc->sc_rx_active); 805 if (data != NULL) { 806 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 807 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 808 } 809 if (error != USB_ERR_CANCELLED) { 810 usbd_xfer_set_stall(xfer); 811 counter_u64_add(ic->ic_ierrors, 1); 812 goto tr_setup; 813 } 814 break; 815 } 816} 817 818static void 819urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 820{ 821 822 URTWN_ASSERT_LOCKED(sc); 823 824 ieee80211_tx_complete(data->ni, data->m, status); 825 826 data->ni = NULL; 827 data->m = NULL; 828 829 sc->sc_txtimer = 0; 830 831 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 832} 833 834static int 835urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 836 int ndata, int maxsz) 837{ 838 int i, error; 839 840 for (i = 0; i < ndata; i++) { 841 struct urtwn_data *dp = &data[i]; 842 dp->sc = sc; 843 dp->m = NULL; 844 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 845 if (dp->buf == NULL) { 846 device_printf(sc->sc_dev, 847 "could not allocate buffer\n"); 848 error = ENOMEM; 849 goto fail; 850 } 851 dp->ni = NULL; 852 } 853 854 return (0); 855fail: 856 urtwn_free_list(sc, data, ndata); 857 return (error); 858} 859 860static int 861urtwn_alloc_rx_list(struct urtwn_softc *sc) 862{ 863 int error, i; 864 865 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 866 URTWN_RXBUFSZ); 867 if (error != 0) 868 return (error); 869 870 STAILQ_INIT(&sc->sc_rx_active); 871 STAILQ_INIT(&sc->sc_rx_inactive); 872 873 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 874 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 875 876 return (0); 877} 878 879static int 880urtwn_alloc_tx_list(struct urtwn_softc *sc) 881{ 882 int error, i; 883 884 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 885 URTWN_TXBUFSZ); 886 if (error != 0) 887 return (error); 888 889 STAILQ_INIT(&sc->sc_tx_active); 890 STAILQ_INIT(&sc->sc_tx_inactive); 891 STAILQ_INIT(&sc->sc_tx_pending); 892 893 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 894 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 895 896 return (0); 897} 898 899static void 900urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 901{ 902 int i; 903 904 for (i = 0; i < ndata; i++) { 905 struct urtwn_data *dp = &data[i]; 906 907 if (dp->buf != NULL) { 908 free(dp->buf, M_USBDEV); 909 dp->buf = NULL; 910 } 911 if (dp->ni != NULL) { 912 ieee80211_free_node(dp->ni); 913 dp->ni = NULL; 914 } 915 } 916} 917 918static void 919urtwn_free_rx_list(struct urtwn_softc *sc) 920{ 921 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 922} 923 924static void 925urtwn_free_tx_list(struct urtwn_softc *sc) 926{ 927 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 928} 929 930static void 931urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 932{ 933 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 934 struct urtwn_data *data; 935 936 URTWN_ASSERT_LOCKED(sc); 937 938 switch (USB_GET_STATE(xfer)){ 939 case USB_ST_TRANSFERRED: 940 data = STAILQ_FIRST(&sc->sc_tx_active); 941 if (data == NULL) 942 goto tr_setup; 943 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 944 urtwn_txeof(sc, data, 0); 945 /* FALLTHROUGH */ 946 case USB_ST_SETUP: 947tr_setup: 948 data = STAILQ_FIRST(&sc->sc_tx_pending); 949 if (data == NULL) { 950 DPRINTF("%s: empty pending queue\n", __func__); 951 goto finish; 952 } 953 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 954 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 955 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 956 usbd_transfer_submit(xfer); 957 break; 958 default: 959 data = STAILQ_FIRST(&sc->sc_tx_active); 960 if (data == NULL) 961 goto tr_setup; 962 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 963 urtwn_txeof(sc, data, 1); 964 if (error != USB_ERR_CANCELLED) { 965 usbd_xfer_set_stall(xfer); 966 goto tr_setup; 967 } 968 break; 969 } 970finish: 971 /* Kick-start more transmit */ 972 urtwn_start(sc); 973} 974 975static struct urtwn_data * 976_urtwn_getbuf(struct urtwn_softc *sc) 977{ 978 struct urtwn_data *bf; 979 980 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 981 if (bf != NULL) 982 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 983 else 984 bf = NULL; 985 if (bf == NULL) 986 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 987 return (bf); 988} 989 990static struct urtwn_data * 991urtwn_getbuf(struct urtwn_softc *sc) 992{ 993 struct urtwn_data *bf; 994 995 URTWN_ASSERT_LOCKED(sc); 996 997 bf = _urtwn_getbuf(sc); 998 if (bf == NULL) 999 DPRINTF("%s: stop queue\n", __func__); 1000 return (bf); 1001} 1002 1003static int 1004urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1005 int len) 1006{ 1007 usb_device_request_t req; 1008 1009 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1010 req.bRequest = R92C_REQ_REGS; 1011 USETW(req.wValue, addr); 1012 USETW(req.wIndex, 0); 1013 USETW(req.wLength, len); 1014 return (urtwn_do_request(sc, &req, buf)); 1015} 1016 1017static void 1018urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1019{ 1020 urtwn_write_region_1(sc, addr, &val, 1); 1021} 1022 1023 1024static void 1025urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1026{ 1027 val = htole16(val); 1028 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1029} 1030 1031static void 1032urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1033{ 1034 val = htole32(val); 1035 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1036} 1037 1038static int 1039urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1040 int len) 1041{ 1042 usb_device_request_t req; 1043 1044 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1045 req.bRequest = R92C_REQ_REGS; 1046 USETW(req.wValue, addr); 1047 USETW(req.wIndex, 0); 1048 USETW(req.wLength, len); 1049 return (urtwn_do_request(sc, &req, buf)); 1050} 1051 1052static uint8_t 1053urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1054{ 1055 uint8_t val; 1056 1057 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1058 return (0xff); 1059 return (val); 1060} 1061 1062static uint16_t 1063urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1064{ 1065 uint16_t val; 1066 1067 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1068 return (0xffff); 1069 return (le16toh(val)); 1070} 1071 1072static uint32_t 1073urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1074{ 1075 uint32_t val; 1076 1077 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1078 return (0xffffffff); 1079 return (le32toh(val)); 1080} 1081 1082static int 1083urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1084{ 1085 struct r92c_fw_cmd cmd; 1086 int ntries; 1087 1088 /* Wait for current FW box to be empty. */ 1089 for (ntries = 0; ntries < 100; ntries++) { 1090 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1091 break; 1092 urtwn_ms_delay(sc); 1093 } 1094 if (ntries == 100) { 1095 device_printf(sc->sc_dev, 1096 "could not send firmware command\n"); 1097 return (ETIMEDOUT); 1098 } 1099 memset(&cmd, 0, sizeof(cmd)); 1100 cmd.id = id; 1101 if (len > 3) 1102 cmd.id |= R92C_CMD_FLAG_EXT; 1103 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1104 memcpy(cmd.msg, buf, len); 1105 1106 /* Write the first word last since that will trigger the FW. */ 1107 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1108 (uint8_t *)&cmd + 4, 2); 1109 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1110 (uint8_t *)&cmd + 0, 4); 1111 1112 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1113 return (0); 1114} 1115 1116static __inline void 1117urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1118{ 1119 1120 sc->sc_rf_write(sc, chain, addr, val); 1121} 1122 1123static void 1124urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1125 uint32_t val) 1126{ 1127 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1128 SM(R92C_LSSI_PARAM_ADDR, addr) | 1129 SM(R92C_LSSI_PARAM_DATA, val)); 1130} 1131 1132static void 1133urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1134uint32_t val) 1135{ 1136 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1137 SM(R88E_LSSI_PARAM_ADDR, addr) | 1138 SM(R92C_LSSI_PARAM_DATA, val)); 1139} 1140 1141static uint32_t 1142urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1143{ 1144 uint32_t reg[R92C_MAX_CHAINS], val; 1145 1146 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1147 if (chain != 0) 1148 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1149 1150 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1151 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1152 urtwn_ms_delay(sc); 1153 1154 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1155 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1156 R92C_HSSI_PARAM2_READ_EDGE); 1157 urtwn_ms_delay(sc); 1158 1159 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1160 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1161 urtwn_ms_delay(sc); 1162 1163 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1164 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1165 else 1166 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1167 return (MS(val, R92C_LSSI_READBACK_DATA)); 1168} 1169 1170static int 1171urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1172{ 1173 int ntries; 1174 1175 urtwn_write_4(sc, R92C_LLT_INIT, 1176 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1177 SM(R92C_LLT_INIT_ADDR, addr) | 1178 SM(R92C_LLT_INIT_DATA, data)); 1179 /* Wait for write operation to complete. */ 1180 for (ntries = 0; ntries < 20; ntries++) { 1181 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1182 R92C_LLT_INIT_OP_NO_ACTIVE) 1183 return (0); 1184 urtwn_ms_delay(sc); 1185 } 1186 return (ETIMEDOUT); 1187} 1188 1189static uint8_t 1190urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1191{ 1192 uint32_t reg; 1193 int ntries; 1194 1195 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1196 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1197 reg &= ~R92C_EFUSE_CTRL_VALID; 1198 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1199 /* Wait for read operation to complete. */ 1200 for (ntries = 0; ntries < 100; ntries++) { 1201 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1202 if (reg & R92C_EFUSE_CTRL_VALID) 1203 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1204 urtwn_ms_delay(sc); 1205 } 1206 device_printf(sc->sc_dev, 1207 "could not read efuse byte at address 0x%x\n", addr); 1208 return (0xff); 1209} 1210 1211static void 1212urtwn_efuse_read(struct urtwn_softc *sc) 1213{ 1214 uint8_t *rom = (uint8_t *)&sc->rom; 1215 uint16_t addr = 0; 1216 uint32_t reg; 1217 uint8_t off, msk; 1218 int i; 1219 1220 urtwn_efuse_switch_power(sc); 1221 1222 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1223 while (addr < 512) { 1224 reg = urtwn_efuse_read_1(sc, addr); 1225 if (reg == 0xff) 1226 break; 1227 addr++; 1228 off = reg >> 4; 1229 msk = reg & 0xf; 1230 for (i = 0; i < 4; i++) { 1231 if (msk & (1 << i)) 1232 continue; 1233 rom[off * 8 + i * 2 + 0] = 1234 urtwn_efuse_read_1(sc, addr); 1235 addr++; 1236 rom[off * 8 + i * 2 + 1] = 1237 urtwn_efuse_read_1(sc, addr); 1238 addr++; 1239 } 1240 } 1241#ifdef URTWN_DEBUG 1242 if (urtwn_debug >= 2) { 1243 /* Dump ROM content. */ 1244 printf("\n"); 1245 for (i = 0; i < sizeof(sc->rom); i++) 1246 printf("%02x:", rom[i]); 1247 printf("\n"); 1248 } 1249#endif 1250 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1251} 1252 1253static void 1254urtwn_efuse_switch_power(struct urtwn_softc *sc) 1255{ 1256 uint32_t reg; 1257 1258 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1259 1260 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1261 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1262 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1263 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1264 } 1265 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1266 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1267 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1268 reg | R92C_SYS_FUNC_EN_ELDR); 1269 } 1270 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1271 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1272 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1273 urtwn_write_2(sc, R92C_SYS_CLKR, 1274 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1275 } 1276} 1277 1278static int 1279urtwn_read_chipid(struct urtwn_softc *sc) 1280{ 1281 uint32_t reg; 1282 1283 if (sc->chip & URTWN_CHIP_88E) 1284 return (0); 1285 1286 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1287 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1288 return (EIO); 1289 1290 if (reg & R92C_SYS_CFG_TYPE_92C) { 1291 sc->chip |= URTWN_CHIP_92C; 1292 /* Check if it is a castrated 8192C. */ 1293 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1294 R92C_HPON_FSM_CHIP_BONDING_ID) == 1295 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1296 sc->chip |= URTWN_CHIP_92C_1T2R; 1297 } 1298 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1299 sc->chip |= URTWN_CHIP_UMC; 1300 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1301 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1302 } 1303 return (0); 1304} 1305 1306static void 1307urtwn_read_rom(struct urtwn_softc *sc) 1308{ 1309 struct r92c_rom *rom = &sc->rom; 1310 1311 /* Read full ROM image. */ 1312 urtwn_efuse_read(sc); 1313 1314 /* XXX Weird but this is what the vendor driver does. */ 1315 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1316 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1317 1318 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1319 1320 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1321 DPRINTF("regulatory type=%d\n", sc->regulatory); 1322 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1323 1324 sc->sc_rf_write = urtwn_r92c_rf_write; 1325 sc->sc_power_on = urtwn_r92c_power_on; 1326 sc->sc_dma_init = urtwn_r92c_dma_init; 1327} 1328 1329static void 1330urtwn_r88e_read_rom(struct urtwn_softc *sc) 1331{ 1332 uint8_t *rom = sc->r88e_rom; 1333 uint16_t addr = 0; 1334 uint32_t reg; 1335 uint8_t off, msk, tmp; 1336 int i; 1337 1338 off = 0; 1339 urtwn_efuse_switch_power(sc); 1340 1341 /* Read full ROM image. */ 1342 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1343 while (addr < 512) { 1344 reg = urtwn_efuse_read_1(sc, addr); 1345 if (reg == 0xff) 1346 break; 1347 addr++; 1348 if ((reg & 0x1f) == 0x0f) { 1349 tmp = (reg & 0xe0) >> 5; 1350 reg = urtwn_efuse_read_1(sc, addr); 1351 if ((reg & 0x0f) != 0x0f) 1352 off = ((reg & 0xf0) >> 1) | tmp; 1353 addr++; 1354 } else 1355 off = reg >> 4; 1356 msk = reg & 0xf; 1357 for (i = 0; i < 4; i++) { 1358 if (msk & (1 << i)) 1359 continue; 1360 rom[off * 8 + i * 2 + 0] = 1361 urtwn_efuse_read_1(sc, addr); 1362 addr++; 1363 rom[off * 8 + i * 2 + 1] = 1364 urtwn_efuse_read_1(sc, addr); 1365 addr++; 1366 } 1367 } 1368 1369 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1370 1371 addr = 0x10; 1372 for (i = 0; i < 6; i++) 1373 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1374 for (i = 0; i < 5; i++) 1375 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1376 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1377 if (sc->bw20_tx_pwr_diff & 0x08) 1378 sc->bw20_tx_pwr_diff |= 0xf0; 1379 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1380 if (sc->ofdm_tx_pwr_diff & 0x08) 1381 sc->ofdm_tx_pwr_diff |= 0xf0; 1382 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1383 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &sc->r88e_rom[0xd7]); 1384 1385 sc->sc_rf_write = urtwn_r88e_rf_write; 1386 sc->sc_power_on = urtwn_r88e_power_on; 1387 sc->sc_dma_init = urtwn_r88e_dma_init; 1388} 1389 1390/* 1391 * Initialize rate adaptation in firmware. 1392 */ 1393static int 1394urtwn_ra_init(struct urtwn_softc *sc) 1395{ 1396 struct ieee80211com *ic = &sc->sc_ic; 1397 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1398 struct ieee80211_node *ni; 1399 struct ieee80211_rateset *rs; 1400 struct r92c_fw_cmd_macid_cfg cmd; 1401 uint32_t rates, basicrates; 1402 uint8_t mode; 1403 int maxrate, maxbasicrate, error, i, j; 1404 1405 ni = ieee80211_ref_node(vap->iv_bss); 1406 rs = &ni->ni_rates; 1407 1408 /* Get normal and basic rates mask. */ 1409 rates = basicrates = 0; 1410 maxrate = maxbasicrate = 0; 1411 for (i = 0; i < rs->rs_nrates; i++) { 1412 /* Convert 802.11 rate to HW rate index. */ 1413 for (j = 0; j < nitems(ridx2rate); j++) 1414 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1415 ridx2rate[j]) 1416 break; 1417 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1418 continue; 1419 rates |= 1 << j; 1420 if (j > maxrate) 1421 maxrate = j; 1422 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1423 basicrates |= 1 << j; 1424 if (j > maxbasicrate) 1425 maxbasicrate = j; 1426 } 1427 } 1428 if (ic->ic_curmode == IEEE80211_MODE_11B) 1429 mode = R92C_RAID_11B; 1430 else 1431 mode = R92C_RAID_11BG; 1432 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1433 mode, rates, basicrates); 1434 1435 /* Set rates mask for group addressed frames. */ 1436 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1437 cmd.mask = htole32(mode << 28 | basicrates); 1438 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1439 if (error != 0) { 1440 ieee80211_free_node(ni); 1441 device_printf(sc->sc_dev, 1442 "could not add broadcast station\n"); 1443 return (error); 1444 } 1445 /* Set initial MRR rate. */ 1446 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1447 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1448 maxbasicrate); 1449 1450 /* Set rates mask for unicast frames. */ 1451 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1452 cmd.mask = htole32(mode << 28 | rates); 1453 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1454 if (error != 0) { 1455 ieee80211_free_node(ni); 1456 device_printf(sc->sc_dev, "could not add BSS station\n"); 1457 return (error); 1458 } 1459 /* Set initial MRR rate. */ 1460 DPRINTF("maxrate=%d\n", maxrate); 1461 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1462 maxrate); 1463 1464 /* Indicate highest supported rate. */ 1465 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1466 ieee80211_free_node(ni); 1467 1468 return (0); 1469} 1470 1471void 1472urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1473{ 1474 struct ieee80211com *ic = &sc->sc_ic; 1475 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1476 struct ieee80211_node *ni = vap->iv_bss; 1477 1478 uint64_t tsf; 1479 1480 /* Enable TSF synchronization. */ 1481 urtwn_write_1(sc, R92C_BCN_CTRL, 1482 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1483 1484 urtwn_write_1(sc, R92C_BCN_CTRL, 1485 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1486 1487 /* Set initial TSF. */ 1488 memcpy(&tsf, ni->ni_tstamp.data, 8); 1489 tsf = le64toh(tsf); 1490 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1491 tsf -= IEEE80211_DUR_TU; 1492 urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1493 urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1494 1495 urtwn_write_1(sc, R92C_BCN_CTRL, 1496 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1497} 1498 1499static void 1500urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1501{ 1502 uint8_t reg; 1503 1504 if (led == URTWN_LED_LINK) { 1505 if (sc->chip & URTWN_CHIP_88E) { 1506 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1507 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1508 if (!on) { 1509 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1510 urtwn_write_1(sc, R92C_LEDCFG2, 1511 reg | R92C_LEDCFG0_DIS); 1512 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1513 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1514 0xfe); 1515 } 1516 } else { 1517 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1518 if (!on) 1519 reg |= R92C_LEDCFG0_DIS; 1520 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1521 } 1522 sc->ledlink = on; /* Save LED state. */ 1523 } 1524} 1525 1526static void 1527urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 1528{ 1529 uint8_t reg; 1530 1531 reg = urtwn_read_1(sc, R92C_MSR); 1532 reg = (reg & ~R92C_MSR_MASK) | mode; 1533 urtwn_write_1(sc, R92C_MSR, reg); 1534} 1535 1536static int 1537urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1538{ 1539 struct urtwn_vap *uvp = URTWN_VAP(vap); 1540 struct ieee80211com *ic = vap->iv_ic; 1541 struct urtwn_softc *sc = ic->ic_softc; 1542 struct ieee80211_node *ni; 1543 enum ieee80211_state ostate; 1544 uint32_t reg; 1545 1546 ostate = vap->iv_state; 1547 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1548 ieee80211_state_name[nstate]); 1549 1550 IEEE80211_UNLOCK(ic); 1551 URTWN_LOCK(sc); 1552 callout_stop(&sc->sc_watchdog_ch); 1553 1554 if (ostate == IEEE80211_S_RUN) { 1555 /* Turn link LED off. */ 1556 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1557 1558 /* Set media status to 'No Link'. */ 1559 urtwn_set_mode(sc, R92C_MSR_NOLINK); 1560 1561 /* Stop Rx of data frames. */ 1562 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1563 1564 /* Rest TSF. */ 1565 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1566 1567 /* Disable TSF synchronization. */ 1568 urtwn_write_1(sc, R92C_BCN_CTRL, 1569 urtwn_read_1(sc, R92C_BCN_CTRL) | 1570 R92C_BCN_CTRL_DIS_TSF_UDT0); 1571 1572 /* Reset EDCA parameters. */ 1573 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1574 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1575 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1576 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1577 } 1578 1579 switch (nstate) { 1580 case IEEE80211_S_INIT: 1581 /* Turn link LED off. */ 1582 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1583 break; 1584 case IEEE80211_S_SCAN: 1585 if (ostate != IEEE80211_S_SCAN) { 1586 /* Allow Rx from any BSSID. */ 1587 urtwn_write_4(sc, R92C_RCR, 1588 urtwn_read_4(sc, R92C_RCR) & 1589 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1590 1591 /* Set gain for scanning. */ 1592 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1593 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1594 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1595 1596 if (!(sc->chip & URTWN_CHIP_88E)) { 1597 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1598 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1599 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1600 } 1601 } 1602 /* Pause AC Tx queues. */ 1603 urtwn_write_1(sc, R92C_TXPAUSE, 1604 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1605 break; 1606 case IEEE80211_S_AUTH: 1607 /* Set initial gain under link. */ 1608 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1609 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1610 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1611 1612 if (!(sc->chip & URTWN_CHIP_88E)) { 1613 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1614 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1615 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1616 } 1617 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1618 break; 1619 case IEEE80211_S_RUN: 1620 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1621 /* Enable Rx of data frames. */ 1622 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1623 1624 /* Enable Rx of ctrl frames. */ 1625 urtwn_write_2(sc, R92C_RXFLTMAP1, 0xffff); 1626 1627 /* 1628 * Accept data/control/management frames 1629 * from any BSSID. 1630 */ 1631 urtwn_write_4(sc, R92C_RCR, 1632 (urtwn_read_4(sc, R92C_RCR) & ~(R92C_RCR_APM | 1633 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)) | 1634 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF | 1635 R92C_RCR_AAP); 1636 1637 /* Turn link LED on. */ 1638 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1639 break; 1640 } 1641 1642 ni = ieee80211_ref_node(vap->iv_bss); 1643 /* Set media status to 'Associated'. */ 1644 urtwn_set_mode(sc, R92C_MSR_INFRA); 1645 1646 /* Set BSSID. */ 1647 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1648 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1649 1650 if (ic->ic_curmode == IEEE80211_MODE_11B) 1651 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1652 else /* 802.11b/g */ 1653 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1654 1655 /* Enable Rx of data frames. */ 1656 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1657 1658 /* Flush all AC queues. */ 1659 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1660 1661 /* Set beacon interval. */ 1662 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1663 1664 /* Allow Rx from our BSSID only. */ 1665 urtwn_write_4(sc, R92C_RCR, 1666 urtwn_read_4(sc, R92C_RCR) | 1667 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1668 1669 /* Enable TSF synchronization. */ 1670 urtwn_tsf_sync_enable(sc); 1671 1672 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1673 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1674 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1675 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1676 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1677 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1678 1679 /* Intialize rate adaptation. */ 1680 if (sc->chip & URTWN_CHIP_88E) 1681 ni->ni_txrate = 1682 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1683 else 1684 urtwn_ra_init(sc); 1685 /* Turn link LED on. */ 1686 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1687 1688 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1689 /* Reset temperature calibration state machine. */ 1690 sc->thcal_state = 0; 1691 sc->thcal_lctemp = 0; 1692 ieee80211_free_node(ni); 1693 break; 1694 default: 1695 break; 1696 } 1697 URTWN_UNLOCK(sc); 1698 IEEE80211_LOCK(ic); 1699 return(uvp->newstate(vap, nstate, arg)); 1700} 1701 1702static void 1703urtwn_watchdog(void *arg) 1704{ 1705 struct urtwn_softc *sc = arg; 1706 1707 if (sc->sc_txtimer > 0) { 1708 if (--sc->sc_txtimer == 0) { 1709 device_printf(sc->sc_dev, "device timeout\n"); 1710 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1711 return; 1712 } 1713 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1714 } 1715} 1716 1717static void 1718urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1719{ 1720 int pwdb; 1721 1722 /* Convert antenna signal to percentage. */ 1723 if (rssi <= -100 || rssi >= 20) 1724 pwdb = 0; 1725 else if (rssi >= 0) 1726 pwdb = 100; 1727 else 1728 pwdb = 100 + rssi; 1729 if (!(sc->chip & URTWN_CHIP_88E)) { 1730 if (rate <= URTWN_RIDX_CCK11) { 1731 /* CCK gain is smaller than OFDM/MCS gain. */ 1732 pwdb += 6; 1733 if (pwdb > 100) 1734 pwdb = 100; 1735 if (pwdb <= 14) 1736 pwdb -= 4; 1737 else if (pwdb <= 26) 1738 pwdb -= 8; 1739 else if (pwdb <= 34) 1740 pwdb -= 6; 1741 else if (pwdb <= 42) 1742 pwdb -= 2; 1743 } 1744 } 1745 if (sc->avg_pwdb == -1) /* Init. */ 1746 sc->avg_pwdb = pwdb; 1747 else if (sc->avg_pwdb < pwdb) 1748 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1749 else 1750 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1751 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1752} 1753 1754static int8_t 1755urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1756{ 1757 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1758 struct r92c_rx_phystat *phy; 1759 struct r92c_rx_cck *cck; 1760 uint8_t rpt; 1761 int8_t rssi; 1762 1763 if (rate <= URTWN_RIDX_CCK11) { 1764 cck = (struct r92c_rx_cck *)physt; 1765 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1766 rpt = (cck->agc_rpt >> 5) & 0x3; 1767 rssi = (cck->agc_rpt & 0x1f) << 1; 1768 } else { 1769 rpt = (cck->agc_rpt >> 6) & 0x3; 1770 rssi = cck->agc_rpt & 0x3e; 1771 } 1772 rssi = cckoff[rpt] - rssi; 1773 } else { /* OFDM/HT. */ 1774 phy = (struct r92c_rx_phystat *)physt; 1775 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1776 } 1777 return (rssi); 1778} 1779 1780static int8_t 1781urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1782{ 1783 struct r92c_rx_phystat *phy; 1784 struct r88e_rx_cck *cck; 1785 uint8_t cck_agc_rpt, lna_idx, vga_idx; 1786 int8_t rssi; 1787 1788 rssi = 0; 1789 if (rate <= URTWN_RIDX_CCK11) { 1790 cck = (struct r88e_rx_cck *)physt; 1791 cck_agc_rpt = cck->agc_rpt; 1792 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1793 vga_idx = cck_agc_rpt & 0x1f; 1794 switch (lna_idx) { 1795 case 7: 1796 if (vga_idx <= 27) 1797 rssi = -100 + 2* (27 - vga_idx); 1798 else 1799 rssi = -100; 1800 break; 1801 case 6: 1802 rssi = -48 + 2 * (2 - vga_idx); 1803 break; 1804 case 5: 1805 rssi = -42 + 2 * (7 - vga_idx); 1806 break; 1807 case 4: 1808 rssi = -36 + 2 * (7 - vga_idx); 1809 break; 1810 case 3: 1811 rssi = -24 + 2 * (7 - vga_idx); 1812 break; 1813 case 2: 1814 rssi = -12 + 2 * (5 - vga_idx); 1815 break; 1816 case 1: 1817 rssi = 8 - (2 * vga_idx); 1818 break; 1819 case 0: 1820 rssi = 14 - (2 * vga_idx); 1821 break; 1822 } 1823 rssi += 6; 1824 } else { /* OFDM/HT. */ 1825 phy = (struct r92c_rx_phystat *)physt; 1826 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1827 } 1828 return (rssi); 1829} 1830 1831static int 1832urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1833 struct mbuf *m0, struct urtwn_data *data) 1834{ 1835 struct ieee80211_frame *wh; 1836 struct ieee80211_key *k; 1837 struct ieee80211com *ic = &sc->sc_ic; 1838 struct ieee80211vap *vap = ni->ni_vap; 1839 struct usb_xfer *xfer; 1840 struct r92c_tx_desc *txd; 1841 uint8_t raid, type; 1842 uint16_t sum; 1843 int i, xferlen; 1844 struct usb_xfer *urtwn_pipes[4] = { 1845 sc->sc_xfer[URTWN_BULK_TX_BE], 1846 sc->sc_xfer[URTWN_BULK_TX_BK], 1847 sc->sc_xfer[URTWN_BULK_TX_VI], 1848 sc->sc_xfer[URTWN_BULK_TX_VO] 1849 }; 1850 1851 URTWN_ASSERT_LOCKED(sc); 1852 1853 /* 1854 * Software crypto. 1855 */ 1856 wh = mtod(m0, struct ieee80211_frame *); 1857 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1858 1859 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1860 k = ieee80211_crypto_encap(ni, m0); 1861 if (k == NULL) { 1862 device_printf(sc->sc_dev, 1863 "ieee80211_crypto_encap returns NULL.\n"); 1864 /* XXX we don't expect the fragmented frames */ 1865 return (ENOBUFS); 1866 } 1867 1868 /* in case packet header moved, reset pointer */ 1869 wh = mtod(m0, struct ieee80211_frame *); 1870 } 1871 1872 switch (type) { 1873 case IEEE80211_FC0_TYPE_CTL: 1874 case IEEE80211_FC0_TYPE_MGT: 1875 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1876 break; 1877 default: 1878 KASSERT(M_WME_GETAC(m0) < 4, 1879 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1880 xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1881 break; 1882 } 1883 1884 /* Fill Tx descriptor. */ 1885 txd = (struct r92c_tx_desc *)data->buf; 1886 memset(txd, 0, sizeof(*txd)); 1887 1888 txd->txdw0 |= htole32( 1889 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1890 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1891 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1892 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1893 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1894 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1895 type == IEEE80211_FC0_TYPE_DATA) { 1896 if (ic->ic_curmode == IEEE80211_MODE_11B) 1897 raid = R92C_RAID_11B; 1898 else 1899 raid = R92C_RAID_11BG; 1900 if (sc->chip & URTWN_CHIP_88E) { 1901 txd->txdw1 |= htole32( 1902 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1903 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1904 SM(R92C_TXDW1_RAID, raid)); 1905 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1906 } else { 1907 txd->txdw1 |= htole32( 1908 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1909 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1910 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1911 } 1912 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1913 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1914 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1915 R92C_TXDW4_HWRTSEN); 1916 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1917 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1918 R92C_TXDW4_HWRTSEN); 1919 } 1920 } 1921 /* Send RTS at OFDM24. */ 1922 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1923 URTWN_RIDX_OFDM24)); 1924 txd->txdw5 |= htole32(0x0001ff00); 1925 /* Send data at OFDM54. */ 1926 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1927 URTWN_RIDX_OFDM54)); 1928 } else { 1929 txd->txdw1 |= htole32( 1930 SM(R92C_TXDW1_MACID, 0) | 1931 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1932 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1933 1934 /* Force CCK1. */ 1935 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1936 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1937 URTWN_RIDX_CCK1)); 1938 } 1939 /* Set sequence number (already little endian). */ 1940 txd->txdseq |= *(uint16_t *)wh->i_seq; 1941 1942 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 1943 /* Use HW sequence numbering for non-QoS frames. */ 1944 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1945 txd->txdseq |= htole16(0x8000); 1946 } else 1947 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1948 1949 /* Compute Tx descriptor checksum. */ 1950 sum = 0; 1951 for (i = 0; i < sizeof(*txd) / 2; i++) 1952 sum ^= ((uint16_t *)txd)[i]; 1953 txd->txdsum = sum; /* NB: already little endian. */ 1954 1955 if (ieee80211_radiotap_active_vap(vap)) { 1956 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1957 1958 tap->wt_flags = 0; 1959 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1960 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1961 ieee80211_radiotap_tx(vap, m0); 1962 } 1963 1964 xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1965 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1966 1967 data->buflen = xferlen; 1968 data->ni = ni; 1969 data->m = m0; 1970 1971 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1972 usbd_transfer_start(xfer); 1973 return (0); 1974} 1975 1976static int 1977urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1978{ 1979 struct urtwn_softc *sc = ic->ic_softc; 1980 int error; 1981 1982 URTWN_LOCK(sc); 1983 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1984 URTWN_UNLOCK(sc); 1985 return (ENXIO); 1986 } 1987 error = mbufq_enqueue(&sc->sc_snd, m); 1988 if (error) { 1989 URTWN_UNLOCK(sc); 1990 return (error); 1991 } 1992 urtwn_start(sc); 1993 URTWN_UNLOCK(sc); 1994 1995 return (0); 1996} 1997 1998static void 1999urtwn_start(struct urtwn_softc *sc) 2000{ 2001 struct ieee80211_node *ni; 2002 struct mbuf *m; 2003 struct urtwn_data *bf; 2004 2005 URTWN_ASSERT_LOCKED(sc); 2006 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2007 bf = urtwn_getbuf(sc); 2008 if (bf == NULL) { 2009 mbufq_prepend(&sc->sc_snd, m); 2010 break; 2011 } 2012 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2013 m->m_pkthdr.rcvif = NULL; 2014 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 2015 if_inc_counter(ni->ni_vap->iv_ifp, 2016 IFCOUNTER_OERRORS, 1); 2017 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2018 m_freem(m); 2019 ieee80211_free_node(ni); 2020 break; 2021 } 2022 sc->sc_txtimer = 5; 2023 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2024 } 2025} 2026 2027static void 2028urtwn_parent(struct ieee80211com *ic) 2029{ 2030 struct urtwn_softc *sc = ic->ic_softc; 2031 int startall = 0; 2032 2033 URTWN_LOCK(sc); 2034 if (sc->sc_flags & URTWN_DETACHED) { 2035 URTWN_UNLOCK(sc); 2036 return; 2037 } 2038 if (ic->ic_nrunning > 0) { 2039 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2040 urtwn_init(sc); 2041 startall = 1; 2042 } 2043 } else if (sc->sc_flags & URTWN_RUNNING) 2044 urtwn_stop(sc); 2045 URTWN_UNLOCK(sc); 2046 2047 if (startall) 2048 ieee80211_start_all(ic); 2049} 2050 2051static __inline int 2052urtwn_power_on(struct urtwn_softc *sc) 2053{ 2054 2055 return sc->sc_power_on(sc); 2056} 2057 2058static int 2059urtwn_r92c_power_on(struct urtwn_softc *sc) 2060{ 2061 uint32_t reg; 2062 int ntries; 2063 2064 /* Wait for autoload done bit. */ 2065 for (ntries = 0; ntries < 1000; ntries++) { 2066 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2067 break; 2068 urtwn_ms_delay(sc); 2069 } 2070 if (ntries == 1000) { 2071 device_printf(sc->sc_dev, 2072 "timeout waiting for chip autoload\n"); 2073 return (ETIMEDOUT); 2074 } 2075 2076 /* Unlock ISO/CLK/Power control register. */ 2077 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2078 /* Move SPS into PWM mode. */ 2079 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2080 urtwn_ms_delay(sc); 2081 2082 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2083 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2084 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2085 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2086 urtwn_ms_delay(sc); 2087 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2088 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2089 ~R92C_SYS_ISO_CTRL_MD2PP); 2090 } 2091 2092 /* Auto enable WLAN. */ 2093 urtwn_write_2(sc, R92C_APS_FSMCO, 2094 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2095 for (ntries = 0; ntries < 1000; ntries++) { 2096 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2097 R92C_APS_FSMCO_APFM_ONMAC)) 2098 break; 2099 urtwn_ms_delay(sc); 2100 } 2101 if (ntries == 1000) { 2102 device_printf(sc->sc_dev, 2103 "timeout waiting for MAC auto ON\n"); 2104 return (ETIMEDOUT); 2105 } 2106 2107 /* Enable radio, GPIO and LED functions. */ 2108 urtwn_write_2(sc, R92C_APS_FSMCO, 2109 R92C_APS_FSMCO_AFSM_HSUS | 2110 R92C_APS_FSMCO_PDN_EN | 2111 R92C_APS_FSMCO_PFM_ALDN); 2112 /* Release RF digital isolation. */ 2113 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2114 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2115 2116 /* Initialize MAC. */ 2117 urtwn_write_1(sc, R92C_APSD_CTRL, 2118 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2119 for (ntries = 0; ntries < 200; ntries++) { 2120 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2121 R92C_APSD_CTRL_OFF_STATUS)) 2122 break; 2123 urtwn_ms_delay(sc); 2124 } 2125 if (ntries == 200) { 2126 device_printf(sc->sc_dev, 2127 "timeout waiting for MAC initialization\n"); 2128 return (ETIMEDOUT); 2129 } 2130 2131 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2132 reg = urtwn_read_2(sc, R92C_CR); 2133 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2134 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2135 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2136 R92C_CR_ENSEC; 2137 urtwn_write_2(sc, R92C_CR, reg); 2138 2139 urtwn_write_1(sc, 0xfe10, 0x19); 2140 return (0); 2141} 2142 2143static int 2144urtwn_r88e_power_on(struct urtwn_softc *sc) 2145{ 2146 uint32_t reg; 2147 int ntries; 2148 2149 /* Wait for power ready bit. */ 2150 for (ntries = 0; ntries < 5000; ntries++) { 2151 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2152 break; 2153 urtwn_ms_delay(sc); 2154 } 2155 if (ntries == 5000) { 2156 device_printf(sc->sc_dev, 2157 "timeout waiting for chip power up\n"); 2158 return (ETIMEDOUT); 2159 } 2160 2161 /* Reset BB. */ 2162 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2163 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2164 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2165 2166 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2167 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2168 2169 /* Disable HWPDN. */ 2170 urtwn_write_2(sc, R92C_APS_FSMCO, 2171 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2172 2173 /* Disable WL suspend. */ 2174 urtwn_write_2(sc, R92C_APS_FSMCO, 2175 urtwn_read_2(sc, R92C_APS_FSMCO) & 2176 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2177 2178 urtwn_write_2(sc, R92C_APS_FSMCO, 2179 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2180 for (ntries = 0; ntries < 5000; ntries++) { 2181 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2182 R92C_APS_FSMCO_APFM_ONMAC)) 2183 break; 2184 urtwn_ms_delay(sc); 2185 } 2186 if (ntries == 5000) 2187 return (ETIMEDOUT); 2188 2189 /* Enable LDO normal mode. */ 2190 urtwn_write_1(sc, R92C_LPLDO_CTRL, 2191 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2192 2193 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2194 urtwn_write_2(sc, R92C_CR, 0); 2195 reg = urtwn_read_2(sc, R92C_CR); 2196 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2197 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2198 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2199 urtwn_write_2(sc, R92C_CR, reg); 2200 2201 return (0); 2202} 2203 2204static int 2205urtwn_llt_init(struct urtwn_softc *sc) 2206{ 2207 int i, error, page_count, pktbuf_count; 2208 2209 page_count = (sc->chip & URTWN_CHIP_88E) ? 2210 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2211 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2212 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2213 2214 /* Reserve pages [0; page_count]. */ 2215 for (i = 0; i < page_count; i++) { 2216 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2217 return (error); 2218 } 2219 /* NB: 0xff indicates end-of-list. */ 2220 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2221 return (error); 2222 /* 2223 * Use pages [page_count + 1; pktbuf_count - 1] 2224 * as ring buffer. 2225 */ 2226 for (++i; i < pktbuf_count - 1; i++) { 2227 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2228 return (error); 2229 } 2230 /* Make the last page point to the beginning of the ring buffer. */ 2231 error = urtwn_llt_write(sc, i, page_count + 1); 2232 return (error); 2233} 2234 2235static void 2236urtwn_fw_reset(struct urtwn_softc *sc) 2237{ 2238 uint16_t reg; 2239 int ntries; 2240 2241 /* Tell 8051 to reset itself. */ 2242 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2243 2244 /* Wait until 8051 resets by itself. */ 2245 for (ntries = 0; ntries < 100; ntries++) { 2246 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2247 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2248 return; 2249 urtwn_ms_delay(sc); 2250 } 2251 /* Force 8051 reset. */ 2252 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2253} 2254 2255static void 2256urtwn_r88e_fw_reset(struct urtwn_softc *sc) 2257{ 2258 uint16_t reg; 2259 2260 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2261 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2262 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2263} 2264 2265static int 2266urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2267{ 2268 uint32_t reg; 2269 int off, mlen, error = 0; 2270 2271 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2272 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2273 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2274 2275 off = R92C_FW_START_ADDR; 2276 while (len > 0) { 2277 if (len > 196) 2278 mlen = 196; 2279 else if (len > 4) 2280 mlen = 4; 2281 else 2282 mlen = 1; 2283 /* XXX fix this deconst */ 2284 error = urtwn_write_region_1(sc, off, 2285 __DECONST(uint8_t *, buf), mlen); 2286 if (error != 0) 2287 break; 2288 off += mlen; 2289 buf += mlen; 2290 len -= mlen; 2291 } 2292 return (error); 2293} 2294 2295static int 2296urtwn_load_firmware(struct urtwn_softc *sc) 2297{ 2298 const struct firmware *fw; 2299 const struct r92c_fw_hdr *hdr; 2300 const char *imagename; 2301 const u_char *ptr; 2302 size_t len; 2303 uint32_t reg; 2304 int mlen, ntries, page, error; 2305 2306 URTWN_UNLOCK(sc); 2307 /* Read firmware image from the filesystem. */ 2308 if (sc->chip & URTWN_CHIP_88E) 2309 imagename = "urtwn-rtl8188eufw"; 2310 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2311 URTWN_CHIP_UMC_A_CUT) 2312 imagename = "urtwn-rtl8192cfwU"; 2313 else 2314 imagename = "urtwn-rtl8192cfwT"; 2315 2316 fw = firmware_get(imagename); 2317 URTWN_LOCK(sc); 2318 if (fw == NULL) { 2319 device_printf(sc->sc_dev, 2320 "failed loadfirmware of file %s\n", imagename); 2321 return (ENOENT); 2322 } 2323 2324 len = fw->datasize; 2325 2326 if (len < sizeof(*hdr)) { 2327 device_printf(sc->sc_dev, "firmware too short\n"); 2328 error = EINVAL; 2329 goto fail; 2330 } 2331 ptr = fw->data; 2332 hdr = (const struct r92c_fw_hdr *)ptr; 2333 /* Check if there is a valid FW header and skip it. */ 2334 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2335 (le16toh(hdr->signature) >> 4) == 0x88e || 2336 (le16toh(hdr->signature) >> 4) == 0x92c) { 2337 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2338 le16toh(hdr->version), le16toh(hdr->subversion), 2339 hdr->month, hdr->date, hdr->hour, hdr->minute); 2340 ptr += sizeof(*hdr); 2341 len -= sizeof(*hdr); 2342 } 2343 2344 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2345 if (sc->chip & URTWN_CHIP_88E) 2346 urtwn_r88e_fw_reset(sc); 2347 else 2348 urtwn_fw_reset(sc); 2349 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2350 } 2351 2352 if (!(sc->chip & URTWN_CHIP_88E)) { 2353 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2354 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2355 R92C_SYS_FUNC_EN_CPUEN); 2356 } 2357 urtwn_write_1(sc, R92C_MCUFWDL, 2358 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2359 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2360 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2361 2362 /* Reset the FWDL checksum. */ 2363 urtwn_write_1(sc, R92C_MCUFWDL, 2364 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2365 2366 for (page = 0; len > 0; page++) { 2367 mlen = min(len, R92C_FW_PAGE_SIZE); 2368 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2369 if (error != 0) { 2370 device_printf(sc->sc_dev, 2371 "could not load firmware page\n"); 2372 goto fail; 2373 } 2374 ptr += mlen; 2375 len -= mlen; 2376 } 2377 urtwn_write_1(sc, R92C_MCUFWDL, 2378 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2379 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2380 2381 /* Wait for checksum report. */ 2382 for (ntries = 0; ntries < 1000; ntries++) { 2383 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2384 break; 2385 urtwn_ms_delay(sc); 2386 } 2387 if (ntries == 1000) { 2388 device_printf(sc->sc_dev, 2389 "timeout waiting for checksum report\n"); 2390 error = ETIMEDOUT; 2391 goto fail; 2392 } 2393 2394 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2395 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2396 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2397 if (sc->chip & URTWN_CHIP_88E) 2398 urtwn_r88e_fw_reset(sc); 2399 /* Wait for firmware readiness. */ 2400 for (ntries = 0; ntries < 1000; ntries++) { 2401 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2402 break; 2403 urtwn_ms_delay(sc); 2404 } 2405 if (ntries == 1000) { 2406 device_printf(sc->sc_dev, 2407 "timeout waiting for firmware readiness\n"); 2408 error = ETIMEDOUT; 2409 goto fail; 2410 } 2411fail: 2412 firmware_put(fw, FIRMWARE_UNLOAD); 2413 return (error); 2414} 2415 2416static __inline int 2417urtwn_dma_init(struct urtwn_softc *sc) 2418{ 2419 2420 return sc->sc_dma_init(sc); 2421} 2422 2423static int 2424urtwn_r92c_dma_init(struct urtwn_softc *sc) 2425{ 2426 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2427 uint32_t reg; 2428 int error; 2429 2430 /* Initialize LLT table. */ 2431 error = urtwn_llt_init(sc); 2432 if (error != 0) 2433 return (error); 2434 2435 /* Get Tx queues to USB endpoints mapping. */ 2436 hashq = hasnq = haslq = 0; 2437 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2438 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2439 if (MS(reg, R92C_USB_EP_HQ) != 0) 2440 hashq = 1; 2441 if (MS(reg, R92C_USB_EP_NQ) != 0) 2442 hasnq = 1; 2443 if (MS(reg, R92C_USB_EP_LQ) != 0) 2444 haslq = 1; 2445 nqueues = hashq + hasnq + haslq; 2446 if (nqueues == 0) 2447 return (EIO); 2448 /* Get the number of pages for each queue. */ 2449 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2450 /* The remaining pages are assigned to the high priority queue. */ 2451 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2452 2453 /* Set number of pages for normal priority queue. */ 2454 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2455 urtwn_write_4(sc, R92C_RQPN, 2456 /* Set number of pages for public queue. */ 2457 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2458 /* Set number of pages for high priority queue. */ 2459 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2460 /* Set number of pages for low priority queue. */ 2461 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2462 /* Load values. */ 2463 R92C_RQPN_LD); 2464 2465 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2466 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2467 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2468 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2469 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2470 2471 /* Set queue to USB pipe mapping. */ 2472 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2473 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2474 if (nqueues == 1) { 2475 if (hashq) 2476 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2477 else if (hasnq) 2478 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2479 else 2480 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2481 } else if (nqueues == 2) { 2482 /* All 2-endpoints configs have a high priority queue. */ 2483 if (!hashq) 2484 return (EIO); 2485 if (hasnq) 2486 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2487 else 2488 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2489 } else 2490 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2491 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2492 2493 /* Set Tx/Rx transfer page boundary. */ 2494 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2495 2496 /* Set Tx/Rx transfer page size. */ 2497 urtwn_write_1(sc, R92C_PBP, 2498 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2499 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2500 return (0); 2501} 2502 2503static int 2504urtwn_r88e_dma_init(struct urtwn_softc *sc) 2505{ 2506 struct usb_interface *iface; 2507 uint32_t reg; 2508 int nqueues; 2509 int error; 2510 2511 /* Initialize LLT table. */ 2512 error = urtwn_llt_init(sc); 2513 if (error != 0) 2514 return (error); 2515 2516 /* Get Tx queues to USB endpoints mapping. */ 2517 iface = usbd_get_iface(sc->sc_udev, 0); 2518 nqueues = iface->idesc->bNumEndpoints - 1; 2519 if (nqueues == 0) 2520 return (EIO); 2521 2522 /* Set number of pages for normal priority queue. */ 2523 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2524 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2525 2526 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2527 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2528 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2529 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2530 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2531 2532 /* Set queue to USB pipe mapping. */ 2533 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2534 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2535 if (nqueues == 1) 2536 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2537 else if (nqueues == 2) 2538 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2539 else 2540 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2541 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2542 2543 /* Set Tx/Rx transfer page boundary. */ 2544 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2545 2546 /* Set Tx/Rx transfer page size. */ 2547 urtwn_write_1(sc, R92C_PBP, 2548 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2549 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2550 2551 return (0); 2552} 2553 2554static void 2555urtwn_mac_init(struct urtwn_softc *sc) 2556{ 2557 int i; 2558 2559 /* Write MAC initialization values. */ 2560 if (sc->chip & URTWN_CHIP_88E) { 2561 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2562 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2563 rtl8188eu_mac[i].val); 2564 } 2565 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2566 } else { 2567 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2568 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2569 rtl8192cu_mac[i].val); 2570 } 2571} 2572 2573static void 2574urtwn_bb_init(struct urtwn_softc *sc) 2575{ 2576 const struct urtwn_bb_prog *prog; 2577 uint32_t reg; 2578 uint8_t crystalcap; 2579 int i; 2580 2581 /* Enable BB and RF. */ 2582 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2583 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2584 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2585 R92C_SYS_FUNC_EN_DIO_RF); 2586 2587 if (!(sc->chip & URTWN_CHIP_88E)) 2588 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2589 2590 urtwn_write_1(sc, R92C_RF_CTRL, 2591 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2592 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2593 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2594 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2595 2596 if (!(sc->chip & URTWN_CHIP_88E)) { 2597 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2598 urtwn_write_1(sc, 0x15, 0xe9); 2599 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2600 } 2601 2602 /* Select BB programming based on board type. */ 2603 if (sc->chip & URTWN_CHIP_88E) 2604 prog = &rtl8188eu_bb_prog; 2605 else if (!(sc->chip & URTWN_CHIP_92C)) { 2606 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2607 prog = &rtl8188ce_bb_prog; 2608 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2609 prog = &rtl8188ru_bb_prog; 2610 else 2611 prog = &rtl8188cu_bb_prog; 2612 } else { 2613 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2614 prog = &rtl8192ce_bb_prog; 2615 else 2616 prog = &rtl8192cu_bb_prog; 2617 } 2618 /* Write BB initialization values. */ 2619 for (i = 0; i < prog->count; i++) { 2620 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2621 urtwn_ms_delay(sc); 2622 } 2623 2624 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2625 /* 8192C 1T only configuration. */ 2626 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2627 reg = (reg & ~0x00000003) | 0x2; 2628 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2629 2630 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2631 reg = (reg & ~0x00300033) | 0x00200022; 2632 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2633 2634 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2635 reg = (reg & ~0xff000000) | 0x45 << 24; 2636 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2637 2638 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2639 reg = (reg & ~0x000000ff) | 0x23; 2640 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2641 2642 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2643 reg = (reg & ~0x00000030) | 1 << 4; 2644 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2645 2646 reg = urtwn_bb_read(sc, 0xe74); 2647 reg = (reg & ~0x0c000000) | 2 << 26; 2648 urtwn_bb_write(sc, 0xe74, reg); 2649 reg = urtwn_bb_read(sc, 0xe78); 2650 reg = (reg & ~0x0c000000) | 2 << 26; 2651 urtwn_bb_write(sc, 0xe78, reg); 2652 reg = urtwn_bb_read(sc, 0xe7c); 2653 reg = (reg & ~0x0c000000) | 2 << 26; 2654 urtwn_bb_write(sc, 0xe7c, reg); 2655 reg = urtwn_bb_read(sc, 0xe80); 2656 reg = (reg & ~0x0c000000) | 2 << 26; 2657 urtwn_bb_write(sc, 0xe80, reg); 2658 reg = urtwn_bb_read(sc, 0xe88); 2659 reg = (reg & ~0x0c000000) | 2 << 26; 2660 urtwn_bb_write(sc, 0xe88, reg); 2661 } 2662 2663 /* Write AGC values. */ 2664 for (i = 0; i < prog->agccount; i++) { 2665 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2666 prog->agcvals[i]); 2667 urtwn_ms_delay(sc); 2668 } 2669 2670 if (sc->chip & URTWN_CHIP_88E) { 2671 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2672 urtwn_ms_delay(sc); 2673 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2674 urtwn_ms_delay(sc); 2675 2676 crystalcap = sc->r88e_rom[0xb9]; 2677 if (crystalcap == 0xff) 2678 crystalcap = 0x20; 2679 crystalcap &= 0x3f; 2680 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2681 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2682 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2683 crystalcap | crystalcap << 6)); 2684 } else { 2685 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2686 R92C_HSSI_PARAM2_CCK_HIPWR) 2687 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2688 } 2689} 2690 2691static void 2692urtwn_rf_init(struct urtwn_softc *sc) 2693{ 2694 const struct urtwn_rf_prog *prog; 2695 uint32_t reg, type; 2696 int i, j, idx, off; 2697 2698 /* Select RF programming based on board type. */ 2699 if (sc->chip & URTWN_CHIP_88E) 2700 prog = rtl8188eu_rf_prog; 2701 else if (!(sc->chip & URTWN_CHIP_92C)) { 2702 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2703 prog = rtl8188ce_rf_prog; 2704 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2705 prog = rtl8188ru_rf_prog; 2706 else 2707 prog = rtl8188cu_rf_prog; 2708 } else 2709 prog = rtl8192ce_rf_prog; 2710 2711 for (i = 0; i < sc->nrxchains; i++) { 2712 /* Save RF_ENV control type. */ 2713 idx = i / 2; 2714 off = (i % 2) * 16; 2715 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2716 type = (reg >> off) & 0x10; 2717 2718 /* Set RF_ENV enable. */ 2719 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2720 reg |= 0x100000; 2721 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2722 urtwn_ms_delay(sc); 2723 /* Set RF_ENV output high. */ 2724 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2725 reg |= 0x10; 2726 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2727 urtwn_ms_delay(sc); 2728 /* Set address and data lengths of RF registers. */ 2729 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2730 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2731 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2732 urtwn_ms_delay(sc); 2733 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2734 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2735 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2736 urtwn_ms_delay(sc); 2737 2738 /* Write RF initialization values for this chain. */ 2739 for (j = 0; j < prog[i].count; j++) { 2740 if (prog[i].regs[j] >= 0xf9 && 2741 prog[i].regs[j] <= 0xfe) { 2742 /* 2743 * These are fake RF registers offsets that 2744 * indicate a delay is required. 2745 */ 2746 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2747 continue; 2748 } 2749 urtwn_rf_write(sc, i, prog[i].regs[j], 2750 prog[i].vals[j]); 2751 urtwn_ms_delay(sc); 2752 } 2753 2754 /* Restore RF_ENV control type. */ 2755 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2756 reg &= ~(0x10 << off) | (type << off); 2757 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2758 2759 /* Cache RF register CHNLBW. */ 2760 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2761 } 2762 2763 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2764 URTWN_CHIP_UMC_A_CUT) { 2765 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2766 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2767 } 2768} 2769 2770static void 2771urtwn_cam_init(struct urtwn_softc *sc) 2772{ 2773 /* Invalidate all CAM entries. */ 2774 urtwn_write_4(sc, R92C_CAMCMD, 2775 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2776} 2777 2778static void 2779urtwn_pa_bias_init(struct urtwn_softc *sc) 2780{ 2781 uint8_t reg; 2782 int i; 2783 2784 for (i = 0; i < sc->nrxchains; i++) { 2785 if (sc->pa_setting & (1 << i)) 2786 continue; 2787 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2788 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2789 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2790 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2791 } 2792 if (!(sc->pa_setting & 0x10)) { 2793 reg = urtwn_read_1(sc, 0x16); 2794 reg = (reg & ~0xf0) | 0x90; 2795 urtwn_write_1(sc, 0x16, reg); 2796 } 2797} 2798 2799static void 2800urtwn_rxfilter_init(struct urtwn_softc *sc) 2801{ 2802 /* Initialize Rx filter. */ 2803 /* TODO: use better filter for monitor mode. */ 2804 urtwn_write_4(sc, R92C_RCR, 2805 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2806 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2807 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2808 /* Accept all multicast frames. */ 2809 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2810 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2811 /* Accept all management frames. */ 2812 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2813 /* Reject all control frames. */ 2814 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2815 /* Accept all data frames. */ 2816 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2817} 2818 2819static void 2820urtwn_edca_init(struct urtwn_softc *sc) 2821{ 2822 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2823 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2824 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2825 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2826 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2827 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2828 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2829 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2830} 2831 2832static void 2833urtwn_write_txpower(struct urtwn_softc *sc, int chain, 2834 uint16_t power[URTWN_RIDX_COUNT]) 2835{ 2836 uint32_t reg; 2837 2838 /* Write per-CCK rate Tx power. */ 2839 if (chain == 0) { 2840 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2841 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2842 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2843 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2844 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2845 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2846 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2847 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2848 } else { 2849 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2850 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2851 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2852 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2853 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2854 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2855 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2856 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2857 } 2858 /* Write per-OFDM rate Tx power. */ 2859 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2860 SM(R92C_TXAGC_RATE06, power[ 4]) | 2861 SM(R92C_TXAGC_RATE09, power[ 5]) | 2862 SM(R92C_TXAGC_RATE12, power[ 6]) | 2863 SM(R92C_TXAGC_RATE18, power[ 7])); 2864 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2865 SM(R92C_TXAGC_RATE24, power[ 8]) | 2866 SM(R92C_TXAGC_RATE36, power[ 9]) | 2867 SM(R92C_TXAGC_RATE48, power[10]) | 2868 SM(R92C_TXAGC_RATE54, power[11])); 2869 /* Write per-MCS Tx power. */ 2870 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2871 SM(R92C_TXAGC_MCS00, power[12]) | 2872 SM(R92C_TXAGC_MCS01, power[13]) | 2873 SM(R92C_TXAGC_MCS02, power[14]) | 2874 SM(R92C_TXAGC_MCS03, power[15])); 2875 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2876 SM(R92C_TXAGC_MCS04, power[16]) | 2877 SM(R92C_TXAGC_MCS05, power[17]) | 2878 SM(R92C_TXAGC_MCS06, power[18]) | 2879 SM(R92C_TXAGC_MCS07, power[19])); 2880 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2881 SM(R92C_TXAGC_MCS08, power[20]) | 2882 SM(R92C_TXAGC_MCS09, power[21]) | 2883 SM(R92C_TXAGC_MCS10, power[22]) | 2884 SM(R92C_TXAGC_MCS11, power[23])); 2885 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2886 SM(R92C_TXAGC_MCS12, power[24]) | 2887 SM(R92C_TXAGC_MCS13, power[25]) | 2888 SM(R92C_TXAGC_MCS14, power[26]) | 2889 SM(R92C_TXAGC_MCS15, power[27])); 2890} 2891 2892static void 2893urtwn_get_txpower(struct urtwn_softc *sc, int chain, 2894 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2895 uint16_t power[URTWN_RIDX_COUNT]) 2896{ 2897 struct ieee80211com *ic = &sc->sc_ic; 2898 struct r92c_rom *rom = &sc->rom; 2899 uint16_t cckpow, ofdmpow, htpow, diff, max; 2900 const struct urtwn_txpwr *base; 2901 int ridx, chan, group; 2902 2903 /* Determine channel group. */ 2904 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2905 if (chan <= 3) 2906 group = 0; 2907 else if (chan <= 9) 2908 group = 1; 2909 else 2910 group = 2; 2911 2912 /* Get original Tx power based on board type and RF chain. */ 2913 if (!(sc->chip & URTWN_CHIP_92C)) { 2914 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2915 base = &rtl8188ru_txagc[chain]; 2916 else 2917 base = &rtl8192cu_txagc[chain]; 2918 } else 2919 base = &rtl8192cu_txagc[chain]; 2920 2921 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2922 if (sc->regulatory == 0) { 2923 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 2924 power[ridx] = base->pwr[0][ridx]; 2925 } 2926 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 2927 if (sc->regulatory == 3) { 2928 power[ridx] = base->pwr[0][ridx]; 2929 /* Apply vendor limits. */ 2930 if (extc != NULL) 2931 max = rom->ht40_max_pwr[group]; 2932 else 2933 max = rom->ht20_max_pwr[group]; 2934 max = (max >> (chain * 4)) & 0xf; 2935 if (power[ridx] > max) 2936 power[ridx] = max; 2937 } else if (sc->regulatory == 1) { 2938 if (extc == NULL) 2939 power[ridx] = base->pwr[group][ridx]; 2940 } else if (sc->regulatory != 2) 2941 power[ridx] = base->pwr[0][ridx]; 2942 } 2943 2944 /* Compute per-CCK rate Tx power. */ 2945 cckpow = rom->cck_tx_pwr[chain][group]; 2946 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 2947 power[ridx] += cckpow; 2948 if (power[ridx] > R92C_MAX_TX_PWR) 2949 power[ridx] = R92C_MAX_TX_PWR; 2950 } 2951 2952 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2953 if (sc->ntxchains > 1) { 2954 /* Apply reduction for 2 spatial streams. */ 2955 diff = rom->ht40_2s_tx_pwr_diff[group]; 2956 diff = (diff >> (chain * 4)) & 0xf; 2957 htpow = (htpow > diff) ? htpow - diff : 0; 2958 } 2959 2960 /* Compute per-OFDM rate Tx power. */ 2961 diff = rom->ofdm_tx_pwr_diff[group]; 2962 diff = (diff >> (chain * 4)) & 0xf; 2963 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2964 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 2965 power[ridx] += ofdmpow; 2966 if (power[ridx] > R92C_MAX_TX_PWR) 2967 power[ridx] = R92C_MAX_TX_PWR; 2968 } 2969 2970 /* Compute per-MCS Tx power. */ 2971 if (extc == NULL) { 2972 diff = rom->ht20_tx_pwr_diff[group]; 2973 diff = (diff >> (chain * 4)) & 0xf; 2974 htpow += diff; /* HT40->HT20 correction. */ 2975 } 2976 for (ridx = 12; ridx <= 27; ridx++) { 2977 power[ridx] += htpow; 2978 if (power[ridx] > R92C_MAX_TX_PWR) 2979 power[ridx] = R92C_MAX_TX_PWR; 2980 } 2981#ifdef URTWN_DEBUG 2982 if (urtwn_debug >= 4) { 2983 /* Dump per-rate Tx power values. */ 2984 printf("Tx power for chain %d:\n", chain); 2985 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 2986 printf("Rate %d = %u\n", ridx, power[ridx]); 2987 } 2988#endif 2989} 2990 2991static void 2992urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 2993 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2994 uint16_t power[URTWN_RIDX_COUNT]) 2995{ 2996 struct ieee80211com *ic = &sc->sc_ic; 2997 uint16_t cckpow, ofdmpow, bw20pow, htpow; 2998 const struct urtwn_r88e_txpwr *base; 2999 int ridx, chan, group; 3000 3001 /* Determine channel group. */ 3002 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3003 if (chan <= 2) 3004 group = 0; 3005 else if (chan <= 5) 3006 group = 1; 3007 else if (chan <= 8) 3008 group = 2; 3009 else if (chan <= 11) 3010 group = 3; 3011 else if (chan <= 13) 3012 group = 4; 3013 else 3014 group = 5; 3015 3016 /* Get original Tx power based on board type and RF chain. */ 3017 base = &rtl8188eu_txagc[chain]; 3018 3019 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3020 if (sc->regulatory == 0) { 3021 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3022 power[ridx] = base->pwr[0][ridx]; 3023 } 3024 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3025 if (sc->regulatory == 3) 3026 power[ridx] = base->pwr[0][ridx]; 3027 else if (sc->regulatory == 1) { 3028 if (extc == NULL) 3029 power[ridx] = base->pwr[group][ridx]; 3030 } else if (sc->regulatory != 2) 3031 power[ridx] = base->pwr[0][ridx]; 3032 } 3033 3034 /* Compute per-CCK rate Tx power. */ 3035 cckpow = sc->cck_tx_pwr[group]; 3036 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3037 power[ridx] += cckpow; 3038 if (power[ridx] > R92C_MAX_TX_PWR) 3039 power[ridx] = R92C_MAX_TX_PWR; 3040 } 3041 3042 htpow = sc->ht40_tx_pwr[group]; 3043 3044 /* Compute per-OFDM rate Tx power. */ 3045 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3046 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3047 power[ridx] += ofdmpow; 3048 if (power[ridx] > R92C_MAX_TX_PWR) 3049 power[ridx] = R92C_MAX_TX_PWR; 3050 } 3051 3052 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3053 for (ridx = 12; ridx <= 27; ridx++) { 3054 power[ridx] += bw20pow; 3055 if (power[ridx] > R92C_MAX_TX_PWR) 3056 power[ridx] = R92C_MAX_TX_PWR; 3057 } 3058} 3059 3060static void 3061urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3062 struct ieee80211_channel *extc) 3063{ 3064 uint16_t power[URTWN_RIDX_COUNT]; 3065 int i; 3066 3067 for (i = 0; i < sc->ntxchains; i++) { 3068 /* Compute per-rate Tx power values. */ 3069 if (sc->chip & URTWN_CHIP_88E) 3070 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3071 else 3072 urtwn_get_txpower(sc, i, c, extc, power); 3073 /* Write per-rate Tx power values to hardware. */ 3074 urtwn_write_txpower(sc, i, power); 3075 } 3076} 3077 3078static void 3079urtwn_scan_start(struct ieee80211com *ic) 3080{ 3081 /* XXX do nothing? */ 3082} 3083 3084static void 3085urtwn_scan_end(struct ieee80211com *ic) 3086{ 3087 /* XXX do nothing? */ 3088} 3089 3090static void 3091urtwn_set_channel(struct ieee80211com *ic) 3092{ 3093 struct urtwn_softc *sc = ic->ic_softc; 3094 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3095 3096 URTWN_LOCK(sc); 3097 if (vap->iv_state == IEEE80211_S_SCAN) { 3098 /* Make link LED blink during scan. */ 3099 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3100 } 3101 urtwn_set_chan(sc, ic->ic_curchan, NULL); 3102 URTWN_UNLOCK(sc); 3103} 3104 3105static void 3106urtwn_update_mcast(struct ieee80211com *ic) 3107{ 3108 /* XXX do nothing? */ 3109} 3110 3111static void 3112urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3113 struct ieee80211_channel *extc) 3114{ 3115 struct ieee80211com *ic = &sc->sc_ic; 3116 uint32_t reg; 3117 u_int chan; 3118 int i; 3119 3120 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3121 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3122 device_printf(sc->sc_dev, 3123 "%s: invalid channel %x\n", __func__, chan); 3124 return; 3125 } 3126 3127 /* Set Tx power for this new channel. */ 3128 urtwn_set_txpower(sc, c, extc); 3129 3130 for (i = 0; i < sc->nrxchains; i++) { 3131 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3132 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3133 } 3134#ifndef IEEE80211_NO_HT 3135 if (extc != NULL) { 3136 /* Is secondary channel below or above primary? */ 3137 int prichlo = c->ic_freq < extc->ic_freq; 3138 3139 urtwn_write_1(sc, R92C_BWOPMODE, 3140 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3141 3142 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3143 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3144 urtwn_write_1(sc, R92C_RRSR + 2, reg); 3145 3146 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3147 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3148 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3149 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3150 3151 /* Set CCK side band. */ 3152 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3153 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3154 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3155 3156 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3157 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3158 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3159 3160 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3161 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3162 ~R92C_FPGA0_ANAPARAM2_CBW20); 3163 3164 reg = urtwn_bb_read(sc, 0x818); 3165 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3166 urtwn_bb_write(sc, 0x818, reg); 3167 3168 /* Select 40MHz bandwidth. */ 3169 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3170 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3171 } else 3172#endif 3173 { 3174 urtwn_write_1(sc, R92C_BWOPMODE, 3175 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3176 3177 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3178 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3179 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3180 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3181 3182 if (!(sc->chip & URTWN_CHIP_88E)) { 3183 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3184 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3185 R92C_FPGA0_ANAPARAM2_CBW20); 3186 } 3187 3188 /* Select 20MHz bandwidth. */ 3189 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3190 (sc->rf_chnlbw[0] & ~0xfff) | chan | 3191 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3192 R92C_RF_CHNLBW_BW20)); 3193 } 3194} 3195 3196static void 3197urtwn_iq_calib(struct urtwn_softc *sc) 3198{ 3199 /* TODO */ 3200} 3201 3202static void 3203urtwn_lc_calib(struct urtwn_softc *sc) 3204{ 3205 uint32_t rf_ac[2]; 3206 uint8_t txmode; 3207 int i; 3208 3209 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3210 if ((txmode & 0x70) != 0) { 3211 /* Disable all continuous Tx. */ 3212 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3213 3214 /* Set RF mode to standby mode. */ 3215 for (i = 0; i < sc->nrxchains; i++) { 3216 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3217 urtwn_rf_write(sc, i, R92C_RF_AC, 3218 RW(rf_ac[i], R92C_RF_AC_MODE, 3219 R92C_RF_AC_MODE_STANDBY)); 3220 } 3221 } else { 3222 /* Block all Tx queues. */ 3223 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3224 } 3225 /* Start calibration. */ 3226 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3227 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3228 3229 /* Give calibration the time to complete. */ 3230 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3231 3232 /* Restore configuration. */ 3233 if ((txmode & 0x70) != 0) { 3234 /* Restore Tx mode. */ 3235 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3236 /* Restore RF mode. */ 3237 for (i = 0; i < sc->nrxchains; i++) 3238 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3239 } else { 3240 /* Unblock all Tx queues. */ 3241 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3242 } 3243} 3244 3245static void 3246urtwn_init(struct urtwn_softc *sc) 3247{ 3248 struct ieee80211com *ic = &sc->sc_ic; 3249 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3250 uint8_t macaddr[IEEE80211_ADDR_LEN]; 3251 uint32_t reg; 3252 int error; 3253 3254 URTWN_ASSERT_LOCKED(sc); 3255 3256 if (sc->sc_flags & URTWN_RUNNING) 3257 urtwn_stop(sc); 3258 3259 /* Init firmware commands ring. */ 3260 sc->fwcur = 0; 3261 3262 /* Allocate Tx/Rx buffers. */ 3263 error = urtwn_alloc_rx_list(sc); 3264 if (error != 0) 3265 goto fail; 3266 3267 error = urtwn_alloc_tx_list(sc); 3268 if (error != 0) 3269 goto fail; 3270 3271 /* Power on adapter. */ 3272 error = urtwn_power_on(sc); 3273 if (error != 0) 3274 goto fail; 3275 3276 /* Initialize DMA. */ 3277 error = urtwn_dma_init(sc); 3278 if (error != 0) 3279 goto fail; 3280 3281 /* Set info size in Rx descriptors (in 64-bit words). */ 3282 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3283 3284 /* Init interrupts. */ 3285 if (sc->chip & URTWN_CHIP_88E) { 3286 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3287 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3288 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3289 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3290 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3291 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3292 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3293 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3294 } else { 3295 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3296 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3297 } 3298 3299 /* Set MAC address. */ 3300 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3301 urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3302 3303 /* Set initial network type. */ 3304 urtwn_set_mode(sc, R92C_MSR_INFRA); 3305 3306 urtwn_rxfilter_init(sc); 3307 3308 /* Set response rate. */ 3309 reg = urtwn_read_4(sc, R92C_RRSR); 3310 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3311 urtwn_write_4(sc, R92C_RRSR, reg); 3312 3313 /* Set short/long retry limits. */ 3314 urtwn_write_2(sc, R92C_RL, 3315 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3316 3317 /* Initialize EDCA parameters. */ 3318 urtwn_edca_init(sc); 3319 3320 /* Setup rate fallback. */ 3321 if (!(sc->chip & URTWN_CHIP_88E)) { 3322 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3323 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3324 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3325 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3326 } 3327 3328 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3329 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3330 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3331 /* Set ACK timeout. */ 3332 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3333 3334 /* Setup USB aggregation. */ 3335 reg = urtwn_read_4(sc, R92C_TDECTRL); 3336 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3337 urtwn_write_4(sc, R92C_TDECTRL, reg); 3338 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3339 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3340 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3341 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3342 if (sc->chip & URTWN_CHIP_88E) 3343 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3344 else { 3345 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3346 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3347 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3348 R92C_USB_SPECIAL_OPTION_AGG_EN); 3349 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3350 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3351 } 3352 3353 /* Initialize beacon parameters. */ 3354 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3355 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3356 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3357 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3358 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3359 3360 if (!(sc->chip & URTWN_CHIP_88E)) { 3361 /* Setup AMPDU aggregation. */ 3362 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3363 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3364 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3365 3366 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3367 } 3368 3369 /* Load 8051 microcode. */ 3370 error = urtwn_load_firmware(sc); 3371 if (error != 0) 3372 goto fail; 3373 3374 /* Initialize MAC/BB/RF blocks. */ 3375 urtwn_mac_init(sc); 3376 urtwn_bb_init(sc); 3377 urtwn_rf_init(sc); 3378 3379 if (sc->chip & URTWN_CHIP_88E) { 3380 urtwn_write_2(sc, R92C_CR, 3381 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3382 R92C_CR_MACRXEN); 3383 } 3384 3385 /* Turn CCK and OFDM blocks on. */ 3386 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3387 reg |= R92C_RFMOD_CCK_EN; 3388 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3389 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3390 reg |= R92C_RFMOD_OFDM_EN; 3391 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3392 3393 /* Clear per-station keys table. */ 3394 urtwn_cam_init(sc); 3395 3396 /* Enable hardware sequence numbering. */ 3397 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3398 3399 /* Perform LO and IQ calibrations. */ 3400 urtwn_iq_calib(sc); 3401 /* Perform LC calibration. */ 3402 urtwn_lc_calib(sc); 3403 3404 /* Fix USB interference issue. */ 3405 if (!(sc->chip & URTWN_CHIP_88E)) { 3406 urtwn_write_1(sc, 0xfe40, 0xe0); 3407 urtwn_write_1(sc, 0xfe41, 0x8d); 3408 urtwn_write_1(sc, 0xfe42, 0x80); 3409 3410 urtwn_pa_bias_init(sc); 3411 } 3412 3413 /* Initialize GPIO setting. */ 3414 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3415 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3416 3417 /* Fix for lower temperature. */ 3418 if (!(sc->chip & URTWN_CHIP_88E)) 3419 urtwn_write_1(sc, 0x15, 0xe9); 3420 3421 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3422 3423 sc->sc_flags |= URTWN_RUNNING; 3424 3425 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3426fail: 3427 return; 3428} 3429 3430static void 3431urtwn_stop(struct urtwn_softc *sc) 3432{ 3433 3434 URTWN_ASSERT_LOCKED(sc); 3435 sc->sc_flags &= ~URTWN_RUNNING; 3436 callout_stop(&sc->sc_watchdog_ch); 3437 urtwn_abort_xfers(sc); 3438 3439 urtwn_drain_mbufq(sc); 3440} 3441 3442static void 3443urtwn_abort_xfers(struct urtwn_softc *sc) 3444{ 3445 int i; 3446 3447 URTWN_ASSERT_LOCKED(sc); 3448 3449 /* abort any pending transfers */ 3450 for (i = 0; i < URTWN_N_TRANSFER; i++) 3451 usbd_transfer_stop(sc->sc_xfer[i]); 3452} 3453 3454static int 3455urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3456 const struct ieee80211_bpf_params *params) 3457{ 3458 struct ieee80211com *ic = ni->ni_ic; 3459 struct urtwn_softc *sc = ic->ic_softc; 3460 struct urtwn_data *bf; 3461 3462 /* prevent management frames from being sent if we're not ready */ 3463 if (!(sc->sc_flags & URTWN_RUNNING)) { 3464 m_freem(m); 3465 return (ENETDOWN); 3466 } 3467 URTWN_LOCK(sc); 3468 bf = urtwn_getbuf(sc); 3469 if (bf == NULL) { 3470 m_freem(m); 3471 URTWN_UNLOCK(sc); 3472 return (ENOBUFS); 3473 } 3474 3475 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3476 m_freem(m); 3477 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3478 URTWN_UNLOCK(sc); 3479 return (EIO); 3480 } 3481 sc->sc_txtimer = 5; 3482 URTWN_UNLOCK(sc); 3483 3484 return (0); 3485} 3486 3487static void 3488urtwn_ms_delay(struct urtwn_softc *sc) 3489{ 3490 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3491} 3492 3493static device_method_t urtwn_methods[] = { 3494 /* Device interface */ 3495 DEVMETHOD(device_probe, urtwn_match), 3496 DEVMETHOD(device_attach, urtwn_attach), 3497 DEVMETHOD(device_detach, urtwn_detach), 3498 3499 DEVMETHOD_END 3500}; 3501 3502static driver_t urtwn_driver = { 3503 "urtwn", 3504 urtwn_methods, 3505 sizeof(struct urtwn_softc) 3506}; 3507 3508static devclass_t urtwn_devclass; 3509 3510DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3511MODULE_DEPEND(urtwn, usb, 1, 1, 1); 3512MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3513MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3514MODULE_VERSION(urtwn, 1); 3515