if_urtwn.c revision 289811
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 289811 2015-10-23 08:26:26Z avos $"); 22 23/* 24 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25 */ 26 27#include "opt_wlan.h" 28 29#include <sys/param.h> 30#include <sys/sockio.h> 31#include <sys/sysctl.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/mbuf.h> 35#include <sys/kernel.h> 36#include <sys/socket.h> 37#include <sys/systm.h> 38#include <sys/malloc.h> 39#include <sys/module.h> 40#include <sys/bus.h> 41#include <sys/endian.h> 42#include <sys/linker.h> 43#include <sys/firmware.h> 44#include <sys/kdb.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48#include <sys/rman.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_var.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/in_var.h> 62#include <netinet/if_ether.h> 63#include <netinet/ip.h> 64 65#include <net80211/ieee80211_var.h> 66#include <net80211/ieee80211_input.h> 67#include <net80211/ieee80211_regdomain.h> 68#include <net80211/ieee80211_radiotap.h> 69#include <net80211/ieee80211_ratectl.h> 70 71#include <dev/usb/usb.h> 72#include <dev/usb/usbdi.h> 73#include "usbdevs.h" 74 75#define USB_DEBUG_VAR urtwn_debug 76#include <dev/usb/usb_debug.h> 77 78#include <dev/usb/wlan/if_urtwnreg.h> 79#include <dev/usb/wlan/if_urtwnvar.h> 80 81#ifdef USB_DEBUG 82static int urtwn_debug = 0; 83 84SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 85SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 86 "Debug level"); 87#endif 88 89#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 90 91/* various supported device vendors/products */ 92static const STRUCT_USB_HOST_ID urtwn_devs[] = { 93#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 94#define URTWN_RTL8188E_DEV(v,p) \ 95 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 96#define URTWN_RTL8188E 1 97 URTWN_DEV(ABOCOM, RTL8188CU_1), 98 URTWN_DEV(ABOCOM, RTL8188CU_2), 99 URTWN_DEV(ABOCOM, RTL8192CU), 100 URTWN_DEV(ASUS, RTL8192CU), 101 URTWN_DEV(ASUS, USBN10NANO), 102 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 103 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 104 URTWN_DEV(AZUREWAVE, RTL8188CU), 105 URTWN_DEV(BELKIN, F7D2102), 106 URTWN_DEV(BELKIN, RTL8188CU), 107 URTWN_DEV(BELKIN, RTL8192CU), 108 URTWN_DEV(CHICONY, RTL8188CUS_1), 109 URTWN_DEV(CHICONY, RTL8188CUS_2), 110 URTWN_DEV(CHICONY, RTL8188CUS_3), 111 URTWN_DEV(CHICONY, RTL8188CUS_4), 112 URTWN_DEV(CHICONY, RTL8188CUS_5), 113 URTWN_DEV(COREGA, RTL8192CU), 114 URTWN_DEV(DLINK, RTL8188CU), 115 URTWN_DEV(DLINK, RTL8192CU_1), 116 URTWN_DEV(DLINK, RTL8192CU_2), 117 URTWN_DEV(DLINK, RTL8192CU_3), 118 URTWN_DEV(DLINK, DWA131B), 119 URTWN_DEV(EDIMAX, EW7811UN), 120 URTWN_DEV(EDIMAX, RTL8192CU), 121 URTWN_DEV(FEIXUN, RTL8188CU), 122 URTWN_DEV(FEIXUN, RTL8192CU), 123 URTWN_DEV(GUILLEMOT, HWNUP150), 124 URTWN_DEV(HAWKING, RTL8192CU), 125 URTWN_DEV(HP3, RTL8188CU), 126 URTWN_DEV(NETGEAR, WNA1000M), 127 URTWN_DEV(NETGEAR, RTL8192CU), 128 URTWN_DEV(NETGEAR4, RTL8188CU), 129 URTWN_DEV(NOVATECH, RTL8188CU), 130 URTWN_DEV(PLANEX2, RTL8188CU_1), 131 URTWN_DEV(PLANEX2, RTL8188CU_2), 132 URTWN_DEV(PLANEX2, RTL8188CU_3), 133 URTWN_DEV(PLANEX2, RTL8188CU_4), 134 URTWN_DEV(PLANEX2, RTL8188CUS), 135 URTWN_DEV(PLANEX2, RTL8192CU), 136 URTWN_DEV(REALTEK, RTL8188CE_0), 137 URTWN_DEV(REALTEK, RTL8188CE_1), 138 URTWN_DEV(REALTEK, RTL8188CTV), 139 URTWN_DEV(REALTEK, RTL8188CU_0), 140 URTWN_DEV(REALTEK, RTL8188CU_1), 141 URTWN_DEV(REALTEK, RTL8188CU_2), 142 URTWN_DEV(REALTEK, RTL8188CU_3), 143 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 144 URTWN_DEV(REALTEK, RTL8188CUS), 145 URTWN_DEV(REALTEK, RTL8188RU_1), 146 URTWN_DEV(REALTEK, RTL8188RU_2), 147 URTWN_DEV(REALTEK, RTL8188RU_3), 148 URTWN_DEV(REALTEK, RTL8191CU), 149 URTWN_DEV(REALTEK, RTL8192CE), 150 URTWN_DEV(REALTEK, RTL8192CU), 151 URTWN_DEV(SITECOMEU, RTL8188CU_1), 152 URTWN_DEV(SITECOMEU, RTL8188CU_2), 153 URTWN_DEV(SITECOMEU, RTL8192CU), 154 URTWN_DEV(TRENDNET, RTL8188CU), 155 URTWN_DEV(TRENDNET, RTL8192CU), 156 URTWN_DEV(ZYXEL, RTL8192CU), 157 /* URTWN_RTL8188E */ 158 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 159 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 160 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 161 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 162 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 163#undef URTWN_RTL8188E_DEV 164#undef URTWN_DEV 165}; 166 167static device_probe_t urtwn_match; 168static device_attach_t urtwn_attach; 169static device_detach_t urtwn_detach; 170 171static usb_callback_t urtwn_bulk_tx_callback; 172static usb_callback_t urtwn_bulk_rx_callback; 173 174static void urtwn_drain_mbufq(struct urtwn_softc *sc); 175static usb_error_t urtwn_do_request(struct urtwn_softc *, 176 struct usb_device_request *, void *); 177static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 178 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 179 const uint8_t [IEEE80211_ADDR_LEN], 180 const uint8_t [IEEE80211_ADDR_LEN]); 181static void urtwn_vap_delete(struct ieee80211vap *); 182static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 183 int *); 184static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 185 int *, int8_t *); 186static void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 187static int urtwn_alloc_list(struct urtwn_softc *, 188 struct urtwn_data[], int, int); 189static int urtwn_alloc_rx_list(struct urtwn_softc *); 190static int urtwn_alloc_tx_list(struct urtwn_softc *); 191static void urtwn_free_list(struct urtwn_softc *, 192 struct urtwn_data data[], int); 193static void urtwn_free_rx_list(struct urtwn_softc *); 194static void urtwn_free_tx_list(struct urtwn_softc *); 195static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 196static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 197static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 198 uint8_t *, int); 199static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 200static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 201static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 202static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 203 uint8_t *, int); 204static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 205static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 206static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 207static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 208 const void *, int); 209static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 210 uint8_t, uint32_t); 211static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 212 uint8_t, uint32_t); 213static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 214static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 215 uint32_t); 216static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 217static void urtwn_efuse_read(struct urtwn_softc *); 218static void urtwn_efuse_switch_power(struct urtwn_softc *); 219static int urtwn_read_chipid(struct urtwn_softc *); 220static void urtwn_read_rom(struct urtwn_softc *); 221static void urtwn_r88e_read_rom(struct urtwn_softc *); 222static int urtwn_ra_init(struct urtwn_softc *); 223static void urtwn_tsf_sync_enable(struct urtwn_softc *); 224static void urtwn_set_led(struct urtwn_softc *, int, int); 225static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 226static int urtwn_newstate(struct ieee80211vap *, 227 enum ieee80211_state, int); 228static void urtwn_watchdog(void *); 229static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 230static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 231static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 232static int urtwn_tx_start(struct urtwn_softc *, 233 struct ieee80211_node *, struct mbuf *, 234 struct urtwn_data *); 235static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 236static void urtwn_start(struct urtwn_softc *); 237static void urtwn_parent(struct ieee80211com *); 238static int urtwn_r92c_power_on(struct urtwn_softc *); 239static int urtwn_r88e_power_on(struct urtwn_softc *); 240static int urtwn_llt_init(struct urtwn_softc *); 241static void urtwn_fw_reset(struct urtwn_softc *); 242static void urtwn_r88e_fw_reset(struct urtwn_softc *); 243static int urtwn_fw_loadpage(struct urtwn_softc *, int, 244 const uint8_t *, int); 245static int urtwn_load_firmware(struct urtwn_softc *); 246static int urtwn_r92c_dma_init(struct urtwn_softc *); 247static int urtwn_r88e_dma_init(struct urtwn_softc *); 248static void urtwn_mac_init(struct urtwn_softc *); 249static void urtwn_bb_init(struct urtwn_softc *); 250static void urtwn_rf_init(struct urtwn_softc *); 251static void urtwn_cam_init(struct urtwn_softc *); 252static void urtwn_pa_bias_init(struct urtwn_softc *); 253static void urtwn_rxfilter_init(struct urtwn_softc *); 254static void urtwn_edca_init(struct urtwn_softc *); 255static void urtwn_write_txpower(struct urtwn_softc *, int, 256 uint16_t[]); 257static void urtwn_get_txpower(struct urtwn_softc *, int, 258 struct ieee80211_channel *, 259 struct ieee80211_channel *, uint16_t[]); 260static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 261 struct ieee80211_channel *, 262 struct ieee80211_channel *, uint16_t[]); 263static void urtwn_set_txpower(struct urtwn_softc *, 264 struct ieee80211_channel *, 265 struct ieee80211_channel *); 266static void urtwn_scan_start(struct ieee80211com *); 267static void urtwn_scan_end(struct ieee80211com *); 268static void urtwn_set_channel(struct ieee80211com *); 269static void urtwn_update_mcast(struct ieee80211com *); 270static void urtwn_set_chan(struct urtwn_softc *, 271 struct ieee80211_channel *, 272 struct ieee80211_channel *); 273static void urtwn_iq_calib(struct urtwn_softc *); 274static void urtwn_lc_calib(struct urtwn_softc *); 275static void urtwn_init(struct urtwn_softc *); 276static void urtwn_stop(struct urtwn_softc *); 277static void urtwn_abort_xfers(struct urtwn_softc *); 278static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 279 const struct ieee80211_bpf_params *); 280static void urtwn_ms_delay(struct urtwn_softc *); 281 282/* Aliases. */ 283#define urtwn_bb_write urtwn_write_4 284#define urtwn_bb_read urtwn_read_4 285 286static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 287 [URTWN_BULK_RX] = { 288 .type = UE_BULK, 289 .endpoint = UE_ADDR_ANY, 290 .direction = UE_DIR_IN, 291 .bufsize = URTWN_RXBUFSZ, 292 .flags = { 293 .pipe_bof = 1, 294 .short_xfer_ok = 1 295 }, 296 .callback = urtwn_bulk_rx_callback, 297 }, 298 [URTWN_BULK_TX_BE] = { 299 .type = UE_BULK, 300 .endpoint = 0x03, 301 .direction = UE_DIR_OUT, 302 .bufsize = URTWN_TXBUFSZ, 303 .flags = { 304 .ext_buffer = 1, 305 .pipe_bof = 1, 306 .force_short_xfer = 1 307 }, 308 .callback = urtwn_bulk_tx_callback, 309 .timeout = URTWN_TX_TIMEOUT, /* ms */ 310 }, 311 [URTWN_BULK_TX_BK] = { 312 .type = UE_BULK, 313 .endpoint = 0x03, 314 .direction = UE_DIR_OUT, 315 .bufsize = URTWN_TXBUFSZ, 316 .flags = { 317 .ext_buffer = 1, 318 .pipe_bof = 1, 319 .force_short_xfer = 1, 320 }, 321 .callback = urtwn_bulk_tx_callback, 322 .timeout = URTWN_TX_TIMEOUT, /* ms */ 323 }, 324 [URTWN_BULK_TX_VI] = { 325 .type = UE_BULK, 326 .endpoint = 0x02, 327 .direction = UE_DIR_OUT, 328 .bufsize = URTWN_TXBUFSZ, 329 .flags = { 330 .ext_buffer = 1, 331 .pipe_bof = 1, 332 .force_short_xfer = 1 333 }, 334 .callback = urtwn_bulk_tx_callback, 335 .timeout = URTWN_TX_TIMEOUT, /* ms */ 336 }, 337 [URTWN_BULK_TX_VO] = { 338 .type = UE_BULK, 339 .endpoint = 0x02, 340 .direction = UE_DIR_OUT, 341 .bufsize = URTWN_TXBUFSZ, 342 .flags = { 343 .ext_buffer = 1, 344 .pipe_bof = 1, 345 .force_short_xfer = 1 346 }, 347 .callback = urtwn_bulk_tx_callback, 348 .timeout = URTWN_TX_TIMEOUT, /* ms */ 349 }, 350}; 351 352static int 353urtwn_match(device_t self) 354{ 355 struct usb_attach_arg *uaa = device_get_ivars(self); 356 357 if (uaa->usb_mode != USB_MODE_HOST) 358 return (ENXIO); 359 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 360 return (ENXIO); 361 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 362 return (ENXIO); 363 364 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 365} 366 367static int 368urtwn_attach(device_t self) 369{ 370 struct usb_attach_arg *uaa = device_get_ivars(self); 371 struct urtwn_softc *sc = device_get_softc(self); 372 struct ieee80211com *ic = &sc->sc_ic; 373 uint8_t iface_index, bands; 374 int error; 375 376 device_set_usb_desc(self); 377 sc->sc_udev = uaa->device; 378 sc->sc_dev = self; 379 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 380 sc->chip |= URTWN_CHIP_88E; 381 382 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 383 MTX_NETWORK_LOCK, MTX_DEF); 384 callout_init(&sc->sc_watchdog_ch, 0); 385 mbufq_init(&sc->sc_snd, ifqmaxlen); 386 387 iface_index = URTWN_IFACE_INDEX; 388 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 389 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 390 if (error) { 391 device_printf(self, "could not allocate USB transfers, " 392 "err=%s\n", usbd_errstr(error)); 393 goto detach; 394 } 395 396 URTWN_LOCK(sc); 397 398 error = urtwn_read_chipid(sc); 399 if (error) { 400 device_printf(sc->sc_dev, "unsupported test chip\n"); 401 URTWN_UNLOCK(sc); 402 goto detach; 403 } 404 405 /* Determine number of Tx/Rx chains. */ 406 if (sc->chip & URTWN_CHIP_92C) { 407 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 408 sc->nrxchains = 2; 409 } else { 410 sc->ntxchains = 1; 411 sc->nrxchains = 1; 412 } 413 414 if (sc->chip & URTWN_CHIP_88E) 415 urtwn_r88e_read_rom(sc); 416 else 417 urtwn_read_rom(sc); 418 419 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 420 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 421 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 422 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 423 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 424 "8188CUS", sc->ntxchains, sc->nrxchains); 425 426 URTWN_UNLOCK(sc); 427 428 ic->ic_softc = sc; 429 ic->ic_name = device_get_nameunit(self); 430 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 431 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 432 433 /* set device capabilities */ 434 ic->ic_caps = 435 IEEE80211_C_STA /* station mode */ 436 | IEEE80211_C_MONITOR /* monitor mode */ 437 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 438 | IEEE80211_C_SHSLOT /* short slot time supported */ 439 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 440 | IEEE80211_C_WPA /* 802.11i */ 441 ; 442 443 bands = 0; 444 setbit(&bands, IEEE80211_MODE_11B); 445 setbit(&bands, IEEE80211_MODE_11G); 446 ieee80211_init_channels(ic, NULL, &bands); 447 448 ieee80211_ifattach(ic); 449 ic->ic_raw_xmit = urtwn_raw_xmit; 450 ic->ic_scan_start = urtwn_scan_start; 451 ic->ic_scan_end = urtwn_scan_end; 452 ic->ic_set_channel = urtwn_set_channel; 453 ic->ic_transmit = urtwn_transmit; 454 ic->ic_parent = urtwn_parent; 455 ic->ic_vap_create = urtwn_vap_create; 456 ic->ic_vap_delete = urtwn_vap_delete; 457 ic->ic_update_mcast = urtwn_update_mcast; 458 459 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 460 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 461 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 462 URTWN_RX_RADIOTAP_PRESENT); 463 464 if (bootverbose) 465 ieee80211_announce(ic); 466 467 return (0); 468 469detach: 470 urtwn_detach(self); 471 return (ENXIO); /* failure */ 472} 473 474static int 475urtwn_detach(device_t self) 476{ 477 struct urtwn_softc *sc = device_get_softc(self); 478 struct ieee80211com *ic = &sc->sc_ic; 479 unsigned int x; 480 481 /* Prevent further ioctls. */ 482 URTWN_LOCK(sc); 483 sc->sc_flags |= URTWN_DETACHED; 484 urtwn_stop(sc); 485 URTWN_UNLOCK(sc); 486 487 callout_drain(&sc->sc_watchdog_ch); 488 489 /* stop all USB transfers */ 490 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 491 492 /* Prevent further allocations from RX/TX data lists. */ 493 URTWN_LOCK(sc); 494 STAILQ_INIT(&sc->sc_tx_active); 495 STAILQ_INIT(&sc->sc_tx_inactive); 496 STAILQ_INIT(&sc->sc_tx_pending); 497 498 STAILQ_INIT(&sc->sc_rx_active); 499 STAILQ_INIT(&sc->sc_rx_inactive); 500 URTWN_UNLOCK(sc); 501 502 /* drain USB transfers */ 503 for (x = 0; x != URTWN_N_TRANSFER; x++) 504 usbd_transfer_drain(sc->sc_xfer[x]); 505 506 /* Free data buffers. */ 507 URTWN_LOCK(sc); 508 urtwn_free_tx_list(sc); 509 urtwn_free_rx_list(sc); 510 URTWN_UNLOCK(sc); 511 512 ieee80211_ifdetach(ic); 513 mtx_destroy(&sc->sc_mtx); 514 515 return (0); 516} 517 518static void 519urtwn_drain_mbufq(struct urtwn_softc *sc) 520{ 521 struct mbuf *m; 522 struct ieee80211_node *ni; 523 URTWN_ASSERT_LOCKED(sc); 524 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 525 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 526 m->m_pkthdr.rcvif = NULL; 527 ieee80211_free_node(ni); 528 m_freem(m); 529 } 530} 531 532static usb_error_t 533urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 534 void *data) 535{ 536 usb_error_t err; 537 int ntries = 10; 538 539 URTWN_ASSERT_LOCKED(sc); 540 541 while (ntries--) { 542 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 543 req, data, 0, NULL, 250 /* ms */); 544 if (err == 0) 545 break; 546 547 DPRINTFN(1, "Control request failed, %s (retrying)\n", 548 usbd_errstr(err)); 549 usb_pause_mtx(&sc->sc_mtx, hz / 100); 550 } 551 return (err); 552} 553 554static struct ieee80211vap * 555urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 556 enum ieee80211_opmode opmode, int flags, 557 const uint8_t bssid[IEEE80211_ADDR_LEN], 558 const uint8_t mac[IEEE80211_ADDR_LEN]) 559{ 560 struct urtwn_vap *uvp; 561 struct ieee80211vap *vap; 562 563 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 564 return (NULL); 565 566 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 567 vap = &uvp->vap; 568 /* enable s/w bmiss handling for sta mode */ 569 570 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 571 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 572 /* out of memory */ 573 free(uvp, M_80211_VAP); 574 return (NULL); 575 } 576 577 /* override state transition machine */ 578 uvp->newstate = vap->iv_newstate; 579 vap->iv_newstate = urtwn_newstate; 580 581 /* complete setup */ 582 ieee80211_vap_attach(vap, ieee80211_media_change, 583 ieee80211_media_status, mac); 584 ic->ic_opmode = opmode; 585 return (vap); 586} 587 588static void 589urtwn_vap_delete(struct ieee80211vap *vap) 590{ 591 struct urtwn_vap *uvp = URTWN_VAP(vap); 592 593 ieee80211_vap_detach(vap); 594 free(uvp, M_80211_VAP); 595} 596 597static struct mbuf * 598urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 599{ 600 struct ieee80211com *ic = &sc->sc_ic; 601 struct ieee80211_frame *wh; 602 struct mbuf *m; 603 struct r92c_rx_stat *stat; 604 uint32_t rxdw0, rxdw3; 605 uint8_t rate; 606 int8_t rssi = 0; 607 int infosz; 608 609 /* 610 * don't pass packets to the ieee80211 framework if the driver isn't 611 * RUNNING. 612 */ 613 if (!(sc->sc_flags & URTWN_RUNNING)) 614 return (NULL); 615 616 stat = (struct r92c_rx_stat *)buf; 617 rxdw0 = le32toh(stat->rxdw0); 618 rxdw3 = le32toh(stat->rxdw3); 619 620 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 621 /* 622 * This should not happen since we setup our Rx filter 623 * to not receive these frames. 624 */ 625 counter_u64_add(ic->ic_ierrors, 1); 626 return (NULL); 627 } 628 if (pktlen < sizeof(*wh) || pktlen > MCLBYTES) { 629 counter_u64_add(ic->ic_ierrors, 1); 630 return (NULL); 631 } 632 633 rate = MS(rxdw3, R92C_RXDW3_RATE); 634 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 635 636 /* Get RSSI from PHY status descriptor if present. */ 637 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 638 if (sc->chip & URTWN_CHIP_88E) 639 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 640 else 641 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 642 /* Update our average RSSI. */ 643 urtwn_update_avgrssi(sc, rate, rssi); 644 } 645 646 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 647 if (m == NULL) { 648 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 649 return (NULL); 650 } 651 652 /* Finalize mbuf. */ 653 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 654 memcpy(mtod(m, uint8_t *), wh, pktlen); 655 m->m_pkthdr.len = m->m_len = pktlen; 656 657 if (ieee80211_radiotap_active(ic)) { 658 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 659 660 tap->wr_flags = 0; 661 /* Map HW rate index to 802.11 rate. */ 662 if (!(rxdw3 & R92C_RXDW3_HT)) { 663 tap->wr_rate = ridx2rate[rate]; 664 } else if (rate >= 12) { /* MCS0~15. */ 665 /* Bit 7 set means HT MCS instead of rate. */ 666 tap->wr_rate = 0x80 | (rate - 12); 667 } 668 tap->wr_dbm_antsignal = rssi; 669 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 670 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 671 } 672 673 *rssi_p = rssi; 674 675 return (m); 676} 677 678static struct mbuf * 679urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 680 int8_t *nf) 681{ 682 struct urtwn_softc *sc = data->sc; 683 struct ieee80211com *ic = &sc->sc_ic; 684 struct r92c_rx_stat *stat; 685 struct mbuf *m, *m0 = NULL, *prevm = NULL; 686 uint32_t rxdw0; 687 uint8_t *buf; 688 int len, totlen, pktlen, infosz, npkts; 689 690 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 691 692 if (len < sizeof(*stat)) { 693 counter_u64_add(ic->ic_ierrors, 1); 694 return (NULL); 695 } 696 697 buf = data->buf; 698 /* Get the number of encapsulated frames. */ 699 stat = (struct r92c_rx_stat *)buf; 700 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 701 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 702 703 /* Process all of them. */ 704 while (npkts-- > 0) { 705 if (len < sizeof(*stat)) 706 break; 707 stat = (struct r92c_rx_stat *)buf; 708 rxdw0 = le32toh(stat->rxdw0); 709 710 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 711 if (pktlen == 0) 712 break; 713 714 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 715 716 /* Make sure everything fits in xfer. */ 717 totlen = sizeof(*stat) + infosz + pktlen; 718 if (totlen > len) 719 break; 720 721 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 722 if (m0 == NULL) 723 m0 = m; 724 if (prevm == NULL) 725 prevm = m; 726 else { 727 prevm->m_next = m; 728 prevm = m; 729 } 730 731 /* Next chunk is 128-byte aligned. */ 732 totlen = (totlen + 127) & ~127; 733 buf += totlen; 734 len -= totlen; 735 } 736 737 return (m0); 738} 739 740static void 741urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 742{ 743 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 744 struct ieee80211com *ic = &sc->sc_ic; 745 struct ieee80211_frame *wh; 746 struct ieee80211_node *ni; 747 struct mbuf *m = NULL, *next; 748 struct urtwn_data *data; 749 int8_t nf; 750 int rssi = 1; 751 752 URTWN_ASSERT_LOCKED(sc); 753 754 switch (USB_GET_STATE(xfer)) { 755 case USB_ST_TRANSFERRED: 756 data = STAILQ_FIRST(&sc->sc_rx_active); 757 if (data == NULL) 758 goto tr_setup; 759 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 760 m = urtwn_rxeof(xfer, data, &rssi, &nf); 761 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 762 /* FALLTHROUGH */ 763 case USB_ST_SETUP: 764tr_setup: 765 data = STAILQ_FIRST(&sc->sc_rx_inactive); 766 if (data == NULL) { 767 KASSERT(m == NULL, ("mbuf isn't NULL")); 768 return; 769 } 770 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 771 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 772 usbd_xfer_set_frame_data(xfer, 0, data->buf, 773 usbd_xfer_max_len(xfer)); 774 usbd_transfer_submit(xfer); 775 776 /* 777 * To avoid LOR we should unlock our private mutex here to call 778 * ieee80211_input() because here is at the end of a USB 779 * callback and safe to unlock. 780 */ 781 URTWN_UNLOCK(sc); 782 while (m != NULL) { 783 next = m->m_next; 784 m->m_next = NULL; 785 wh = mtod(m, struct ieee80211_frame *); 786 ni = ieee80211_find_rxnode(ic, 787 (struct ieee80211_frame_min *)wh); 788 nf = URTWN_NOISE_FLOOR; 789 if (ni != NULL) { 790 (void)ieee80211_input(ni, m, rssi - nf, nf); 791 ieee80211_free_node(ni); 792 } else { 793 (void)ieee80211_input_all(ic, m, rssi - nf, 794 nf); 795 } 796 m = next; 797 } 798 URTWN_LOCK(sc); 799 break; 800 default: 801 /* needs it to the inactive queue due to a error. */ 802 data = STAILQ_FIRST(&sc->sc_rx_active); 803 if (data != NULL) { 804 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 805 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 806 } 807 if (error != USB_ERR_CANCELLED) { 808 usbd_xfer_set_stall(xfer); 809 counter_u64_add(ic->ic_ierrors, 1); 810 goto tr_setup; 811 } 812 break; 813 } 814} 815 816static void 817urtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 818{ 819 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 820 821 URTWN_ASSERT_LOCKED(sc); 822 /* XXX status? */ 823 ieee80211_tx_complete(data->ni, data->m, 0); 824 data->ni = NULL; 825 data->m = NULL; 826 sc->sc_txtimer = 0; 827} 828 829static int 830urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 831 int ndata, int maxsz) 832{ 833 int i, error; 834 835 for (i = 0; i < ndata; i++) { 836 struct urtwn_data *dp = &data[i]; 837 dp->sc = sc; 838 dp->m = NULL; 839 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 840 if (dp->buf == NULL) { 841 device_printf(sc->sc_dev, 842 "could not allocate buffer\n"); 843 error = ENOMEM; 844 goto fail; 845 } 846 dp->ni = NULL; 847 } 848 849 return (0); 850fail: 851 urtwn_free_list(sc, data, ndata); 852 return (error); 853} 854 855static int 856urtwn_alloc_rx_list(struct urtwn_softc *sc) 857{ 858 int error, i; 859 860 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 861 URTWN_RXBUFSZ); 862 if (error != 0) 863 return (error); 864 865 STAILQ_INIT(&sc->sc_rx_active); 866 STAILQ_INIT(&sc->sc_rx_inactive); 867 868 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 869 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 870 871 return (0); 872} 873 874static int 875urtwn_alloc_tx_list(struct urtwn_softc *sc) 876{ 877 int error, i; 878 879 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 880 URTWN_TXBUFSZ); 881 if (error != 0) 882 return (error); 883 884 STAILQ_INIT(&sc->sc_tx_active); 885 STAILQ_INIT(&sc->sc_tx_inactive); 886 STAILQ_INIT(&sc->sc_tx_pending); 887 888 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 889 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 890 891 return (0); 892} 893 894static void 895urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 896{ 897 int i; 898 899 for (i = 0; i < ndata; i++) { 900 struct urtwn_data *dp = &data[i]; 901 902 if (dp->buf != NULL) { 903 free(dp->buf, M_USBDEV); 904 dp->buf = NULL; 905 } 906 if (dp->ni != NULL) { 907 ieee80211_free_node(dp->ni); 908 dp->ni = NULL; 909 } 910 } 911} 912 913static void 914urtwn_free_rx_list(struct urtwn_softc *sc) 915{ 916 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 917} 918 919static void 920urtwn_free_tx_list(struct urtwn_softc *sc) 921{ 922 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 923} 924 925static void 926urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 927{ 928 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 929 struct urtwn_data *data; 930 931 URTWN_ASSERT_LOCKED(sc); 932 933 switch (USB_GET_STATE(xfer)){ 934 case USB_ST_TRANSFERRED: 935 data = STAILQ_FIRST(&sc->sc_tx_active); 936 if (data == NULL) 937 goto tr_setup; 938 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 939 urtwn_txeof(xfer, data); 940 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 941 /* FALLTHROUGH */ 942 case USB_ST_SETUP: 943tr_setup: 944 data = STAILQ_FIRST(&sc->sc_tx_pending); 945 if (data == NULL) { 946 DPRINTF("%s: empty pending queue\n", __func__); 947 goto finish; 948 } 949 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 950 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 951 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 952 usbd_transfer_submit(xfer); 953 break; 954 default: 955 data = STAILQ_FIRST(&sc->sc_tx_active); 956 if (data == NULL) 957 goto tr_setup; 958 if (data->ni != NULL) { 959 if_inc_counter(data->ni->ni_vap->iv_ifp, 960 IFCOUNTER_OERRORS, 1); 961 ieee80211_free_node(data->ni); 962 data->ni = NULL; 963 } 964 if (error != USB_ERR_CANCELLED) { 965 usbd_xfer_set_stall(xfer); 966 goto tr_setup; 967 } 968 break; 969 } 970finish: 971 /* Kick-start more transmit */ 972 urtwn_start(sc); 973} 974 975static struct urtwn_data * 976_urtwn_getbuf(struct urtwn_softc *sc) 977{ 978 struct urtwn_data *bf; 979 980 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 981 if (bf != NULL) 982 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 983 else 984 bf = NULL; 985 if (bf == NULL) 986 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 987 return (bf); 988} 989 990static struct urtwn_data * 991urtwn_getbuf(struct urtwn_softc *sc) 992{ 993 struct urtwn_data *bf; 994 995 URTWN_ASSERT_LOCKED(sc); 996 997 bf = _urtwn_getbuf(sc); 998 if (bf == NULL) 999 DPRINTF("%s: stop queue\n", __func__); 1000 return (bf); 1001} 1002 1003static int 1004urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1005 int len) 1006{ 1007 usb_device_request_t req; 1008 1009 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1010 req.bRequest = R92C_REQ_REGS; 1011 USETW(req.wValue, addr); 1012 USETW(req.wIndex, 0); 1013 USETW(req.wLength, len); 1014 return (urtwn_do_request(sc, &req, buf)); 1015} 1016 1017static void 1018urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1019{ 1020 urtwn_write_region_1(sc, addr, &val, 1); 1021} 1022 1023 1024static void 1025urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1026{ 1027 val = htole16(val); 1028 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1029} 1030 1031static void 1032urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1033{ 1034 val = htole32(val); 1035 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1036} 1037 1038static int 1039urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1040 int len) 1041{ 1042 usb_device_request_t req; 1043 1044 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1045 req.bRequest = R92C_REQ_REGS; 1046 USETW(req.wValue, addr); 1047 USETW(req.wIndex, 0); 1048 USETW(req.wLength, len); 1049 return (urtwn_do_request(sc, &req, buf)); 1050} 1051 1052static uint8_t 1053urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1054{ 1055 uint8_t val; 1056 1057 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1058 return (0xff); 1059 return (val); 1060} 1061 1062static uint16_t 1063urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1064{ 1065 uint16_t val; 1066 1067 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1068 return (0xffff); 1069 return (le16toh(val)); 1070} 1071 1072static uint32_t 1073urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1074{ 1075 uint32_t val; 1076 1077 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1078 return (0xffffffff); 1079 return (le32toh(val)); 1080} 1081 1082static int 1083urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1084{ 1085 struct r92c_fw_cmd cmd; 1086 int ntries; 1087 1088 /* Wait for current FW box to be empty. */ 1089 for (ntries = 0; ntries < 100; ntries++) { 1090 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1091 break; 1092 urtwn_ms_delay(sc); 1093 } 1094 if (ntries == 100) { 1095 device_printf(sc->sc_dev, 1096 "could not send firmware command\n"); 1097 return (ETIMEDOUT); 1098 } 1099 memset(&cmd, 0, sizeof(cmd)); 1100 cmd.id = id; 1101 if (len > 3) 1102 cmd.id |= R92C_CMD_FLAG_EXT; 1103 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1104 memcpy(cmd.msg, buf, len); 1105 1106 /* Write the first word last since that will trigger the FW. */ 1107 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1108 (uint8_t *)&cmd + 4, 2); 1109 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1110 (uint8_t *)&cmd + 0, 4); 1111 1112 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1113 return (0); 1114} 1115 1116static __inline void 1117urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1118{ 1119 1120 sc->sc_rf_write(sc, chain, addr, val); 1121} 1122 1123static void 1124urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1125 uint32_t val) 1126{ 1127 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1128 SM(R92C_LSSI_PARAM_ADDR, addr) | 1129 SM(R92C_LSSI_PARAM_DATA, val)); 1130} 1131 1132static void 1133urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1134uint32_t val) 1135{ 1136 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1137 SM(R88E_LSSI_PARAM_ADDR, addr) | 1138 SM(R92C_LSSI_PARAM_DATA, val)); 1139} 1140 1141static uint32_t 1142urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1143{ 1144 uint32_t reg[R92C_MAX_CHAINS], val; 1145 1146 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1147 if (chain != 0) 1148 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1149 1150 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1151 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1152 urtwn_ms_delay(sc); 1153 1154 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1155 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1156 R92C_HSSI_PARAM2_READ_EDGE); 1157 urtwn_ms_delay(sc); 1158 1159 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1160 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1161 urtwn_ms_delay(sc); 1162 1163 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1164 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1165 else 1166 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1167 return (MS(val, R92C_LSSI_READBACK_DATA)); 1168} 1169 1170static int 1171urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1172{ 1173 int ntries; 1174 1175 urtwn_write_4(sc, R92C_LLT_INIT, 1176 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1177 SM(R92C_LLT_INIT_ADDR, addr) | 1178 SM(R92C_LLT_INIT_DATA, data)); 1179 /* Wait for write operation to complete. */ 1180 for (ntries = 0; ntries < 20; ntries++) { 1181 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1182 R92C_LLT_INIT_OP_NO_ACTIVE) 1183 return (0); 1184 urtwn_ms_delay(sc); 1185 } 1186 return (ETIMEDOUT); 1187} 1188 1189static uint8_t 1190urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1191{ 1192 uint32_t reg; 1193 int ntries; 1194 1195 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1196 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1197 reg &= ~R92C_EFUSE_CTRL_VALID; 1198 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1199 /* Wait for read operation to complete. */ 1200 for (ntries = 0; ntries < 100; ntries++) { 1201 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1202 if (reg & R92C_EFUSE_CTRL_VALID) 1203 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1204 urtwn_ms_delay(sc); 1205 } 1206 device_printf(sc->sc_dev, 1207 "could not read efuse byte at address 0x%x\n", addr); 1208 return (0xff); 1209} 1210 1211static void 1212urtwn_efuse_read(struct urtwn_softc *sc) 1213{ 1214 uint8_t *rom = (uint8_t *)&sc->rom; 1215 uint16_t addr = 0; 1216 uint32_t reg; 1217 uint8_t off, msk; 1218 int i; 1219 1220 urtwn_efuse_switch_power(sc); 1221 1222 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1223 while (addr < 512) { 1224 reg = urtwn_efuse_read_1(sc, addr); 1225 if (reg == 0xff) 1226 break; 1227 addr++; 1228 off = reg >> 4; 1229 msk = reg & 0xf; 1230 for (i = 0; i < 4; i++) { 1231 if (msk & (1 << i)) 1232 continue; 1233 rom[off * 8 + i * 2 + 0] = 1234 urtwn_efuse_read_1(sc, addr); 1235 addr++; 1236 rom[off * 8 + i * 2 + 1] = 1237 urtwn_efuse_read_1(sc, addr); 1238 addr++; 1239 } 1240 } 1241#ifdef URTWN_DEBUG 1242 if (urtwn_debug >= 2) { 1243 /* Dump ROM content. */ 1244 printf("\n"); 1245 for (i = 0; i < sizeof(sc->rom); i++) 1246 printf("%02x:", rom[i]); 1247 printf("\n"); 1248 } 1249#endif 1250 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1251} 1252 1253static void 1254urtwn_efuse_switch_power(struct urtwn_softc *sc) 1255{ 1256 uint32_t reg; 1257 1258 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1259 1260 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1261 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1262 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1263 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1264 } 1265 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1266 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1267 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1268 reg | R92C_SYS_FUNC_EN_ELDR); 1269 } 1270 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1271 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1272 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1273 urtwn_write_2(sc, R92C_SYS_CLKR, 1274 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1275 } 1276} 1277 1278static int 1279urtwn_read_chipid(struct urtwn_softc *sc) 1280{ 1281 uint32_t reg; 1282 1283 if (sc->chip & URTWN_CHIP_88E) 1284 return (0); 1285 1286 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1287 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1288 return (EIO); 1289 1290 if (reg & R92C_SYS_CFG_TYPE_92C) { 1291 sc->chip |= URTWN_CHIP_92C; 1292 /* Check if it is a castrated 8192C. */ 1293 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1294 R92C_HPON_FSM_CHIP_BONDING_ID) == 1295 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1296 sc->chip |= URTWN_CHIP_92C_1T2R; 1297 } 1298 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1299 sc->chip |= URTWN_CHIP_UMC; 1300 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1301 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1302 } 1303 return (0); 1304} 1305 1306static void 1307urtwn_read_rom(struct urtwn_softc *sc) 1308{ 1309 struct r92c_rom *rom = &sc->rom; 1310 1311 /* Read full ROM image. */ 1312 urtwn_efuse_read(sc); 1313 1314 /* XXX Weird but this is what the vendor driver does. */ 1315 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1316 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1317 1318 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1319 1320 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1321 DPRINTF("regulatory type=%d\n", sc->regulatory); 1322 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1323 1324 sc->sc_rf_write = urtwn_r92c_rf_write; 1325 sc->sc_power_on = urtwn_r92c_power_on; 1326 sc->sc_dma_init = urtwn_r92c_dma_init; 1327} 1328 1329static void 1330urtwn_r88e_read_rom(struct urtwn_softc *sc) 1331{ 1332 uint8_t *rom = sc->r88e_rom; 1333 uint16_t addr = 0; 1334 uint32_t reg; 1335 uint8_t off, msk, tmp; 1336 int i; 1337 1338 off = 0; 1339 urtwn_efuse_switch_power(sc); 1340 1341 /* Read full ROM image. */ 1342 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1343 while (addr < 512) { 1344 reg = urtwn_efuse_read_1(sc, addr); 1345 if (reg == 0xff) 1346 break; 1347 addr++; 1348 if ((reg & 0x1f) == 0x0f) { 1349 tmp = (reg & 0xe0) >> 5; 1350 reg = urtwn_efuse_read_1(sc, addr); 1351 if ((reg & 0x0f) != 0x0f) 1352 off = ((reg & 0xf0) >> 1) | tmp; 1353 addr++; 1354 } else 1355 off = reg >> 4; 1356 msk = reg & 0xf; 1357 for (i = 0; i < 4; i++) { 1358 if (msk & (1 << i)) 1359 continue; 1360 rom[off * 8 + i * 2 + 0] = 1361 urtwn_efuse_read_1(sc, addr); 1362 addr++; 1363 rom[off * 8 + i * 2 + 1] = 1364 urtwn_efuse_read_1(sc, addr); 1365 addr++; 1366 } 1367 } 1368 1369 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1370 1371 addr = 0x10; 1372 for (i = 0; i < 6; i++) 1373 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1374 for (i = 0; i < 5; i++) 1375 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1376 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1377 if (sc->bw20_tx_pwr_diff & 0x08) 1378 sc->bw20_tx_pwr_diff |= 0xf0; 1379 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1380 if (sc->ofdm_tx_pwr_diff & 0x08) 1381 sc->ofdm_tx_pwr_diff |= 0xf0; 1382 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1383 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &sc->r88e_rom[0xd7]); 1384 1385 sc->sc_rf_write = urtwn_r88e_rf_write; 1386 sc->sc_power_on = urtwn_r88e_power_on; 1387 sc->sc_dma_init = urtwn_r88e_dma_init; 1388} 1389 1390/* 1391 * Initialize rate adaptation in firmware. 1392 */ 1393static int 1394urtwn_ra_init(struct urtwn_softc *sc) 1395{ 1396 struct ieee80211com *ic = &sc->sc_ic; 1397 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1398 struct ieee80211_node *ni; 1399 struct ieee80211_rateset *rs; 1400 struct r92c_fw_cmd_macid_cfg cmd; 1401 uint32_t rates, basicrates; 1402 uint8_t mode; 1403 int maxrate, maxbasicrate, error, i, j; 1404 1405 ni = ieee80211_ref_node(vap->iv_bss); 1406 rs = &ni->ni_rates; 1407 1408 /* Get normal and basic rates mask. */ 1409 rates = basicrates = 0; 1410 maxrate = maxbasicrate = 0; 1411 for (i = 0; i < rs->rs_nrates; i++) { 1412 /* Convert 802.11 rate to HW rate index. */ 1413 for (j = 0; j < nitems(ridx2rate); j++) 1414 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1415 ridx2rate[j]) 1416 break; 1417 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1418 continue; 1419 rates |= 1 << j; 1420 if (j > maxrate) 1421 maxrate = j; 1422 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1423 basicrates |= 1 << j; 1424 if (j > maxbasicrate) 1425 maxbasicrate = j; 1426 } 1427 } 1428 if (ic->ic_curmode == IEEE80211_MODE_11B) 1429 mode = R92C_RAID_11B; 1430 else 1431 mode = R92C_RAID_11BG; 1432 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1433 mode, rates, basicrates); 1434 1435 /* Set rates mask for group addressed frames. */ 1436 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1437 cmd.mask = htole32(mode << 28 | basicrates); 1438 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1439 if (error != 0) { 1440 ieee80211_free_node(ni); 1441 device_printf(sc->sc_dev, 1442 "could not add broadcast station\n"); 1443 return (error); 1444 } 1445 /* Set initial MRR rate. */ 1446 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1447 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1448 maxbasicrate); 1449 1450 /* Set rates mask for unicast frames. */ 1451 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1452 cmd.mask = htole32(mode << 28 | rates); 1453 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1454 if (error != 0) { 1455 ieee80211_free_node(ni); 1456 device_printf(sc->sc_dev, "could not add BSS station\n"); 1457 return (error); 1458 } 1459 /* Set initial MRR rate. */ 1460 DPRINTF("maxrate=%d\n", maxrate); 1461 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1462 maxrate); 1463 1464 /* Indicate highest supported rate. */ 1465 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1466 ieee80211_free_node(ni); 1467 1468 return (0); 1469} 1470 1471void 1472urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1473{ 1474 struct ieee80211com *ic = &sc->sc_ic; 1475 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1476 struct ieee80211_node *ni = vap->iv_bss; 1477 1478 uint64_t tsf; 1479 1480 /* Enable TSF synchronization. */ 1481 urtwn_write_1(sc, R92C_BCN_CTRL, 1482 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1483 1484 urtwn_write_1(sc, R92C_BCN_CTRL, 1485 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1486 1487 /* Set initial TSF. */ 1488 memcpy(&tsf, ni->ni_tstamp.data, 8); 1489 tsf = le64toh(tsf); 1490 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1491 tsf -= IEEE80211_DUR_TU; 1492 urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1493 urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1494 1495 urtwn_write_1(sc, R92C_BCN_CTRL, 1496 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1497} 1498 1499static void 1500urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1501{ 1502 uint8_t reg; 1503 1504 if (led == URTWN_LED_LINK) { 1505 if (sc->chip & URTWN_CHIP_88E) { 1506 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1507 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1508 if (!on) { 1509 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1510 urtwn_write_1(sc, R92C_LEDCFG2, 1511 reg | R92C_LEDCFG0_DIS); 1512 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1513 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1514 0xfe); 1515 } 1516 } else { 1517 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1518 if (!on) 1519 reg |= R92C_LEDCFG0_DIS; 1520 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1521 } 1522 sc->ledlink = on; /* Save LED state. */ 1523 } 1524} 1525 1526static void 1527urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 1528{ 1529 uint8_t reg; 1530 1531 reg = urtwn_read_1(sc, R92C_MSR); 1532 reg = (reg & ~R92C_MSR_MASK) | mode; 1533 urtwn_write_1(sc, R92C_MSR, reg); 1534} 1535 1536static int 1537urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1538{ 1539 struct urtwn_vap *uvp = URTWN_VAP(vap); 1540 struct ieee80211com *ic = vap->iv_ic; 1541 struct urtwn_softc *sc = ic->ic_softc; 1542 struct ieee80211_node *ni; 1543 enum ieee80211_state ostate; 1544 1545 ostate = vap->iv_state; 1546 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1547 ieee80211_state_name[nstate]); 1548 1549 IEEE80211_UNLOCK(ic); 1550 URTWN_LOCK(sc); 1551 callout_stop(&sc->sc_watchdog_ch); 1552 1553 if (ostate == IEEE80211_S_RUN) { 1554 /* Turn link LED off. */ 1555 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1556 1557 /* Set media status to 'No Link'. */ 1558 urtwn_set_mode(sc, R92C_MSR_NOLINK); 1559 1560 /* Stop Rx of data frames. */ 1561 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1562 1563 /* Rest TSF. */ 1564 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1565 1566 /* Disable TSF synchronization. */ 1567 urtwn_write_1(sc, R92C_BCN_CTRL, 1568 urtwn_read_1(sc, R92C_BCN_CTRL) | 1569 R92C_BCN_CTRL_DIS_TSF_UDT0); 1570 1571 /* Reset EDCA parameters. */ 1572 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1573 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1574 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1575 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1576 } 1577 1578 switch (nstate) { 1579 case IEEE80211_S_INIT: 1580 /* Turn link LED off. */ 1581 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1582 break; 1583 case IEEE80211_S_SCAN: 1584 if (ostate != IEEE80211_S_SCAN) { 1585 /* Allow Rx from any BSSID. */ 1586 urtwn_write_4(sc, R92C_RCR, 1587 urtwn_read_4(sc, R92C_RCR) & 1588 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1589 1590 /* Set gain for scanning. */ 1591 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1592 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1593 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1594 1595 if (!(sc->chip & URTWN_CHIP_88E)) { 1596 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1597 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1598 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1599 } 1600 } 1601 /* Pause AC Tx queues. */ 1602 urtwn_write_1(sc, R92C_TXPAUSE, 1603 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1604 break; 1605 case IEEE80211_S_AUTH: 1606 /* Set initial gain under link. */ 1607 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1608 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1609 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1610 1611 if (!(sc->chip & URTWN_CHIP_88E)) { 1612 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1613 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1614 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1615 } 1616 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1617 break; 1618 case IEEE80211_S_RUN: 1619 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1620 /* Enable Rx of data frames. */ 1621 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1622 1623 /* Enable Rx of ctrl frames. */ 1624 urtwn_write_2(sc, R92C_RXFLTMAP1, 0xffff); 1625 1626 /* 1627 * Accept data/control/management frames 1628 * from any BSSID. 1629 */ 1630 urtwn_write_4(sc, R92C_RCR, 1631 (urtwn_read_4(sc, R92C_RCR) & ~(R92C_RCR_APM | 1632 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)) | 1633 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF | 1634 R92C_RCR_AAP); 1635 1636 /* Turn link LED on. */ 1637 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1638 break; 1639 } 1640 1641 ni = ieee80211_ref_node(vap->iv_bss); 1642 /* Set media status to 'Associated'. */ 1643 urtwn_set_mode(sc, R92C_MSR_INFRA); 1644 1645 /* Set BSSID. */ 1646 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1647 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1648 1649 if (ic->ic_curmode == IEEE80211_MODE_11B) 1650 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1651 else /* 802.11b/g */ 1652 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1653 1654 /* Enable Rx of data frames. */ 1655 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1656 1657 /* Flush all AC queues. */ 1658 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1659 1660 /* Set beacon interval. */ 1661 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1662 1663 /* Allow Rx from our BSSID only. */ 1664 urtwn_write_4(sc, R92C_RCR, 1665 urtwn_read_4(sc, R92C_RCR) | 1666 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1667 1668 /* Enable TSF synchronization. */ 1669 urtwn_tsf_sync_enable(sc); 1670 1671 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1672 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1673 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1674 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1675 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1676 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1677 1678 /* Intialize rate adaptation. */ 1679 if (sc->chip & URTWN_CHIP_88E) 1680 ni->ni_txrate = 1681 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1682 else 1683 urtwn_ra_init(sc); 1684 /* Turn link LED on. */ 1685 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1686 1687 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1688 /* Reset temperature calibration state machine. */ 1689 sc->thcal_state = 0; 1690 sc->thcal_lctemp = 0; 1691 ieee80211_free_node(ni); 1692 break; 1693 default: 1694 break; 1695 } 1696 URTWN_UNLOCK(sc); 1697 IEEE80211_LOCK(ic); 1698 return(uvp->newstate(vap, nstate, arg)); 1699} 1700 1701static void 1702urtwn_watchdog(void *arg) 1703{ 1704 struct urtwn_softc *sc = arg; 1705 1706 if (sc->sc_txtimer > 0) { 1707 if (--sc->sc_txtimer == 0) { 1708 device_printf(sc->sc_dev, "device timeout\n"); 1709 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1710 return; 1711 } 1712 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1713 } 1714} 1715 1716static void 1717urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1718{ 1719 int pwdb; 1720 1721 /* Convert antenna signal to percentage. */ 1722 if (rssi <= -100 || rssi >= 20) 1723 pwdb = 0; 1724 else if (rssi >= 0) 1725 pwdb = 100; 1726 else 1727 pwdb = 100 + rssi; 1728 if (!(sc->chip & URTWN_CHIP_88E)) { 1729 if (rate <= URTWN_RIDX_CCK11) { 1730 /* CCK gain is smaller than OFDM/MCS gain. */ 1731 pwdb += 6; 1732 if (pwdb > 100) 1733 pwdb = 100; 1734 if (pwdb <= 14) 1735 pwdb -= 4; 1736 else if (pwdb <= 26) 1737 pwdb -= 8; 1738 else if (pwdb <= 34) 1739 pwdb -= 6; 1740 else if (pwdb <= 42) 1741 pwdb -= 2; 1742 } 1743 } 1744 if (sc->avg_pwdb == -1) /* Init. */ 1745 sc->avg_pwdb = pwdb; 1746 else if (sc->avg_pwdb < pwdb) 1747 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1748 else 1749 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1750 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1751} 1752 1753static int8_t 1754urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1755{ 1756 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1757 struct r92c_rx_phystat *phy; 1758 struct r92c_rx_cck *cck; 1759 uint8_t rpt; 1760 int8_t rssi; 1761 1762 if (rate <= URTWN_RIDX_CCK11) { 1763 cck = (struct r92c_rx_cck *)physt; 1764 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1765 rpt = (cck->agc_rpt >> 5) & 0x3; 1766 rssi = (cck->agc_rpt & 0x1f) << 1; 1767 } else { 1768 rpt = (cck->agc_rpt >> 6) & 0x3; 1769 rssi = cck->agc_rpt & 0x3e; 1770 } 1771 rssi = cckoff[rpt] - rssi; 1772 } else { /* OFDM/HT. */ 1773 phy = (struct r92c_rx_phystat *)physt; 1774 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1775 } 1776 return (rssi); 1777} 1778 1779static int8_t 1780urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1781{ 1782 struct r92c_rx_phystat *phy; 1783 struct r88e_rx_cck *cck; 1784 uint8_t cck_agc_rpt, lna_idx, vga_idx; 1785 int8_t rssi; 1786 1787 rssi = 0; 1788 if (rate <= URTWN_RIDX_CCK11) { 1789 cck = (struct r88e_rx_cck *)physt; 1790 cck_agc_rpt = cck->agc_rpt; 1791 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1792 vga_idx = cck_agc_rpt & 0x1f; 1793 switch (lna_idx) { 1794 case 7: 1795 if (vga_idx <= 27) 1796 rssi = -100 + 2* (27 - vga_idx); 1797 else 1798 rssi = -100; 1799 break; 1800 case 6: 1801 rssi = -48 + 2 * (2 - vga_idx); 1802 break; 1803 case 5: 1804 rssi = -42 + 2 * (7 - vga_idx); 1805 break; 1806 case 4: 1807 rssi = -36 + 2 * (7 - vga_idx); 1808 break; 1809 case 3: 1810 rssi = -24 + 2 * (7 - vga_idx); 1811 break; 1812 case 2: 1813 rssi = -12 + 2 * (5 - vga_idx); 1814 break; 1815 case 1: 1816 rssi = 8 - (2 * vga_idx); 1817 break; 1818 case 0: 1819 rssi = 14 - (2 * vga_idx); 1820 break; 1821 } 1822 rssi += 6; 1823 } else { /* OFDM/HT. */ 1824 phy = (struct r92c_rx_phystat *)physt; 1825 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1826 } 1827 return (rssi); 1828} 1829 1830static int 1831urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1832 struct mbuf *m0, struct urtwn_data *data) 1833{ 1834 struct ieee80211_frame *wh; 1835 struct ieee80211_key *k; 1836 struct ieee80211com *ic = &sc->sc_ic; 1837 struct ieee80211vap *vap = ni->ni_vap; 1838 struct usb_xfer *xfer; 1839 struct r92c_tx_desc *txd; 1840 uint8_t raid, type; 1841 uint16_t sum; 1842 int i, xferlen; 1843 struct usb_xfer *urtwn_pipes[4] = { 1844 sc->sc_xfer[URTWN_BULK_TX_BE], 1845 sc->sc_xfer[URTWN_BULK_TX_BK], 1846 sc->sc_xfer[URTWN_BULK_TX_VI], 1847 sc->sc_xfer[URTWN_BULK_TX_VO] 1848 }; 1849 1850 URTWN_ASSERT_LOCKED(sc); 1851 1852 /* 1853 * Software crypto. 1854 */ 1855 wh = mtod(m0, struct ieee80211_frame *); 1856 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1857 1858 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1859 k = ieee80211_crypto_encap(ni, m0); 1860 if (k == NULL) { 1861 device_printf(sc->sc_dev, 1862 "ieee80211_crypto_encap returns NULL.\n"); 1863 /* XXX we don't expect the fragmented frames */ 1864 return (ENOBUFS); 1865 } 1866 1867 /* in case packet header moved, reset pointer */ 1868 wh = mtod(m0, struct ieee80211_frame *); 1869 } 1870 1871 switch (type) { 1872 case IEEE80211_FC0_TYPE_CTL: 1873 case IEEE80211_FC0_TYPE_MGT: 1874 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1875 break; 1876 default: 1877 KASSERT(M_WME_GETAC(m0) < 4, 1878 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1879 xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1880 break; 1881 } 1882 1883 /* Fill Tx descriptor. */ 1884 txd = (struct r92c_tx_desc *)data->buf; 1885 memset(txd, 0, sizeof(*txd)); 1886 1887 txd->txdw0 |= htole32( 1888 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1889 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1890 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1891 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1892 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1893 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1894 type == IEEE80211_FC0_TYPE_DATA) { 1895 if (ic->ic_curmode == IEEE80211_MODE_11B) 1896 raid = R92C_RAID_11B; 1897 else 1898 raid = R92C_RAID_11BG; 1899 if (sc->chip & URTWN_CHIP_88E) { 1900 txd->txdw1 |= htole32( 1901 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1902 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1903 SM(R92C_TXDW1_RAID, raid)); 1904 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1905 } else { 1906 txd->txdw1 |= htole32( 1907 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1908 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1909 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1910 } 1911 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1912 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1913 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1914 R92C_TXDW4_HWRTSEN); 1915 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1916 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1917 R92C_TXDW4_HWRTSEN); 1918 } 1919 } 1920 /* Send RTS at OFDM24. */ 1921 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1922 URTWN_RIDX_OFDM24)); 1923 txd->txdw5 |= htole32(0x0001ff00); 1924 /* Send data at OFDM54. */ 1925 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1926 URTWN_RIDX_OFDM54)); 1927 } else { 1928 txd->txdw1 |= htole32( 1929 SM(R92C_TXDW1_MACID, 0) | 1930 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1931 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1932 1933 /* Force CCK1. */ 1934 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1935 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1936 URTWN_RIDX_CCK1)); 1937 } 1938 /* Set sequence number (already little endian). */ 1939 txd->txdseq |= *(uint16_t *)wh->i_seq; 1940 1941 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 1942 /* Use HW sequence numbering for non-QoS frames. */ 1943 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1944 txd->txdseq |= htole16(0x8000); 1945 } else 1946 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1947 1948 /* Compute Tx descriptor checksum. */ 1949 sum = 0; 1950 for (i = 0; i < sizeof(*txd) / 2; i++) 1951 sum ^= ((uint16_t *)txd)[i]; 1952 txd->txdsum = sum; /* NB: already little endian. */ 1953 1954 if (ieee80211_radiotap_active_vap(vap)) { 1955 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1956 1957 tap->wt_flags = 0; 1958 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1959 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1960 ieee80211_radiotap_tx(vap, m0); 1961 } 1962 1963 xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1964 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1965 1966 data->buflen = xferlen; 1967 data->ni = ni; 1968 data->m = m0; 1969 1970 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1971 usbd_transfer_start(xfer); 1972 return (0); 1973} 1974 1975static int 1976urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1977{ 1978 struct urtwn_softc *sc = ic->ic_softc; 1979 int error; 1980 1981 URTWN_LOCK(sc); 1982 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1983 URTWN_UNLOCK(sc); 1984 return (ENXIO); 1985 } 1986 error = mbufq_enqueue(&sc->sc_snd, m); 1987 if (error) { 1988 URTWN_UNLOCK(sc); 1989 return (error); 1990 } 1991 urtwn_start(sc); 1992 URTWN_UNLOCK(sc); 1993 1994 return (0); 1995} 1996 1997static void 1998urtwn_start(struct urtwn_softc *sc) 1999{ 2000 struct ieee80211_node *ni; 2001 struct mbuf *m; 2002 struct urtwn_data *bf; 2003 2004 URTWN_ASSERT_LOCKED(sc); 2005 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2006 bf = urtwn_getbuf(sc); 2007 if (bf == NULL) { 2008 mbufq_prepend(&sc->sc_snd, m); 2009 break; 2010 } 2011 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2012 m->m_pkthdr.rcvif = NULL; 2013 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 2014 if_inc_counter(ni->ni_vap->iv_ifp, 2015 IFCOUNTER_OERRORS, 1); 2016 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2017 m_freem(m); 2018 ieee80211_free_node(ni); 2019 break; 2020 } 2021 sc->sc_txtimer = 5; 2022 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2023 } 2024} 2025 2026static void 2027urtwn_parent(struct ieee80211com *ic) 2028{ 2029 struct urtwn_softc *sc = ic->ic_softc; 2030 int startall = 0; 2031 2032 URTWN_LOCK(sc); 2033 if (sc->sc_flags & URTWN_DETACHED) { 2034 URTWN_UNLOCK(sc); 2035 return; 2036 } 2037 if (ic->ic_nrunning > 0) { 2038 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2039 urtwn_init(sc); 2040 startall = 1; 2041 } 2042 } else if (sc->sc_flags & URTWN_RUNNING) 2043 urtwn_stop(sc); 2044 URTWN_UNLOCK(sc); 2045 2046 if (startall) 2047 ieee80211_start_all(ic); 2048} 2049 2050static __inline int 2051urtwn_power_on(struct urtwn_softc *sc) 2052{ 2053 2054 return sc->sc_power_on(sc); 2055} 2056 2057static int 2058urtwn_r92c_power_on(struct urtwn_softc *sc) 2059{ 2060 uint32_t reg; 2061 int ntries; 2062 2063 /* Wait for autoload done bit. */ 2064 for (ntries = 0; ntries < 1000; ntries++) { 2065 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2066 break; 2067 urtwn_ms_delay(sc); 2068 } 2069 if (ntries == 1000) { 2070 device_printf(sc->sc_dev, 2071 "timeout waiting for chip autoload\n"); 2072 return (ETIMEDOUT); 2073 } 2074 2075 /* Unlock ISO/CLK/Power control register. */ 2076 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2077 /* Move SPS into PWM mode. */ 2078 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2079 urtwn_ms_delay(sc); 2080 2081 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2082 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2083 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2084 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2085 urtwn_ms_delay(sc); 2086 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2087 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2088 ~R92C_SYS_ISO_CTRL_MD2PP); 2089 } 2090 2091 /* Auto enable WLAN. */ 2092 urtwn_write_2(sc, R92C_APS_FSMCO, 2093 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2094 for (ntries = 0; ntries < 1000; ntries++) { 2095 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2096 R92C_APS_FSMCO_APFM_ONMAC)) 2097 break; 2098 urtwn_ms_delay(sc); 2099 } 2100 if (ntries == 1000) { 2101 device_printf(sc->sc_dev, 2102 "timeout waiting for MAC auto ON\n"); 2103 return (ETIMEDOUT); 2104 } 2105 2106 /* Enable radio, GPIO and LED functions. */ 2107 urtwn_write_2(sc, R92C_APS_FSMCO, 2108 R92C_APS_FSMCO_AFSM_HSUS | 2109 R92C_APS_FSMCO_PDN_EN | 2110 R92C_APS_FSMCO_PFM_ALDN); 2111 /* Release RF digital isolation. */ 2112 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2113 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2114 2115 /* Initialize MAC. */ 2116 urtwn_write_1(sc, R92C_APSD_CTRL, 2117 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2118 for (ntries = 0; ntries < 200; ntries++) { 2119 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2120 R92C_APSD_CTRL_OFF_STATUS)) 2121 break; 2122 urtwn_ms_delay(sc); 2123 } 2124 if (ntries == 200) { 2125 device_printf(sc->sc_dev, 2126 "timeout waiting for MAC initialization\n"); 2127 return (ETIMEDOUT); 2128 } 2129 2130 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2131 reg = urtwn_read_2(sc, R92C_CR); 2132 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2133 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2134 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2135 R92C_CR_ENSEC; 2136 urtwn_write_2(sc, R92C_CR, reg); 2137 2138 urtwn_write_1(sc, 0xfe10, 0x19); 2139 return (0); 2140} 2141 2142static int 2143urtwn_r88e_power_on(struct urtwn_softc *sc) 2144{ 2145 uint32_t reg; 2146 int ntries; 2147 2148 /* Wait for power ready bit. */ 2149 for (ntries = 0; ntries < 5000; ntries++) { 2150 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2151 break; 2152 urtwn_ms_delay(sc); 2153 } 2154 if (ntries == 5000) { 2155 device_printf(sc->sc_dev, 2156 "timeout waiting for chip power up\n"); 2157 return (ETIMEDOUT); 2158 } 2159 2160 /* Reset BB. */ 2161 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2162 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2163 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2164 2165 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2166 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2167 2168 /* Disable HWPDN. */ 2169 urtwn_write_2(sc, R92C_APS_FSMCO, 2170 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2171 2172 /* Disable WL suspend. */ 2173 urtwn_write_2(sc, R92C_APS_FSMCO, 2174 urtwn_read_2(sc, R92C_APS_FSMCO) & 2175 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2176 2177 urtwn_write_2(sc, R92C_APS_FSMCO, 2178 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2179 for (ntries = 0; ntries < 5000; ntries++) { 2180 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2181 R92C_APS_FSMCO_APFM_ONMAC)) 2182 break; 2183 urtwn_ms_delay(sc); 2184 } 2185 if (ntries == 5000) 2186 return (ETIMEDOUT); 2187 2188 /* Enable LDO normal mode. */ 2189 urtwn_write_1(sc, R92C_LPLDO_CTRL, 2190 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2191 2192 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2193 urtwn_write_2(sc, R92C_CR, 0); 2194 reg = urtwn_read_2(sc, R92C_CR); 2195 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2196 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2197 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2198 urtwn_write_2(sc, R92C_CR, reg); 2199 2200 return (0); 2201} 2202 2203static int 2204urtwn_llt_init(struct urtwn_softc *sc) 2205{ 2206 int i, error, page_count, pktbuf_count; 2207 2208 page_count = (sc->chip & URTWN_CHIP_88E) ? 2209 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2210 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2211 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2212 2213 /* Reserve pages [0; page_count]. */ 2214 for (i = 0; i < page_count; i++) { 2215 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2216 return (error); 2217 } 2218 /* NB: 0xff indicates end-of-list. */ 2219 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2220 return (error); 2221 /* 2222 * Use pages [page_count + 1; pktbuf_count - 1] 2223 * as ring buffer. 2224 */ 2225 for (++i; i < pktbuf_count - 1; i++) { 2226 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2227 return (error); 2228 } 2229 /* Make the last page point to the beginning of the ring buffer. */ 2230 error = urtwn_llt_write(sc, i, page_count + 1); 2231 return (error); 2232} 2233 2234static void 2235urtwn_fw_reset(struct urtwn_softc *sc) 2236{ 2237 uint16_t reg; 2238 int ntries; 2239 2240 /* Tell 8051 to reset itself. */ 2241 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2242 2243 /* Wait until 8051 resets by itself. */ 2244 for (ntries = 0; ntries < 100; ntries++) { 2245 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2246 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2247 return; 2248 urtwn_ms_delay(sc); 2249 } 2250 /* Force 8051 reset. */ 2251 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2252} 2253 2254static void 2255urtwn_r88e_fw_reset(struct urtwn_softc *sc) 2256{ 2257 uint16_t reg; 2258 2259 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2260 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2261 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2262} 2263 2264static int 2265urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2266{ 2267 uint32_t reg; 2268 int off, mlen, error = 0; 2269 2270 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2271 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2272 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2273 2274 off = R92C_FW_START_ADDR; 2275 while (len > 0) { 2276 if (len > 196) 2277 mlen = 196; 2278 else if (len > 4) 2279 mlen = 4; 2280 else 2281 mlen = 1; 2282 /* XXX fix this deconst */ 2283 error = urtwn_write_region_1(sc, off, 2284 __DECONST(uint8_t *, buf), mlen); 2285 if (error != 0) 2286 break; 2287 off += mlen; 2288 buf += mlen; 2289 len -= mlen; 2290 } 2291 return (error); 2292} 2293 2294static int 2295urtwn_load_firmware(struct urtwn_softc *sc) 2296{ 2297 const struct firmware *fw; 2298 const struct r92c_fw_hdr *hdr; 2299 const char *imagename; 2300 const u_char *ptr; 2301 size_t len; 2302 uint32_t reg; 2303 int mlen, ntries, page, error; 2304 2305 URTWN_UNLOCK(sc); 2306 /* Read firmware image from the filesystem. */ 2307 if (sc->chip & URTWN_CHIP_88E) 2308 imagename = "urtwn-rtl8188eufw"; 2309 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2310 URTWN_CHIP_UMC_A_CUT) 2311 imagename = "urtwn-rtl8192cfwU"; 2312 else 2313 imagename = "urtwn-rtl8192cfwT"; 2314 2315 fw = firmware_get(imagename); 2316 URTWN_LOCK(sc); 2317 if (fw == NULL) { 2318 device_printf(sc->sc_dev, 2319 "failed loadfirmware of file %s\n", imagename); 2320 return (ENOENT); 2321 } 2322 2323 len = fw->datasize; 2324 2325 if (len < sizeof(*hdr)) { 2326 device_printf(sc->sc_dev, "firmware too short\n"); 2327 error = EINVAL; 2328 goto fail; 2329 } 2330 ptr = fw->data; 2331 hdr = (const struct r92c_fw_hdr *)ptr; 2332 /* Check if there is a valid FW header and skip it. */ 2333 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2334 (le16toh(hdr->signature) >> 4) == 0x88e || 2335 (le16toh(hdr->signature) >> 4) == 0x92c) { 2336 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2337 le16toh(hdr->version), le16toh(hdr->subversion), 2338 hdr->month, hdr->date, hdr->hour, hdr->minute); 2339 ptr += sizeof(*hdr); 2340 len -= sizeof(*hdr); 2341 } 2342 2343 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2344 if (sc->chip & URTWN_CHIP_88E) 2345 urtwn_r88e_fw_reset(sc); 2346 else 2347 urtwn_fw_reset(sc); 2348 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2349 } 2350 2351 if (!(sc->chip & URTWN_CHIP_88E)) { 2352 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2353 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2354 R92C_SYS_FUNC_EN_CPUEN); 2355 } 2356 urtwn_write_1(sc, R92C_MCUFWDL, 2357 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2358 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2359 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2360 2361 /* Reset the FWDL checksum. */ 2362 urtwn_write_1(sc, R92C_MCUFWDL, 2363 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2364 2365 for (page = 0; len > 0; page++) { 2366 mlen = min(len, R92C_FW_PAGE_SIZE); 2367 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2368 if (error != 0) { 2369 device_printf(sc->sc_dev, 2370 "could not load firmware page\n"); 2371 goto fail; 2372 } 2373 ptr += mlen; 2374 len -= mlen; 2375 } 2376 urtwn_write_1(sc, R92C_MCUFWDL, 2377 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2378 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2379 2380 /* Wait for checksum report. */ 2381 for (ntries = 0; ntries < 1000; ntries++) { 2382 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2383 break; 2384 urtwn_ms_delay(sc); 2385 } 2386 if (ntries == 1000) { 2387 device_printf(sc->sc_dev, 2388 "timeout waiting for checksum report\n"); 2389 error = ETIMEDOUT; 2390 goto fail; 2391 } 2392 2393 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2394 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2395 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2396 if (sc->chip & URTWN_CHIP_88E) 2397 urtwn_r88e_fw_reset(sc); 2398 /* Wait for firmware readiness. */ 2399 for (ntries = 0; ntries < 1000; ntries++) { 2400 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2401 break; 2402 urtwn_ms_delay(sc); 2403 } 2404 if (ntries == 1000) { 2405 device_printf(sc->sc_dev, 2406 "timeout waiting for firmware readiness\n"); 2407 error = ETIMEDOUT; 2408 goto fail; 2409 } 2410fail: 2411 firmware_put(fw, FIRMWARE_UNLOAD); 2412 return (error); 2413} 2414 2415static __inline int 2416urtwn_dma_init(struct urtwn_softc *sc) 2417{ 2418 2419 return sc->sc_dma_init(sc); 2420} 2421 2422static int 2423urtwn_r92c_dma_init(struct urtwn_softc *sc) 2424{ 2425 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2426 uint32_t reg; 2427 int error; 2428 2429 /* Initialize LLT table. */ 2430 error = urtwn_llt_init(sc); 2431 if (error != 0) 2432 return (error); 2433 2434 /* Get Tx queues to USB endpoints mapping. */ 2435 hashq = hasnq = haslq = 0; 2436 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2437 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2438 if (MS(reg, R92C_USB_EP_HQ) != 0) 2439 hashq = 1; 2440 if (MS(reg, R92C_USB_EP_NQ) != 0) 2441 hasnq = 1; 2442 if (MS(reg, R92C_USB_EP_LQ) != 0) 2443 haslq = 1; 2444 nqueues = hashq + hasnq + haslq; 2445 if (nqueues == 0) 2446 return (EIO); 2447 /* Get the number of pages for each queue. */ 2448 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2449 /* The remaining pages are assigned to the high priority queue. */ 2450 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2451 2452 /* Set number of pages for normal priority queue. */ 2453 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2454 urtwn_write_4(sc, R92C_RQPN, 2455 /* Set number of pages for public queue. */ 2456 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2457 /* Set number of pages for high priority queue. */ 2458 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2459 /* Set number of pages for low priority queue. */ 2460 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2461 /* Load values. */ 2462 R92C_RQPN_LD); 2463 2464 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2465 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2466 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2467 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2468 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2469 2470 /* Set queue to USB pipe mapping. */ 2471 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2472 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2473 if (nqueues == 1) { 2474 if (hashq) 2475 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2476 else if (hasnq) 2477 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2478 else 2479 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2480 } else if (nqueues == 2) { 2481 /* All 2-endpoints configs have a high priority queue. */ 2482 if (!hashq) 2483 return (EIO); 2484 if (hasnq) 2485 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2486 else 2487 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2488 } else 2489 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2490 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2491 2492 /* Set Tx/Rx transfer page boundary. */ 2493 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2494 2495 /* Set Tx/Rx transfer page size. */ 2496 urtwn_write_1(sc, R92C_PBP, 2497 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2498 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2499 return (0); 2500} 2501 2502static int 2503urtwn_r88e_dma_init(struct urtwn_softc *sc) 2504{ 2505 struct usb_interface *iface; 2506 uint32_t reg; 2507 int nqueues; 2508 int error; 2509 2510 /* Initialize LLT table. */ 2511 error = urtwn_llt_init(sc); 2512 if (error != 0) 2513 return (error); 2514 2515 /* Get Tx queues to USB endpoints mapping. */ 2516 iface = usbd_get_iface(sc->sc_udev, 0); 2517 nqueues = iface->idesc->bNumEndpoints - 1; 2518 if (nqueues == 0) 2519 return (EIO); 2520 2521 /* Set number of pages for normal priority queue. */ 2522 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2523 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2524 2525 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2526 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2527 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2528 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2529 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2530 2531 /* Set queue to USB pipe mapping. */ 2532 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2533 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2534 if (nqueues == 1) 2535 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2536 else if (nqueues == 2) 2537 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2538 else 2539 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2540 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2541 2542 /* Set Tx/Rx transfer page boundary. */ 2543 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2544 2545 /* Set Tx/Rx transfer page size. */ 2546 urtwn_write_1(sc, R92C_PBP, 2547 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2548 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2549 2550 return (0); 2551} 2552 2553static void 2554urtwn_mac_init(struct urtwn_softc *sc) 2555{ 2556 int i; 2557 2558 /* Write MAC initialization values. */ 2559 if (sc->chip & URTWN_CHIP_88E) { 2560 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2561 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2562 rtl8188eu_mac[i].val); 2563 } 2564 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2565 } else { 2566 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2567 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2568 rtl8192cu_mac[i].val); 2569 } 2570} 2571 2572static void 2573urtwn_bb_init(struct urtwn_softc *sc) 2574{ 2575 const struct urtwn_bb_prog *prog; 2576 uint32_t reg; 2577 uint8_t crystalcap; 2578 int i; 2579 2580 /* Enable BB and RF. */ 2581 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2582 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2583 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2584 R92C_SYS_FUNC_EN_DIO_RF); 2585 2586 if (!(sc->chip & URTWN_CHIP_88E)) 2587 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2588 2589 urtwn_write_1(sc, R92C_RF_CTRL, 2590 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2591 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2592 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2593 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2594 2595 if (!(sc->chip & URTWN_CHIP_88E)) { 2596 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2597 urtwn_write_1(sc, 0x15, 0xe9); 2598 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2599 } 2600 2601 /* Select BB programming based on board type. */ 2602 if (sc->chip & URTWN_CHIP_88E) 2603 prog = &rtl8188eu_bb_prog; 2604 else if (!(sc->chip & URTWN_CHIP_92C)) { 2605 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2606 prog = &rtl8188ce_bb_prog; 2607 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2608 prog = &rtl8188ru_bb_prog; 2609 else 2610 prog = &rtl8188cu_bb_prog; 2611 } else { 2612 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2613 prog = &rtl8192ce_bb_prog; 2614 else 2615 prog = &rtl8192cu_bb_prog; 2616 } 2617 /* Write BB initialization values. */ 2618 for (i = 0; i < prog->count; i++) { 2619 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2620 urtwn_ms_delay(sc); 2621 } 2622 2623 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2624 /* 8192C 1T only configuration. */ 2625 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2626 reg = (reg & ~0x00000003) | 0x2; 2627 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2628 2629 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2630 reg = (reg & ~0x00300033) | 0x00200022; 2631 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2632 2633 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2634 reg = (reg & ~0xff000000) | 0x45 << 24; 2635 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2636 2637 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2638 reg = (reg & ~0x000000ff) | 0x23; 2639 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2640 2641 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2642 reg = (reg & ~0x00000030) | 1 << 4; 2643 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2644 2645 reg = urtwn_bb_read(sc, 0xe74); 2646 reg = (reg & ~0x0c000000) | 2 << 26; 2647 urtwn_bb_write(sc, 0xe74, reg); 2648 reg = urtwn_bb_read(sc, 0xe78); 2649 reg = (reg & ~0x0c000000) | 2 << 26; 2650 urtwn_bb_write(sc, 0xe78, reg); 2651 reg = urtwn_bb_read(sc, 0xe7c); 2652 reg = (reg & ~0x0c000000) | 2 << 26; 2653 urtwn_bb_write(sc, 0xe7c, reg); 2654 reg = urtwn_bb_read(sc, 0xe80); 2655 reg = (reg & ~0x0c000000) | 2 << 26; 2656 urtwn_bb_write(sc, 0xe80, reg); 2657 reg = urtwn_bb_read(sc, 0xe88); 2658 reg = (reg & ~0x0c000000) | 2 << 26; 2659 urtwn_bb_write(sc, 0xe88, reg); 2660 } 2661 2662 /* Write AGC values. */ 2663 for (i = 0; i < prog->agccount; i++) { 2664 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2665 prog->agcvals[i]); 2666 urtwn_ms_delay(sc); 2667 } 2668 2669 if (sc->chip & URTWN_CHIP_88E) { 2670 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2671 urtwn_ms_delay(sc); 2672 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2673 urtwn_ms_delay(sc); 2674 2675 crystalcap = sc->r88e_rom[0xb9]; 2676 if (crystalcap == 0xff) 2677 crystalcap = 0x20; 2678 crystalcap &= 0x3f; 2679 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2680 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2681 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2682 crystalcap | crystalcap << 6)); 2683 } else { 2684 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2685 R92C_HSSI_PARAM2_CCK_HIPWR) 2686 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2687 } 2688} 2689 2690static void 2691urtwn_rf_init(struct urtwn_softc *sc) 2692{ 2693 const struct urtwn_rf_prog *prog; 2694 uint32_t reg, type; 2695 int i, j, idx, off; 2696 2697 /* Select RF programming based on board type. */ 2698 if (sc->chip & URTWN_CHIP_88E) 2699 prog = rtl8188eu_rf_prog; 2700 else if (!(sc->chip & URTWN_CHIP_92C)) { 2701 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2702 prog = rtl8188ce_rf_prog; 2703 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2704 prog = rtl8188ru_rf_prog; 2705 else 2706 prog = rtl8188cu_rf_prog; 2707 } else 2708 prog = rtl8192ce_rf_prog; 2709 2710 for (i = 0; i < sc->nrxchains; i++) { 2711 /* Save RF_ENV control type. */ 2712 idx = i / 2; 2713 off = (i % 2) * 16; 2714 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2715 type = (reg >> off) & 0x10; 2716 2717 /* Set RF_ENV enable. */ 2718 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2719 reg |= 0x100000; 2720 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2721 urtwn_ms_delay(sc); 2722 /* Set RF_ENV output high. */ 2723 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2724 reg |= 0x10; 2725 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2726 urtwn_ms_delay(sc); 2727 /* Set address and data lengths of RF registers. */ 2728 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2729 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2730 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2731 urtwn_ms_delay(sc); 2732 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2733 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2734 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2735 urtwn_ms_delay(sc); 2736 2737 /* Write RF initialization values for this chain. */ 2738 for (j = 0; j < prog[i].count; j++) { 2739 if (prog[i].regs[j] >= 0xf9 && 2740 prog[i].regs[j] <= 0xfe) { 2741 /* 2742 * These are fake RF registers offsets that 2743 * indicate a delay is required. 2744 */ 2745 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2746 continue; 2747 } 2748 urtwn_rf_write(sc, i, prog[i].regs[j], 2749 prog[i].vals[j]); 2750 urtwn_ms_delay(sc); 2751 } 2752 2753 /* Restore RF_ENV control type. */ 2754 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2755 reg &= ~(0x10 << off) | (type << off); 2756 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2757 2758 /* Cache RF register CHNLBW. */ 2759 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2760 } 2761 2762 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2763 URTWN_CHIP_UMC_A_CUT) { 2764 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2765 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2766 } 2767} 2768 2769static void 2770urtwn_cam_init(struct urtwn_softc *sc) 2771{ 2772 /* Invalidate all CAM entries. */ 2773 urtwn_write_4(sc, R92C_CAMCMD, 2774 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2775} 2776 2777static void 2778urtwn_pa_bias_init(struct urtwn_softc *sc) 2779{ 2780 uint8_t reg; 2781 int i; 2782 2783 for (i = 0; i < sc->nrxchains; i++) { 2784 if (sc->pa_setting & (1 << i)) 2785 continue; 2786 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2787 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2788 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2789 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2790 } 2791 if (!(sc->pa_setting & 0x10)) { 2792 reg = urtwn_read_1(sc, 0x16); 2793 reg = (reg & ~0xf0) | 0x90; 2794 urtwn_write_1(sc, 0x16, reg); 2795 } 2796} 2797 2798static void 2799urtwn_rxfilter_init(struct urtwn_softc *sc) 2800{ 2801 /* Initialize Rx filter. */ 2802 /* TODO: use better filter for monitor mode. */ 2803 urtwn_write_4(sc, R92C_RCR, 2804 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2805 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2806 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2807 /* Accept all multicast frames. */ 2808 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2809 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2810 /* Accept all management frames. */ 2811 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2812 /* Reject all control frames. */ 2813 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2814 /* Accept all data frames. */ 2815 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2816} 2817 2818static void 2819urtwn_edca_init(struct urtwn_softc *sc) 2820{ 2821 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2822 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2823 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2824 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2825 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2826 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2827 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2828 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2829} 2830 2831static void 2832urtwn_write_txpower(struct urtwn_softc *sc, int chain, 2833 uint16_t power[URTWN_RIDX_COUNT]) 2834{ 2835 uint32_t reg; 2836 2837 /* Write per-CCK rate Tx power. */ 2838 if (chain == 0) { 2839 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2840 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2841 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2842 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2843 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2844 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2845 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2846 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2847 } else { 2848 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2849 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2850 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2851 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2852 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2853 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2854 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2855 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2856 } 2857 /* Write per-OFDM rate Tx power. */ 2858 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2859 SM(R92C_TXAGC_RATE06, power[ 4]) | 2860 SM(R92C_TXAGC_RATE09, power[ 5]) | 2861 SM(R92C_TXAGC_RATE12, power[ 6]) | 2862 SM(R92C_TXAGC_RATE18, power[ 7])); 2863 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2864 SM(R92C_TXAGC_RATE24, power[ 8]) | 2865 SM(R92C_TXAGC_RATE36, power[ 9]) | 2866 SM(R92C_TXAGC_RATE48, power[10]) | 2867 SM(R92C_TXAGC_RATE54, power[11])); 2868 /* Write per-MCS Tx power. */ 2869 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2870 SM(R92C_TXAGC_MCS00, power[12]) | 2871 SM(R92C_TXAGC_MCS01, power[13]) | 2872 SM(R92C_TXAGC_MCS02, power[14]) | 2873 SM(R92C_TXAGC_MCS03, power[15])); 2874 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2875 SM(R92C_TXAGC_MCS04, power[16]) | 2876 SM(R92C_TXAGC_MCS05, power[17]) | 2877 SM(R92C_TXAGC_MCS06, power[18]) | 2878 SM(R92C_TXAGC_MCS07, power[19])); 2879 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2880 SM(R92C_TXAGC_MCS08, power[20]) | 2881 SM(R92C_TXAGC_MCS09, power[21]) | 2882 SM(R92C_TXAGC_MCS10, power[22]) | 2883 SM(R92C_TXAGC_MCS11, power[23])); 2884 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2885 SM(R92C_TXAGC_MCS12, power[24]) | 2886 SM(R92C_TXAGC_MCS13, power[25]) | 2887 SM(R92C_TXAGC_MCS14, power[26]) | 2888 SM(R92C_TXAGC_MCS15, power[27])); 2889} 2890 2891static void 2892urtwn_get_txpower(struct urtwn_softc *sc, int chain, 2893 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2894 uint16_t power[URTWN_RIDX_COUNT]) 2895{ 2896 struct ieee80211com *ic = &sc->sc_ic; 2897 struct r92c_rom *rom = &sc->rom; 2898 uint16_t cckpow, ofdmpow, htpow, diff, max; 2899 const struct urtwn_txpwr *base; 2900 int ridx, chan, group; 2901 2902 /* Determine channel group. */ 2903 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2904 if (chan <= 3) 2905 group = 0; 2906 else if (chan <= 9) 2907 group = 1; 2908 else 2909 group = 2; 2910 2911 /* Get original Tx power based on board type and RF chain. */ 2912 if (!(sc->chip & URTWN_CHIP_92C)) { 2913 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2914 base = &rtl8188ru_txagc[chain]; 2915 else 2916 base = &rtl8192cu_txagc[chain]; 2917 } else 2918 base = &rtl8192cu_txagc[chain]; 2919 2920 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2921 if (sc->regulatory == 0) { 2922 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 2923 power[ridx] = base->pwr[0][ridx]; 2924 } 2925 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 2926 if (sc->regulatory == 3) { 2927 power[ridx] = base->pwr[0][ridx]; 2928 /* Apply vendor limits. */ 2929 if (extc != NULL) 2930 max = rom->ht40_max_pwr[group]; 2931 else 2932 max = rom->ht20_max_pwr[group]; 2933 max = (max >> (chain * 4)) & 0xf; 2934 if (power[ridx] > max) 2935 power[ridx] = max; 2936 } else if (sc->regulatory == 1) { 2937 if (extc == NULL) 2938 power[ridx] = base->pwr[group][ridx]; 2939 } else if (sc->regulatory != 2) 2940 power[ridx] = base->pwr[0][ridx]; 2941 } 2942 2943 /* Compute per-CCK rate Tx power. */ 2944 cckpow = rom->cck_tx_pwr[chain][group]; 2945 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 2946 power[ridx] += cckpow; 2947 if (power[ridx] > R92C_MAX_TX_PWR) 2948 power[ridx] = R92C_MAX_TX_PWR; 2949 } 2950 2951 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2952 if (sc->ntxchains > 1) { 2953 /* Apply reduction for 2 spatial streams. */ 2954 diff = rom->ht40_2s_tx_pwr_diff[group]; 2955 diff = (diff >> (chain * 4)) & 0xf; 2956 htpow = (htpow > diff) ? htpow - diff : 0; 2957 } 2958 2959 /* Compute per-OFDM rate Tx power. */ 2960 diff = rom->ofdm_tx_pwr_diff[group]; 2961 diff = (diff >> (chain * 4)) & 0xf; 2962 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2963 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 2964 power[ridx] += ofdmpow; 2965 if (power[ridx] > R92C_MAX_TX_PWR) 2966 power[ridx] = R92C_MAX_TX_PWR; 2967 } 2968 2969 /* Compute per-MCS Tx power. */ 2970 if (extc == NULL) { 2971 diff = rom->ht20_tx_pwr_diff[group]; 2972 diff = (diff >> (chain * 4)) & 0xf; 2973 htpow += diff; /* HT40->HT20 correction. */ 2974 } 2975 for (ridx = 12; ridx <= 27; ridx++) { 2976 power[ridx] += htpow; 2977 if (power[ridx] > R92C_MAX_TX_PWR) 2978 power[ridx] = R92C_MAX_TX_PWR; 2979 } 2980#ifdef URTWN_DEBUG 2981 if (urtwn_debug >= 4) { 2982 /* Dump per-rate Tx power values. */ 2983 printf("Tx power for chain %d:\n", chain); 2984 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 2985 printf("Rate %d = %u\n", ridx, power[ridx]); 2986 } 2987#endif 2988} 2989 2990static void 2991urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 2992 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2993 uint16_t power[URTWN_RIDX_COUNT]) 2994{ 2995 struct ieee80211com *ic = &sc->sc_ic; 2996 uint16_t cckpow, ofdmpow, bw20pow, htpow; 2997 const struct urtwn_r88e_txpwr *base; 2998 int ridx, chan, group; 2999 3000 /* Determine channel group. */ 3001 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3002 if (chan <= 2) 3003 group = 0; 3004 else if (chan <= 5) 3005 group = 1; 3006 else if (chan <= 8) 3007 group = 2; 3008 else if (chan <= 11) 3009 group = 3; 3010 else if (chan <= 13) 3011 group = 4; 3012 else 3013 group = 5; 3014 3015 /* Get original Tx power based on board type and RF chain. */ 3016 base = &rtl8188eu_txagc[chain]; 3017 3018 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3019 if (sc->regulatory == 0) { 3020 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3021 power[ridx] = base->pwr[0][ridx]; 3022 } 3023 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3024 if (sc->regulatory == 3) 3025 power[ridx] = base->pwr[0][ridx]; 3026 else if (sc->regulatory == 1) { 3027 if (extc == NULL) 3028 power[ridx] = base->pwr[group][ridx]; 3029 } else if (sc->regulatory != 2) 3030 power[ridx] = base->pwr[0][ridx]; 3031 } 3032 3033 /* Compute per-CCK rate Tx power. */ 3034 cckpow = sc->cck_tx_pwr[group]; 3035 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3036 power[ridx] += cckpow; 3037 if (power[ridx] > R92C_MAX_TX_PWR) 3038 power[ridx] = R92C_MAX_TX_PWR; 3039 } 3040 3041 htpow = sc->ht40_tx_pwr[group]; 3042 3043 /* Compute per-OFDM rate Tx power. */ 3044 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3045 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3046 power[ridx] += ofdmpow; 3047 if (power[ridx] > R92C_MAX_TX_PWR) 3048 power[ridx] = R92C_MAX_TX_PWR; 3049 } 3050 3051 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3052 for (ridx = 12; ridx <= 27; ridx++) { 3053 power[ridx] += bw20pow; 3054 if (power[ridx] > R92C_MAX_TX_PWR) 3055 power[ridx] = R92C_MAX_TX_PWR; 3056 } 3057} 3058 3059static void 3060urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3061 struct ieee80211_channel *extc) 3062{ 3063 uint16_t power[URTWN_RIDX_COUNT]; 3064 int i; 3065 3066 for (i = 0; i < sc->ntxchains; i++) { 3067 /* Compute per-rate Tx power values. */ 3068 if (sc->chip & URTWN_CHIP_88E) 3069 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3070 else 3071 urtwn_get_txpower(sc, i, c, extc, power); 3072 /* Write per-rate Tx power values to hardware. */ 3073 urtwn_write_txpower(sc, i, power); 3074 } 3075} 3076 3077static void 3078urtwn_scan_start(struct ieee80211com *ic) 3079{ 3080 /* XXX do nothing? */ 3081} 3082 3083static void 3084urtwn_scan_end(struct ieee80211com *ic) 3085{ 3086 /* XXX do nothing? */ 3087} 3088 3089static void 3090urtwn_set_channel(struct ieee80211com *ic) 3091{ 3092 struct urtwn_softc *sc = ic->ic_softc; 3093 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3094 3095 URTWN_LOCK(sc); 3096 if (vap->iv_state == IEEE80211_S_SCAN) { 3097 /* Make link LED blink during scan. */ 3098 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3099 } 3100 urtwn_set_chan(sc, ic->ic_curchan, NULL); 3101 URTWN_UNLOCK(sc); 3102} 3103 3104static void 3105urtwn_update_mcast(struct ieee80211com *ic) 3106{ 3107 /* XXX do nothing? */ 3108} 3109 3110static void 3111urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3112 struct ieee80211_channel *extc) 3113{ 3114 struct ieee80211com *ic = &sc->sc_ic; 3115 uint32_t reg; 3116 u_int chan; 3117 int i; 3118 3119 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3120 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3121 device_printf(sc->sc_dev, 3122 "%s: invalid channel %x\n", __func__, chan); 3123 return; 3124 } 3125 3126 /* Set Tx power for this new channel. */ 3127 urtwn_set_txpower(sc, c, extc); 3128 3129 for (i = 0; i < sc->nrxchains; i++) { 3130 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3131 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3132 } 3133#ifndef IEEE80211_NO_HT 3134 if (extc != NULL) { 3135 /* Is secondary channel below or above primary? */ 3136 int prichlo = c->ic_freq < extc->ic_freq; 3137 3138 urtwn_write_1(sc, R92C_BWOPMODE, 3139 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3140 3141 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3142 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3143 urtwn_write_1(sc, R92C_RRSR + 2, reg); 3144 3145 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3146 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3147 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3148 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3149 3150 /* Set CCK side band. */ 3151 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3152 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3153 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3154 3155 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3156 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3157 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3158 3159 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3160 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3161 ~R92C_FPGA0_ANAPARAM2_CBW20); 3162 3163 reg = urtwn_bb_read(sc, 0x818); 3164 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3165 urtwn_bb_write(sc, 0x818, reg); 3166 3167 /* Select 40MHz bandwidth. */ 3168 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3169 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3170 } else 3171#endif 3172 { 3173 urtwn_write_1(sc, R92C_BWOPMODE, 3174 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3175 3176 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3177 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3178 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3179 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3180 3181 if (!(sc->chip & URTWN_CHIP_88E)) { 3182 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3183 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3184 R92C_FPGA0_ANAPARAM2_CBW20); 3185 } 3186 3187 /* Select 20MHz bandwidth. */ 3188 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3189 (sc->rf_chnlbw[0] & ~0xfff) | chan | 3190 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3191 R92C_RF_CHNLBW_BW20)); 3192 } 3193} 3194 3195static void 3196urtwn_iq_calib(struct urtwn_softc *sc) 3197{ 3198 /* TODO */ 3199} 3200 3201static void 3202urtwn_lc_calib(struct urtwn_softc *sc) 3203{ 3204 uint32_t rf_ac[2]; 3205 uint8_t txmode; 3206 int i; 3207 3208 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3209 if ((txmode & 0x70) != 0) { 3210 /* Disable all continuous Tx. */ 3211 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3212 3213 /* Set RF mode to standby mode. */ 3214 for (i = 0; i < sc->nrxchains; i++) { 3215 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3216 urtwn_rf_write(sc, i, R92C_RF_AC, 3217 RW(rf_ac[i], R92C_RF_AC_MODE, 3218 R92C_RF_AC_MODE_STANDBY)); 3219 } 3220 } else { 3221 /* Block all Tx queues. */ 3222 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3223 } 3224 /* Start calibration. */ 3225 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3226 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3227 3228 /* Give calibration the time to complete. */ 3229 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3230 3231 /* Restore configuration. */ 3232 if ((txmode & 0x70) != 0) { 3233 /* Restore Tx mode. */ 3234 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3235 /* Restore RF mode. */ 3236 for (i = 0; i < sc->nrxchains; i++) 3237 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3238 } else { 3239 /* Unblock all Tx queues. */ 3240 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3241 } 3242} 3243 3244static void 3245urtwn_init(struct urtwn_softc *sc) 3246{ 3247 struct ieee80211com *ic = &sc->sc_ic; 3248 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3249 uint8_t macaddr[IEEE80211_ADDR_LEN]; 3250 uint32_t reg; 3251 int error; 3252 3253 URTWN_ASSERT_LOCKED(sc); 3254 3255 if (sc->sc_flags & URTWN_RUNNING) 3256 urtwn_stop(sc); 3257 3258 /* Init firmware commands ring. */ 3259 sc->fwcur = 0; 3260 3261 /* Allocate Tx/Rx buffers. */ 3262 error = urtwn_alloc_rx_list(sc); 3263 if (error != 0) 3264 goto fail; 3265 3266 error = urtwn_alloc_tx_list(sc); 3267 if (error != 0) 3268 goto fail; 3269 3270 /* Power on adapter. */ 3271 error = urtwn_power_on(sc); 3272 if (error != 0) 3273 goto fail; 3274 3275 /* Initialize DMA. */ 3276 error = urtwn_dma_init(sc); 3277 if (error != 0) 3278 goto fail; 3279 3280 /* Set info size in Rx descriptors (in 64-bit words). */ 3281 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3282 3283 /* Init interrupts. */ 3284 if (sc->chip & URTWN_CHIP_88E) { 3285 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3286 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3287 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3288 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3289 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3290 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3291 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3292 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3293 } else { 3294 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3295 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3296 } 3297 3298 /* Set MAC address. */ 3299 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3300 urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3301 3302 /* Set initial network type. */ 3303 urtwn_set_mode(sc, R92C_MSR_INFRA); 3304 3305 urtwn_rxfilter_init(sc); 3306 3307 /* Set response rate. */ 3308 reg = urtwn_read_4(sc, R92C_RRSR); 3309 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3310 urtwn_write_4(sc, R92C_RRSR, reg); 3311 3312 /* Set short/long retry limits. */ 3313 urtwn_write_2(sc, R92C_RL, 3314 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3315 3316 /* Initialize EDCA parameters. */ 3317 urtwn_edca_init(sc); 3318 3319 /* Setup rate fallback. */ 3320 if (!(sc->chip & URTWN_CHIP_88E)) { 3321 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3322 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3323 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3324 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3325 } 3326 3327 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3328 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3329 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3330 /* Set ACK timeout. */ 3331 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3332 3333 /* Setup USB aggregation. */ 3334 reg = urtwn_read_4(sc, R92C_TDECTRL); 3335 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3336 urtwn_write_4(sc, R92C_TDECTRL, reg); 3337 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3338 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3339 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3340 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3341 if (sc->chip & URTWN_CHIP_88E) 3342 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3343 else { 3344 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3345 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3346 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3347 R92C_USB_SPECIAL_OPTION_AGG_EN); 3348 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3349 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3350 } 3351 3352 /* Initialize beacon parameters. */ 3353 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3354 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3355 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3356 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3357 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3358 3359 if (!(sc->chip & URTWN_CHIP_88E)) { 3360 /* Setup AMPDU aggregation. */ 3361 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3362 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3363 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3364 3365 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3366 } 3367 3368 /* Load 8051 microcode. */ 3369 error = urtwn_load_firmware(sc); 3370 if (error != 0) 3371 goto fail; 3372 3373 /* Initialize MAC/BB/RF blocks. */ 3374 urtwn_mac_init(sc); 3375 urtwn_bb_init(sc); 3376 urtwn_rf_init(sc); 3377 3378 if (sc->chip & URTWN_CHIP_88E) { 3379 urtwn_write_2(sc, R92C_CR, 3380 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3381 R92C_CR_MACRXEN); 3382 } 3383 3384 /* Turn CCK and OFDM blocks on. */ 3385 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3386 reg |= R92C_RFMOD_CCK_EN; 3387 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3388 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3389 reg |= R92C_RFMOD_OFDM_EN; 3390 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3391 3392 /* Clear per-station keys table. */ 3393 urtwn_cam_init(sc); 3394 3395 /* Enable hardware sequence numbering. */ 3396 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3397 3398 /* Perform LO and IQ calibrations. */ 3399 urtwn_iq_calib(sc); 3400 /* Perform LC calibration. */ 3401 urtwn_lc_calib(sc); 3402 3403 /* Fix USB interference issue. */ 3404 if (!(sc->chip & URTWN_CHIP_88E)) { 3405 urtwn_write_1(sc, 0xfe40, 0xe0); 3406 urtwn_write_1(sc, 0xfe41, 0x8d); 3407 urtwn_write_1(sc, 0xfe42, 0x80); 3408 3409 urtwn_pa_bias_init(sc); 3410 } 3411 3412 /* Initialize GPIO setting. */ 3413 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3414 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3415 3416 /* Fix for lower temperature. */ 3417 if (!(sc->chip & URTWN_CHIP_88E)) 3418 urtwn_write_1(sc, 0x15, 0xe9); 3419 3420 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3421 3422 sc->sc_flags |= URTWN_RUNNING; 3423 3424 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3425fail: 3426 return; 3427} 3428 3429static void 3430urtwn_stop(struct urtwn_softc *sc) 3431{ 3432 3433 URTWN_ASSERT_LOCKED(sc); 3434 sc->sc_flags &= ~URTWN_RUNNING; 3435 callout_stop(&sc->sc_watchdog_ch); 3436 urtwn_abort_xfers(sc); 3437 3438 urtwn_drain_mbufq(sc); 3439} 3440 3441static void 3442urtwn_abort_xfers(struct urtwn_softc *sc) 3443{ 3444 int i; 3445 3446 URTWN_ASSERT_LOCKED(sc); 3447 3448 /* abort any pending transfers */ 3449 for (i = 0; i < URTWN_N_TRANSFER; i++) 3450 usbd_transfer_stop(sc->sc_xfer[i]); 3451} 3452 3453static int 3454urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3455 const struct ieee80211_bpf_params *params) 3456{ 3457 struct ieee80211com *ic = ni->ni_ic; 3458 struct urtwn_softc *sc = ic->ic_softc; 3459 struct urtwn_data *bf; 3460 3461 /* prevent management frames from being sent if we're not ready */ 3462 if (!(sc->sc_flags & URTWN_RUNNING)) { 3463 m_freem(m); 3464 return (ENETDOWN); 3465 } 3466 URTWN_LOCK(sc); 3467 bf = urtwn_getbuf(sc); 3468 if (bf == NULL) { 3469 m_freem(m); 3470 URTWN_UNLOCK(sc); 3471 return (ENOBUFS); 3472 } 3473 3474 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3475 m_freem(m); 3476 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3477 URTWN_UNLOCK(sc); 3478 return (EIO); 3479 } 3480 sc->sc_txtimer = 5; 3481 URTWN_UNLOCK(sc); 3482 3483 return (0); 3484} 3485 3486static void 3487urtwn_ms_delay(struct urtwn_softc *sc) 3488{ 3489 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3490} 3491 3492static device_method_t urtwn_methods[] = { 3493 /* Device interface */ 3494 DEVMETHOD(device_probe, urtwn_match), 3495 DEVMETHOD(device_attach, urtwn_attach), 3496 DEVMETHOD(device_detach, urtwn_detach), 3497 3498 DEVMETHOD_END 3499}; 3500 3501static driver_t urtwn_driver = { 3502 "urtwn", 3503 urtwn_methods, 3504 sizeof(struct urtwn_softc) 3505}; 3506 3507static devclass_t urtwn_devclass; 3508 3509DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3510MODULE_DEPEND(urtwn, usb, 1, 1, 1); 3511MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3512MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3513MODULE_VERSION(urtwn, 1); 3514