if_urtwn.c revision 260444
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19#include <sys/cdefs.h> 20__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 260444 2014-01-08 08:06:56Z kevlo $"); 21 22/* 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188RU/RTL8192CU. 24 */ 25 26#include <sys/param.h> 27#include <sys/sockio.h> 28#include <sys/sysctl.h> 29#include <sys/lock.h> 30#include <sys/mutex.h> 31#include <sys/mbuf.h> 32#include <sys/kernel.h> 33#include <sys/socket.h> 34#include <sys/systm.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37#include <sys/bus.h> 38#include <sys/endian.h> 39#include <sys/linker.h> 40#include <sys/firmware.h> 41#include <sys/kdb.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <sys/rman.h> 46 47#include <net/bpf.h> 48#include <net/if.h> 49#include <net/if_var.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55 56#include <netinet/in.h> 57#include <netinet/in_systm.h> 58#include <netinet/in_var.h> 59#include <netinet/if_ether.h> 60#include <netinet/ip.h> 61 62#include <net80211/ieee80211_var.h> 63#include <net80211/ieee80211_regdomain.h> 64#include <net80211/ieee80211_radiotap.h> 65#include <net80211/ieee80211_ratectl.h> 66 67#include <dev/usb/usb.h> 68#include <dev/usb/usbdi.h> 69#include "usbdevs.h" 70 71#define USB_DEBUG_VAR urtwn_debug 72#include <dev/usb/usb_debug.h> 73 74#include <dev/usb/wlan/if_urtwnreg.h> 75 76#ifdef USB_DEBUG 77static int urtwn_debug = 0; 78 79SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 80SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RW, &urtwn_debug, 0, 81 "Debug level"); 82#endif 83 84#define URTWN_RSSI(r) (r) - 110 85#define IEEE80211_HAS_ADDR4(wh) \ 86 (((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) 87 88/* various supported device vendors/products */ 89static const STRUCT_USB_HOST_ID urtwn_devs[] = { 90#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 91 URTWN_DEV(ABOCOM, RTL8188CU_1), 92 URTWN_DEV(ABOCOM, RTL8188CU_2), 93 URTWN_DEV(ABOCOM, RTL8192CU), 94 URTWN_DEV(ASUS, RTL8192CU), 95 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 96 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 97 URTWN_DEV(AZUREWAVE, RTL8188CU), 98 URTWN_DEV(BELKIN, F7D2102), 99 URTWN_DEV(BELKIN, RTL8188CU), 100 URTWN_DEV(BELKIN, RTL8192CU), 101 URTWN_DEV(CHICONY, RTL8188CUS_1), 102 URTWN_DEV(CHICONY, RTL8188CUS_2), 103 URTWN_DEV(CHICONY, RTL8188CUS_3), 104 URTWN_DEV(CHICONY, RTL8188CUS_4), 105 URTWN_DEV(CHICONY, RTL8188CUS_5), 106 URTWN_DEV(COREGA, RTL8192CU), 107 URTWN_DEV(DLINK, RTL8188CU), 108 URTWN_DEV(DLINK, RTL8192CU_1), 109 URTWN_DEV(DLINK, RTL8192CU_2), 110 URTWN_DEV(DLINK, RTL8192CU_3), 111 URTWN_DEV(DLINK, DWA131B), 112 URTWN_DEV(EDIMAX, EW7811UN), 113 URTWN_DEV(EDIMAX, RTL8192CU), 114 URTWN_DEV(FEIXUN, RTL8188CU), 115 URTWN_DEV(FEIXUN, RTL8192CU), 116 URTWN_DEV(GUILLEMOT, HWNUP150), 117 URTWN_DEV(HAWKING, RTL8192CU), 118 URTWN_DEV(HP3, RTL8188CU), 119 URTWN_DEV(NETGEAR, WNA1000M), 120 URTWN_DEV(NETGEAR, RTL8192CU), 121 URTWN_DEV(NETGEAR4, RTL8188CU), 122 URTWN_DEV(NOVATECH, RTL8188CU), 123 URTWN_DEV(PLANEX2, RTL8188CU_1), 124 URTWN_DEV(PLANEX2, RTL8188CU_2), 125 URTWN_DEV(PLANEX2, RTL8188CU_3), 126 URTWN_DEV(PLANEX2, RTL8188CU_4), 127 URTWN_DEV(PLANEX2, RTL8188CUS), 128 URTWN_DEV(PLANEX2, RTL8192CU), 129 URTWN_DEV(REALTEK, RTL8188CE_0), 130 URTWN_DEV(REALTEK, RTL8188CE_1), 131 URTWN_DEV(REALTEK, RTL8188CTV), 132 URTWN_DEV(REALTEK, RTL8188CU_0), 133 URTWN_DEV(REALTEK, RTL8188CU_1), 134 URTWN_DEV(REALTEK, RTL8188CU_2), 135 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 136 URTWN_DEV(REALTEK, RTL8188CUS), 137 URTWN_DEV(REALTEK, RTL8188RU_1), 138 URTWN_DEV(REALTEK, RTL8188RU_2), 139 URTWN_DEV(REALTEK, RTL8191CU), 140 URTWN_DEV(REALTEK, RTL8192CE), 141 URTWN_DEV(REALTEK, RTL8192CU), 142 URTWN_DEV(REALTEK, RTL8188CU_0), 143 URTWN_DEV(SITECOMEU, RTL8188CU_1), 144 URTWN_DEV(SITECOMEU, RTL8188CU_2), 145 URTWN_DEV(SITECOMEU, RTL8192CU), 146 URTWN_DEV(TRENDNET, RTL8188CU), 147 URTWN_DEV(TRENDNET, RTL8192CU), 148 URTWN_DEV(ZYXEL, RTL8192CU), 149#undef URTWN_DEV 150}; 151 152static device_probe_t urtwn_match; 153static device_attach_t urtwn_attach; 154static device_detach_t urtwn_detach; 155 156static usb_callback_t urtwn_bulk_tx_callback; 157static usb_callback_t urtwn_bulk_rx_callback; 158 159static usb_error_t urtwn_do_request(struct urtwn_softc *sc, 160 struct usb_device_request *req, void *data); 161static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 162 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 163 const uint8_t [IEEE80211_ADDR_LEN], 164 const uint8_t [IEEE80211_ADDR_LEN]); 165static void urtwn_vap_delete(struct ieee80211vap *); 166static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 167 int *); 168static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 169 int *, int8_t *); 170static void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 171static int urtwn_alloc_list(struct urtwn_softc *, 172 struct urtwn_data[], int, int); 173static int urtwn_alloc_rx_list(struct urtwn_softc *); 174static int urtwn_alloc_tx_list(struct urtwn_softc *); 175static void urtwn_free_tx_list(struct urtwn_softc *); 176static void urtwn_free_rx_list(struct urtwn_softc *); 177static void urtwn_free_list(struct urtwn_softc *, 178 struct urtwn_data data[], int); 179static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 180static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 181static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 182 uint8_t *, int); 183static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 184static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 185static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 186static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 187 uint8_t *, int); 188static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 189static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 190static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 191static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 192 const void *, int); 193static void urtwn_rf_write(struct urtwn_softc *, int, uint8_t, 194 uint32_t); 195static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 196static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 197 uint32_t); 198static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 199static void urtwn_efuse_read(struct urtwn_softc *); 200static int urtwn_read_chipid(struct urtwn_softc *); 201static void urtwn_read_rom(struct urtwn_softc *); 202static int urtwn_ra_init(struct urtwn_softc *); 203static void urtwn_tsf_sync_enable(struct urtwn_softc *); 204static void urtwn_set_led(struct urtwn_softc *, int, int); 205static int urtwn_newstate(struct ieee80211vap *, 206 enum ieee80211_state, int); 207static void urtwn_watchdog(void *); 208static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 209static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 210static int urtwn_tx_start(struct urtwn_softc *, 211 struct ieee80211_node *, struct mbuf *, 212 struct urtwn_data *); 213static void urtwn_start(struct ifnet *); 214static int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 215static int urtwn_power_on(struct urtwn_softc *); 216static int urtwn_llt_init(struct urtwn_softc *); 217static void urtwn_fw_reset(struct urtwn_softc *); 218static int urtwn_fw_loadpage(struct urtwn_softc *, int, 219 const uint8_t *, int); 220static int urtwn_load_firmware(struct urtwn_softc *); 221static int urtwn_dma_init(struct urtwn_softc *); 222static void urtwn_mac_init(struct urtwn_softc *); 223static void urtwn_bb_init(struct urtwn_softc *); 224static void urtwn_rf_init(struct urtwn_softc *); 225static void urtwn_cam_init(struct urtwn_softc *); 226static void urtwn_pa_bias_init(struct urtwn_softc *); 227static void urtwn_rxfilter_init(struct urtwn_softc *); 228static void urtwn_edca_init(struct urtwn_softc *); 229static void urtwn_write_txpower(struct urtwn_softc *, int, 230 uint16_t[]); 231static void urtwn_get_txpower(struct urtwn_softc *, int, 232 struct ieee80211_channel *, 233 struct ieee80211_channel *, uint16_t[]); 234static void urtwn_set_txpower(struct urtwn_softc *, 235 struct ieee80211_channel *, 236 struct ieee80211_channel *); 237static void urtwn_scan_start(struct ieee80211com *); 238static void urtwn_scan_end(struct ieee80211com *); 239static void urtwn_set_channel(struct ieee80211com *); 240static void urtwn_set_chan(struct urtwn_softc *, 241 struct ieee80211_channel *, 242 struct ieee80211_channel *); 243static void urtwn_update_mcast(struct ifnet *); 244static void urtwn_iq_calib(struct urtwn_softc *); 245static void urtwn_lc_calib(struct urtwn_softc *); 246static void urtwn_init(void *); 247static void urtwn_init_locked(void *); 248static void urtwn_stop(struct ifnet *, int); 249static void urtwn_stop_locked(struct ifnet *, int); 250static void urtwn_abort_xfers(struct urtwn_softc *); 251static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 252 const struct ieee80211_bpf_params *); 253 254/* Aliases. */ 255#define urtwn_bb_write urtwn_write_4 256#define urtwn_bb_read urtwn_read_4 257 258static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 259 [URTWN_BULK_RX] = { 260 .type = UE_BULK, 261 .endpoint = UE_ADDR_ANY, 262 .direction = UE_DIR_IN, 263 .bufsize = URTWN_RXBUFSZ, 264 .flags = { 265 .pipe_bof = 1, 266 .short_xfer_ok = 1 267 }, 268 .callback = urtwn_bulk_rx_callback, 269 }, 270 [URTWN_BULK_TX_BE] = { 271 .type = UE_BULK, 272 .endpoint = 0x03, 273 .direction = UE_DIR_OUT, 274 .bufsize = URTWN_TXBUFSZ, 275 .flags = { 276 .ext_buffer = 1, 277 .pipe_bof = 1, 278 .force_short_xfer = 1 279 }, 280 .callback = urtwn_bulk_tx_callback, 281 .timeout = URTWN_TX_TIMEOUT, /* ms */ 282 }, 283 [URTWN_BULK_TX_BK] = { 284 .type = UE_BULK, 285 .endpoint = 0x03, 286 .direction = UE_DIR_OUT, 287 .bufsize = URTWN_TXBUFSZ, 288 .flags = { 289 .ext_buffer = 1, 290 .pipe_bof = 1, 291 .force_short_xfer = 1, 292 }, 293 .callback = urtwn_bulk_tx_callback, 294 .timeout = URTWN_TX_TIMEOUT, /* ms */ 295 }, 296 [URTWN_BULK_TX_VI] = { 297 .type = UE_BULK, 298 .endpoint = 0x02, 299 .direction = UE_DIR_OUT, 300 .bufsize = URTWN_TXBUFSZ, 301 .flags = { 302 .ext_buffer = 1, 303 .pipe_bof = 1, 304 .force_short_xfer = 1 305 }, 306 .callback = urtwn_bulk_tx_callback, 307 .timeout = URTWN_TX_TIMEOUT, /* ms */ 308 }, 309 [URTWN_BULK_TX_VO] = { 310 .type = UE_BULK, 311 .endpoint = 0x02, 312 .direction = UE_DIR_OUT, 313 .bufsize = URTWN_TXBUFSZ, 314 .flags = { 315 .ext_buffer = 1, 316 .pipe_bof = 1, 317 .force_short_xfer = 1 318 }, 319 .callback = urtwn_bulk_tx_callback, 320 .timeout = URTWN_TX_TIMEOUT, /* ms */ 321 }, 322}; 323 324static int 325urtwn_match(device_t self) 326{ 327 struct usb_attach_arg *uaa = device_get_ivars(self); 328 329 if (uaa->usb_mode != USB_MODE_HOST) 330 return (ENXIO); 331 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 332 return (ENXIO); 333 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 334 return (ENXIO); 335 336 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 337} 338 339static int 340urtwn_attach(device_t self) 341{ 342 struct usb_attach_arg *uaa = device_get_ivars(self); 343 struct urtwn_softc *sc = device_get_softc(self); 344 struct ifnet *ifp; 345 struct ieee80211com *ic; 346 uint8_t iface_index, bands; 347 int error; 348 349 device_set_usb_desc(self); 350 sc->sc_udev = uaa->device; 351 sc->sc_dev = self; 352 353 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 354 MTX_NETWORK_LOCK, MTX_DEF); 355 callout_init(&sc->sc_watchdog_ch, 0); 356 357 iface_index = URTWN_IFACE_INDEX; 358 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 359 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 360 if (error) { 361 device_printf(self, "could not allocate USB transfers, " 362 "err=%s\n", usbd_errstr(error)); 363 goto detach; 364 } 365 366 URTWN_LOCK(sc); 367 368 error = urtwn_read_chipid(sc); 369 if (error) { 370 device_printf(sc->sc_dev, "unsupported test chip\n"); 371 URTWN_UNLOCK(sc); 372 goto detach; 373 } 374 375 /* Determine number of Tx/Rx chains. */ 376 if (sc->chip & URTWN_CHIP_92C) { 377 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 378 sc->nrxchains = 2; 379 } else { 380 sc->ntxchains = 1; 381 sc->nrxchains = 1; 382 } 383 urtwn_read_rom(sc); 384 385 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 386 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 387 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 388 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 389 "8188CUS", sc->ntxchains, sc->nrxchains); 390 391 URTWN_UNLOCK(sc); 392 393 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 394 if (ifp == NULL) { 395 device_printf(sc->sc_dev, "can not if_alloc()\n"); 396 goto detach; 397 } 398 ic = ifp->if_l2com; 399 400 ifp->if_softc = sc; 401 if_initname(ifp, "urtwn", device_get_unit(sc->sc_dev)); 402 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 403 ifp->if_init = urtwn_init; 404 ifp->if_ioctl = urtwn_ioctl; 405 ifp->if_start = urtwn_start; 406 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 407 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 408 IFQ_SET_READY(&ifp->if_snd); 409 410 ic->ic_ifp = ifp; 411 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 412 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 413 414 /* set device capabilities */ 415 ic->ic_caps = 416 IEEE80211_C_STA /* station mode */ 417 | IEEE80211_C_MONITOR /* monitor mode */ 418 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 419 | IEEE80211_C_SHSLOT /* short slot time supported */ 420 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 421 | IEEE80211_C_WPA /* 802.11i */ 422 ; 423 424 bands = 0; 425 setbit(&bands, IEEE80211_MODE_11B); 426 setbit(&bands, IEEE80211_MODE_11G); 427 ieee80211_init_channels(ic, NULL, &bands); 428 429 ieee80211_ifattach(ic, sc->sc_bssid); 430 ic->ic_raw_xmit = urtwn_raw_xmit; 431 ic->ic_scan_start = urtwn_scan_start; 432 ic->ic_scan_end = urtwn_scan_end; 433 ic->ic_set_channel = urtwn_set_channel; 434 435 ic->ic_vap_create = urtwn_vap_create; 436 ic->ic_vap_delete = urtwn_vap_delete; 437 ic->ic_update_mcast = urtwn_update_mcast; 438 439 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 440 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 441 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 442 URTWN_RX_RADIOTAP_PRESENT); 443 444 if (bootverbose) 445 ieee80211_announce(ic); 446 447 return (0); 448 449detach: 450 urtwn_detach(self); 451 return (ENXIO); /* failure */ 452} 453 454static int 455urtwn_detach(device_t self) 456{ 457 struct urtwn_softc *sc = device_get_softc(self); 458 struct ifnet *ifp = sc->sc_ifp; 459 struct ieee80211com *ic = ifp->if_l2com; 460 461 if (!device_is_attached(self)) 462 return (0); 463 464 urtwn_stop(ifp, 1); 465 466 callout_drain(&sc->sc_watchdog_ch); 467 468 /* stop all USB transfers */ 469 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 470 ieee80211_ifdetach(ic); 471 472 urtwn_free_tx_list(sc); 473 urtwn_free_rx_list(sc); 474 475 if_free(ifp); 476 mtx_destroy(&sc->sc_mtx); 477 478 return (0); 479} 480 481static void 482urtwn_free_tx_list(struct urtwn_softc *sc) 483{ 484 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 485} 486 487static void 488urtwn_free_rx_list(struct urtwn_softc *sc) 489{ 490 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 491} 492 493static void 494urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 495{ 496 int i; 497 498 for (i = 0; i < ndata; i++) { 499 struct urtwn_data *dp = &data[i]; 500 501 if (dp->buf != NULL) { 502 free(dp->buf, M_USBDEV); 503 dp->buf = NULL; 504 } 505 if (dp->ni != NULL) { 506 ieee80211_free_node(dp->ni); 507 dp->ni = NULL; 508 } 509 } 510} 511 512static usb_error_t 513urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 514 void *data) 515{ 516 usb_error_t err; 517 int ntries = 10; 518 519 URTWN_ASSERT_LOCKED(sc); 520 521 while (ntries--) { 522 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 523 req, data, 0, NULL, 250 /* ms */); 524 if (err == 0) 525 break; 526 527 DPRINTFN(1, "Control request failed, %s (retrying)\n", 528 usbd_errstr(err)); 529 usb_pause_mtx(&sc->sc_mtx, hz / 100); 530 } 531 return (err); 532} 533 534static struct ieee80211vap * 535urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 536 enum ieee80211_opmode opmode, int flags, 537 const uint8_t bssid[IEEE80211_ADDR_LEN], 538 const uint8_t mac[IEEE80211_ADDR_LEN]) 539{ 540 struct urtwn_vap *uvp; 541 struct ieee80211vap *vap; 542 543 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 544 return (NULL); 545 546 uvp = (struct urtwn_vap *) malloc(sizeof(struct urtwn_vap), 547 M_80211_VAP, M_NOWAIT | M_ZERO); 548 if (uvp == NULL) 549 return (NULL); 550 vap = &uvp->vap; 551 /* enable s/w bmiss handling for sta mode */ 552 553 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 554 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac) != 0) { 555 /* out of memory */ 556 free(uvp, M_80211_VAP); 557 return (NULL); 558 } 559 560 /* override state transition machine */ 561 uvp->newstate = vap->iv_newstate; 562 vap->iv_newstate = urtwn_newstate; 563 564 /* complete setup */ 565 ieee80211_vap_attach(vap, ieee80211_media_change, 566 ieee80211_media_status); 567 ic->ic_opmode = opmode; 568 return (vap); 569} 570 571static void 572urtwn_vap_delete(struct ieee80211vap *vap) 573{ 574 struct urtwn_vap *uvp = URTWN_VAP(vap); 575 576 ieee80211_vap_detach(vap); 577 free(uvp, M_80211_VAP); 578} 579 580static struct mbuf * 581urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 582{ 583 struct ifnet *ifp = sc->sc_ifp; 584 struct ieee80211com *ic = ifp->if_l2com; 585 struct ieee80211_frame *wh; 586 struct mbuf *m; 587 struct r92c_rx_stat *stat; 588 uint32_t rxdw0, rxdw3; 589 uint8_t rate; 590 int8_t rssi = 0; 591 int infosz; 592 593 /* 594 * don't pass packets to the ieee80211 framework if the driver isn't 595 * RUNNING. 596 */ 597 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 598 return (NULL); 599 600 stat = (struct r92c_rx_stat *)buf; 601 rxdw0 = le32toh(stat->rxdw0); 602 rxdw3 = le32toh(stat->rxdw3); 603 604 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 605 /* 606 * This should not happen since we setup our Rx filter 607 * to not receive these frames. 608 */ 609 ifp->if_ierrors++; 610 return (NULL); 611 } 612 613 rate = MS(rxdw3, R92C_RXDW3_RATE); 614 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 615 616 /* Get RSSI from PHY status descriptor if present. */ 617 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 618 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 619 /* Update our average RSSI. */ 620 urtwn_update_avgrssi(sc, rate, rssi); 621 /* 622 * Convert the RSSI to a range that will be accepted 623 * by net80211. 624 */ 625 rssi = URTWN_RSSI(rssi); 626 } 627 628 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 629 if (m == NULL) { 630 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 631 return (NULL); 632 } 633 634 /* Finalize mbuf. */ 635 m->m_pkthdr.rcvif = ifp; 636 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 637 memcpy(mtod(m, uint8_t *), wh, pktlen); 638 m->m_pkthdr.len = m->m_len = pktlen; 639 640 if (ieee80211_radiotap_active(ic)) { 641 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 642 643 tap->wr_flags = 0; 644 /* Map HW rate index to 802.11 rate. */ 645 if (!(rxdw3 & R92C_RXDW3_HT)) { 646 switch (rate) { 647 /* CCK. */ 648 case 0: tap->wr_rate = 2; break; 649 case 1: tap->wr_rate = 4; break; 650 case 2: tap->wr_rate = 11; break; 651 case 3: tap->wr_rate = 22; break; 652 /* OFDM. */ 653 case 4: tap->wr_rate = 12; break; 654 case 5: tap->wr_rate = 18; break; 655 case 6: tap->wr_rate = 24; break; 656 case 7: tap->wr_rate = 36; break; 657 case 8: tap->wr_rate = 48; break; 658 case 9: tap->wr_rate = 72; break; 659 case 10: tap->wr_rate = 96; break; 660 case 11: tap->wr_rate = 108; break; 661 } 662 } else if (rate >= 12) { /* MCS0~15. */ 663 /* Bit 7 set means HT MCS instead of rate. */ 664 tap->wr_rate = 0x80 | (rate - 12); 665 } 666 tap->wr_dbm_antsignal = rssi; 667 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 668 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 669 } 670 671 *rssi_p = rssi; 672 673 return (m); 674} 675 676static struct mbuf * 677urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 678 int8_t *nf) 679{ 680 struct urtwn_softc *sc = data->sc; 681 struct ifnet *ifp = sc->sc_ifp; 682 struct r92c_rx_stat *stat; 683 struct mbuf *m, *m0 = NULL, *prevm = NULL; 684 uint32_t rxdw0; 685 uint8_t *buf; 686 int len, totlen, pktlen, infosz, npkts; 687 688 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 689 690 if (len < sizeof(*stat)) { 691 ifp->if_ierrors++; 692 return (NULL); 693 } 694 695 buf = data->buf; 696 /* Get the number of encapsulated frames. */ 697 stat = (struct r92c_rx_stat *)buf; 698 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 699 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 700 701 /* Process all of them. */ 702 while (npkts-- > 0) { 703 if (len < sizeof(*stat)) 704 break; 705 stat = (struct r92c_rx_stat *)buf; 706 rxdw0 = le32toh(stat->rxdw0); 707 708 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 709 if (pktlen == 0) 710 break; 711 712 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 713 714 /* Make sure everything fits in xfer. */ 715 totlen = sizeof(*stat) + infosz + pktlen; 716 if (totlen > len) 717 break; 718 719 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 720 if (m0 == NULL) 721 m0 = m; 722 if (prevm == NULL) 723 prevm = m; 724 else { 725 prevm->m_next = m; 726 prevm = m; 727 } 728 729 /* Next chunk is 128-byte aligned. */ 730 totlen = (totlen + 127) & ~127; 731 buf += totlen; 732 len -= totlen; 733 } 734 735 return (m0); 736} 737 738static void 739urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 740{ 741 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 742 struct ifnet *ifp = sc->sc_ifp; 743 struct ieee80211com *ic = ifp->if_l2com; 744 struct ieee80211_frame *wh; 745 struct ieee80211_node *ni; 746 struct mbuf *m = NULL, *next; 747 struct urtwn_data *data; 748 int8_t nf; 749 int rssi = 1; 750 751 URTWN_ASSERT_LOCKED(sc); 752 753 switch (USB_GET_STATE(xfer)) { 754 case USB_ST_TRANSFERRED: 755 data = STAILQ_FIRST(&sc->sc_rx_active); 756 if (data == NULL) 757 goto tr_setup; 758 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 759 m = urtwn_rxeof(xfer, data, &rssi, &nf); 760 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 761 /* FALLTHROUGH */ 762 case USB_ST_SETUP: 763tr_setup: 764 data = STAILQ_FIRST(&sc->sc_rx_inactive); 765 if (data == NULL) { 766 KASSERT(m == NULL, ("mbuf isn't NULL")); 767 return; 768 } 769 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 770 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 771 usbd_xfer_set_frame_data(xfer, 0, data->buf, 772 usbd_xfer_max_len(xfer)); 773 usbd_transfer_submit(xfer); 774 775 /* 776 * To avoid LOR we should unlock our private mutex here to call 777 * ieee80211_input() because here is at the end of a USB 778 * callback and safe to unlock. 779 */ 780 URTWN_UNLOCK(sc); 781 while (m != NULL) { 782 next = m->m_next; 783 m->m_next = NULL; 784 wh = mtod(m, struct ieee80211_frame *); 785 ni = ieee80211_find_rxnode(ic, 786 (struct ieee80211_frame_min *)wh); 787 nf = URTWN_NOISE_FLOOR; 788 if (ni != NULL) { 789 (void)ieee80211_input(ni, m, rssi, nf); 790 ieee80211_free_node(ni); 791 } else 792 (void)ieee80211_input_all(ic, m, rssi, nf); 793 m = next; 794 } 795 URTWN_LOCK(sc); 796 break; 797 default: 798 /* needs it to the inactive queue due to a error. */ 799 data = STAILQ_FIRST(&sc->sc_rx_active); 800 if (data != NULL) { 801 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 802 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 803 } 804 if (error != USB_ERR_CANCELLED) { 805 usbd_xfer_set_stall(xfer); 806 ifp->if_ierrors++; 807 goto tr_setup; 808 } 809 break; 810 } 811} 812 813static void 814urtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 815{ 816 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 817 struct ifnet *ifp = sc->sc_ifp; 818 struct mbuf *m; 819 820 URTWN_ASSERT_LOCKED(sc); 821 822 /* 823 * Do any tx complete callback. Note this must be done before releasing 824 * the node reference. 825 */ 826 if (data->m) { 827 m = data->m; 828 if (m->m_flags & M_TXCB) { 829 /* XXX status? */ 830 ieee80211_process_callback(data->ni, m, 0); 831 } 832 m_freem(m); 833 data->m = NULL; 834 } 835 if (data->ni) { 836 ieee80211_free_node(data->ni); 837 data->ni = NULL; 838 } 839 sc->sc_txtimer = 0; 840 ifp->if_opackets++; 841 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 842} 843 844static void 845urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 846{ 847 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 848 struct ifnet *ifp = sc->sc_ifp; 849 struct urtwn_data *data; 850 851 URTWN_ASSERT_LOCKED(sc); 852 853 switch (USB_GET_STATE(xfer)){ 854 case USB_ST_TRANSFERRED: 855 data = STAILQ_FIRST(&sc->sc_tx_active); 856 if (data == NULL) 857 goto tr_setup; 858 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 859 urtwn_txeof(xfer, data); 860 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 861 /* FALLTHROUGH */ 862 case USB_ST_SETUP: 863tr_setup: 864 data = STAILQ_FIRST(&sc->sc_tx_pending); 865 if (data == NULL) { 866 DPRINTF("%s: empty pending queue\n", __func__); 867 return; 868 } 869 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 870 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 871 872 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 873 usbd_transfer_submit(xfer); 874 875 URTWN_UNLOCK(sc); 876 urtwn_start(ifp); 877 URTWN_LOCK(sc); 878 break; 879 default: 880 data = STAILQ_FIRST(&sc->sc_tx_active); 881 if (data == NULL) 882 goto tr_setup; 883 if (data->ni != NULL) { 884 ieee80211_free_node(data->ni); 885 data->ni = NULL; 886 ifp->if_oerrors++; 887 } 888 if (error != USB_ERR_CANCELLED) { 889 usbd_xfer_set_stall(xfer); 890 goto tr_setup; 891 } 892 break; 893 } 894} 895 896static struct urtwn_data * 897_urtwn_getbuf(struct urtwn_softc *sc) 898{ 899 struct urtwn_data *bf; 900 901 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 902 if (bf != NULL) 903 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 904 else 905 bf = NULL; 906 if (bf == NULL) 907 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 908 return (bf); 909} 910 911static struct urtwn_data * 912urtwn_getbuf(struct urtwn_softc *sc) 913{ 914 struct urtwn_data *bf; 915 916 URTWN_ASSERT_LOCKED(sc); 917 918 bf = _urtwn_getbuf(sc); 919 if (bf == NULL) { 920 struct ifnet *ifp = sc->sc_ifp; 921 DPRINTF("%s: stop queue\n", __func__); 922 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 923 } 924 return (bf); 925} 926 927static int 928urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 929 int len) 930{ 931 usb_device_request_t req; 932 933 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 934 req.bRequest = R92C_REQ_REGS; 935 USETW(req.wValue, addr); 936 USETW(req.wIndex, 0); 937 USETW(req.wLength, len); 938 return (urtwn_do_request(sc, &req, buf)); 939} 940 941static void 942urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 943{ 944 urtwn_write_region_1(sc, addr, &val, 1); 945} 946 947 948static void 949urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 950{ 951 val = htole16(val); 952 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 953} 954 955static void 956urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 957{ 958 val = htole32(val); 959 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 960} 961 962static int 963urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 964 int len) 965{ 966 usb_device_request_t req; 967 968 req.bmRequestType = UT_READ_VENDOR_DEVICE; 969 req.bRequest = R92C_REQ_REGS; 970 USETW(req.wValue, addr); 971 USETW(req.wIndex, 0); 972 USETW(req.wLength, len); 973 return (urtwn_do_request(sc, &req, buf)); 974} 975 976static uint8_t 977urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 978{ 979 uint8_t val; 980 981 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 982 return (0xff); 983 return (val); 984} 985 986static uint16_t 987urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 988{ 989 uint16_t val; 990 991 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 992 return (0xffff); 993 return (le16toh(val)); 994} 995 996static uint32_t 997urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 998{ 999 uint32_t val; 1000 1001 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1002 return (0xffffffff); 1003 return (le32toh(val)); 1004} 1005 1006static int 1007urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1008{ 1009 struct r92c_fw_cmd cmd; 1010 int ntries; 1011 1012 /* Wait for current FW box to be empty. */ 1013 for (ntries = 0; ntries < 100; ntries++) { 1014 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1015 break; 1016 DELAY(1); 1017 } 1018 if (ntries == 100) { 1019 device_printf(sc->sc_dev, 1020 "could not send firmware command\n"); 1021 return (ETIMEDOUT); 1022 } 1023 memset(&cmd, 0, sizeof(cmd)); 1024 cmd.id = id; 1025 if (len > 3) 1026 cmd.id |= R92C_CMD_FLAG_EXT; 1027 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1028 memcpy(cmd.msg, buf, len); 1029 1030 /* Write the first word last since that will trigger the FW. */ 1031 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1032 (uint8_t *)&cmd + 4, 2); 1033 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1034 (uint8_t *)&cmd + 0, 4); 1035 1036 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1037 return (0); 1038} 1039 1040static void 1041urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1042{ 1043 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1044 SM(R92C_LSSI_PARAM_ADDR, addr) | 1045 SM(R92C_LSSI_PARAM_DATA, val)); 1046} 1047 1048static uint32_t 1049urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1050{ 1051 uint32_t reg[R92C_MAX_CHAINS], val; 1052 1053 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1054 if (chain != 0) 1055 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1056 1057 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1058 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1059 DELAY(1000); 1060 1061 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1062 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1063 R92C_HSSI_PARAM2_READ_EDGE); 1064 DELAY(1000); 1065 1066 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1067 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1068 DELAY(1000); 1069 1070 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1071 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1072 else 1073 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1074 return (MS(val, R92C_LSSI_READBACK_DATA)); 1075} 1076 1077static int 1078urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1079{ 1080 int ntries; 1081 1082 urtwn_write_4(sc, R92C_LLT_INIT, 1083 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1084 SM(R92C_LLT_INIT_ADDR, addr) | 1085 SM(R92C_LLT_INIT_DATA, data)); 1086 /* Wait for write operation to complete. */ 1087 for (ntries = 0; ntries < 20; ntries++) { 1088 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1089 R92C_LLT_INIT_OP_NO_ACTIVE) 1090 return (0); 1091 DELAY(5); 1092 } 1093 return (ETIMEDOUT); 1094} 1095 1096static uint8_t 1097urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1098{ 1099 uint32_t reg; 1100 int ntries; 1101 1102 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1103 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1104 reg &= ~R92C_EFUSE_CTRL_VALID; 1105 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1106 /* Wait for read operation to complete. */ 1107 for (ntries = 0; ntries < 100; ntries++) { 1108 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1109 if (reg & R92C_EFUSE_CTRL_VALID) 1110 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1111 DELAY(5); 1112 } 1113 device_printf(sc->sc_dev, 1114 "could not read efuse byte at address 0x%x\n", addr); 1115 return (0xff); 1116} 1117 1118static void 1119urtwn_efuse_read(struct urtwn_softc *sc) 1120{ 1121 uint8_t *rom = (uint8_t *)&sc->rom; 1122 uint16_t addr = 0; 1123 uint32_t reg; 1124 uint8_t off, msk; 1125 int i; 1126 1127 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1128 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1129 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1130 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1131 } 1132 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1133 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1134 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1135 reg | R92C_SYS_FUNC_EN_ELDR); 1136 } 1137 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1138 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1139 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1140 urtwn_write_2(sc, R92C_SYS_CLKR, 1141 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1142 } 1143 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1144 while (addr < 512) { 1145 reg = urtwn_efuse_read_1(sc, addr); 1146 if (reg == 0xff) 1147 break; 1148 addr++; 1149 off = reg >> 4; 1150 msk = reg & 0xf; 1151 for (i = 0; i < 4; i++) { 1152 if (msk & (1 << i)) 1153 continue; 1154 rom[off * 8 + i * 2 + 0] = 1155 urtwn_efuse_read_1(sc, addr); 1156 addr++; 1157 rom[off * 8 + i * 2 + 1] = 1158 urtwn_efuse_read_1(sc, addr); 1159 addr++; 1160 } 1161 } 1162#ifdef URTWN_DEBUG 1163 if (urtwn_debug >= 2) { 1164 /* Dump ROM content. */ 1165 printf("\n"); 1166 for (i = 0; i < sizeof(sc->rom); i++) 1167 printf("%02x:", rom[i]); 1168 printf("\n"); 1169 } 1170#endif 1171} 1172 1173static int 1174urtwn_read_chipid(struct urtwn_softc *sc) 1175{ 1176 uint32_t reg; 1177 1178 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1179 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1180 return (EIO); 1181 1182 if (reg & R92C_SYS_CFG_TYPE_92C) { 1183 sc->chip |= URTWN_CHIP_92C; 1184 /* Check if it is a castrated 8192C. */ 1185 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1186 R92C_HPON_FSM_CHIP_BONDING_ID) == 1187 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1188 sc->chip |= URTWN_CHIP_92C_1T2R; 1189 } 1190 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1191 sc->chip |= URTWN_CHIP_UMC; 1192 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1193 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1194 } 1195 return (0); 1196} 1197 1198static void 1199urtwn_read_rom(struct urtwn_softc *sc) 1200{ 1201 struct r92c_rom *rom = &sc->rom; 1202 1203 /* Read full ROM image. */ 1204 urtwn_efuse_read(sc); 1205 1206 /* XXX Weird but this is what the vendor driver does. */ 1207 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1208 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1209 1210 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1211 1212 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1213 DPRINTF("regulatory type=%d\n", sc->regulatory); 1214 1215 IEEE80211_ADDR_COPY(sc->sc_bssid, rom->macaddr); 1216} 1217 1218/* 1219 * Initialize rate adaptation in firmware. 1220 */ 1221static int 1222urtwn_ra_init(struct urtwn_softc *sc) 1223{ 1224 static const uint8_t map[] = 1225 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1226 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1227 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1228 struct ieee80211_node *ni; 1229 struct ieee80211_rateset *rs; 1230 struct r92c_fw_cmd_macid_cfg cmd; 1231 uint32_t rates, basicrates; 1232 uint8_t mode; 1233 int maxrate, maxbasicrate, error, i, j; 1234 1235 ni = ieee80211_ref_node(vap->iv_bss); 1236 rs = &ni->ni_rates; 1237 1238 /* Get normal and basic rates mask. */ 1239 rates = basicrates = 0; 1240 maxrate = maxbasicrate = 0; 1241 for (i = 0; i < rs->rs_nrates; i++) { 1242 /* Convert 802.11 rate to HW rate index. */ 1243 for (j = 0; j < nitems(map); j++) 1244 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1245 break; 1246 if (j == nitems(map)) /* Unknown rate, skip. */ 1247 continue; 1248 rates |= 1 << j; 1249 if (j > maxrate) 1250 maxrate = j; 1251 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1252 basicrates |= 1 << j; 1253 if (j > maxbasicrate) 1254 maxbasicrate = j; 1255 } 1256 } 1257 if (ic->ic_curmode == IEEE80211_MODE_11B) 1258 mode = R92C_RAID_11B; 1259 else 1260 mode = R92C_RAID_11BG; 1261 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1262 mode, rates, basicrates); 1263 1264 /* Set rates mask for group addressed frames. */ 1265 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1266 cmd.mask = htole32(mode << 28 | basicrates); 1267 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1268 if (error != 0) { 1269 ieee80211_free_node(ni); 1270 device_printf(sc->sc_dev, 1271 "could not add broadcast station\n"); 1272 return (error); 1273 } 1274 /* Set initial MRR rate. */ 1275 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1276 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1277 maxbasicrate); 1278 1279 /* Set rates mask for unicast frames. */ 1280 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1281 cmd.mask = htole32(mode << 28 | rates); 1282 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1283 if (error != 0) { 1284 ieee80211_free_node(ni); 1285 device_printf(sc->sc_dev, "could not add BSS station\n"); 1286 return (error); 1287 } 1288 /* Set initial MRR rate. */ 1289 DPRINTF("maxrate=%d\n", maxrate); 1290 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1291 maxrate); 1292 1293 /* Indicate highest supported rate. */ 1294 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1295 ieee80211_free_node(ni); 1296 1297 return (0); 1298} 1299 1300void 1301urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1302{ 1303 struct ifnet *ifp = sc->sc_ifp; 1304 struct ieee80211com *ic = ifp->if_l2com; 1305 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1306 struct ieee80211_node *ni = vap->iv_bss; 1307 1308 uint64_t tsf; 1309 1310 /* Enable TSF synchronization. */ 1311 urtwn_write_1(sc, R92C_BCN_CTRL, 1312 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1313 1314 urtwn_write_1(sc, R92C_BCN_CTRL, 1315 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1316 1317 /* Set initial TSF. */ 1318 memcpy(&tsf, ni->ni_tstamp.data, 8); 1319 tsf = le64toh(tsf); 1320 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1321 tsf -= IEEE80211_DUR_TU; 1322 urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1323 urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1324 1325 urtwn_write_1(sc, R92C_BCN_CTRL, 1326 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1327} 1328 1329static void 1330urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1331{ 1332 uint8_t reg; 1333 1334 if (led == URTWN_LED_LINK) { 1335 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1336 if (!on) 1337 reg |= R92C_LEDCFG0_DIS; 1338 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1339 sc->ledlink = on; /* Save LED state. */ 1340 } 1341} 1342 1343static int 1344urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1345{ 1346 struct urtwn_vap *uvp = URTWN_VAP(vap); 1347 struct ieee80211com *ic = vap->iv_ic; 1348 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1349 struct ieee80211_node *ni; 1350 enum ieee80211_state ostate; 1351 uint32_t reg; 1352 1353 ostate = vap->iv_state; 1354 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1355 ieee80211_state_name[nstate]); 1356 1357 IEEE80211_UNLOCK(ic); 1358 URTWN_LOCK(sc); 1359 callout_stop(&sc->sc_watchdog_ch); 1360 1361 if (ostate == IEEE80211_S_RUN) { 1362 /* Turn link LED off. */ 1363 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1364 1365 /* Set media status to 'No Link'. */ 1366 reg = urtwn_read_4(sc, R92C_CR); 1367 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1368 urtwn_write_4(sc, R92C_CR, reg); 1369 1370 /* Stop Rx of data frames. */ 1371 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1372 1373 /* Rest TSF. */ 1374 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1375 1376 /* Disable TSF synchronization. */ 1377 urtwn_write_1(sc, R92C_BCN_CTRL, 1378 urtwn_read_1(sc, R92C_BCN_CTRL) | 1379 R92C_BCN_CTRL_DIS_TSF_UDT0); 1380 1381 /* Reset EDCA parameters. */ 1382 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1383 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1384 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1385 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1386 } 1387 1388 switch (nstate) { 1389 case IEEE80211_S_INIT: 1390 /* Turn link LED off. */ 1391 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1392 break; 1393 case IEEE80211_S_SCAN: 1394 if (ostate != IEEE80211_S_SCAN) { 1395 /* Allow Rx from any BSSID. */ 1396 urtwn_write_4(sc, R92C_RCR, 1397 urtwn_read_4(sc, R92C_RCR) & 1398 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1399 1400 /* Set gain for scanning. */ 1401 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1402 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1403 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1404 1405 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1406 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1407 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1408 } 1409 1410 /* Make link LED blink during scan. */ 1411 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1412 1413 /* Pause AC Tx queues. */ 1414 urtwn_write_1(sc, R92C_TXPAUSE, 1415 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1416 1417 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1418 break; 1419 case IEEE80211_S_AUTH: 1420 /* Set initial gain under link. */ 1421 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1422 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1423 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1424 1425 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1426 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1427 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1428 1429 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1430 break; 1431 case IEEE80211_S_RUN: 1432 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1433 /* Enable Rx of data frames. */ 1434 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1435 1436 /* Turn link LED on. */ 1437 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1438 break; 1439 } 1440 1441 ni = ieee80211_ref_node(vap->iv_bss); 1442 /* Set media status to 'Associated'. */ 1443 reg = urtwn_read_4(sc, R92C_CR); 1444 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1445 urtwn_write_4(sc, R92C_CR, reg); 1446 1447 /* Set BSSID. */ 1448 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1449 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1450 1451 if (ic->ic_curmode == IEEE80211_MODE_11B) 1452 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1453 else /* 802.11b/g */ 1454 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1455 1456 /* Enable Rx of data frames. */ 1457 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1458 1459 /* Flush all AC queues. */ 1460 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1461 1462 /* Set beacon interval. */ 1463 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1464 1465 /* Allow Rx from our BSSID only. */ 1466 urtwn_write_4(sc, R92C_RCR, 1467 urtwn_read_4(sc, R92C_RCR) | 1468 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1469 1470 /* Enable TSF synchronization. */ 1471 urtwn_tsf_sync_enable(sc); 1472 1473 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1474 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1475 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1476 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1477 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1478 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1479 1480 /* Intialize rate adaptation. */ 1481 urtwn_ra_init(sc); 1482 /* Turn link LED on. */ 1483 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1484 1485 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1486 /* Reset temperature calibration state machine. */ 1487 sc->thcal_state = 0; 1488 sc->thcal_lctemp = 0; 1489 ieee80211_free_node(ni); 1490 break; 1491 default: 1492 break; 1493 } 1494 URTWN_UNLOCK(sc); 1495 IEEE80211_LOCK(ic); 1496 return(uvp->newstate(vap, nstate, arg)); 1497} 1498 1499static void 1500urtwn_watchdog(void *arg) 1501{ 1502 struct urtwn_softc *sc = arg; 1503 struct ifnet *ifp = sc->sc_ifp; 1504 1505 if (sc->sc_txtimer > 0) { 1506 if (--sc->sc_txtimer == 0) { 1507 device_printf(sc->sc_dev, "device timeout\n"); 1508 ifp->if_oerrors++; 1509 return; 1510 } 1511 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1512 } 1513} 1514 1515static void 1516urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1517{ 1518 int pwdb; 1519 1520 /* Convert antenna signal to percentage. */ 1521 if (rssi <= -100 || rssi >= 20) 1522 pwdb = 0; 1523 else if (rssi >= 0) 1524 pwdb = 100; 1525 else 1526 pwdb = 100 + rssi; 1527 if (rate <= 3) { 1528 /* CCK gain is smaller than OFDM/MCS gain. */ 1529 pwdb += 6; 1530 if (pwdb > 100) 1531 pwdb = 100; 1532 if (pwdb <= 14) 1533 pwdb -= 4; 1534 else if (pwdb <= 26) 1535 pwdb -= 8; 1536 else if (pwdb <= 34) 1537 pwdb -= 6; 1538 else if (pwdb <= 42) 1539 pwdb -= 2; 1540 } 1541 if (sc->avg_pwdb == -1) /* Init. */ 1542 sc->avg_pwdb = pwdb; 1543 else if (sc->avg_pwdb < pwdb) 1544 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1545 else 1546 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1547 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1548} 1549 1550static int8_t 1551urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1552{ 1553 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1554 struct r92c_rx_phystat *phy; 1555 struct r92c_rx_cck *cck; 1556 uint8_t rpt; 1557 int8_t rssi; 1558 1559 if (rate <= 3) { 1560 cck = (struct r92c_rx_cck *)physt; 1561 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1562 rpt = (cck->agc_rpt >> 5) & 0x3; 1563 rssi = (cck->agc_rpt & 0x1f) << 1; 1564 } else { 1565 rpt = (cck->agc_rpt >> 6) & 0x3; 1566 rssi = cck->agc_rpt & 0x3e; 1567 } 1568 rssi = cckoff[rpt] - rssi; 1569 } else { /* OFDM/HT. */ 1570 phy = (struct r92c_rx_phystat *)physt; 1571 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1572 } 1573 return (rssi); 1574} 1575 1576static int 1577urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1578 struct mbuf *m0, struct urtwn_data *data) 1579{ 1580 struct ifnet *ifp = sc->sc_ifp; 1581 struct ieee80211_frame *wh; 1582 struct ieee80211_key *k; 1583 struct ieee80211com *ic = ifp->if_l2com; 1584 struct ieee80211vap *vap = ni->ni_vap; 1585 struct usb_xfer *xfer; 1586 struct r92c_tx_desc *txd; 1587 uint8_t raid, type; 1588 uint16_t sum; 1589 int i, hasqos, xferlen; 1590 struct usb_xfer *urtwn_pipes[4] = { 1591 sc->sc_xfer[URTWN_BULK_TX_BE], 1592 sc->sc_xfer[URTWN_BULK_TX_BK], 1593 sc->sc_xfer[URTWN_BULK_TX_VI], 1594 sc->sc_xfer[URTWN_BULK_TX_VO] 1595 }; 1596 1597 URTWN_ASSERT_LOCKED(sc); 1598 1599 /* 1600 * Software crypto. 1601 */ 1602 wh = mtod(m0, struct ieee80211_frame *); 1603 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1604 k = ieee80211_crypto_encap(ni, m0); 1605 if (k == NULL) { 1606 device_printf(sc->sc_dev, 1607 "ieee80211_crypto_encap returns NULL.\n"); 1608 /* XXX we don't expect the fragmented frames */ 1609 m_freem(m0); 1610 return (ENOBUFS); 1611 } 1612 1613 /* in case packet header moved, reset pointer */ 1614 wh = mtod(m0, struct ieee80211_frame *); 1615 } 1616 1617 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1618 case IEEE80211_FC0_TYPE_CTL: 1619 case IEEE80211_FC0_TYPE_MGT: 1620 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1621 break; 1622 default: 1623 KASSERT(M_WME_GETAC(m0) < 4, 1624 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1625 xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1626 break; 1627 } 1628 1629 hasqos = 0; 1630 1631 /* Fill Tx descriptor. */ 1632 txd = (struct r92c_tx_desc *)data->buf; 1633 memset(txd, 0, sizeof(*txd)); 1634 1635 txd->txdw0 |= htole32( 1636 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1637 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1638 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1639 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1640 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1641 1642 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1643 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1644 type == IEEE80211_FC0_TYPE_DATA) { 1645 if (ic->ic_curmode == IEEE80211_MODE_11B) 1646 raid = R92C_RAID_11B; 1647 else 1648 raid = R92C_RAID_11BG; 1649 txd->txdw1 |= htole32( 1650 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1651 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1652 SM(R92C_TXDW1_RAID, raid) | 1653 R92C_TXDW1_AGGBK); 1654 1655 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1656 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1657 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1658 R92C_TXDW4_HWRTSEN); 1659 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1660 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1661 R92C_TXDW4_HWRTSEN); 1662 } 1663 } 1664 /* Send RTS at OFDM24. */ 1665 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1666 txd->txdw5 |= htole32(0x0001ff00); 1667 /* Send data at OFDM54. */ 1668 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1669 } else { 1670 txd->txdw1 |= htole32( 1671 SM(R92C_TXDW1_MACID, 0) | 1672 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1673 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1674 1675 /* Force CCK1. */ 1676 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1677 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1678 } 1679 /* Set sequence number (already little endian). */ 1680 txd->txdseq |= *(uint16_t *)wh->i_seq; 1681 1682 if (!hasqos) { 1683 /* Use HW sequence numbering for non-QoS frames. */ 1684 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1685 txd->txdseq |= htole16(0x8000); 1686 } else 1687 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1688 1689 /* Compute Tx descriptor checksum. */ 1690 sum = 0; 1691 for (i = 0; i < sizeof(*txd) / 2; i++) 1692 sum ^= ((uint16_t *)txd)[i]; 1693 txd->txdsum = sum; /* NB: already little endian. */ 1694 1695 if (ieee80211_radiotap_active_vap(vap)) { 1696 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1697 1698 tap->wt_flags = 0; 1699 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1700 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1701 ieee80211_radiotap_tx(vap, m0); 1702 } 1703 1704 xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1705 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1706 1707 data->buflen = xferlen; 1708 data->ni = ni; 1709 data->m = m0; 1710 1711 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1712 usbd_transfer_start(xfer); 1713 return (0); 1714} 1715 1716static void 1717urtwn_start(struct ifnet *ifp) 1718{ 1719 struct urtwn_softc *sc = ifp->if_softc; 1720 struct ieee80211_node *ni; 1721 struct mbuf *m; 1722 struct urtwn_data *bf; 1723 1724 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1725 return; 1726 1727 URTWN_LOCK(sc); 1728 for (;;) { 1729 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1730 if (m == NULL) 1731 break; 1732 bf = urtwn_getbuf(sc); 1733 if (bf == NULL) { 1734 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1735 break; 1736 } 1737 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1738 m->m_pkthdr.rcvif = NULL; 1739 1740 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 1741 ifp->if_oerrors++; 1742 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1743 ieee80211_free_node(ni); 1744 break; 1745 } 1746 1747 sc->sc_txtimer = 5; 1748 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1749 } 1750 URTWN_UNLOCK(sc); 1751} 1752 1753static int 1754urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1755{ 1756 struct ieee80211com *ic = ifp->if_l2com; 1757 struct ifreq *ifr = (struct ifreq *) data; 1758 int error = 0, startall = 0; 1759 1760 switch (cmd) { 1761 case SIOCSIFFLAGS: 1762 if (ifp->if_flags & IFF_UP) { 1763 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1764 urtwn_init(ifp->if_softc); 1765 startall = 1; 1766 } 1767 } else { 1768 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1769 urtwn_stop(ifp, 1); 1770 } 1771 if (startall) 1772 ieee80211_start_all(ic); 1773 break; 1774 case SIOCGIFMEDIA: 1775 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1776 break; 1777 case SIOCGIFADDR: 1778 error = ether_ioctl(ifp, cmd, data); 1779 break; 1780 default: 1781 error = EINVAL; 1782 break; 1783 } 1784 return (error); 1785} 1786 1787static int 1788urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1789 int ndata, int maxsz) 1790{ 1791 int i, error; 1792 1793 for (i = 0; i < ndata; i++) { 1794 struct urtwn_data *dp = &data[i]; 1795 dp->sc = sc; 1796 dp->m = NULL; 1797 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1798 if (dp->buf == NULL) { 1799 device_printf(sc->sc_dev, 1800 "could not allocate buffer\n"); 1801 error = ENOMEM; 1802 goto fail; 1803 } 1804 dp->ni = NULL; 1805 } 1806 1807 return (0); 1808fail: 1809 urtwn_free_list(sc, data, ndata); 1810 return (error); 1811} 1812 1813static int 1814urtwn_alloc_rx_list(struct urtwn_softc *sc) 1815{ 1816 int error, i; 1817 1818 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1819 URTWN_RXBUFSZ); 1820 if (error != 0) 1821 return (error); 1822 1823 STAILQ_INIT(&sc->sc_rx_active); 1824 STAILQ_INIT(&sc->sc_rx_inactive); 1825 1826 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1827 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1828 1829 return (0); 1830} 1831 1832static int 1833urtwn_alloc_tx_list(struct urtwn_softc *sc) 1834{ 1835 int error, i; 1836 1837 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1838 URTWN_TXBUFSZ); 1839 if (error != 0) 1840 return (error); 1841 1842 STAILQ_INIT(&sc->sc_tx_active); 1843 STAILQ_INIT(&sc->sc_tx_inactive); 1844 STAILQ_INIT(&sc->sc_tx_pending); 1845 1846 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1847 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1848 1849 return (0); 1850} 1851 1852static int 1853urtwn_power_on(struct urtwn_softc *sc) 1854{ 1855 uint32_t reg; 1856 int ntries; 1857 1858 /* Wait for autoload done bit. */ 1859 for (ntries = 0; ntries < 1000; ntries++) { 1860 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1861 break; 1862 DELAY(5); 1863 } 1864 if (ntries == 1000) { 1865 device_printf(sc->sc_dev, 1866 "timeout waiting for chip autoload\n"); 1867 return (ETIMEDOUT); 1868 } 1869 1870 /* Unlock ISO/CLK/Power control register. */ 1871 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 1872 /* Move SPS into PWM mode. */ 1873 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1874 DELAY(100); 1875 1876 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 1877 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 1878 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 1879 reg | R92C_LDOV12D_CTRL_LDV12_EN); 1880 DELAY(100); 1881 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 1882 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 1883 ~R92C_SYS_ISO_CTRL_MD2PP); 1884 } 1885 1886 /* Auto enable WLAN. */ 1887 urtwn_write_2(sc, R92C_APS_FSMCO, 1888 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1889 for (ntries = 0; ntries < 1000; ntries++) { 1890 if (urtwn_read_2(sc, R92C_APS_FSMCO) & 1891 R92C_APS_FSMCO_APFM_ONMAC) 1892 break; 1893 DELAY(5); 1894 } 1895 if (ntries == 1000) { 1896 device_printf(sc->sc_dev, 1897 "timeout waiting for MAC auto ON\n"); 1898 return (ETIMEDOUT); 1899 } 1900 1901 /* Enable radio, GPIO and LED functions. */ 1902 urtwn_write_2(sc, R92C_APS_FSMCO, 1903 R92C_APS_FSMCO_AFSM_HSUS | 1904 R92C_APS_FSMCO_PDN_EN | 1905 R92C_APS_FSMCO_PFM_ALDN); 1906 /* Release RF digital isolation. */ 1907 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1908 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1909 1910 /* Initialize MAC. */ 1911 urtwn_write_1(sc, R92C_APSD_CTRL, 1912 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 1913 for (ntries = 0; ntries < 200; ntries++) { 1914 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 1915 R92C_APSD_CTRL_OFF_STATUS)) 1916 break; 1917 DELAY(5); 1918 } 1919 if (ntries == 200) { 1920 device_printf(sc->sc_dev, 1921 "timeout waiting for MAC initialization\n"); 1922 return (ETIMEDOUT); 1923 } 1924 1925 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1926 reg = urtwn_read_2(sc, R92C_CR); 1927 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1928 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1929 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 1930 R92C_CR_ENSEC; 1931 urtwn_write_2(sc, R92C_CR, reg); 1932 1933 urtwn_write_1(sc, 0xfe10, 0x19); 1934 return (0); 1935} 1936 1937static int 1938urtwn_llt_init(struct urtwn_softc *sc) 1939{ 1940 int i, error; 1941 1942 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 1943 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 1944 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1945 return (error); 1946 } 1947 /* NB: 0xff indicates end-of-list. */ 1948 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 1949 return (error); 1950 /* 1951 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 1952 * as ring buffer. 1953 */ 1954 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 1955 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1956 return (error); 1957 } 1958 /* Make the last page point to the beginning of the ring buffer. */ 1959 error = urtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 1960 return (error); 1961} 1962 1963static void 1964urtwn_fw_reset(struct urtwn_softc *sc) 1965{ 1966 uint16_t reg; 1967 int ntries; 1968 1969 /* Tell 8051 to reset itself. */ 1970 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 1971 1972 /* Wait until 8051 resets by itself. */ 1973 for (ntries = 0; ntries < 100; ntries++) { 1974 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1975 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 1976 return; 1977 DELAY(50); 1978 } 1979 /* Force 8051 reset. */ 1980 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 1981} 1982 1983static int 1984urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 1985{ 1986 uint32_t reg; 1987 int off, mlen, error = 0; 1988 1989 reg = urtwn_read_4(sc, R92C_MCUFWDL); 1990 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 1991 urtwn_write_4(sc, R92C_MCUFWDL, reg); 1992 1993 off = R92C_FW_START_ADDR; 1994 while (len > 0) { 1995 if (len > 196) 1996 mlen = 196; 1997 else if (len > 4) 1998 mlen = 4; 1999 else 2000 mlen = 1; 2001 /* XXX fix this deconst */ 2002 error = urtwn_write_region_1(sc, off, 2003 __DECONST(uint8_t *, buf), mlen); 2004 if (error != 0) 2005 break; 2006 off += mlen; 2007 buf += mlen; 2008 len -= mlen; 2009 } 2010 return (error); 2011} 2012 2013static int 2014urtwn_load_firmware(struct urtwn_softc *sc) 2015{ 2016 const struct firmware *fw; 2017 const struct r92c_fw_hdr *hdr; 2018 const char *imagename; 2019 const u_char *ptr; 2020 size_t len; 2021 uint32_t reg; 2022 int mlen, ntries, page, error; 2023 2024 /* Read firmware image from the filesystem. */ 2025 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2026 URTWN_CHIP_UMC_A_CUT) 2027 imagename = "urtwn-rtl8192cfwU"; 2028 else 2029 imagename = "urtwn-rtl8192cfwT"; 2030 2031 fw = firmware_get(imagename); 2032 if (fw == NULL) { 2033 device_printf(sc->sc_dev, 2034 "failed loadfirmware of file %s\n", imagename); 2035 return (ENOENT); 2036 } 2037 2038 len = fw->datasize; 2039 2040 if (len < sizeof(*hdr)) { 2041 device_printf(sc->sc_dev, "firmware too short\n"); 2042 error = EINVAL; 2043 goto fail; 2044 } 2045 ptr = fw->data; 2046 hdr = (const struct r92c_fw_hdr *)ptr; 2047 /* Check if there is a valid FW header and skip it. */ 2048 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2049 (le16toh(hdr->signature) >> 4) == 0x92c) { 2050 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2051 le16toh(hdr->version), le16toh(hdr->subversion), 2052 hdr->month, hdr->date, hdr->hour, hdr->minute); 2053 ptr += sizeof(*hdr); 2054 len -= sizeof(*hdr); 2055 } 2056 2057 if (urtwn_read_1(sc, R92C_MCUFWDL) & 0x80) { 2058 urtwn_fw_reset(sc); 2059 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2060 } 2061 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2062 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2063 R92C_SYS_FUNC_EN_CPUEN); 2064 urtwn_write_1(sc, R92C_MCUFWDL, 2065 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2066 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2067 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2068 2069 for (page = 0; len > 0; page++) { 2070 mlen = min(len, R92C_FW_PAGE_SIZE); 2071 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2072 if (error != 0) { 2073 device_printf(sc->sc_dev, 2074 "could not load firmware page\n"); 2075 goto fail; 2076 } 2077 ptr += mlen; 2078 len -= mlen; 2079 } 2080 urtwn_write_1(sc, R92C_MCUFWDL, 2081 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2082 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2083 2084 /* Wait for checksum report. */ 2085 for (ntries = 0; ntries < 1000; ntries++) { 2086 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2087 break; 2088 DELAY(5); 2089 } 2090 if (ntries == 1000) { 2091 device_printf(sc->sc_dev, 2092 "timeout waiting for checksum report\n"); 2093 error = ETIMEDOUT; 2094 goto fail; 2095 } 2096 2097 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2098 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2099 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2100 /* Wait for firmware readiness. */ 2101 for (ntries = 0; ntries < 1000; ntries++) { 2102 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2103 break; 2104 DELAY(5); 2105 } 2106 if (ntries == 1000) { 2107 device_printf(sc->sc_dev, 2108 "timeout waiting for firmware readiness\n"); 2109 error = ETIMEDOUT; 2110 goto fail; 2111 } 2112fail: 2113 firmware_put(fw, FIRMWARE_UNLOAD); 2114 return (error); 2115} 2116 2117static int 2118urtwn_dma_init(struct urtwn_softc *sc) 2119{ 2120 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2121 uint32_t reg; 2122 int error; 2123 2124 /* Initialize LLT table. */ 2125 error = urtwn_llt_init(sc); 2126 if (error != 0) 2127 return (error); 2128 2129 /* Get Tx queues to USB endpoints mapping. */ 2130 hashq = hasnq = haslq = 0; 2131 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2132 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2133 if (MS(reg, R92C_USB_EP_HQ) != 0) 2134 hashq = 1; 2135 if (MS(reg, R92C_USB_EP_NQ) != 0) 2136 hasnq = 1; 2137 if (MS(reg, R92C_USB_EP_LQ) != 0) 2138 haslq = 1; 2139 nqueues = hashq + hasnq + haslq; 2140 if (nqueues == 0) 2141 return (EIO); 2142 /* Get the number of pages for each queue. */ 2143 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2144 /* The remaining pages are assigned to the high priority queue. */ 2145 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2146 2147 /* Set number of pages for normal priority queue. */ 2148 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2149 urtwn_write_4(sc, R92C_RQPN, 2150 /* Set number of pages for public queue. */ 2151 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2152 /* Set number of pages for high priority queue. */ 2153 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2154 /* Set number of pages for low priority queue. */ 2155 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2156 /* Load values. */ 2157 R92C_RQPN_LD); 2158 2159 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2160 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2161 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2162 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2163 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2164 2165 /* Set queue to USB pipe mapping. */ 2166 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2167 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2168 if (nqueues == 1) { 2169 if (hashq) 2170 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2171 else if (hasnq) 2172 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2173 else 2174 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2175 } else if (nqueues == 2) { 2176 /* All 2-endpoints configs have a high priority queue. */ 2177 if (!hashq) 2178 return (EIO); 2179 if (hasnq) 2180 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2181 else 2182 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2183 } else 2184 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2185 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2186 2187 /* Set Tx/Rx transfer page boundary. */ 2188 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2189 2190 /* Set Tx/Rx transfer page size. */ 2191 urtwn_write_1(sc, R92C_PBP, 2192 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2193 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2194 return (0); 2195} 2196 2197static void 2198urtwn_mac_init(struct urtwn_softc *sc) 2199{ 2200 int i; 2201 2202 /* Write MAC initialization values. */ 2203 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2204 urtwn_write_1(sc, rtl8192cu_mac[i].reg, rtl8192cu_mac[i].val); 2205} 2206 2207static void 2208urtwn_bb_init(struct urtwn_softc *sc) 2209{ 2210 const struct urtwn_bb_prog *prog; 2211 uint32_t reg; 2212 int i; 2213 2214 /* Enable BB and RF. */ 2215 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2216 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2217 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2218 R92C_SYS_FUNC_EN_DIO_RF); 2219 2220 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2221 2222 urtwn_write_1(sc, R92C_RF_CTRL, 2223 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2224 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2225 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2226 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2227 2228 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2229 urtwn_write_1(sc, 0x15, 0xe9); 2230 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2231 2232 /* Select BB programming based on board type. */ 2233 if (!(sc->chip & URTWN_CHIP_92C)) { 2234 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2235 prog = &rtl8188ce_bb_prog; 2236 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2237 prog = &rtl8188ru_bb_prog; 2238 else 2239 prog = &rtl8188cu_bb_prog; 2240 } else { 2241 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2242 prog = &rtl8192ce_bb_prog; 2243 else 2244 prog = &rtl8192cu_bb_prog; 2245 } 2246 /* Write BB initialization values. */ 2247 for (i = 0; i < prog->count; i++) { 2248 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2249 DELAY(1); 2250 } 2251 2252 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2253 /* 8192C 1T only configuration. */ 2254 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2255 reg = (reg & ~0x00000003) | 0x2; 2256 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2257 2258 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2259 reg = (reg & ~0x00300033) | 0x00200022; 2260 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2261 2262 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2263 reg = (reg & ~0xff000000) | 0x45 << 24; 2264 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2265 2266 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2267 reg = (reg & ~0x000000ff) | 0x23; 2268 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2269 2270 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2271 reg = (reg & ~0x00000030) | 1 << 4; 2272 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2273 2274 reg = urtwn_bb_read(sc, 0xe74); 2275 reg = (reg & ~0x0c000000) | 2 << 26; 2276 urtwn_bb_write(sc, 0xe74, reg); 2277 reg = urtwn_bb_read(sc, 0xe78); 2278 reg = (reg & ~0x0c000000) | 2 << 26; 2279 urtwn_bb_write(sc, 0xe78, reg); 2280 reg = urtwn_bb_read(sc, 0xe7c); 2281 reg = (reg & ~0x0c000000) | 2 << 26; 2282 urtwn_bb_write(sc, 0xe7c, reg); 2283 reg = urtwn_bb_read(sc, 0xe80); 2284 reg = (reg & ~0x0c000000) | 2 << 26; 2285 urtwn_bb_write(sc, 0xe80, reg); 2286 reg = urtwn_bb_read(sc, 0xe88); 2287 reg = (reg & ~0x0c000000) | 2 << 26; 2288 urtwn_bb_write(sc, 0xe88, reg); 2289 } 2290 2291 /* Write AGC values. */ 2292 for (i = 0; i < prog->agccount; i++) { 2293 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2294 prog->agcvals[i]); 2295 DELAY(1); 2296 } 2297 2298 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2299 R92C_HSSI_PARAM2_CCK_HIPWR) 2300 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2301} 2302 2303void 2304urtwn_rf_init(struct urtwn_softc *sc) 2305{ 2306 const struct urtwn_rf_prog *prog; 2307 uint32_t reg, type; 2308 int i, j, idx, off; 2309 2310 /* Select RF programming based on board type. */ 2311 if (!(sc->chip & URTWN_CHIP_92C)) { 2312 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2313 prog = rtl8188ce_rf_prog; 2314 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2315 prog = rtl8188ru_rf_prog; 2316 else 2317 prog = rtl8188cu_rf_prog; 2318 } else 2319 prog = rtl8192ce_rf_prog; 2320 2321 for (i = 0; i < sc->nrxchains; i++) { 2322 /* Save RF_ENV control type. */ 2323 idx = i / 2; 2324 off = (i % 2) * 16; 2325 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2326 type = (reg >> off) & 0x10; 2327 2328 /* Set RF_ENV enable. */ 2329 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2330 reg |= 0x100000; 2331 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2332 DELAY(1); 2333 /* Set RF_ENV output high. */ 2334 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2335 reg |= 0x10; 2336 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2337 DELAY(1); 2338 /* Set address and data lengths of RF registers. */ 2339 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2340 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2341 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2342 DELAY(1); 2343 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2344 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2345 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2346 DELAY(1); 2347 2348 /* Write RF initialization values for this chain. */ 2349 for (j = 0; j < prog[i].count; j++) { 2350 if (prog[i].regs[j] >= 0xf9 && 2351 prog[i].regs[j] <= 0xfe) { 2352 /* 2353 * These are fake RF registers offsets that 2354 * indicate a delay is required. 2355 */ 2356 usb_pause_mtx(&sc->sc_mtx, 50); 2357 continue; 2358 } 2359 urtwn_rf_write(sc, i, prog[i].regs[j], 2360 prog[i].vals[j]); 2361 DELAY(1); 2362 } 2363 2364 /* Restore RF_ENV control type. */ 2365 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2366 reg &= ~(0x10 << off) | (type << off); 2367 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2368 2369 /* Cache RF register CHNLBW. */ 2370 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2371 } 2372 2373 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2374 URTWN_CHIP_UMC_A_CUT) { 2375 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2376 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2377 } 2378} 2379 2380static void 2381urtwn_cam_init(struct urtwn_softc *sc) 2382{ 2383 /* Invalidate all CAM entries. */ 2384 urtwn_write_4(sc, R92C_CAMCMD, 2385 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2386} 2387 2388static void 2389urtwn_pa_bias_init(struct urtwn_softc *sc) 2390{ 2391 uint8_t reg; 2392 int i; 2393 2394 for (i = 0; i < sc->nrxchains; i++) { 2395 if (sc->pa_setting & (1 << i)) 2396 continue; 2397 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2398 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2399 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2400 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2401 } 2402 if (!(sc->pa_setting & 0x10)) { 2403 reg = urtwn_read_1(sc, 0x16); 2404 reg = (reg & ~0xf0) | 0x90; 2405 urtwn_write_1(sc, 0x16, reg); 2406 } 2407} 2408 2409static void 2410urtwn_rxfilter_init(struct urtwn_softc *sc) 2411{ 2412 /* Initialize Rx filter. */ 2413 /* TODO: use better filter for monitor mode. */ 2414 urtwn_write_4(sc, R92C_RCR, 2415 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2416 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2417 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2418 /* Accept all multicast frames. */ 2419 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2420 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2421 /* Accept all management frames. */ 2422 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2423 /* Reject all control frames. */ 2424 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2425 /* Accept all data frames. */ 2426 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2427} 2428 2429static void 2430urtwn_edca_init(struct urtwn_softc *sc) 2431{ 2432 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2433 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2434 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2435 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2436 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2437 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2438 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2439 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2440} 2441 2442void 2443urtwn_write_txpower(struct urtwn_softc *sc, int chain, 2444 uint16_t power[URTWN_RIDX_COUNT]) 2445{ 2446 uint32_t reg; 2447 2448 /* Write per-CCK rate Tx power. */ 2449 if (chain == 0) { 2450 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2451 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2452 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2453 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2454 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2455 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2456 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2457 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2458 } else { 2459 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2460 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2461 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2462 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2463 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2464 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2465 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2466 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2467 } 2468 /* Write per-OFDM rate Tx power. */ 2469 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2470 SM(R92C_TXAGC_RATE06, power[ 4]) | 2471 SM(R92C_TXAGC_RATE09, power[ 5]) | 2472 SM(R92C_TXAGC_RATE12, power[ 6]) | 2473 SM(R92C_TXAGC_RATE18, power[ 7])); 2474 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2475 SM(R92C_TXAGC_RATE24, power[ 8]) | 2476 SM(R92C_TXAGC_RATE36, power[ 9]) | 2477 SM(R92C_TXAGC_RATE48, power[10]) | 2478 SM(R92C_TXAGC_RATE54, power[11])); 2479 /* Write per-MCS Tx power. */ 2480 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2481 SM(R92C_TXAGC_MCS00, power[12]) | 2482 SM(R92C_TXAGC_MCS01, power[13]) | 2483 SM(R92C_TXAGC_MCS02, power[14]) | 2484 SM(R92C_TXAGC_MCS03, power[15])); 2485 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2486 SM(R92C_TXAGC_MCS04, power[16]) | 2487 SM(R92C_TXAGC_MCS05, power[17]) | 2488 SM(R92C_TXAGC_MCS06, power[18]) | 2489 SM(R92C_TXAGC_MCS07, power[19])); 2490 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2491 SM(R92C_TXAGC_MCS08, power[20]) | 2492 SM(R92C_TXAGC_MCS08, power[21]) | 2493 SM(R92C_TXAGC_MCS10, power[22]) | 2494 SM(R92C_TXAGC_MCS11, power[23])); 2495 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2496 SM(R92C_TXAGC_MCS12, power[24]) | 2497 SM(R92C_TXAGC_MCS13, power[25]) | 2498 SM(R92C_TXAGC_MCS14, power[26]) | 2499 SM(R92C_TXAGC_MCS15, power[27])); 2500} 2501 2502void 2503urtwn_get_txpower(struct urtwn_softc *sc, int chain, 2504 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2505 uint16_t power[URTWN_RIDX_COUNT]) 2506{ 2507 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2508 struct r92c_rom *rom = &sc->rom; 2509 uint16_t cckpow, ofdmpow, htpow, diff, max; 2510 const struct urtwn_txpwr *base; 2511 int ridx, chan, group; 2512 2513 /* Determine channel group. */ 2514 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2515 if (chan <= 3) 2516 group = 0; 2517 else if (chan <= 9) 2518 group = 1; 2519 else 2520 group = 2; 2521 2522 /* Get original Tx power based on board type and RF chain. */ 2523 if (!(sc->chip & URTWN_CHIP_92C)) { 2524 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2525 base = &rtl8188ru_txagc[chain]; 2526 else 2527 base = &rtl8192cu_txagc[chain]; 2528 } else 2529 base = &rtl8192cu_txagc[chain]; 2530 2531 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2532 if (sc->regulatory == 0) { 2533 for (ridx = 0; ridx <= 3; ridx++) 2534 power[ridx] = base->pwr[0][ridx]; 2535 } 2536 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 2537 if (sc->regulatory == 3) { 2538 power[ridx] = base->pwr[0][ridx]; 2539 /* Apply vendor limits. */ 2540 if (extc != NULL) 2541 max = rom->ht40_max_pwr[group]; 2542 else 2543 max = rom->ht20_max_pwr[group]; 2544 max = (max >> (chain * 4)) & 0xf; 2545 if (power[ridx] > max) 2546 power[ridx] = max; 2547 } else if (sc->regulatory == 1) { 2548 if (extc == NULL) 2549 power[ridx] = base->pwr[group][ridx]; 2550 } else if (sc->regulatory != 2) 2551 power[ridx] = base->pwr[0][ridx]; 2552 } 2553 2554 /* Compute per-CCK rate Tx power. */ 2555 cckpow = rom->cck_tx_pwr[chain][group]; 2556 for (ridx = 0; ridx <= 3; ridx++) { 2557 power[ridx] += cckpow; 2558 if (power[ridx] > R92C_MAX_TX_PWR) 2559 power[ridx] = R92C_MAX_TX_PWR; 2560 } 2561 2562 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2563 if (sc->ntxchains > 1) { 2564 /* Apply reduction for 2 spatial streams. */ 2565 diff = rom->ht40_2s_tx_pwr_diff[group]; 2566 diff = (diff >> (chain * 4)) & 0xf; 2567 htpow = (htpow > diff) ? htpow - diff : 0; 2568 } 2569 2570 /* Compute per-OFDM rate Tx power. */ 2571 diff = rom->ofdm_tx_pwr_diff[group]; 2572 diff = (diff >> (chain * 4)) & 0xf; 2573 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2574 for (ridx = 4; ridx <= 11; ridx++) { 2575 power[ridx] += ofdmpow; 2576 if (power[ridx] > R92C_MAX_TX_PWR) 2577 power[ridx] = R92C_MAX_TX_PWR; 2578 } 2579 2580 /* Compute per-MCS Tx power. */ 2581 if (extc == NULL) { 2582 diff = rom->ht20_tx_pwr_diff[group]; 2583 diff = (diff >> (chain * 4)) & 0xf; 2584 htpow += diff; /* HT40->HT20 correction. */ 2585 } 2586 for (ridx = 12; ridx <= 27; ridx++) { 2587 power[ridx] += htpow; 2588 if (power[ridx] > R92C_MAX_TX_PWR) 2589 power[ridx] = R92C_MAX_TX_PWR; 2590 } 2591#ifdef URTWN_DEBUG 2592 if (urtwn_debug >= 4) { 2593 /* Dump per-rate Tx power values. */ 2594 printf("Tx power for chain %d:\n", chain); 2595 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 2596 printf("Rate %d = %u\n", ridx, power[ridx]); 2597 } 2598#endif 2599} 2600 2601void 2602urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 2603 struct ieee80211_channel *extc) 2604{ 2605 uint16_t power[URTWN_RIDX_COUNT]; 2606 int i; 2607 2608 for (i = 0; i < sc->ntxchains; i++) { 2609 /* Compute per-rate Tx power values. */ 2610 urtwn_get_txpower(sc, i, c, extc, power); 2611 /* Write per-rate Tx power values to hardware. */ 2612 urtwn_write_txpower(sc, i, power); 2613 } 2614} 2615 2616static void 2617urtwn_scan_start(struct ieee80211com *ic) 2618{ 2619 /* XXX do nothing? */ 2620} 2621 2622static void 2623urtwn_scan_end(struct ieee80211com *ic) 2624{ 2625 /* XXX do nothing? */ 2626} 2627 2628static void 2629urtwn_set_channel(struct ieee80211com *ic) 2630{ 2631 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2632 2633 URTWN_LOCK(sc); 2634 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2635 URTWN_UNLOCK(sc); 2636} 2637 2638static void 2639urtwn_update_mcast(struct ifnet *ifp) 2640{ 2641 /* XXX do nothing? */ 2642} 2643 2644static void 2645urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 2646 struct ieee80211_channel *extc) 2647{ 2648 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2649 uint32_t reg; 2650 u_int chan; 2651 int i; 2652 2653 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2654 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 2655 device_printf(sc->sc_dev, 2656 "%s: invalid channel %x\n", __func__, chan); 2657 return; 2658 } 2659 2660 /* Set Tx power for this new channel. */ 2661 urtwn_set_txpower(sc, c, extc); 2662 2663 for (i = 0; i < sc->nrxchains; i++) { 2664 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 2665 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 2666 } 2667#ifndef IEEE80211_NO_HT 2668 if (extc != NULL) { 2669 /* Is secondary channel below or above primary? */ 2670 int prichlo = c->ic_freq < extc->ic_freq; 2671 2672 urtwn_write_1(sc, R92C_BWOPMODE, 2673 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 2674 2675 reg = urtwn_read_1(sc, R92C_RRSR + 2); 2676 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 2677 urtwn_write_1(sc, R92C_RRSR + 2, reg); 2678 2679 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2680 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 2681 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2682 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 2683 2684 /* Set CCK side band. */ 2685 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 2686 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 2687 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 2688 2689 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 2690 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 2691 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 2692 2693 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2694 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 2695 ~R92C_FPGA0_ANAPARAM2_CBW20); 2696 2697 reg = urtwn_bb_read(sc, 0x818); 2698 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 2699 urtwn_bb_write(sc, 0x818, reg); 2700 2701 /* Select 40MHz bandwidth. */ 2702 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2703 (sc->rf_chnlbw[0] & ~0xfff) | chan); 2704 } else 2705#endif 2706 { 2707 urtwn_write_1(sc, R92C_BWOPMODE, 2708 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 2709 2710 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2711 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 2712 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2713 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 2714 2715 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2716 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 2717 R92C_FPGA0_ANAPARAM2_CBW20); 2718 2719 /* Select 20MHz bandwidth. */ 2720 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2721 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 2722 } 2723} 2724 2725static void 2726urtwn_iq_calib(struct urtwn_softc *sc) 2727{ 2728 /* TODO */ 2729} 2730 2731static void 2732urtwn_lc_calib(struct urtwn_softc *sc) 2733{ 2734 uint32_t rf_ac[2]; 2735 uint8_t txmode; 2736 int i; 2737 2738 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 2739 if ((txmode & 0x70) != 0) { 2740 /* Disable all continuous Tx. */ 2741 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 2742 2743 /* Set RF mode to standby mode. */ 2744 for (i = 0; i < sc->nrxchains; i++) { 2745 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 2746 urtwn_rf_write(sc, i, R92C_RF_AC, 2747 RW(rf_ac[i], R92C_RF_AC_MODE, 2748 R92C_RF_AC_MODE_STANDBY)); 2749 } 2750 } else { 2751 /* Block all Tx queues. */ 2752 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 2753 } 2754 /* Start calibration. */ 2755 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2756 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 2757 2758 /* Give calibration the time to complete. */ 2759 usb_pause_mtx(&sc->sc_mtx, 100); 2760 2761 /* Restore configuration. */ 2762 if ((txmode & 0x70) != 0) { 2763 /* Restore Tx mode. */ 2764 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 2765 /* Restore RF mode. */ 2766 for (i = 0; i < sc->nrxchains; i++) 2767 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 2768 } else { 2769 /* Unblock all Tx queues. */ 2770 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 2771 } 2772} 2773 2774static void 2775urtwn_init_locked(void *arg) 2776{ 2777 struct urtwn_softc *sc = arg; 2778 struct ifnet *ifp = sc->sc_ifp; 2779 uint32_t reg; 2780 int error; 2781 2782 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2783 urtwn_stop_locked(ifp, 0); 2784 2785 /* Init firmware commands ring. */ 2786 sc->fwcur = 0; 2787 2788 /* Allocate Tx/Rx buffers. */ 2789 error = urtwn_alloc_rx_list(sc); 2790 if (error != 0) 2791 goto fail; 2792 2793 error = urtwn_alloc_tx_list(sc); 2794 if (error != 0) 2795 goto fail; 2796 2797 /* Power on adapter. */ 2798 error = urtwn_power_on(sc); 2799 if (error != 0) 2800 goto fail; 2801 2802 /* Initialize DMA. */ 2803 error = urtwn_dma_init(sc); 2804 if (error != 0) 2805 goto fail; 2806 2807 /* Set info size in Rx descriptors (in 64-bit words). */ 2808 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 2809 2810 /* Init interrupts. */ 2811 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 2812 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 2813 2814 /* Set MAC address. */ 2815 urtwn_write_region_1(sc, R92C_MACID, IF_LLADDR(ifp), 2816 IEEE80211_ADDR_LEN); 2817 2818 /* Set initial network type. */ 2819 reg = urtwn_read_4(sc, R92C_CR); 2820 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 2821 urtwn_write_4(sc, R92C_CR, reg); 2822 2823 urtwn_rxfilter_init(sc); 2824 2825 reg = urtwn_read_4(sc, R92C_RRSR); 2826 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 2827 urtwn_write_4(sc, R92C_RRSR, reg); 2828 2829 /* Set short/long retry limits. */ 2830 urtwn_write_2(sc, R92C_RL, 2831 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 2832 2833 /* Initialize EDCA parameters. */ 2834 urtwn_edca_init(sc); 2835 2836 /* Setup rate fallback. */ 2837 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 2838 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 2839 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 2840 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 2841 2842 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 2843 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 2844 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 2845 /* Set ACK timeout. */ 2846 urtwn_write_1(sc, R92C_ACKTO, 0x40); 2847 2848 /* Setup USB aggregation. */ 2849 reg = urtwn_read_4(sc, R92C_TDECTRL); 2850 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 2851 urtwn_write_4(sc, R92C_TDECTRL, reg); 2852 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 2853 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 2854 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 2855 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 2856 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 2857 R92C_USB_SPECIAL_OPTION_AGG_EN); 2858 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 2859 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 2860 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 2861 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 2862 2863 /* Initialize beacon parameters. */ 2864 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 2865 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 2866 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 2867 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 2868 2869 /* Setup AMPDU aggregation. */ 2870 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 2871 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 2872 urtwn_write_2(sc, 0x4ca, 0x0708); 2873 2874 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 2875 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 2876 2877 /* Load 8051 microcode. */ 2878 error = urtwn_load_firmware(sc); 2879 if (error != 0) 2880 goto fail; 2881 2882 /* Initialize MAC/BB/RF blocks. */ 2883 urtwn_mac_init(sc); 2884 urtwn_bb_init(sc); 2885 urtwn_rf_init(sc); 2886 2887 /* Turn CCK and OFDM blocks on. */ 2888 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 2889 reg |= R92C_RFMOD_CCK_EN; 2890 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 2891 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 2892 reg |= R92C_RFMOD_OFDM_EN; 2893 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 2894 2895 /* Clear per-station keys table. */ 2896 urtwn_cam_init(sc); 2897 2898 /* Enable hardware sequence numbering. */ 2899 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 2900 2901 /* Perform LO and IQ calibrations. */ 2902 urtwn_iq_calib(sc); 2903 /* Perform LC calibration. */ 2904 urtwn_lc_calib(sc); 2905 2906 /* Fix USB interference issue. */ 2907 urtwn_write_1(sc, 0xfe40, 0xe0); 2908 urtwn_write_1(sc, 0xfe41, 0x8d); 2909 urtwn_write_1(sc, 0xfe42, 0x80); 2910 2911 urtwn_pa_bias_init(sc); 2912 2913 /* Initialize GPIO setting. */ 2914 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 2915 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 2916 2917 /* Fix for lower temperature. */ 2918 urtwn_write_1(sc, 0x15, 0xe9); 2919 2920 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 2921 2922 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2923 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2924 2925 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2926fail: 2927 return; 2928} 2929 2930static void 2931urtwn_init(void *arg) 2932{ 2933 struct urtwn_softc *sc = arg; 2934 2935 URTWN_LOCK(sc); 2936 urtwn_init_locked(arg); 2937 URTWN_UNLOCK(sc); 2938} 2939 2940static void 2941urtwn_stop_locked(struct ifnet *ifp, int disable) 2942{ 2943 struct urtwn_softc *sc = ifp->if_softc; 2944 2945 (void)disable; 2946 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2947 2948 callout_stop(&sc->sc_watchdog_ch); 2949 urtwn_abort_xfers(sc); 2950} 2951 2952static void 2953urtwn_stop(struct ifnet *ifp, int disable) 2954{ 2955 struct urtwn_softc *sc = ifp->if_softc; 2956 2957 URTWN_LOCK(sc); 2958 urtwn_stop_locked(ifp, disable); 2959 URTWN_UNLOCK(sc); 2960} 2961 2962static void 2963urtwn_abort_xfers(struct urtwn_softc *sc) 2964{ 2965 int i; 2966 2967 URTWN_ASSERT_LOCKED(sc); 2968 2969 /* abort any pending transfers */ 2970 for (i = 0; i < URTWN_N_TRANSFER; i++) 2971 usbd_transfer_stop(sc->sc_xfer[i]); 2972} 2973 2974static int 2975urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2976 const struct ieee80211_bpf_params *params) 2977{ 2978 struct ieee80211com *ic = ni->ni_ic; 2979 struct ifnet *ifp = ic->ic_ifp; 2980 struct urtwn_softc *sc = ifp->if_softc; 2981 struct urtwn_data *bf; 2982 2983 /* prevent management frames from being sent if we're not ready */ 2984 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2985 m_freem(m); 2986 ieee80211_free_node(ni); 2987 return (ENETDOWN); 2988 } 2989 URTWN_LOCK(sc); 2990 bf = urtwn_getbuf(sc); 2991 if (bf == NULL) { 2992 ieee80211_free_node(ni); 2993 m_freem(m); 2994 URTWN_UNLOCK(sc); 2995 return (ENOBUFS); 2996 } 2997 2998 ifp->if_opackets++; 2999 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3000 ieee80211_free_node(ni); 3001 ifp->if_oerrors++; 3002 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3003 URTWN_UNLOCK(sc); 3004 return (EIO); 3005 } 3006 URTWN_UNLOCK(sc); 3007 3008 sc->sc_txtimer = 5; 3009 return (0); 3010} 3011 3012static device_method_t urtwn_methods[] = { 3013 /* Device interface */ 3014 DEVMETHOD(device_probe, urtwn_match), 3015 DEVMETHOD(device_attach, urtwn_attach), 3016 DEVMETHOD(device_detach, urtwn_detach), 3017 3018 { 0, 0 } 3019}; 3020 3021static driver_t urtwn_driver = { 3022 "urtwn", 3023 urtwn_methods, 3024 sizeof(struct urtwn_softc) 3025}; 3026 3027static devclass_t urtwn_devclass; 3028 3029DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3030MODULE_DEPEND(urtwn, usb, 1, 1, 1); 3031MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3032MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3033MODULE_VERSION(urtwn, 1); 3034