if_urtwn.c revision 302186
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2015 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#include <sys/cdefs.h> 22__FBSDID("$FreeBSD: head/sys/dev/urtwn/if_urtwn.c 302186 2016-06-24 23:43:19Z avos $"); 23 24/* 25 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 26 */ 27 28#include "opt_wlan.h" 29#include "opt_urtwn.h" 30 31#include <sys/param.h> 32#include <sys/sockio.h> 33#include <sys/sysctl.h> 34#include <sys/lock.h> 35#include <sys/mutex.h> 36#include <sys/condvar.h> 37#include <sys/mbuf.h> 38#include <sys/kernel.h> 39#include <sys/socket.h> 40#include <sys/systm.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/bus.h> 44#include <sys/endian.h> 45#include <sys/linker.h> 46#include <sys/firmware.h> 47#include <sys/kdb.h> 48 49#include <machine/bus.h> 50#include <machine/resource.h> 51#include <sys/rman.h> 52 53#include <net/bpf.h> 54#include <net/if.h> 55#include <net/if_var.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61 62#include <netinet/in.h> 63#include <netinet/in_systm.h> 64#include <netinet/in_var.h> 65#include <netinet/if_ether.h> 66#include <netinet/ip.h> 67 68#include <net80211/ieee80211_var.h> 69#include <net80211/ieee80211_regdomain.h> 70#include <net80211/ieee80211_radiotap.h> 71#include <net80211/ieee80211_ratectl.h> 72#ifdef IEEE80211_SUPPORT_SUPERG 73#include <net80211/ieee80211_superg.h> 74#endif 75 76#include <dev/usb/usb.h> 77#include <dev/usb/usbdi.h> 78#include <dev/usb/usb_device.h> 79#include "usbdevs.h" 80 81#include <dev/usb/usb_debug.h> 82 83#include <dev/urtwn/if_urtwnreg.h> 84#include <dev/urtwn/if_urtwnvar.h> 85 86#ifdef USB_DEBUG 87enum { 88 URTWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 89 URTWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 90 URTWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 91 URTWN_DEBUG_RA = 0x00000008, /* f/w rate adaptation setup */ 92 URTWN_DEBUG_USB = 0x00000010, /* usb requests */ 93 URTWN_DEBUG_FIRMWARE = 0x00000020, /* firmware(9) loading debug */ 94 URTWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 95 URTWN_DEBUG_INTR = 0x00000080, /* ISR */ 96 URTWN_DEBUG_TEMP = 0x00000100, /* temperature calibration */ 97 URTWN_DEBUG_ROM = 0x00000200, /* various ROM info */ 98 URTWN_DEBUG_KEY = 0x00000400, /* crypto keys management */ 99 URTWN_DEBUG_TXPWR = 0x00000800, /* dump Tx power values */ 100 URTWN_DEBUG_RSSI = 0x00001000, /* dump RSSI lookups */ 101 URTWN_DEBUG_ANY = 0xffffffff 102}; 103 104#define URTWN_DPRINTF(_sc, _m, ...) do { \ 105 if ((_sc)->sc_debug & (_m)) \ 106 device_printf((_sc)->sc_dev, __VA_ARGS__); \ 107} while(0) 108 109#else 110#define URTWN_DPRINTF(_sc, _m, ...) do { (void) sc; } while (0) 111#endif 112 113#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 114 115static int urtwn_enable_11n = 1; 116TUNABLE_INT("hw.usb.urtwn.enable_11n", &urtwn_enable_11n); 117 118/* various supported device vendors/products */ 119static const STRUCT_USB_HOST_ID urtwn_devs[] = { 120#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 121#define URTWN_RTL8188E_DEV(v,p) \ 122 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 123#define URTWN_RTL8188E 1 124 URTWN_DEV(ABOCOM, RTL8188CU_1), 125 URTWN_DEV(ABOCOM, RTL8188CU_2), 126 URTWN_DEV(ABOCOM, RTL8192CU), 127 URTWN_DEV(ASUS, RTL8192CU), 128 URTWN_DEV(ASUS, USBN10NANO), 129 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 130 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 131 URTWN_DEV(AZUREWAVE, RTL8188CU), 132 URTWN_DEV(BELKIN, F7D2102), 133 URTWN_DEV(BELKIN, RTL8188CU), 134 URTWN_DEV(BELKIN, RTL8192CU), 135 URTWN_DEV(CHICONY, RTL8188CUS_1), 136 URTWN_DEV(CHICONY, RTL8188CUS_2), 137 URTWN_DEV(CHICONY, RTL8188CUS_3), 138 URTWN_DEV(CHICONY, RTL8188CUS_4), 139 URTWN_DEV(CHICONY, RTL8188CUS_5), 140 URTWN_DEV(COREGA, RTL8192CU), 141 URTWN_DEV(DLINK, RTL8188CU), 142 URTWN_DEV(DLINK, RTL8192CU_1), 143 URTWN_DEV(DLINK, RTL8192CU_2), 144 URTWN_DEV(DLINK, RTL8192CU_3), 145 URTWN_DEV(DLINK, DWA131B), 146 URTWN_DEV(EDIMAX, EW7811UN), 147 URTWN_DEV(EDIMAX, RTL8192CU), 148 URTWN_DEV(FEIXUN, RTL8188CU), 149 URTWN_DEV(FEIXUN, RTL8192CU), 150 URTWN_DEV(GUILLEMOT, HWNUP150), 151 URTWN_DEV(HAWKING, RTL8192CU), 152 URTWN_DEV(HP3, RTL8188CU), 153 URTWN_DEV(NETGEAR, WNA1000M), 154 URTWN_DEV(NETGEAR, RTL8192CU), 155 URTWN_DEV(NETGEAR4, RTL8188CU), 156 URTWN_DEV(NOVATECH, RTL8188CU), 157 URTWN_DEV(PLANEX2, RTL8188CU_1), 158 URTWN_DEV(PLANEX2, RTL8188CU_2), 159 URTWN_DEV(PLANEX2, RTL8188CU_3), 160 URTWN_DEV(PLANEX2, RTL8188CU_4), 161 URTWN_DEV(PLANEX2, RTL8188CUS), 162 URTWN_DEV(PLANEX2, RTL8192CU), 163 URTWN_DEV(REALTEK, RTL8188CE_0), 164 URTWN_DEV(REALTEK, RTL8188CE_1), 165 URTWN_DEV(REALTEK, RTL8188CTV), 166 URTWN_DEV(REALTEK, RTL8188CU_0), 167 URTWN_DEV(REALTEK, RTL8188CU_1), 168 URTWN_DEV(REALTEK, RTL8188CU_2), 169 URTWN_DEV(REALTEK, RTL8188CU_3), 170 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 171 URTWN_DEV(REALTEK, RTL8188CUS), 172 URTWN_DEV(REALTEK, RTL8188RU_1), 173 URTWN_DEV(REALTEK, RTL8188RU_2), 174 URTWN_DEV(REALTEK, RTL8188RU_3), 175 URTWN_DEV(REALTEK, RTL8191CU), 176 URTWN_DEV(REALTEK, RTL8192CE), 177 URTWN_DEV(REALTEK, RTL8192CU), 178 URTWN_DEV(SITECOMEU, RTL8188CU_1), 179 URTWN_DEV(SITECOMEU, RTL8188CU_2), 180 URTWN_DEV(SITECOMEU, RTL8192CU), 181 URTWN_DEV(TRENDNET, RTL8188CU), 182 URTWN_DEV(TRENDNET, RTL8192CU), 183 URTWN_DEV(ZYXEL, RTL8192CU), 184 /* URTWN_RTL8188E */ 185 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 186 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 187 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 188 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 189 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 190 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 191#undef URTWN_RTL8188E_DEV 192#undef URTWN_DEV 193}; 194 195static device_probe_t urtwn_match; 196static device_attach_t urtwn_attach; 197static device_detach_t urtwn_detach; 198 199static usb_callback_t urtwn_bulk_tx_callback; 200static usb_callback_t urtwn_bulk_rx_callback; 201 202static void urtwn_sysctlattach(struct urtwn_softc *); 203static void urtwn_drain_mbufq(struct urtwn_softc *); 204static usb_error_t urtwn_do_request(struct urtwn_softc *, 205 struct usb_device_request *, void *); 206static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 207 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 208 const uint8_t [IEEE80211_ADDR_LEN], 209 const uint8_t [IEEE80211_ADDR_LEN]); 210static void urtwn_vap_delete(struct ieee80211vap *); 211static void urtwn_vap_clear_tx(struct urtwn_softc *, 212 struct ieee80211vap *); 213static void urtwn_vap_clear_tx_queue(struct urtwn_softc *, 214 urtwn_datahead *, struct ieee80211vap *); 215static struct mbuf * urtwn_rx_copy_to_mbuf(struct urtwn_softc *, 216 struct r92c_rx_stat *, int); 217static struct mbuf * urtwn_report_intr(struct usb_xfer *, 218 struct urtwn_data *); 219static struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int); 220static void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 221 void *); 222static struct ieee80211_node *urtwn_rx_frame(struct urtwn_softc *, 223 struct mbuf *, int8_t *); 224static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 225 int); 226static int urtwn_alloc_list(struct urtwn_softc *, 227 struct urtwn_data[], int, int); 228static int urtwn_alloc_rx_list(struct urtwn_softc *); 229static int urtwn_alloc_tx_list(struct urtwn_softc *); 230static void urtwn_free_list(struct urtwn_softc *, 231 struct urtwn_data data[], int); 232static void urtwn_free_rx_list(struct urtwn_softc *); 233static void urtwn_free_tx_list(struct urtwn_softc *); 234static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 235static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 236static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 237 uint8_t *, int); 238static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 239static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 240static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 241static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 242 uint8_t *, int); 243static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 244static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 245static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 246static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 247 const void *, int); 248static void urtwn_cmdq_cb(void *, int); 249static int urtwn_cmd_sleepable(struct urtwn_softc *, const void *, 250 size_t, CMD_FUNC_PROTO); 251static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 252 uint8_t, uint32_t); 253static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 254 uint8_t, uint32_t); 255static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 256static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 257 uint32_t); 258static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 259static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 260 uint8_t, uint8_t); 261#ifdef USB_DEBUG 262static void urtwn_dump_rom_contents(struct urtwn_softc *, 263 uint8_t *, uint16_t); 264#endif 265static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 266 uint16_t); 267static int urtwn_efuse_switch_power(struct urtwn_softc *); 268static int urtwn_read_chipid(struct urtwn_softc *); 269static int urtwn_read_rom(struct urtwn_softc *); 270static int urtwn_r88e_read_rom(struct urtwn_softc *); 271static int urtwn_ra_init(struct urtwn_softc *); 272static void urtwn_init_beacon(struct urtwn_softc *, 273 struct urtwn_vap *); 274static int urtwn_setup_beacon(struct urtwn_softc *, 275 struct ieee80211_node *); 276static void urtwn_update_beacon(struct ieee80211vap *, int); 277static int urtwn_tx_beacon(struct urtwn_softc *sc, 278 struct urtwn_vap *); 279static int urtwn_key_alloc(struct ieee80211vap *, 280 struct ieee80211_key *, ieee80211_keyix *, 281 ieee80211_keyix *); 282static void urtwn_key_set_cb(struct urtwn_softc *, 283 union sec_param *); 284static void urtwn_key_del_cb(struct urtwn_softc *, 285 union sec_param *); 286static int urtwn_key_set(struct ieee80211vap *, 287 const struct ieee80211_key *); 288static int urtwn_key_delete(struct ieee80211vap *, 289 const struct ieee80211_key *); 290static void urtwn_tsf_task_adhoc(void *, int); 291static void urtwn_tsf_sync_enable(struct urtwn_softc *, 292 struct ieee80211vap *); 293static void urtwn_get_tsf(struct urtwn_softc *, uint64_t *); 294static void urtwn_set_led(struct urtwn_softc *, int, int); 295static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 296static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 297 struct mbuf *, int, 298 const struct ieee80211_rx_stats *, int, int); 299static int urtwn_newstate(struct ieee80211vap *, 300 enum ieee80211_state, int); 301static void urtwn_calib_to(void *); 302static void urtwn_calib_cb(struct urtwn_softc *, 303 union sec_param *); 304static void urtwn_watchdog(void *); 305static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 306static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 307static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 308static int urtwn_tx_data(struct urtwn_softc *, 309 struct ieee80211_node *, struct mbuf *, 310 struct urtwn_data *); 311static int urtwn_tx_raw(struct urtwn_softc *, 312 struct ieee80211_node *, struct mbuf *, 313 struct urtwn_data *, 314 const struct ieee80211_bpf_params *); 315static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 316 uint8_t, struct urtwn_data *); 317static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 318static void urtwn_start(struct urtwn_softc *); 319static void urtwn_parent(struct ieee80211com *); 320static int urtwn_r92c_power_on(struct urtwn_softc *); 321static int urtwn_r88e_power_on(struct urtwn_softc *); 322static void urtwn_r92c_power_off(struct urtwn_softc *); 323static void urtwn_r88e_power_off(struct urtwn_softc *); 324static int urtwn_llt_init(struct urtwn_softc *); 325#ifndef URTWN_WITHOUT_UCODE 326static void urtwn_fw_reset(struct urtwn_softc *); 327static void urtwn_r88e_fw_reset(struct urtwn_softc *); 328static int urtwn_fw_loadpage(struct urtwn_softc *, int, 329 const uint8_t *, int); 330static int urtwn_load_firmware(struct urtwn_softc *); 331#endif 332static int urtwn_dma_init(struct urtwn_softc *); 333static int urtwn_mac_init(struct urtwn_softc *); 334static void urtwn_bb_init(struct urtwn_softc *); 335static void urtwn_rf_init(struct urtwn_softc *); 336static void urtwn_cam_init(struct urtwn_softc *); 337static int urtwn_cam_write(struct urtwn_softc *, uint32_t, 338 uint32_t); 339static void urtwn_pa_bias_init(struct urtwn_softc *); 340static void urtwn_rxfilter_init(struct urtwn_softc *); 341static void urtwn_edca_init(struct urtwn_softc *); 342static void urtwn_write_txpower(struct urtwn_softc *, int, 343 uint16_t[]); 344static void urtwn_get_txpower(struct urtwn_softc *, int, 345 struct ieee80211_channel *, 346 struct ieee80211_channel *, uint16_t[]); 347static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 348 struct ieee80211_channel *, 349 struct ieee80211_channel *, uint16_t[]); 350static void urtwn_set_txpower(struct urtwn_softc *, 351 struct ieee80211_channel *, 352 struct ieee80211_channel *); 353static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 354static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 355static void urtwn_scan_start(struct ieee80211com *); 356static void urtwn_scan_end(struct ieee80211com *); 357static void urtwn_getradiocaps(struct ieee80211com *, int, int *, 358 struct ieee80211_channel[]); 359static void urtwn_set_channel(struct ieee80211com *); 360static int urtwn_wme_update(struct ieee80211com *); 361static void urtwn_update_slot(struct ieee80211com *); 362static void urtwn_update_slot_cb(struct urtwn_softc *, 363 union sec_param *); 364static void urtwn_update_aifs(struct urtwn_softc *, uint8_t); 365static uint8_t urtwn_get_multi_pos(const uint8_t[]); 366static void urtwn_set_multi(struct urtwn_softc *); 367static void urtwn_set_promisc(struct urtwn_softc *); 368static void urtwn_update_promisc(struct ieee80211com *); 369static void urtwn_update_mcast(struct ieee80211com *); 370static struct ieee80211_node *urtwn_node_alloc(struct ieee80211vap *, 371 const uint8_t mac[IEEE80211_ADDR_LEN]); 372static void urtwn_newassoc(struct ieee80211_node *, int); 373static void urtwn_node_free(struct ieee80211_node *); 374static void urtwn_set_chan(struct urtwn_softc *, 375 struct ieee80211_channel *, 376 struct ieee80211_channel *); 377static void urtwn_iq_calib(struct urtwn_softc *); 378static void urtwn_lc_calib(struct urtwn_softc *); 379static void urtwn_temp_calib(struct urtwn_softc *); 380static void urtwn_setup_static_keys(struct urtwn_softc *, 381 struct urtwn_vap *); 382static int urtwn_init(struct urtwn_softc *); 383static void urtwn_stop(struct urtwn_softc *); 384static void urtwn_abort_xfers(struct urtwn_softc *); 385static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 386 const struct ieee80211_bpf_params *); 387static void urtwn_ms_delay(struct urtwn_softc *); 388 389/* Aliases. */ 390#define urtwn_bb_write urtwn_write_4 391#define urtwn_bb_read urtwn_read_4 392 393static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 394 [URTWN_BULK_RX] = { 395 .type = UE_BULK, 396 .endpoint = UE_ADDR_ANY, 397 .direction = UE_DIR_IN, 398 .bufsize = URTWN_RXBUFSZ, 399 .flags = { 400 .pipe_bof = 1, 401 .short_xfer_ok = 1 402 }, 403 .callback = urtwn_bulk_rx_callback, 404 }, 405 [URTWN_BULK_TX_BE] = { 406 .type = UE_BULK, 407 .endpoint = 0x03, 408 .direction = UE_DIR_OUT, 409 .bufsize = URTWN_TXBUFSZ, 410 .flags = { 411 .ext_buffer = 1, 412 .pipe_bof = 1, 413 .force_short_xfer = 1 414 }, 415 .callback = urtwn_bulk_tx_callback, 416 .timeout = URTWN_TX_TIMEOUT, /* ms */ 417 }, 418 [URTWN_BULK_TX_BK] = { 419 .type = UE_BULK, 420 .endpoint = 0x03, 421 .direction = UE_DIR_OUT, 422 .bufsize = URTWN_TXBUFSZ, 423 .flags = { 424 .ext_buffer = 1, 425 .pipe_bof = 1, 426 .force_short_xfer = 1, 427 }, 428 .callback = urtwn_bulk_tx_callback, 429 .timeout = URTWN_TX_TIMEOUT, /* ms */ 430 }, 431 [URTWN_BULK_TX_VI] = { 432 .type = UE_BULK, 433 .endpoint = 0x02, 434 .direction = UE_DIR_OUT, 435 .bufsize = URTWN_TXBUFSZ, 436 .flags = { 437 .ext_buffer = 1, 438 .pipe_bof = 1, 439 .force_short_xfer = 1 440 }, 441 .callback = urtwn_bulk_tx_callback, 442 .timeout = URTWN_TX_TIMEOUT, /* ms */ 443 }, 444 [URTWN_BULK_TX_VO] = { 445 .type = UE_BULK, 446 .endpoint = 0x02, 447 .direction = UE_DIR_OUT, 448 .bufsize = URTWN_TXBUFSZ, 449 .flags = { 450 .ext_buffer = 1, 451 .pipe_bof = 1, 452 .force_short_xfer = 1 453 }, 454 .callback = urtwn_bulk_tx_callback, 455 .timeout = URTWN_TX_TIMEOUT, /* ms */ 456 }, 457}; 458 459static const struct wme_to_queue { 460 uint16_t reg; 461 uint8_t qid; 462} wme2queue[WME_NUM_AC] = { 463 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 464 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 465 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 466 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 467}; 468 469static const uint8_t urtwn_chan_2ghz[] = 470 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 471 472static int 473urtwn_match(device_t self) 474{ 475 struct usb_attach_arg *uaa = device_get_ivars(self); 476 477 if (uaa->usb_mode != USB_MODE_HOST) 478 return (ENXIO); 479 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 480 return (ENXIO); 481 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 482 return (ENXIO); 483 484 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 485} 486 487static void 488urtwn_update_chw(struct ieee80211com *ic) 489{ 490} 491 492static int 493urtwn_ampdu_enable(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 494{ 495 496 /* We're driving this ourselves (eventually); don't involve net80211 */ 497 return (0); 498} 499 500static int 501urtwn_attach(device_t self) 502{ 503 struct usb_attach_arg *uaa = device_get_ivars(self); 504 struct urtwn_softc *sc = device_get_softc(self); 505 struct ieee80211com *ic = &sc->sc_ic; 506 int error; 507 508 device_set_usb_desc(self); 509 sc->sc_udev = uaa->device; 510 sc->sc_dev = self; 511 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 512 sc->chip |= URTWN_CHIP_88E; 513 514#ifdef USB_DEBUG 515 int debug; 516 if (resource_int_value(device_get_name(sc->sc_dev), 517 device_get_unit(sc->sc_dev), "debug", &debug) == 0) 518 sc->sc_debug = debug; 519#endif 520 521 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 522 MTX_NETWORK_LOCK, MTX_DEF); 523 URTWN_CMDQ_LOCK_INIT(sc); 524 URTWN_NT_LOCK_INIT(sc); 525 callout_init(&sc->sc_calib_to, 0); 526 callout_init(&sc->sc_watchdog_ch, 0); 527 mbufq_init(&sc->sc_snd, ifqmaxlen); 528 529 sc->sc_iface_index = URTWN_IFACE_INDEX; 530 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 531 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 532 if (error) { 533 device_printf(self, "could not allocate USB transfers, " 534 "err=%s\n", usbd_errstr(error)); 535 goto detach; 536 } 537 538 URTWN_LOCK(sc); 539 540 error = urtwn_read_chipid(sc); 541 if (error) { 542 device_printf(sc->sc_dev, "unsupported test chip\n"); 543 URTWN_UNLOCK(sc); 544 goto detach; 545 } 546 547 /* Determine number of Tx/Rx chains. */ 548 if (sc->chip & URTWN_CHIP_92C) { 549 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 550 sc->nrxchains = 2; 551 } else { 552 sc->ntxchains = 1; 553 sc->nrxchains = 1; 554 } 555 556 if (sc->chip & URTWN_CHIP_88E) 557 error = urtwn_r88e_read_rom(sc); 558 else 559 error = urtwn_read_rom(sc); 560 if (error != 0) { 561 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 562 __func__, error); 563 URTWN_UNLOCK(sc); 564 goto detach; 565 } 566 567 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 568 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 569 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 570 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 571 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 572 "8188CUS", sc->ntxchains, sc->nrxchains); 573 574 URTWN_UNLOCK(sc); 575 576 ic->ic_softc = sc; 577 ic->ic_name = device_get_nameunit(self); 578 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 579 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 580 581 /* set device capabilities */ 582 ic->ic_caps = 583 IEEE80211_C_STA /* station mode */ 584 | IEEE80211_C_MONITOR /* monitor mode */ 585 | IEEE80211_C_IBSS /* adhoc mode */ 586 | IEEE80211_C_HOSTAP /* hostap mode */ 587 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 588 | IEEE80211_C_SHSLOT /* short slot time supported */ 589#if 0 590 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 591#endif 592 | IEEE80211_C_WPA /* 802.11i */ 593 | IEEE80211_C_WME /* 802.11e */ 594 | IEEE80211_C_SWAMSDUTX /* Do software A-MSDU TX */ 595 | IEEE80211_C_FF /* Atheros fast-frames */ 596 ; 597 598 ic->ic_cryptocaps = 599 IEEE80211_CRYPTO_WEP | 600 IEEE80211_CRYPTO_TKIP | 601 IEEE80211_CRYPTO_AES_CCM; 602 603 /* Assume they're all 11n capable for now */ 604 if (urtwn_enable_11n) { 605 device_printf(self, "enabling 11n\n"); 606 ic->ic_htcaps = IEEE80211_HTC_HT | 607#if 0 608 IEEE80211_HTC_AMPDU | 609#endif 610 IEEE80211_HTC_AMSDU | 611 IEEE80211_HTCAP_MAXAMSDU_3839 | 612 IEEE80211_HTCAP_SMPS_OFF; 613 /* no HT40 just yet */ 614 // ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40; 615 616 /* XXX TODO: verify chains versus streams for urtwn */ 617 ic->ic_txstream = sc->ntxchains; 618 ic->ic_rxstream = sc->nrxchains; 619 } 620 621 /* XXX TODO: setup regdomain if R92C_CHANNEL_PLAN_BY_HW bit is set. */ 622 623 urtwn_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 624 ic->ic_channels); 625 626 ieee80211_ifattach(ic); 627 ic->ic_raw_xmit = urtwn_raw_xmit; 628 ic->ic_scan_start = urtwn_scan_start; 629 ic->ic_scan_end = urtwn_scan_end; 630 ic->ic_getradiocaps = urtwn_getradiocaps; 631 ic->ic_set_channel = urtwn_set_channel; 632 ic->ic_transmit = urtwn_transmit; 633 ic->ic_parent = urtwn_parent; 634 ic->ic_vap_create = urtwn_vap_create; 635 ic->ic_vap_delete = urtwn_vap_delete; 636 ic->ic_wme.wme_update = urtwn_wme_update; 637 ic->ic_updateslot = urtwn_update_slot; 638 ic->ic_update_promisc = urtwn_update_promisc; 639 ic->ic_update_mcast = urtwn_update_mcast; 640 if (sc->chip & URTWN_CHIP_88E) { 641 ic->ic_node_alloc = urtwn_node_alloc; 642 ic->ic_newassoc = urtwn_newassoc; 643 sc->sc_node_free = ic->ic_node_free; 644 ic->ic_node_free = urtwn_node_free; 645 } 646 ic->ic_update_chw = urtwn_update_chw; 647 ic->ic_ampdu_enable = urtwn_ampdu_enable; 648 649 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 650 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 651 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 652 URTWN_RX_RADIOTAP_PRESENT); 653 654 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc); 655 656 urtwn_sysctlattach(sc); 657 658 if (bootverbose) 659 ieee80211_announce(ic); 660 661 return (0); 662 663detach: 664 urtwn_detach(self); 665 return (ENXIO); /* failure */ 666} 667 668static void 669urtwn_sysctlattach(struct urtwn_softc *sc) 670{ 671#ifdef USB_DEBUG 672 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 673 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 674 675 SYSCTL_ADD_U32(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 676 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 677 "control debugging printfs"); 678#endif 679} 680 681static int 682urtwn_detach(device_t self) 683{ 684 struct urtwn_softc *sc = device_get_softc(self); 685 struct ieee80211com *ic = &sc->sc_ic; 686 687 /* Prevent further ioctls. */ 688 URTWN_LOCK(sc); 689 sc->sc_flags |= URTWN_DETACHED; 690 URTWN_UNLOCK(sc); 691 692 urtwn_stop(sc); 693 694 callout_drain(&sc->sc_watchdog_ch); 695 callout_drain(&sc->sc_calib_to); 696 697 /* stop all USB transfers */ 698 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 699 700 if (ic->ic_softc == sc) { 701 ieee80211_draintask(ic, &sc->cmdq_task); 702 ieee80211_ifdetach(ic); 703 } 704 705 URTWN_NT_LOCK_DESTROY(sc); 706 URTWN_CMDQ_LOCK_DESTROY(sc); 707 mtx_destroy(&sc->sc_mtx); 708 709 return (0); 710} 711 712static void 713urtwn_drain_mbufq(struct urtwn_softc *sc) 714{ 715 struct mbuf *m; 716 struct ieee80211_node *ni; 717 URTWN_ASSERT_LOCKED(sc); 718 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 719 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 720 m->m_pkthdr.rcvif = NULL; 721 ieee80211_free_node(ni); 722 m_freem(m); 723 } 724} 725 726static usb_error_t 727urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 728 void *data) 729{ 730 usb_error_t err; 731 int ntries = 10; 732 733 URTWN_ASSERT_LOCKED(sc); 734 735 while (ntries--) { 736 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 737 req, data, 0, NULL, 250 /* ms */); 738 if (err == 0) 739 break; 740 741 URTWN_DPRINTF(sc, URTWN_DEBUG_USB, 742 "%s: control request failed, %s (retries left: %d)\n", 743 __func__, usbd_errstr(err), ntries); 744 usb_pause_mtx(&sc->sc_mtx, hz / 100); 745 } 746 return (err); 747} 748 749static struct ieee80211vap * 750urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 751 enum ieee80211_opmode opmode, int flags, 752 const uint8_t bssid[IEEE80211_ADDR_LEN], 753 const uint8_t mac[IEEE80211_ADDR_LEN]) 754{ 755 struct urtwn_softc *sc = ic->ic_softc; 756 struct urtwn_vap *uvp; 757 struct ieee80211vap *vap; 758 759 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 760 return (NULL); 761 762 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 763 vap = &uvp->vap; 764 /* enable s/w bmiss handling for sta mode */ 765 766 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 767 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 768 /* out of memory */ 769 free(uvp, M_80211_VAP); 770 return (NULL); 771 } 772 773 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 774 urtwn_init_beacon(sc, uvp); 775 776 /* override state transition machine */ 777 uvp->newstate = vap->iv_newstate; 778 vap->iv_newstate = urtwn_newstate; 779 vap->iv_update_beacon = urtwn_update_beacon; 780 vap->iv_key_alloc = urtwn_key_alloc; 781 vap->iv_key_set = urtwn_key_set; 782 vap->iv_key_delete = urtwn_key_delete; 783 784 /* 802.11n parameters */ 785 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_16; 786 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 787 788 if (opmode == IEEE80211_M_IBSS) { 789 uvp->recv_mgmt = vap->iv_recv_mgmt; 790 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 791 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 792 } 793 794 if (URTWN_CHIP_HAS_RATECTL(sc)) 795 ieee80211_ratectl_init(vap); 796 /* complete setup */ 797 ieee80211_vap_attach(vap, ieee80211_media_change, 798 ieee80211_media_status, mac); 799 ic->ic_opmode = opmode; 800 return (vap); 801} 802 803static void 804urtwn_vap_delete(struct ieee80211vap *vap) 805{ 806 struct ieee80211com *ic = vap->iv_ic; 807 struct urtwn_softc *sc = ic->ic_softc; 808 struct urtwn_vap *uvp = URTWN_VAP(vap); 809 810 /* Guarantee that nothing will go through this vap. */ 811 ieee80211_new_state(vap, IEEE80211_S_INIT, -1); 812 ieee80211_draintask(ic, &vap->iv_nstate_task); 813 814 URTWN_LOCK(sc); 815 if (uvp->bcn_mbuf != NULL) 816 m_freem(uvp->bcn_mbuf); 817 /* Cancel any unfinished Tx. */ 818 urtwn_vap_clear_tx(sc, vap); 819 URTWN_UNLOCK(sc); 820 if (vap->iv_opmode == IEEE80211_M_IBSS) 821 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 822 if (URTWN_CHIP_HAS_RATECTL(sc)) 823 ieee80211_ratectl_deinit(vap); 824 ieee80211_vap_detach(vap); 825 free(uvp, M_80211_VAP); 826} 827 828static void 829urtwn_vap_clear_tx(struct urtwn_softc *sc, struct ieee80211vap *vap) 830{ 831 832 URTWN_ASSERT_LOCKED(sc); 833 834 urtwn_vap_clear_tx_queue(sc, &sc->sc_tx_active, vap); 835 urtwn_vap_clear_tx_queue(sc, &sc->sc_tx_pending, vap); 836} 837 838static void 839urtwn_vap_clear_tx_queue(struct urtwn_softc *sc, urtwn_datahead *head, 840 struct ieee80211vap *vap) 841{ 842 struct urtwn_data *dp, *tmp; 843 844 STAILQ_FOREACH_SAFE(dp, head, next, tmp) { 845 if (dp->ni != NULL) { 846 if (dp->ni->ni_vap == vap) { 847 ieee80211_free_node(dp->ni); 848 dp->ni = NULL; 849 850 if (dp->m != NULL) { 851 m_freem(dp->m); 852 dp->m = NULL; 853 } 854 855 STAILQ_REMOVE(head, dp, urtwn_data, next); 856 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, dp, 857 next); 858 } 859 } 860 } 861} 862 863static struct mbuf * 864urtwn_rx_copy_to_mbuf(struct urtwn_softc *sc, struct r92c_rx_stat *stat, 865 int totlen) 866{ 867 struct ieee80211com *ic = &sc->sc_ic; 868 struct mbuf *m; 869 uint32_t rxdw0; 870 int pktlen; 871 872 /* 873 * don't pass packets to the ieee80211 framework if the driver isn't 874 * RUNNING. 875 */ 876 if (!(sc->sc_flags & URTWN_RUNNING)) 877 return (NULL); 878 879 rxdw0 = le32toh(stat->rxdw0); 880 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 881 /* 882 * This should not happen since we setup our Rx filter 883 * to not receive these frames. 884 */ 885 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 886 "%s: RX flags error (%s)\n", __func__, 887 rxdw0 & R92C_RXDW0_CRCERR ? "CRC" : "ICV"); 888 goto fail; 889 } 890 891 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 892 if (pktlen < sizeof(struct ieee80211_frame_ack)) { 893 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 894 "%s: frame is too short: %d\n", __func__, pktlen); 895 goto fail; 896 } 897 898 m = m_get2(totlen, M_NOWAIT, MT_DATA, M_PKTHDR); 899 if (__predict_false(m == NULL)) { 900 device_printf(sc->sc_dev, "%s: could not allocate RX mbuf\n", 901 __func__); 902 goto fail; 903 } 904 905 /* Finalize mbuf. */ 906 memcpy(mtod(m, uint8_t *), (uint8_t *)stat, totlen); 907 m->m_pkthdr.len = m->m_len = totlen; 908 909 return (m); 910fail: 911 counter_u64_add(ic->ic_ierrors, 1); 912 return (NULL); 913} 914 915static struct mbuf * 916urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data) 917{ 918 struct urtwn_softc *sc = data->sc; 919 struct ieee80211com *ic = &sc->sc_ic; 920 struct r92c_rx_stat *stat; 921 uint8_t *buf; 922 int len; 923 924 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 925 926 if (len < sizeof(*stat)) { 927 counter_u64_add(ic->ic_ierrors, 1); 928 return (NULL); 929 } 930 931 buf = data->buf; 932 stat = (struct r92c_rx_stat *)buf; 933 934 /* 935 * For 88E chips we can tie the FF flushing here; 936 * this is where we do know exactly how deep the 937 * transmit queue is. 938 * 939 * But it won't work for R92 chips, so we can't 940 * take the easy way out. 941 */ 942 943 if (sc->chip & URTWN_CHIP_88E) { 944 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 945 946 switch (report_sel) { 947 case R88E_RXDW3_RPT_RX: 948 return (urtwn_rxeof(sc, buf, len)); 949 case R88E_RXDW3_RPT_TX1: 950 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 951 break; 952 default: 953 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, 954 "%s: case %d was not handled\n", __func__, 955 report_sel); 956 break; 957 } 958 } else 959 return (urtwn_rxeof(sc, buf, len)); 960 961 return (NULL); 962} 963 964static struct mbuf * 965urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len) 966{ 967 struct r92c_rx_stat *stat; 968 struct mbuf *m, *m0 = NULL, *prevm = NULL; 969 uint32_t rxdw0; 970 int totlen, pktlen, infosz, npkts; 971 972 /* Get the number of encapsulated frames. */ 973 stat = (struct r92c_rx_stat *)buf; 974 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 975 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 976 "%s: Rx %d frames in one chunk\n", __func__, npkts); 977 978 /* Process all of them. */ 979 while (npkts-- > 0) { 980 if (len < sizeof(*stat)) 981 break; 982 stat = (struct r92c_rx_stat *)buf; 983 rxdw0 = le32toh(stat->rxdw0); 984 985 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 986 if (pktlen == 0) 987 break; 988 989 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 990 991 /* Make sure everything fits in xfer. */ 992 totlen = sizeof(*stat) + infosz + pktlen; 993 if (totlen > len) 994 break; 995 996 m = urtwn_rx_copy_to_mbuf(sc, stat, totlen); 997 if (m0 == NULL) 998 m0 = m; 999 if (prevm == NULL) 1000 prevm = m; 1001 else { 1002 prevm->m_next = m; 1003 prevm = m; 1004 } 1005 1006 /* Next chunk is 128-byte aligned. */ 1007 totlen = (totlen + 127) & ~127; 1008 buf += totlen; 1009 len -= totlen; 1010 } 1011 1012 return (m0); 1013} 1014 1015static void 1016urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 1017{ 1018 struct r88e_tx_rpt_ccx *rpt = arg; 1019 struct ieee80211vap *vap; 1020 struct ieee80211_node *ni; 1021 uint8_t macid; 1022 int ntries; 1023 1024 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 1025 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 1026 1027 URTWN_NT_LOCK(sc); 1028 ni = sc->node_list[macid]; 1029 if (ni != NULL) { 1030 vap = ni->ni_vap; 1031 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: frame for macid %d was" 1032 "%s sent (%d retries)\n", __func__, macid, 1033 (rpt->rptb1 & R88E_RPTB1_PKT_OK) ? "" : " not", 1034 ntries); 1035 1036 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 1037 ieee80211_ratectl_tx_complete(vap, ni, 1038 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 1039 } else { 1040 ieee80211_ratectl_tx_complete(vap, ni, 1041 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 1042 } 1043 } else { 1044 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: macid %d, ni is NULL\n", 1045 __func__, macid); 1046 } 1047 URTWN_NT_UNLOCK(sc); 1048} 1049 1050static struct ieee80211_node * 1051urtwn_rx_frame(struct urtwn_softc *sc, struct mbuf *m, int8_t *rssi_p) 1052{ 1053 struct ieee80211com *ic = &sc->sc_ic; 1054 struct ieee80211_frame_min *wh; 1055 struct r92c_rx_stat *stat; 1056 uint32_t rxdw0, rxdw3; 1057 uint8_t rate, cipher; 1058 int8_t rssi = -127; 1059 int infosz; 1060 1061 stat = mtod(m, struct r92c_rx_stat *); 1062 rxdw0 = le32toh(stat->rxdw0); 1063 rxdw3 = le32toh(stat->rxdw3); 1064 1065 rate = MS(rxdw3, R92C_RXDW3_RATE); 1066 cipher = MS(rxdw0, R92C_RXDW0_CIPHER); 1067 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1068 1069 /* Get RSSI from PHY status descriptor if present. */ 1070 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1071 if (sc->chip & URTWN_CHIP_88E) 1072 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 1073 else 1074 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 1075 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: rssi=%d\n", __func__, rssi); 1076 /* Update our average RSSI. */ 1077 urtwn_update_avgrssi(sc, rate, rssi); 1078 } 1079 1080 if (ieee80211_radiotap_active(ic)) { 1081 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1082 1083 tap->wr_flags = 0; 1084 1085 urtwn_get_tsf(sc, &tap->wr_tsft); 1086 if (__predict_false(le32toh((uint32_t)tap->wr_tsft) < 1087 le32toh(stat->rxdw5))) { 1088 tap->wr_tsft = le32toh(tap->wr_tsft >> 32) - 1; 1089 tap->wr_tsft = (uint64_t)htole32(tap->wr_tsft) << 32; 1090 } else 1091 tap->wr_tsft &= 0xffffffff00000000; 1092 tap->wr_tsft += stat->rxdw5; 1093 1094 /* XXX 20/40? */ 1095 /* XXX shortgi? */ 1096 1097 /* Map HW rate index to 802.11 rate. */ 1098 if (!(rxdw3 & R92C_RXDW3_HT)) { 1099 tap->wr_rate = ridx2rate[rate]; 1100 } else if (rate >= 12) { /* MCS0~15. */ 1101 /* Bit 7 set means HT MCS instead of rate. */ 1102 tap->wr_rate = 0x80 | (rate - 12); 1103 } 1104 1105 /* XXX TODO: this isn't right; should use the last good RSSI */ 1106 tap->wr_dbm_antsignal = rssi; 1107 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 1108 } 1109 1110 *rssi_p = rssi; 1111 1112 /* Drop descriptor. */ 1113 m_adj(m, sizeof(*stat) + infosz); 1114 wh = mtod(m, struct ieee80211_frame_min *); 1115 1116 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1117 cipher != R92C_CAM_ALGO_NONE) { 1118 m->m_flags |= M_WEP; 1119 } 1120 1121 if (m->m_len >= sizeof(*wh)) 1122 return (ieee80211_find_rxnode(ic, wh)); 1123 1124 return (NULL); 1125} 1126 1127static void 1128urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 1129{ 1130 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1131 struct ieee80211com *ic = &sc->sc_ic; 1132 struct ieee80211_node *ni; 1133 struct mbuf *m = NULL, *next; 1134 struct urtwn_data *data; 1135 int8_t nf, rssi; 1136 1137 URTWN_ASSERT_LOCKED(sc); 1138 1139 switch (USB_GET_STATE(xfer)) { 1140 case USB_ST_TRANSFERRED: 1141 data = STAILQ_FIRST(&sc->sc_rx_active); 1142 if (data == NULL) 1143 goto tr_setup; 1144 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1145 m = urtwn_report_intr(xfer, data); 1146 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1147 /* FALLTHROUGH */ 1148 case USB_ST_SETUP: 1149tr_setup: 1150 data = STAILQ_FIRST(&sc->sc_rx_inactive); 1151 if (data == NULL) { 1152 KASSERT(m == NULL, ("mbuf isn't NULL")); 1153 goto finish; 1154 } 1155 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 1156 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 1157 usbd_xfer_set_frame_data(xfer, 0, data->buf, 1158 usbd_xfer_max_len(xfer)); 1159 usbd_transfer_submit(xfer); 1160 1161 /* 1162 * To avoid LOR we should unlock our private mutex here to call 1163 * ieee80211_input() because here is at the end of a USB 1164 * callback and safe to unlock. 1165 */ 1166 while (m != NULL) { 1167 next = m->m_next; 1168 m->m_next = NULL; 1169 1170 ni = urtwn_rx_frame(sc, m, &rssi); 1171 1172 /* Store a global last-good RSSI */ 1173 if (rssi != -127) 1174 sc->last_rssi = rssi; 1175 1176 URTWN_UNLOCK(sc); 1177 1178 nf = URTWN_NOISE_FLOOR; 1179 if (ni != NULL) { 1180 if (rssi != -127) 1181 URTWN_NODE(ni)->last_rssi = rssi; 1182 if (ni->ni_flags & IEEE80211_NODE_HT) 1183 m->m_flags |= M_AMPDU; 1184 (void)ieee80211_input(ni, m, 1185 URTWN_NODE(ni)->last_rssi - nf, nf); 1186 ieee80211_free_node(ni); 1187 } else { 1188 /* Use last good global RSSI */ 1189 (void)ieee80211_input_all(ic, m, 1190 sc->last_rssi - nf, nf); 1191 } 1192 URTWN_LOCK(sc); 1193 m = next; 1194 } 1195 break; 1196 default: 1197 /* needs it to the inactive queue due to a error. */ 1198 data = STAILQ_FIRST(&sc->sc_rx_active); 1199 if (data != NULL) { 1200 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1201 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1202 } 1203 if (error != USB_ERR_CANCELLED) { 1204 usbd_xfer_set_stall(xfer); 1205 counter_u64_add(ic->ic_ierrors, 1); 1206 goto tr_setup; 1207 } 1208 break; 1209 } 1210finish: 1211 /* Finished receive; age anything left on the FF queue by a little bump */ 1212 /* 1213 * XXX TODO: just make this a callout timer schedule so we can 1214 * flush the FF staging queue if we're approaching idle. 1215 */ 1216#ifdef IEEE80211_SUPPORT_SUPERG 1217 URTWN_UNLOCK(sc); 1218 ieee80211_ff_age_all(ic, 1); 1219 URTWN_LOCK(sc); 1220#endif 1221 1222 /* Kick-start more transmit in case we stalled */ 1223 urtwn_start(sc); 1224} 1225 1226static void 1227urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 1228{ 1229 1230 URTWN_ASSERT_LOCKED(sc); 1231 1232 if (data->ni != NULL) /* not a beacon frame */ 1233 ieee80211_tx_complete(data->ni, data->m, status); 1234 1235 if (sc->sc_tx_n_active > 0) 1236 sc->sc_tx_n_active--; 1237 1238 data->ni = NULL; 1239 data->m = NULL; 1240 1241 sc->sc_txtimer = 0; 1242 1243 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 1244} 1245 1246static int 1247urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1248 int ndata, int maxsz) 1249{ 1250 int i, error; 1251 1252 for (i = 0; i < ndata; i++) { 1253 struct urtwn_data *dp = &data[i]; 1254 dp->sc = sc; 1255 dp->m = NULL; 1256 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1257 if (dp->buf == NULL) { 1258 device_printf(sc->sc_dev, 1259 "could not allocate buffer\n"); 1260 error = ENOMEM; 1261 goto fail; 1262 } 1263 dp->ni = NULL; 1264 } 1265 1266 return (0); 1267fail: 1268 urtwn_free_list(sc, data, ndata); 1269 return (error); 1270} 1271 1272static int 1273urtwn_alloc_rx_list(struct urtwn_softc *sc) 1274{ 1275 int error, i; 1276 1277 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1278 URTWN_RXBUFSZ); 1279 if (error != 0) 1280 return (error); 1281 1282 STAILQ_INIT(&sc->sc_rx_active); 1283 STAILQ_INIT(&sc->sc_rx_inactive); 1284 1285 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1286 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1287 1288 return (0); 1289} 1290 1291static int 1292urtwn_alloc_tx_list(struct urtwn_softc *sc) 1293{ 1294 int error, i; 1295 1296 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1297 URTWN_TXBUFSZ); 1298 if (error != 0) 1299 return (error); 1300 1301 STAILQ_INIT(&sc->sc_tx_active); 1302 STAILQ_INIT(&sc->sc_tx_inactive); 1303 STAILQ_INIT(&sc->sc_tx_pending); 1304 1305 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1306 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1307 1308 return (0); 1309} 1310 1311static void 1312urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1313{ 1314 int i; 1315 1316 for (i = 0; i < ndata; i++) { 1317 struct urtwn_data *dp = &data[i]; 1318 1319 if (dp->buf != NULL) { 1320 free(dp->buf, M_USBDEV); 1321 dp->buf = NULL; 1322 } 1323 if (dp->ni != NULL) { 1324 ieee80211_free_node(dp->ni); 1325 dp->ni = NULL; 1326 } 1327 } 1328} 1329 1330static void 1331urtwn_free_rx_list(struct urtwn_softc *sc) 1332{ 1333 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1334 1335 STAILQ_INIT(&sc->sc_rx_active); 1336 STAILQ_INIT(&sc->sc_rx_inactive); 1337} 1338 1339static void 1340urtwn_free_tx_list(struct urtwn_softc *sc) 1341{ 1342 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1343 1344 STAILQ_INIT(&sc->sc_tx_active); 1345 STAILQ_INIT(&sc->sc_tx_inactive); 1346 STAILQ_INIT(&sc->sc_tx_pending); 1347} 1348 1349static void 1350urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1351{ 1352 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1353#ifdef IEEE80211_SUPPORT_SUPERG 1354 struct ieee80211com *ic = &sc->sc_ic; 1355#endif 1356 struct urtwn_data *data; 1357 1358 URTWN_ASSERT_LOCKED(sc); 1359 1360 switch (USB_GET_STATE(xfer)){ 1361 case USB_ST_TRANSFERRED: 1362 data = STAILQ_FIRST(&sc->sc_tx_active); 1363 if (data == NULL) 1364 goto tr_setup; 1365 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1366 urtwn_txeof(sc, data, 0); 1367 /* FALLTHROUGH */ 1368 case USB_ST_SETUP: 1369tr_setup: 1370 data = STAILQ_FIRST(&sc->sc_tx_pending); 1371 if (data == NULL) { 1372 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1373 "%s: empty pending queue\n", __func__); 1374 sc->sc_tx_n_active = 0; 1375 goto finish; 1376 } 1377 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1378 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1379 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1380 usbd_transfer_submit(xfer); 1381 sc->sc_tx_n_active++; 1382 break; 1383 default: 1384 data = STAILQ_FIRST(&sc->sc_tx_active); 1385 if (data == NULL) 1386 goto tr_setup; 1387 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1388 urtwn_txeof(sc, data, 1); 1389 if (error != USB_ERR_CANCELLED) { 1390 usbd_xfer_set_stall(xfer); 1391 goto tr_setup; 1392 } 1393 break; 1394 } 1395finish: 1396#ifdef IEEE80211_SUPPORT_SUPERG 1397 /* 1398 * If the TX active queue drops below a certain 1399 * threshold, ensure we age fast-frames out so they're 1400 * transmitted. 1401 */ 1402 if (sc->sc_tx_n_active <= 1) { 1403 /* XXX ew - net80211 should defer this for us! */ 1404 1405 /* 1406 * Note: this sc_tx_n_active currently tracks 1407 * the number of pending transmit submissions 1408 * and not the actual depth of the TX frames 1409 * pending to the hardware. That means that 1410 * we're going to end up with some sub-optimal 1411 * aggregation behaviour. 1412 */ 1413 /* 1414 * XXX TODO: just make this a callout timer schedule so we can 1415 * flush the FF staging queue if we're approaching idle. 1416 */ 1417 URTWN_UNLOCK(sc); 1418 ieee80211_ff_flush(ic, WME_AC_VO); 1419 ieee80211_ff_flush(ic, WME_AC_VI); 1420 ieee80211_ff_flush(ic, WME_AC_BE); 1421 ieee80211_ff_flush(ic, WME_AC_BK); 1422 URTWN_LOCK(sc); 1423 } 1424#endif 1425 /* Kick-start more transmit */ 1426 urtwn_start(sc); 1427} 1428 1429static struct urtwn_data * 1430_urtwn_getbuf(struct urtwn_softc *sc) 1431{ 1432 struct urtwn_data *bf; 1433 1434 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1435 if (bf != NULL) 1436 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1437 else { 1438 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1439 "%s: out of xmit buffers\n", __func__); 1440 } 1441 return (bf); 1442} 1443 1444static struct urtwn_data * 1445urtwn_getbuf(struct urtwn_softc *sc) 1446{ 1447 struct urtwn_data *bf; 1448 1449 URTWN_ASSERT_LOCKED(sc); 1450 1451 bf = _urtwn_getbuf(sc); 1452 if (bf == NULL) { 1453 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: stop queue\n", 1454 __func__); 1455 } 1456 return (bf); 1457} 1458 1459static usb_error_t 1460urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1461 int len) 1462{ 1463 usb_device_request_t req; 1464 1465 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1466 req.bRequest = R92C_REQ_REGS; 1467 USETW(req.wValue, addr); 1468 USETW(req.wIndex, 0); 1469 USETW(req.wLength, len); 1470 return (urtwn_do_request(sc, &req, buf)); 1471} 1472 1473static usb_error_t 1474urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1475{ 1476 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1477} 1478 1479static usb_error_t 1480urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1481{ 1482 val = htole16(val); 1483 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1484} 1485 1486static usb_error_t 1487urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1488{ 1489 val = htole32(val); 1490 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1491} 1492 1493static usb_error_t 1494urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1495 int len) 1496{ 1497 usb_device_request_t req; 1498 1499 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1500 req.bRequest = R92C_REQ_REGS; 1501 USETW(req.wValue, addr); 1502 USETW(req.wIndex, 0); 1503 USETW(req.wLength, len); 1504 return (urtwn_do_request(sc, &req, buf)); 1505} 1506 1507static uint8_t 1508urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1509{ 1510 uint8_t val; 1511 1512 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1513 return (0xff); 1514 return (val); 1515} 1516 1517static uint16_t 1518urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1519{ 1520 uint16_t val; 1521 1522 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1523 return (0xffff); 1524 return (le16toh(val)); 1525} 1526 1527static uint32_t 1528urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1529{ 1530 uint32_t val; 1531 1532 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1533 return (0xffffffff); 1534 return (le32toh(val)); 1535} 1536 1537static int 1538urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1539{ 1540 struct r92c_fw_cmd cmd; 1541 usb_error_t error; 1542 int ntries; 1543 1544 if (!(sc->sc_flags & URTWN_FW_LOADED)) { 1545 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, "%s: firmware " 1546 "was not loaded; command (id %d) will be discarded\n", 1547 __func__, id); 1548 return (0); 1549 } 1550 1551 /* Wait for current FW box to be empty. */ 1552 for (ntries = 0; ntries < 100; ntries++) { 1553 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1554 break; 1555 urtwn_ms_delay(sc); 1556 } 1557 if (ntries == 100) { 1558 device_printf(sc->sc_dev, 1559 "could not send firmware command\n"); 1560 return (ETIMEDOUT); 1561 } 1562 memset(&cmd, 0, sizeof(cmd)); 1563 cmd.id = id; 1564 if (len > 3) 1565 cmd.id |= R92C_CMD_FLAG_EXT; 1566 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1567 memcpy(cmd.msg, buf, len); 1568 1569 /* Write the first word last since that will trigger the FW. */ 1570 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1571 (uint8_t *)&cmd + 4, 2); 1572 if (error != USB_ERR_NORMAL_COMPLETION) 1573 return (EIO); 1574 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1575 (uint8_t *)&cmd + 0, 4); 1576 if (error != USB_ERR_NORMAL_COMPLETION) 1577 return (EIO); 1578 1579 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1580 return (0); 1581} 1582 1583static void 1584urtwn_cmdq_cb(void *arg, int pending) 1585{ 1586 struct urtwn_softc *sc = arg; 1587 struct urtwn_cmdq *item; 1588 1589 /* 1590 * Device must be powered on (via urtwn_power_on()) 1591 * before any command may be sent. 1592 */ 1593 URTWN_LOCK(sc); 1594 if (!(sc->sc_flags & URTWN_RUNNING)) { 1595 URTWN_UNLOCK(sc); 1596 return; 1597 } 1598 1599 URTWN_CMDQ_LOCK(sc); 1600 while (sc->cmdq[sc->cmdq_first].func != NULL) { 1601 item = &sc->cmdq[sc->cmdq_first]; 1602 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE; 1603 URTWN_CMDQ_UNLOCK(sc); 1604 1605 item->func(sc, &item->data); 1606 1607 URTWN_CMDQ_LOCK(sc); 1608 memset(item, 0, sizeof (*item)); 1609 } 1610 URTWN_CMDQ_UNLOCK(sc); 1611 URTWN_UNLOCK(sc); 1612} 1613 1614static int 1615urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len, 1616 CMD_FUNC_PROTO) 1617{ 1618 struct ieee80211com *ic = &sc->sc_ic; 1619 1620 KASSERT(len <= sizeof(union sec_param), ("buffer overflow")); 1621 1622 URTWN_CMDQ_LOCK(sc); 1623 if (sc->cmdq[sc->cmdq_last].func != NULL) { 1624 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__); 1625 URTWN_CMDQ_UNLOCK(sc); 1626 1627 return (EAGAIN); 1628 } 1629 1630 if (ptr != NULL) 1631 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len); 1632 sc->cmdq[sc->cmdq_last].func = func; 1633 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE; 1634 URTWN_CMDQ_UNLOCK(sc); 1635 1636 ieee80211_runtask(ic, &sc->cmdq_task); 1637 1638 return (0); 1639} 1640 1641static __inline void 1642urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1643{ 1644 1645 sc->sc_rf_write(sc, chain, addr, val); 1646} 1647 1648static void 1649urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1650 uint32_t val) 1651{ 1652 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1653 SM(R92C_LSSI_PARAM_ADDR, addr) | 1654 SM(R92C_LSSI_PARAM_DATA, val)); 1655} 1656 1657static void 1658urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1659uint32_t val) 1660{ 1661 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1662 SM(R88E_LSSI_PARAM_ADDR, addr) | 1663 SM(R92C_LSSI_PARAM_DATA, val)); 1664} 1665 1666static uint32_t 1667urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1668{ 1669 uint32_t reg[R92C_MAX_CHAINS], val; 1670 1671 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1672 if (chain != 0) 1673 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1674 1675 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1676 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1677 urtwn_ms_delay(sc); 1678 1679 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1680 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1681 R92C_HSSI_PARAM2_READ_EDGE); 1682 urtwn_ms_delay(sc); 1683 1684 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1685 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1686 urtwn_ms_delay(sc); 1687 1688 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1689 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1690 else 1691 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1692 return (MS(val, R92C_LSSI_READBACK_DATA)); 1693} 1694 1695static int 1696urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1697{ 1698 usb_error_t error; 1699 int ntries; 1700 1701 error = urtwn_write_4(sc, R92C_LLT_INIT, 1702 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1703 SM(R92C_LLT_INIT_ADDR, addr) | 1704 SM(R92C_LLT_INIT_DATA, data)); 1705 if (error != USB_ERR_NORMAL_COMPLETION) 1706 return (EIO); 1707 /* Wait for write operation to complete. */ 1708 for (ntries = 0; ntries < 20; ntries++) { 1709 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1710 R92C_LLT_INIT_OP_NO_ACTIVE) 1711 return (0); 1712 urtwn_ms_delay(sc); 1713 } 1714 return (ETIMEDOUT); 1715} 1716 1717static int 1718urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1719{ 1720 uint32_t reg; 1721 usb_error_t error; 1722 int ntries; 1723 1724 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1725 return (EFAULT); 1726 1727 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1728 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1729 reg &= ~R92C_EFUSE_CTRL_VALID; 1730 1731 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1732 if (error != USB_ERR_NORMAL_COMPLETION) 1733 return (EIO); 1734 /* Wait for read operation to complete. */ 1735 for (ntries = 0; ntries < 100; ntries++) { 1736 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1737 if (reg & R92C_EFUSE_CTRL_VALID) 1738 break; 1739 urtwn_ms_delay(sc); 1740 } 1741 if (ntries == 100) { 1742 device_printf(sc->sc_dev, 1743 "could not read efuse byte at address 0x%x\n", 1744 sc->last_rom_addr); 1745 return (ETIMEDOUT); 1746 } 1747 1748 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1749 sc->last_rom_addr++; 1750 1751 return (0); 1752} 1753 1754static int 1755urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1756 uint8_t msk) 1757{ 1758 uint8_t reg; 1759 int i, error; 1760 1761 for (i = 0; i < 4; i++) { 1762 if (msk & (1 << i)) 1763 continue; 1764 error = urtwn_efuse_read_next(sc, ®); 1765 if (error != 0) 1766 return (error); 1767 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1768 off * 8 + i * 2, reg); 1769 rom[off * 8 + i * 2 + 0] = reg; 1770 1771 error = urtwn_efuse_read_next(sc, ®); 1772 if (error != 0) 1773 return (error); 1774 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1775 off * 8 + i * 2 + 1, reg); 1776 rom[off * 8 + i * 2 + 1] = reg; 1777 } 1778 1779 return (0); 1780} 1781 1782#ifdef USB_DEBUG 1783static void 1784urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1785{ 1786 int i; 1787 1788 /* Dump ROM contents. */ 1789 device_printf(sc->sc_dev, "%s:", __func__); 1790 for (i = 0; i < size; i++) { 1791 if (i % 32 == 0) 1792 printf("\n%03X: ", i); 1793 else if (i % 4 == 0) 1794 printf(" "); 1795 1796 printf("%02X", rom[i]); 1797 } 1798 printf("\n"); 1799} 1800#endif 1801 1802static int 1803urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1804{ 1805#define URTWN_CHK(res) do { \ 1806 if ((error = res) != 0) \ 1807 goto end; \ 1808} while(0) 1809 uint8_t msk, off, reg; 1810 int error; 1811 1812 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1813 1814 /* Read full ROM image. */ 1815 sc->last_rom_addr = 0; 1816 memset(rom, 0xff, size); 1817 1818 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1819 while (reg != 0xff) { 1820 /* check for extended header */ 1821 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1822 off = reg >> 5; 1823 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1824 1825 if ((reg & 0x0f) != 0x0f) 1826 off = ((reg & 0xf0) >> 1) | off; 1827 else 1828 continue; 1829 } else 1830 off = reg >> 4; 1831 msk = reg & 0xf; 1832 1833 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1834 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1835 } 1836 1837end: 1838 1839#ifdef USB_DEBUG 1840 if (sc->sc_debug & URTWN_DEBUG_ROM) 1841 urtwn_dump_rom_contents(sc, rom, size); 1842#endif 1843 1844 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1845 1846 if (error != 0) { 1847 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1848 __func__); 1849 } 1850 1851 return (error); 1852#undef URTWN_CHK 1853} 1854 1855static int 1856urtwn_efuse_switch_power(struct urtwn_softc *sc) 1857{ 1858 usb_error_t error; 1859 uint32_t reg; 1860 1861 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1862 if (error != USB_ERR_NORMAL_COMPLETION) 1863 return (EIO); 1864 1865 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1866 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1867 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1868 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1869 if (error != USB_ERR_NORMAL_COMPLETION) 1870 return (EIO); 1871 } 1872 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1873 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1874 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1875 reg | R92C_SYS_FUNC_EN_ELDR); 1876 if (error != USB_ERR_NORMAL_COMPLETION) 1877 return (EIO); 1878 } 1879 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1880 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1881 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1882 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1883 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1884 if (error != USB_ERR_NORMAL_COMPLETION) 1885 return (EIO); 1886 } 1887 1888 return (0); 1889} 1890 1891static int 1892urtwn_read_chipid(struct urtwn_softc *sc) 1893{ 1894 uint32_t reg; 1895 1896 if (sc->chip & URTWN_CHIP_88E) 1897 return (0); 1898 1899 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1900 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1901 return (EIO); 1902 1903 if (reg & R92C_SYS_CFG_TYPE_92C) { 1904 sc->chip |= URTWN_CHIP_92C; 1905 /* Check if it is a castrated 8192C. */ 1906 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1907 R92C_HPON_FSM_CHIP_BONDING_ID) == 1908 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1909 sc->chip |= URTWN_CHIP_92C_1T2R; 1910 } 1911 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1912 sc->chip |= URTWN_CHIP_UMC; 1913 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1914 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1915 } 1916 return (0); 1917} 1918 1919static int 1920urtwn_read_rom(struct urtwn_softc *sc) 1921{ 1922 struct r92c_rom *rom = &sc->rom.r92c_rom; 1923 int error; 1924 1925 /* Read full ROM image. */ 1926 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1927 if (error != 0) 1928 return (error); 1929 1930 /* XXX Weird but this is what the vendor driver does. */ 1931 sc->last_rom_addr = 0x1fa; 1932 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1933 if (error != 0) 1934 return (error); 1935 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: PA setting=0x%x\n", __func__, 1936 sc->pa_setting); 1937 1938 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1939 1940 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1941 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type=%d\n", 1942 __func__, sc->regulatory); 1943 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1944 1945 sc->sc_rf_write = urtwn_r92c_rf_write; 1946 sc->sc_power_on = urtwn_r92c_power_on; 1947 sc->sc_power_off = urtwn_r92c_power_off; 1948 1949 return (0); 1950} 1951 1952static int 1953urtwn_r88e_read_rom(struct urtwn_softc *sc) 1954{ 1955 struct r88e_rom *rom = &sc->rom.r88e_rom; 1956 int error; 1957 1958 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(sc->rom.r88e_rom)); 1959 if (error != 0) 1960 return (error); 1961 1962 sc->bw20_tx_pwr_diff = (rom->tx_pwr_diff >> 4); 1963 if (sc->bw20_tx_pwr_diff & 0x08) 1964 sc->bw20_tx_pwr_diff |= 0xf0; 1965 sc->ofdm_tx_pwr_diff = (rom->tx_pwr_diff & 0xf); 1966 if (sc->ofdm_tx_pwr_diff & 0x08) 1967 sc->ofdm_tx_pwr_diff |= 0xf0; 1968 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 1969 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type %d\n", 1970 __func__,sc->regulatory); 1971 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1972 1973 sc->sc_rf_write = urtwn_r88e_rf_write; 1974 sc->sc_power_on = urtwn_r88e_power_on; 1975 sc->sc_power_off = urtwn_r88e_power_off; 1976 1977 return (0); 1978} 1979 1980static __inline uint8_t 1981rate2ridx(uint8_t rate) 1982{ 1983 if (rate & IEEE80211_RATE_MCS) { 1984 /* 11n rates start at idx 12 */ 1985 return ((rate & 0xf) + 12); 1986 } 1987 switch (rate) { 1988 /* 11g */ 1989 case 12: return 4; 1990 case 18: return 5; 1991 case 24: return 6; 1992 case 36: return 7; 1993 case 48: return 8; 1994 case 72: return 9; 1995 case 96: return 10; 1996 case 108: return 11; 1997 /* 11b */ 1998 case 2: return 0; 1999 case 4: return 1; 2000 case 11: return 2; 2001 case 22: return 3; 2002 default: return URTWN_RIDX_UNKNOWN; 2003 } 2004} 2005 2006/* 2007 * Initialize rate adaptation in firmware. 2008 */ 2009static int 2010urtwn_ra_init(struct urtwn_softc *sc) 2011{ 2012 struct ieee80211com *ic = &sc->sc_ic; 2013 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2014 struct ieee80211_node *ni; 2015 struct ieee80211_rateset *rs, *rs_ht; 2016 struct r92c_fw_cmd_macid_cfg cmd; 2017 uint32_t rates, basicrates; 2018 uint8_t mode, ridx; 2019 int maxrate, maxbasicrate, error, i; 2020 2021 ni = ieee80211_ref_node(vap->iv_bss); 2022 rs = &ni->ni_rates; 2023 rs_ht = (struct ieee80211_rateset *) &ni->ni_htrates; 2024 2025 /* Get normal and basic rates mask. */ 2026 rates = basicrates = 0; 2027 maxrate = maxbasicrate = 0; 2028 2029 /* This is for 11bg */ 2030 for (i = 0; i < rs->rs_nrates; i++) { 2031 /* Convert 802.11 rate to HW rate index. */ 2032 ridx = rate2ridx(IEEE80211_RV(rs->rs_rates[i])); 2033 if (ridx == URTWN_RIDX_UNKNOWN) /* Unknown rate, skip. */ 2034 continue; 2035 rates |= 1 << ridx; 2036 if (ridx > maxrate) 2037 maxrate = ridx; 2038 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 2039 basicrates |= 1 << ridx; 2040 if (ridx > maxbasicrate) 2041 maxbasicrate = ridx; 2042 } 2043 } 2044 2045 /* If we're doing 11n, enable 11n rates */ 2046 if (ni->ni_flags & IEEE80211_NODE_HT) { 2047 for (i = 0; i < rs_ht->rs_nrates; i++) { 2048 if ((rs_ht->rs_rates[i] & 0x7f) > 0xf) 2049 continue; 2050 /* 11n rates start at index 12 */ 2051 ridx = ((rs_ht->rs_rates[i]) & 0xf) + 12; 2052 rates |= (1 << ridx); 2053 2054 /* Guard against the rate table being oddly ordered */ 2055 if (ridx > maxrate) 2056 maxrate = ridx; 2057 } 2058 } 2059 2060#if 0 2061 if (ic->ic_curmode == IEEE80211_MODE_11NG) 2062 raid = R92C_RAID_11GN; 2063#endif 2064 /* NB: group addressed frames are done at 11bg rates for now */ 2065 if (ic->ic_curmode == IEEE80211_MODE_11B) 2066 mode = R92C_RAID_11B; 2067 else 2068 mode = R92C_RAID_11BG; 2069 /* XXX misleading 'mode' value here for unicast frames */ 2070 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, 2071 "%s: mode 0x%x, rates 0x%08x, basicrates 0x%08x\n", __func__, 2072 mode, rates, basicrates); 2073 2074 /* Set rates mask for group addressed frames. */ 2075 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 2076 cmd.mask = htole32(mode << 28 | basicrates); 2077 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 2078 if (error != 0) { 2079 ieee80211_free_node(ni); 2080 device_printf(sc->sc_dev, 2081 "could not add broadcast station\n"); 2082 return (error); 2083 } 2084 2085 /* Set initial MRR rate. */ 2086 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxbasicrate %d\n", __func__, 2087 maxbasicrate); 2088 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 2089 maxbasicrate); 2090 2091 /* Set rates mask for unicast frames. */ 2092 if (ni->ni_flags & IEEE80211_NODE_HT) 2093 mode = R92C_RAID_11GN; 2094 else if (ic->ic_curmode == IEEE80211_MODE_11B) 2095 mode = R92C_RAID_11B; 2096 else 2097 mode = R92C_RAID_11BG; 2098 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 2099 cmd.mask = htole32(mode << 28 | rates); 2100 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 2101 if (error != 0) { 2102 ieee80211_free_node(ni); 2103 device_printf(sc->sc_dev, "could not add BSS station\n"); 2104 return (error); 2105 } 2106 /* Set initial MRR rate. */ 2107 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxrate %d\n", __func__, 2108 maxrate); 2109 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 2110 maxrate); 2111 2112 /* Indicate highest supported rate. */ 2113 if (ni->ni_flags & IEEE80211_NODE_HT) 2114 ni->ni_txrate = rs_ht->rs_rates[rs_ht->rs_nrates - 1] 2115 | IEEE80211_RATE_MCS; 2116 else 2117 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 2118 ieee80211_free_node(ni); 2119 2120 return (0); 2121} 2122 2123static void 2124urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2125{ 2126 struct r92c_tx_desc *txd = &uvp->bcn_desc; 2127 2128 txd->txdw0 = htole32( 2129 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 2130 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2131 txd->txdw1 = htole32( 2132 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 2133 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2134 2135 if (sc->chip & URTWN_CHIP_88E) { 2136 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 2137 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 2138 } else { 2139 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 2140 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2141 } 2142 2143 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 2144 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 2145} 2146 2147static int 2148urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 2149{ 2150 struct ieee80211vap *vap = ni->ni_vap; 2151 struct urtwn_vap *uvp = URTWN_VAP(vap); 2152 struct mbuf *m; 2153 int error; 2154 2155 URTWN_ASSERT_LOCKED(sc); 2156 2157 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 2158 return (EINVAL); 2159 2160 m = ieee80211_beacon_alloc(ni); 2161 if (m == NULL) { 2162 device_printf(sc->sc_dev, 2163 "%s: could not allocate beacon frame\n", __func__); 2164 return (ENOMEM); 2165 } 2166 2167 if (uvp->bcn_mbuf != NULL) 2168 m_freem(uvp->bcn_mbuf); 2169 2170 uvp->bcn_mbuf = m; 2171 2172 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 2173 return (error); 2174 2175 /* XXX bcnq stuck workaround */ 2176 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 2177 return (error); 2178 2179 URTWN_DPRINTF(sc, URTWN_DEBUG_BEACON, "%s: beacon was %srecognized\n", 2180 __func__, urtwn_read_1(sc, R92C_TDECTRL + 2) & 2181 (R92C_TDECTRL_BCN_VALID >> 16) ? "" : "not "); 2182 2183 return (0); 2184} 2185 2186static void 2187urtwn_update_beacon(struct ieee80211vap *vap, int item) 2188{ 2189 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2190 struct urtwn_vap *uvp = URTWN_VAP(vap); 2191 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 2192 struct ieee80211_node *ni = vap->iv_bss; 2193 int mcast = 0; 2194 2195 URTWN_LOCK(sc); 2196 if (uvp->bcn_mbuf == NULL) { 2197 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 2198 if (uvp->bcn_mbuf == NULL) { 2199 device_printf(sc->sc_dev, 2200 "%s: could not allocate beacon frame\n", __func__); 2201 URTWN_UNLOCK(sc); 2202 return; 2203 } 2204 } 2205 URTWN_UNLOCK(sc); 2206 2207 if (item == IEEE80211_BEACON_TIM) 2208 mcast = 1; /* XXX */ 2209 2210 setbit(bo->bo_flags, item); 2211 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 2212 2213 URTWN_LOCK(sc); 2214 urtwn_tx_beacon(sc, uvp); 2215 URTWN_UNLOCK(sc); 2216} 2217 2218/* 2219 * Push a beacon frame into the chip. Beacon will 2220 * be repeated by the chip every R92C_BCN_INTERVAL. 2221 */ 2222static int 2223urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2224{ 2225 struct r92c_tx_desc *desc = &uvp->bcn_desc; 2226 struct urtwn_data *bf; 2227 2228 URTWN_ASSERT_LOCKED(sc); 2229 2230 bf = urtwn_getbuf(sc); 2231 if (bf == NULL) 2232 return (ENOMEM); 2233 2234 memcpy(bf->buf, desc, sizeof(*desc)); 2235 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 2236 2237 sc->sc_txtimer = 5; 2238 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2239 2240 return (0); 2241} 2242 2243static int 2244urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2245 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2246{ 2247 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2248 uint8_t i; 2249 2250 if (!(&vap->iv_nw_keys[0] <= k && 2251 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2252 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2253 URTWN_LOCK(sc); 2254 /* 2255 * First 4 slots for group keys, 2256 * what is left - for pairwise. 2257 * XXX incompatible with IBSS RSN. 2258 */ 2259 for (i = IEEE80211_WEP_NKID; 2260 i < R92C_CAM_ENTRY_COUNT; i++) { 2261 if ((sc->keys_bmap & (1 << i)) == 0) { 2262 sc->keys_bmap |= 1 << i; 2263 *keyix = i; 2264 break; 2265 } 2266 } 2267 URTWN_UNLOCK(sc); 2268 if (i == R92C_CAM_ENTRY_COUNT) { 2269 device_printf(sc->sc_dev, 2270 "%s: no free space in the key table\n", 2271 __func__); 2272 return 0; 2273 } 2274 } else 2275 *keyix = 0; 2276 } else { 2277 *keyix = k - vap->iv_nw_keys; 2278 } 2279 *rxkeyix = *keyix; 2280 return 1; 2281} 2282 2283static void 2284urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data) 2285{ 2286 struct ieee80211_key *k = &data->key; 2287 uint8_t algo, keyid; 2288 int i, error; 2289 2290 if (k->wk_keyix < IEEE80211_WEP_NKID) 2291 keyid = k->wk_keyix; 2292 else 2293 keyid = 0; 2294 2295 /* Map net80211 cipher to HW crypto algorithm. */ 2296 switch (k->wk_cipher->ic_cipher) { 2297 case IEEE80211_CIPHER_WEP: 2298 if (k->wk_keylen < 8) 2299 algo = R92C_CAM_ALGO_WEP40; 2300 else 2301 algo = R92C_CAM_ALGO_WEP104; 2302 break; 2303 case IEEE80211_CIPHER_TKIP: 2304 algo = R92C_CAM_ALGO_TKIP; 2305 break; 2306 case IEEE80211_CIPHER_AES_CCM: 2307 algo = R92C_CAM_ALGO_AES; 2308 break; 2309 default: 2310 device_printf(sc->sc_dev, "%s: undefined cipher %d\n", 2311 __func__, k->wk_cipher->ic_cipher); 2312 return; 2313 } 2314 2315 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2316 "%s: keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, " 2317 "macaddr %s\n", __func__, k->wk_keyix, keyid, 2318 k->wk_cipher->ic_cipher, algo, k->wk_flags, k->wk_keylen, 2319 ether_sprintf(k->wk_macaddr)); 2320 2321 /* Write key. */ 2322 for (i = 0; i < 4; i++) { 2323 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 2324 le32dec(&k->wk_key[i * 4])); 2325 if (error != 0) 2326 goto fail; 2327 } 2328 2329 /* Write CTL0 last since that will validate the CAM entry. */ 2330 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 2331 le32dec(&k->wk_macaddr[2])); 2332 if (error != 0) 2333 goto fail; 2334 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 2335 SM(R92C_CAM_ALGO, algo) | 2336 SM(R92C_CAM_KEYID, keyid) | 2337 SM(R92C_CAM_MACLO, le16dec(&k->wk_macaddr[0])) | 2338 R92C_CAM_VALID); 2339 if (error != 0) 2340 goto fail; 2341 2342 return; 2343 2344fail: 2345 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error); 2346} 2347 2348static void 2349urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data) 2350{ 2351 struct ieee80211_key *k = &data->key; 2352 int i; 2353 2354 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2355 "%s: keyix %d, flags %04X, macaddr %s\n", __func__, 2356 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr)); 2357 2358 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0); 2359 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0); 2360 2361 /* Clear key. */ 2362 for (i = 0; i < 4; i++) 2363 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0); 2364 sc->keys_bmap &= ~(1 << k->wk_keyix); 2365} 2366 2367static int 2368urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 2369{ 2370 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2371 struct urtwn_vap *uvp = URTWN_VAP(vap); 2372 2373 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2374 /* Not for us. */ 2375 return (1); 2376 } 2377 2378 if (&vap->iv_nw_keys[0] <= k && 2379 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID]) { 2380 URTWN_LOCK(sc); 2381 uvp->keys[k->wk_keyix] = k; 2382 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2383 /* 2384 * The device was not started; 2385 * the key will be installed later. 2386 */ 2387 URTWN_UNLOCK(sc); 2388 return (1); 2389 } 2390 URTWN_UNLOCK(sc); 2391 } 2392 2393 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb)); 2394} 2395 2396static int 2397urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2398{ 2399 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2400 struct urtwn_vap *uvp = URTWN_VAP(vap); 2401 2402 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2403 /* Not for us. */ 2404 return (1); 2405 } 2406 2407 if (&vap->iv_nw_keys[0] <= k && 2408 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID]) { 2409 URTWN_LOCK(sc); 2410 uvp->keys[k->wk_keyix] = NULL; 2411 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2412 /* All keys are removed on device reset. */ 2413 URTWN_UNLOCK(sc); 2414 return (1); 2415 } 2416 URTWN_UNLOCK(sc); 2417 } 2418 2419 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb)); 2420} 2421 2422static void 2423urtwn_tsf_task_adhoc(void *arg, int pending) 2424{ 2425 struct ieee80211vap *vap = arg; 2426 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2427 struct ieee80211_node *ni; 2428 uint32_t reg; 2429 2430 URTWN_LOCK(sc); 2431 ni = ieee80211_ref_node(vap->iv_bss); 2432 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 2433 2434 /* Accept beacons with the same BSSID. */ 2435 urtwn_set_rx_bssid_all(sc, 0); 2436 2437 /* Enable synchronization. */ 2438 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 2439 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2440 2441 /* Synchronize. */ 2442 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 2443 2444 /* Disable synchronization. */ 2445 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 2446 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2447 2448 /* Remove beacon filter. */ 2449 urtwn_set_rx_bssid_all(sc, 1); 2450 2451 /* Enable beaconing. */ 2452 urtwn_write_1(sc, R92C_MBID_NUM, 2453 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2454 reg |= R92C_BCN_CTRL_EN_BCN; 2455 2456 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2457 ieee80211_free_node(ni); 2458 URTWN_UNLOCK(sc); 2459} 2460 2461static void 2462urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 2463{ 2464 struct ieee80211com *ic = &sc->sc_ic; 2465 struct urtwn_vap *uvp = URTWN_VAP(vap); 2466 2467 /* Reset TSF. */ 2468 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2469 2470 switch (vap->iv_opmode) { 2471 case IEEE80211_M_STA: 2472 /* Enable TSF synchronization. */ 2473 urtwn_write_1(sc, R92C_BCN_CTRL, 2474 urtwn_read_1(sc, R92C_BCN_CTRL) & 2475 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 2476 break; 2477 case IEEE80211_M_IBSS: 2478 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 2479 break; 2480 case IEEE80211_M_HOSTAP: 2481 /* Enable beaconing. */ 2482 urtwn_write_1(sc, R92C_MBID_NUM, 2483 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2484 urtwn_write_1(sc, R92C_BCN_CTRL, 2485 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 2486 break; 2487 default: 2488 device_printf(sc->sc_dev, "undefined opmode %d\n", 2489 vap->iv_opmode); 2490 return; 2491 } 2492} 2493 2494static void 2495urtwn_get_tsf(struct urtwn_softc *sc, uint64_t *buf) 2496{ 2497 urtwn_read_region_1(sc, R92C_TSFTR, (uint8_t *)buf, sizeof(*buf)); 2498} 2499 2500static void 2501urtwn_set_led(struct urtwn_softc *sc, int led, int on) 2502{ 2503 uint8_t reg; 2504 2505 if (led == URTWN_LED_LINK) { 2506 if (sc->chip & URTWN_CHIP_88E) { 2507 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 2508 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 2509 if (!on) { 2510 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 2511 urtwn_write_1(sc, R92C_LEDCFG2, 2512 reg | R92C_LEDCFG0_DIS); 2513 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 2514 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 2515 0xfe); 2516 } 2517 } else { 2518 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 2519 if (!on) 2520 reg |= R92C_LEDCFG0_DIS; 2521 urtwn_write_1(sc, R92C_LEDCFG0, reg); 2522 } 2523 sc->ledlink = on; /* Save LED state. */ 2524 } 2525} 2526 2527static void 2528urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 2529{ 2530 uint8_t reg; 2531 2532 reg = urtwn_read_1(sc, R92C_MSR); 2533 reg = (reg & ~R92C_MSR_MASK) | mode; 2534 urtwn_write_1(sc, R92C_MSR, reg); 2535} 2536 2537static void 2538urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 2539 const struct ieee80211_rx_stats *rxs, 2540 int rssi, int nf) 2541{ 2542 struct ieee80211vap *vap = ni->ni_vap; 2543 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2544 struct urtwn_vap *uvp = URTWN_VAP(vap); 2545 uint64_t ni_tstamp, curr_tstamp; 2546 2547 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 2548 2549 if (vap->iv_state == IEEE80211_S_RUN && 2550 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 2551 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 2552 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 2553 URTWN_LOCK(sc); 2554 urtwn_get_tsf(sc, &curr_tstamp); 2555 URTWN_UNLOCK(sc); 2556 curr_tstamp = le64toh(curr_tstamp); 2557 2558 if (ni_tstamp >= curr_tstamp) 2559 (void) ieee80211_ibss_merge(ni); 2560 } 2561} 2562 2563static int 2564urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2565{ 2566 struct urtwn_vap *uvp = URTWN_VAP(vap); 2567 struct ieee80211com *ic = vap->iv_ic; 2568 struct urtwn_softc *sc = ic->ic_softc; 2569 struct ieee80211_node *ni; 2570 enum ieee80211_state ostate; 2571 uint32_t reg; 2572 uint8_t mode; 2573 int error = 0; 2574 2575 ostate = vap->iv_state; 2576 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s -> %s\n", 2577 ieee80211_state_name[ostate], ieee80211_state_name[nstate]); 2578 2579 IEEE80211_UNLOCK(ic); 2580 URTWN_LOCK(sc); 2581 callout_stop(&sc->sc_watchdog_ch); 2582 2583 if (ostate == IEEE80211_S_RUN) { 2584 /* Stop calibration. */ 2585 callout_stop(&sc->sc_calib_to); 2586 2587 /* Turn link LED off. */ 2588 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2589 2590 /* Set media status to 'No Link'. */ 2591 urtwn_set_mode(sc, R92C_MSR_NOLINK); 2592 2593 /* Stop Rx of data frames. */ 2594 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2595 2596 /* Disable TSF synchronization. */ 2597 urtwn_write_1(sc, R92C_BCN_CTRL, 2598 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 2599 R92C_BCN_CTRL_DIS_TSF_UDT0); 2600 2601 /* Disable beaconing. */ 2602 urtwn_write_1(sc, R92C_MBID_NUM, 2603 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 2604 2605 /* Reset TSF. */ 2606 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2607 2608 /* Reset EDCA parameters. */ 2609 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2610 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2611 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2612 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2613 } 2614 2615 switch (nstate) { 2616 case IEEE80211_S_INIT: 2617 /* Turn link LED off. */ 2618 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2619 break; 2620 case IEEE80211_S_SCAN: 2621 /* Pause AC Tx queues. */ 2622 urtwn_write_1(sc, R92C_TXPAUSE, 2623 urtwn_read_1(sc, R92C_TXPAUSE) | R92C_TX_QUEUE_AC); 2624 break; 2625 case IEEE80211_S_AUTH: 2626 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2627 break; 2628 case IEEE80211_S_RUN: 2629 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2630 /* Turn link LED on. */ 2631 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2632 break; 2633 } 2634 2635 ni = ieee80211_ref_node(vap->iv_bss); 2636 2637 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2638 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2639 device_printf(sc->sc_dev, 2640 "%s: could not move to RUN state\n", __func__); 2641 error = EINVAL; 2642 goto end_run; 2643 } 2644 2645 switch (vap->iv_opmode) { 2646 case IEEE80211_M_STA: 2647 mode = R92C_MSR_INFRA; 2648 break; 2649 case IEEE80211_M_IBSS: 2650 mode = R92C_MSR_ADHOC; 2651 break; 2652 case IEEE80211_M_HOSTAP: 2653 mode = R92C_MSR_AP; 2654 break; 2655 default: 2656 device_printf(sc->sc_dev, "undefined opmode %d\n", 2657 vap->iv_opmode); 2658 error = EINVAL; 2659 goto end_run; 2660 } 2661 2662 /* Set media status to 'Associated'. */ 2663 urtwn_set_mode(sc, mode); 2664 2665 /* Set BSSID. */ 2666 urtwn_write_4(sc, R92C_BSSID + 0, le32dec(&ni->ni_bssid[0])); 2667 urtwn_write_4(sc, R92C_BSSID + 4, le16dec(&ni->ni_bssid[4])); 2668 2669 if (ic->ic_curmode == IEEE80211_MODE_11B) 2670 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2671 else /* 802.11b/g */ 2672 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2673 2674 /* Enable Rx of data frames. */ 2675 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2676 2677 /* Flush all AC queues. */ 2678 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2679 2680 /* Set beacon interval. */ 2681 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2682 2683 /* Allow Rx from our BSSID only. */ 2684 if (ic->ic_promisc == 0) { 2685 reg = urtwn_read_4(sc, R92C_RCR); 2686 2687 if (vap->iv_opmode != IEEE80211_M_HOSTAP) { 2688 reg |= R92C_RCR_CBSSID_DATA; 2689 if (vap->iv_opmode != IEEE80211_M_IBSS) 2690 reg |= R92C_RCR_CBSSID_BCN; 2691 } 2692 2693 urtwn_write_4(sc, R92C_RCR, reg); 2694 } 2695 2696 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2697 vap->iv_opmode == IEEE80211_M_IBSS) { 2698 error = urtwn_setup_beacon(sc, ni); 2699 if (error != 0) { 2700 device_printf(sc->sc_dev, 2701 "unable to push beacon into the chip, " 2702 "error %d\n", error); 2703 goto end_run; 2704 } 2705 } 2706 2707 /* Enable TSF synchronization. */ 2708 urtwn_tsf_sync_enable(sc, vap); 2709 2710 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2711 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2712 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2713 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2714 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2715 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2716 2717 /* Intialize rate adaptation. */ 2718 if (!(sc->chip & URTWN_CHIP_88E)) 2719 urtwn_ra_init(sc); 2720 /* Turn link LED on. */ 2721 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2722 2723 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2724 /* Reset temperature calibration state machine. */ 2725 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 2726 sc->thcal_lctemp = 0; 2727 /* Start periodic calibration. */ 2728 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2729 2730end_run: 2731 ieee80211_free_node(ni); 2732 break; 2733 default: 2734 break; 2735 } 2736 2737 URTWN_UNLOCK(sc); 2738 IEEE80211_LOCK(ic); 2739 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2740} 2741 2742static void 2743urtwn_calib_to(void *arg) 2744{ 2745 struct urtwn_softc *sc = arg; 2746 2747 /* Do it in a process context. */ 2748 urtwn_cmd_sleepable(sc, NULL, 0, urtwn_calib_cb); 2749} 2750 2751static void 2752urtwn_calib_cb(struct urtwn_softc *sc, union sec_param *data) 2753{ 2754 /* Do temperature compensation. */ 2755 urtwn_temp_calib(sc); 2756 2757 if ((urtwn_read_1(sc, R92C_MSR) & R92C_MSR_MASK) != R92C_MSR_NOLINK) 2758 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2759} 2760 2761static void 2762urtwn_watchdog(void *arg) 2763{ 2764 struct urtwn_softc *sc = arg; 2765 2766 if (sc->sc_txtimer > 0) { 2767 if (--sc->sc_txtimer == 0) { 2768 device_printf(sc->sc_dev, "device timeout\n"); 2769 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2770 return; 2771 } 2772 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2773 } 2774} 2775 2776static void 2777urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2778{ 2779 int pwdb; 2780 2781 /* Convert antenna signal to percentage. */ 2782 if (rssi <= -100 || rssi >= 20) 2783 pwdb = 0; 2784 else if (rssi >= 0) 2785 pwdb = 100; 2786 else 2787 pwdb = 100 + rssi; 2788 if (!(sc->chip & URTWN_CHIP_88E)) { 2789 if (rate <= URTWN_RIDX_CCK11) { 2790 /* CCK gain is smaller than OFDM/MCS gain. */ 2791 pwdb += 6; 2792 if (pwdb > 100) 2793 pwdb = 100; 2794 if (pwdb <= 14) 2795 pwdb -= 4; 2796 else if (pwdb <= 26) 2797 pwdb -= 8; 2798 else if (pwdb <= 34) 2799 pwdb -= 6; 2800 else if (pwdb <= 42) 2801 pwdb -= 2; 2802 } 2803 } 2804 if (sc->avg_pwdb == -1) /* Init. */ 2805 sc->avg_pwdb = pwdb; 2806 else if (sc->avg_pwdb < pwdb) 2807 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2808 else 2809 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2810 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: PWDB %d, EMA %d\n", __func__, 2811 pwdb, sc->avg_pwdb); 2812} 2813 2814static int8_t 2815urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2816{ 2817 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2818 struct r92c_rx_phystat *phy; 2819 struct r92c_rx_cck *cck; 2820 uint8_t rpt; 2821 int8_t rssi; 2822 2823 if (rate <= URTWN_RIDX_CCK11) { 2824 cck = (struct r92c_rx_cck *)physt; 2825 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2826 rpt = (cck->agc_rpt >> 5) & 0x3; 2827 rssi = (cck->agc_rpt & 0x1f) << 1; 2828 } else { 2829 rpt = (cck->agc_rpt >> 6) & 0x3; 2830 rssi = cck->agc_rpt & 0x3e; 2831 } 2832 rssi = cckoff[rpt] - rssi; 2833 } else { /* OFDM/HT. */ 2834 phy = (struct r92c_rx_phystat *)physt; 2835 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2836 } 2837 return (rssi); 2838} 2839 2840static int8_t 2841urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2842{ 2843 struct r92c_rx_phystat *phy; 2844 struct r88e_rx_cck *cck; 2845 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2846 int8_t rssi; 2847 2848 rssi = 0; 2849 if (rate <= URTWN_RIDX_CCK11) { 2850 cck = (struct r88e_rx_cck *)physt; 2851 cck_agc_rpt = cck->agc_rpt; 2852 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2853 vga_idx = cck_agc_rpt & 0x1f; 2854 switch (lna_idx) { 2855 case 7: 2856 if (vga_idx <= 27) 2857 rssi = -100 + 2* (27 - vga_idx); 2858 else 2859 rssi = -100; 2860 break; 2861 case 6: 2862 rssi = -48 + 2 * (2 - vga_idx); 2863 break; 2864 case 5: 2865 rssi = -42 + 2 * (7 - vga_idx); 2866 break; 2867 case 4: 2868 rssi = -36 + 2 * (7 - vga_idx); 2869 break; 2870 case 3: 2871 rssi = -24 + 2 * (7 - vga_idx); 2872 break; 2873 case 2: 2874 rssi = -12 + 2 * (5 - vga_idx); 2875 break; 2876 case 1: 2877 rssi = 8 - (2 * vga_idx); 2878 break; 2879 case 0: 2880 rssi = 14 - (2 * vga_idx); 2881 break; 2882 } 2883 rssi += 6; 2884 } else { /* OFDM/HT. */ 2885 phy = (struct r92c_rx_phystat *)physt; 2886 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2887 } 2888 return (rssi); 2889} 2890 2891static int 2892urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2893 struct mbuf *m, struct urtwn_data *data) 2894{ 2895 const struct ieee80211_txparam *tp; 2896 struct ieee80211com *ic = &sc->sc_ic; 2897 struct ieee80211vap *vap = ni->ni_vap; 2898 struct ieee80211_key *k = NULL; 2899 struct ieee80211_channel *chan; 2900 struct ieee80211_frame *wh; 2901 struct r92c_tx_desc *txd; 2902 uint8_t macid, raid, rate, ridx, type, tid, qos, qsel; 2903 int hasqos, ismcast; 2904 2905 URTWN_ASSERT_LOCKED(sc); 2906 2907 wh = mtod(m, struct ieee80211_frame *); 2908 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2909 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2910 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2911 2912 /* Select TX ring for this frame. */ 2913 if (hasqos) { 2914 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2915 tid = qos & IEEE80211_QOS_TID; 2916 } else { 2917 qos = 0; 2918 tid = 0; 2919 } 2920 2921 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2922 ni->ni_chan : ic->ic_curchan; 2923 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2924 2925 /* Choose a TX rate index. */ 2926 if (type == IEEE80211_FC0_TYPE_MGT) 2927 rate = tp->mgmtrate; 2928 else if (ismcast) 2929 rate = tp->mcastrate; 2930 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2931 rate = tp->ucastrate; 2932 else if (m->m_flags & M_EAPOL) 2933 rate = tp->mgmtrate; 2934 else { 2935 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2936 /* XXX pass pktlen */ 2937 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2938 rate = ni->ni_txrate; 2939 } else { 2940 /* XXX TODO: drop the default rate for 11b/11g? */ 2941 if (ni->ni_flags & IEEE80211_NODE_HT) 2942 rate = IEEE80211_RATE_MCS | 0x4; /* MCS4 */ 2943 else if (ic->ic_curmode != IEEE80211_MODE_11B) 2944 rate = 108; 2945 else 2946 rate = 22; 2947 } 2948 } 2949 2950 /* 2951 * XXX TODO: this should be per-node, for 11b versus 11bg 2952 * nodes in hostap mode 2953 */ 2954 ridx = rate2ridx(rate); 2955 if (ni->ni_flags & IEEE80211_NODE_HT) 2956 raid = R92C_RAID_11GN; 2957 else if (ic->ic_curmode != IEEE80211_MODE_11B) 2958 raid = R92C_RAID_11BG; 2959 else 2960 raid = R92C_RAID_11B; 2961 2962 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2963 k = ieee80211_crypto_encap(ni, m); 2964 if (k == NULL) { 2965 device_printf(sc->sc_dev, 2966 "ieee80211_crypto_encap returns NULL.\n"); 2967 return (ENOBUFS); 2968 } 2969 2970 /* in case packet header moved, reset pointer */ 2971 wh = mtod(m, struct ieee80211_frame *); 2972 } 2973 2974 /* Fill Tx descriptor. */ 2975 txd = (struct r92c_tx_desc *)data->buf; 2976 memset(txd, 0, sizeof(*txd)); 2977 2978 txd->txdw0 |= htole32( 2979 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2980 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2981 if (ismcast) 2982 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2983 2984 if (!ismcast) { 2985 /* Unicast frame, check if an ACK is expected. */ 2986 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 2987 IEEE80211_QOS_ACKPOLICY_NOACK) { 2988 txd->txdw5 |= htole32(R92C_TXDW5_RTY_LMT_ENA); 2989 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTY_LMT, 2990 tp->maxretry)); 2991 } 2992 2993 if (sc->chip & URTWN_CHIP_88E) { 2994 struct urtwn_node *un = URTWN_NODE(ni); 2995 macid = un->id; 2996 } else 2997 macid = URTWN_MACID_BSS; 2998 2999 if (type == IEEE80211_FC0_TYPE_DATA) { 3000 qsel = tid % URTWN_MAX_TID; 3001 3002 if (sc->chip & URTWN_CHIP_88E) { 3003 txd->txdw2 |= htole32( 3004 R88E_TXDW2_AGGBK | 3005 R88E_TXDW2_CCX_RPT); 3006 } else 3007 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 3008 3009 /* protmode, non-HT */ 3010 /* XXX TODO: noack frames? */ 3011 if ((rate & 0x80) == 0 && 3012 (ic->ic_flags & IEEE80211_F_USEPROT)) { 3013 switch (ic->ic_protmode) { 3014 case IEEE80211_PROT_CTSONLY: 3015 txd->txdw4 |= htole32( 3016 R92C_TXDW4_CTS2SELF); 3017 break; 3018 case IEEE80211_PROT_RTSCTS: 3019 txd->txdw4 |= htole32( 3020 R92C_TXDW4_RTSEN | 3021 R92C_TXDW4_HWRTSEN); 3022 break; 3023 default: 3024 break; 3025 } 3026 } 3027 3028 /* protmode, HT */ 3029 /* XXX TODO: noack frames? */ 3030 if ((rate & 0x80) && 3031 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) { 3032 txd->txdw4 |= htole32( 3033 R92C_TXDW4_RTSEN | 3034 R92C_TXDW4_HWRTSEN); 3035 } 3036 3037 /* XXX TODO: rtsrate is configurable? 24mbit may 3038 * be a bit high for RTS rate? */ 3039 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 3040 URTWN_RIDX_OFDM24)); 3041 3042 txd->txdw5 |= htole32(0x0001ff00); 3043 } else /* IEEE80211_FC0_TYPE_MGT */ 3044 qsel = R92C_TXDW1_QSEL_MGNT; 3045 } else { 3046 macid = URTWN_MACID_BC; 3047 qsel = R92C_TXDW1_QSEL_MGNT; 3048 } 3049 3050 txd->txdw1 |= htole32( 3051 SM(R92C_TXDW1_QSEL, qsel) | 3052 SM(R92C_TXDW1_RAID, raid)); 3053 3054 /* XXX TODO: 40MHZ flag? */ 3055 /* XXX TODO: AMPDU flag? (AGG_ENABLE or AGG_BREAK?) Density shift? */ 3056 /* XXX Short preamble? */ 3057 /* XXX Short-GI? */ 3058 3059 if (sc->chip & URTWN_CHIP_88E) 3060 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 3061 else 3062 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 3063 3064 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 3065 3066 /* Force this rate if needed. */ 3067 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 3068 (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) || 3069 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 3070 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3071 3072 if (!hasqos) { 3073 /* Use HW sequence numbering for non-QoS frames. */ 3074 if (sc->chip & URTWN_CHIP_88E) 3075 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 3076 else 3077 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 3078 } else { 3079 /* Set sequence number. */ 3080 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 3081 } 3082 3083 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 3084 uint8_t cipher; 3085 3086 switch (k->wk_cipher->ic_cipher) { 3087 case IEEE80211_CIPHER_WEP: 3088 case IEEE80211_CIPHER_TKIP: 3089 cipher = R92C_TXDW1_CIPHER_RC4; 3090 break; 3091 case IEEE80211_CIPHER_AES_CCM: 3092 cipher = R92C_TXDW1_CIPHER_AES; 3093 break; 3094 default: 3095 device_printf(sc->sc_dev, "%s: unknown cipher %d\n", 3096 __func__, k->wk_cipher->ic_cipher); 3097 return (EINVAL); 3098 } 3099 3100 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 3101 } 3102 3103 if (ieee80211_radiotap_active_vap(vap)) { 3104 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3105 3106 tap->wt_flags = 0; 3107 if (k != NULL) 3108 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3109 ieee80211_radiotap_tx(vap, m); 3110 } 3111 3112 data->ni = ni; 3113 3114 urtwn_tx_start(sc, m, type, data); 3115 3116 return (0); 3117} 3118 3119static int 3120urtwn_tx_raw(struct urtwn_softc *sc, struct ieee80211_node *ni, 3121 struct mbuf *m, struct urtwn_data *data, 3122 const struct ieee80211_bpf_params *params) 3123{ 3124 struct ieee80211vap *vap = ni->ni_vap; 3125 struct ieee80211_key *k = NULL; 3126 struct ieee80211_frame *wh; 3127 struct r92c_tx_desc *txd; 3128 uint8_t cipher, ridx, type; 3129 3130 /* Encrypt the frame if need be. */ 3131 cipher = R92C_TXDW1_CIPHER_NONE; 3132 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 3133 /* Retrieve key for TX. */ 3134 k = ieee80211_crypto_encap(ni, m); 3135 if (k == NULL) 3136 return (ENOBUFS); 3137 3138 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 3139 switch (k->wk_cipher->ic_cipher) { 3140 case IEEE80211_CIPHER_WEP: 3141 case IEEE80211_CIPHER_TKIP: 3142 cipher = R92C_TXDW1_CIPHER_RC4; 3143 break; 3144 case IEEE80211_CIPHER_AES_CCM: 3145 cipher = R92C_TXDW1_CIPHER_AES; 3146 break; 3147 default: 3148 device_printf(sc->sc_dev, 3149 "%s: unknown cipher %d\n", 3150 __func__, k->wk_cipher->ic_cipher); 3151 return (EINVAL); 3152 } 3153 } 3154 } 3155 3156 /* XXX TODO: 11n checks, matching urtwn_tx_data() */ 3157 3158 wh = mtod(m, struct ieee80211_frame *); 3159 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3160 3161 /* Fill Tx descriptor. */ 3162 txd = (struct r92c_tx_desc *)data->buf; 3163 memset(txd, 0, sizeof(*txd)); 3164 3165 txd->txdw0 |= htole32( 3166 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 3167 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 3168 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3169 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 3170 3171 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3172 txd->txdw5 |= htole32(R92C_TXDW5_RTY_LMT_ENA); 3173 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTY_LMT, 3174 params->ibp_try0)); 3175 } 3176 if (params->ibp_flags & IEEE80211_BPF_RTS) 3177 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_HWRTSEN); 3178 if (params->ibp_flags & IEEE80211_BPF_CTS) 3179 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF); 3180 if (txd->txdw4 & htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_CTS2SELF)) { 3181 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 3182 URTWN_RIDX_OFDM24)); 3183 } 3184 3185 if (sc->chip & URTWN_CHIP_88E) 3186 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 3187 else 3188 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 3189 3190 /* XXX TODO: rate index/config (RAID) for 11n? */ 3191 txd->txdw1 |= htole32(SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT)); 3192 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 3193 3194 /* Choose a TX rate index. */ 3195 ridx = rate2ridx(params->ibp_rate0); 3196 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 3197 txd->txdw5 |= htole32(0x0001ff00); 3198 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3199 3200 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 3201 /* Use HW sequence numbering for non-QoS frames. */ 3202 if (sc->chip & URTWN_CHIP_88E) 3203 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 3204 else 3205 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 3206 } else { 3207 /* Set sequence number. */ 3208 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 3209 } 3210 3211 if (ieee80211_radiotap_active_vap(vap)) { 3212 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3213 3214 tap->wt_flags = 0; 3215 if (k != NULL) 3216 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3217 ieee80211_radiotap_tx(vap, m); 3218 } 3219 3220 data->ni = ni; 3221 3222 urtwn_tx_start(sc, m, type, data); 3223 3224 return (0); 3225} 3226 3227static void 3228urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 3229 struct urtwn_data *data) 3230{ 3231 struct usb_xfer *xfer; 3232 struct r92c_tx_desc *txd; 3233 uint16_t ac, sum; 3234 int i, xferlen; 3235 3236 URTWN_ASSERT_LOCKED(sc); 3237 3238 ac = M_WME_GETAC(m); 3239 3240 switch (type) { 3241 case IEEE80211_FC0_TYPE_CTL: 3242 case IEEE80211_FC0_TYPE_MGT: 3243 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 3244 break; 3245 default: 3246 xfer = sc->sc_xfer[wme2queue[ac].qid]; 3247 break; 3248 } 3249 3250 txd = (struct r92c_tx_desc *)data->buf; 3251 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 3252 3253 /* Compute Tx descriptor checksum. */ 3254 sum = 0; 3255 for (i = 0; i < sizeof(*txd) / 2; i++) 3256 sum ^= ((uint16_t *)txd)[i]; 3257 txd->txdsum = sum; /* NB: already little endian. */ 3258 3259 xferlen = sizeof(*txd) + m->m_pkthdr.len; 3260 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 3261 3262 data->buflen = xferlen; 3263 data->m = m; 3264 3265 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 3266 usbd_transfer_start(xfer); 3267} 3268 3269static int 3270urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 3271{ 3272 struct urtwn_softc *sc = ic->ic_softc; 3273 int error; 3274 3275 URTWN_LOCK(sc); 3276 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 3277 URTWN_UNLOCK(sc); 3278 return (ENXIO); 3279 } 3280 error = mbufq_enqueue(&sc->sc_snd, m); 3281 if (error) { 3282 URTWN_UNLOCK(sc); 3283 return (error); 3284 } 3285 urtwn_start(sc); 3286 URTWN_UNLOCK(sc); 3287 3288 return (0); 3289} 3290 3291static void 3292urtwn_start(struct urtwn_softc *sc) 3293{ 3294 struct ieee80211_node *ni; 3295 struct mbuf *m; 3296 struct urtwn_data *bf; 3297 3298 URTWN_ASSERT_LOCKED(sc); 3299 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 3300 bf = urtwn_getbuf(sc); 3301 if (bf == NULL) { 3302 mbufq_prepend(&sc->sc_snd, m); 3303 break; 3304 } 3305 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3306 m->m_pkthdr.rcvif = NULL; 3307 3308 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n", 3309 __func__, 3310 m); 3311 3312 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 3313 if_inc_counter(ni->ni_vap->iv_ifp, 3314 IFCOUNTER_OERRORS, 1); 3315 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3316 m_freem(m); 3317 ieee80211_free_node(ni); 3318 break; 3319 } 3320 sc->sc_txtimer = 5; 3321 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3322 } 3323} 3324 3325static void 3326urtwn_parent(struct ieee80211com *ic) 3327{ 3328 struct urtwn_softc *sc = ic->ic_softc; 3329 3330 URTWN_LOCK(sc); 3331 if (sc->sc_flags & URTWN_DETACHED) { 3332 URTWN_UNLOCK(sc); 3333 return; 3334 } 3335 URTWN_UNLOCK(sc); 3336 3337 if (ic->ic_nrunning > 0) { 3338 if (urtwn_init(sc) != 0) { 3339 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3340 if (vap != NULL) 3341 ieee80211_stop(vap); 3342 } else 3343 ieee80211_start_all(ic); 3344 } else 3345 urtwn_stop(sc); 3346} 3347 3348static __inline int 3349urtwn_power_on(struct urtwn_softc *sc) 3350{ 3351 3352 return sc->sc_power_on(sc); 3353} 3354 3355static int 3356urtwn_r92c_power_on(struct urtwn_softc *sc) 3357{ 3358 uint32_t reg; 3359 usb_error_t error; 3360 int ntries; 3361 3362 /* Wait for autoload done bit. */ 3363 for (ntries = 0; ntries < 1000; ntries++) { 3364 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3365 break; 3366 urtwn_ms_delay(sc); 3367 } 3368 if (ntries == 1000) { 3369 device_printf(sc->sc_dev, 3370 "timeout waiting for chip autoload\n"); 3371 return (ETIMEDOUT); 3372 } 3373 3374 /* Unlock ISO/CLK/Power control register. */ 3375 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3376 if (error != USB_ERR_NORMAL_COMPLETION) 3377 return (EIO); 3378 /* Move SPS into PWM mode. */ 3379 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3380 if (error != USB_ERR_NORMAL_COMPLETION) 3381 return (EIO); 3382 urtwn_ms_delay(sc); 3383 3384 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3385 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3386 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3387 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3388 if (error != USB_ERR_NORMAL_COMPLETION) 3389 return (EIO); 3390 urtwn_ms_delay(sc); 3391 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3392 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3393 ~R92C_SYS_ISO_CTRL_MD2PP); 3394 if (error != USB_ERR_NORMAL_COMPLETION) 3395 return (EIO); 3396 } 3397 3398 /* Auto enable WLAN. */ 3399 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3400 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3401 if (error != USB_ERR_NORMAL_COMPLETION) 3402 return (EIO); 3403 for (ntries = 0; ntries < 1000; ntries++) { 3404 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3405 R92C_APS_FSMCO_APFM_ONMAC)) 3406 break; 3407 urtwn_ms_delay(sc); 3408 } 3409 if (ntries == 1000) { 3410 device_printf(sc->sc_dev, 3411 "timeout waiting for MAC auto ON\n"); 3412 return (ETIMEDOUT); 3413 } 3414 3415 /* Enable radio, GPIO and LED functions. */ 3416 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3417 R92C_APS_FSMCO_AFSM_HSUS | 3418 R92C_APS_FSMCO_PDN_EN | 3419 R92C_APS_FSMCO_PFM_ALDN); 3420 if (error != USB_ERR_NORMAL_COMPLETION) 3421 return (EIO); 3422 /* Release RF digital isolation. */ 3423 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3424 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3425 if (error != USB_ERR_NORMAL_COMPLETION) 3426 return (EIO); 3427 3428 /* Initialize MAC. */ 3429 error = urtwn_write_1(sc, R92C_APSD_CTRL, 3430 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3431 if (error != USB_ERR_NORMAL_COMPLETION) 3432 return (EIO); 3433 for (ntries = 0; ntries < 200; ntries++) { 3434 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3435 R92C_APSD_CTRL_OFF_STATUS)) 3436 break; 3437 urtwn_ms_delay(sc); 3438 } 3439 if (ntries == 200) { 3440 device_printf(sc->sc_dev, 3441 "timeout waiting for MAC initialization\n"); 3442 return (ETIMEDOUT); 3443 } 3444 3445 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3446 reg = urtwn_read_2(sc, R92C_CR); 3447 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3448 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3449 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3450 R92C_CR_ENSEC; 3451 error = urtwn_write_2(sc, R92C_CR, reg); 3452 if (error != USB_ERR_NORMAL_COMPLETION) 3453 return (EIO); 3454 3455 error = urtwn_write_1(sc, 0xfe10, 0x19); 3456 if (error != USB_ERR_NORMAL_COMPLETION) 3457 return (EIO); 3458 return (0); 3459} 3460 3461static int 3462urtwn_r88e_power_on(struct urtwn_softc *sc) 3463{ 3464 uint32_t reg; 3465 usb_error_t error; 3466 int ntries; 3467 3468 /* Wait for power ready bit. */ 3469 for (ntries = 0; ntries < 5000; ntries++) { 3470 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 3471 break; 3472 urtwn_ms_delay(sc); 3473 } 3474 if (ntries == 5000) { 3475 device_printf(sc->sc_dev, 3476 "timeout waiting for chip power up\n"); 3477 return (ETIMEDOUT); 3478 } 3479 3480 /* Reset BB. */ 3481 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3482 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3483 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3484 if (error != USB_ERR_NORMAL_COMPLETION) 3485 return (EIO); 3486 3487 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3488 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3489 if (error != USB_ERR_NORMAL_COMPLETION) 3490 return (EIO); 3491 3492 /* Disable HWPDN. */ 3493 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3494 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3495 if (error != USB_ERR_NORMAL_COMPLETION) 3496 return (EIO); 3497 3498 /* Disable WL suspend. */ 3499 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3500 urtwn_read_2(sc, R92C_APS_FSMCO) & 3501 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 3502 if (error != USB_ERR_NORMAL_COMPLETION) 3503 return (EIO); 3504 3505 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3506 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3507 if (error != USB_ERR_NORMAL_COMPLETION) 3508 return (EIO); 3509 for (ntries = 0; ntries < 5000; ntries++) { 3510 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3511 R92C_APS_FSMCO_APFM_ONMAC)) 3512 break; 3513 urtwn_ms_delay(sc); 3514 } 3515 if (ntries == 5000) 3516 return (ETIMEDOUT); 3517 3518 /* Enable LDO normal mode. */ 3519 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 3520 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~R92C_LPLDO_CTRL_SLEEP); 3521 if (error != USB_ERR_NORMAL_COMPLETION) 3522 return (EIO); 3523 3524 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3525 error = urtwn_write_2(sc, R92C_CR, 0); 3526 if (error != USB_ERR_NORMAL_COMPLETION) 3527 return (EIO); 3528 reg = urtwn_read_2(sc, R92C_CR); 3529 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3530 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3531 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3532 error = urtwn_write_2(sc, R92C_CR, reg); 3533 if (error != USB_ERR_NORMAL_COMPLETION) 3534 return (EIO); 3535 3536 return (0); 3537} 3538 3539static __inline void 3540urtwn_power_off(struct urtwn_softc *sc) 3541{ 3542 3543 return sc->sc_power_off(sc); 3544} 3545 3546static void 3547urtwn_r92c_power_off(struct urtwn_softc *sc) 3548{ 3549 uint32_t reg; 3550 3551 /* Block all Tx queues. */ 3552 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3553 3554 /* Disable RF */ 3555 urtwn_rf_write(sc, 0, 0, 0); 3556 3557 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3558 3559 /* Reset BB state machine */ 3560 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3561 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA | 3562 R92C_SYS_FUNC_EN_BB_GLB_RST); 3563 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3564 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3565 3566 /* 3567 * Reset digital sequence 3568 */ 3569#ifndef URTWN_WITHOUT_UCODE 3570 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3571 /* Reset MCU ready status */ 3572 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3573 3574 /* If firmware in ram code, do reset */ 3575 urtwn_fw_reset(sc); 3576 } 3577#endif 3578 3579 /* Reset MAC and Enable 8051 */ 3580 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 3581 (R92C_SYS_FUNC_EN_CPUEN | 3582 R92C_SYS_FUNC_EN_ELDR | 3583 R92C_SYS_FUNC_EN_HWPDN) >> 8); 3584 3585 /* Reset MCU ready status */ 3586 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3587 3588 /* Disable MAC clock */ 3589 urtwn_write_2(sc, R92C_SYS_CLKR, 3590 R92C_SYS_CLKR_ANAD16V_EN | 3591 R92C_SYS_CLKR_ANA8M | 3592 R92C_SYS_CLKR_LOADER_EN | 3593 R92C_SYS_CLKR_80M_SSC_DIS | 3594 R92C_SYS_CLKR_SYS_EN | 3595 R92C_SYS_CLKR_RING_EN | 3596 0x4000); 3597 3598 /* Disable AFE PLL */ 3599 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3600 3601 /* Gated AFE DIG_CLOCK */ 3602 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3603 3604 /* Isolated digital to PON */ 3605 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3606 R92C_SYS_ISO_CTRL_MD2PP | 3607 R92C_SYS_ISO_CTRL_PA2PCIE | 3608 R92C_SYS_ISO_CTRL_PD2CORE | 3609 R92C_SYS_ISO_CTRL_IP2MAC | 3610 R92C_SYS_ISO_CTRL_DIOP | 3611 R92C_SYS_ISO_CTRL_DIOE); 3612 3613 /* 3614 * Pull GPIO PIN to balance level and LED control 3615 */ 3616 /* 1. Disable GPIO[7:0] */ 3617 urtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000); 3618 3619 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3620 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3621 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3622 3623 /* Disable GPIO[10:8] */ 3624 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x00); 3625 3626 reg = urtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0; 3627 reg |= (((reg & 0x000f) << 4) | 0x0780); 3628 urtwn_write_2(sc, R92C_GPIO_IO_SEL, reg); 3629 3630 /* Disable LED0 & 1 */ 3631 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3632 3633 /* 3634 * Reset digital sequence 3635 */ 3636 /* Disable ELDR clock */ 3637 urtwn_write_2(sc, R92C_SYS_CLKR, 3638 R92C_SYS_CLKR_ANAD16V_EN | 3639 R92C_SYS_CLKR_ANA8M | 3640 R92C_SYS_CLKR_LOADER_EN | 3641 R92C_SYS_CLKR_80M_SSC_DIS | 3642 R92C_SYS_CLKR_SYS_EN | 3643 R92C_SYS_CLKR_RING_EN | 3644 0x4000); 3645 3646 /* Isolated ELDR to PON */ 3647 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 3648 (R92C_SYS_ISO_CTRL_DIOR | 3649 R92C_SYS_ISO_CTRL_PWC_EV12V) >> 8); 3650 3651 /* 3652 * Disable analog sequence 3653 */ 3654 /* Disable A15 power */ 3655 urtwn_write_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_OBUF); 3656 /* Disable digital core power */ 3657 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3658 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3659 ~R92C_LDOV12D_CTRL_LDV12_EN); 3660 3661 /* Enter PFM mode */ 3662 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3663 3664 /* Set USB suspend */ 3665 urtwn_write_2(sc, R92C_APS_FSMCO, 3666 R92C_APS_FSMCO_APDM_HOST | 3667 R92C_APS_FSMCO_AFSM_HSUS | 3668 R92C_APS_FSMCO_PFM_ALDN); 3669 3670 /* Lock ISO/CLK/Power control register. */ 3671 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 3672} 3673 3674static void 3675urtwn_r88e_power_off(struct urtwn_softc *sc) 3676{ 3677 uint8_t reg; 3678 int ntries; 3679 3680 /* Disable any kind of TX reports. */ 3681 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 3682 urtwn_read_1(sc, R88E_TX_RPT_CTRL) & 3683 ~(R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA)); 3684 3685 /* Stop Rx. */ 3686 urtwn_write_1(sc, R92C_CR, 0); 3687 3688 /* Move card to Low Power State. */ 3689 /* Block all Tx queues. */ 3690 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3691 3692 for (ntries = 0; ntries < 20; ntries++) { 3693 /* Should be zero if no packet is transmitting. */ 3694 if (urtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 3695 break; 3696 3697 urtwn_ms_delay(sc); 3698 } 3699 if (ntries == 20) { 3700 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 3701 __func__); 3702 return; 3703 } 3704 3705 /* CCK and OFDM are disabled, and clock are gated. */ 3706 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3707 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_BBRSTB); 3708 3709 urtwn_ms_delay(sc); 3710 3711 /* Reset MAC TRX */ 3712 urtwn_write_1(sc, R92C_CR, 3713 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3714 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | 3715 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN); 3716 3717 /* check if removed later */ 3718 urtwn_write_1(sc, R92C_CR + 1, 3719 urtwn_read_1(sc, R92C_CR + 1) & ~(R92C_CR_ENSEC >> 8)); 3720 3721 /* Respond TxOK to scheduler */ 3722 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 3723 urtwn_read_1(sc, R92C_DUAL_TSF_RST) | 0x20); 3724 3725 /* If firmware in ram code, do reset. */ 3726#ifndef URTWN_WITHOUT_UCODE 3727 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) 3728 urtwn_r88e_fw_reset(sc); 3729#endif 3730 3731 /* Reset MCU ready status. */ 3732 urtwn_write_1(sc, R92C_MCUFWDL, 0x00); 3733 3734 /* Disable 32k. */ 3735 urtwn_write_1(sc, R88E_32K_CTRL, 3736 urtwn_read_1(sc, R88E_32K_CTRL) & ~0x01); 3737 3738 /* Move card to Disabled state. */ 3739 /* Turn off RF. */ 3740 urtwn_write_1(sc, R92C_RF_CTRL, 0); 3741 3742 /* LDO Sleep mode. */ 3743 urtwn_write_1(sc, R92C_LPLDO_CTRL, 3744 urtwn_read_1(sc, R92C_LPLDO_CTRL) | R92C_LPLDO_CTRL_SLEEP); 3745 3746 /* Turn off MAC by HW state machine */ 3747 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3748 urtwn_read_1(sc, R92C_APS_FSMCO + 1) | 3749 (R92C_APS_FSMCO_APFM_OFF >> 8)); 3750 3751 for (ntries = 0; ntries < 20; ntries++) { 3752 /* Wait until it will be disabled. */ 3753 if ((urtwn_read_1(sc, R92C_APS_FSMCO + 1) & 3754 (R92C_APS_FSMCO_APFM_OFF >> 8)) == 0) 3755 break; 3756 3757 urtwn_ms_delay(sc); 3758 } 3759 if (ntries == 20) { 3760 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 3761 __func__); 3762 return; 3763 } 3764 3765 /* schmit trigger */ 3766 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3767 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3768 3769 /* Enable WL suspend. */ 3770 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3771 (urtwn_read_1(sc, R92C_APS_FSMCO + 1) & ~0x10) | 0x08); 3772 3773 /* Enable bandgap mbias in suspend. */ 3774 urtwn_write_1(sc, R92C_APS_FSMCO + 3, 0); 3775 3776 /* Clear SIC_EN register. */ 3777 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 1, 3778 urtwn_read_1(sc, R92C_GPIO_MUXCFG + 1) & ~0x10); 3779 3780 /* Set USB suspend enable local register */ 3781 urtwn_write_1(sc, R92C_USB_SUSPEND, 3782 urtwn_read_1(sc, R92C_USB_SUSPEND) | 0x10); 3783 3784 /* Reset MCU IO Wrapper. */ 3785 reg = urtwn_read_1(sc, R92C_RSV_CTRL + 1); 3786 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08); 3787 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08); 3788 3789 /* marked as 'For Power Consumption' code. */ 3790 urtwn_write_1(sc, R92C_GPIO_OUT, urtwn_read_1(sc, R92C_GPIO_IN)); 3791 urtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff); 3792 3793 urtwn_write_1(sc, R92C_GPIO_IO_SEL, 3794 urtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4); 3795 urtwn_write_1(sc, R92C_GPIO_MOD, 3796 urtwn_read_1(sc, R92C_GPIO_MOD) | 0x0f); 3797 3798 /* Set LNA, TRSW, EX_PA Pin to output mode. */ 3799 urtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808); 3800} 3801 3802static int 3803urtwn_llt_init(struct urtwn_softc *sc) 3804{ 3805 int i, error, page_count, pktbuf_count; 3806 3807 page_count = (sc->chip & URTWN_CHIP_88E) ? 3808 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 3809 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 3810 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 3811 3812 /* Reserve pages [0; page_count]. */ 3813 for (i = 0; i < page_count; i++) { 3814 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3815 return (error); 3816 } 3817 /* NB: 0xff indicates end-of-list. */ 3818 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3819 return (error); 3820 /* 3821 * Use pages [page_count + 1; pktbuf_count - 1] 3822 * as ring buffer. 3823 */ 3824 for (++i; i < pktbuf_count - 1; i++) { 3825 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3826 return (error); 3827 } 3828 /* Make the last page point to the beginning of the ring buffer. */ 3829 error = urtwn_llt_write(sc, i, page_count + 1); 3830 return (error); 3831} 3832 3833#ifndef URTWN_WITHOUT_UCODE 3834static void 3835urtwn_fw_reset(struct urtwn_softc *sc) 3836{ 3837 uint16_t reg; 3838 int ntries; 3839 3840 /* Tell 8051 to reset itself. */ 3841 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3842 3843 /* Wait until 8051 resets by itself. */ 3844 for (ntries = 0; ntries < 100; ntries++) { 3845 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3846 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3847 return; 3848 urtwn_ms_delay(sc); 3849 } 3850 /* Force 8051 reset. */ 3851 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3852} 3853 3854static void 3855urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3856{ 3857 uint16_t reg; 3858 3859 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3860 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3861 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3862} 3863 3864static int 3865urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 3866{ 3867 uint32_t reg; 3868 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 3869 int off, mlen; 3870 3871 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3872 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3873 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3874 3875 off = R92C_FW_START_ADDR; 3876 while (len > 0) { 3877 if (len > 196) 3878 mlen = 196; 3879 else if (len > 4) 3880 mlen = 4; 3881 else 3882 mlen = 1; 3883 /* XXX fix this deconst */ 3884 error = urtwn_write_region_1(sc, off, 3885 __DECONST(uint8_t *, buf), mlen); 3886 if (error != USB_ERR_NORMAL_COMPLETION) 3887 break; 3888 off += mlen; 3889 buf += mlen; 3890 len -= mlen; 3891 } 3892 return (error); 3893} 3894 3895static int 3896urtwn_load_firmware(struct urtwn_softc *sc) 3897{ 3898 const struct firmware *fw; 3899 const struct r92c_fw_hdr *hdr; 3900 const char *imagename; 3901 const u_char *ptr; 3902 size_t len; 3903 uint32_t reg; 3904 int mlen, ntries, page, error; 3905 3906 URTWN_UNLOCK(sc); 3907 /* Read firmware image from the filesystem. */ 3908 if (sc->chip & URTWN_CHIP_88E) 3909 imagename = "urtwn-rtl8188eufw"; 3910 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3911 URTWN_CHIP_UMC_A_CUT) 3912 imagename = "urtwn-rtl8192cfwU"; 3913 else 3914 imagename = "urtwn-rtl8192cfwT"; 3915 3916 fw = firmware_get(imagename); 3917 URTWN_LOCK(sc); 3918 if (fw == NULL) { 3919 device_printf(sc->sc_dev, 3920 "failed loadfirmware of file %s\n", imagename); 3921 return (ENOENT); 3922 } 3923 3924 len = fw->datasize; 3925 3926 if (len < sizeof(*hdr)) { 3927 device_printf(sc->sc_dev, "firmware too short\n"); 3928 error = EINVAL; 3929 goto fail; 3930 } 3931 ptr = fw->data; 3932 hdr = (const struct r92c_fw_hdr *)ptr; 3933 /* Check if there is a valid FW header and skip it. */ 3934 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3935 (le16toh(hdr->signature) >> 4) == 0x88e || 3936 (le16toh(hdr->signature) >> 4) == 0x92c) { 3937 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, 3938 "FW V%d.%d %02d-%02d %02d:%02d\n", 3939 le16toh(hdr->version), le16toh(hdr->subversion), 3940 hdr->month, hdr->date, hdr->hour, hdr->minute); 3941 ptr += sizeof(*hdr); 3942 len -= sizeof(*hdr); 3943 } 3944 3945 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3946 if (sc->chip & URTWN_CHIP_88E) 3947 urtwn_r88e_fw_reset(sc); 3948 else 3949 urtwn_fw_reset(sc); 3950 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3951 } 3952 3953 if (!(sc->chip & URTWN_CHIP_88E)) { 3954 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3955 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3956 R92C_SYS_FUNC_EN_CPUEN); 3957 } 3958 urtwn_write_1(sc, R92C_MCUFWDL, 3959 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3960 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3961 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3962 3963 /* Reset the FWDL checksum. */ 3964 urtwn_write_1(sc, R92C_MCUFWDL, 3965 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3966 3967 for (page = 0; len > 0; page++) { 3968 mlen = min(len, R92C_FW_PAGE_SIZE); 3969 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3970 if (error != 0) { 3971 device_printf(sc->sc_dev, 3972 "could not load firmware page\n"); 3973 goto fail; 3974 } 3975 ptr += mlen; 3976 len -= mlen; 3977 } 3978 urtwn_write_1(sc, R92C_MCUFWDL, 3979 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3980 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3981 3982 /* Wait for checksum report. */ 3983 for (ntries = 0; ntries < 1000; ntries++) { 3984 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3985 break; 3986 urtwn_ms_delay(sc); 3987 } 3988 if (ntries == 1000) { 3989 device_printf(sc->sc_dev, 3990 "timeout waiting for checksum report\n"); 3991 error = ETIMEDOUT; 3992 goto fail; 3993 } 3994 3995 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3996 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3997 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3998 if (sc->chip & URTWN_CHIP_88E) 3999 urtwn_r88e_fw_reset(sc); 4000 /* Wait for firmware readiness. */ 4001 for (ntries = 0; ntries < 1000; ntries++) { 4002 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 4003 break; 4004 urtwn_ms_delay(sc); 4005 } 4006 if (ntries == 1000) { 4007 device_printf(sc->sc_dev, 4008 "timeout waiting for firmware readiness\n"); 4009 error = ETIMEDOUT; 4010 goto fail; 4011 } 4012fail: 4013 firmware_put(fw, FIRMWARE_UNLOAD); 4014 return (error); 4015} 4016#endif 4017 4018static int 4019urtwn_dma_init(struct urtwn_softc *sc) 4020{ 4021 struct usb_endpoint *ep, *ep_end; 4022 usb_error_t usb_err; 4023 uint32_t reg; 4024 int hashq, hasnq, haslq, nqueues, ntx; 4025 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 4026 4027 /* Initialize LLT table. */ 4028 error = urtwn_llt_init(sc); 4029 if (error != 0) 4030 return (error); 4031 4032 /* Determine the number of bulk-out pipes. */ 4033 ntx = 0; 4034 ep = sc->sc_udev->endpoints; 4035 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 4036 for (; ep != ep_end; ep++) { 4037 if ((ep->edesc == NULL) || 4038 (ep->iface_index != sc->sc_iface_index)) 4039 continue; 4040 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 4041 ntx++; 4042 } 4043 if (ntx == 0) { 4044 device_printf(sc->sc_dev, 4045 "%d: invalid number of Tx bulk pipes\n", ntx); 4046 return (EIO); 4047 } 4048 4049 /* Get Tx queues to USB endpoints mapping. */ 4050 hashq = hasnq = haslq = nqueues = 0; 4051 switch (ntx) { 4052 case 1: hashq = 1; break; 4053 case 2: hashq = hasnq = 1; break; 4054 case 3: case 4: hashq = hasnq = haslq = 1; break; 4055 } 4056 nqueues = hashq + hasnq + haslq; 4057 if (nqueues == 0) 4058 return (EIO); 4059 4060 npubqpages = nqpages = nrempages = pagecount = 0; 4061 if (sc->chip & URTWN_CHIP_88E) 4062 tx_boundary = R88E_TX_PAGE_BOUNDARY; 4063 else { 4064 pagecount = R92C_TX_PAGE_COUNT; 4065 npubqpages = R92C_PUBQ_NPAGES; 4066 tx_boundary = R92C_TX_PAGE_BOUNDARY; 4067 } 4068 4069 /* Set number of pages for normal priority queue. */ 4070 if (sc->chip & URTWN_CHIP_88E) { 4071 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 4072 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4073 return (EIO); 4074 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 4075 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4076 return (EIO); 4077 } else { 4078 /* Get the number of pages for each queue. */ 4079 nqpages = (pagecount - npubqpages) / nqueues; 4080 /* 4081 * The remaining pages are assigned to the high priority 4082 * queue. 4083 */ 4084 nrempages = (pagecount - npubqpages) % nqueues; 4085 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 4086 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4087 return (EIO); 4088 usb_err = urtwn_write_4(sc, R92C_RQPN, 4089 /* Set number of pages for public queue. */ 4090 SM(R92C_RQPN_PUBQ, npubqpages) | 4091 /* Set number of pages for high priority queue. */ 4092 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 4093 /* Set number of pages for low priority queue. */ 4094 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 4095 /* Load values. */ 4096 R92C_RQPN_LD); 4097 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4098 return (EIO); 4099 } 4100 4101 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 4102 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4103 return (EIO); 4104 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 4105 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4106 return (EIO); 4107 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 4108 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4109 return (EIO); 4110 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 4111 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4112 return (EIO); 4113 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 4114 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4115 return (EIO); 4116 4117 /* Set queue to USB pipe mapping. */ 4118 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4119 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4120 if (nqueues == 1) { 4121 if (hashq) 4122 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 4123 else if (hasnq) 4124 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 4125 else 4126 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4127 } else if (nqueues == 2) { 4128 /* 4129 * All 2-endpoints configs have high and normal 4130 * priority queues. 4131 */ 4132 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4133 } else 4134 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4135 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4136 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4137 return (EIO); 4138 4139 /* Set Tx/Rx transfer page boundary. */ 4140 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 4141 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 4142 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4143 return (EIO); 4144 4145 /* Set Tx/Rx transfer page size. */ 4146 usb_err = urtwn_write_1(sc, R92C_PBP, 4147 SM(R92C_PBP_PSRX, R92C_PBP_128) | 4148 SM(R92C_PBP_PSTX, R92C_PBP_128)); 4149 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4150 return (EIO); 4151 4152 return (0); 4153} 4154 4155static int 4156urtwn_mac_init(struct urtwn_softc *sc) 4157{ 4158 usb_error_t error; 4159 int i; 4160 4161 /* Write MAC initialization values. */ 4162 if (sc->chip & URTWN_CHIP_88E) { 4163 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 4164 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 4165 rtl8188eu_mac[i].val); 4166 if (error != USB_ERR_NORMAL_COMPLETION) 4167 return (EIO); 4168 } 4169 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 4170 } else { 4171 for (i = 0; i < nitems(rtl8192cu_mac); i++) 4172 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 4173 rtl8192cu_mac[i].val); 4174 if (error != USB_ERR_NORMAL_COMPLETION) 4175 return (EIO); 4176 } 4177 4178 return (0); 4179} 4180 4181static void 4182urtwn_bb_init(struct urtwn_softc *sc) 4183{ 4184 const struct urtwn_bb_prog *prog; 4185 uint32_t reg; 4186 uint8_t crystalcap; 4187 int i; 4188 4189 /* Enable BB and RF. */ 4190 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4191 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4192 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 4193 R92C_SYS_FUNC_EN_DIO_RF); 4194 4195 if (!(sc->chip & URTWN_CHIP_88E)) 4196 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 4197 4198 urtwn_write_1(sc, R92C_RF_CTRL, 4199 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 4200 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4201 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 4202 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 4203 4204 if (!(sc->chip & URTWN_CHIP_88E)) { 4205 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 4206 urtwn_write_1(sc, 0x15, 0xe9); 4207 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 4208 } 4209 4210 /* Select BB programming based on board type. */ 4211 if (sc->chip & URTWN_CHIP_88E) 4212 prog = &rtl8188eu_bb_prog; 4213 else if (!(sc->chip & URTWN_CHIP_92C)) { 4214 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4215 prog = &rtl8188ce_bb_prog; 4216 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4217 prog = &rtl8188ru_bb_prog; 4218 else 4219 prog = &rtl8188cu_bb_prog; 4220 } else { 4221 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4222 prog = &rtl8192ce_bb_prog; 4223 else 4224 prog = &rtl8192cu_bb_prog; 4225 } 4226 /* Write BB initialization values. */ 4227 for (i = 0; i < prog->count; i++) { 4228 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 4229 urtwn_ms_delay(sc); 4230 } 4231 4232 if (sc->chip & URTWN_CHIP_92C_1T2R) { 4233 /* 8192C 1T only configuration. */ 4234 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 4235 reg = (reg & ~0x00000003) | 0x2; 4236 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 4237 4238 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 4239 reg = (reg & ~0x00300033) | 0x00200022; 4240 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 4241 4242 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 4243 reg = (reg & ~0xff000000) | 0x45 << 24; 4244 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 4245 4246 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4247 reg = (reg & ~0x000000ff) | 0x23; 4248 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 4249 4250 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 4251 reg = (reg & ~0x00000030) | 1 << 4; 4252 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 4253 4254 reg = urtwn_bb_read(sc, 0xe74); 4255 reg = (reg & ~0x0c000000) | 2 << 26; 4256 urtwn_bb_write(sc, 0xe74, reg); 4257 reg = urtwn_bb_read(sc, 0xe78); 4258 reg = (reg & ~0x0c000000) | 2 << 26; 4259 urtwn_bb_write(sc, 0xe78, reg); 4260 reg = urtwn_bb_read(sc, 0xe7c); 4261 reg = (reg & ~0x0c000000) | 2 << 26; 4262 urtwn_bb_write(sc, 0xe7c, reg); 4263 reg = urtwn_bb_read(sc, 0xe80); 4264 reg = (reg & ~0x0c000000) | 2 << 26; 4265 urtwn_bb_write(sc, 0xe80, reg); 4266 reg = urtwn_bb_read(sc, 0xe88); 4267 reg = (reg & ~0x0c000000) | 2 << 26; 4268 urtwn_bb_write(sc, 0xe88, reg); 4269 } 4270 4271 /* Write AGC values. */ 4272 for (i = 0; i < prog->agccount; i++) { 4273 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 4274 prog->agcvals[i]); 4275 urtwn_ms_delay(sc); 4276 } 4277 4278 if (sc->chip & URTWN_CHIP_88E) { 4279 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4280 urtwn_ms_delay(sc); 4281 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4282 urtwn_ms_delay(sc); 4283 4284 crystalcap = sc->rom.r88e_rom.crystalcap; 4285 if (crystalcap == 0xff) 4286 crystalcap = 0x20; 4287 crystalcap &= 0x3f; 4288 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4289 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4290 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4291 crystalcap | crystalcap << 6)); 4292 } else { 4293 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4294 R92C_HSSI_PARAM2_CCK_HIPWR) 4295 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 4296 } 4297} 4298 4299static void 4300urtwn_rf_init(struct urtwn_softc *sc) 4301{ 4302 const struct urtwn_rf_prog *prog; 4303 uint32_t reg, type; 4304 int i, j, idx, off; 4305 4306 /* Select RF programming based on board type. */ 4307 if (sc->chip & URTWN_CHIP_88E) 4308 prog = rtl8188eu_rf_prog; 4309 else if (!(sc->chip & URTWN_CHIP_92C)) { 4310 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4311 prog = rtl8188ce_rf_prog; 4312 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4313 prog = rtl8188ru_rf_prog; 4314 else 4315 prog = rtl8188cu_rf_prog; 4316 } else 4317 prog = rtl8192ce_rf_prog; 4318 4319 for (i = 0; i < sc->nrxchains; i++) { 4320 /* Save RF_ENV control type. */ 4321 idx = i / 2; 4322 off = (i % 2) * 16; 4323 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4324 type = (reg >> off) & 0x10; 4325 4326 /* Set RF_ENV enable. */ 4327 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4328 reg |= 0x100000; 4329 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4330 urtwn_ms_delay(sc); 4331 /* Set RF_ENV output high. */ 4332 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4333 reg |= 0x10; 4334 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4335 urtwn_ms_delay(sc); 4336 /* Set address and data lengths of RF registers. */ 4337 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4338 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4339 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4340 urtwn_ms_delay(sc); 4341 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4342 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4343 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4344 urtwn_ms_delay(sc); 4345 4346 /* Write RF initialization values for this chain. */ 4347 for (j = 0; j < prog[i].count; j++) { 4348 if (prog[i].regs[j] >= 0xf9 && 4349 prog[i].regs[j] <= 0xfe) { 4350 /* 4351 * These are fake RF registers offsets that 4352 * indicate a delay is required. 4353 */ 4354 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 4355 continue; 4356 } 4357 urtwn_rf_write(sc, i, prog[i].regs[j], 4358 prog[i].vals[j]); 4359 urtwn_ms_delay(sc); 4360 } 4361 4362 /* Restore RF_ENV control type. */ 4363 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4364 reg &= ~(0x10 << off) | (type << off); 4365 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 4366 4367 /* Cache RF register CHNLBW. */ 4368 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4369 } 4370 4371 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4372 URTWN_CHIP_UMC_A_CUT) { 4373 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4374 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4375 } 4376} 4377 4378static void 4379urtwn_cam_init(struct urtwn_softc *sc) 4380{ 4381 /* Invalidate all CAM entries. */ 4382 urtwn_write_4(sc, R92C_CAMCMD, 4383 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4384} 4385 4386static int 4387urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 4388{ 4389 usb_error_t error; 4390 4391 error = urtwn_write_4(sc, R92C_CAMWRITE, data); 4392 if (error != USB_ERR_NORMAL_COMPLETION) 4393 return (EIO); 4394 error = urtwn_write_4(sc, R92C_CAMCMD, 4395 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 4396 SM(R92C_CAMCMD_ADDR, addr)); 4397 if (error != USB_ERR_NORMAL_COMPLETION) 4398 return (EIO); 4399 4400 return (0); 4401} 4402 4403static void 4404urtwn_pa_bias_init(struct urtwn_softc *sc) 4405{ 4406 uint8_t reg; 4407 int i; 4408 4409 for (i = 0; i < sc->nrxchains; i++) { 4410 if (sc->pa_setting & (1 << i)) 4411 continue; 4412 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4413 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4414 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4415 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4416 } 4417 if (!(sc->pa_setting & 0x10)) { 4418 reg = urtwn_read_1(sc, 0x16); 4419 reg = (reg & ~0xf0) | 0x90; 4420 urtwn_write_1(sc, 0x16, reg); 4421 } 4422} 4423 4424static void 4425urtwn_rxfilter_init(struct urtwn_softc *sc) 4426{ 4427 struct ieee80211com *ic = &sc->sc_ic; 4428 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4429 uint32_t rcr; 4430 uint16_t filter; 4431 4432 URTWN_ASSERT_LOCKED(sc); 4433 4434 /* Setup multicast filter. */ 4435 urtwn_set_multi(sc); 4436 4437 /* Filter for management frames. */ 4438 filter = 0x7f3f; 4439 switch (vap->iv_opmode) { 4440 case IEEE80211_M_STA: 4441 filter &= ~( 4442 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 4443 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 4444 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 4445 break; 4446 case IEEE80211_M_HOSTAP: 4447 filter &= ~( 4448 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 4449 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP)); 4450 break; 4451 case IEEE80211_M_MONITOR: 4452 case IEEE80211_M_IBSS: 4453 break; 4454 default: 4455 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4456 __func__, vap->iv_opmode); 4457 break; 4458 } 4459 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 4460 4461 /* Reject all control frames. */ 4462 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4463 4464 /* Reject all data frames. */ 4465 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 4466 4467 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 4468 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 4469 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 4470 4471 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 4472 /* Accept all frames. */ 4473 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 4474 R92C_RCR_AAP; 4475 } 4476 4477 /* Set Rx filter. */ 4478 urtwn_write_4(sc, R92C_RCR, rcr); 4479 4480 if (ic->ic_promisc != 0) { 4481 /* Update Rx filter. */ 4482 urtwn_set_promisc(sc); 4483 } 4484} 4485 4486static void 4487urtwn_edca_init(struct urtwn_softc *sc) 4488{ 4489 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4490 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4491 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4492 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4493 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4494 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4495 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4496 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4497} 4498 4499static void 4500urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4501 uint16_t power[URTWN_RIDX_COUNT]) 4502{ 4503 uint32_t reg; 4504 4505 /* Write per-CCK rate Tx power. */ 4506 if (chain == 0) { 4507 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4508 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4509 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4510 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4511 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4512 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4513 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4514 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4515 } else { 4516 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4517 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4518 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4519 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4520 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4521 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4522 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4523 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4524 } 4525 /* Write per-OFDM rate Tx power. */ 4526 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4527 SM(R92C_TXAGC_RATE06, power[ 4]) | 4528 SM(R92C_TXAGC_RATE09, power[ 5]) | 4529 SM(R92C_TXAGC_RATE12, power[ 6]) | 4530 SM(R92C_TXAGC_RATE18, power[ 7])); 4531 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4532 SM(R92C_TXAGC_RATE24, power[ 8]) | 4533 SM(R92C_TXAGC_RATE36, power[ 9]) | 4534 SM(R92C_TXAGC_RATE48, power[10]) | 4535 SM(R92C_TXAGC_RATE54, power[11])); 4536 /* Write per-MCS Tx power. */ 4537 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4538 SM(R92C_TXAGC_MCS00, power[12]) | 4539 SM(R92C_TXAGC_MCS01, power[13]) | 4540 SM(R92C_TXAGC_MCS02, power[14]) | 4541 SM(R92C_TXAGC_MCS03, power[15])); 4542 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4543 SM(R92C_TXAGC_MCS04, power[16]) | 4544 SM(R92C_TXAGC_MCS05, power[17]) | 4545 SM(R92C_TXAGC_MCS06, power[18]) | 4546 SM(R92C_TXAGC_MCS07, power[19])); 4547 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4548 SM(R92C_TXAGC_MCS08, power[20]) | 4549 SM(R92C_TXAGC_MCS09, power[21]) | 4550 SM(R92C_TXAGC_MCS10, power[22]) | 4551 SM(R92C_TXAGC_MCS11, power[23])); 4552 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4553 SM(R92C_TXAGC_MCS12, power[24]) | 4554 SM(R92C_TXAGC_MCS13, power[25]) | 4555 SM(R92C_TXAGC_MCS14, power[26]) | 4556 SM(R92C_TXAGC_MCS15, power[27])); 4557} 4558 4559static void 4560urtwn_get_txpower(struct urtwn_softc *sc, int chain, 4561 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4562 uint16_t power[URTWN_RIDX_COUNT]) 4563{ 4564 struct ieee80211com *ic = &sc->sc_ic; 4565 struct r92c_rom *rom = &sc->rom.r92c_rom; 4566 uint16_t cckpow, ofdmpow, htpow, diff, max; 4567 const struct urtwn_txpwr *base; 4568 int ridx, chan, group; 4569 4570 /* Determine channel group. */ 4571 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4572 if (chan <= 3) 4573 group = 0; 4574 else if (chan <= 9) 4575 group = 1; 4576 else 4577 group = 2; 4578 4579 /* Get original Tx power based on board type and RF chain. */ 4580 if (!(sc->chip & URTWN_CHIP_92C)) { 4581 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4582 base = &rtl8188ru_txagc[chain]; 4583 else 4584 base = &rtl8192cu_txagc[chain]; 4585 } else 4586 base = &rtl8192cu_txagc[chain]; 4587 4588 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4589 if (sc->regulatory == 0) { 4590 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4591 power[ridx] = base->pwr[0][ridx]; 4592 } 4593 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4594 if (sc->regulatory == 3) { 4595 power[ridx] = base->pwr[0][ridx]; 4596 /* Apply vendor limits. */ 4597 if (extc != NULL) 4598 max = rom->ht40_max_pwr[group]; 4599 else 4600 max = rom->ht20_max_pwr[group]; 4601 max = (max >> (chain * 4)) & 0xf; 4602 if (power[ridx] > max) 4603 power[ridx] = max; 4604 } else if (sc->regulatory == 1) { 4605 if (extc == NULL) 4606 power[ridx] = base->pwr[group][ridx]; 4607 } else if (sc->regulatory != 2) 4608 power[ridx] = base->pwr[0][ridx]; 4609 } 4610 4611 /* Compute per-CCK rate Tx power. */ 4612 cckpow = rom->cck_tx_pwr[chain][group]; 4613 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4614 power[ridx] += cckpow; 4615 if (power[ridx] > R92C_MAX_TX_PWR) 4616 power[ridx] = R92C_MAX_TX_PWR; 4617 } 4618 4619 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4620 if (sc->ntxchains > 1) { 4621 /* Apply reduction for 2 spatial streams. */ 4622 diff = rom->ht40_2s_tx_pwr_diff[group]; 4623 diff = (diff >> (chain * 4)) & 0xf; 4624 htpow = (htpow > diff) ? htpow - diff : 0; 4625 } 4626 4627 /* Compute per-OFDM rate Tx power. */ 4628 diff = rom->ofdm_tx_pwr_diff[group]; 4629 diff = (diff >> (chain * 4)) & 0xf; 4630 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4631 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4632 power[ridx] += ofdmpow; 4633 if (power[ridx] > R92C_MAX_TX_PWR) 4634 power[ridx] = R92C_MAX_TX_PWR; 4635 } 4636 4637 /* Compute per-MCS Tx power. */ 4638 if (extc == NULL) { 4639 diff = rom->ht20_tx_pwr_diff[group]; 4640 diff = (diff >> (chain * 4)) & 0xf; 4641 htpow += diff; /* HT40->HT20 correction. */ 4642 } 4643 for (ridx = 12; ridx <= 27; ridx++) { 4644 power[ridx] += htpow; 4645 if (power[ridx] > R92C_MAX_TX_PWR) 4646 power[ridx] = R92C_MAX_TX_PWR; 4647 } 4648#ifdef USB_DEBUG 4649 if (sc->sc_debug & URTWN_DEBUG_TXPWR) { 4650 /* Dump per-rate Tx power values. */ 4651 printf("Tx power for chain %d:\n", chain); 4652 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 4653 printf("Rate %d = %u\n", ridx, power[ridx]); 4654 } 4655#endif 4656} 4657 4658static void 4659urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 4660 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4661 uint16_t power[URTWN_RIDX_COUNT]) 4662{ 4663 struct ieee80211com *ic = &sc->sc_ic; 4664 struct r88e_rom *rom = &sc->rom.r88e_rom; 4665 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4666 const struct urtwn_r88e_txpwr *base; 4667 int ridx, chan, group; 4668 4669 /* Determine channel group. */ 4670 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4671 if (chan <= 2) 4672 group = 0; 4673 else if (chan <= 5) 4674 group = 1; 4675 else if (chan <= 8) 4676 group = 2; 4677 else if (chan <= 11) 4678 group = 3; 4679 else if (chan <= 13) 4680 group = 4; 4681 else 4682 group = 5; 4683 4684 /* Get original Tx power based on board type and RF chain. */ 4685 base = &rtl8188eu_txagc[chain]; 4686 4687 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4688 if (sc->regulatory == 0) { 4689 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4690 power[ridx] = base->pwr[0][ridx]; 4691 } 4692 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4693 if (sc->regulatory == 3) 4694 power[ridx] = base->pwr[0][ridx]; 4695 else if (sc->regulatory == 1) { 4696 if (extc == NULL) 4697 power[ridx] = base->pwr[group][ridx]; 4698 } else if (sc->regulatory != 2) 4699 power[ridx] = base->pwr[0][ridx]; 4700 } 4701 4702 /* Compute per-CCK rate Tx power. */ 4703 cckpow = rom->cck_tx_pwr[group]; 4704 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4705 power[ridx] += cckpow; 4706 if (power[ridx] > R92C_MAX_TX_PWR) 4707 power[ridx] = R92C_MAX_TX_PWR; 4708 } 4709 4710 htpow = rom->ht40_tx_pwr[group]; 4711 4712 /* Compute per-OFDM rate Tx power. */ 4713 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4714 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4715 power[ridx] += ofdmpow; 4716 if (power[ridx] > R92C_MAX_TX_PWR) 4717 power[ridx] = R92C_MAX_TX_PWR; 4718 } 4719 4720 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4721 for (ridx = 12; ridx <= 27; ridx++) { 4722 power[ridx] += bw20pow; 4723 if (power[ridx] > R92C_MAX_TX_PWR) 4724 power[ridx] = R92C_MAX_TX_PWR; 4725 } 4726} 4727 4728static void 4729urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 4730 struct ieee80211_channel *extc) 4731{ 4732 uint16_t power[URTWN_RIDX_COUNT]; 4733 int i; 4734 4735 for (i = 0; i < sc->ntxchains; i++) { 4736 /* Compute per-rate Tx power values. */ 4737 if (sc->chip & URTWN_CHIP_88E) 4738 urtwn_r88e_get_txpower(sc, i, c, extc, power); 4739 else 4740 urtwn_get_txpower(sc, i, c, extc, power); 4741 /* Write per-rate Tx power values to hardware. */ 4742 urtwn_write_txpower(sc, i, power); 4743 } 4744} 4745 4746static void 4747urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 4748{ 4749 uint32_t reg; 4750 4751 reg = urtwn_read_4(sc, R92C_RCR); 4752 if (enable) 4753 reg &= ~R92C_RCR_CBSSID_BCN; 4754 else 4755 reg |= R92C_RCR_CBSSID_BCN; 4756 urtwn_write_4(sc, R92C_RCR, reg); 4757} 4758 4759static void 4760urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 4761{ 4762 uint32_t reg; 4763 4764 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 4765 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4766 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 4767 4768 if (!(sc->chip & URTWN_CHIP_88E)) { 4769 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 4770 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4771 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 4772 } 4773} 4774 4775static void 4776urtwn_scan_start(struct ieee80211com *ic) 4777{ 4778 struct urtwn_softc *sc = ic->ic_softc; 4779 4780 URTWN_LOCK(sc); 4781 /* Receive beacons / probe responses from any BSSID. */ 4782 if (ic->ic_opmode != IEEE80211_M_IBSS && 4783 ic->ic_opmode != IEEE80211_M_HOSTAP) 4784 urtwn_set_rx_bssid_all(sc, 1); 4785 4786 /* Set gain for scanning. */ 4787 urtwn_set_gain(sc, 0x20); 4788 URTWN_UNLOCK(sc); 4789} 4790 4791static void 4792urtwn_scan_end(struct ieee80211com *ic) 4793{ 4794 struct urtwn_softc *sc = ic->ic_softc; 4795 4796 URTWN_LOCK(sc); 4797 /* Restore limitations. */ 4798 if (ic->ic_promisc == 0 && 4799 ic->ic_opmode != IEEE80211_M_IBSS && 4800 ic->ic_opmode != IEEE80211_M_HOSTAP) 4801 urtwn_set_rx_bssid_all(sc, 0); 4802 4803 /* Set gain under link. */ 4804 urtwn_set_gain(sc, 0x32); 4805 URTWN_UNLOCK(sc); 4806} 4807 4808static void 4809urtwn_getradiocaps(struct ieee80211com *ic, 4810 int maxchans, int *nchans, struct ieee80211_channel chans[]) 4811{ 4812 uint8_t bands[IEEE80211_MODE_BYTES]; 4813 4814 memset(bands, 0, sizeof(bands)); 4815 setbit(bands, IEEE80211_MODE_11B); 4816 setbit(bands, IEEE80211_MODE_11G); 4817 if (urtwn_enable_11n) 4818 setbit(bands, IEEE80211_MODE_11NG); 4819 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 4820 urtwn_chan_2ghz, nitems(urtwn_chan_2ghz), bands, 0); 4821} 4822 4823static void 4824urtwn_set_channel(struct ieee80211com *ic) 4825{ 4826 struct urtwn_softc *sc = ic->ic_softc; 4827 struct ieee80211_channel *c = ic->ic_curchan; 4828 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4829 4830 URTWN_LOCK(sc); 4831 if (vap->iv_state == IEEE80211_S_SCAN) { 4832 /* Make link LED blink during scan. */ 4833 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 4834 } 4835 urtwn_set_chan(sc, c, NULL); 4836 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 4837 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 4838 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 4839 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 4840 URTWN_UNLOCK(sc); 4841} 4842 4843static int 4844urtwn_wme_update(struct ieee80211com *ic) 4845{ 4846 const struct wmeParams *wmep = 4847 ic->ic_wme.wme_chanParams.cap_wmeParams; 4848 struct urtwn_softc *sc = ic->ic_softc; 4849 uint8_t aifs, acm, slottime; 4850 int ac; 4851 4852 acm = 0; 4853 slottime = IEEE80211_GET_SLOTTIME(ic); 4854 4855 URTWN_LOCK(sc); 4856 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4857 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4858 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4859 urtwn_write_4(sc, wme2queue[ac].reg, 4860 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 4861 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 4862 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 4863 SM(R92C_EDCA_PARAM_AIFS, aifs)); 4864 if (ac != WME_AC_BE) 4865 acm |= wmep[ac].wmep_acm << ac; 4866 } 4867 4868 if (acm != 0) 4869 acm |= R92C_ACMHWCTRL_EN; 4870 urtwn_write_1(sc, R92C_ACMHWCTRL, 4871 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 4872 acm); 4873 4874 URTWN_UNLOCK(sc); 4875 4876 return 0; 4877} 4878 4879static void 4880urtwn_update_slot(struct ieee80211com *ic) 4881{ 4882 urtwn_cmd_sleepable(ic->ic_softc, NULL, 0, urtwn_update_slot_cb); 4883} 4884 4885static void 4886urtwn_update_slot_cb(struct urtwn_softc *sc, union sec_param *data) 4887{ 4888 struct ieee80211com *ic = &sc->sc_ic; 4889 uint8_t slottime; 4890 4891 slottime = IEEE80211_GET_SLOTTIME(ic); 4892 4893 URTWN_DPRINTF(sc, URTWN_DEBUG_ANY, "%s: setting slot time to %uus\n", 4894 __func__, slottime); 4895 4896 urtwn_write_1(sc, R92C_SLOT, slottime); 4897 urtwn_update_aifs(sc, slottime); 4898} 4899 4900static void 4901urtwn_update_aifs(struct urtwn_softc *sc, uint8_t slottime) 4902{ 4903 const struct wmeParams *wmep = 4904 sc->sc_ic.ic_wme.wme_chanParams.cap_wmeParams; 4905 uint8_t aifs, ac; 4906 4907 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4908 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4909 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4910 urtwn_write_1(sc, wme2queue[ac].reg, aifs); 4911 } 4912} 4913 4914static uint8_t 4915urtwn_get_multi_pos(const uint8_t maddr[]) 4916{ 4917 uint64_t mask = 0x00004d101df481b4; 4918 uint8_t pos = 0x27; /* initial value */ 4919 int i, j; 4920 4921 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 4922 for (j = (i == 0) ? 1 : 0; j < 8; j++) 4923 if ((maddr[i] >> j) & 1) 4924 pos ^= (mask >> (i * 8 + j - 1)); 4925 4926 pos &= 0x3f; 4927 4928 return (pos); 4929} 4930 4931static void 4932urtwn_set_multi(struct urtwn_softc *sc) 4933{ 4934 struct ieee80211com *ic = &sc->sc_ic; 4935 uint32_t mfilt[2]; 4936 4937 URTWN_ASSERT_LOCKED(sc); 4938 4939 /* general structure was copied from ath(4). */ 4940 if (ic->ic_allmulti == 0) { 4941 struct ieee80211vap *vap; 4942 struct ifnet *ifp; 4943 struct ifmultiaddr *ifma; 4944 4945 /* 4946 * Merge multicast addresses to form the hardware filter. 4947 */ 4948 mfilt[0] = mfilt[1] = 0; 4949 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 4950 ifp = vap->iv_ifp; 4951 if_maddr_rlock(ifp); 4952 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4953 caddr_t dl; 4954 uint8_t pos; 4955 4956 dl = LLADDR((struct sockaddr_dl *) 4957 ifma->ifma_addr); 4958 pos = urtwn_get_multi_pos(dl); 4959 4960 mfilt[pos / 32] |= (1 << (pos % 32)); 4961 } 4962 if_maddr_runlock(ifp); 4963 } 4964 } else 4965 mfilt[0] = mfilt[1] = ~0; 4966 4967 4968 urtwn_write_4(sc, R92C_MAR + 0, mfilt[0]); 4969 urtwn_write_4(sc, R92C_MAR + 4, mfilt[1]); 4970 4971 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s: MC filter %08x:%08x\n", 4972 __func__, mfilt[0], mfilt[1]); 4973} 4974 4975static void 4976urtwn_set_promisc(struct urtwn_softc *sc) 4977{ 4978 struct ieee80211com *ic = &sc->sc_ic; 4979 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4980 uint32_t rcr, mask1, mask2; 4981 4982 URTWN_ASSERT_LOCKED(sc); 4983 4984 if (vap->iv_opmode == IEEE80211_M_MONITOR) 4985 return; 4986 4987 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 4988 mask2 = R92C_RCR_APM; 4989 4990 if (vap->iv_state == IEEE80211_S_RUN) { 4991 switch (vap->iv_opmode) { 4992 case IEEE80211_M_STA: 4993 mask2 |= R92C_RCR_CBSSID_BCN; 4994 /* FALLTHROUGH */ 4995 case IEEE80211_M_IBSS: 4996 mask2 |= R92C_RCR_CBSSID_DATA; 4997 break; 4998 case IEEE80211_M_HOSTAP: 4999 break; 5000 default: 5001 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 5002 __func__, vap->iv_opmode); 5003 return; 5004 } 5005 } 5006 5007 rcr = urtwn_read_4(sc, R92C_RCR); 5008 if (ic->ic_promisc == 0) 5009 rcr = (rcr & ~mask1) | mask2; 5010 else 5011 rcr = (rcr & ~mask2) | mask1; 5012 urtwn_write_4(sc, R92C_RCR, rcr); 5013} 5014 5015static void 5016urtwn_update_promisc(struct ieee80211com *ic) 5017{ 5018 struct urtwn_softc *sc = ic->ic_softc; 5019 5020 URTWN_LOCK(sc); 5021 if (sc->sc_flags & URTWN_RUNNING) 5022 urtwn_set_promisc(sc); 5023 URTWN_UNLOCK(sc); 5024} 5025 5026static void 5027urtwn_update_mcast(struct ieee80211com *ic) 5028{ 5029 struct urtwn_softc *sc = ic->ic_softc; 5030 5031 URTWN_LOCK(sc); 5032 if (sc->sc_flags & URTWN_RUNNING) 5033 urtwn_set_multi(sc); 5034 URTWN_UNLOCK(sc); 5035} 5036 5037static struct ieee80211_node * 5038urtwn_node_alloc(struct ieee80211vap *vap, 5039 const uint8_t mac[IEEE80211_ADDR_LEN]) 5040{ 5041 struct urtwn_node *un; 5042 5043 un = malloc(sizeof (struct urtwn_node), M_80211_NODE, 5044 M_NOWAIT | M_ZERO); 5045 5046 if (un == NULL) 5047 return NULL; 5048 5049 un->id = URTWN_MACID_UNDEFINED; 5050 5051 return &un->ni; 5052} 5053 5054static void 5055urtwn_newassoc(struct ieee80211_node *ni, int isnew) 5056{ 5057 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 5058 struct urtwn_node *un = URTWN_NODE(ni); 5059 uint8_t id; 5060 5061 /* Only do this bit for R88E chips */ 5062 if (! (sc->chip & URTWN_CHIP_88E)) 5063 return; 5064 5065 if (!isnew) 5066 return; 5067 5068 URTWN_NT_LOCK(sc); 5069 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 5070 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 5071 un->id = id; 5072 sc->node_list[id] = ni; 5073 break; 5074 } 5075 } 5076 URTWN_NT_UNLOCK(sc); 5077 5078 if (id > URTWN_MACID_MAX(sc)) { 5079 device_printf(sc->sc_dev, "%s: node table is full\n", 5080 __func__); 5081 } 5082} 5083 5084static void 5085urtwn_node_free(struct ieee80211_node *ni) 5086{ 5087 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 5088 struct urtwn_node *un = URTWN_NODE(ni); 5089 5090 URTWN_NT_LOCK(sc); 5091 if (un->id != URTWN_MACID_UNDEFINED) 5092 sc->node_list[un->id] = NULL; 5093 URTWN_NT_UNLOCK(sc); 5094 5095 sc->sc_node_free(ni); 5096} 5097 5098static void 5099urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 5100 struct ieee80211_channel *extc) 5101{ 5102 struct ieee80211com *ic = &sc->sc_ic; 5103 uint32_t reg; 5104 u_int chan; 5105 int i; 5106 5107 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 5108 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 5109 device_printf(sc->sc_dev, 5110 "%s: invalid channel %x\n", __func__, chan); 5111 return; 5112 } 5113 5114 /* Set Tx power for this new channel. */ 5115 urtwn_set_txpower(sc, c, extc); 5116 5117 for (i = 0; i < sc->nrxchains; i++) { 5118 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 5119 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 5120 } 5121#ifndef IEEE80211_NO_HT 5122 if (extc != NULL) { 5123 /* Is secondary channel below or above primary? */ 5124 int prichlo = c->ic_freq < extc->ic_freq; 5125 5126 urtwn_write_1(sc, R92C_BWOPMODE, 5127 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 5128 5129 reg = urtwn_read_1(sc, R92C_RRSR + 2); 5130 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 5131 urtwn_write_1(sc, R92C_RRSR + 2, reg); 5132 5133 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5134 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 5135 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5136 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 5137 5138 /* Set CCK side band. */ 5139 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 5140 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 5141 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 5142 5143 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 5144 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 5145 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 5146 5147 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5148 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 5149 ~R92C_FPGA0_ANAPARAM2_CBW20); 5150 5151 reg = urtwn_bb_read(sc, 0x818); 5152 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 5153 urtwn_bb_write(sc, 0x818, reg); 5154 5155 /* Select 40MHz bandwidth. */ 5156 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5157 (sc->rf_chnlbw[0] & ~0xfff) | chan); 5158 } else 5159#endif 5160 { 5161 urtwn_write_1(sc, R92C_BWOPMODE, 5162 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 5163 5164 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5165 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 5166 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5167 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 5168 5169 if (!(sc->chip & URTWN_CHIP_88E)) { 5170 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5171 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 5172 R92C_FPGA0_ANAPARAM2_CBW20); 5173 } 5174 5175 /* Select 20MHz bandwidth. */ 5176 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5177 (sc->rf_chnlbw[0] & ~0xfff) | chan | 5178 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 5179 R92C_RF_CHNLBW_BW20)); 5180 } 5181} 5182 5183static void 5184urtwn_iq_calib(struct urtwn_softc *sc) 5185{ 5186 /* TODO */ 5187} 5188 5189static void 5190urtwn_lc_calib(struct urtwn_softc *sc) 5191{ 5192 uint32_t rf_ac[2]; 5193 uint8_t txmode; 5194 int i; 5195 5196 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 5197 if ((txmode & 0x70) != 0) { 5198 /* Disable all continuous Tx. */ 5199 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 5200 5201 /* Set RF mode to standby mode. */ 5202 for (i = 0; i < sc->nrxchains; i++) { 5203 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 5204 urtwn_rf_write(sc, i, R92C_RF_AC, 5205 RW(rf_ac[i], R92C_RF_AC_MODE, 5206 R92C_RF_AC_MODE_STANDBY)); 5207 } 5208 } else { 5209 /* Block all Tx queues. */ 5210 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 5211 } 5212 /* Start calibration. */ 5213 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5214 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 5215 5216 /* Give calibration the time to complete. */ 5217 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 5218 5219 /* Restore configuration. */ 5220 if ((txmode & 0x70) != 0) { 5221 /* Restore Tx mode. */ 5222 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 5223 /* Restore RF mode. */ 5224 for (i = 0; i < sc->nrxchains; i++) 5225 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 5226 } else { 5227 /* Unblock all Tx queues. */ 5228 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 5229 } 5230} 5231 5232static void 5233urtwn_temp_calib(struct urtwn_softc *sc) 5234{ 5235 uint8_t temp; 5236 5237 URTWN_ASSERT_LOCKED(sc); 5238 5239 if (!(sc->sc_flags & URTWN_TEMP_MEASURED)) { 5240 /* Start measuring temperature. */ 5241 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5242 "%s: start measuring temperature\n", __func__); 5243 if (sc->chip & URTWN_CHIP_88E) { 5244 urtwn_rf_write(sc, 0, R88E_RF_T_METER, 5245 R88E_RF_T_METER_START); 5246 } else { 5247 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 5248 R92C_RF_T_METER_START); 5249 } 5250 sc->sc_flags |= URTWN_TEMP_MEASURED; 5251 return; 5252 } 5253 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 5254 5255 /* Read measured temperature. */ 5256 if (sc->chip & URTWN_CHIP_88E) { 5257 temp = MS(urtwn_rf_read(sc, 0, R88E_RF_T_METER), 5258 R88E_RF_T_METER_VAL); 5259 } else { 5260 temp = MS(urtwn_rf_read(sc, 0, R92C_RF_T_METER), 5261 R92C_RF_T_METER_VAL); 5262 } 5263 if (temp == 0) { /* Read failed, skip. */ 5264 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5265 "%s: temperature read failed, skipping\n", __func__); 5266 return; 5267 } 5268 5269 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5270 "%s: temperature: previous %u, current %u\n", 5271 __func__, sc->thcal_lctemp, temp); 5272 5273 /* 5274 * Redo LC calibration if temperature changed significantly since 5275 * last calibration. 5276 */ 5277 if (sc->thcal_lctemp == 0) { 5278 /* First LC calibration is performed in urtwn_init(). */ 5279 sc->thcal_lctemp = temp; 5280 } else if (abs(temp - sc->thcal_lctemp) > 1) { 5281 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5282 "%s: LC calib triggered by temp: %u -> %u\n", 5283 __func__, sc->thcal_lctemp, temp); 5284 urtwn_lc_calib(sc); 5285 /* Record temperature of last LC calibration. */ 5286 sc->thcal_lctemp = temp; 5287 } 5288} 5289 5290static void 5291urtwn_setup_static_keys(struct urtwn_softc *sc, struct urtwn_vap *uvp) 5292{ 5293 int i; 5294 5295 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 5296 const struct ieee80211_key *k = uvp->keys[i]; 5297 if (k != NULL) { 5298 urtwn_cmd_sleepable(sc, k, sizeof(*k), 5299 urtwn_key_set_cb); 5300 } 5301 } 5302} 5303 5304static int 5305urtwn_init(struct urtwn_softc *sc) 5306{ 5307 struct ieee80211com *ic = &sc->sc_ic; 5308 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5309 uint8_t macaddr[IEEE80211_ADDR_LEN]; 5310 uint32_t reg; 5311 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 5312 int error; 5313 5314 URTWN_LOCK(sc); 5315 if (sc->sc_flags & URTWN_RUNNING) { 5316 URTWN_UNLOCK(sc); 5317 return (0); 5318 } 5319 5320 /* Init firmware commands ring. */ 5321 sc->fwcur = 0; 5322 5323 /* Allocate Tx/Rx buffers. */ 5324 error = urtwn_alloc_rx_list(sc); 5325 if (error != 0) 5326 goto fail; 5327 5328 error = urtwn_alloc_tx_list(sc); 5329 if (error != 0) 5330 goto fail; 5331 5332 /* Power on adapter. */ 5333 error = urtwn_power_on(sc); 5334 if (error != 0) 5335 goto fail; 5336 5337 /* Initialize DMA. */ 5338 error = urtwn_dma_init(sc); 5339 if (error != 0) 5340 goto fail; 5341 5342 /* Set info size in Rx descriptors (in 64-bit words). */ 5343 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 5344 5345 /* Init interrupts. */ 5346 if (sc->chip & URTWN_CHIP_88E) { 5347 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 5348 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5349 goto fail; 5350 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 5351 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 5352 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5353 goto fail; 5354 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 5355 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 5356 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5357 goto fail; 5358 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5359 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5360 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 5361 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5362 goto fail; 5363 } else { 5364 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 5365 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5366 goto fail; 5367 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 5368 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5369 goto fail; 5370 } 5371 5372 /* Set MAC address. */ 5373 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 5374 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 5375 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5376 goto fail; 5377 5378 /* Set initial network type. */ 5379 urtwn_set_mode(sc, R92C_MSR_INFRA); 5380 5381 /* Initialize Rx filter. */ 5382 urtwn_rxfilter_init(sc); 5383 5384 /* Set response rate. */ 5385 reg = urtwn_read_4(sc, R92C_RRSR); 5386 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5387 urtwn_write_4(sc, R92C_RRSR, reg); 5388 5389 /* Set short/long retry limits. */ 5390 urtwn_write_2(sc, R92C_RL, 5391 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5392 5393 /* Initialize EDCA parameters. */ 5394 urtwn_edca_init(sc); 5395 5396 /* Setup rate fallback. */ 5397 if (!(sc->chip & URTWN_CHIP_88E)) { 5398 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5399 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5400 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5401 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5402 } 5403 5404 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5405 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5406 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5407 /* Set ACK timeout. */ 5408 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5409 5410 /* Setup USB aggregation. */ 5411 reg = urtwn_read_4(sc, R92C_TDECTRL); 5412 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5413 urtwn_write_4(sc, R92C_TDECTRL, reg); 5414 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5415 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5416 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5417 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5418 if (sc->chip & URTWN_CHIP_88E) 5419 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5420 else { 5421 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5422 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5423 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5424 R92C_USB_SPECIAL_OPTION_AGG_EN); 5425 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 5426 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 5427 } 5428 5429 /* Initialize beacon parameters. */ 5430 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5431 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5432 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 5433 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 5434 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5435 5436 if (!(sc->chip & URTWN_CHIP_88E)) { 5437 /* Setup AMPDU aggregation. */ 5438 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5439 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5440 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 5441 5442 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5443 } 5444 5445#ifndef URTWN_WITHOUT_UCODE 5446 /* Load 8051 microcode. */ 5447 error = urtwn_load_firmware(sc); 5448 if (error == 0) 5449 sc->sc_flags |= URTWN_FW_LOADED; 5450#endif 5451 5452 /* Initialize MAC/BB/RF blocks. */ 5453 error = urtwn_mac_init(sc); 5454 if (error != 0) { 5455 device_printf(sc->sc_dev, 5456 "%s: error while initializing MAC block\n", __func__); 5457 goto fail; 5458 } 5459 urtwn_bb_init(sc); 5460 urtwn_rf_init(sc); 5461 5462 /* Reinitialize Rx filter (D3845 is not committed yet). */ 5463 urtwn_rxfilter_init(sc); 5464 5465 if (sc->chip & URTWN_CHIP_88E) { 5466 urtwn_write_2(sc, R92C_CR, 5467 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5468 R92C_CR_MACRXEN); 5469 } 5470 5471 /* Turn CCK and OFDM blocks on. */ 5472 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5473 reg |= R92C_RFMOD_CCK_EN; 5474 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5475 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5476 goto fail; 5477 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5478 reg |= R92C_RFMOD_OFDM_EN; 5479 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5480 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5481 goto fail; 5482 5483 /* Clear per-station keys table. */ 5484 urtwn_cam_init(sc); 5485 5486 /* Enable decryption / encryption. */ 5487 urtwn_write_2(sc, R92C_SECCFG, 5488 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 5489 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA | 5490 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 5491 5492 /* Enable hardware sequence numbering. */ 5493 urtwn_write_1(sc, R92C_HWSEQ_CTRL, R92C_TX_QUEUE_ALL); 5494 5495 /* Enable per-packet TX report. */ 5496 if (sc->chip & URTWN_CHIP_88E) { 5497 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 5498 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 5499 } 5500 5501 /* Perform LO and IQ calibrations. */ 5502 urtwn_iq_calib(sc); 5503 /* Perform LC calibration. */ 5504 urtwn_lc_calib(sc); 5505 5506 /* Fix USB interference issue. */ 5507 if (!(sc->chip & URTWN_CHIP_88E)) { 5508 urtwn_write_1(sc, 0xfe40, 0xe0); 5509 urtwn_write_1(sc, 0xfe41, 0x8d); 5510 urtwn_write_1(sc, 0xfe42, 0x80); 5511 5512 urtwn_pa_bias_init(sc); 5513 } 5514 5515 /* Initialize GPIO setting. */ 5516 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5517 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5518 5519 /* Fix for lower temperature. */ 5520 if (!(sc->chip & URTWN_CHIP_88E)) 5521 urtwn_write_1(sc, 0x15, 0xe9); 5522 5523 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 5524 5525 sc->sc_flags |= URTWN_RUNNING; 5526 5527 /* 5528 * Install static keys (if any). 5529 * Must be called after urtwn_cam_init(). 5530 */ 5531 if (vap != NULL) 5532 urtwn_setup_static_keys(sc, URTWN_VAP(vap)); 5533 5534 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5535fail: 5536 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5537 error = EIO; 5538 5539 URTWN_UNLOCK(sc); 5540 5541 return (error); 5542} 5543 5544static void 5545urtwn_stop(struct urtwn_softc *sc) 5546{ 5547 5548 URTWN_LOCK(sc); 5549 if (!(sc->sc_flags & URTWN_RUNNING)) { 5550 URTWN_UNLOCK(sc); 5551 return; 5552 } 5553 5554 sc->sc_flags &= ~(URTWN_RUNNING | URTWN_FW_LOADED | 5555 URTWN_TEMP_MEASURED); 5556 sc->thcal_lctemp = 0; 5557 callout_stop(&sc->sc_watchdog_ch); 5558 5559 urtwn_abort_xfers(sc); 5560 urtwn_drain_mbufq(sc); 5561 urtwn_free_tx_list(sc); 5562 urtwn_free_rx_list(sc); 5563 urtwn_power_off(sc); 5564 URTWN_UNLOCK(sc); 5565} 5566 5567static void 5568urtwn_abort_xfers(struct urtwn_softc *sc) 5569{ 5570 int i; 5571 5572 URTWN_ASSERT_LOCKED(sc); 5573 5574 /* abort any pending transfers */ 5575 for (i = 0; i < URTWN_N_TRANSFER; i++) 5576 usbd_transfer_stop(sc->sc_xfer[i]); 5577} 5578 5579static int 5580urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5581 const struct ieee80211_bpf_params *params) 5582{ 5583 struct ieee80211com *ic = ni->ni_ic; 5584 struct urtwn_softc *sc = ic->ic_softc; 5585 struct urtwn_data *bf; 5586 int error; 5587 5588 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n", 5589 __func__, 5590 m); 5591 5592 /* prevent management frames from being sent if we're not ready */ 5593 URTWN_LOCK(sc); 5594 if (!(sc->sc_flags & URTWN_RUNNING)) { 5595 error = ENETDOWN; 5596 goto end; 5597 } 5598 5599 bf = urtwn_getbuf(sc); 5600 if (bf == NULL) { 5601 error = ENOBUFS; 5602 goto end; 5603 } 5604 5605 if (params == NULL) { 5606 /* 5607 * Legacy path; interpret frame contents to decide 5608 * precisely how to send the frame. 5609 */ 5610 error = urtwn_tx_data(sc, ni, m, bf); 5611 } else { 5612 /* 5613 * Caller supplied explicit parameters to use in 5614 * sending the frame. 5615 */ 5616 error = urtwn_tx_raw(sc, ni, m, bf, params); 5617 } 5618 if (error != 0) { 5619 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 5620 goto end; 5621 } 5622 5623 sc->sc_txtimer = 5; 5624 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5625 5626end: 5627 if (error != 0) 5628 m_freem(m); 5629 5630 URTWN_UNLOCK(sc); 5631 5632 return (error); 5633} 5634 5635static void 5636urtwn_ms_delay(struct urtwn_softc *sc) 5637{ 5638 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 5639} 5640 5641static device_method_t urtwn_methods[] = { 5642 /* Device interface */ 5643 DEVMETHOD(device_probe, urtwn_match), 5644 DEVMETHOD(device_attach, urtwn_attach), 5645 DEVMETHOD(device_detach, urtwn_detach), 5646 5647 DEVMETHOD_END 5648}; 5649 5650static driver_t urtwn_driver = { 5651 "urtwn", 5652 urtwn_methods, 5653 sizeof(struct urtwn_softc) 5654}; 5655 5656static devclass_t urtwn_devclass; 5657 5658DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 5659MODULE_DEPEND(urtwn, usb, 1, 1, 1); 5660MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 5661#ifndef URTWN_WITHOUT_UCODE 5662MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 5663#endif 5664MODULE_VERSION(urtwn, 1); 5665USB_PNP_HOST_INFO(urtwn_devs); 5666