if_urtwn.c revision 302183
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2015 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#include <sys/cdefs.h> 22__FBSDID("$FreeBSD: head/sys/dev/urtwn/if_urtwn.c 302183 2016-06-24 23:36:22Z avos $"); 23 24/* 25 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 26 */ 27 28#include "opt_wlan.h" 29#include "opt_urtwn.h" 30 31#include <sys/param.h> 32#include <sys/sockio.h> 33#include <sys/sysctl.h> 34#include <sys/lock.h> 35#include <sys/mutex.h> 36#include <sys/condvar.h> 37#include <sys/mbuf.h> 38#include <sys/kernel.h> 39#include <sys/socket.h> 40#include <sys/systm.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/bus.h> 44#include <sys/endian.h> 45#include <sys/linker.h> 46#include <sys/firmware.h> 47#include <sys/kdb.h> 48 49#include <machine/bus.h> 50#include <machine/resource.h> 51#include <sys/rman.h> 52 53#include <net/bpf.h> 54#include <net/if.h> 55#include <net/if_var.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61 62#include <netinet/in.h> 63#include <netinet/in_systm.h> 64#include <netinet/in_var.h> 65#include <netinet/if_ether.h> 66#include <netinet/ip.h> 67 68#include <net80211/ieee80211_var.h> 69#include <net80211/ieee80211_regdomain.h> 70#include <net80211/ieee80211_radiotap.h> 71#include <net80211/ieee80211_ratectl.h> 72#ifdef IEEE80211_SUPPORT_SUPERG 73#include <net80211/ieee80211_superg.h> 74#endif 75 76#include <dev/usb/usb.h> 77#include <dev/usb/usbdi.h> 78#include <dev/usb/usb_device.h> 79#include "usbdevs.h" 80 81#include <dev/usb/usb_debug.h> 82 83#include <dev/urtwn/if_urtwnreg.h> 84#include <dev/urtwn/if_urtwnvar.h> 85 86#ifdef USB_DEBUG 87enum { 88 URTWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 89 URTWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 90 URTWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 91 URTWN_DEBUG_RA = 0x00000008, /* f/w rate adaptation setup */ 92 URTWN_DEBUG_USB = 0x00000010, /* usb requests */ 93 URTWN_DEBUG_FIRMWARE = 0x00000020, /* firmware(9) loading debug */ 94 URTWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 95 URTWN_DEBUG_INTR = 0x00000080, /* ISR */ 96 URTWN_DEBUG_TEMP = 0x00000100, /* temperature calibration */ 97 URTWN_DEBUG_ROM = 0x00000200, /* various ROM info */ 98 URTWN_DEBUG_KEY = 0x00000400, /* crypto keys management */ 99 URTWN_DEBUG_TXPWR = 0x00000800, /* dump Tx power values */ 100 URTWN_DEBUG_RSSI = 0x00001000, /* dump RSSI lookups */ 101 URTWN_DEBUG_ANY = 0xffffffff 102}; 103 104#define URTWN_DPRINTF(_sc, _m, ...) do { \ 105 if ((_sc)->sc_debug & (_m)) \ 106 device_printf((_sc)->sc_dev, __VA_ARGS__); \ 107} while(0) 108 109#else 110#define URTWN_DPRINTF(_sc, _m, ...) do { (void) sc; } while (0) 111#endif 112 113#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 114 115static int urtwn_enable_11n = 1; 116TUNABLE_INT("hw.usb.urtwn.enable_11n", &urtwn_enable_11n); 117 118/* various supported device vendors/products */ 119static const STRUCT_USB_HOST_ID urtwn_devs[] = { 120#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 121#define URTWN_RTL8188E_DEV(v,p) \ 122 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 123#define URTWN_RTL8188E 1 124 URTWN_DEV(ABOCOM, RTL8188CU_1), 125 URTWN_DEV(ABOCOM, RTL8188CU_2), 126 URTWN_DEV(ABOCOM, RTL8192CU), 127 URTWN_DEV(ASUS, RTL8192CU), 128 URTWN_DEV(ASUS, USBN10NANO), 129 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 130 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 131 URTWN_DEV(AZUREWAVE, RTL8188CU), 132 URTWN_DEV(BELKIN, F7D2102), 133 URTWN_DEV(BELKIN, RTL8188CU), 134 URTWN_DEV(BELKIN, RTL8192CU), 135 URTWN_DEV(CHICONY, RTL8188CUS_1), 136 URTWN_DEV(CHICONY, RTL8188CUS_2), 137 URTWN_DEV(CHICONY, RTL8188CUS_3), 138 URTWN_DEV(CHICONY, RTL8188CUS_4), 139 URTWN_DEV(CHICONY, RTL8188CUS_5), 140 URTWN_DEV(COREGA, RTL8192CU), 141 URTWN_DEV(DLINK, RTL8188CU), 142 URTWN_DEV(DLINK, RTL8192CU_1), 143 URTWN_DEV(DLINK, RTL8192CU_2), 144 URTWN_DEV(DLINK, RTL8192CU_3), 145 URTWN_DEV(DLINK, DWA131B), 146 URTWN_DEV(EDIMAX, EW7811UN), 147 URTWN_DEV(EDIMAX, RTL8192CU), 148 URTWN_DEV(FEIXUN, RTL8188CU), 149 URTWN_DEV(FEIXUN, RTL8192CU), 150 URTWN_DEV(GUILLEMOT, HWNUP150), 151 URTWN_DEV(HAWKING, RTL8192CU), 152 URTWN_DEV(HP3, RTL8188CU), 153 URTWN_DEV(NETGEAR, WNA1000M), 154 URTWN_DEV(NETGEAR, RTL8192CU), 155 URTWN_DEV(NETGEAR4, RTL8188CU), 156 URTWN_DEV(NOVATECH, RTL8188CU), 157 URTWN_DEV(PLANEX2, RTL8188CU_1), 158 URTWN_DEV(PLANEX2, RTL8188CU_2), 159 URTWN_DEV(PLANEX2, RTL8188CU_3), 160 URTWN_DEV(PLANEX2, RTL8188CU_4), 161 URTWN_DEV(PLANEX2, RTL8188CUS), 162 URTWN_DEV(PLANEX2, RTL8192CU), 163 URTWN_DEV(REALTEK, RTL8188CE_0), 164 URTWN_DEV(REALTEK, RTL8188CE_1), 165 URTWN_DEV(REALTEK, RTL8188CTV), 166 URTWN_DEV(REALTEK, RTL8188CU_0), 167 URTWN_DEV(REALTEK, RTL8188CU_1), 168 URTWN_DEV(REALTEK, RTL8188CU_2), 169 URTWN_DEV(REALTEK, RTL8188CU_3), 170 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 171 URTWN_DEV(REALTEK, RTL8188CUS), 172 URTWN_DEV(REALTEK, RTL8188RU_1), 173 URTWN_DEV(REALTEK, RTL8188RU_2), 174 URTWN_DEV(REALTEK, RTL8188RU_3), 175 URTWN_DEV(REALTEK, RTL8191CU), 176 URTWN_DEV(REALTEK, RTL8192CE), 177 URTWN_DEV(REALTEK, RTL8192CU), 178 URTWN_DEV(SITECOMEU, RTL8188CU_1), 179 URTWN_DEV(SITECOMEU, RTL8188CU_2), 180 URTWN_DEV(SITECOMEU, RTL8192CU), 181 URTWN_DEV(TRENDNET, RTL8188CU), 182 URTWN_DEV(TRENDNET, RTL8192CU), 183 URTWN_DEV(ZYXEL, RTL8192CU), 184 /* URTWN_RTL8188E */ 185 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 186 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 187 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 188 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 189 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 190 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 191#undef URTWN_RTL8188E_DEV 192#undef URTWN_DEV 193}; 194 195static device_probe_t urtwn_match; 196static device_attach_t urtwn_attach; 197static device_detach_t urtwn_detach; 198 199static usb_callback_t urtwn_bulk_tx_callback; 200static usb_callback_t urtwn_bulk_rx_callback; 201 202static void urtwn_sysctlattach(struct urtwn_softc *); 203static void urtwn_drain_mbufq(struct urtwn_softc *); 204static usb_error_t urtwn_do_request(struct urtwn_softc *, 205 struct usb_device_request *, void *); 206static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 207 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 208 const uint8_t [IEEE80211_ADDR_LEN], 209 const uint8_t [IEEE80211_ADDR_LEN]); 210static void urtwn_vap_delete(struct ieee80211vap *); 211static void urtwn_vap_clear_tx(struct urtwn_softc *, 212 struct ieee80211vap *); 213static void urtwn_vap_clear_tx_queue(struct urtwn_softc *, 214 urtwn_datahead *, struct ieee80211vap *); 215static struct mbuf * urtwn_rx_copy_to_mbuf(struct urtwn_softc *, 216 struct r92c_rx_stat *, int); 217static struct mbuf * urtwn_report_intr(struct usb_xfer *, 218 struct urtwn_data *); 219static struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int); 220static void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 221 void *); 222static struct ieee80211_node *urtwn_rx_frame(struct urtwn_softc *, 223 struct mbuf *, int8_t *); 224static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 225 int); 226static int urtwn_alloc_list(struct urtwn_softc *, 227 struct urtwn_data[], int, int); 228static int urtwn_alloc_rx_list(struct urtwn_softc *); 229static int urtwn_alloc_tx_list(struct urtwn_softc *); 230static void urtwn_free_list(struct urtwn_softc *, 231 struct urtwn_data data[], int); 232static void urtwn_free_rx_list(struct urtwn_softc *); 233static void urtwn_free_tx_list(struct urtwn_softc *); 234static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 235static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 236static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 237 uint8_t *, int); 238static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 239static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 240static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 241static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 242 uint8_t *, int); 243static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 244static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 245static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 246static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 247 const void *, int); 248static void urtwn_cmdq_cb(void *, int); 249static int urtwn_cmd_sleepable(struct urtwn_softc *, const void *, 250 size_t, CMD_FUNC_PROTO); 251static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 252 uint8_t, uint32_t); 253static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 254 uint8_t, uint32_t); 255static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 256static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 257 uint32_t); 258static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 259static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 260 uint8_t, uint8_t); 261#ifdef USB_DEBUG 262static void urtwn_dump_rom_contents(struct urtwn_softc *, 263 uint8_t *, uint16_t); 264#endif 265static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 266 uint16_t); 267static int urtwn_efuse_switch_power(struct urtwn_softc *); 268static int urtwn_read_chipid(struct urtwn_softc *); 269static int urtwn_read_rom(struct urtwn_softc *); 270static int urtwn_r88e_read_rom(struct urtwn_softc *); 271static int urtwn_ra_init(struct urtwn_softc *); 272static void urtwn_init_beacon(struct urtwn_softc *, 273 struct urtwn_vap *); 274static int urtwn_setup_beacon(struct urtwn_softc *, 275 struct ieee80211_node *); 276static void urtwn_update_beacon(struct ieee80211vap *, int); 277static int urtwn_tx_beacon(struct urtwn_softc *sc, 278 struct urtwn_vap *); 279static int urtwn_key_alloc(struct ieee80211vap *, 280 struct ieee80211_key *, ieee80211_keyix *, 281 ieee80211_keyix *); 282static void urtwn_key_set_cb(struct urtwn_softc *, 283 union sec_param *); 284static void urtwn_key_del_cb(struct urtwn_softc *, 285 union sec_param *); 286static int urtwn_key_set(struct ieee80211vap *, 287 const struct ieee80211_key *); 288static int urtwn_key_delete(struct ieee80211vap *, 289 const struct ieee80211_key *); 290static void urtwn_tsf_task_adhoc(void *, int); 291static void urtwn_tsf_sync_enable(struct urtwn_softc *, 292 struct ieee80211vap *); 293static void urtwn_get_tsf(struct urtwn_softc *, uint64_t *); 294static void urtwn_set_led(struct urtwn_softc *, int, int); 295static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 296static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 297 struct mbuf *, int, 298 const struct ieee80211_rx_stats *, int, int); 299static int urtwn_newstate(struct ieee80211vap *, 300 enum ieee80211_state, int); 301static void urtwn_calib_to(void *); 302static void urtwn_calib_cb(struct urtwn_softc *, 303 union sec_param *); 304static void urtwn_watchdog(void *); 305static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 306static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 307static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 308static int urtwn_tx_data(struct urtwn_softc *, 309 struct ieee80211_node *, struct mbuf *, 310 struct urtwn_data *); 311static int urtwn_tx_raw(struct urtwn_softc *, 312 struct ieee80211_node *, struct mbuf *, 313 struct urtwn_data *, 314 const struct ieee80211_bpf_params *); 315static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 316 uint8_t, struct urtwn_data *); 317static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 318static void urtwn_start(struct urtwn_softc *); 319static void urtwn_parent(struct ieee80211com *); 320static int urtwn_r92c_power_on(struct urtwn_softc *); 321static int urtwn_r88e_power_on(struct urtwn_softc *); 322static void urtwn_r92c_power_off(struct urtwn_softc *); 323static void urtwn_r88e_power_off(struct urtwn_softc *); 324static int urtwn_llt_init(struct urtwn_softc *); 325#ifndef URTWN_WITHOUT_UCODE 326static void urtwn_fw_reset(struct urtwn_softc *); 327static void urtwn_r88e_fw_reset(struct urtwn_softc *); 328static int urtwn_fw_loadpage(struct urtwn_softc *, int, 329 const uint8_t *, int); 330static int urtwn_load_firmware(struct urtwn_softc *); 331#endif 332static int urtwn_dma_init(struct urtwn_softc *); 333static int urtwn_mac_init(struct urtwn_softc *); 334static void urtwn_bb_init(struct urtwn_softc *); 335static void urtwn_rf_init(struct urtwn_softc *); 336static void urtwn_cam_init(struct urtwn_softc *); 337static int urtwn_cam_write(struct urtwn_softc *, uint32_t, 338 uint32_t); 339static void urtwn_pa_bias_init(struct urtwn_softc *); 340static void urtwn_rxfilter_init(struct urtwn_softc *); 341static void urtwn_edca_init(struct urtwn_softc *); 342static void urtwn_write_txpower(struct urtwn_softc *, int, 343 uint16_t[]); 344static void urtwn_get_txpower(struct urtwn_softc *, int, 345 struct ieee80211_channel *, 346 struct ieee80211_channel *, uint16_t[]); 347static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 348 struct ieee80211_channel *, 349 struct ieee80211_channel *, uint16_t[]); 350static void urtwn_set_txpower(struct urtwn_softc *, 351 struct ieee80211_channel *, 352 struct ieee80211_channel *); 353static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 354static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 355static void urtwn_scan_start(struct ieee80211com *); 356static void urtwn_scan_end(struct ieee80211com *); 357static void urtwn_getradiocaps(struct ieee80211com *, int, int *, 358 struct ieee80211_channel[]); 359static void urtwn_set_channel(struct ieee80211com *); 360static int urtwn_wme_update(struct ieee80211com *); 361static void urtwn_update_slot(struct ieee80211com *); 362static void urtwn_update_slot_cb(struct urtwn_softc *, 363 union sec_param *); 364static void urtwn_update_aifs(struct urtwn_softc *, uint8_t); 365static uint8_t urtwn_get_multi_pos(const uint8_t[]); 366static void urtwn_set_multi(struct urtwn_softc *); 367static void urtwn_set_promisc(struct urtwn_softc *); 368static void urtwn_update_promisc(struct ieee80211com *); 369static void urtwn_update_mcast(struct ieee80211com *); 370static struct ieee80211_node *urtwn_node_alloc(struct ieee80211vap *, 371 const uint8_t mac[IEEE80211_ADDR_LEN]); 372static void urtwn_newassoc(struct ieee80211_node *, int); 373static void urtwn_node_free(struct ieee80211_node *); 374static void urtwn_set_chan(struct urtwn_softc *, 375 struct ieee80211_channel *, 376 struct ieee80211_channel *); 377static void urtwn_iq_calib(struct urtwn_softc *); 378static void urtwn_lc_calib(struct urtwn_softc *); 379static void urtwn_temp_calib(struct urtwn_softc *); 380static void urtwn_setup_static_keys(struct urtwn_softc *, 381 struct urtwn_vap *); 382static int urtwn_init(struct urtwn_softc *); 383static void urtwn_stop(struct urtwn_softc *); 384static void urtwn_abort_xfers(struct urtwn_softc *); 385static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 386 const struct ieee80211_bpf_params *); 387static void urtwn_ms_delay(struct urtwn_softc *); 388 389/* Aliases. */ 390#define urtwn_bb_write urtwn_write_4 391#define urtwn_bb_read urtwn_read_4 392 393static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 394 [URTWN_BULK_RX] = { 395 .type = UE_BULK, 396 .endpoint = UE_ADDR_ANY, 397 .direction = UE_DIR_IN, 398 .bufsize = URTWN_RXBUFSZ, 399 .flags = { 400 .pipe_bof = 1, 401 .short_xfer_ok = 1 402 }, 403 .callback = urtwn_bulk_rx_callback, 404 }, 405 [URTWN_BULK_TX_BE] = { 406 .type = UE_BULK, 407 .endpoint = 0x03, 408 .direction = UE_DIR_OUT, 409 .bufsize = URTWN_TXBUFSZ, 410 .flags = { 411 .ext_buffer = 1, 412 .pipe_bof = 1, 413 .force_short_xfer = 1 414 }, 415 .callback = urtwn_bulk_tx_callback, 416 .timeout = URTWN_TX_TIMEOUT, /* ms */ 417 }, 418 [URTWN_BULK_TX_BK] = { 419 .type = UE_BULK, 420 .endpoint = 0x03, 421 .direction = UE_DIR_OUT, 422 .bufsize = URTWN_TXBUFSZ, 423 .flags = { 424 .ext_buffer = 1, 425 .pipe_bof = 1, 426 .force_short_xfer = 1, 427 }, 428 .callback = urtwn_bulk_tx_callback, 429 .timeout = URTWN_TX_TIMEOUT, /* ms */ 430 }, 431 [URTWN_BULK_TX_VI] = { 432 .type = UE_BULK, 433 .endpoint = 0x02, 434 .direction = UE_DIR_OUT, 435 .bufsize = URTWN_TXBUFSZ, 436 .flags = { 437 .ext_buffer = 1, 438 .pipe_bof = 1, 439 .force_short_xfer = 1 440 }, 441 .callback = urtwn_bulk_tx_callback, 442 .timeout = URTWN_TX_TIMEOUT, /* ms */ 443 }, 444 [URTWN_BULK_TX_VO] = { 445 .type = UE_BULK, 446 .endpoint = 0x02, 447 .direction = UE_DIR_OUT, 448 .bufsize = URTWN_TXBUFSZ, 449 .flags = { 450 .ext_buffer = 1, 451 .pipe_bof = 1, 452 .force_short_xfer = 1 453 }, 454 .callback = urtwn_bulk_tx_callback, 455 .timeout = URTWN_TX_TIMEOUT, /* ms */ 456 }, 457}; 458 459static const struct wme_to_queue { 460 uint16_t reg; 461 uint8_t qid; 462} wme2queue[WME_NUM_AC] = { 463 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 464 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 465 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 466 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 467}; 468 469static const uint8_t urtwn_chan_2ghz[] = 470 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 471 472static int 473urtwn_match(device_t self) 474{ 475 struct usb_attach_arg *uaa = device_get_ivars(self); 476 477 if (uaa->usb_mode != USB_MODE_HOST) 478 return (ENXIO); 479 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 480 return (ENXIO); 481 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 482 return (ENXIO); 483 484 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 485} 486 487static void 488urtwn_update_chw(struct ieee80211com *ic) 489{ 490} 491 492static int 493urtwn_ampdu_enable(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 494{ 495 496 /* We're driving this ourselves (eventually); don't involve net80211 */ 497 return (0); 498} 499 500static int 501urtwn_attach(device_t self) 502{ 503 struct usb_attach_arg *uaa = device_get_ivars(self); 504 struct urtwn_softc *sc = device_get_softc(self); 505 struct ieee80211com *ic = &sc->sc_ic; 506 int error; 507 508 device_set_usb_desc(self); 509 sc->sc_udev = uaa->device; 510 sc->sc_dev = self; 511 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 512 sc->chip |= URTWN_CHIP_88E; 513 514#ifdef USB_DEBUG 515 int debug; 516 if (resource_int_value(device_get_name(sc->sc_dev), 517 device_get_unit(sc->sc_dev), "debug", &debug) == 0) 518 sc->sc_debug = debug; 519#endif 520 521 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 522 MTX_NETWORK_LOCK, MTX_DEF); 523 URTWN_CMDQ_LOCK_INIT(sc); 524 URTWN_NT_LOCK_INIT(sc); 525 callout_init(&sc->sc_calib_to, 0); 526 callout_init(&sc->sc_watchdog_ch, 0); 527 mbufq_init(&sc->sc_snd, ifqmaxlen); 528 529 sc->sc_iface_index = URTWN_IFACE_INDEX; 530 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 531 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 532 if (error) { 533 device_printf(self, "could not allocate USB transfers, " 534 "err=%s\n", usbd_errstr(error)); 535 goto detach; 536 } 537 538 URTWN_LOCK(sc); 539 540 error = urtwn_read_chipid(sc); 541 if (error) { 542 device_printf(sc->sc_dev, "unsupported test chip\n"); 543 URTWN_UNLOCK(sc); 544 goto detach; 545 } 546 547 /* Determine number of Tx/Rx chains. */ 548 if (sc->chip & URTWN_CHIP_92C) { 549 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 550 sc->nrxchains = 2; 551 } else { 552 sc->ntxchains = 1; 553 sc->nrxchains = 1; 554 } 555 556 if (sc->chip & URTWN_CHIP_88E) 557 error = urtwn_r88e_read_rom(sc); 558 else 559 error = urtwn_read_rom(sc); 560 if (error != 0) { 561 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 562 __func__, error); 563 URTWN_UNLOCK(sc); 564 goto detach; 565 } 566 567 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 568 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 569 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 570 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 571 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 572 "8188CUS", sc->ntxchains, sc->nrxchains); 573 574 URTWN_UNLOCK(sc); 575 576 ic->ic_softc = sc; 577 ic->ic_name = device_get_nameunit(self); 578 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 579 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 580 581 /* set device capabilities */ 582 ic->ic_caps = 583 IEEE80211_C_STA /* station mode */ 584 | IEEE80211_C_MONITOR /* monitor mode */ 585 | IEEE80211_C_IBSS /* adhoc mode */ 586 | IEEE80211_C_HOSTAP /* hostap mode */ 587 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 588 | IEEE80211_C_SHSLOT /* short slot time supported */ 589#if 0 590 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 591#endif 592 | IEEE80211_C_WPA /* 802.11i */ 593 | IEEE80211_C_WME /* 802.11e */ 594 | IEEE80211_C_SWAMSDUTX /* Do software A-MSDU TX */ 595 | IEEE80211_C_FF /* Atheros fast-frames */ 596 ; 597 598 ic->ic_cryptocaps = 599 IEEE80211_CRYPTO_WEP | 600 IEEE80211_CRYPTO_TKIP | 601 IEEE80211_CRYPTO_AES_CCM; 602 603 /* Assume they're all 11n capable for now */ 604 if (urtwn_enable_11n) { 605 device_printf(self, "enabling 11n\n"); 606 ic->ic_htcaps = IEEE80211_HTC_HT | 607#if 0 608 IEEE80211_HTC_AMPDU | 609#endif 610 IEEE80211_HTC_AMSDU | 611 IEEE80211_HTCAP_MAXAMSDU_3839 | 612 IEEE80211_HTCAP_SMPS_OFF; 613 /* no HT40 just yet */ 614 // ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40; 615 616 /* XXX TODO: verify chains versus streams for urtwn */ 617 ic->ic_txstream = sc->ntxchains; 618 ic->ic_rxstream = sc->nrxchains; 619 } 620 621 /* XXX TODO: setup regdomain if R92C_CHANNEL_PLAN_BY_HW bit is set. */ 622 623 urtwn_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 624 ic->ic_channels); 625 626 ieee80211_ifattach(ic); 627 ic->ic_raw_xmit = urtwn_raw_xmit; 628 ic->ic_scan_start = urtwn_scan_start; 629 ic->ic_scan_end = urtwn_scan_end; 630 ic->ic_getradiocaps = urtwn_getradiocaps; 631 ic->ic_set_channel = urtwn_set_channel; 632 ic->ic_transmit = urtwn_transmit; 633 ic->ic_parent = urtwn_parent; 634 ic->ic_vap_create = urtwn_vap_create; 635 ic->ic_vap_delete = urtwn_vap_delete; 636 ic->ic_wme.wme_update = urtwn_wme_update; 637 ic->ic_updateslot = urtwn_update_slot; 638 ic->ic_update_promisc = urtwn_update_promisc; 639 ic->ic_update_mcast = urtwn_update_mcast; 640 if (sc->chip & URTWN_CHIP_88E) { 641 ic->ic_node_alloc = urtwn_node_alloc; 642 ic->ic_newassoc = urtwn_newassoc; 643 sc->sc_node_free = ic->ic_node_free; 644 ic->ic_node_free = urtwn_node_free; 645 } 646 ic->ic_update_chw = urtwn_update_chw; 647 ic->ic_ampdu_enable = urtwn_ampdu_enable; 648 649 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 650 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 651 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 652 URTWN_RX_RADIOTAP_PRESENT); 653 654 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc); 655 656 urtwn_sysctlattach(sc); 657 658 if (bootverbose) 659 ieee80211_announce(ic); 660 661 return (0); 662 663detach: 664 urtwn_detach(self); 665 return (ENXIO); /* failure */ 666} 667 668static void 669urtwn_sysctlattach(struct urtwn_softc *sc) 670{ 671#ifdef USB_DEBUG 672 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 673 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 674 675 SYSCTL_ADD_U32(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 676 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 677 "control debugging printfs"); 678#endif 679} 680 681static int 682urtwn_detach(device_t self) 683{ 684 struct urtwn_softc *sc = device_get_softc(self); 685 struct ieee80211com *ic = &sc->sc_ic; 686 687 /* Prevent further ioctls. */ 688 URTWN_LOCK(sc); 689 sc->sc_flags |= URTWN_DETACHED; 690 URTWN_UNLOCK(sc); 691 692 urtwn_stop(sc); 693 694 callout_drain(&sc->sc_watchdog_ch); 695 callout_drain(&sc->sc_calib_to); 696 697 /* stop all USB transfers */ 698 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 699 700 if (ic->ic_softc == sc) { 701 ieee80211_draintask(ic, &sc->cmdq_task); 702 ieee80211_ifdetach(ic); 703 } 704 705 URTWN_NT_LOCK_DESTROY(sc); 706 URTWN_CMDQ_LOCK_DESTROY(sc); 707 mtx_destroy(&sc->sc_mtx); 708 709 return (0); 710} 711 712static void 713urtwn_drain_mbufq(struct urtwn_softc *sc) 714{ 715 struct mbuf *m; 716 struct ieee80211_node *ni; 717 URTWN_ASSERT_LOCKED(sc); 718 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 719 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 720 m->m_pkthdr.rcvif = NULL; 721 ieee80211_free_node(ni); 722 m_freem(m); 723 } 724} 725 726static usb_error_t 727urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 728 void *data) 729{ 730 usb_error_t err; 731 int ntries = 10; 732 733 URTWN_ASSERT_LOCKED(sc); 734 735 while (ntries--) { 736 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 737 req, data, 0, NULL, 250 /* ms */); 738 if (err == 0) 739 break; 740 741 URTWN_DPRINTF(sc, URTWN_DEBUG_USB, 742 "%s: control request failed, %s (retries left: %d)\n", 743 __func__, usbd_errstr(err), ntries); 744 usb_pause_mtx(&sc->sc_mtx, hz / 100); 745 } 746 return (err); 747} 748 749static struct ieee80211vap * 750urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 751 enum ieee80211_opmode opmode, int flags, 752 const uint8_t bssid[IEEE80211_ADDR_LEN], 753 const uint8_t mac[IEEE80211_ADDR_LEN]) 754{ 755 struct urtwn_softc *sc = ic->ic_softc; 756 struct urtwn_vap *uvp; 757 struct ieee80211vap *vap; 758 759 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 760 return (NULL); 761 762 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 763 vap = &uvp->vap; 764 /* enable s/w bmiss handling for sta mode */ 765 766 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 767 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 768 /* out of memory */ 769 free(uvp, M_80211_VAP); 770 return (NULL); 771 } 772 773 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 774 urtwn_init_beacon(sc, uvp); 775 776 /* override state transition machine */ 777 uvp->newstate = vap->iv_newstate; 778 vap->iv_newstate = urtwn_newstate; 779 vap->iv_update_beacon = urtwn_update_beacon; 780 vap->iv_key_alloc = urtwn_key_alloc; 781 vap->iv_key_set = urtwn_key_set; 782 vap->iv_key_delete = urtwn_key_delete; 783 784 /* 802.11n parameters */ 785 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_16; 786 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K; 787 788 if (opmode == IEEE80211_M_IBSS) { 789 uvp->recv_mgmt = vap->iv_recv_mgmt; 790 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 791 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 792 } 793 794 if (URTWN_CHIP_HAS_RATECTL(sc)) 795 ieee80211_ratectl_init(vap); 796 /* complete setup */ 797 ieee80211_vap_attach(vap, ieee80211_media_change, 798 ieee80211_media_status, mac); 799 ic->ic_opmode = opmode; 800 return (vap); 801} 802 803static void 804urtwn_vap_delete(struct ieee80211vap *vap) 805{ 806 struct ieee80211com *ic = vap->iv_ic; 807 struct urtwn_softc *sc = ic->ic_softc; 808 struct urtwn_vap *uvp = URTWN_VAP(vap); 809 810 /* Guarantee that nothing will go through this vap. */ 811 ieee80211_new_state(vap, IEEE80211_S_INIT, -1); 812 ieee80211_draintask(ic, &vap->iv_nstate_task); 813 814 URTWN_LOCK(sc); 815 if (uvp->bcn_mbuf != NULL) 816 m_freem(uvp->bcn_mbuf); 817 /* Cancel any unfinished Tx. */ 818 urtwn_vap_clear_tx(sc, vap); 819 URTWN_UNLOCK(sc); 820 if (vap->iv_opmode == IEEE80211_M_IBSS) 821 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 822 if (URTWN_CHIP_HAS_RATECTL(sc)) 823 ieee80211_ratectl_deinit(vap); 824 ieee80211_vap_detach(vap); 825 free(uvp, M_80211_VAP); 826} 827 828static void 829urtwn_vap_clear_tx(struct urtwn_softc *sc, struct ieee80211vap *vap) 830{ 831 832 URTWN_ASSERT_LOCKED(sc); 833 834 urtwn_vap_clear_tx_queue(sc, &sc->sc_tx_active, vap); 835 urtwn_vap_clear_tx_queue(sc, &sc->sc_tx_pending, vap); 836} 837 838static void 839urtwn_vap_clear_tx_queue(struct urtwn_softc *sc, urtwn_datahead *head, 840 struct ieee80211vap *vap) 841{ 842 struct urtwn_data *dp, *tmp; 843 844 STAILQ_FOREACH_SAFE(dp, head, next, tmp) { 845 if (dp->ni != NULL) { 846 if (dp->ni->ni_vap == vap) { 847 ieee80211_free_node(dp->ni); 848 dp->ni = NULL; 849 850 if (dp->m != NULL) { 851 m_freem(dp->m); 852 dp->m = NULL; 853 } 854 855 STAILQ_REMOVE(head, dp, urtwn_data, next); 856 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, dp, 857 next); 858 } 859 } 860 } 861} 862 863static struct mbuf * 864urtwn_rx_copy_to_mbuf(struct urtwn_softc *sc, struct r92c_rx_stat *stat, 865 int totlen) 866{ 867 struct ieee80211com *ic = &sc->sc_ic; 868 struct mbuf *m; 869 uint32_t rxdw0; 870 int pktlen; 871 872 /* 873 * don't pass packets to the ieee80211 framework if the driver isn't 874 * RUNNING. 875 */ 876 if (!(sc->sc_flags & URTWN_RUNNING)) 877 return (NULL); 878 879 rxdw0 = le32toh(stat->rxdw0); 880 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 881 /* 882 * This should not happen since we setup our Rx filter 883 * to not receive these frames. 884 */ 885 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 886 "%s: RX flags error (%s)\n", __func__, 887 rxdw0 & R92C_RXDW0_CRCERR ? "CRC" : "ICV"); 888 goto fail; 889 } 890 891 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 892 if (pktlen < sizeof(struct ieee80211_frame_ack)) { 893 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 894 "%s: frame is too short: %d\n", __func__, pktlen); 895 goto fail; 896 } 897 898 if (__predict_false(totlen > MCLBYTES)) { 899 /* convert to m_getjcl if this happens */ 900 device_printf(sc->sc_dev, "%s: frame too long: %d (%d)\n", 901 __func__, pktlen, totlen); 902 goto fail; 903 } 904 905 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 906 if (__predict_false(m == NULL)) { 907 device_printf(sc->sc_dev, "%s: could not allocate RX mbuf\n", 908 __func__); 909 goto fail; 910 } 911 912 /* Finalize mbuf. */ 913 memcpy(mtod(m, uint8_t *), (uint8_t *)stat, totlen); 914 m->m_pkthdr.len = m->m_len = totlen; 915 916 return (m); 917fail: 918 counter_u64_add(ic->ic_ierrors, 1); 919 return (NULL); 920} 921 922static struct mbuf * 923urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data) 924{ 925 struct urtwn_softc *sc = data->sc; 926 struct ieee80211com *ic = &sc->sc_ic; 927 struct r92c_rx_stat *stat; 928 uint8_t *buf; 929 int len; 930 931 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 932 933 if (len < sizeof(*stat)) { 934 counter_u64_add(ic->ic_ierrors, 1); 935 return (NULL); 936 } 937 938 buf = data->buf; 939 stat = (struct r92c_rx_stat *)buf; 940 941 /* 942 * For 88E chips we can tie the FF flushing here; 943 * this is where we do know exactly how deep the 944 * transmit queue is. 945 * 946 * But it won't work for R92 chips, so we can't 947 * take the easy way out. 948 */ 949 950 if (sc->chip & URTWN_CHIP_88E) { 951 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 952 953 switch (report_sel) { 954 case R88E_RXDW3_RPT_RX: 955 return (urtwn_rxeof(sc, buf, len)); 956 case R88E_RXDW3_RPT_TX1: 957 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 958 break; 959 default: 960 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, 961 "%s: case %d was not handled\n", __func__, 962 report_sel); 963 break; 964 } 965 } else 966 return (urtwn_rxeof(sc, buf, len)); 967 968 return (NULL); 969} 970 971static struct mbuf * 972urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len) 973{ 974 struct r92c_rx_stat *stat; 975 struct mbuf *m, *m0 = NULL, *prevm = NULL; 976 uint32_t rxdw0; 977 int totlen, pktlen, infosz, npkts; 978 979 /* Get the number of encapsulated frames. */ 980 stat = (struct r92c_rx_stat *)buf; 981 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 982 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 983 "%s: Rx %d frames in one chunk\n", __func__, npkts); 984 985 /* Process all of them. */ 986 while (npkts-- > 0) { 987 if (len < sizeof(*stat)) 988 break; 989 stat = (struct r92c_rx_stat *)buf; 990 rxdw0 = le32toh(stat->rxdw0); 991 992 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 993 if (pktlen == 0) 994 break; 995 996 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 997 998 /* Make sure everything fits in xfer. */ 999 totlen = sizeof(*stat) + infosz + pktlen; 1000 if (totlen > len) 1001 break; 1002 1003 m = urtwn_rx_copy_to_mbuf(sc, stat, totlen); 1004 if (m0 == NULL) 1005 m0 = m; 1006 if (prevm == NULL) 1007 prevm = m; 1008 else { 1009 prevm->m_next = m; 1010 prevm = m; 1011 } 1012 1013 /* Next chunk is 128-byte aligned. */ 1014 totlen = (totlen + 127) & ~127; 1015 buf += totlen; 1016 len -= totlen; 1017 } 1018 1019 return (m0); 1020} 1021 1022static void 1023urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 1024{ 1025 struct r88e_tx_rpt_ccx *rpt = arg; 1026 struct ieee80211vap *vap; 1027 struct ieee80211_node *ni; 1028 uint8_t macid; 1029 int ntries; 1030 1031 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 1032 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 1033 1034 URTWN_NT_LOCK(sc); 1035 ni = sc->node_list[macid]; 1036 if (ni != NULL) { 1037 vap = ni->ni_vap; 1038 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: frame for macid %d was" 1039 "%s sent (%d retries)\n", __func__, macid, 1040 (rpt->rptb1 & R88E_RPTB1_PKT_OK) ? "" : " not", 1041 ntries); 1042 1043 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 1044 ieee80211_ratectl_tx_complete(vap, ni, 1045 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 1046 } else { 1047 ieee80211_ratectl_tx_complete(vap, ni, 1048 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 1049 } 1050 } else { 1051 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: macid %d, ni is NULL\n", 1052 __func__, macid); 1053 } 1054 URTWN_NT_UNLOCK(sc); 1055} 1056 1057static struct ieee80211_node * 1058urtwn_rx_frame(struct urtwn_softc *sc, struct mbuf *m, int8_t *rssi_p) 1059{ 1060 struct ieee80211com *ic = &sc->sc_ic; 1061 struct ieee80211_frame_min *wh; 1062 struct r92c_rx_stat *stat; 1063 uint32_t rxdw0, rxdw3; 1064 uint8_t rate, cipher; 1065 int8_t rssi = -127; 1066 int infosz; 1067 1068 stat = mtod(m, struct r92c_rx_stat *); 1069 rxdw0 = le32toh(stat->rxdw0); 1070 rxdw3 = le32toh(stat->rxdw3); 1071 1072 rate = MS(rxdw3, R92C_RXDW3_RATE); 1073 cipher = MS(rxdw0, R92C_RXDW0_CIPHER); 1074 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1075 1076 /* Get RSSI from PHY status descriptor if present. */ 1077 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1078 if (sc->chip & URTWN_CHIP_88E) 1079 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 1080 else 1081 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 1082 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: rssi=%d\n", __func__, rssi); 1083 /* Update our average RSSI. */ 1084 urtwn_update_avgrssi(sc, rate, rssi); 1085 } 1086 1087 if (ieee80211_radiotap_active(ic)) { 1088 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1089 1090 tap->wr_flags = 0; 1091 1092 urtwn_get_tsf(sc, &tap->wr_tsft); 1093 if (__predict_false(le32toh((uint32_t)tap->wr_tsft) < 1094 le32toh(stat->rxdw5))) { 1095 tap->wr_tsft = le32toh(tap->wr_tsft >> 32) - 1; 1096 tap->wr_tsft = (uint64_t)htole32(tap->wr_tsft) << 32; 1097 } else 1098 tap->wr_tsft &= 0xffffffff00000000; 1099 tap->wr_tsft += stat->rxdw5; 1100 1101 /* XXX 20/40? */ 1102 /* XXX shortgi? */ 1103 1104 /* Map HW rate index to 802.11 rate. */ 1105 if (!(rxdw3 & R92C_RXDW3_HT)) { 1106 tap->wr_rate = ridx2rate[rate]; 1107 } else if (rate >= 12) { /* MCS0~15. */ 1108 /* Bit 7 set means HT MCS instead of rate. */ 1109 tap->wr_rate = 0x80 | (rate - 12); 1110 } 1111 1112 /* XXX TODO: this isn't right; should use the last good RSSI */ 1113 tap->wr_dbm_antsignal = rssi; 1114 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 1115 } 1116 1117 *rssi_p = rssi; 1118 1119 /* Drop descriptor. */ 1120 m_adj(m, sizeof(*stat) + infosz); 1121 wh = mtod(m, struct ieee80211_frame_min *); 1122 1123 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1124 cipher != R92C_CAM_ALGO_NONE) { 1125 m->m_flags |= M_WEP; 1126 } 1127 1128 if (m->m_len >= sizeof(*wh)) 1129 return (ieee80211_find_rxnode(ic, wh)); 1130 1131 return (NULL); 1132} 1133 1134static void 1135urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 1136{ 1137 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1138 struct ieee80211com *ic = &sc->sc_ic; 1139 struct ieee80211_node *ni; 1140 struct mbuf *m = NULL, *next; 1141 struct urtwn_data *data; 1142 int8_t nf, rssi; 1143 1144 URTWN_ASSERT_LOCKED(sc); 1145 1146 switch (USB_GET_STATE(xfer)) { 1147 case USB_ST_TRANSFERRED: 1148 data = STAILQ_FIRST(&sc->sc_rx_active); 1149 if (data == NULL) 1150 goto tr_setup; 1151 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1152 m = urtwn_report_intr(xfer, data); 1153 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1154 /* FALLTHROUGH */ 1155 case USB_ST_SETUP: 1156tr_setup: 1157 data = STAILQ_FIRST(&sc->sc_rx_inactive); 1158 if (data == NULL) { 1159 KASSERT(m == NULL, ("mbuf isn't NULL")); 1160 goto finish; 1161 } 1162 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 1163 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 1164 usbd_xfer_set_frame_data(xfer, 0, data->buf, 1165 usbd_xfer_max_len(xfer)); 1166 usbd_transfer_submit(xfer); 1167 1168 /* 1169 * To avoid LOR we should unlock our private mutex here to call 1170 * ieee80211_input() because here is at the end of a USB 1171 * callback and safe to unlock. 1172 */ 1173 while (m != NULL) { 1174 next = m->m_next; 1175 m->m_next = NULL; 1176 1177 ni = urtwn_rx_frame(sc, m, &rssi); 1178 1179 /* Store a global last-good RSSI */ 1180 if (rssi != -127) 1181 sc->last_rssi = rssi; 1182 1183 URTWN_UNLOCK(sc); 1184 1185 nf = URTWN_NOISE_FLOOR; 1186 if (ni != NULL) { 1187 if (rssi != -127) 1188 URTWN_NODE(ni)->last_rssi = rssi; 1189 if (ni->ni_flags & IEEE80211_NODE_HT) 1190 m->m_flags |= M_AMPDU; 1191 (void)ieee80211_input(ni, m, 1192 URTWN_NODE(ni)->last_rssi - nf, nf); 1193 ieee80211_free_node(ni); 1194 } else { 1195 /* Use last good global RSSI */ 1196 (void)ieee80211_input_all(ic, m, 1197 sc->last_rssi - nf, nf); 1198 } 1199 URTWN_LOCK(sc); 1200 m = next; 1201 } 1202 break; 1203 default: 1204 /* needs it to the inactive queue due to a error. */ 1205 data = STAILQ_FIRST(&sc->sc_rx_active); 1206 if (data != NULL) { 1207 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1208 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1209 } 1210 if (error != USB_ERR_CANCELLED) { 1211 usbd_xfer_set_stall(xfer); 1212 counter_u64_add(ic->ic_ierrors, 1); 1213 goto tr_setup; 1214 } 1215 break; 1216 } 1217finish: 1218 /* Finished receive; age anything left on the FF queue by a little bump */ 1219 /* 1220 * XXX TODO: just make this a callout timer schedule so we can 1221 * flush the FF staging queue if we're approaching idle. 1222 */ 1223#ifdef IEEE80211_SUPPORT_SUPERG 1224 URTWN_UNLOCK(sc); 1225 ieee80211_ff_age_all(ic, 1); 1226 URTWN_LOCK(sc); 1227#endif 1228 1229 /* Kick-start more transmit in case we stalled */ 1230 urtwn_start(sc); 1231} 1232 1233static void 1234urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 1235{ 1236 1237 URTWN_ASSERT_LOCKED(sc); 1238 1239 if (data->ni != NULL) /* not a beacon frame */ 1240 ieee80211_tx_complete(data->ni, data->m, status); 1241 1242 if (sc->sc_tx_n_active > 0) 1243 sc->sc_tx_n_active--; 1244 1245 data->ni = NULL; 1246 data->m = NULL; 1247 1248 sc->sc_txtimer = 0; 1249 1250 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 1251} 1252 1253static int 1254urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1255 int ndata, int maxsz) 1256{ 1257 int i, error; 1258 1259 for (i = 0; i < ndata; i++) { 1260 struct urtwn_data *dp = &data[i]; 1261 dp->sc = sc; 1262 dp->m = NULL; 1263 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1264 if (dp->buf == NULL) { 1265 device_printf(sc->sc_dev, 1266 "could not allocate buffer\n"); 1267 error = ENOMEM; 1268 goto fail; 1269 } 1270 dp->ni = NULL; 1271 } 1272 1273 return (0); 1274fail: 1275 urtwn_free_list(sc, data, ndata); 1276 return (error); 1277} 1278 1279static int 1280urtwn_alloc_rx_list(struct urtwn_softc *sc) 1281{ 1282 int error, i; 1283 1284 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1285 URTWN_RXBUFSZ); 1286 if (error != 0) 1287 return (error); 1288 1289 STAILQ_INIT(&sc->sc_rx_active); 1290 STAILQ_INIT(&sc->sc_rx_inactive); 1291 1292 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1293 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1294 1295 return (0); 1296} 1297 1298static int 1299urtwn_alloc_tx_list(struct urtwn_softc *sc) 1300{ 1301 int error, i; 1302 1303 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1304 URTWN_TXBUFSZ); 1305 if (error != 0) 1306 return (error); 1307 1308 STAILQ_INIT(&sc->sc_tx_active); 1309 STAILQ_INIT(&sc->sc_tx_inactive); 1310 STAILQ_INIT(&sc->sc_tx_pending); 1311 1312 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1313 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1314 1315 return (0); 1316} 1317 1318static void 1319urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1320{ 1321 int i; 1322 1323 for (i = 0; i < ndata; i++) { 1324 struct urtwn_data *dp = &data[i]; 1325 1326 if (dp->buf != NULL) { 1327 free(dp->buf, M_USBDEV); 1328 dp->buf = NULL; 1329 } 1330 if (dp->ni != NULL) { 1331 ieee80211_free_node(dp->ni); 1332 dp->ni = NULL; 1333 } 1334 } 1335} 1336 1337static void 1338urtwn_free_rx_list(struct urtwn_softc *sc) 1339{ 1340 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1341 1342 STAILQ_INIT(&sc->sc_rx_active); 1343 STAILQ_INIT(&sc->sc_rx_inactive); 1344} 1345 1346static void 1347urtwn_free_tx_list(struct urtwn_softc *sc) 1348{ 1349 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1350 1351 STAILQ_INIT(&sc->sc_tx_active); 1352 STAILQ_INIT(&sc->sc_tx_inactive); 1353 STAILQ_INIT(&sc->sc_tx_pending); 1354} 1355 1356static void 1357urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1358{ 1359 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1360#ifdef IEEE80211_SUPPORT_SUPERG 1361 struct ieee80211com *ic = &sc->sc_ic; 1362#endif 1363 struct urtwn_data *data; 1364 1365 URTWN_ASSERT_LOCKED(sc); 1366 1367 switch (USB_GET_STATE(xfer)){ 1368 case USB_ST_TRANSFERRED: 1369 data = STAILQ_FIRST(&sc->sc_tx_active); 1370 if (data == NULL) 1371 goto tr_setup; 1372 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1373 urtwn_txeof(sc, data, 0); 1374 /* FALLTHROUGH */ 1375 case USB_ST_SETUP: 1376tr_setup: 1377 data = STAILQ_FIRST(&sc->sc_tx_pending); 1378 if (data == NULL) { 1379 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1380 "%s: empty pending queue\n", __func__); 1381 sc->sc_tx_n_active = 0; 1382 goto finish; 1383 } 1384 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1385 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1386 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1387 usbd_transfer_submit(xfer); 1388 sc->sc_tx_n_active++; 1389 break; 1390 default: 1391 data = STAILQ_FIRST(&sc->sc_tx_active); 1392 if (data == NULL) 1393 goto tr_setup; 1394 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1395 urtwn_txeof(sc, data, 1); 1396 if (error != USB_ERR_CANCELLED) { 1397 usbd_xfer_set_stall(xfer); 1398 goto tr_setup; 1399 } 1400 break; 1401 } 1402finish: 1403#ifdef IEEE80211_SUPPORT_SUPERG 1404 /* 1405 * If the TX active queue drops below a certain 1406 * threshold, ensure we age fast-frames out so they're 1407 * transmitted. 1408 */ 1409 if (sc->sc_tx_n_active <= 1) { 1410 /* XXX ew - net80211 should defer this for us! */ 1411 1412 /* 1413 * Note: this sc_tx_n_active currently tracks 1414 * the number of pending transmit submissions 1415 * and not the actual depth of the TX frames 1416 * pending to the hardware. That means that 1417 * we're going to end up with some sub-optimal 1418 * aggregation behaviour. 1419 */ 1420 /* 1421 * XXX TODO: just make this a callout timer schedule so we can 1422 * flush the FF staging queue if we're approaching idle. 1423 */ 1424 URTWN_UNLOCK(sc); 1425 ieee80211_ff_flush(ic, WME_AC_VO); 1426 ieee80211_ff_flush(ic, WME_AC_VI); 1427 ieee80211_ff_flush(ic, WME_AC_BE); 1428 ieee80211_ff_flush(ic, WME_AC_BK); 1429 URTWN_LOCK(sc); 1430 } 1431#endif 1432 /* Kick-start more transmit */ 1433 urtwn_start(sc); 1434} 1435 1436static struct urtwn_data * 1437_urtwn_getbuf(struct urtwn_softc *sc) 1438{ 1439 struct urtwn_data *bf; 1440 1441 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1442 if (bf != NULL) 1443 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1444 else { 1445 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1446 "%s: out of xmit buffers\n", __func__); 1447 } 1448 return (bf); 1449} 1450 1451static struct urtwn_data * 1452urtwn_getbuf(struct urtwn_softc *sc) 1453{ 1454 struct urtwn_data *bf; 1455 1456 URTWN_ASSERT_LOCKED(sc); 1457 1458 bf = _urtwn_getbuf(sc); 1459 if (bf == NULL) { 1460 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: stop queue\n", 1461 __func__); 1462 } 1463 return (bf); 1464} 1465 1466static usb_error_t 1467urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1468 int len) 1469{ 1470 usb_device_request_t req; 1471 1472 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1473 req.bRequest = R92C_REQ_REGS; 1474 USETW(req.wValue, addr); 1475 USETW(req.wIndex, 0); 1476 USETW(req.wLength, len); 1477 return (urtwn_do_request(sc, &req, buf)); 1478} 1479 1480static usb_error_t 1481urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1482{ 1483 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1484} 1485 1486static usb_error_t 1487urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1488{ 1489 val = htole16(val); 1490 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1491} 1492 1493static usb_error_t 1494urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1495{ 1496 val = htole32(val); 1497 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1498} 1499 1500static usb_error_t 1501urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1502 int len) 1503{ 1504 usb_device_request_t req; 1505 1506 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1507 req.bRequest = R92C_REQ_REGS; 1508 USETW(req.wValue, addr); 1509 USETW(req.wIndex, 0); 1510 USETW(req.wLength, len); 1511 return (urtwn_do_request(sc, &req, buf)); 1512} 1513 1514static uint8_t 1515urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1516{ 1517 uint8_t val; 1518 1519 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1520 return (0xff); 1521 return (val); 1522} 1523 1524static uint16_t 1525urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1526{ 1527 uint16_t val; 1528 1529 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1530 return (0xffff); 1531 return (le16toh(val)); 1532} 1533 1534static uint32_t 1535urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1536{ 1537 uint32_t val; 1538 1539 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1540 return (0xffffffff); 1541 return (le32toh(val)); 1542} 1543 1544static int 1545urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1546{ 1547 struct r92c_fw_cmd cmd; 1548 usb_error_t error; 1549 int ntries; 1550 1551 if (!(sc->sc_flags & URTWN_FW_LOADED)) { 1552 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, "%s: firmware " 1553 "was not loaded; command (id %d) will be discarded\n", 1554 __func__, id); 1555 return (0); 1556 } 1557 1558 /* Wait for current FW box to be empty. */ 1559 for (ntries = 0; ntries < 100; ntries++) { 1560 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1561 break; 1562 urtwn_ms_delay(sc); 1563 } 1564 if (ntries == 100) { 1565 device_printf(sc->sc_dev, 1566 "could not send firmware command\n"); 1567 return (ETIMEDOUT); 1568 } 1569 memset(&cmd, 0, sizeof(cmd)); 1570 cmd.id = id; 1571 if (len > 3) 1572 cmd.id |= R92C_CMD_FLAG_EXT; 1573 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1574 memcpy(cmd.msg, buf, len); 1575 1576 /* Write the first word last since that will trigger the FW. */ 1577 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1578 (uint8_t *)&cmd + 4, 2); 1579 if (error != USB_ERR_NORMAL_COMPLETION) 1580 return (EIO); 1581 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1582 (uint8_t *)&cmd + 0, 4); 1583 if (error != USB_ERR_NORMAL_COMPLETION) 1584 return (EIO); 1585 1586 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1587 return (0); 1588} 1589 1590static void 1591urtwn_cmdq_cb(void *arg, int pending) 1592{ 1593 struct urtwn_softc *sc = arg; 1594 struct urtwn_cmdq *item; 1595 1596 /* 1597 * Device must be powered on (via urtwn_power_on()) 1598 * before any command may be sent. 1599 */ 1600 URTWN_LOCK(sc); 1601 if (!(sc->sc_flags & URTWN_RUNNING)) { 1602 URTWN_UNLOCK(sc); 1603 return; 1604 } 1605 1606 URTWN_CMDQ_LOCK(sc); 1607 while (sc->cmdq[sc->cmdq_first].func != NULL) { 1608 item = &sc->cmdq[sc->cmdq_first]; 1609 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE; 1610 URTWN_CMDQ_UNLOCK(sc); 1611 1612 item->func(sc, &item->data); 1613 1614 URTWN_CMDQ_LOCK(sc); 1615 memset(item, 0, sizeof (*item)); 1616 } 1617 URTWN_CMDQ_UNLOCK(sc); 1618 URTWN_UNLOCK(sc); 1619} 1620 1621static int 1622urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len, 1623 CMD_FUNC_PROTO) 1624{ 1625 struct ieee80211com *ic = &sc->sc_ic; 1626 1627 KASSERT(len <= sizeof(union sec_param), ("buffer overflow")); 1628 1629 URTWN_CMDQ_LOCK(sc); 1630 if (sc->cmdq[sc->cmdq_last].func != NULL) { 1631 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__); 1632 URTWN_CMDQ_UNLOCK(sc); 1633 1634 return (EAGAIN); 1635 } 1636 1637 if (ptr != NULL) 1638 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len); 1639 sc->cmdq[sc->cmdq_last].func = func; 1640 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE; 1641 URTWN_CMDQ_UNLOCK(sc); 1642 1643 ieee80211_runtask(ic, &sc->cmdq_task); 1644 1645 return (0); 1646} 1647 1648static __inline void 1649urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1650{ 1651 1652 sc->sc_rf_write(sc, chain, addr, val); 1653} 1654 1655static void 1656urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1657 uint32_t val) 1658{ 1659 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1660 SM(R92C_LSSI_PARAM_ADDR, addr) | 1661 SM(R92C_LSSI_PARAM_DATA, val)); 1662} 1663 1664static void 1665urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1666uint32_t val) 1667{ 1668 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1669 SM(R88E_LSSI_PARAM_ADDR, addr) | 1670 SM(R92C_LSSI_PARAM_DATA, val)); 1671} 1672 1673static uint32_t 1674urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1675{ 1676 uint32_t reg[R92C_MAX_CHAINS], val; 1677 1678 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1679 if (chain != 0) 1680 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1681 1682 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1683 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1684 urtwn_ms_delay(sc); 1685 1686 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1687 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1688 R92C_HSSI_PARAM2_READ_EDGE); 1689 urtwn_ms_delay(sc); 1690 1691 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1692 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1693 urtwn_ms_delay(sc); 1694 1695 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1696 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1697 else 1698 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1699 return (MS(val, R92C_LSSI_READBACK_DATA)); 1700} 1701 1702static int 1703urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1704{ 1705 usb_error_t error; 1706 int ntries; 1707 1708 error = urtwn_write_4(sc, R92C_LLT_INIT, 1709 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1710 SM(R92C_LLT_INIT_ADDR, addr) | 1711 SM(R92C_LLT_INIT_DATA, data)); 1712 if (error != USB_ERR_NORMAL_COMPLETION) 1713 return (EIO); 1714 /* Wait for write operation to complete. */ 1715 for (ntries = 0; ntries < 20; ntries++) { 1716 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1717 R92C_LLT_INIT_OP_NO_ACTIVE) 1718 return (0); 1719 urtwn_ms_delay(sc); 1720 } 1721 return (ETIMEDOUT); 1722} 1723 1724static int 1725urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1726{ 1727 uint32_t reg; 1728 usb_error_t error; 1729 int ntries; 1730 1731 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1732 return (EFAULT); 1733 1734 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1735 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1736 reg &= ~R92C_EFUSE_CTRL_VALID; 1737 1738 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1739 if (error != USB_ERR_NORMAL_COMPLETION) 1740 return (EIO); 1741 /* Wait for read operation to complete. */ 1742 for (ntries = 0; ntries < 100; ntries++) { 1743 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1744 if (reg & R92C_EFUSE_CTRL_VALID) 1745 break; 1746 urtwn_ms_delay(sc); 1747 } 1748 if (ntries == 100) { 1749 device_printf(sc->sc_dev, 1750 "could not read efuse byte at address 0x%x\n", 1751 sc->last_rom_addr); 1752 return (ETIMEDOUT); 1753 } 1754 1755 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1756 sc->last_rom_addr++; 1757 1758 return (0); 1759} 1760 1761static int 1762urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1763 uint8_t msk) 1764{ 1765 uint8_t reg; 1766 int i, error; 1767 1768 for (i = 0; i < 4; i++) { 1769 if (msk & (1 << i)) 1770 continue; 1771 error = urtwn_efuse_read_next(sc, ®); 1772 if (error != 0) 1773 return (error); 1774 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1775 off * 8 + i * 2, reg); 1776 rom[off * 8 + i * 2 + 0] = reg; 1777 1778 error = urtwn_efuse_read_next(sc, ®); 1779 if (error != 0) 1780 return (error); 1781 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1782 off * 8 + i * 2 + 1, reg); 1783 rom[off * 8 + i * 2 + 1] = reg; 1784 } 1785 1786 return (0); 1787} 1788 1789#ifdef USB_DEBUG 1790static void 1791urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1792{ 1793 int i; 1794 1795 /* Dump ROM contents. */ 1796 device_printf(sc->sc_dev, "%s:", __func__); 1797 for (i = 0; i < size; i++) { 1798 if (i % 32 == 0) 1799 printf("\n%03X: ", i); 1800 else if (i % 4 == 0) 1801 printf(" "); 1802 1803 printf("%02X", rom[i]); 1804 } 1805 printf("\n"); 1806} 1807#endif 1808 1809static int 1810urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1811{ 1812#define URTWN_CHK(res) do { \ 1813 if ((error = res) != 0) \ 1814 goto end; \ 1815} while(0) 1816 uint8_t msk, off, reg; 1817 int error; 1818 1819 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1820 1821 /* Read full ROM image. */ 1822 sc->last_rom_addr = 0; 1823 memset(rom, 0xff, size); 1824 1825 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1826 while (reg != 0xff) { 1827 /* check for extended header */ 1828 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1829 off = reg >> 5; 1830 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1831 1832 if ((reg & 0x0f) != 0x0f) 1833 off = ((reg & 0xf0) >> 1) | off; 1834 else 1835 continue; 1836 } else 1837 off = reg >> 4; 1838 msk = reg & 0xf; 1839 1840 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1841 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1842 } 1843 1844end: 1845 1846#ifdef USB_DEBUG 1847 if (sc->sc_debug & URTWN_DEBUG_ROM) 1848 urtwn_dump_rom_contents(sc, rom, size); 1849#endif 1850 1851 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1852 1853 if (error != 0) { 1854 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1855 __func__); 1856 } 1857 1858 return (error); 1859#undef URTWN_CHK 1860} 1861 1862static int 1863urtwn_efuse_switch_power(struct urtwn_softc *sc) 1864{ 1865 usb_error_t error; 1866 uint32_t reg; 1867 1868 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1869 if (error != USB_ERR_NORMAL_COMPLETION) 1870 return (EIO); 1871 1872 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1873 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1874 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1875 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1876 if (error != USB_ERR_NORMAL_COMPLETION) 1877 return (EIO); 1878 } 1879 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1880 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1881 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1882 reg | R92C_SYS_FUNC_EN_ELDR); 1883 if (error != USB_ERR_NORMAL_COMPLETION) 1884 return (EIO); 1885 } 1886 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1887 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1888 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1889 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1890 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1891 if (error != USB_ERR_NORMAL_COMPLETION) 1892 return (EIO); 1893 } 1894 1895 return (0); 1896} 1897 1898static int 1899urtwn_read_chipid(struct urtwn_softc *sc) 1900{ 1901 uint32_t reg; 1902 1903 if (sc->chip & URTWN_CHIP_88E) 1904 return (0); 1905 1906 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1907 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1908 return (EIO); 1909 1910 if (reg & R92C_SYS_CFG_TYPE_92C) { 1911 sc->chip |= URTWN_CHIP_92C; 1912 /* Check if it is a castrated 8192C. */ 1913 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1914 R92C_HPON_FSM_CHIP_BONDING_ID) == 1915 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1916 sc->chip |= URTWN_CHIP_92C_1T2R; 1917 } 1918 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1919 sc->chip |= URTWN_CHIP_UMC; 1920 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1921 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1922 } 1923 return (0); 1924} 1925 1926static int 1927urtwn_read_rom(struct urtwn_softc *sc) 1928{ 1929 struct r92c_rom *rom = &sc->rom.r92c_rom; 1930 int error; 1931 1932 /* Read full ROM image. */ 1933 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1934 if (error != 0) 1935 return (error); 1936 1937 /* XXX Weird but this is what the vendor driver does. */ 1938 sc->last_rom_addr = 0x1fa; 1939 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1940 if (error != 0) 1941 return (error); 1942 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: PA setting=0x%x\n", __func__, 1943 sc->pa_setting); 1944 1945 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1946 1947 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1948 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type=%d\n", 1949 __func__, sc->regulatory); 1950 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1951 1952 sc->sc_rf_write = urtwn_r92c_rf_write; 1953 sc->sc_power_on = urtwn_r92c_power_on; 1954 sc->sc_power_off = urtwn_r92c_power_off; 1955 1956 return (0); 1957} 1958 1959static int 1960urtwn_r88e_read_rom(struct urtwn_softc *sc) 1961{ 1962 struct r88e_rom *rom = &sc->rom.r88e_rom; 1963 int error; 1964 1965 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(sc->rom.r88e_rom)); 1966 if (error != 0) 1967 return (error); 1968 1969 sc->bw20_tx_pwr_diff = (rom->tx_pwr_diff >> 4); 1970 if (sc->bw20_tx_pwr_diff & 0x08) 1971 sc->bw20_tx_pwr_diff |= 0xf0; 1972 sc->ofdm_tx_pwr_diff = (rom->tx_pwr_diff & 0xf); 1973 if (sc->ofdm_tx_pwr_diff & 0x08) 1974 sc->ofdm_tx_pwr_diff |= 0xf0; 1975 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 1976 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type %d\n", 1977 __func__,sc->regulatory); 1978 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1979 1980 sc->sc_rf_write = urtwn_r88e_rf_write; 1981 sc->sc_power_on = urtwn_r88e_power_on; 1982 sc->sc_power_off = urtwn_r88e_power_off; 1983 1984 return (0); 1985} 1986 1987static __inline uint8_t 1988rate2ridx(uint8_t rate) 1989{ 1990 if (rate & IEEE80211_RATE_MCS) { 1991 /* 11n rates start at idx 12 */ 1992 return ((rate & 0xf) + 12); 1993 } 1994 switch (rate) { 1995 /* 11g */ 1996 case 12: return 4; 1997 case 18: return 5; 1998 case 24: return 6; 1999 case 36: return 7; 2000 case 48: return 8; 2001 case 72: return 9; 2002 case 96: return 10; 2003 case 108: return 11; 2004 /* 11b */ 2005 case 2: return 0; 2006 case 4: return 1; 2007 case 11: return 2; 2008 case 22: return 3; 2009 default: return URTWN_RIDX_UNKNOWN; 2010 } 2011} 2012 2013/* 2014 * Initialize rate adaptation in firmware. 2015 */ 2016static int 2017urtwn_ra_init(struct urtwn_softc *sc) 2018{ 2019 struct ieee80211com *ic = &sc->sc_ic; 2020 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2021 struct ieee80211_node *ni; 2022 struct ieee80211_rateset *rs, *rs_ht; 2023 struct r92c_fw_cmd_macid_cfg cmd; 2024 uint32_t rates, basicrates; 2025 uint8_t mode, ridx; 2026 int maxrate, maxbasicrate, error, i; 2027 2028 ni = ieee80211_ref_node(vap->iv_bss); 2029 rs = &ni->ni_rates; 2030 rs_ht = (struct ieee80211_rateset *) &ni->ni_htrates; 2031 2032 /* Get normal and basic rates mask. */ 2033 rates = basicrates = 0; 2034 maxrate = maxbasicrate = 0; 2035 2036 /* This is for 11bg */ 2037 for (i = 0; i < rs->rs_nrates; i++) { 2038 /* Convert 802.11 rate to HW rate index. */ 2039 ridx = rate2ridx(IEEE80211_RV(rs->rs_rates[i])); 2040 if (ridx == URTWN_RIDX_UNKNOWN) /* Unknown rate, skip. */ 2041 continue; 2042 rates |= 1 << ridx; 2043 if (ridx > maxrate) 2044 maxrate = ridx; 2045 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 2046 basicrates |= 1 << ridx; 2047 if (ridx > maxbasicrate) 2048 maxbasicrate = ridx; 2049 } 2050 } 2051 2052 /* If we're doing 11n, enable 11n rates */ 2053 if (ni->ni_flags & IEEE80211_NODE_HT) { 2054 for (i = 0; i < rs_ht->rs_nrates; i++) { 2055 if ((rs_ht->rs_rates[i] & 0x7f) > 0xf) 2056 continue; 2057 /* 11n rates start at index 12 */ 2058 ridx = ((rs_ht->rs_rates[i]) & 0xf) + 12; 2059 rates |= (1 << ridx); 2060 2061 /* Guard against the rate table being oddly ordered */ 2062 if (ridx > maxrate) 2063 maxrate = ridx; 2064 } 2065 } 2066 2067#if 0 2068 if (ic->ic_curmode == IEEE80211_MODE_11NG) 2069 raid = R92C_RAID_11GN; 2070#endif 2071 /* NB: group addressed frames are done at 11bg rates for now */ 2072 if (ic->ic_curmode == IEEE80211_MODE_11B) 2073 mode = R92C_RAID_11B; 2074 else 2075 mode = R92C_RAID_11BG; 2076 /* XXX misleading 'mode' value here for unicast frames */ 2077 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, 2078 "%s: mode 0x%x, rates 0x%08x, basicrates 0x%08x\n", __func__, 2079 mode, rates, basicrates); 2080 2081 /* Set rates mask for group addressed frames. */ 2082 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 2083 cmd.mask = htole32(mode << 28 | basicrates); 2084 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 2085 if (error != 0) { 2086 ieee80211_free_node(ni); 2087 device_printf(sc->sc_dev, 2088 "could not add broadcast station\n"); 2089 return (error); 2090 } 2091 2092 /* Set initial MRR rate. */ 2093 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxbasicrate %d\n", __func__, 2094 maxbasicrate); 2095 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 2096 maxbasicrate); 2097 2098 /* Set rates mask for unicast frames. */ 2099 if (ni->ni_flags & IEEE80211_NODE_HT) 2100 mode = R92C_RAID_11GN; 2101 else if (ic->ic_curmode == IEEE80211_MODE_11B) 2102 mode = R92C_RAID_11B; 2103 else 2104 mode = R92C_RAID_11BG; 2105 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 2106 cmd.mask = htole32(mode << 28 | rates); 2107 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 2108 if (error != 0) { 2109 ieee80211_free_node(ni); 2110 device_printf(sc->sc_dev, "could not add BSS station\n"); 2111 return (error); 2112 } 2113 /* Set initial MRR rate. */ 2114 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxrate %d\n", __func__, 2115 maxrate); 2116 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 2117 maxrate); 2118 2119 /* Indicate highest supported rate. */ 2120 if (ni->ni_flags & IEEE80211_NODE_HT) 2121 ni->ni_txrate = rs_ht->rs_rates[rs_ht->rs_nrates - 1] 2122 | IEEE80211_RATE_MCS; 2123 else 2124 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 2125 ieee80211_free_node(ni); 2126 2127 return (0); 2128} 2129 2130static void 2131urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2132{ 2133 struct r92c_tx_desc *txd = &uvp->bcn_desc; 2134 2135 txd->txdw0 = htole32( 2136 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 2137 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2138 txd->txdw1 = htole32( 2139 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 2140 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2141 2142 if (sc->chip & URTWN_CHIP_88E) { 2143 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 2144 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 2145 } else { 2146 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 2147 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2148 } 2149 2150 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 2151 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 2152} 2153 2154static int 2155urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 2156{ 2157 struct ieee80211vap *vap = ni->ni_vap; 2158 struct urtwn_vap *uvp = URTWN_VAP(vap); 2159 struct mbuf *m; 2160 int error; 2161 2162 URTWN_ASSERT_LOCKED(sc); 2163 2164 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 2165 return (EINVAL); 2166 2167 m = ieee80211_beacon_alloc(ni); 2168 if (m == NULL) { 2169 device_printf(sc->sc_dev, 2170 "%s: could not allocate beacon frame\n", __func__); 2171 return (ENOMEM); 2172 } 2173 2174 if (uvp->bcn_mbuf != NULL) 2175 m_freem(uvp->bcn_mbuf); 2176 2177 uvp->bcn_mbuf = m; 2178 2179 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 2180 return (error); 2181 2182 /* XXX bcnq stuck workaround */ 2183 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 2184 return (error); 2185 2186 URTWN_DPRINTF(sc, URTWN_DEBUG_BEACON, "%s: beacon was %srecognized\n", 2187 __func__, urtwn_read_1(sc, R92C_TDECTRL + 2) & 2188 (R92C_TDECTRL_BCN_VALID >> 16) ? "" : "not "); 2189 2190 return (0); 2191} 2192 2193static void 2194urtwn_update_beacon(struct ieee80211vap *vap, int item) 2195{ 2196 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2197 struct urtwn_vap *uvp = URTWN_VAP(vap); 2198 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 2199 struct ieee80211_node *ni = vap->iv_bss; 2200 int mcast = 0; 2201 2202 URTWN_LOCK(sc); 2203 if (uvp->bcn_mbuf == NULL) { 2204 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 2205 if (uvp->bcn_mbuf == NULL) { 2206 device_printf(sc->sc_dev, 2207 "%s: could not allocate beacon frame\n", __func__); 2208 URTWN_UNLOCK(sc); 2209 return; 2210 } 2211 } 2212 URTWN_UNLOCK(sc); 2213 2214 if (item == IEEE80211_BEACON_TIM) 2215 mcast = 1; /* XXX */ 2216 2217 setbit(bo->bo_flags, item); 2218 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 2219 2220 URTWN_LOCK(sc); 2221 urtwn_tx_beacon(sc, uvp); 2222 URTWN_UNLOCK(sc); 2223} 2224 2225/* 2226 * Push a beacon frame into the chip. Beacon will 2227 * be repeated by the chip every R92C_BCN_INTERVAL. 2228 */ 2229static int 2230urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2231{ 2232 struct r92c_tx_desc *desc = &uvp->bcn_desc; 2233 struct urtwn_data *bf; 2234 2235 URTWN_ASSERT_LOCKED(sc); 2236 2237 bf = urtwn_getbuf(sc); 2238 if (bf == NULL) 2239 return (ENOMEM); 2240 2241 memcpy(bf->buf, desc, sizeof(*desc)); 2242 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 2243 2244 sc->sc_txtimer = 5; 2245 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2246 2247 return (0); 2248} 2249 2250static int 2251urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2252 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2253{ 2254 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2255 uint8_t i; 2256 2257 if (!(&vap->iv_nw_keys[0] <= k && 2258 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2259 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2260 URTWN_LOCK(sc); 2261 /* 2262 * First 4 slots for group keys, 2263 * what is left - for pairwise. 2264 * XXX incompatible with IBSS RSN. 2265 */ 2266 for (i = IEEE80211_WEP_NKID; 2267 i < R92C_CAM_ENTRY_COUNT; i++) { 2268 if ((sc->keys_bmap & (1 << i)) == 0) { 2269 sc->keys_bmap |= 1 << i; 2270 *keyix = i; 2271 break; 2272 } 2273 } 2274 URTWN_UNLOCK(sc); 2275 if (i == R92C_CAM_ENTRY_COUNT) { 2276 device_printf(sc->sc_dev, 2277 "%s: no free space in the key table\n", 2278 __func__); 2279 return 0; 2280 } 2281 } else 2282 *keyix = 0; 2283 } else { 2284 *keyix = k - vap->iv_nw_keys; 2285 } 2286 *rxkeyix = *keyix; 2287 return 1; 2288} 2289 2290static void 2291urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data) 2292{ 2293 struct ieee80211_key *k = &data->key; 2294 uint8_t algo, keyid; 2295 int i, error; 2296 2297 if (k->wk_keyix < IEEE80211_WEP_NKID) 2298 keyid = k->wk_keyix; 2299 else 2300 keyid = 0; 2301 2302 /* Map net80211 cipher to HW crypto algorithm. */ 2303 switch (k->wk_cipher->ic_cipher) { 2304 case IEEE80211_CIPHER_WEP: 2305 if (k->wk_keylen < 8) 2306 algo = R92C_CAM_ALGO_WEP40; 2307 else 2308 algo = R92C_CAM_ALGO_WEP104; 2309 break; 2310 case IEEE80211_CIPHER_TKIP: 2311 algo = R92C_CAM_ALGO_TKIP; 2312 break; 2313 case IEEE80211_CIPHER_AES_CCM: 2314 algo = R92C_CAM_ALGO_AES; 2315 break; 2316 default: 2317 device_printf(sc->sc_dev, "%s: undefined cipher %d\n", 2318 __func__, k->wk_cipher->ic_cipher); 2319 return; 2320 } 2321 2322 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2323 "%s: keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, " 2324 "macaddr %s\n", __func__, k->wk_keyix, keyid, 2325 k->wk_cipher->ic_cipher, algo, k->wk_flags, k->wk_keylen, 2326 ether_sprintf(k->wk_macaddr)); 2327 2328 /* Write key. */ 2329 for (i = 0; i < 4; i++) { 2330 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 2331 le32dec(&k->wk_key[i * 4])); 2332 if (error != 0) 2333 goto fail; 2334 } 2335 2336 /* Write CTL0 last since that will validate the CAM entry. */ 2337 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 2338 le32dec(&k->wk_macaddr[2])); 2339 if (error != 0) 2340 goto fail; 2341 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 2342 SM(R92C_CAM_ALGO, algo) | 2343 SM(R92C_CAM_KEYID, keyid) | 2344 SM(R92C_CAM_MACLO, le16dec(&k->wk_macaddr[0])) | 2345 R92C_CAM_VALID); 2346 if (error != 0) 2347 goto fail; 2348 2349 return; 2350 2351fail: 2352 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error); 2353} 2354 2355static void 2356urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data) 2357{ 2358 struct ieee80211_key *k = &data->key; 2359 int i; 2360 2361 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2362 "%s: keyix %d, flags %04X, macaddr %s\n", __func__, 2363 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr)); 2364 2365 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0); 2366 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0); 2367 2368 /* Clear key. */ 2369 for (i = 0; i < 4; i++) 2370 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0); 2371 sc->keys_bmap &= ~(1 << k->wk_keyix); 2372} 2373 2374static int 2375urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 2376{ 2377 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2378 struct urtwn_vap *uvp = URTWN_VAP(vap); 2379 2380 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2381 /* Not for us. */ 2382 return (1); 2383 } 2384 2385 if (&vap->iv_nw_keys[0] <= k && 2386 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID]) { 2387 URTWN_LOCK(sc); 2388 uvp->keys[k->wk_keyix] = k; 2389 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2390 /* 2391 * The device was not started; 2392 * the key will be installed later. 2393 */ 2394 URTWN_UNLOCK(sc); 2395 return (1); 2396 } 2397 URTWN_UNLOCK(sc); 2398 } 2399 2400 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb)); 2401} 2402 2403static int 2404urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2405{ 2406 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2407 struct urtwn_vap *uvp = URTWN_VAP(vap); 2408 2409 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2410 /* Not for us. */ 2411 return (1); 2412 } 2413 2414 if (&vap->iv_nw_keys[0] <= k && 2415 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID]) { 2416 URTWN_LOCK(sc); 2417 uvp->keys[k->wk_keyix] = NULL; 2418 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2419 /* All keys are removed on device reset. */ 2420 URTWN_UNLOCK(sc); 2421 return (1); 2422 } 2423 URTWN_UNLOCK(sc); 2424 } 2425 2426 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb)); 2427} 2428 2429static void 2430urtwn_tsf_task_adhoc(void *arg, int pending) 2431{ 2432 struct ieee80211vap *vap = arg; 2433 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2434 struct ieee80211_node *ni; 2435 uint32_t reg; 2436 2437 URTWN_LOCK(sc); 2438 ni = ieee80211_ref_node(vap->iv_bss); 2439 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 2440 2441 /* Accept beacons with the same BSSID. */ 2442 urtwn_set_rx_bssid_all(sc, 0); 2443 2444 /* Enable synchronization. */ 2445 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 2446 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2447 2448 /* Synchronize. */ 2449 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 2450 2451 /* Disable synchronization. */ 2452 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 2453 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2454 2455 /* Remove beacon filter. */ 2456 urtwn_set_rx_bssid_all(sc, 1); 2457 2458 /* Enable beaconing. */ 2459 urtwn_write_1(sc, R92C_MBID_NUM, 2460 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2461 reg |= R92C_BCN_CTRL_EN_BCN; 2462 2463 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2464 ieee80211_free_node(ni); 2465 URTWN_UNLOCK(sc); 2466} 2467 2468static void 2469urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 2470{ 2471 struct ieee80211com *ic = &sc->sc_ic; 2472 struct urtwn_vap *uvp = URTWN_VAP(vap); 2473 2474 /* Reset TSF. */ 2475 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2476 2477 switch (vap->iv_opmode) { 2478 case IEEE80211_M_STA: 2479 /* Enable TSF synchronization. */ 2480 urtwn_write_1(sc, R92C_BCN_CTRL, 2481 urtwn_read_1(sc, R92C_BCN_CTRL) & 2482 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 2483 break; 2484 case IEEE80211_M_IBSS: 2485 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 2486 break; 2487 case IEEE80211_M_HOSTAP: 2488 /* Enable beaconing. */ 2489 urtwn_write_1(sc, R92C_MBID_NUM, 2490 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2491 urtwn_write_1(sc, R92C_BCN_CTRL, 2492 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 2493 break; 2494 default: 2495 device_printf(sc->sc_dev, "undefined opmode %d\n", 2496 vap->iv_opmode); 2497 return; 2498 } 2499} 2500 2501static void 2502urtwn_get_tsf(struct urtwn_softc *sc, uint64_t *buf) 2503{ 2504 urtwn_read_region_1(sc, R92C_TSFTR, (uint8_t *)buf, sizeof(*buf)); 2505} 2506 2507static void 2508urtwn_set_led(struct urtwn_softc *sc, int led, int on) 2509{ 2510 uint8_t reg; 2511 2512 if (led == URTWN_LED_LINK) { 2513 if (sc->chip & URTWN_CHIP_88E) { 2514 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 2515 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 2516 if (!on) { 2517 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 2518 urtwn_write_1(sc, R92C_LEDCFG2, 2519 reg | R92C_LEDCFG0_DIS); 2520 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 2521 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 2522 0xfe); 2523 } 2524 } else { 2525 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 2526 if (!on) 2527 reg |= R92C_LEDCFG0_DIS; 2528 urtwn_write_1(sc, R92C_LEDCFG0, reg); 2529 } 2530 sc->ledlink = on; /* Save LED state. */ 2531 } 2532} 2533 2534static void 2535urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 2536{ 2537 uint8_t reg; 2538 2539 reg = urtwn_read_1(sc, R92C_MSR); 2540 reg = (reg & ~R92C_MSR_MASK) | mode; 2541 urtwn_write_1(sc, R92C_MSR, reg); 2542} 2543 2544static void 2545urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 2546 const struct ieee80211_rx_stats *rxs, 2547 int rssi, int nf) 2548{ 2549 struct ieee80211vap *vap = ni->ni_vap; 2550 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2551 struct urtwn_vap *uvp = URTWN_VAP(vap); 2552 uint64_t ni_tstamp, curr_tstamp; 2553 2554 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 2555 2556 if (vap->iv_state == IEEE80211_S_RUN && 2557 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 2558 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 2559 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 2560 URTWN_LOCK(sc); 2561 urtwn_get_tsf(sc, &curr_tstamp); 2562 URTWN_UNLOCK(sc); 2563 curr_tstamp = le64toh(curr_tstamp); 2564 2565 if (ni_tstamp >= curr_tstamp) 2566 (void) ieee80211_ibss_merge(ni); 2567 } 2568} 2569 2570static int 2571urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2572{ 2573 struct urtwn_vap *uvp = URTWN_VAP(vap); 2574 struct ieee80211com *ic = vap->iv_ic; 2575 struct urtwn_softc *sc = ic->ic_softc; 2576 struct ieee80211_node *ni; 2577 enum ieee80211_state ostate; 2578 uint32_t reg; 2579 uint8_t mode; 2580 int error = 0; 2581 2582 ostate = vap->iv_state; 2583 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s -> %s\n", 2584 ieee80211_state_name[ostate], ieee80211_state_name[nstate]); 2585 2586 IEEE80211_UNLOCK(ic); 2587 URTWN_LOCK(sc); 2588 callout_stop(&sc->sc_watchdog_ch); 2589 2590 if (ostate == IEEE80211_S_RUN) { 2591 /* Stop calibration. */ 2592 callout_stop(&sc->sc_calib_to); 2593 2594 /* Turn link LED off. */ 2595 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2596 2597 /* Set media status to 'No Link'. */ 2598 urtwn_set_mode(sc, R92C_MSR_NOLINK); 2599 2600 /* Stop Rx of data frames. */ 2601 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2602 2603 /* Disable TSF synchronization. */ 2604 urtwn_write_1(sc, R92C_BCN_CTRL, 2605 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 2606 R92C_BCN_CTRL_DIS_TSF_UDT0); 2607 2608 /* Disable beaconing. */ 2609 urtwn_write_1(sc, R92C_MBID_NUM, 2610 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 2611 2612 /* Reset TSF. */ 2613 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2614 2615 /* Reset EDCA parameters. */ 2616 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2617 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2618 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2619 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2620 } 2621 2622 switch (nstate) { 2623 case IEEE80211_S_INIT: 2624 /* Turn link LED off. */ 2625 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2626 break; 2627 case IEEE80211_S_SCAN: 2628 /* Pause AC Tx queues. */ 2629 urtwn_write_1(sc, R92C_TXPAUSE, 2630 urtwn_read_1(sc, R92C_TXPAUSE) | R92C_TX_QUEUE_AC); 2631 break; 2632 case IEEE80211_S_AUTH: 2633 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2634 break; 2635 case IEEE80211_S_RUN: 2636 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2637 /* Turn link LED on. */ 2638 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2639 break; 2640 } 2641 2642 ni = ieee80211_ref_node(vap->iv_bss); 2643 2644 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2645 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2646 device_printf(sc->sc_dev, 2647 "%s: could not move to RUN state\n", __func__); 2648 error = EINVAL; 2649 goto end_run; 2650 } 2651 2652 switch (vap->iv_opmode) { 2653 case IEEE80211_M_STA: 2654 mode = R92C_MSR_INFRA; 2655 break; 2656 case IEEE80211_M_IBSS: 2657 mode = R92C_MSR_ADHOC; 2658 break; 2659 case IEEE80211_M_HOSTAP: 2660 mode = R92C_MSR_AP; 2661 break; 2662 default: 2663 device_printf(sc->sc_dev, "undefined opmode %d\n", 2664 vap->iv_opmode); 2665 error = EINVAL; 2666 goto end_run; 2667 } 2668 2669 /* Set media status to 'Associated'. */ 2670 urtwn_set_mode(sc, mode); 2671 2672 /* Set BSSID. */ 2673 urtwn_write_4(sc, R92C_BSSID + 0, le32dec(&ni->ni_bssid[0])); 2674 urtwn_write_4(sc, R92C_BSSID + 4, le16dec(&ni->ni_bssid[4])); 2675 2676 if (ic->ic_curmode == IEEE80211_MODE_11B) 2677 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2678 else /* 802.11b/g */ 2679 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2680 2681 /* Enable Rx of data frames. */ 2682 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2683 2684 /* Flush all AC queues. */ 2685 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2686 2687 /* Set beacon interval. */ 2688 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2689 2690 /* Allow Rx from our BSSID only. */ 2691 if (ic->ic_promisc == 0) { 2692 reg = urtwn_read_4(sc, R92C_RCR); 2693 2694 if (vap->iv_opmode != IEEE80211_M_HOSTAP) { 2695 reg |= R92C_RCR_CBSSID_DATA; 2696 if (vap->iv_opmode != IEEE80211_M_IBSS) 2697 reg |= R92C_RCR_CBSSID_BCN; 2698 } 2699 2700 urtwn_write_4(sc, R92C_RCR, reg); 2701 } 2702 2703 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2704 vap->iv_opmode == IEEE80211_M_IBSS) { 2705 error = urtwn_setup_beacon(sc, ni); 2706 if (error != 0) { 2707 device_printf(sc->sc_dev, 2708 "unable to push beacon into the chip, " 2709 "error %d\n", error); 2710 goto end_run; 2711 } 2712 } 2713 2714 /* Enable TSF synchronization. */ 2715 urtwn_tsf_sync_enable(sc, vap); 2716 2717 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2718 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2719 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2720 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2721 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2722 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2723 2724 /* Intialize rate adaptation. */ 2725 if (!(sc->chip & URTWN_CHIP_88E)) 2726 urtwn_ra_init(sc); 2727 /* Turn link LED on. */ 2728 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2729 2730 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2731 /* Reset temperature calibration state machine. */ 2732 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 2733 sc->thcal_lctemp = 0; 2734 /* Start periodic calibration. */ 2735 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2736 2737end_run: 2738 ieee80211_free_node(ni); 2739 break; 2740 default: 2741 break; 2742 } 2743 2744 URTWN_UNLOCK(sc); 2745 IEEE80211_LOCK(ic); 2746 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2747} 2748 2749static void 2750urtwn_calib_to(void *arg) 2751{ 2752 struct urtwn_softc *sc = arg; 2753 2754 /* Do it in a process context. */ 2755 urtwn_cmd_sleepable(sc, NULL, 0, urtwn_calib_cb); 2756} 2757 2758static void 2759urtwn_calib_cb(struct urtwn_softc *sc, union sec_param *data) 2760{ 2761 /* Do temperature compensation. */ 2762 urtwn_temp_calib(sc); 2763 2764 if ((urtwn_read_1(sc, R92C_MSR) & R92C_MSR_MASK) != R92C_MSR_NOLINK) 2765 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2766} 2767 2768static void 2769urtwn_watchdog(void *arg) 2770{ 2771 struct urtwn_softc *sc = arg; 2772 2773 if (sc->sc_txtimer > 0) { 2774 if (--sc->sc_txtimer == 0) { 2775 device_printf(sc->sc_dev, "device timeout\n"); 2776 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2777 return; 2778 } 2779 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2780 } 2781} 2782 2783static void 2784urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2785{ 2786 int pwdb; 2787 2788 /* Convert antenna signal to percentage. */ 2789 if (rssi <= -100 || rssi >= 20) 2790 pwdb = 0; 2791 else if (rssi >= 0) 2792 pwdb = 100; 2793 else 2794 pwdb = 100 + rssi; 2795 if (!(sc->chip & URTWN_CHIP_88E)) { 2796 if (rate <= URTWN_RIDX_CCK11) { 2797 /* CCK gain is smaller than OFDM/MCS gain. */ 2798 pwdb += 6; 2799 if (pwdb > 100) 2800 pwdb = 100; 2801 if (pwdb <= 14) 2802 pwdb -= 4; 2803 else if (pwdb <= 26) 2804 pwdb -= 8; 2805 else if (pwdb <= 34) 2806 pwdb -= 6; 2807 else if (pwdb <= 42) 2808 pwdb -= 2; 2809 } 2810 } 2811 if (sc->avg_pwdb == -1) /* Init. */ 2812 sc->avg_pwdb = pwdb; 2813 else if (sc->avg_pwdb < pwdb) 2814 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2815 else 2816 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2817 URTWN_DPRINTF(sc, URTWN_DEBUG_RSSI, "%s: PWDB %d, EMA %d\n", __func__, 2818 pwdb, sc->avg_pwdb); 2819} 2820 2821static int8_t 2822urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2823{ 2824 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2825 struct r92c_rx_phystat *phy; 2826 struct r92c_rx_cck *cck; 2827 uint8_t rpt; 2828 int8_t rssi; 2829 2830 if (rate <= URTWN_RIDX_CCK11) { 2831 cck = (struct r92c_rx_cck *)physt; 2832 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2833 rpt = (cck->agc_rpt >> 5) & 0x3; 2834 rssi = (cck->agc_rpt & 0x1f) << 1; 2835 } else { 2836 rpt = (cck->agc_rpt >> 6) & 0x3; 2837 rssi = cck->agc_rpt & 0x3e; 2838 } 2839 rssi = cckoff[rpt] - rssi; 2840 } else { /* OFDM/HT. */ 2841 phy = (struct r92c_rx_phystat *)physt; 2842 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2843 } 2844 return (rssi); 2845} 2846 2847static int8_t 2848urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2849{ 2850 struct r92c_rx_phystat *phy; 2851 struct r88e_rx_cck *cck; 2852 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2853 int8_t rssi; 2854 2855 rssi = 0; 2856 if (rate <= URTWN_RIDX_CCK11) { 2857 cck = (struct r88e_rx_cck *)physt; 2858 cck_agc_rpt = cck->agc_rpt; 2859 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2860 vga_idx = cck_agc_rpt & 0x1f; 2861 switch (lna_idx) { 2862 case 7: 2863 if (vga_idx <= 27) 2864 rssi = -100 + 2* (27 - vga_idx); 2865 else 2866 rssi = -100; 2867 break; 2868 case 6: 2869 rssi = -48 + 2 * (2 - vga_idx); 2870 break; 2871 case 5: 2872 rssi = -42 + 2 * (7 - vga_idx); 2873 break; 2874 case 4: 2875 rssi = -36 + 2 * (7 - vga_idx); 2876 break; 2877 case 3: 2878 rssi = -24 + 2 * (7 - vga_idx); 2879 break; 2880 case 2: 2881 rssi = -12 + 2 * (5 - vga_idx); 2882 break; 2883 case 1: 2884 rssi = 8 - (2 * vga_idx); 2885 break; 2886 case 0: 2887 rssi = 14 - (2 * vga_idx); 2888 break; 2889 } 2890 rssi += 6; 2891 } else { /* OFDM/HT. */ 2892 phy = (struct r92c_rx_phystat *)physt; 2893 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2894 } 2895 return (rssi); 2896} 2897 2898static int 2899urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2900 struct mbuf *m, struct urtwn_data *data) 2901{ 2902 const struct ieee80211_txparam *tp; 2903 struct ieee80211com *ic = &sc->sc_ic; 2904 struct ieee80211vap *vap = ni->ni_vap; 2905 struct ieee80211_key *k = NULL; 2906 struct ieee80211_channel *chan; 2907 struct ieee80211_frame *wh; 2908 struct r92c_tx_desc *txd; 2909 uint8_t macid, raid, rate, ridx, type, tid, qos, qsel; 2910 int hasqos, ismcast; 2911 2912 URTWN_ASSERT_LOCKED(sc); 2913 2914 wh = mtod(m, struct ieee80211_frame *); 2915 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2916 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2917 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2918 2919 /* Select TX ring for this frame. */ 2920 if (hasqos) { 2921 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2922 tid = qos & IEEE80211_QOS_TID; 2923 } else { 2924 qos = 0; 2925 tid = 0; 2926 } 2927 2928 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2929 ni->ni_chan : ic->ic_curchan; 2930 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2931 2932 /* Choose a TX rate index. */ 2933 if (type == IEEE80211_FC0_TYPE_MGT) 2934 rate = tp->mgmtrate; 2935 else if (ismcast) 2936 rate = tp->mcastrate; 2937 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2938 rate = tp->ucastrate; 2939 else if (m->m_flags & M_EAPOL) 2940 rate = tp->mgmtrate; 2941 else { 2942 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2943 /* XXX pass pktlen */ 2944 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2945 rate = ni->ni_txrate; 2946 } else { 2947 /* XXX TODO: drop the default rate for 11b/11g? */ 2948 if (ni->ni_flags & IEEE80211_NODE_HT) 2949 rate = IEEE80211_RATE_MCS | 0x4; /* MCS4 */ 2950 else if (ic->ic_curmode != IEEE80211_MODE_11B) 2951 rate = 108; 2952 else 2953 rate = 22; 2954 } 2955 } 2956 2957 /* 2958 * XXX TODO: this should be per-node, for 11b versus 11bg 2959 * nodes in hostap mode 2960 */ 2961 ridx = rate2ridx(rate); 2962 if (ni->ni_flags & IEEE80211_NODE_HT) 2963 raid = R92C_RAID_11GN; 2964 else if (ic->ic_curmode != IEEE80211_MODE_11B) 2965 raid = R92C_RAID_11BG; 2966 else 2967 raid = R92C_RAID_11B; 2968 2969 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2970 k = ieee80211_crypto_encap(ni, m); 2971 if (k == NULL) { 2972 device_printf(sc->sc_dev, 2973 "ieee80211_crypto_encap returns NULL.\n"); 2974 return (ENOBUFS); 2975 } 2976 2977 /* in case packet header moved, reset pointer */ 2978 wh = mtod(m, struct ieee80211_frame *); 2979 } 2980 2981 /* Fill Tx descriptor. */ 2982 txd = (struct r92c_tx_desc *)data->buf; 2983 memset(txd, 0, sizeof(*txd)); 2984 2985 txd->txdw0 |= htole32( 2986 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2987 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2988 if (ismcast) 2989 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2990 2991 if (!ismcast) { 2992 /* Unicast frame, check if an ACK is expected. */ 2993 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 2994 IEEE80211_QOS_ACKPOLICY_NOACK) { 2995 txd->txdw5 |= htole32(R92C_TXDW5_RTY_LMT_ENA); 2996 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTY_LMT, 2997 tp->maxretry)); 2998 } 2999 3000 if (sc->chip & URTWN_CHIP_88E) { 3001 struct urtwn_node *un = URTWN_NODE(ni); 3002 macid = un->id; 3003 } else 3004 macid = URTWN_MACID_BSS; 3005 3006 if (type == IEEE80211_FC0_TYPE_DATA) { 3007 qsel = tid % URTWN_MAX_TID; 3008 3009 if (sc->chip & URTWN_CHIP_88E) { 3010 txd->txdw2 |= htole32( 3011 R88E_TXDW2_AGGBK | 3012 R88E_TXDW2_CCX_RPT); 3013 } else 3014 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 3015 3016 /* protmode, non-HT */ 3017 /* XXX TODO: noack frames? */ 3018 if ((rate & 0x80) == 0 && 3019 (ic->ic_flags & IEEE80211_F_USEPROT)) { 3020 switch (ic->ic_protmode) { 3021 case IEEE80211_PROT_CTSONLY: 3022 txd->txdw4 |= htole32( 3023 R92C_TXDW4_CTS2SELF); 3024 break; 3025 case IEEE80211_PROT_RTSCTS: 3026 txd->txdw4 |= htole32( 3027 R92C_TXDW4_RTSEN | 3028 R92C_TXDW4_HWRTSEN); 3029 break; 3030 default: 3031 break; 3032 } 3033 } 3034 3035 /* protmode, HT */ 3036 /* XXX TODO: noack frames? */ 3037 if ((rate & 0x80) && 3038 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) { 3039 txd->txdw4 |= htole32( 3040 R92C_TXDW4_RTSEN | 3041 R92C_TXDW4_HWRTSEN); 3042 } 3043 3044 /* XXX TODO: rtsrate is configurable? 24mbit may 3045 * be a bit high for RTS rate? */ 3046 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 3047 URTWN_RIDX_OFDM24)); 3048 3049 txd->txdw5 |= htole32(0x0001ff00); 3050 } else /* IEEE80211_FC0_TYPE_MGT */ 3051 qsel = R92C_TXDW1_QSEL_MGNT; 3052 } else { 3053 macid = URTWN_MACID_BC; 3054 qsel = R92C_TXDW1_QSEL_MGNT; 3055 } 3056 3057 txd->txdw1 |= htole32( 3058 SM(R92C_TXDW1_QSEL, qsel) | 3059 SM(R92C_TXDW1_RAID, raid)); 3060 3061 /* XXX TODO: 40MHZ flag? */ 3062 /* XXX TODO: AMPDU flag? (AGG_ENABLE or AGG_BREAK?) Density shift? */ 3063 /* XXX Short preamble? */ 3064 /* XXX Short-GI? */ 3065 3066 if (sc->chip & URTWN_CHIP_88E) 3067 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 3068 else 3069 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 3070 3071 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 3072 3073 /* Force this rate if needed. */ 3074 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 3075 (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) || 3076 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 3077 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3078 3079 if (!hasqos) { 3080 /* Use HW sequence numbering for non-QoS frames. */ 3081 if (sc->chip & URTWN_CHIP_88E) 3082 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 3083 else 3084 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 3085 } else { 3086 /* Set sequence number. */ 3087 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 3088 } 3089 3090 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 3091 uint8_t cipher; 3092 3093 switch (k->wk_cipher->ic_cipher) { 3094 case IEEE80211_CIPHER_WEP: 3095 case IEEE80211_CIPHER_TKIP: 3096 cipher = R92C_TXDW1_CIPHER_RC4; 3097 break; 3098 case IEEE80211_CIPHER_AES_CCM: 3099 cipher = R92C_TXDW1_CIPHER_AES; 3100 break; 3101 default: 3102 device_printf(sc->sc_dev, "%s: unknown cipher %d\n", 3103 __func__, k->wk_cipher->ic_cipher); 3104 return (EINVAL); 3105 } 3106 3107 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 3108 } 3109 3110 if (ieee80211_radiotap_active_vap(vap)) { 3111 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3112 3113 tap->wt_flags = 0; 3114 if (k != NULL) 3115 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3116 ieee80211_radiotap_tx(vap, m); 3117 } 3118 3119 data->ni = ni; 3120 3121 urtwn_tx_start(sc, m, type, data); 3122 3123 return (0); 3124} 3125 3126static int 3127urtwn_tx_raw(struct urtwn_softc *sc, struct ieee80211_node *ni, 3128 struct mbuf *m, struct urtwn_data *data, 3129 const struct ieee80211_bpf_params *params) 3130{ 3131 struct ieee80211vap *vap = ni->ni_vap; 3132 struct ieee80211_key *k = NULL; 3133 struct ieee80211_frame *wh; 3134 struct r92c_tx_desc *txd; 3135 uint8_t cipher, ridx, type; 3136 3137 /* Encrypt the frame if need be. */ 3138 cipher = R92C_TXDW1_CIPHER_NONE; 3139 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 3140 /* Retrieve key for TX. */ 3141 k = ieee80211_crypto_encap(ni, m); 3142 if (k == NULL) 3143 return (ENOBUFS); 3144 3145 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 3146 switch (k->wk_cipher->ic_cipher) { 3147 case IEEE80211_CIPHER_WEP: 3148 case IEEE80211_CIPHER_TKIP: 3149 cipher = R92C_TXDW1_CIPHER_RC4; 3150 break; 3151 case IEEE80211_CIPHER_AES_CCM: 3152 cipher = R92C_TXDW1_CIPHER_AES; 3153 break; 3154 default: 3155 device_printf(sc->sc_dev, 3156 "%s: unknown cipher %d\n", 3157 __func__, k->wk_cipher->ic_cipher); 3158 return (EINVAL); 3159 } 3160 } 3161 } 3162 3163 /* XXX TODO: 11n checks, matching urtwn_tx_data() */ 3164 3165 wh = mtod(m, struct ieee80211_frame *); 3166 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3167 3168 /* Fill Tx descriptor. */ 3169 txd = (struct r92c_tx_desc *)data->buf; 3170 memset(txd, 0, sizeof(*txd)); 3171 3172 txd->txdw0 |= htole32( 3173 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 3174 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 3175 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 3176 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 3177 3178 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3179 txd->txdw5 |= htole32(R92C_TXDW5_RTY_LMT_ENA); 3180 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTY_LMT, 3181 params->ibp_try0)); 3182 } 3183 if (params->ibp_flags & IEEE80211_BPF_RTS) 3184 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_HWRTSEN); 3185 if (params->ibp_flags & IEEE80211_BPF_CTS) 3186 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF); 3187 if (txd->txdw4 & htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_CTS2SELF)) { 3188 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 3189 URTWN_RIDX_OFDM24)); 3190 } 3191 3192 if (sc->chip & URTWN_CHIP_88E) 3193 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 3194 else 3195 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 3196 3197 /* XXX TODO: rate index/config (RAID) for 11n? */ 3198 txd->txdw1 |= htole32(SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT)); 3199 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 3200 3201 /* Choose a TX rate index. */ 3202 ridx = rate2ridx(params->ibp_rate0); 3203 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 3204 txd->txdw5 |= htole32(0x0001ff00); 3205 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 3206 3207 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 3208 /* Use HW sequence numbering for non-QoS frames. */ 3209 if (sc->chip & URTWN_CHIP_88E) 3210 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 3211 else 3212 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 3213 } else { 3214 /* Set sequence number. */ 3215 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 3216 } 3217 3218 if (ieee80211_radiotap_active_vap(vap)) { 3219 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 3220 3221 tap->wt_flags = 0; 3222 if (k != NULL) 3223 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3224 ieee80211_radiotap_tx(vap, m); 3225 } 3226 3227 data->ni = ni; 3228 3229 urtwn_tx_start(sc, m, type, data); 3230 3231 return (0); 3232} 3233 3234static void 3235urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 3236 struct urtwn_data *data) 3237{ 3238 struct usb_xfer *xfer; 3239 struct r92c_tx_desc *txd; 3240 uint16_t ac, sum; 3241 int i, xferlen; 3242 3243 URTWN_ASSERT_LOCKED(sc); 3244 3245 ac = M_WME_GETAC(m); 3246 3247 switch (type) { 3248 case IEEE80211_FC0_TYPE_CTL: 3249 case IEEE80211_FC0_TYPE_MGT: 3250 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 3251 break; 3252 default: 3253 xfer = sc->sc_xfer[wme2queue[ac].qid]; 3254 break; 3255 } 3256 3257 txd = (struct r92c_tx_desc *)data->buf; 3258 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 3259 3260 /* Compute Tx descriptor checksum. */ 3261 sum = 0; 3262 for (i = 0; i < sizeof(*txd) / 2; i++) 3263 sum ^= ((uint16_t *)txd)[i]; 3264 txd->txdsum = sum; /* NB: already little endian. */ 3265 3266 xferlen = sizeof(*txd) + m->m_pkthdr.len; 3267 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 3268 3269 data->buflen = xferlen; 3270 data->m = m; 3271 3272 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 3273 usbd_transfer_start(xfer); 3274} 3275 3276static int 3277urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 3278{ 3279 struct urtwn_softc *sc = ic->ic_softc; 3280 int error; 3281 3282 URTWN_LOCK(sc); 3283 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 3284 URTWN_UNLOCK(sc); 3285 return (ENXIO); 3286 } 3287 error = mbufq_enqueue(&sc->sc_snd, m); 3288 if (error) { 3289 URTWN_UNLOCK(sc); 3290 return (error); 3291 } 3292 urtwn_start(sc); 3293 URTWN_UNLOCK(sc); 3294 3295 return (0); 3296} 3297 3298static void 3299urtwn_start(struct urtwn_softc *sc) 3300{ 3301 struct ieee80211_node *ni; 3302 struct mbuf *m; 3303 struct urtwn_data *bf; 3304 3305 URTWN_ASSERT_LOCKED(sc); 3306 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 3307 bf = urtwn_getbuf(sc); 3308 if (bf == NULL) { 3309 mbufq_prepend(&sc->sc_snd, m); 3310 break; 3311 } 3312 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3313 m->m_pkthdr.rcvif = NULL; 3314 3315 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n", 3316 __func__, 3317 m); 3318 3319 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 3320 if_inc_counter(ni->ni_vap->iv_ifp, 3321 IFCOUNTER_OERRORS, 1); 3322 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3323 m_freem(m); 3324 ieee80211_free_node(ni); 3325 break; 3326 } 3327 sc->sc_txtimer = 5; 3328 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3329 } 3330} 3331 3332static void 3333urtwn_parent(struct ieee80211com *ic) 3334{ 3335 struct urtwn_softc *sc = ic->ic_softc; 3336 3337 URTWN_LOCK(sc); 3338 if (sc->sc_flags & URTWN_DETACHED) { 3339 URTWN_UNLOCK(sc); 3340 return; 3341 } 3342 URTWN_UNLOCK(sc); 3343 3344 if (ic->ic_nrunning > 0) { 3345 if (urtwn_init(sc) != 0) { 3346 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3347 if (vap != NULL) 3348 ieee80211_stop(vap); 3349 } else 3350 ieee80211_start_all(ic); 3351 } else 3352 urtwn_stop(sc); 3353} 3354 3355static __inline int 3356urtwn_power_on(struct urtwn_softc *sc) 3357{ 3358 3359 return sc->sc_power_on(sc); 3360} 3361 3362static int 3363urtwn_r92c_power_on(struct urtwn_softc *sc) 3364{ 3365 uint32_t reg; 3366 usb_error_t error; 3367 int ntries; 3368 3369 /* Wait for autoload done bit. */ 3370 for (ntries = 0; ntries < 1000; ntries++) { 3371 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3372 break; 3373 urtwn_ms_delay(sc); 3374 } 3375 if (ntries == 1000) { 3376 device_printf(sc->sc_dev, 3377 "timeout waiting for chip autoload\n"); 3378 return (ETIMEDOUT); 3379 } 3380 3381 /* Unlock ISO/CLK/Power control register. */ 3382 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3383 if (error != USB_ERR_NORMAL_COMPLETION) 3384 return (EIO); 3385 /* Move SPS into PWM mode. */ 3386 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3387 if (error != USB_ERR_NORMAL_COMPLETION) 3388 return (EIO); 3389 urtwn_ms_delay(sc); 3390 3391 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3392 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3393 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3394 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3395 if (error != USB_ERR_NORMAL_COMPLETION) 3396 return (EIO); 3397 urtwn_ms_delay(sc); 3398 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3399 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3400 ~R92C_SYS_ISO_CTRL_MD2PP); 3401 if (error != USB_ERR_NORMAL_COMPLETION) 3402 return (EIO); 3403 } 3404 3405 /* Auto enable WLAN. */ 3406 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3407 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3408 if (error != USB_ERR_NORMAL_COMPLETION) 3409 return (EIO); 3410 for (ntries = 0; ntries < 1000; ntries++) { 3411 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3412 R92C_APS_FSMCO_APFM_ONMAC)) 3413 break; 3414 urtwn_ms_delay(sc); 3415 } 3416 if (ntries == 1000) { 3417 device_printf(sc->sc_dev, 3418 "timeout waiting for MAC auto ON\n"); 3419 return (ETIMEDOUT); 3420 } 3421 3422 /* Enable radio, GPIO and LED functions. */ 3423 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3424 R92C_APS_FSMCO_AFSM_HSUS | 3425 R92C_APS_FSMCO_PDN_EN | 3426 R92C_APS_FSMCO_PFM_ALDN); 3427 if (error != USB_ERR_NORMAL_COMPLETION) 3428 return (EIO); 3429 /* Release RF digital isolation. */ 3430 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3431 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3432 if (error != USB_ERR_NORMAL_COMPLETION) 3433 return (EIO); 3434 3435 /* Initialize MAC. */ 3436 error = urtwn_write_1(sc, R92C_APSD_CTRL, 3437 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3438 if (error != USB_ERR_NORMAL_COMPLETION) 3439 return (EIO); 3440 for (ntries = 0; ntries < 200; ntries++) { 3441 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3442 R92C_APSD_CTRL_OFF_STATUS)) 3443 break; 3444 urtwn_ms_delay(sc); 3445 } 3446 if (ntries == 200) { 3447 device_printf(sc->sc_dev, 3448 "timeout waiting for MAC initialization\n"); 3449 return (ETIMEDOUT); 3450 } 3451 3452 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3453 reg = urtwn_read_2(sc, R92C_CR); 3454 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3455 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3456 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3457 R92C_CR_ENSEC; 3458 error = urtwn_write_2(sc, R92C_CR, reg); 3459 if (error != USB_ERR_NORMAL_COMPLETION) 3460 return (EIO); 3461 3462 error = urtwn_write_1(sc, 0xfe10, 0x19); 3463 if (error != USB_ERR_NORMAL_COMPLETION) 3464 return (EIO); 3465 return (0); 3466} 3467 3468static int 3469urtwn_r88e_power_on(struct urtwn_softc *sc) 3470{ 3471 uint32_t reg; 3472 usb_error_t error; 3473 int ntries; 3474 3475 /* Wait for power ready bit. */ 3476 for (ntries = 0; ntries < 5000; ntries++) { 3477 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 3478 break; 3479 urtwn_ms_delay(sc); 3480 } 3481 if (ntries == 5000) { 3482 device_printf(sc->sc_dev, 3483 "timeout waiting for chip power up\n"); 3484 return (ETIMEDOUT); 3485 } 3486 3487 /* Reset BB. */ 3488 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3489 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3490 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3491 if (error != USB_ERR_NORMAL_COMPLETION) 3492 return (EIO); 3493 3494 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3495 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3496 if (error != USB_ERR_NORMAL_COMPLETION) 3497 return (EIO); 3498 3499 /* Disable HWPDN. */ 3500 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3501 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3502 if (error != USB_ERR_NORMAL_COMPLETION) 3503 return (EIO); 3504 3505 /* Disable WL suspend. */ 3506 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3507 urtwn_read_2(sc, R92C_APS_FSMCO) & 3508 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 3509 if (error != USB_ERR_NORMAL_COMPLETION) 3510 return (EIO); 3511 3512 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3513 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3514 if (error != USB_ERR_NORMAL_COMPLETION) 3515 return (EIO); 3516 for (ntries = 0; ntries < 5000; ntries++) { 3517 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3518 R92C_APS_FSMCO_APFM_ONMAC)) 3519 break; 3520 urtwn_ms_delay(sc); 3521 } 3522 if (ntries == 5000) 3523 return (ETIMEDOUT); 3524 3525 /* Enable LDO normal mode. */ 3526 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 3527 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~R92C_LPLDO_CTRL_SLEEP); 3528 if (error != USB_ERR_NORMAL_COMPLETION) 3529 return (EIO); 3530 3531 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3532 error = urtwn_write_2(sc, R92C_CR, 0); 3533 if (error != USB_ERR_NORMAL_COMPLETION) 3534 return (EIO); 3535 reg = urtwn_read_2(sc, R92C_CR); 3536 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3537 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3538 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3539 error = urtwn_write_2(sc, R92C_CR, reg); 3540 if (error != USB_ERR_NORMAL_COMPLETION) 3541 return (EIO); 3542 3543 return (0); 3544} 3545 3546static __inline void 3547urtwn_power_off(struct urtwn_softc *sc) 3548{ 3549 3550 return sc->sc_power_off(sc); 3551} 3552 3553static void 3554urtwn_r92c_power_off(struct urtwn_softc *sc) 3555{ 3556 uint32_t reg; 3557 3558 /* Block all Tx queues. */ 3559 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3560 3561 /* Disable RF */ 3562 urtwn_rf_write(sc, 0, 0, 0); 3563 3564 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3565 3566 /* Reset BB state machine */ 3567 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3568 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA | 3569 R92C_SYS_FUNC_EN_BB_GLB_RST); 3570 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3571 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3572 3573 /* 3574 * Reset digital sequence 3575 */ 3576#ifndef URTWN_WITHOUT_UCODE 3577 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3578 /* Reset MCU ready status */ 3579 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3580 3581 /* If firmware in ram code, do reset */ 3582 urtwn_fw_reset(sc); 3583 } 3584#endif 3585 3586 /* Reset MAC and Enable 8051 */ 3587 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 3588 (R92C_SYS_FUNC_EN_CPUEN | 3589 R92C_SYS_FUNC_EN_ELDR | 3590 R92C_SYS_FUNC_EN_HWPDN) >> 8); 3591 3592 /* Reset MCU ready status */ 3593 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3594 3595 /* Disable MAC clock */ 3596 urtwn_write_2(sc, R92C_SYS_CLKR, 3597 R92C_SYS_CLKR_ANAD16V_EN | 3598 R92C_SYS_CLKR_ANA8M | 3599 R92C_SYS_CLKR_LOADER_EN | 3600 R92C_SYS_CLKR_80M_SSC_DIS | 3601 R92C_SYS_CLKR_SYS_EN | 3602 R92C_SYS_CLKR_RING_EN | 3603 0x4000); 3604 3605 /* Disable AFE PLL */ 3606 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3607 3608 /* Gated AFE DIG_CLOCK */ 3609 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3610 3611 /* Isolated digital to PON */ 3612 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3613 R92C_SYS_ISO_CTRL_MD2PP | 3614 R92C_SYS_ISO_CTRL_PA2PCIE | 3615 R92C_SYS_ISO_CTRL_PD2CORE | 3616 R92C_SYS_ISO_CTRL_IP2MAC | 3617 R92C_SYS_ISO_CTRL_DIOP | 3618 R92C_SYS_ISO_CTRL_DIOE); 3619 3620 /* 3621 * Pull GPIO PIN to balance level and LED control 3622 */ 3623 /* 1. Disable GPIO[7:0] */ 3624 urtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000); 3625 3626 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3627 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3628 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3629 3630 /* Disable GPIO[10:8] */ 3631 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x00); 3632 3633 reg = urtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0; 3634 reg |= (((reg & 0x000f) << 4) | 0x0780); 3635 urtwn_write_2(sc, R92C_GPIO_IO_SEL, reg); 3636 3637 /* Disable LED0 & 1 */ 3638 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3639 3640 /* 3641 * Reset digital sequence 3642 */ 3643 /* Disable ELDR clock */ 3644 urtwn_write_2(sc, R92C_SYS_CLKR, 3645 R92C_SYS_CLKR_ANAD16V_EN | 3646 R92C_SYS_CLKR_ANA8M | 3647 R92C_SYS_CLKR_LOADER_EN | 3648 R92C_SYS_CLKR_80M_SSC_DIS | 3649 R92C_SYS_CLKR_SYS_EN | 3650 R92C_SYS_CLKR_RING_EN | 3651 0x4000); 3652 3653 /* Isolated ELDR to PON */ 3654 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 3655 (R92C_SYS_ISO_CTRL_DIOR | 3656 R92C_SYS_ISO_CTRL_PWC_EV12V) >> 8); 3657 3658 /* 3659 * Disable analog sequence 3660 */ 3661 /* Disable A15 power */ 3662 urtwn_write_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_OBUF); 3663 /* Disable digital core power */ 3664 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3665 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3666 ~R92C_LDOV12D_CTRL_LDV12_EN); 3667 3668 /* Enter PFM mode */ 3669 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3670 3671 /* Set USB suspend */ 3672 urtwn_write_2(sc, R92C_APS_FSMCO, 3673 R92C_APS_FSMCO_APDM_HOST | 3674 R92C_APS_FSMCO_AFSM_HSUS | 3675 R92C_APS_FSMCO_PFM_ALDN); 3676 3677 /* Lock ISO/CLK/Power control register. */ 3678 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 3679} 3680 3681static void 3682urtwn_r88e_power_off(struct urtwn_softc *sc) 3683{ 3684 uint8_t reg; 3685 int ntries; 3686 3687 /* Disable any kind of TX reports. */ 3688 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 3689 urtwn_read_1(sc, R88E_TX_RPT_CTRL) & 3690 ~(R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA)); 3691 3692 /* Stop Rx. */ 3693 urtwn_write_1(sc, R92C_CR, 0); 3694 3695 /* Move card to Low Power State. */ 3696 /* Block all Tx queues. */ 3697 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3698 3699 for (ntries = 0; ntries < 20; ntries++) { 3700 /* Should be zero if no packet is transmitting. */ 3701 if (urtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 3702 break; 3703 3704 urtwn_ms_delay(sc); 3705 } 3706 if (ntries == 20) { 3707 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 3708 __func__); 3709 return; 3710 } 3711 3712 /* CCK and OFDM are disabled, and clock are gated. */ 3713 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3714 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_BBRSTB); 3715 3716 urtwn_ms_delay(sc); 3717 3718 /* Reset MAC TRX */ 3719 urtwn_write_1(sc, R92C_CR, 3720 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3721 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | 3722 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN); 3723 3724 /* check if removed later */ 3725 urtwn_write_1(sc, R92C_CR + 1, 3726 urtwn_read_1(sc, R92C_CR + 1) & ~(R92C_CR_ENSEC >> 8)); 3727 3728 /* Respond TxOK to scheduler */ 3729 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 3730 urtwn_read_1(sc, R92C_DUAL_TSF_RST) | 0x20); 3731 3732 /* If firmware in ram code, do reset. */ 3733#ifndef URTWN_WITHOUT_UCODE 3734 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) 3735 urtwn_r88e_fw_reset(sc); 3736#endif 3737 3738 /* Reset MCU ready status. */ 3739 urtwn_write_1(sc, R92C_MCUFWDL, 0x00); 3740 3741 /* Disable 32k. */ 3742 urtwn_write_1(sc, R88E_32K_CTRL, 3743 urtwn_read_1(sc, R88E_32K_CTRL) & ~0x01); 3744 3745 /* Move card to Disabled state. */ 3746 /* Turn off RF. */ 3747 urtwn_write_1(sc, R92C_RF_CTRL, 0); 3748 3749 /* LDO Sleep mode. */ 3750 urtwn_write_1(sc, R92C_LPLDO_CTRL, 3751 urtwn_read_1(sc, R92C_LPLDO_CTRL) | R92C_LPLDO_CTRL_SLEEP); 3752 3753 /* Turn off MAC by HW state machine */ 3754 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3755 urtwn_read_1(sc, R92C_APS_FSMCO + 1) | 3756 (R92C_APS_FSMCO_APFM_OFF >> 8)); 3757 3758 for (ntries = 0; ntries < 20; ntries++) { 3759 /* Wait until it will be disabled. */ 3760 if ((urtwn_read_1(sc, R92C_APS_FSMCO + 1) & 3761 (R92C_APS_FSMCO_APFM_OFF >> 8)) == 0) 3762 break; 3763 3764 urtwn_ms_delay(sc); 3765 } 3766 if (ntries == 20) { 3767 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 3768 __func__); 3769 return; 3770 } 3771 3772 /* schmit trigger */ 3773 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3774 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3775 3776 /* Enable WL suspend. */ 3777 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3778 (urtwn_read_1(sc, R92C_APS_FSMCO + 1) & ~0x10) | 0x08); 3779 3780 /* Enable bandgap mbias in suspend. */ 3781 urtwn_write_1(sc, R92C_APS_FSMCO + 3, 0); 3782 3783 /* Clear SIC_EN register. */ 3784 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 1, 3785 urtwn_read_1(sc, R92C_GPIO_MUXCFG + 1) & ~0x10); 3786 3787 /* Set USB suspend enable local register */ 3788 urtwn_write_1(sc, R92C_USB_SUSPEND, 3789 urtwn_read_1(sc, R92C_USB_SUSPEND) | 0x10); 3790 3791 /* Reset MCU IO Wrapper. */ 3792 reg = urtwn_read_1(sc, R92C_RSV_CTRL + 1); 3793 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08); 3794 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08); 3795 3796 /* marked as 'For Power Consumption' code. */ 3797 urtwn_write_1(sc, R92C_GPIO_OUT, urtwn_read_1(sc, R92C_GPIO_IN)); 3798 urtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff); 3799 3800 urtwn_write_1(sc, R92C_GPIO_IO_SEL, 3801 urtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4); 3802 urtwn_write_1(sc, R92C_GPIO_MOD, 3803 urtwn_read_1(sc, R92C_GPIO_MOD) | 0x0f); 3804 3805 /* Set LNA, TRSW, EX_PA Pin to output mode. */ 3806 urtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808); 3807} 3808 3809static int 3810urtwn_llt_init(struct urtwn_softc *sc) 3811{ 3812 int i, error, page_count, pktbuf_count; 3813 3814 page_count = (sc->chip & URTWN_CHIP_88E) ? 3815 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 3816 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 3817 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 3818 3819 /* Reserve pages [0; page_count]. */ 3820 for (i = 0; i < page_count; i++) { 3821 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3822 return (error); 3823 } 3824 /* NB: 0xff indicates end-of-list. */ 3825 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3826 return (error); 3827 /* 3828 * Use pages [page_count + 1; pktbuf_count - 1] 3829 * as ring buffer. 3830 */ 3831 for (++i; i < pktbuf_count - 1; i++) { 3832 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3833 return (error); 3834 } 3835 /* Make the last page point to the beginning of the ring buffer. */ 3836 error = urtwn_llt_write(sc, i, page_count + 1); 3837 return (error); 3838} 3839 3840#ifndef URTWN_WITHOUT_UCODE 3841static void 3842urtwn_fw_reset(struct urtwn_softc *sc) 3843{ 3844 uint16_t reg; 3845 int ntries; 3846 3847 /* Tell 8051 to reset itself. */ 3848 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3849 3850 /* Wait until 8051 resets by itself. */ 3851 for (ntries = 0; ntries < 100; ntries++) { 3852 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3853 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3854 return; 3855 urtwn_ms_delay(sc); 3856 } 3857 /* Force 8051 reset. */ 3858 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3859} 3860 3861static void 3862urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3863{ 3864 uint16_t reg; 3865 3866 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3867 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3868 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3869} 3870 3871static int 3872urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 3873{ 3874 uint32_t reg; 3875 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 3876 int off, mlen; 3877 3878 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3879 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3880 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3881 3882 off = R92C_FW_START_ADDR; 3883 while (len > 0) { 3884 if (len > 196) 3885 mlen = 196; 3886 else if (len > 4) 3887 mlen = 4; 3888 else 3889 mlen = 1; 3890 /* XXX fix this deconst */ 3891 error = urtwn_write_region_1(sc, off, 3892 __DECONST(uint8_t *, buf), mlen); 3893 if (error != USB_ERR_NORMAL_COMPLETION) 3894 break; 3895 off += mlen; 3896 buf += mlen; 3897 len -= mlen; 3898 } 3899 return (error); 3900} 3901 3902static int 3903urtwn_load_firmware(struct urtwn_softc *sc) 3904{ 3905 const struct firmware *fw; 3906 const struct r92c_fw_hdr *hdr; 3907 const char *imagename; 3908 const u_char *ptr; 3909 size_t len; 3910 uint32_t reg; 3911 int mlen, ntries, page, error; 3912 3913 URTWN_UNLOCK(sc); 3914 /* Read firmware image from the filesystem. */ 3915 if (sc->chip & URTWN_CHIP_88E) 3916 imagename = "urtwn-rtl8188eufw"; 3917 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3918 URTWN_CHIP_UMC_A_CUT) 3919 imagename = "urtwn-rtl8192cfwU"; 3920 else 3921 imagename = "urtwn-rtl8192cfwT"; 3922 3923 fw = firmware_get(imagename); 3924 URTWN_LOCK(sc); 3925 if (fw == NULL) { 3926 device_printf(sc->sc_dev, 3927 "failed loadfirmware of file %s\n", imagename); 3928 return (ENOENT); 3929 } 3930 3931 len = fw->datasize; 3932 3933 if (len < sizeof(*hdr)) { 3934 device_printf(sc->sc_dev, "firmware too short\n"); 3935 error = EINVAL; 3936 goto fail; 3937 } 3938 ptr = fw->data; 3939 hdr = (const struct r92c_fw_hdr *)ptr; 3940 /* Check if there is a valid FW header and skip it. */ 3941 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3942 (le16toh(hdr->signature) >> 4) == 0x88e || 3943 (le16toh(hdr->signature) >> 4) == 0x92c) { 3944 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, 3945 "FW V%d.%d %02d-%02d %02d:%02d\n", 3946 le16toh(hdr->version), le16toh(hdr->subversion), 3947 hdr->month, hdr->date, hdr->hour, hdr->minute); 3948 ptr += sizeof(*hdr); 3949 len -= sizeof(*hdr); 3950 } 3951 3952 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3953 if (sc->chip & URTWN_CHIP_88E) 3954 urtwn_r88e_fw_reset(sc); 3955 else 3956 urtwn_fw_reset(sc); 3957 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3958 } 3959 3960 if (!(sc->chip & URTWN_CHIP_88E)) { 3961 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3962 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3963 R92C_SYS_FUNC_EN_CPUEN); 3964 } 3965 urtwn_write_1(sc, R92C_MCUFWDL, 3966 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3967 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3968 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3969 3970 /* Reset the FWDL checksum. */ 3971 urtwn_write_1(sc, R92C_MCUFWDL, 3972 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3973 3974 for (page = 0; len > 0; page++) { 3975 mlen = min(len, R92C_FW_PAGE_SIZE); 3976 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3977 if (error != 0) { 3978 device_printf(sc->sc_dev, 3979 "could not load firmware page\n"); 3980 goto fail; 3981 } 3982 ptr += mlen; 3983 len -= mlen; 3984 } 3985 urtwn_write_1(sc, R92C_MCUFWDL, 3986 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3987 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3988 3989 /* Wait for checksum report. */ 3990 for (ntries = 0; ntries < 1000; ntries++) { 3991 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3992 break; 3993 urtwn_ms_delay(sc); 3994 } 3995 if (ntries == 1000) { 3996 device_printf(sc->sc_dev, 3997 "timeout waiting for checksum report\n"); 3998 error = ETIMEDOUT; 3999 goto fail; 4000 } 4001 4002 reg = urtwn_read_4(sc, R92C_MCUFWDL); 4003 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 4004 urtwn_write_4(sc, R92C_MCUFWDL, reg); 4005 if (sc->chip & URTWN_CHIP_88E) 4006 urtwn_r88e_fw_reset(sc); 4007 /* Wait for firmware readiness. */ 4008 for (ntries = 0; ntries < 1000; ntries++) { 4009 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 4010 break; 4011 urtwn_ms_delay(sc); 4012 } 4013 if (ntries == 1000) { 4014 device_printf(sc->sc_dev, 4015 "timeout waiting for firmware readiness\n"); 4016 error = ETIMEDOUT; 4017 goto fail; 4018 } 4019fail: 4020 firmware_put(fw, FIRMWARE_UNLOAD); 4021 return (error); 4022} 4023#endif 4024 4025static int 4026urtwn_dma_init(struct urtwn_softc *sc) 4027{ 4028 struct usb_endpoint *ep, *ep_end; 4029 usb_error_t usb_err; 4030 uint32_t reg; 4031 int hashq, hasnq, haslq, nqueues, ntx; 4032 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 4033 4034 /* Initialize LLT table. */ 4035 error = urtwn_llt_init(sc); 4036 if (error != 0) 4037 return (error); 4038 4039 /* Determine the number of bulk-out pipes. */ 4040 ntx = 0; 4041 ep = sc->sc_udev->endpoints; 4042 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 4043 for (; ep != ep_end; ep++) { 4044 if ((ep->edesc == NULL) || 4045 (ep->iface_index != sc->sc_iface_index)) 4046 continue; 4047 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 4048 ntx++; 4049 } 4050 if (ntx == 0) { 4051 device_printf(sc->sc_dev, 4052 "%d: invalid number of Tx bulk pipes\n", ntx); 4053 return (EIO); 4054 } 4055 4056 /* Get Tx queues to USB endpoints mapping. */ 4057 hashq = hasnq = haslq = nqueues = 0; 4058 switch (ntx) { 4059 case 1: hashq = 1; break; 4060 case 2: hashq = hasnq = 1; break; 4061 case 3: case 4: hashq = hasnq = haslq = 1; break; 4062 } 4063 nqueues = hashq + hasnq + haslq; 4064 if (nqueues == 0) 4065 return (EIO); 4066 4067 npubqpages = nqpages = nrempages = pagecount = 0; 4068 if (sc->chip & URTWN_CHIP_88E) 4069 tx_boundary = R88E_TX_PAGE_BOUNDARY; 4070 else { 4071 pagecount = R92C_TX_PAGE_COUNT; 4072 npubqpages = R92C_PUBQ_NPAGES; 4073 tx_boundary = R92C_TX_PAGE_BOUNDARY; 4074 } 4075 4076 /* Set number of pages for normal priority queue. */ 4077 if (sc->chip & URTWN_CHIP_88E) { 4078 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 4079 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4080 return (EIO); 4081 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 4082 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4083 return (EIO); 4084 } else { 4085 /* Get the number of pages for each queue. */ 4086 nqpages = (pagecount - npubqpages) / nqueues; 4087 /* 4088 * The remaining pages are assigned to the high priority 4089 * queue. 4090 */ 4091 nrempages = (pagecount - npubqpages) % nqueues; 4092 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 4093 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4094 return (EIO); 4095 usb_err = urtwn_write_4(sc, R92C_RQPN, 4096 /* Set number of pages for public queue. */ 4097 SM(R92C_RQPN_PUBQ, npubqpages) | 4098 /* Set number of pages for high priority queue. */ 4099 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 4100 /* Set number of pages for low priority queue. */ 4101 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 4102 /* Load values. */ 4103 R92C_RQPN_LD); 4104 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4105 return (EIO); 4106 } 4107 4108 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 4109 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4110 return (EIO); 4111 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 4112 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4113 return (EIO); 4114 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 4115 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4116 return (EIO); 4117 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 4118 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4119 return (EIO); 4120 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 4121 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4122 return (EIO); 4123 4124 /* Set queue to USB pipe mapping. */ 4125 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 4126 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 4127 if (nqueues == 1) { 4128 if (hashq) 4129 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 4130 else if (hasnq) 4131 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 4132 else 4133 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 4134 } else if (nqueues == 2) { 4135 /* 4136 * All 2-endpoints configs have high and normal 4137 * priority queues. 4138 */ 4139 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 4140 } else 4141 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 4142 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 4143 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4144 return (EIO); 4145 4146 /* Set Tx/Rx transfer page boundary. */ 4147 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 4148 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 4149 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4150 return (EIO); 4151 4152 /* Set Tx/Rx transfer page size. */ 4153 usb_err = urtwn_write_1(sc, R92C_PBP, 4154 SM(R92C_PBP_PSRX, R92C_PBP_128) | 4155 SM(R92C_PBP_PSTX, R92C_PBP_128)); 4156 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4157 return (EIO); 4158 4159 return (0); 4160} 4161 4162static int 4163urtwn_mac_init(struct urtwn_softc *sc) 4164{ 4165 usb_error_t error; 4166 int i; 4167 4168 /* Write MAC initialization values. */ 4169 if (sc->chip & URTWN_CHIP_88E) { 4170 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 4171 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 4172 rtl8188eu_mac[i].val); 4173 if (error != USB_ERR_NORMAL_COMPLETION) 4174 return (EIO); 4175 } 4176 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 4177 } else { 4178 for (i = 0; i < nitems(rtl8192cu_mac); i++) 4179 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 4180 rtl8192cu_mac[i].val); 4181 if (error != USB_ERR_NORMAL_COMPLETION) 4182 return (EIO); 4183 } 4184 4185 return (0); 4186} 4187 4188static void 4189urtwn_bb_init(struct urtwn_softc *sc) 4190{ 4191 const struct urtwn_bb_prog *prog; 4192 uint32_t reg; 4193 uint8_t crystalcap; 4194 int i; 4195 4196 /* Enable BB and RF. */ 4197 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 4198 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 4199 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 4200 R92C_SYS_FUNC_EN_DIO_RF); 4201 4202 if (!(sc->chip & URTWN_CHIP_88E)) 4203 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 4204 4205 urtwn_write_1(sc, R92C_RF_CTRL, 4206 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 4207 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 4208 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 4209 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 4210 4211 if (!(sc->chip & URTWN_CHIP_88E)) { 4212 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 4213 urtwn_write_1(sc, 0x15, 0xe9); 4214 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 4215 } 4216 4217 /* Select BB programming based on board type. */ 4218 if (sc->chip & URTWN_CHIP_88E) 4219 prog = &rtl8188eu_bb_prog; 4220 else if (!(sc->chip & URTWN_CHIP_92C)) { 4221 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4222 prog = &rtl8188ce_bb_prog; 4223 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4224 prog = &rtl8188ru_bb_prog; 4225 else 4226 prog = &rtl8188cu_bb_prog; 4227 } else { 4228 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4229 prog = &rtl8192ce_bb_prog; 4230 else 4231 prog = &rtl8192cu_bb_prog; 4232 } 4233 /* Write BB initialization values. */ 4234 for (i = 0; i < prog->count; i++) { 4235 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 4236 urtwn_ms_delay(sc); 4237 } 4238 4239 if (sc->chip & URTWN_CHIP_92C_1T2R) { 4240 /* 8192C 1T only configuration. */ 4241 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 4242 reg = (reg & ~0x00000003) | 0x2; 4243 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 4244 4245 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 4246 reg = (reg & ~0x00300033) | 0x00200022; 4247 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 4248 4249 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 4250 reg = (reg & ~0xff000000) | 0x45 << 24; 4251 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 4252 4253 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4254 reg = (reg & ~0x000000ff) | 0x23; 4255 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 4256 4257 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 4258 reg = (reg & ~0x00000030) | 1 << 4; 4259 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 4260 4261 reg = urtwn_bb_read(sc, 0xe74); 4262 reg = (reg & ~0x0c000000) | 2 << 26; 4263 urtwn_bb_write(sc, 0xe74, reg); 4264 reg = urtwn_bb_read(sc, 0xe78); 4265 reg = (reg & ~0x0c000000) | 2 << 26; 4266 urtwn_bb_write(sc, 0xe78, reg); 4267 reg = urtwn_bb_read(sc, 0xe7c); 4268 reg = (reg & ~0x0c000000) | 2 << 26; 4269 urtwn_bb_write(sc, 0xe7c, reg); 4270 reg = urtwn_bb_read(sc, 0xe80); 4271 reg = (reg & ~0x0c000000) | 2 << 26; 4272 urtwn_bb_write(sc, 0xe80, reg); 4273 reg = urtwn_bb_read(sc, 0xe88); 4274 reg = (reg & ~0x0c000000) | 2 << 26; 4275 urtwn_bb_write(sc, 0xe88, reg); 4276 } 4277 4278 /* Write AGC values. */ 4279 for (i = 0; i < prog->agccount; i++) { 4280 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 4281 prog->agcvals[i]); 4282 urtwn_ms_delay(sc); 4283 } 4284 4285 if (sc->chip & URTWN_CHIP_88E) { 4286 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4287 urtwn_ms_delay(sc); 4288 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4289 urtwn_ms_delay(sc); 4290 4291 crystalcap = sc->rom.r88e_rom.crystalcap; 4292 if (crystalcap == 0xff) 4293 crystalcap = 0x20; 4294 crystalcap &= 0x3f; 4295 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4296 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4297 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4298 crystalcap | crystalcap << 6)); 4299 } else { 4300 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4301 R92C_HSSI_PARAM2_CCK_HIPWR) 4302 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 4303 } 4304} 4305 4306static void 4307urtwn_rf_init(struct urtwn_softc *sc) 4308{ 4309 const struct urtwn_rf_prog *prog; 4310 uint32_t reg, type; 4311 int i, j, idx, off; 4312 4313 /* Select RF programming based on board type. */ 4314 if (sc->chip & URTWN_CHIP_88E) 4315 prog = rtl8188eu_rf_prog; 4316 else if (!(sc->chip & URTWN_CHIP_92C)) { 4317 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4318 prog = rtl8188ce_rf_prog; 4319 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4320 prog = rtl8188ru_rf_prog; 4321 else 4322 prog = rtl8188cu_rf_prog; 4323 } else 4324 prog = rtl8192ce_rf_prog; 4325 4326 for (i = 0; i < sc->nrxchains; i++) { 4327 /* Save RF_ENV control type. */ 4328 idx = i / 2; 4329 off = (i % 2) * 16; 4330 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4331 type = (reg >> off) & 0x10; 4332 4333 /* Set RF_ENV enable. */ 4334 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4335 reg |= 0x100000; 4336 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4337 urtwn_ms_delay(sc); 4338 /* Set RF_ENV output high. */ 4339 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4340 reg |= 0x10; 4341 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4342 urtwn_ms_delay(sc); 4343 /* Set address and data lengths of RF registers. */ 4344 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4345 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4346 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4347 urtwn_ms_delay(sc); 4348 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4349 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4350 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4351 urtwn_ms_delay(sc); 4352 4353 /* Write RF initialization values for this chain. */ 4354 for (j = 0; j < prog[i].count; j++) { 4355 if (prog[i].regs[j] >= 0xf9 && 4356 prog[i].regs[j] <= 0xfe) { 4357 /* 4358 * These are fake RF registers offsets that 4359 * indicate a delay is required. 4360 */ 4361 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 4362 continue; 4363 } 4364 urtwn_rf_write(sc, i, prog[i].regs[j], 4365 prog[i].vals[j]); 4366 urtwn_ms_delay(sc); 4367 } 4368 4369 /* Restore RF_ENV control type. */ 4370 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4371 reg &= ~(0x10 << off) | (type << off); 4372 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 4373 4374 /* Cache RF register CHNLBW. */ 4375 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4376 } 4377 4378 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4379 URTWN_CHIP_UMC_A_CUT) { 4380 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4381 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4382 } 4383} 4384 4385static void 4386urtwn_cam_init(struct urtwn_softc *sc) 4387{ 4388 /* Invalidate all CAM entries. */ 4389 urtwn_write_4(sc, R92C_CAMCMD, 4390 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4391} 4392 4393static int 4394urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 4395{ 4396 usb_error_t error; 4397 4398 error = urtwn_write_4(sc, R92C_CAMWRITE, data); 4399 if (error != USB_ERR_NORMAL_COMPLETION) 4400 return (EIO); 4401 error = urtwn_write_4(sc, R92C_CAMCMD, 4402 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 4403 SM(R92C_CAMCMD_ADDR, addr)); 4404 if (error != USB_ERR_NORMAL_COMPLETION) 4405 return (EIO); 4406 4407 return (0); 4408} 4409 4410static void 4411urtwn_pa_bias_init(struct urtwn_softc *sc) 4412{ 4413 uint8_t reg; 4414 int i; 4415 4416 for (i = 0; i < sc->nrxchains; i++) { 4417 if (sc->pa_setting & (1 << i)) 4418 continue; 4419 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4420 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4421 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4422 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4423 } 4424 if (!(sc->pa_setting & 0x10)) { 4425 reg = urtwn_read_1(sc, 0x16); 4426 reg = (reg & ~0xf0) | 0x90; 4427 urtwn_write_1(sc, 0x16, reg); 4428 } 4429} 4430 4431static void 4432urtwn_rxfilter_init(struct urtwn_softc *sc) 4433{ 4434 struct ieee80211com *ic = &sc->sc_ic; 4435 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4436 uint32_t rcr; 4437 uint16_t filter; 4438 4439 URTWN_ASSERT_LOCKED(sc); 4440 4441 /* Setup multicast filter. */ 4442 urtwn_set_multi(sc); 4443 4444 /* Filter for management frames. */ 4445 filter = 0x7f3f; 4446 switch (vap->iv_opmode) { 4447 case IEEE80211_M_STA: 4448 filter &= ~( 4449 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 4450 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 4451 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 4452 break; 4453 case IEEE80211_M_HOSTAP: 4454 filter &= ~( 4455 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 4456 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP)); 4457 break; 4458 case IEEE80211_M_MONITOR: 4459 case IEEE80211_M_IBSS: 4460 break; 4461 default: 4462 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4463 __func__, vap->iv_opmode); 4464 break; 4465 } 4466 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 4467 4468 /* Reject all control frames. */ 4469 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4470 4471 /* Reject all data frames. */ 4472 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 4473 4474 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 4475 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 4476 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 4477 4478 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 4479 /* Accept all frames. */ 4480 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 4481 R92C_RCR_AAP; 4482 } 4483 4484 /* Set Rx filter. */ 4485 urtwn_write_4(sc, R92C_RCR, rcr); 4486 4487 if (ic->ic_promisc != 0) { 4488 /* Update Rx filter. */ 4489 urtwn_set_promisc(sc); 4490 } 4491} 4492 4493static void 4494urtwn_edca_init(struct urtwn_softc *sc) 4495{ 4496 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4497 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4498 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4499 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4500 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4501 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4502 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4503 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4504} 4505 4506static void 4507urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4508 uint16_t power[URTWN_RIDX_COUNT]) 4509{ 4510 uint32_t reg; 4511 4512 /* Write per-CCK rate Tx power. */ 4513 if (chain == 0) { 4514 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4515 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4516 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4517 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4518 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4519 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4520 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4521 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4522 } else { 4523 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4524 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4525 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4526 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4527 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4528 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4529 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4530 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4531 } 4532 /* Write per-OFDM rate Tx power. */ 4533 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4534 SM(R92C_TXAGC_RATE06, power[ 4]) | 4535 SM(R92C_TXAGC_RATE09, power[ 5]) | 4536 SM(R92C_TXAGC_RATE12, power[ 6]) | 4537 SM(R92C_TXAGC_RATE18, power[ 7])); 4538 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4539 SM(R92C_TXAGC_RATE24, power[ 8]) | 4540 SM(R92C_TXAGC_RATE36, power[ 9]) | 4541 SM(R92C_TXAGC_RATE48, power[10]) | 4542 SM(R92C_TXAGC_RATE54, power[11])); 4543 /* Write per-MCS Tx power. */ 4544 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4545 SM(R92C_TXAGC_MCS00, power[12]) | 4546 SM(R92C_TXAGC_MCS01, power[13]) | 4547 SM(R92C_TXAGC_MCS02, power[14]) | 4548 SM(R92C_TXAGC_MCS03, power[15])); 4549 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4550 SM(R92C_TXAGC_MCS04, power[16]) | 4551 SM(R92C_TXAGC_MCS05, power[17]) | 4552 SM(R92C_TXAGC_MCS06, power[18]) | 4553 SM(R92C_TXAGC_MCS07, power[19])); 4554 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4555 SM(R92C_TXAGC_MCS08, power[20]) | 4556 SM(R92C_TXAGC_MCS09, power[21]) | 4557 SM(R92C_TXAGC_MCS10, power[22]) | 4558 SM(R92C_TXAGC_MCS11, power[23])); 4559 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4560 SM(R92C_TXAGC_MCS12, power[24]) | 4561 SM(R92C_TXAGC_MCS13, power[25]) | 4562 SM(R92C_TXAGC_MCS14, power[26]) | 4563 SM(R92C_TXAGC_MCS15, power[27])); 4564} 4565 4566static void 4567urtwn_get_txpower(struct urtwn_softc *sc, int chain, 4568 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4569 uint16_t power[URTWN_RIDX_COUNT]) 4570{ 4571 struct ieee80211com *ic = &sc->sc_ic; 4572 struct r92c_rom *rom = &sc->rom.r92c_rom; 4573 uint16_t cckpow, ofdmpow, htpow, diff, max; 4574 const struct urtwn_txpwr *base; 4575 int ridx, chan, group; 4576 4577 /* Determine channel group. */ 4578 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4579 if (chan <= 3) 4580 group = 0; 4581 else if (chan <= 9) 4582 group = 1; 4583 else 4584 group = 2; 4585 4586 /* Get original Tx power based on board type and RF chain. */ 4587 if (!(sc->chip & URTWN_CHIP_92C)) { 4588 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4589 base = &rtl8188ru_txagc[chain]; 4590 else 4591 base = &rtl8192cu_txagc[chain]; 4592 } else 4593 base = &rtl8192cu_txagc[chain]; 4594 4595 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4596 if (sc->regulatory == 0) { 4597 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4598 power[ridx] = base->pwr[0][ridx]; 4599 } 4600 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4601 if (sc->regulatory == 3) { 4602 power[ridx] = base->pwr[0][ridx]; 4603 /* Apply vendor limits. */ 4604 if (extc != NULL) 4605 max = rom->ht40_max_pwr[group]; 4606 else 4607 max = rom->ht20_max_pwr[group]; 4608 max = (max >> (chain * 4)) & 0xf; 4609 if (power[ridx] > max) 4610 power[ridx] = max; 4611 } else if (sc->regulatory == 1) { 4612 if (extc == NULL) 4613 power[ridx] = base->pwr[group][ridx]; 4614 } else if (sc->regulatory != 2) 4615 power[ridx] = base->pwr[0][ridx]; 4616 } 4617 4618 /* Compute per-CCK rate Tx power. */ 4619 cckpow = rom->cck_tx_pwr[chain][group]; 4620 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4621 power[ridx] += cckpow; 4622 if (power[ridx] > R92C_MAX_TX_PWR) 4623 power[ridx] = R92C_MAX_TX_PWR; 4624 } 4625 4626 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4627 if (sc->ntxchains > 1) { 4628 /* Apply reduction for 2 spatial streams. */ 4629 diff = rom->ht40_2s_tx_pwr_diff[group]; 4630 diff = (diff >> (chain * 4)) & 0xf; 4631 htpow = (htpow > diff) ? htpow - diff : 0; 4632 } 4633 4634 /* Compute per-OFDM rate Tx power. */ 4635 diff = rom->ofdm_tx_pwr_diff[group]; 4636 diff = (diff >> (chain * 4)) & 0xf; 4637 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4638 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4639 power[ridx] += ofdmpow; 4640 if (power[ridx] > R92C_MAX_TX_PWR) 4641 power[ridx] = R92C_MAX_TX_PWR; 4642 } 4643 4644 /* Compute per-MCS Tx power. */ 4645 if (extc == NULL) { 4646 diff = rom->ht20_tx_pwr_diff[group]; 4647 diff = (diff >> (chain * 4)) & 0xf; 4648 htpow += diff; /* HT40->HT20 correction. */ 4649 } 4650 for (ridx = 12; ridx <= 27; ridx++) { 4651 power[ridx] += htpow; 4652 if (power[ridx] > R92C_MAX_TX_PWR) 4653 power[ridx] = R92C_MAX_TX_PWR; 4654 } 4655#ifdef USB_DEBUG 4656 if (sc->sc_debug & URTWN_DEBUG_TXPWR) { 4657 /* Dump per-rate Tx power values. */ 4658 printf("Tx power for chain %d:\n", chain); 4659 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 4660 printf("Rate %d = %u\n", ridx, power[ridx]); 4661 } 4662#endif 4663} 4664 4665static void 4666urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 4667 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4668 uint16_t power[URTWN_RIDX_COUNT]) 4669{ 4670 struct ieee80211com *ic = &sc->sc_ic; 4671 struct r88e_rom *rom = &sc->rom.r88e_rom; 4672 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4673 const struct urtwn_r88e_txpwr *base; 4674 int ridx, chan, group; 4675 4676 /* Determine channel group. */ 4677 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4678 if (chan <= 2) 4679 group = 0; 4680 else if (chan <= 5) 4681 group = 1; 4682 else if (chan <= 8) 4683 group = 2; 4684 else if (chan <= 11) 4685 group = 3; 4686 else if (chan <= 13) 4687 group = 4; 4688 else 4689 group = 5; 4690 4691 /* Get original Tx power based on board type and RF chain. */ 4692 base = &rtl8188eu_txagc[chain]; 4693 4694 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4695 if (sc->regulatory == 0) { 4696 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4697 power[ridx] = base->pwr[0][ridx]; 4698 } 4699 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4700 if (sc->regulatory == 3) 4701 power[ridx] = base->pwr[0][ridx]; 4702 else if (sc->regulatory == 1) { 4703 if (extc == NULL) 4704 power[ridx] = base->pwr[group][ridx]; 4705 } else if (sc->regulatory != 2) 4706 power[ridx] = base->pwr[0][ridx]; 4707 } 4708 4709 /* Compute per-CCK rate Tx power. */ 4710 cckpow = rom->cck_tx_pwr[group]; 4711 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4712 power[ridx] += cckpow; 4713 if (power[ridx] > R92C_MAX_TX_PWR) 4714 power[ridx] = R92C_MAX_TX_PWR; 4715 } 4716 4717 htpow = rom->ht40_tx_pwr[group]; 4718 4719 /* Compute per-OFDM rate Tx power. */ 4720 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4721 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4722 power[ridx] += ofdmpow; 4723 if (power[ridx] > R92C_MAX_TX_PWR) 4724 power[ridx] = R92C_MAX_TX_PWR; 4725 } 4726 4727 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4728 for (ridx = 12; ridx <= 27; ridx++) { 4729 power[ridx] += bw20pow; 4730 if (power[ridx] > R92C_MAX_TX_PWR) 4731 power[ridx] = R92C_MAX_TX_PWR; 4732 } 4733} 4734 4735static void 4736urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 4737 struct ieee80211_channel *extc) 4738{ 4739 uint16_t power[URTWN_RIDX_COUNT]; 4740 int i; 4741 4742 for (i = 0; i < sc->ntxchains; i++) { 4743 /* Compute per-rate Tx power values. */ 4744 if (sc->chip & URTWN_CHIP_88E) 4745 urtwn_r88e_get_txpower(sc, i, c, extc, power); 4746 else 4747 urtwn_get_txpower(sc, i, c, extc, power); 4748 /* Write per-rate Tx power values to hardware. */ 4749 urtwn_write_txpower(sc, i, power); 4750 } 4751} 4752 4753static void 4754urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 4755{ 4756 uint32_t reg; 4757 4758 reg = urtwn_read_4(sc, R92C_RCR); 4759 if (enable) 4760 reg &= ~R92C_RCR_CBSSID_BCN; 4761 else 4762 reg |= R92C_RCR_CBSSID_BCN; 4763 urtwn_write_4(sc, R92C_RCR, reg); 4764} 4765 4766static void 4767urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 4768{ 4769 uint32_t reg; 4770 4771 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 4772 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4773 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 4774 4775 if (!(sc->chip & URTWN_CHIP_88E)) { 4776 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 4777 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4778 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 4779 } 4780} 4781 4782static void 4783urtwn_scan_start(struct ieee80211com *ic) 4784{ 4785 struct urtwn_softc *sc = ic->ic_softc; 4786 4787 URTWN_LOCK(sc); 4788 /* Receive beacons / probe responses from any BSSID. */ 4789 if (ic->ic_opmode != IEEE80211_M_IBSS && 4790 ic->ic_opmode != IEEE80211_M_HOSTAP) 4791 urtwn_set_rx_bssid_all(sc, 1); 4792 4793 /* Set gain for scanning. */ 4794 urtwn_set_gain(sc, 0x20); 4795 URTWN_UNLOCK(sc); 4796} 4797 4798static void 4799urtwn_scan_end(struct ieee80211com *ic) 4800{ 4801 struct urtwn_softc *sc = ic->ic_softc; 4802 4803 URTWN_LOCK(sc); 4804 /* Restore limitations. */ 4805 if (ic->ic_promisc == 0 && 4806 ic->ic_opmode != IEEE80211_M_IBSS && 4807 ic->ic_opmode != IEEE80211_M_HOSTAP) 4808 urtwn_set_rx_bssid_all(sc, 0); 4809 4810 /* Set gain under link. */ 4811 urtwn_set_gain(sc, 0x32); 4812 URTWN_UNLOCK(sc); 4813} 4814 4815static void 4816urtwn_getradiocaps(struct ieee80211com *ic, 4817 int maxchans, int *nchans, struct ieee80211_channel chans[]) 4818{ 4819 uint8_t bands[IEEE80211_MODE_BYTES]; 4820 4821 memset(bands, 0, sizeof(bands)); 4822 setbit(bands, IEEE80211_MODE_11B); 4823 setbit(bands, IEEE80211_MODE_11G); 4824 if (urtwn_enable_11n) 4825 setbit(bands, IEEE80211_MODE_11NG); 4826 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 4827 urtwn_chan_2ghz, nitems(urtwn_chan_2ghz), bands, 0); 4828} 4829 4830static void 4831urtwn_set_channel(struct ieee80211com *ic) 4832{ 4833 struct urtwn_softc *sc = ic->ic_softc; 4834 struct ieee80211_channel *c = ic->ic_curchan; 4835 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4836 4837 URTWN_LOCK(sc); 4838 if (vap->iv_state == IEEE80211_S_SCAN) { 4839 /* Make link LED blink during scan. */ 4840 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 4841 } 4842 urtwn_set_chan(sc, c, NULL); 4843 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 4844 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 4845 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 4846 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 4847 URTWN_UNLOCK(sc); 4848} 4849 4850static int 4851urtwn_wme_update(struct ieee80211com *ic) 4852{ 4853 const struct wmeParams *wmep = 4854 ic->ic_wme.wme_chanParams.cap_wmeParams; 4855 struct urtwn_softc *sc = ic->ic_softc; 4856 uint8_t aifs, acm, slottime; 4857 int ac; 4858 4859 acm = 0; 4860 slottime = IEEE80211_GET_SLOTTIME(ic); 4861 4862 URTWN_LOCK(sc); 4863 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4864 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4865 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4866 urtwn_write_4(sc, wme2queue[ac].reg, 4867 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 4868 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 4869 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 4870 SM(R92C_EDCA_PARAM_AIFS, aifs)); 4871 if (ac != WME_AC_BE) 4872 acm |= wmep[ac].wmep_acm << ac; 4873 } 4874 4875 if (acm != 0) 4876 acm |= R92C_ACMHWCTRL_EN; 4877 urtwn_write_1(sc, R92C_ACMHWCTRL, 4878 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 4879 acm); 4880 4881 URTWN_UNLOCK(sc); 4882 4883 return 0; 4884} 4885 4886static void 4887urtwn_update_slot(struct ieee80211com *ic) 4888{ 4889 urtwn_cmd_sleepable(ic->ic_softc, NULL, 0, urtwn_update_slot_cb); 4890} 4891 4892static void 4893urtwn_update_slot_cb(struct urtwn_softc *sc, union sec_param *data) 4894{ 4895 struct ieee80211com *ic = &sc->sc_ic; 4896 uint8_t slottime; 4897 4898 slottime = IEEE80211_GET_SLOTTIME(ic); 4899 4900 URTWN_DPRINTF(sc, URTWN_DEBUG_ANY, "%s: setting slot time to %uus\n", 4901 __func__, slottime); 4902 4903 urtwn_write_1(sc, R92C_SLOT, slottime); 4904 urtwn_update_aifs(sc, slottime); 4905} 4906 4907static void 4908urtwn_update_aifs(struct urtwn_softc *sc, uint8_t slottime) 4909{ 4910 const struct wmeParams *wmep = 4911 sc->sc_ic.ic_wme.wme_chanParams.cap_wmeParams; 4912 uint8_t aifs, ac; 4913 4914 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4915 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4916 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4917 urtwn_write_1(sc, wme2queue[ac].reg, aifs); 4918 } 4919} 4920 4921static uint8_t 4922urtwn_get_multi_pos(const uint8_t maddr[]) 4923{ 4924 uint64_t mask = 0x00004d101df481b4; 4925 uint8_t pos = 0x27; /* initial value */ 4926 int i, j; 4927 4928 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 4929 for (j = (i == 0) ? 1 : 0; j < 8; j++) 4930 if ((maddr[i] >> j) & 1) 4931 pos ^= (mask >> (i * 8 + j - 1)); 4932 4933 pos &= 0x3f; 4934 4935 return (pos); 4936} 4937 4938static void 4939urtwn_set_multi(struct urtwn_softc *sc) 4940{ 4941 struct ieee80211com *ic = &sc->sc_ic; 4942 uint32_t mfilt[2]; 4943 4944 URTWN_ASSERT_LOCKED(sc); 4945 4946 /* general structure was copied from ath(4). */ 4947 if (ic->ic_allmulti == 0) { 4948 struct ieee80211vap *vap; 4949 struct ifnet *ifp; 4950 struct ifmultiaddr *ifma; 4951 4952 /* 4953 * Merge multicast addresses to form the hardware filter. 4954 */ 4955 mfilt[0] = mfilt[1] = 0; 4956 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 4957 ifp = vap->iv_ifp; 4958 if_maddr_rlock(ifp); 4959 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4960 caddr_t dl; 4961 uint8_t pos; 4962 4963 dl = LLADDR((struct sockaddr_dl *) 4964 ifma->ifma_addr); 4965 pos = urtwn_get_multi_pos(dl); 4966 4967 mfilt[pos / 32] |= (1 << (pos % 32)); 4968 } 4969 if_maddr_runlock(ifp); 4970 } 4971 } else 4972 mfilt[0] = mfilt[1] = ~0; 4973 4974 4975 urtwn_write_4(sc, R92C_MAR + 0, mfilt[0]); 4976 urtwn_write_4(sc, R92C_MAR + 4, mfilt[1]); 4977 4978 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s: MC filter %08x:%08x\n", 4979 __func__, mfilt[0], mfilt[1]); 4980} 4981 4982static void 4983urtwn_set_promisc(struct urtwn_softc *sc) 4984{ 4985 struct ieee80211com *ic = &sc->sc_ic; 4986 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4987 uint32_t rcr, mask1, mask2; 4988 4989 URTWN_ASSERT_LOCKED(sc); 4990 4991 if (vap->iv_opmode == IEEE80211_M_MONITOR) 4992 return; 4993 4994 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 4995 mask2 = R92C_RCR_APM; 4996 4997 if (vap->iv_state == IEEE80211_S_RUN) { 4998 switch (vap->iv_opmode) { 4999 case IEEE80211_M_STA: 5000 mask2 |= R92C_RCR_CBSSID_BCN; 5001 /* FALLTHROUGH */ 5002 case IEEE80211_M_IBSS: 5003 mask2 |= R92C_RCR_CBSSID_DATA; 5004 break; 5005 case IEEE80211_M_HOSTAP: 5006 break; 5007 default: 5008 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 5009 __func__, vap->iv_opmode); 5010 return; 5011 } 5012 } 5013 5014 rcr = urtwn_read_4(sc, R92C_RCR); 5015 if (ic->ic_promisc == 0) 5016 rcr = (rcr & ~mask1) | mask2; 5017 else 5018 rcr = (rcr & ~mask2) | mask1; 5019 urtwn_write_4(sc, R92C_RCR, rcr); 5020} 5021 5022static void 5023urtwn_update_promisc(struct ieee80211com *ic) 5024{ 5025 struct urtwn_softc *sc = ic->ic_softc; 5026 5027 URTWN_LOCK(sc); 5028 if (sc->sc_flags & URTWN_RUNNING) 5029 urtwn_set_promisc(sc); 5030 URTWN_UNLOCK(sc); 5031} 5032 5033static void 5034urtwn_update_mcast(struct ieee80211com *ic) 5035{ 5036 struct urtwn_softc *sc = ic->ic_softc; 5037 5038 URTWN_LOCK(sc); 5039 if (sc->sc_flags & URTWN_RUNNING) 5040 urtwn_set_multi(sc); 5041 URTWN_UNLOCK(sc); 5042} 5043 5044static struct ieee80211_node * 5045urtwn_node_alloc(struct ieee80211vap *vap, 5046 const uint8_t mac[IEEE80211_ADDR_LEN]) 5047{ 5048 struct urtwn_node *un; 5049 5050 un = malloc(sizeof (struct urtwn_node), M_80211_NODE, 5051 M_NOWAIT | M_ZERO); 5052 5053 if (un == NULL) 5054 return NULL; 5055 5056 un->id = URTWN_MACID_UNDEFINED; 5057 5058 return &un->ni; 5059} 5060 5061static void 5062urtwn_newassoc(struct ieee80211_node *ni, int isnew) 5063{ 5064 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 5065 struct urtwn_node *un = URTWN_NODE(ni); 5066 uint8_t id; 5067 5068 /* Only do this bit for R88E chips */ 5069 if (! (sc->chip & URTWN_CHIP_88E)) 5070 return; 5071 5072 if (!isnew) 5073 return; 5074 5075 URTWN_NT_LOCK(sc); 5076 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 5077 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 5078 un->id = id; 5079 sc->node_list[id] = ni; 5080 break; 5081 } 5082 } 5083 URTWN_NT_UNLOCK(sc); 5084 5085 if (id > URTWN_MACID_MAX(sc)) { 5086 device_printf(sc->sc_dev, "%s: node table is full\n", 5087 __func__); 5088 } 5089} 5090 5091static void 5092urtwn_node_free(struct ieee80211_node *ni) 5093{ 5094 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 5095 struct urtwn_node *un = URTWN_NODE(ni); 5096 5097 URTWN_NT_LOCK(sc); 5098 if (un->id != URTWN_MACID_UNDEFINED) 5099 sc->node_list[un->id] = NULL; 5100 URTWN_NT_UNLOCK(sc); 5101 5102 sc->sc_node_free(ni); 5103} 5104 5105static void 5106urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 5107 struct ieee80211_channel *extc) 5108{ 5109 struct ieee80211com *ic = &sc->sc_ic; 5110 uint32_t reg; 5111 u_int chan; 5112 int i; 5113 5114 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 5115 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 5116 device_printf(sc->sc_dev, 5117 "%s: invalid channel %x\n", __func__, chan); 5118 return; 5119 } 5120 5121 /* Set Tx power for this new channel. */ 5122 urtwn_set_txpower(sc, c, extc); 5123 5124 for (i = 0; i < sc->nrxchains; i++) { 5125 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 5126 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 5127 } 5128#ifndef IEEE80211_NO_HT 5129 if (extc != NULL) { 5130 /* Is secondary channel below or above primary? */ 5131 int prichlo = c->ic_freq < extc->ic_freq; 5132 5133 urtwn_write_1(sc, R92C_BWOPMODE, 5134 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 5135 5136 reg = urtwn_read_1(sc, R92C_RRSR + 2); 5137 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 5138 urtwn_write_1(sc, R92C_RRSR + 2, reg); 5139 5140 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5141 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 5142 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5143 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 5144 5145 /* Set CCK side band. */ 5146 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 5147 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 5148 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 5149 5150 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 5151 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 5152 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 5153 5154 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5155 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 5156 ~R92C_FPGA0_ANAPARAM2_CBW20); 5157 5158 reg = urtwn_bb_read(sc, 0x818); 5159 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 5160 urtwn_bb_write(sc, 0x818, reg); 5161 5162 /* Select 40MHz bandwidth. */ 5163 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5164 (sc->rf_chnlbw[0] & ~0xfff) | chan); 5165 } else 5166#endif 5167 { 5168 urtwn_write_1(sc, R92C_BWOPMODE, 5169 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 5170 5171 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 5172 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 5173 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 5174 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 5175 5176 if (!(sc->chip & URTWN_CHIP_88E)) { 5177 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 5178 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 5179 R92C_FPGA0_ANAPARAM2_CBW20); 5180 } 5181 5182 /* Select 20MHz bandwidth. */ 5183 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5184 (sc->rf_chnlbw[0] & ~0xfff) | chan | 5185 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 5186 R92C_RF_CHNLBW_BW20)); 5187 } 5188} 5189 5190static void 5191urtwn_iq_calib(struct urtwn_softc *sc) 5192{ 5193 /* TODO */ 5194} 5195 5196static void 5197urtwn_lc_calib(struct urtwn_softc *sc) 5198{ 5199 uint32_t rf_ac[2]; 5200 uint8_t txmode; 5201 int i; 5202 5203 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 5204 if ((txmode & 0x70) != 0) { 5205 /* Disable all continuous Tx. */ 5206 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 5207 5208 /* Set RF mode to standby mode. */ 5209 for (i = 0; i < sc->nrxchains; i++) { 5210 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 5211 urtwn_rf_write(sc, i, R92C_RF_AC, 5212 RW(rf_ac[i], R92C_RF_AC_MODE, 5213 R92C_RF_AC_MODE_STANDBY)); 5214 } 5215 } else { 5216 /* Block all Tx queues. */ 5217 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 5218 } 5219 /* Start calibration. */ 5220 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 5221 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 5222 5223 /* Give calibration the time to complete. */ 5224 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 5225 5226 /* Restore configuration. */ 5227 if ((txmode & 0x70) != 0) { 5228 /* Restore Tx mode. */ 5229 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 5230 /* Restore RF mode. */ 5231 for (i = 0; i < sc->nrxchains; i++) 5232 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 5233 } else { 5234 /* Unblock all Tx queues. */ 5235 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 5236 } 5237} 5238 5239static void 5240urtwn_temp_calib(struct urtwn_softc *sc) 5241{ 5242 uint8_t temp; 5243 5244 URTWN_ASSERT_LOCKED(sc); 5245 5246 if (!(sc->sc_flags & URTWN_TEMP_MEASURED)) { 5247 /* Start measuring temperature. */ 5248 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5249 "%s: start measuring temperature\n", __func__); 5250 if (sc->chip & URTWN_CHIP_88E) { 5251 urtwn_rf_write(sc, 0, R88E_RF_T_METER, 5252 R88E_RF_T_METER_START); 5253 } else { 5254 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 5255 R92C_RF_T_METER_START); 5256 } 5257 sc->sc_flags |= URTWN_TEMP_MEASURED; 5258 return; 5259 } 5260 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 5261 5262 /* Read measured temperature. */ 5263 if (sc->chip & URTWN_CHIP_88E) { 5264 temp = MS(urtwn_rf_read(sc, 0, R88E_RF_T_METER), 5265 R88E_RF_T_METER_VAL); 5266 } else { 5267 temp = MS(urtwn_rf_read(sc, 0, R92C_RF_T_METER), 5268 R92C_RF_T_METER_VAL); 5269 } 5270 if (temp == 0) { /* Read failed, skip. */ 5271 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5272 "%s: temperature read failed, skipping\n", __func__); 5273 return; 5274 } 5275 5276 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5277 "%s: temperature: previous %u, current %u\n", 5278 __func__, sc->thcal_lctemp, temp); 5279 5280 /* 5281 * Redo LC calibration if temperature changed significantly since 5282 * last calibration. 5283 */ 5284 if (sc->thcal_lctemp == 0) { 5285 /* First LC calibration is performed in urtwn_init(). */ 5286 sc->thcal_lctemp = temp; 5287 } else if (abs(temp - sc->thcal_lctemp) > 1) { 5288 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 5289 "%s: LC calib triggered by temp: %u -> %u\n", 5290 __func__, sc->thcal_lctemp, temp); 5291 urtwn_lc_calib(sc); 5292 /* Record temperature of last LC calibration. */ 5293 sc->thcal_lctemp = temp; 5294 } 5295} 5296 5297static void 5298urtwn_setup_static_keys(struct urtwn_softc *sc, struct urtwn_vap *uvp) 5299{ 5300 int i; 5301 5302 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 5303 const struct ieee80211_key *k = uvp->keys[i]; 5304 if (k != NULL) { 5305 urtwn_cmd_sleepable(sc, k, sizeof(*k), 5306 urtwn_key_set_cb); 5307 } 5308 } 5309} 5310 5311static int 5312urtwn_init(struct urtwn_softc *sc) 5313{ 5314 struct ieee80211com *ic = &sc->sc_ic; 5315 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5316 uint8_t macaddr[IEEE80211_ADDR_LEN]; 5317 uint32_t reg; 5318 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 5319 int error; 5320 5321 URTWN_LOCK(sc); 5322 if (sc->sc_flags & URTWN_RUNNING) { 5323 URTWN_UNLOCK(sc); 5324 return (0); 5325 } 5326 5327 /* Init firmware commands ring. */ 5328 sc->fwcur = 0; 5329 5330 /* Allocate Tx/Rx buffers. */ 5331 error = urtwn_alloc_rx_list(sc); 5332 if (error != 0) 5333 goto fail; 5334 5335 error = urtwn_alloc_tx_list(sc); 5336 if (error != 0) 5337 goto fail; 5338 5339 /* Power on adapter. */ 5340 error = urtwn_power_on(sc); 5341 if (error != 0) 5342 goto fail; 5343 5344 /* Initialize DMA. */ 5345 error = urtwn_dma_init(sc); 5346 if (error != 0) 5347 goto fail; 5348 5349 /* Set info size in Rx descriptors (in 64-bit words). */ 5350 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 5351 5352 /* Init interrupts. */ 5353 if (sc->chip & URTWN_CHIP_88E) { 5354 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 5355 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5356 goto fail; 5357 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 5358 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 5359 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5360 goto fail; 5361 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 5362 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 5363 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5364 goto fail; 5365 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5366 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5367 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 5368 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5369 goto fail; 5370 } else { 5371 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 5372 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5373 goto fail; 5374 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 5375 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5376 goto fail; 5377 } 5378 5379 /* Set MAC address. */ 5380 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 5381 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 5382 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5383 goto fail; 5384 5385 /* Set initial network type. */ 5386 urtwn_set_mode(sc, R92C_MSR_INFRA); 5387 5388 /* Initialize Rx filter. */ 5389 urtwn_rxfilter_init(sc); 5390 5391 /* Set response rate. */ 5392 reg = urtwn_read_4(sc, R92C_RRSR); 5393 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5394 urtwn_write_4(sc, R92C_RRSR, reg); 5395 5396 /* Set short/long retry limits. */ 5397 urtwn_write_2(sc, R92C_RL, 5398 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5399 5400 /* Initialize EDCA parameters. */ 5401 urtwn_edca_init(sc); 5402 5403 /* Setup rate fallback. */ 5404 if (!(sc->chip & URTWN_CHIP_88E)) { 5405 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5406 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5407 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5408 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5409 } 5410 5411 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5412 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5413 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5414 /* Set ACK timeout. */ 5415 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5416 5417 /* Setup USB aggregation. */ 5418 reg = urtwn_read_4(sc, R92C_TDECTRL); 5419 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5420 urtwn_write_4(sc, R92C_TDECTRL, reg); 5421 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5422 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5423 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5424 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5425 if (sc->chip & URTWN_CHIP_88E) 5426 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5427 else { 5428 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5429 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5430 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5431 R92C_USB_SPECIAL_OPTION_AGG_EN); 5432 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 5433 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 5434 } 5435 5436 /* Initialize beacon parameters. */ 5437 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5438 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5439 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 5440 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 5441 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5442 5443 if (!(sc->chip & URTWN_CHIP_88E)) { 5444 /* Setup AMPDU aggregation. */ 5445 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5446 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5447 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 5448 5449 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5450 } 5451 5452#ifndef URTWN_WITHOUT_UCODE 5453 /* Load 8051 microcode. */ 5454 error = urtwn_load_firmware(sc); 5455 if (error == 0) 5456 sc->sc_flags |= URTWN_FW_LOADED; 5457#endif 5458 5459 /* Initialize MAC/BB/RF blocks. */ 5460 error = urtwn_mac_init(sc); 5461 if (error != 0) { 5462 device_printf(sc->sc_dev, 5463 "%s: error while initializing MAC block\n", __func__); 5464 goto fail; 5465 } 5466 urtwn_bb_init(sc); 5467 urtwn_rf_init(sc); 5468 5469 /* Reinitialize Rx filter (D3845 is not committed yet). */ 5470 urtwn_rxfilter_init(sc); 5471 5472 if (sc->chip & URTWN_CHIP_88E) { 5473 urtwn_write_2(sc, R92C_CR, 5474 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5475 R92C_CR_MACRXEN); 5476 } 5477 5478 /* Turn CCK and OFDM blocks on. */ 5479 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5480 reg |= R92C_RFMOD_CCK_EN; 5481 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5482 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5483 goto fail; 5484 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5485 reg |= R92C_RFMOD_OFDM_EN; 5486 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5487 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5488 goto fail; 5489 5490 /* Clear per-station keys table. */ 5491 urtwn_cam_init(sc); 5492 5493 /* Enable decryption / encryption. */ 5494 urtwn_write_2(sc, R92C_SECCFG, 5495 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 5496 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA | 5497 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 5498 5499 /* Enable hardware sequence numbering. */ 5500 urtwn_write_1(sc, R92C_HWSEQ_CTRL, R92C_TX_QUEUE_ALL); 5501 5502 /* Enable per-packet TX report. */ 5503 if (sc->chip & URTWN_CHIP_88E) { 5504 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 5505 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 5506 } 5507 5508 /* Perform LO and IQ calibrations. */ 5509 urtwn_iq_calib(sc); 5510 /* Perform LC calibration. */ 5511 urtwn_lc_calib(sc); 5512 5513 /* Fix USB interference issue. */ 5514 if (!(sc->chip & URTWN_CHIP_88E)) { 5515 urtwn_write_1(sc, 0xfe40, 0xe0); 5516 urtwn_write_1(sc, 0xfe41, 0x8d); 5517 urtwn_write_1(sc, 0xfe42, 0x80); 5518 5519 urtwn_pa_bias_init(sc); 5520 } 5521 5522 /* Initialize GPIO setting. */ 5523 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5524 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5525 5526 /* Fix for lower temperature. */ 5527 if (!(sc->chip & URTWN_CHIP_88E)) 5528 urtwn_write_1(sc, 0x15, 0xe9); 5529 5530 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 5531 5532 sc->sc_flags |= URTWN_RUNNING; 5533 5534 /* 5535 * Install static keys (if any). 5536 * Must be called after urtwn_cam_init(). 5537 */ 5538 if (vap != NULL) 5539 urtwn_setup_static_keys(sc, URTWN_VAP(vap)); 5540 5541 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5542fail: 5543 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5544 error = EIO; 5545 5546 URTWN_UNLOCK(sc); 5547 5548 return (error); 5549} 5550 5551static void 5552urtwn_stop(struct urtwn_softc *sc) 5553{ 5554 5555 URTWN_LOCK(sc); 5556 if (!(sc->sc_flags & URTWN_RUNNING)) { 5557 URTWN_UNLOCK(sc); 5558 return; 5559 } 5560 5561 sc->sc_flags &= ~(URTWN_RUNNING | URTWN_FW_LOADED | 5562 URTWN_TEMP_MEASURED); 5563 sc->thcal_lctemp = 0; 5564 callout_stop(&sc->sc_watchdog_ch); 5565 5566 urtwn_abort_xfers(sc); 5567 urtwn_drain_mbufq(sc); 5568 urtwn_free_tx_list(sc); 5569 urtwn_free_rx_list(sc); 5570 urtwn_power_off(sc); 5571 URTWN_UNLOCK(sc); 5572} 5573 5574static void 5575urtwn_abort_xfers(struct urtwn_softc *sc) 5576{ 5577 int i; 5578 5579 URTWN_ASSERT_LOCKED(sc); 5580 5581 /* abort any pending transfers */ 5582 for (i = 0; i < URTWN_N_TRANSFER; i++) 5583 usbd_transfer_stop(sc->sc_xfer[i]); 5584} 5585 5586static int 5587urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5588 const struct ieee80211_bpf_params *params) 5589{ 5590 struct ieee80211com *ic = ni->ni_ic; 5591 struct urtwn_softc *sc = ic->ic_softc; 5592 struct urtwn_data *bf; 5593 int error; 5594 5595 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: called; m=%p\n", 5596 __func__, 5597 m); 5598 5599 /* prevent management frames from being sent if we're not ready */ 5600 URTWN_LOCK(sc); 5601 if (!(sc->sc_flags & URTWN_RUNNING)) { 5602 error = ENETDOWN; 5603 goto end; 5604 } 5605 5606 bf = urtwn_getbuf(sc); 5607 if (bf == NULL) { 5608 error = ENOBUFS; 5609 goto end; 5610 } 5611 5612 if (params == NULL) { 5613 /* 5614 * Legacy path; interpret frame contents to decide 5615 * precisely how to send the frame. 5616 */ 5617 error = urtwn_tx_data(sc, ni, m, bf); 5618 } else { 5619 /* 5620 * Caller supplied explicit parameters to use in 5621 * sending the frame. 5622 */ 5623 error = urtwn_tx_raw(sc, ni, m, bf, params); 5624 } 5625 if (error != 0) { 5626 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 5627 goto end; 5628 } 5629 5630 sc->sc_txtimer = 5; 5631 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5632 5633end: 5634 if (error != 0) 5635 m_freem(m); 5636 5637 URTWN_UNLOCK(sc); 5638 5639 return (error); 5640} 5641 5642static void 5643urtwn_ms_delay(struct urtwn_softc *sc) 5644{ 5645 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 5646} 5647 5648static device_method_t urtwn_methods[] = { 5649 /* Device interface */ 5650 DEVMETHOD(device_probe, urtwn_match), 5651 DEVMETHOD(device_attach, urtwn_attach), 5652 DEVMETHOD(device_detach, urtwn_detach), 5653 5654 DEVMETHOD_END 5655}; 5656 5657static driver_t urtwn_driver = { 5658 "urtwn", 5659 urtwn_methods, 5660 sizeof(struct urtwn_softc) 5661}; 5662 5663static devclass_t urtwn_devclass; 5664 5665DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 5666MODULE_DEPEND(urtwn, usb, 1, 1, 1); 5667MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 5668#ifndef URTWN_WITHOUT_UCODE 5669MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 5670#endif 5671MODULE_VERSION(urtwn, 1); 5672USB_PNP_HOST_INFO(urtwn_devs); 5673