if_urtwn.c revision 296174
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2015 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#include <sys/cdefs.h> 22__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 296174 2016-02-29 00:05:37Z avos $"); 23 24/* 25 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 26 */ 27 28#include "opt_wlan.h" 29#include "opt_urtwn.h" 30 31#include <sys/param.h> 32#include <sys/sockio.h> 33#include <sys/sysctl.h> 34#include <sys/lock.h> 35#include <sys/mutex.h> 36#include <sys/condvar.h> 37#include <sys/mbuf.h> 38#include <sys/kernel.h> 39#include <sys/socket.h> 40#include <sys/systm.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/bus.h> 44#include <sys/endian.h> 45#include <sys/linker.h> 46#include <sys/firmware.h> 47#include <sys/kdb.h> 48 49#include <machine/bus.h> 50#include <machine/resource.h> 51#include <sys/rman.h> 52 53#include <net/bpf.h> 54#include <net/if.h> 55#include <net/if_var.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61 62#include <netinet/in.h> 63#include <netinet/in_systm.h> 64#include <netinet/in_var.h> 65#include <netinet/if_ether.h> 66#include <netinet/ip.h> 67 68#include <net80211/ieee80211_var.h> 69#include <net80211/ieee80211_input.h> 70#include <net80211/ieee80211_regdomain.h> 71#include <net80211/ieee80211_radiotap.h> 72#include <net80211/ieee80211_ratectl.h> 73 74#include <dev/usb/usb.h> 75#include <dev/usb/usbdi.h> 76#include <dev/usb/usb_device.h> 77#include "usbdevs.h" 78 79#include <dev/usb/usb_debug.h> 80 81#include <dev/usb/wlan/if_urtwnreg.h> 82#include <dev/usb/wlan/if_urtwnvar.h> 83 84#ifdef USB_DEBUG 85enum { 86 URTWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 87 URTWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 88 URTWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 89 URTWN_DEBUG_RA = 0x00000008, /* f/w rate adaptation setup */ 90 URTWN_DEBUG_USB = 0x00000010, /* usb requests */ 91 URTWN_DEBUG_FIRMWARE = 0x00000020, /* firmware(9) loading debug */ 92 URTWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 93 URTWN_DEBUG_INTR = 0x00000080, /* ISR */ 94 URTWN_DEBUG_TEMP = 0x00000100, /* temperature calibration */ 95 URTWN_DEBUG_ROM = 0x00000200, /* various ROM info */ 96 URTWN_DEBUG_KEY = 0x00000400, /* crypto keys management */ 97 URTWN_DEBUG_TXPWR = 0x00000800, /* dump Tx power values */ 98 URTWN_DEBUG_ANY = 0xffffffff 99}; 100 101#define URTWN_DPRINTF(_sc, _m, ...) do { \ 102 if ((_sc)->sc_debug & (_m)) \ 103 device_printf((_sc)->sc_dev, __VA_ARGS__); \ 104} while(0) 105 106#else 107#define URTWN_DPRINTF(_sc, _m, ...) do { (void) sc; } while (0) 108#endif 109 110#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 111 112/* various supported device vendors/products */ 113static const STRUCT_USB_HOST_ID urtwn_devs[] = { 114#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 115#define URTWN_RTL8188E_DEV(v,p) \ 116 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 117#define URTWN_RTL8188E 1 118 URTWN_DEV(ABOCOM, RTL8188CU_1), 119 URTWN_DEV(ABOCOM, RTL8188CU_2), 120 URTWN_DEV(ABOCOM, RTL8192CU), 121 URTWN_DEV(ASUS, RTL8192CU), 122 URTWN_DEV(ASUS, USBN10NANO), 123 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 124 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 125 URTWN_DEV(AZUREWAVE, RTL8188CU), 126 URTWN_DEV(BELKIN, F7D2102), 127 URTWN_DEV(BELKIN, RTL8188CU), 128 URTWN_DEV(BELKIN, RTL8192CU), 129 URTWN_DEV(CHICONY, RTL8188CUS_1), 130 URTWN_DEV(CHICONY, RTL8188CUS_2), 131 URTWN_DEV(CHICONY, RTL8188CUS_3), 132 URTWN_DEV(CHICONY, RTL8188CUS_4), 133 URTWN_DEV(CHICONY, RTL8188CUS_5), 134 URTWN_DEV(COREGA, RTL8192CU), 135 URTWN_DEV(DLINK, RTL8188CU), 136 URTWN_DEV(DLINK, RTL8192CU_1), 137 URTWN_DEV(DLINK, RTL8192CU_2), 138 URTWN_DEV(DLINK, RTL8192CU_3), 139 URTWN_DEV(DLINK, DWA131B), 140 URTWN_DEV(EDIMAX, EW7811UN), 141 URTWN_DEV(EDIMAX, RTL8192CU), 142 URTWN_DEV(FEIXUN, RTL8188CU), 143 URTWN_DEV(FEIXUN, RTL8192CU), 144 URTWN_DEV(GUILLEMOT, HWNUP150), 145 URTWN_DEV(HAWKING, RTL8192CU), 146 URTWN_DEV(HP3, RTL8188CU), 147 URTWN_DEV(NETGEAR, WNA1000M), 148 URTWN_DEV(NETGEAR, RTL8192CU), 149 URTWN_DEV(NETGEAR4, RTL8188CU), 150 URTWN_DEV(NOVATECH, RTL8188CU), 151 URTWN_DEV(PLANEX2, RTL8188CU_1), 152 URTWN_DEV(PLANEX2, RTL8188CU_2), 153 URTWN_DEV(PLANEX2, RTL8188CU_3), 154 URTWN_DEV(PLANEX2, RTL8188CU_4), 155 URTWN_DEV(PLANEX2, RTL8188CUS), 156 URTWN_DEV(PLANEX2, RTL8192CU), 157 URTWN_DEV(REALTEK, RTL8188CE_0), 158 URTWN_DEV(REALTEK, RTL8188CE_1), 159 URTWN_DEV(REALTEK, RTL8188CTV), 160 URTWN_DEV(REALTEK, RTL8188CU_0), 161 URTWN_DEV(REALTEK, RTL8188CU_1), 162 URTWN_DEV(REALTEK, RTL8188CU_2), 163 URTWN_DEV(REALTEK, RTL8188CU_3), 164 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 165 URTWN_DEV(REALTEK, RTL8188CUS), 166 URTWN_DEV(REALTEK, RTL8188RU_1), 167 URTWN_DEV(REALTEK, RTL8188RU_2), 168 URTWN_DEV(REALTEK, RTL8188RU_3), 169 URTWN_DEV(REALTEK, RTL8191CU), 170 URTWN_DEV(REALTEK, RTL8192CE), 171 URTWN_DEV(REALTEK, RTL8192CU), 172 URTWN_DEV(SITECOMEU, RTL8188CU_1), 173 URTWN_DEV(SITECOMEU, RTL8188CU_2), 174 URTWN_DEV(SITECOMEU, RTL8192CU), 175 URTWN_DEV(TRENDNET, RTL8188CU), 176 URTWN_DEV(TRENDNET, RTL8192CU), 177 URTWN_DEV(ZYXEL, RTL8192CU), 178 /* URTWN_RTL8188E */ 179 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 180 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 181 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 182 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 183 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 184 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 185#undef URTWN_RTL8188E_DEV 186#undef URTWN_DEV 187}; 188 189static device_probe_t urtwn_match; 190static device_attach_t urtwn_attach; 191static device_detach_t urtwn_detach; 192 193static usb_callback_t urtwn_bulk_tx_callback; 194static usb_callback_t urtwn_bulk_rx_callback; 195 196static void urtwn_sysctlattach(struct urtwn_softc *); 197static void urtwn_drain_mbufq(struct urtwn_softc *); 198static usb_error_t urtwn_do_request(struct urtwn_softc *, 199 struct usb_device_request *, void *); 200static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 201 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 202 const uint8_t [IEEE80211_ADDR_LEN], 203 const uint8_t [IEEE80211_ADDR_LEN]); 204static void urtwn_vap_delete(struct ieee80211vap *); 205static struct mbuf * urtwn_rx_copy_to_mbuf(struct urtwn_softc *, 206 struct r92c_rx_stat *, int); 207static struct mbuf * urtwn_report_intr(struct usb_xfer *, 208 struct urtwn_data *); 209static struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int); 210static void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 211 void *); 212static struct ieee80211_node *urtwn_rx_frame(struct urtwn_softc *, 213 struct mbuf *, int8_t *); 214static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 215 int); 216static int urtwn_alloc_list(struct urtwn_softc *, 217 struct urtwn_data[], int, int); 218static int urtwn_alloc_rx_list(struct urtwn_softc *); 219static int urtwn_alloc_tx_list(struct urtwn_softc *); 220static void urtwn_free_list(struct urtwn_softc *, 221 struct urtwn_data data[], int); 222static void urtwn_free_rx_list(struct urtwn_softc *); 223static void urtwn_free_tx_list(struct urtwn_softc *); 224static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 225static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 226static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 227 uint8_t *, int); 228static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 229static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 230static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 231static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 232 uint8_t *, int); 233static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 234static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 235static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 236static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 237 const void *, int); 238static void urtwn_cmdq_cb(void *, int); 239static int urtwn_cmd_sleepable(struct urtwn_softc *, const void *, 240 size_t, CMD_FUNC_PROTO); 241static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 242 uint8_t, uint32_t); 243static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 244 uint8_t, uint32_t); 245static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 246static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 247 uint32_t); 248static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 249static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 250 uint8_t, uint8_t); 251#ifdef USB_DEBUG 252static void urtwn_dump_rom_contents(struct urtwn_softc *, 253 uint8_t *, uint16_t); 254#endif 255static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 256 uint16_t); 257static int urtwn_efuse_switch_power(struct urtwn_softc *); 258static int urtwn_read_chipid(struct urtwn_softc *); 259static int urtwn_read_rom(struct urtwn_softc *); 260static int urtwn_r88e_read_rom(struct urtwn_softc *); 261static int urtwn_ra_init(struct urtwn_softc *); 262static void urtwn_init_beacon(struct urtwn_softc *, 263 struct urtwn_vap *); 264static int urtwn_setup_beacon(struct urtwn_softc *, 265 struct ieee80211_node *); 266static void urtwn_update_beacon(struct ieee80211vap *, int); 267static int urtwn_tx_beacon(struct urtwn_softc *sc, 268 struct urtwn_vap *); 269static int urtwn_key_alloc(struct ieee80211vap *, 270 struct ieee80211_key *, ieee80211_keyix *, 271 ieee80211_keyix *); 272static void urtwn_key_set_cb(struct urtwn_softc *, 273 union sec_param *); 274static void urtwn_key_del_cb(struct urtwn_softc *, 275 union sec_param *); 276static int urtwn_key_set(struct ieee80211vap *, 277 const struct ieee80211_key *); 278static int urtwn_key_delete(struct ieee80211vap *, 279 const struct ieee80211_key *); 280static void urtwn_tsf_task_adhoc(void *, int); 281static void urtwn_tsf_sync_enable(struct urtwn_softc *, 282 struct ieee80211vap *); 283static void urtwn_get_tsf(struct urtwn_softc *, uint64_t *); 284static void urtwn_set_led(struct urtwn_softc *, int, int); 285static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 286static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 287 struct mbuf *, int, 288 const struct ieee80211_rx_stats *, int, int); 289static int urtwn_newstate(struct ieee80211vap *, 290 enum ieee80211_state, int); 291static void urtwn_calib_to(void *); 292static void urtwn_calib_cb(struct urtwn_softc *, 293 union sec_param *); 294static void urtwn_watchdog(void *); 295static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 296static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 297static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 298static int urtwn_tx_data(struct urtwn_softc *, 299 struct ieee80211_node *, struct mbuf *, 300 struct urtwn_data *); 301static int urtwn_tx_raw(struct urtwn_softc *, 302 struct ieee80211_node *, struct mbuf *, 303 struct urtwn_data *, 304 const struct ieee80211_bpf_params *); 305static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 306 uint8_t, struct urtwn_data *); 307static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 308static void urtwn_start(struct urtwn_softc *); 309static void urtwn_parent(struct ieee80211com *); 310static int urtwn_r92c_power_on(struct urtwn_softc *); 311static int urtwn_r88e_power_on(struct urtwn_softc *); 312static void urtwn_r92c_power_off(struct urtwn_softc *); 313static void urtwn_r88e_power_off(struct urtwn_softc *); 314static int urtwn_llt_init(struct urtwn_softc *); 315#ifndef URTWN_WITHOUT_UCODE 316static void urtwn_fw_reset(struct urtwn_softc *); 317static void urtwn_r88e_fw_reset(struct urtwn_softc *); 318static int urtwn_fw_loadpage(struct urtwn_softc *, int, 319 const uint8_t *, int); 320static int urtwn_load_firmware(struct urtwn_softc *); 321#endif 322static int urtwn_dma_init(struct urtwn_softc *); 323static int urtwn_mac_init(struct urtwn_softc *); 324static void urtwn_bb_init(struct urtwn_softc *); 325static void urtwn_rf_init(struct urtwn_softc *); 326static void urtwn_cam_init(struct urtwn_softc *); 327static int urtwn_cam_write(struct urtwn_softc *, uint32_t, 328 uint32_t); 329static void urtwn_pa_bias_init(struct urtwn_softc *); 330static void urtwn_rxfilter_init(struct urtwn_softc *); 331static void urtwn_edca_init(struct urtwn_softc *); 332static void urtwn_write_txpower(struct urtwn_softc *, int, 333 uint16_t[]); 334static void urtwn_get_txpower(struct urtwn_softc *, int, 335 struct ieee80211_channel *, 336 struct ieee80211_channel *, uint16_t[]); 337static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 338 struct ieee80211_channel *, 339 struct ieee80211_channel *, uint16_t[]); 340static void urtwn_set_txpower(struct urtwn_softc *, 341 struct ieee80211_channel *, 342 struct ieee80211_channel *); 343static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 344static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 345static void urtwn_scan_start(struct ieee80211com *); 346static void urtwn_scan_end(struct ieee80211com *); 347static void urtwn_set_channel(struct ieee80211com *); 348static int urtwn_wme_update(struct ieee80211com *); 349static void urtwn_update_slot(struct ieee80211com *); 350static void urtwn_update_slot_cb(struct urtwn_softc *, 351 union sec_param *); 352static void urtwn_update_aifs(struct urtwn_softc *, uint8_t); 353static void urtwn_set_promisc(struct urtwn_softc *); 354static void urtwn_update_promisc(struct ieee80211com *); 355static void urtwn_update_mcast(struct ieee80211com *); 356static struct ieee80211_node *urtwn_r88e_node_alloc(struct ieee80211vap *, 357 const uint8_t mac[IEEE80211_ADDR_LEN]); 358static void urtwn_r88e_newassoc(struct ieee80211_node *, int); 359static void urtwn_r88e_node_free(struct ieee80211_node *); 360static void urtwn_set_chan(struct urtwn_softc *, 361 struct ieee80211_channel *, 362 struct ieee80211_channel *); 363static void urtwn_iq_calib(struct urtwn_softc *); 364static void urtwn_lc_calib(struct urtwn_softc *); 365static void urtwn_temp_calib(struct urtwn_softc *); 366static int urtwn_init(struct urtwn_softc *); 367static void urtwn_stop(struct urtwn_softc *); 368static void urtwn_abort_xfers(struct urtwn_softc *); 369static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 370 const struct ieee80211_bpf_params *); 371static void urtwn_ms_delay(struct urtwn_softc *); 372 373/* Aliases. */ 374#define urtwn_bb_write urtwn_write_4 375#define urtwn_bb_read urtwn_read_4 376 377static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 378 [URTWN_BULK_RX] = { 379 .type = UE_BULK, 380 .endpoint = UE_ADDR_ANY, 381 .direction = UE_DIR_IN, 382 .bufsize = URTWN_RXBUFSZ, 383 .flags = { 384 .pipe_bof = 1, 385 .short_xfer_ok = 1 386 }, 387 .callback = urtwn_bulk_rx_callback, 388 }, 389 [URTWN_BULK_TX_BE] = { 390 .type = UE_BULK, 391 .endpoint = 0x03, 392 .direction = UE_DIR_OUT, 393 .bufsize = URTWN_TXBUFSZ, 394 .flags = { 395 .ext_buffer = 1, 396 .pipe_bof = 1, 397 .force_short_xfer = 1 398 }, 399 .callback = urtwn_bulk_tx_callback, 400 .timeout = URTWN_TX_TIMEOUT, /* ms */ 401 }, 402 [URTWN_BULK_TX_BK] = { 403 .type = UE_BULK, 404 .endpoint = 0x03, 405 .direction = UE_DIR_OUT, 406 .bufsize = URTWN_TXBUFSZ, 407 .flags = { 408 .ext_buffer = 1, 409 .pipe_bof = 1, 410 .force_short_xfer = 1, 411 }, 412 .callback = urtwn_bulk_tx_callback, 413 .timeout = URTWN_TX_TIMEOUT, /* ms */ 414 }, 415 [URTWN_BULK_TX_VI] = { 416 .type = UE_BULK, 417 .endpoint = 0x02, 418 .direction = UE_DIR_OUT, 419 .bufsize = URTWN_TXBUFSZ, 420 .flags = { 421 .ext_buffer = 1, 422 .pipe_bof = 1, 423 .force_short_xfer = 1 424 }, 425 .callback = urtwn_bulk_tx_callback, 426 .timeout = URTWN_TX_TIMEOUT, /* ms */ 427 }, 428 [URTWN_BULK_TX_VO] = { 429 .type = UE_BULK, 430 .endpoint = 0x02, 431 .direction = UE_DIR_OUT, 432 .bufsize = URTWN_TXBUFSZ, 433 .flags = { 434 .ext_buffer = 1, 435 .pipe_bof = 1, 436 .force_short_xfer = 1 437 }, 438 .callback = urtwn_bulk_tx_callback, 439 .timeout = URTWN_TX_TIMEOUT, /* ms */ 440 }, 441}; 442 443static const struct wme_to_queue { 444 uint16_t reg; 445 uint8_t qid; 446} wme2queue[WME_NUM_AC] = { 447 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 448 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 449 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 450 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 451}; 452 453static int 454urtwn_match(device_t self) 455{ 456 struct usb_attach_arg *uaa = device_get_ivars(self); 457 458 if (uaa->usb_mode != USB_MODE_HOST) 459 return (ENXIO); 460 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 461 return (ENXIO); 462 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 463 return (ENXIO); 464 465 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 466} 467 468static int 469urtwn_attach(device_t self) 470{ 471 struct usb_attach_arg *uaa = device_get_ivars(self); 472 struct urtwn_softc *sc = device_get_softc(self); 473 struct ieee80211com *ic = &sc->sc_ic; 474 uint8_t bands[howmany(IEEE80211_MODE_MAX, 8)]; 475 int error; 476 477 device_set_usb_desc(self); 478 sc->sc_udev = uaa->device; 479 sc->sc_dev = self; 480 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 481 sc->chip |= URTWN_CHIP_88E; 482 483#ifdef USB_DEBUG 484 int debug; 485 if (resource_int_value(device_get_name(sc->sc_dev), 486 device_get_unit(sc->sc_dev), "debug", &debug) == 0) 487 sc->sc_debug = debug; 488#endif 489 490 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 491 MTX_NETWORK_LOCK, MTX_DEF); 492 URTWN_CMDQ_LOCK_INIT(sc); 493 URTWN_NT_LOCK_INIT(sc); 494 callout_init(&sc->sc_calib_to, 0); 495 callout_init(&sc->sc_watchdog_ch, 0); 496 mbufq_init(&sc->sc_snd, ifqmaxlen); 497 498 sc->sc_iface_index = URTWN_IFACE_INDEX; 499 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 500 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 501 if (error) { 502 device_printf(self, "could not allocate USB transfers, " 503 "err=%s\n", usbd_errstr(error)); 504 goto detach; 505 } 506 507 URTWN_LOCK(sc); 508 509 error = urtwn_read_chipid(sc); 510 if (error) { 511 device_printf(sc->sc_dev, "unsupported test chip\n"); 512 URTWN_UNLOCK(sc); 513 goto detach; 514 } 515 516 /* Determine number of Tx/Rx chains. */ 517 if (sc->chip & URTWN_CHIP_92C) { 518 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 519 sc->nrxchains = 2; 520 } else { 521 sc->ntxchains = 1; 522 sc->nrxchains = 1; 523 } 524 525 if (sc->chip & URTWN_CHIP_88E) 526 error = urtwn_r88e_read_rom(sc); 527 else 528 error = urtwn_read_rom(sc); 529 if (error != 0) { 530 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 531 __func__, error); 532 URTWN_UNLOCK(sc); 533 goto detach; 534 } 535 536 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 537 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 538 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 539 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 540 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 541 "8188CUS", sc->ntxchains, sc->nrxchains); 542 543 URTWN_UNLOCK(sc); 544 545 ic->ic_softc = sc; 546 ic->ic_name = device_get_nameunit(self); 547 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 548 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 549 550 /* set device capabilities */ 551 ic->ic_caps = 552 IEEE80211_C_STA /* station mode */ 553 | IEEE80211_C_MONITOR /* monitor mode */ 554 | IEEE80211_C_IBSS /* adhoc mode */ 555 | IEEE80211_C_HOSTAP /* hostap mode */ 556 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 557 | IEEE80211_C_SHSLOT /* short slot time supported */ 558 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 559 | IEEE80211_C_WPA /* 802.11i */ 560 | IEEE80211_C_WME /* 802.11e */ 561 ; 562 563 ic->ic_cryptocaps = 564 IEEE80211_CRYPTO_WEP | 565 IEEE80211_CRYPTO_TKIP | 566 IEEE80211_CRYPTO_AES_CCM; 567 568 memset(bands, 0, sizeof(bands)); 569 setbit(bands, IEEE80211_MODE_11B); 570 setbit(bands, IEEE80211_MODE_11G); 571 ieee80211_init_channels(ic, NULL, bands); 572 573 ieee80211_ifattach(ic); 574 ic->ic_raw_xmit = urtwn_raw_xmit; 575 ic->ic_scan_start = urtwn_scan_start; 576 ic->ic_scan_end = urtwn_scan_end; 577 ic->ic_set_channel = urtwn_set_channel; 578 ic->ic_transmit = urtwn_transmit; 579 ic->ic_parent = urtwn_parent; 580 ic->ic_vap_create = urtwn_vap_create; 581 ic->ic_vap_delete = urtwn_vap_delete; 582 ic->ic_wme.wme_update = urtwn_wme_update; 583 ic->ic_updateslot = urtwn_update_slot; 584 ic->ic_update_promisc = urtwn_update_promisc; 585 ic->ic_update_mcast = urtwn_update_mcast; 586 if (sc->chip & URTWN_CHIP_88E) { 587 ic->ic_node_alloc = urtwn_r88e_node_alloc; 588 ic->ic_newassoc = urtwn_r88e_newassoc; 589 sc->sc_node_free = ic->ic_node_free; 590 ic->ic_node_free = urtwn_r88e_node_free; 591 } 592 593 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 594 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 595 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 596 URTWN_RX_RADIOTAP_PRESENT); 597 598 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc); 599 600 urtwn_sysctlattach(sc); 601 602 if (bootverbose) 603 ieee80211_announce(ic); 604 605 return (0); 606 607detach: 608 urtwn_detach(self); 609 return (ENXIO); /* failure */ 610} 611 612static void 613urtwn_sysctlattach(struct urtwn_softc *sc) 614{ 615#ifdef USB_DEBUG 616 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 617 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 618 619 SYSCTL_ADD_U32(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 620 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 621 "control debugging printfs"); 622#endif 623} 624 625static int 626urtwn_detach(device_t self) 627{ 628 struct urtwn_softc *sc = device_get_softc(self); 629 struct ieee80211com *ic = &sc->sc_ic; 630 unsigned int x; 631 632 /* Prevent further ioctls. */ 633 URTWN_LOCK(sc); 634 sc->sc_flags |= URTWN_DETACHED; 635 URTWN_UNLOCK(sc); 636 637 urtwn_stop(sc); 638 639 callout_drain(&sc->sc_watchdog_ch); 640 callout_drain(&sc->sc_calib_to); 641 642 /* stop all USB transfers */ 643 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 644 645 /* Prevent further allocations from RX/TX data lists. */ 646 URTWN_LOCK(sc); 647 STAILQ_INIT(&sc->sc_tx_active); 648 STAILQ_INIT(&sc->sc_tx_inactive); 649 STAILQ_INIT(&sc->sc_tx_pending); 650 651 STAILQ_INIT(&sc->sc_rx_active); 652 STAILQ_INIT(&sc->sc_rx_inactive); 653 URTWN_UNLOCK(sc); 654 655 /* drain USB transfers */ 656 for (x = 0; x != URTWN_N_TRANSFER; x++) 657 usbd_transfer_drain(sc->sc_xfer[x]); 658 659 /* Free data buffers. */ 660 URTWN_LOCK(sc); 661 urtwn_free_tx_list(sc); 662 urtwn_free_rx_list(sc); 663 URTWN_UNLOCK(sc); 664 665 if (ic->ic_softc == sc) { 666 ieee80211_draintask(ic, &sc->cmdq_task); 667 ieee80211_ifdetach(ic); 668 } 669 670 URTWN_NT_LOCK_DESTROY(sc); 671 URTWN_CMDQ_LOCK_DESTROY(sc); 672 mtx_destroy(&sc->sc_mtx); 673 674 return (0); 675} 676 677static void 678urtwn_drain_mbufq(struct urtwn_softc *sc) 679{ 680 struct mbuf *m; 681 struct ieee80211_node *ni; 682 URTWN_ASSERT_LOCKED(sc); 683 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 684 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 685 m->m_pkthdr.rcvif = NULL; 686 ieee80211_free_node(ni); 687 m_freem(m); 688 } 689} 690 691static usb_error_t 692urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 693 void *data) 694{ 695 usb_error_t err; 696 int ntries = 10; 697 698 URTWN_ASSERT_LOCKED(sc); 699 700 while (ntries--) { 701 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 702 req, data, 0, NULL, 250 /* ms */); 703 if (err == 0) 704 break; 705 706 URTWN_DPRINTF(sc, URTWN_DEBUG_USB, 707 "%s: control request failed, %s (retries left: %d)\n", 708 __func__, usbd_errstr(err), ntries); 709 usb_pause_mtx(&sc->sc_mtx, hz / 100); 710 } 711 return (err); 712} 713 714static struct ieee80211vap * 715urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 716 enum ieee80211_opmode opmode, int flags, 717 const uint8_t bssid[IEEE80211_ADDR_LEN], 718 const uint8_t mac[IEEE80211_ADDR_LEN]) 719{ 720 struct urtwn_softc *sc = ic->ic_softc; 721 struct urtwn_vap *uvp; 722 struct ieee80211vap *vap; 723 724 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 725 return (NULL); 726 727 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 728 vap = &uvp->vap; 729 /* enable s/w bmiss handling for sta mode */ 730 731 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 732 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 733 /* out of memory */ 734 free(uvp, M_80211_VAP); 735 return (NULL); 736 } 737 738 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 739 urtwn_init_beacon(sc, uvp); 740 741 /* override state transition machine */ 742 uvp->newstate = vap->iv_newstate; 743 vap->iv_newstate = urtwn_newstate; 744 vap->iv_update_beacon = urtwn_update_beacon; 745 vap->iv_key_alloc = urtwn_key_alloc; 746 vap->iv_key_set = urtwn_key_set; 747 vap->iv_key_delete = urtwn_key_delete; 748 if (opmode == IEEE80211_M_IBSS) { 749 uvp->recv_mgmt = vap->iv_recv_mgmt; 750 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 751 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 752 } 753 754 if (URTWN_CHIP_HAS_RATECTL(sc)) 755 ieee80211_ratectl_init(vap); 756 /* complete setup */ 757 ieee80211_vap_attach(vap, ieee80211_media_change, 758 ieee80211_media_status, mac); 759 ic->ic_opmode = opmode; 760 return (vap); 761} 762 763static void 764urtwn_vap_delete(struct ieee80211vap *vap) 765{ 766 struct ieee80211com *ic = vap->iv_ic; 767 struct urtwn_softc *sc = ic->ic_softc; 768 struct urtwn_vap *uvp = URTWN_VAP(vap); 769 770 if (uvp->bcn_mbuf != NULL) 771 m_freem(uvp->bcn_mbuf); 772 if (vap->iv_opmode == IEEE80211_M_IBSS) 773 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 774 if (URTWN_CHIP_HAS_RATECTL(sc)) 775 ieee80211_ratectl_deinit(vap); 776 ieee80211_vap_detach(vap); 777 free(uvp, M_80211_VAP); 778} 779 780static struct mbuf * 781urtwn_rx_copy_to_mbuf(struct urtwn_softc *sc, struct r92c_rx_stat *stat, 782 int totlen) 783{ 784 struct ieee80211com *ic = &sc->sc_ic; 785 struct mbuf *m; 786 uint32_t rxdw0; 787 int pktlen; 788 789 /* 790 * don't pass packets to the ieee80211 framework if the driver isn't 791 * RUNNING. 792 */ 793 if (!(sc->sc_flags & URTWN_RUNNING)) 794 return (NULL); 795 796 rxdw0 = le32toh(stat->rxdw0); 797 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 798 /* 799 * This should not happen since we setup our Rx filter 800 * to not receive these frames. 801 */ 802 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 803 "%s: RX flags error (%s)\n", __func__, 804 rxdw0 & R92C_RXDW0_CRCERR ? "CRC" : "ICV"); 805 goto fail; 806 } 807 808 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 809 if (pktlen < sizeof(struct ieee80211_frame_ack)) { 810 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 811 "%s: frame is too short: %d\n", __func__, pktlen); 812 goto fail; 813 } 814 815 if (__predict_false(totlen > MCLBYTES)) { 816 /* convert to m_getjcl if this happens */ 817 device_printf(sc->sc_dev, "%s: frame too long: %d (%d)\n", 818 __func__, pktlen, totlen); 819 goto fail; 820 } 821 822 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 823 if (__predict_false(m == NULL)) { 824 device_printf(sc->sc_dev, "%s: could not allocate RX mbuf\n", 825 __func__); 826 goto fail; 827 } 828 829 /* Finalize mbuf. */ 830 memcpy(mtod(m, uint8_t *), (uint8_t *)stat, totlen); 831 m->m_pkthdr.len = m->m_len = totlen; 832 833 return (m); 834fail: 835 counter_u64_add(ic->ic_ierrors, 1); 836 return (NULL); 837} 838 839static struct mbuf * 840urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data) 841{ 842 struct urtwn_softc *sc = data->sc; 843 struct ieee80211com *ic = &sc->sc_ic; 844 struct r92c_rx_stat *stat; 845 uint8_t *buf; 846 int len; 847 848 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 849 850 if (len < sizeof(*stat)) { 851 counter_u64_add(ic->ic_ierrors, 1); 852 return (NULL); 853 } 854 855 buf = data->buf; 856 stat = (struct r92c_rx_stat *)buf; 857 858 if (sc->chip & URTWN_CHIP_88E) { 859 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 860 861 switch (report_sel) { 862 case R88E_RXDW3_RPT_RX: 863 return (urtwn_rxeof(sc, buf, len)); 864 case R88E_RXDW3_RPT_TX1: 865 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 866 break; 867 default: 868 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, 869 "%s: case %d was not handled\n", __func__, 870 report_sel); 871 break; 872 } 873 } else 874 return (urtwn_rxeof(sc, buf, len)); 875 876 return (NULL); 877} 878 879static struct mbuf * 880urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len) 881{ 882 struct r92c_rx_stat *stat; 883 struct mbuf *m, *m0 = NULL, *prevm = NULL; 884 uint32_t rxdw0; 885 int totlen, pktlen, infosz, npkts; 886 887 /* Get the number of encapsulated frames. */ 888 stat = (struct r92c_rx_stat *)buf; 889 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 890 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 891 "%s: Rx %d frames in one chunk\n", __func__, npkts); 892 893 /* Process all of them. */ 894 while (npkts-- > 0) { 895 if (len < sizeof(*stat)) 896 break; 897 stat = (struct r92c_rx_stat *)buf; 898 rxdw0 = le32toh(stat->rxdw0); 899 900 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 901 if (pktlen == 0) 902 break; 903 904 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 905 906 /* Make sure everything fits in xfer. */ 907 totlen = sizeof(*stat) + infosz + pktlen; 908 if (totlen > len) 909 break; 910 911 m = urtwn_rx_copy_to_mbuf(sc, stat, totlen); 912 if (m0 == NULL) 913 m0 = m; 914 if (prevm == NULL) 915 prevm = m; 916 else { 917 prevm->m_next = m; 918 prevm = m; 919 } 920 921 /* Next chunk is 128-byte aligned. */ 922 totlen = (totlen + 127) & ~127; 923 buf += totlen; 924 len -= totlen; 925 } 926 927 return (m0); 928} 929 930static void 931urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 932{ 933 struct r88e_tx_rpt_ccx *rpt = arg; 934 struct ieee80211vap *vap; 935 struct ieee80211_node *ni; 936 uint8_t macid; 937 int ntries; 938 939 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 940 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 941 942 URTWN_NT_LOCK(sc); 943 ni = sc->node_list[macid]; 944 if (ni != NULL) { 945 vap = ni->ni_vap; 946 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: frame for macid %d was" 947 "%s sent (%d retries)\n", __func__, macid, 948 (rpt->rptb1 & R88E_RPTB1_PKT_OK) ? "" : " not", 949 ntries); 950 951 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 952 ieee80211_ratectl_tx_complete(vap, ni, 953 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 954 } else { 955 ieee80211_ratectl_tx_complete(vap, ni, 956 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 957 } 958 } else { 959 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: macid %d, ni is NULL\n", 960 __func__, macid); 961 } 962 URTWN_NT_UNLOCK(sc); 963} 964 965static struct ieee80211_node * 966urtwn_rx_frame(struct urtwn_softc *sc, struct mbuf *m, int8_t *rssi_p) 967{ 968 struct ieee80211com *ic = &sc->sc_ic; 969 struct ieee80211_frame_min *wh; 970 struct r92c_rx_stat *stat; 971 uint32_t rxdw0, rxdw3; 972 uint8_t rate, cipher; 973 int8_t rssi = URTWN_NOISE_FLOOR + 1; 974 int infosz; 975 976 stat = mtod(m, struct r92c_rx_stat *); 977 rxdw0 = le32toh(stat->rxdw0); 978 rxdw3 = le32toh(stat->rxdw3); 979 980 rate = MS(rxdw3, R92C_RXDW3_RATE); 981 cipher = MS(rxdw0, R92C_RXDW0_CIPHER); 982 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 983 984 /* Get RSSI from PHY status descriptor if present. */ 985 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 986 if (sc->chip & URTWN_CHIP_88E) 987 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 988 else 989 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 990 /* Update our average RSSI. */ 991 urtwn_update_avgrssi(sc, rate, rssi); 992 } 993 994 if (ieee80211_radiotap_active(ic)) { 995 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 996 997 tap->wr_flags = 0; 998 999 urtwn_get_tsf(sc, &tap->wr_tsft); 1000 if (__predict_false(le32toh((uint32_t)tap->wr_tsft) < 1001 le32toh(stat->rxdw5))) { 1002 tap->wr_tsft = le32toh(tap->wr_tsft >> 32) - 1; 1003 tap->wr_tsft = (uint64_t)htole32(tap->wr_tsft) << 32; 1004 } else 1005 tap->wr_tsft &= 0xffffffff00000000; 1006 tap->wr_tsft += stat->rxdw5; 1007 1008 /* Map HW rate index to 802.11 rate. */ 1009 if (!(rxdw3 & R92C_RXDW3_HT)) { 1010 tap->wr_rate = ridx2rate[rate]; 1011 } else if (rate >= 12) { /* MCS0~15. */ 1012 /* Bit 7 set means HT MCS instead of rate. */ 1013 tap->wr_rate = 0x80 | (rate - 12); 1014 } 1015 tap->wr_dbm_antsignal = rssi; 1016 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 1017 } 1018 1019 *rssi_p = rssi; 1020 1021 /* Drop descriptor. */ 1022 m_adj(m, sizeof(*stat) + infosz); 1023 wh = mtod(m, struct ieee80211_frame_min *); 1024 1025 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1026 cipher != R92C_CAM_ALGO_NONE) { 1027 m->m_flags |= M_WEP; 1028 } 1029 1030 if (m->m_len >= sizeof(*wh)) 1031 return (ieee80211_find_rxnode(ic, wh)); 1032 1033 return (NULL); 1034} 1035 1036static void 1037urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 1038{ 1039 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1040 struct ieee80211com *ic = &sc->sc_ic; 1041 struct ieee80211_node *ni; 1042 struct mbuf *m = NULL, *next; 1043 struct urtwn_data *data; 1044 int8_t nf, rssi; 1045 1046 URTWN_ASSERT_LOCKED(sc); 1047 1048 switch (USB_GET_STATE(xfer)) { 1049 case USB_ST_TRANSFERRED: 1050 data = STAILQ_FIRST(&sc->sc_rx_active); 1051 if (data == NULL) 1052 goto tr_setup; 1053 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1054 m = urtwn_report_intr(xfer, data); 1055 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1056 /* FALLTHROUGH */ 1057 case USB_ST_SETUP: 1058tr_setup: 1059 data = STAILQ_FIRST(&sc->sc_rx_inactive); 1060 if (data == NULL) { 1061 KASSERT(m == NULL, ("mbuf isn't NULL")); 1062 return; 1063 } 1064 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 1065 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 1066 usbd_xfer_set_frame_data(xfer, 0, data->buf, 1067 usbd_xfer_max_len(xfer)); 1068 usbd_transfer_submit(xfer); 1069 1070 /* 1071 * To avoid LOR we should unlock our private mutex here to call 1072 * ieee80211_input() because here is at the end of a USB 1073 * callback and safe to unlock. 1074 */ 1075 while (m != NULL) { 1076 next = m->m_next; 1077 m->m_next = NULL; 1078 1079 ni = urtwn_rx_frame(sc, m, &rssi); 1080 URTWN_UNLOCK(sc); 1081 1082 nf = URTWN_NOISE_FLOOR; 1083 if (ni != NULL) { 1084 (void)ieee80211_input(ni, m, rssi - nf, nf); 1085 ieee80211_free_node(ni); 1086 } else { 1087 (void)ieee80211_input_all(ic, m, rssi - nf, 1088 nf); 1089 } 1090 1091 URTWN_LOCK(sc); 1092 m = next; 1093 } 1094 break; 1095 default: 1096 /* needs it to the inactive queue due to a error. */ 1097 data = STAILQ_FIRST(&sc->sc_rx_active); 1098 if (data != NULL) { 1099 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1100 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1101 } 1102 if (error != USB_ERR_CANCELLED) { 1103 usbd_xfer_set_stall(xfer); 1104 counter_u64_add(ic->ic_ierrors, 1); 1105 goto tr_setup; 1106 } 1107 break; 1108 } 1109} 1110 1111static void 1112urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 1113{ 1114 1115 URTWN_ASSERT_LOCKED(sc); 1116 1117 if (data->ni != NULL) /* not a beacon frame */ 1118 ieee80211_tx_complete(data->ni, data->m, status); 1119 1120 data->ni = NULL; 1121 data->m = NULL; 1122 1123 sc->sc_txtimer = 0; 1124 1125 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 1126} 1127 1128static int 1129urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1130 int ndata, int maxsz) 1131{ 1132 int i, error; 1133 1134 for (i = 0; i < ndata; i++) { 1135 struct urtwn_data *dp = &data[i]; 1136 dp->sc = sc; 1137 dp->m = NULL; 1138 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1139 if (dp->buf == NULL) { 1140 device_printf(sc->sc_dev, 1141 "could not allocate buffer\n"); 1142 error = ENOMEM; 1143 goto fail; 1144 } 1145 dp->ni = NULL; 1146 } 1147 1148 return (0); 1149fail: 1150 urtwn_free_list(sc, data, ndata); 1151 return (error); 1152} 1153 1154static int 1155urtwn_alloc_rx_list(struct urtwn_softc *sc) 1156{ 1157 int error, i; 1158 1159 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1160 URTWN_RXBUFSZ); 1161 if (error != 0) 1162 return (error); 1163 1164 STAILQ_INIT(&sc->sc_rx_active); 1165 STAILQ_INIT(&sc->sc_rx_inactive); 1166 1167 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1168 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1169 1170 return (0); 1171} 1172 1173static int 1174urtwn_alloc_tx_list(struct urtwn_softc *sc) 1175{ 1176 int error, i; 1177 1178 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1179 URTWN_TXBUFSZ); 1180 if (error != 0) 1181 return (error); 1182 1183 STAILQ_INIT(&sc->sc_tx_active); 1184 STAILQ_INIT(&sc->sc_tx_inactive); 1185 STAILQ_INIT(&sc->sc_tx_pending); 1186 1187 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1188 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1189 1190 return (0); 1191} 1192 1193static void 1194urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1195{ 1196 int i; 1197 1198 for (i = 0; i < ndata; i++) { 1199 struct urtwn_data *dp = &data[i]; 1200 1201 if (dp->buf != NULL) { 1202 free(dp->buf, M_USBDEV); 1203 dp->buf = NULL; 1204 } 1205 if (dp->ni != NULL) { 1206 ieee80211_free_node(dp->ni); 1207 dp->ni = NULL; 1208 } 1209 } 1210} 1211 1212static void 1213urtwn_free_rx_list(struct urtwn_softc *sc) 1214{ 1215 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1216} 1217 1218static void 1219urtwn_free_tx_list(struct urtwn_softc *sc) 1220{ 1221 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1222} 1223 1224static void 1225urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1226{ 1227 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1228 struct urtwn_data *data; 1229 1230 URTWN_ASSERT_LOCKED(sc); 1231 1232 switch (USB_GET_STATE(xfer)){ 1233 case USB_ST_TRANSFERRED: 1234 data = STAILQ_FIRST(&sc->sc_tx_active); 1235 if (data == NULL) 1236 goto tr_setup; 1237 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1238 urtwn_txeof(sc, data, 0); 1239 /* FALLTHROUGH */ 1240 case USB_ST_SETUP: 1241tr_setup: 1242 data = STAILQ_FIRST(&sc->sc_tx_pending); 1243 if (data == NULL) { 1244 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1245 "%s: empty pending queue\n", __func__); 1246 goto finish; 1247 } 1248 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1249 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1250 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1251 usbd_transfer_submit(xfer); 1252 break; 1253 default: 1254 data = STAILQ_FIRST(&sc->sc_tx_active); 1255 if (data == NULL) 1256 goto tr_setup; 1257 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1258 urtwn_txeof(sc, data, 1); 1259 if (error != USB_ERR_CANCELLED) { 1260 usbd_xfer_set_stall(xfer); 1261 goto tr_setup; 1262 } 1263 break; 1264 } 1265finish: 1266 /* Kick-start more transmit */ 1267 urtwn_start(sc); 1268} 1269 1270static struct urtwn_data * 1271_urtwn_getbuf(struct urtwn_softc *sc) 1272{ 1273 struct urtwn_data *bf; 1274 1275 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1276 if (bf != NULL) 1277 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1278 else { 1279 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1280 "%s: out of xmit buffers\n", __func__); 1281 } 1282 return (bf); 1283} 1284 1285static struct urtwn_data * 1286urtwn_getbuf(struct urtwn_softc *sc) 1287{ 1288 struct urtwn_data *bf; 1289 1290 URTWN_ASSERT_LOCKED(sc); 1291 1292 bf = _urtwn_getbuf(sc); 1293 if (bf == NULL) { 1294 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: stop queue\n", 1295 __func__); 1296 } 1297 return (bf); 1298} 1299 1300static usb_error_t 1301urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1302 int len) 1303{ 1304 usb_device_request_t req; 1305 1306 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1307 req.bRequest = R92C_REQ_REGS; 1308 USETW(req.wValue, addr); 1309 USETW(req.wIndex, 0); 1310 USETW(req.wLength, len); 1311 return (urtwn_do_request(sc, &req, buf)); 1312} 1313 1314static usb_error_t 1315urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1316{ 1317 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1318} 1319 1320static usb_error_t 1321urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1322{ 1323 val = htole16(val); 1324 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1325} 1326 1327static usb_error_t 1328urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1329{ 1330 val = htole32(val); 1331 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1332} 1333 1334static usb_error_t 1335urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1336 int len) 1337{ 1338 usb_device_request_t req; 1339 1340 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1341 req.bRequest = R92C_REQ_REGS; 1342 USETW(req.wValue, addr); 1343 USETW(req.wIndex, 0); 1344 USETW(req.wLength, len); 1345 return (urtwn_do_request(sc, &req, buf)); 1346} 1347 1348static uint8_t 1349urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1350{ 1351 uint8_t val; 1352 1353 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1354 return (0xff); 1355 return (val); 1356} 1357 1358static uint16_t 1359urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1360{ 1361 uint16_t val; 1362 1363 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1364 return (0xffff); 1365 return (le16toh(val)); 1366} 1367 1368static uint32_t 1369urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1370{ 1371 uint32_t val; 1372 1373 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1374 return (0xffffffff); 1375 return (le32toh(val)); 1376} 1377 1378static int 1379urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1380{ 1381 struct r92c_fw_cmd cmd; 1382 usb_error_t error; 1383 int ntries; 1384 1385 if (!(sc->sc_flags & URTWN_FW_LOADED)) { 1386 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, "%s: firmware " 1387 "was not loaded; command (id %d) will be discarded\n", 1388 __func__, id); 1389 return (0); 1390 } 1391 1392 /* Wait for current FW box to be empty. */ 1393 for (ntries = 0; ntries < 100; ntries++) { 1394 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1395 break; 1396 urtwn_ms_delay(sc); 1397 } 1398 if (ntries == 100) { 1399 device_printf(sc->sc_dev, 1400 "could not send firmware command\n"); 1401 return (ETIMEDOUT); 1402 } 1403 memset(&cmd, 0, sizeof(cmd)); 1404 cmd.id = id; 1405 if (len > 3) 1406 cmd.id |= R92C_CMD_FLAG_EXT; 1407 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1408 memcpy(cmd.msg, buf, len); 1409 1410 /* Write the first word last since that will trigger the FW. */ 1411 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1412 (uint8_t *)&cmd + 4, 2); 1413 if (error != USB_ERR_NORMAL_COMPLETION) 1414 return (EIO); 1415 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1416 (uint8_t *)&cmd + 0, 4); 1417 if (error != USB_ERR_NORMAL_COMPLETION) 1418 return (EIO); 1419 1420 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1421 return (0); 1422} 1423 1424static void 1425urtwn_cmdq_cb(void *arg, int pending) 1426{ 1427 struct urtwn_softc *sc = arg; 1428 struct urtwn_cmdq *item; 1429 1430 /* 1431 * Device must be powered on (via urtwn_power_on()) 1432 * before any command may be sent. 1433 */ 1434 URTWN_LOCK(sc); 1435 if (!(sc->sc_flags & URTWN_RUNNING)) { 1436 URTWN_UNLOCK(sc); 1437 return; 1438 } 1439 1440 URTWN_CMDQ_LOCK(sc); 1441 while (sc->cmdq[sc->cmdq_first].func != NULL) { 1442 item = &sc->cmdq[sc->cmdq_first]; 1443 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE; 1444 URTWN_CMDQ_UNLOCK(sc); 1445 1446 item->func(sc, &item->data); 1447 1448 URTWN_CMDQ_LOCK(sc); 1449 memset(item, 0, sizeof (*item)); 1450 } 1451 URTWN_CMDQ_UNLOCK(sc); 1452 URTWN_UNLOCK(sc); 1453} 1454 1455static int 1456urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len, 1457 CMD_FUNC_PROTO) 1458{ 1459 struct ieee80211com *ic = &sc->sc_ic; 1460 1461 KASSERT(len <= sizeof(union sec_param), ("buffer overflow")); 1462 1463 URTWN_CMDQ_LOCK(sc); 1464 if (sc->cmdq[sc->cmdq_last].func != NULL) { 1465 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__); 1466 URTWN_CMDQ_UNLOCK(sc); 1467 1468 return (EAGAIN); 1469 } 1470 1471 if (ptr != NULL) 1472 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len); 1473 sc->cmdq[sc->cmdq_last].func = func; 1474 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE; 1475 URTWN_CMDQ_UNLOCK(sc); 1476 1477 ieee80211_runtask(ic, &sc->cmdq_task); 1478 1479 return (0); 1480} 1481 1482static __inline void 1483urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1484{ 1485 1486 sc->sc_rf_write(sc, chain, addr, val); 1487} 1488 1489static void 1490urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1491 uint32_t val) 1492{ 1493 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1494 SM(R92C_LSSI_PARAM_ADDR, addr) | 1495 SM(R92C_LSSI_PARAM_DATA, val)); 1496} 1497 1498static void 1499urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1500uint32_t val) 1501{ 1502 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1503 SM(R88E_LSSI_PARAM_ADDR, addr) | 1504 SM(R92C_LSSI_PARAM_DATA, val)); 1505} 1506 1507static uint32_t 1508urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1509{ 1510 uint32_t reg[R92C_MAX_CHAINS], val; 1511 1512 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1513 if (chain != 0) 1514 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1515 1516 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1517 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1518 urtwn_ms_delay(sc); 1519 1520 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1521 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1522 R92C_HSSI_PARAM2_READ_EDGE); 1523 urtwn_ms_delay(sc); 1524 1525 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1526 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1527 urtwn_ms_delay(sc); 1528 1529 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1530 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1531 else 1532 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1533 return (MS(val, R92C_LSSI_READBACK_DATA)); 1534} 1535 1536static int 1537urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1538{ 1539 usb_error_t error; 1540 int ntries; 1541 1542 error = urtwn_write_4(sc, R92C_LLT_INIT, 1543 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1544 SM(R92C_LLT_INIT_ADDR, addr) | 1545 SM(R92C_LLT_INIT_DATA, data)); 1546 if (error != USB_ERR_NORMAL_COMPLETION) 1547 return (EIO); 1548 /* Wait for write operation to complete. */ 1549 for (ntries = 0; ntries < 20; ntries++) { 1550 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1551 R92C_LLT_INIT_OP_NO_ACTIVE) 1552 return (0); 1553 urtwn_ms_delay(sc); 1554 } 1555 return (ETIMEDOUT); 1556} 1557 1558static int 1559urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1560{ 1561 uint32_t reg; 1562 usb_error_t error; 1563 int ntries; 1564 1565 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1566 return (EFAULT); 1567 1568 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1569 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1570 reg &= ~R92C_EFUSE_CTRL_VALID; 1571 1572 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1573 if (error != USB_ERR_NORMAL_COMPLETION) 1574 return (EIO); 1575 /* Wait for read operation to complete. */ 1576 for (ntries = 0; ntries < 100; ntries++) { 1577 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1578 if (reg & R92C_EFUSE_CTRL_VALID) 1579 break; 1580 urtwn_ms_delay(sc); 1581 } 1582 if (ntries == 100) { 1583 device_printf(sc->sc_dev, 1584 "could not read efuse byte at address 0x%x\n", 1585 sc->last_rom_addr); 1586 return (ETIMEDOUT); 1587 } 1588 1589 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1590 sc->last_rom_addr++; 1591 1592 return (0); 1593} 1594 1595static int 1596urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1597 uint8_t msk) 1598{ 1599 uint8_t reg; 1600 int i, error; 1601 1602 for (i = 0; i < 4; i++) { 1603 if (msk & (1 << i)) 1604 continue; 1605 error = urtwn_efuse_read_next(sc, ®); 1606 if (error != 0) 1607 return (error); 1608 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1609 off * 8 + i * 2, reg); 1610 rom[off * 8 + i * 2 + 0] = reg; 1611 1612 error = urtwn_efuse_read_next(sc, ®); 1613 if (error != 0) 1614 return (error); 1615 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1616 off * 8 + i * 2 + 1, reg); 1617 rom[off * 8 + i * 2 + 1] = reg; 1618 } 1619 1620 return (0); 1621} 1622 1623#ifdef USB_DEBUG 1624static void 1625urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1626{ 1627 int i; 1628 1629 /* Dump ROM contents. */ 1630 device_printf(sc->sc_dev, "%s:", __func__); 1631 for (i = 0; i < size; i++) { 1632 if (i % 32 == 0) 1633 printf("\n%03X: ", i); 1634 else if (i % 4 == 0) 1635 printf(" "); 1636 1637 printf("%02X", rom[i]); 1638 } 1639 printf("\n"); 1640} 1641#endif 1642 1643static int 1644urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1645{ 1646#define URTWN_CHK(res) do { \ 1647 if ((error = res) != 0) \ 1648 goto end; \ 1649} while(0) 1650 uint8_t msk, off, reg; 1651 int error; 1652 1653 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1654 1655 /* Read full ROM image. */ 1656 sc->last_rom_addr = 0; 1657 memset(rom, 0xff, size); 1658 1659 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1660 while (reg != 0xff) { 1661 /* check for extended header */ 1662 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1663 off = reg >> 5; 1664 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1665 1666 if ((reg & 0x0f) != 0x0f) 1667 off = ((reg & 0xf0) >> 1) | off; 1668 else 1669 continue; 1670 } else 1671 off = reg >> 4; 1672 msk = reg & 0xf; 1673 1674 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1675 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1676 } 1677 1678end: 1679 1680#ifdef USB_DEBUG 1681 if (sc->sc_debug & URTWN_DEBUG_ROM) 1682 urtwn_dump_rom_contents(sc, rom, size); 1683#endif 1684 1685 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1686 1687 if (error != 0) { 1688 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1689 __func__); 1690 } 1691 1692 return (error); 1693#undef URTWN_CHK 1694} 1695 1696static int 1697urtwn_efuse_switch_power(struct urtwn_softc *sc) 1698{ 1699 usb_error_t error; 1700 uint32_t reg; 1701 1702 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1703 if (error != USB_ERR_NORMAL_COMPLETION) 1704 return (EIO); 1705 1706 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1707 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1708 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1709 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1710 if (error != USB_ERR_NORMAL_COMPLETION) 1711 return (EIO); 1712 } 1713 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1714 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1715 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1716 reg | R92C_SYS_FUNC_EN_ELDR); 1717 if (error != USB_ERR_NORMAL_COMPLETION) 1718 return (EIO); 1719 } 1720 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1721 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1722 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1723 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1724 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1725 if (error != USB_ERR_NORMAL_COMPLETION) 1726 return (EIO); 1727 } 1728 1729 return (0); 1730} 1731 1732static int 1733urtwn_read_chipid(struct urtwn_softc *sc) 1734{ 1735 uint32_t reg; 1736 1737 if (sc->chip & URTWN_CHIP_88E) 1738 return (0); 1739 1740 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1741 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1742 return (EIO); 1743 1744 if (reg & R92C_SYS_CFG_TYPE_92C) { 1745 sc->chip |= URTWN_CHIP_92C; 1746 /* Check if it is a castrated 8192C. */ 1747 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1748 R92C_HPON_FSM_CHIP_BONDING_ID) == 1749 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1750 sc->chip |= URTWN_CHIP_92C_1T2R; 1751 } 1752 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1753 sc->chip |= URTWN_CHIP_UMC; 1754 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1755 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1756 } 1757 return (0); 1758} 1759 1760static int 1761urtwn_read_rom(struct urtwn_softc *sc) 1762{ 1763 struct r92c_rom *rom = &sc->rom.r92c_rom; 1764 int error; 1765 1766 /* Read full ROM image. */ 1767 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1768 if (error != 0) 1769 return (error); 1770 1771 /* XXX Weird but this is what the vendor driver does. */ 1772 sc->last_rom_addr = 0x1fa; 1773 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1774 if (error != 0) 1775 return (error); 1776 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: PA setting=0x%x\n", __func__, 1777 sc->pa_setting); 1778 1779 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1780 1781 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1782 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type=%d\n", 1783 __func__, sc->regulatory); 1784 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1785 1786 sc->sc_rf_write = urtwn_r92c_rf_write; 1787 sc->sc_power_on = urtwn_r92c_power_on; 1788 sc->sc_power_off = urtwn_r92c_power_off; 1789 1790 return (0); 1791} 1792 1793static int 1794urtwn_r88e_read_rom(struct urtwn_softc *sc) 1795{ 1796 struct r88e_rom *rom = &sc->rom.r88e_rom; 1797 int error; 1798 1799 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(sc->rom.r88e_rom)); 1800 if (error != 0) 1801 return (error); 1802 1803 sc->bw20_tx_pwr_diff = (rom->tx_pwr_diff >> 4); 1804 if (sc->bw20_tx_pwr_diff & 0x08) 1805 sc->bw20_tx_pwr_diff |= 0xf0; 1806 sc->ofdm_tx_pwr_diff = (rom->tx_pwr_diff & 0xf); 1807 if (sc->ofdm_tx_pwr_diff & 0x08) 1808 sc->ofdm_tx_pwr_diff |= 0xf0; 1809 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 1810 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type %d\n", 1811 __func__,sc->regulatory); 1812 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1813 1814 sc->sc_rf_write = urtwn_r88e_rf_write; 1815 sc->sc_power_on = urtwn_r88e_power_on; 1816 sc->sc_power_off = urtwn_r88e_power_off; 1817 1818 return (0); 1819} 1820 1821/* 1822 * Initialize rate adaptation in firmware. 1823 */ 1824static int 1825urtwn_ra_init(struct urtwn_softc *sc) 1826{ 1827 struct ieee80211com *ic = &sc->sc_ic; 1828 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1829 struct ieee80211_node *ni; 1830 struct ieee80211_rateset *rs; 1831 struct r92c_fw_cmd_macid_cfg cmd; 1832 uint32_t rates, basicrates; 1833 uint8_t mode; 1834 int maxrate, maxbasicrate, error, i, j; 1835 1836 ni = ieee80211_ref_node(vap->iv_bss); 1837 rs = &ni->ni_rates; 1838 1839 /* Get normal and basic rates mask. */ 1840 rates = basicrates = 0; 1841 maxrate = maxbasicrate = 0; 1842 for (i = 0; i < rs->rs_nrates; i++) { 1843 /* Convert 802.11 rate to HW rate index. */ 1844 for (j = 0; j < nitems(ridx2rate); j++) 1845 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1846 ridx2rate[j]) 1847 break; 1848 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1849 continue; 1850 rates |= 1 << j; 1851 if (j > maxrate) 1852 maxrate = j; 1853 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1854 basicrates |= 1 << j; 1855 if (j > maxbasicrate) 1856 maxbasicrate = j; 1857 } 1858 } 1859 if (ic->ic_curmode == IEEE80211_MODE_11B) 1860 mode = R92C_RAID_11B; 1861 else 1862 mode = R92C_RAID_11BG; 1863 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, 1864 "%s: mode 0x%x, rates 0x%08x, basicrates 0x%08x\n", __func__, 1865 mode, rates, basicrates); 1866 1867 /* Set rates mask for group addressed frames. */ 1868 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1869 cmd.mask = htole32(mode << 28 | basicrates); 1870 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1871 if (error != 0) { 1872 ieee80211_free_node(ni); 1873 device_printf(sc->sc_dev, 1874 "could not add broadcast station\n"); 1875 return (error); 1876 } 1877 /* Set initial MRR rate. */ 1878 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxbasicrate %d\n", __func__, 1879 maxbasicrate); 1880 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1881 maxbasicrate); 1882 1883 /* Set rates mask for unicast frames. */ 1884 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1885 cmd.mask = htole32(mode << 28 | rates); 1886 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1887 if (error != 0) { 1888 ieee80211_free_node(ni); 1889 device_printf(sc->sc_dev, "could not add BSS station\n"); 1890 return (error); 1891 } 1892 /* Set initial MRR rate. */ 1893 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxrate %d\n", __func__, 1894 maxrate); 1895 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1896 maxrate); 1897 1898 /* Indicate highest supported rate. */ 1899 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1900 ieee80211_free_node(ni); 1901 1902 return (0); 1903} 1904 1905static void 1906urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1907{ 1908 struct r92c_tx_desc *txd = &uvp->bcn_desc; 1909 1910 txd->txdw0 = htole32( 1911 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 1912 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1913 txd->txdw1 = htole32( 1914 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 1915 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1916 1917 if (sc->chip & URTWN_CHIP_88E) { 1918 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 1919 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 1920 } else { 1921 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 1922 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 1923 } 1924 1925 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 1926 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 1927} 1928 1929static int 1930urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 1931{ 1932 struct ieee80211vap *vap = ni->ni_vap; 1933 struct urtwn_vap *uvp = URTWN_VAP(vap); 1934 struct mbuf *m; 1935 int error; 1936 1937 URTWN_ASSERT_LOCKED(sc); 1938 1939 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 1940 return (EINVAL); 1941 1942 m = ieee80211_beacon_alloc(ni); 1943 if (m == NULL) { 1944 device_printf(sc->sc_dev, 1945 "%s: could not allocate beacon frame\n", __func__); 1946 return (ENOMEM); 1947 } 1948 1949 if (uvp->bcn_mbuf != NULL) 1950 m_freem(uvp->bcn_mbuf); 1951 1952 uvp->bcn_mbuf = m; 1953 1954 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1955 return (error); 1956 1957 /* XXX bcnq stuck workaround */ 1958 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1959 return (error); 1960 1961 URTWN_DPRINTF(sc, URTWN_DEBUG_BEACON, "%s: beacon was %srecognized\n", 1962 __func__, urtwn_read_1(sc, R92C_TDECTRL + 2) & 1963 (R92C_TDECTRL_BCN_VALID >> 16) ? "" : "not "); 1964 1965 return (0); 1966} 1967 1968static void 1969urtwn_update_beacon(struct ieee80211vap *vap, int item) 1970{ 1971 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1972 struct urtwn_vap *uvp = URTWN_VAP(vap); 1973 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 1974 struct ieee80211_node *ni = vap->iv_bss; 1975 int mcast = 0; 1976 1977 URTWN_LOCK(sc); 1978 if (uvp->bcn_mbuf == NULL) { 1979 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 1980 if (uvp->bcn_mbuf == NULL) { 1981 device_printf(sc->sc_dev, 1982 "%s: could not allocate beacon frame\n", __func__); 1983 URTWN_UNLOCK(sc); 1984 return; 1985 } 1986 } 1987 URTWN_UNLOCK(sc); 1988 1989 if (item == IEEE80211_BEACON_TIM) 1990 mcast = 1; /* XXX */ 1991 1992 setbit(bo->bo_flags, item); 1993 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 1994 1995 URTWN_LOCK(sc); 1996 urtwn_tx_beacon(sc, uvp); 1997 URTWN_UNLOCK(sc); 1998} 1999 2000/* 2001 * Push a beacon frame into the chip. Beacon will 2002 * be repeated by the chip every R92C_BCN_INTERVAL. 2003 */ 2004static int 2005urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2006{ 2007 struct r92c_tx_desc *desc = &uvp->bcn_desc; 2008 struct urtwn_data *bf; 2009 2010 URTWN_ASSERT_LOCKED(sc); 2011 2012 bf = urtwn_getbuf(sc); 2013 if (bf == NULL) 2014 return (ENOMEM); 2015 2016 memcpy(bf->buf, desc, sizeof(*desc)); 2017 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 2018 2019 sc->sc_txtimer = 5; 2020 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2021 2022 return (0); 2023} 2024 2025static int 2026urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2027 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2028{ 2029 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2030 uint8_t i; 2031 2032 if (!(&vap->iv_nw_keys[0] <= k && 2033 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2034 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2035 URTWN_LOCK(sc); 2036 /* 2037 * First 4 slots for group keys, 2038 * what is left - for pairwise. 2039 * XXX incompatible with IBSS RSN. 2040 */ 2041 for (i = IEEE80211_WEP_NKID; 2042 i < R92C_CAM_ENTRY_COUNT; i++) { 2043 if ((sc->keys_bmap & (1 << i)) == 0) { 2044 sc->keys_bmap |= 1 << i; 2045 *keyix = i; 2046 break; 2047 } 2048 } 2049 URTWN_UNLOCK(sc); 2050 if (i == R92C_CAM_ENTRY_COUNT) { 2051 device_printf(sc->sc_dev, 2052 "%s: no free space in the key table\n", 2053 __func__); 2054 return 0; 2055 } 2056 } else 2057 *keyix = 0; 2058 } else { 2059 *keyix = k - vap->iv_nw_keys; 2060 } 2061 *rxkeyix = *keyix; 2062 return 1; 2063} 2064 2065static void 2066urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data) 2067{ 2068 struct ieee80211_key *k = &data->key; 2069 uint8_t algo, keyid; 2070 int i, error; 2071 2072 if (k->wk_keyix < IEEE80211_WEP_NKID) 2073 keyid = k->wk_keyix; 2074 else 2075 keyid = 0; 2076 2077 /* Map net80211 cipher to HW crypto algorithm. */ 2078 switch (k->wk_cipher->ic_cipher) { 2079 case IEEE80211_CIPHER_WEP: 2080 if (k->wk_keylen < 8) 2081 algo = R92C_CAM_ALGO_WEP40; 2082 else 2083 algo = R92C_CAM_ALGO_WEP104; 2084 break; 2085 case IEEE80211_CIPHER_TKIP: 2086 algo = R92C_CAM_ALGO_TKIP; 2087 break; 2088 case IEEE80211_CIPHER_AES_CCM: 2089 algo = R92C_CAM_ALGO_AES; 2090 break; 2091 default: 2092 device_printf(sc->sc_dev, "%s: undefined cipher %d\n", 2093 __func__, k->wk_cipher->ic_cipher); 2094 return; 2095 } 2096 2097 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2098 "%s: keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, " 2099 "macaddr %s\n", __func__, k->wk_keyix, keyid, 2100 k->wk_cipher->ic_cipher, algo, k->wk_flags, k->wk_keylen, 2101 ether_sprintf(k->wk_macaddr)); 2102 2103 /* Write key. */ 2104 for (i = 0; i < 4; i++) { 2105 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 2106 LE_READ_4(&k->wk_key[i * 4])); 2107 if (error != 0) 2108 goto fail; 2109 } 2110 2111 /* Write CTL0 last since that will validate the CAM entry. */ 2112 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 2113 LE_READ_4(&k->wk_macaddr[2])); 2114 if (error != 0) 2115 goto fail; 2116 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 2117 SM(R92C_CAM_ALGO, algo) | 2118 SM(R92C_CAM_KEYID, keyid) | 2119 SM(R92C_CAM_MACLO, LE_READ_2(&k->wk_macaddr[0])) | 2120 R92C_CAM_VALID); 2121 if (error != 0) 2122 goto fail; 2123 2124 return; 2125 2126fail: 2127 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error); 2128} 2129 2130static void 2131urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data) 2132{ 2133 struct ieee80211_key *k = &data->key; 2134 int i; 2135 2136 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2137 "%s: keyix %d, flags %04X, macaddr %s\n", __func__, 2138 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr)); 2139 2140 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0); 2141 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0); 2142 2143 /* Clear key. */ 2144 for (i = 0; i < 4; i++) 2145 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0); 2146 sc->keys_bmap &= ~(1 << k->wk_keyix); 2147} 2148 2149static int 2150urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 2151{ 2152 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2153 2154 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2155 /* Not for us. */ 2156 return (1); 2157 } 2158 2159 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb)); 2160} 2161 2162static int 2163urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2164{ 2165 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2166 2167 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2168 /* Not for us. */ 2169 return (1); 2170 } 2171 2172 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb)); 2173} 2174 2175static void 2176urtwn_tsf_task_adhoc(void *arg, int pending) 2177{ 2178 struct ieee80211vap *vap = arg; 2179 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2180 struct ieee80211_node *ni; 2181 uint32_t reg; 2182 2183 URTWN_LOCK(sc); 2184 ni = ieee80211_ref_node(vap->iv_bss); 2185 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 2186 2187 /* Accept beacons with the same BSSID. */ 2188 urtwn_set_rx_bssid_all(sc, 0); 2189 2190 /* Enable synchronization. */ 2191 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 2192 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2193 2194 /* Synchronize. */ 2195 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 2196 2197 /* Disable synchronization. */ 2198 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 2199 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2200 2201 /* Remove beacon filter. */ 2202 urtwn_set_rx_bssid_all(sc, 1); 2203 2204 /* Enable beaconing. */ 2205 urtwn_write_1(sc, R92C_MBID_NUM, 2206 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2207 reg |= R92C_BCN_CTRL_EN_BCN; 2208 2209 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2210 ieee80211_free_node(ni); 2211 URTWN_UNLOCK(sc); 2212} 2213 2214static void 2215urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 2216{ 2217 struct ieee80211com *ic = &sc->sc_ic; 2218 struct urtwn_vap *uvp = URTWN_VAP(vap); 2219 2220 /* Reset TSF. */ 2221 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2222 2223 switch (vap->iv_opmode) { 2224 case IEEE80211_M_STA: 2225 /* Enable TSF synchronization. */ 2226 urtwn_write_1(sc, R92C_BCN_CTRL, 2227 urtwn_read_1(sc, R92C_BCN_CTRL) & 2228 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 2229 break; 2230 case IEEE80211_M_IBSS: 2231 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 2232 break; 2233 case IEEE80211_M_HOSTAP: 2234 /* Enable beaconing. */ 2235 urtwn_write_1(sc, R92C_MBID_NUM, 2236 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2237 urtwn_write_1(sc, R92C_BCN_CTRL, 2238 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 2239 break; 2240 default: 2241 device_printf(sc->sc_dev, "undefined opmode %d\n", 2242 vap->iv_opmode); 2243 return; 2244 } 2245} 2246 2247static void 2248urtwn_get_tsf(struct urtwn_softc *sc, uint64_t *buf) 2249{ 2250 urtwn_read_region_1(sc, R92C_TSFTR, (uint8_t *)buf, sizeof(*buf)); 2251} 2252 2253static void 2254urtwn_set_led(struct urtwn_softc *sc, int led, int on) 2255{ 2256 uint8_t reg; 2257 2258 if (led == URTWN_LED_LINK) { 2259 if (sc->chip & URTWN_CHIP_88E) { 2260 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 2261 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 2262 if (!on) { 2263 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 2264 urtwn_write_1(sc, R92C_LEDCFG2, 2265 reg | R92C_LEDCFG0_DIS); 2266 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 2267 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 2268 0xfe); 2269 } 2270 } else { 2271 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 2272 if (!on) 2273 reg |= R92C_LEDCFG0_DIS; 2274 urtwn_write_1(sc, R92C_LEDCFG0, reg); 2275 } 2276 sc->ledlink = on; /* Save LED state. */ 2277 } 2278} 2279 2280static void 2281urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 2282{ 2283 uint8_t reg; 2284 2285 reg = urtwn_read_1(sc, R92C_MSR); 2286 reg = (reg & ~R92C_MSR_MASK) | mode; 2287 urtwn_write_1(sc, R92C_MSR, reg); 2288} 2289 2290static void 2291urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 2292 const struct ieee80211_rx_stats *rxs, 2293 int rssi, int nf) 2294{ 2295 struct ieee80211vap *vap = ni->ni_vap; 2296 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2297 struct urtwn_vap *uvp = URTWN_VAP(vap); 2298 uint64_t ni_tstamp, curr_tstamp; 2299 2300 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 2301 2302 if (vap->iv_state == IEEE80211_S_RUN && 2303 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 2304 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 2305 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 2306 URTWN_LOCK(sc); 2307 urtwn_get_tsf(sc, &curr_tstamp); 2308 URTWN_UNLOCK(sc); 2309 curr_tstamp = le64toh(curr_tstamp); 2310 2311 if (ni_tstamp >= curr_tstamp) 2312 (void) ieee80211_ibss_merge(ni); 2313 } 2314} 2315 2316static int 2317urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2318{ 2319 struct urtwn_vap *uvp = URTWN_VAP(vap); 2320 struct ieee80211com *ic = vap->iv_ic; 2321 struct urtwn_softc *sc = ic->ic_softc; 2322 struct ieee80211_node *ni; 2323 enum ieee80211_state ostate; 2324 uint32_t reg; 2325 uint8_t mode; 2326 int error = 0; 2327 2328 ostate = vap->iv_state; 2329 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s -> %s\n", 2330 ieee80211_state_name[ostate], ieee80211_state_name[nstate]); 2331 2332 IEEE80211_UNLOCK(ic); 2333 URTWN_LOCK(sc); 2334 callout_stop(&sc->sc_watchdog_ch); 2335 2336 if (ostate == IEEE80211_S_RUN) { 2337 /* Stop calibration. */ 2338 callout_stop(&sc->sc_calib_to); 2339 2340 /* Turn link LED off. */ 2341 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2342 2343 /* Set media status to 'No Link'. */ 2344 urtwn_set_mode(sc, R92C_MSR_NOLINK); 2345 2346 /* Stop Rx of data frames. */ 2347 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2348 2349 /* Disable TSF synchronization. */ 2350 urtwn_write_1(sc, R92C_BCN_CTRL, 2351 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 2352 R92C_BCN_CTRL_DIS_TSF_UDT0); 2353 2354 /* Disable beaconing. */ 2355 urtwn_write_1(sc, R92C_MBID_NUM, 2356 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 2357 2358 /* Reset TSF. */ 2359 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2360 2361 /* Reset EDCA parameters. */ 2362 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2363 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2364 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2365 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2366 } 2367 2368 switch (nstate) { 2369 case IEEE80211_S_INIT: 2370 /* Turn link LED off. */ 2371 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2372 break; 2373 case IEEE80211_S_SCAN: 2374 /* Pause AC Tx queues. */ 2375 urtwn_write_1(sc, R92C_TXPAUSE, 2376 urtwn_read_1(sc, R92C_TXPAUSE) | R92C_TX_QUEUE_AC); 2377 break; 2378 case IEEE80211_S_AUTH: 2379 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2380 break; 2381 case IEEE80211_S_RUN: 2382 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2383 /* Turn link LED on. */ 2384 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2385 break; 2386 } 2387 2388 ni = ieee80211_ref_node(vap->iv_bss); 2389 2390 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2391 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2392 device_printf(sc->sc_dev, 2393 "%s: could not move to RUN state\n", __func__); 2394 error = EINVAL; 2395 goto end_run; 2396 } 2397 2398 switch (vap->iv_opmode) { 2399 case IEEE80211_M_STA: 2400 mode = R92C_MSR_INFRA; 2401 break; 2402 case IEEE80211_M_IBSS: 2403 mode = R92C_MSR_ADHOC; 2404 break; 2405 case IEEE80211_M_HOSTAP: 2406 mode = R92C_MSR_AP; 2407 break; 2408 default: 2409 device_printf(sc->sc_dev, "undefined opmode %d\n", 2410 vap->iv_opmode); 2411 error = EINVAL; 2412 goto end_run; 2413 } 2414 2415 /* Set media status to 'Associated'. */ 2416 urtwn_set_mode(sc, mode); 2417 2418 /* Set BSSID. */ 2419 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2420 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2421 2422 if (ic->ic_curmode == IEEE80211_MODE_11B) 2423 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2424 else /* 802.11b/g */ 2425 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2426 2427 /* Enable Rx of data frames. */ 2428 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2429 2430 /* Flush all AC queues. */ 2431 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2432 2433 /* Set beacon interval. */ 2434 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2435 2436 /* Allow Rx from our BSSID only. */ 2437 if (ic->ic_promisc == 0) { 2438 reg = urtwn_read_4(sc, R92C_RCR); 2439 2440 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 2441 reg |= R92C_RCR_CBSSID_DATA; 2442 if (vap->iv_opmode != IEEE80211_M_IBSS) 2443 reg |= R92C_RCR_CBSSID_BCN; 2444 2445 urtwn_write_4(sc, R92C_RCR, reg); 2446 } 2447 2448 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2449 vap->iv_opmode == IEEE80211_M_IBSS) { 2450 error = urtwn_setup_beacon(sc, ni); 2451 if (error != 0) { 2452 device_printf(sc->sc_dev, 2453 "unable to push beacon into the chip, " 2454 "error %d\n", error); 2455 goto end_run; 2456 } 2457 } 2458 2459 /* Enable TSF synchronization. */ 2460 urtwn_tsf_sync_enable(sc, vap); 2461 2462 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2463 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2464 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2465 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2466 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2467 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2468 2469 /* Intialize rate adaptation. */ 2470 if (!(sc->chip & URTWN_CHIP_88E)) 2471 urtwn_ra_init(sc); 2472 /* Turn link LED on. */ 2473 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2474 2475 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2476 /* Reset temperature calibration state machine. */ 2477 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 2478 sc->thcal_lctemp = 0; 2479 /* Start periodic calibration. */ 2480 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2481 2482end_run: 2483 ieee80211_free_node(ni); 2484 break; 2485 default: 2486 break; 2487 } 2488 2489 URTWN_UNLOCK(sc); 2490 IEEE80211_LOCK(ic); 2491 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2492} 2493 2494static void 2495urtwn_calib_to(void *arg) 2496{ 2497 struct urtwn_softc *sc = arg; 2498 2499 /* Do it in a process context. */ 2500 urtwn_cmd_sleepable(sc, NULL, 0, urtwn_calib_cb); 2501} 2502 2503static void 2504urtwn_calib_cb(struct urtwn_softc *sc, union sec_param *data) 2505{ 2506 /* Do temperature compensation. */ 2507 urtwn_temp_calib(sc); 2508 2509 if ((urtwn_read_1(sc, R92C_MSR) & R92C_MSR_MASK) != R92C_MSR_NOLINK) 2510 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2511} 2512 2513static void 2514urtwn_watchdog(void *arg) 2515{ 2516 struct urtwn_softc *sc = arg; 2517 2518 if (sc->sc_txtimer > 0) { 2519 if (--sc->sc_txtimer == 0) { 2520 device_printf(sc->sc_dev, "device timeout\n"); 2521 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2522 return; 2523 } 2524 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2525 } 2526} 2527 2528static void 2529urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2530{ 2531 int pwdb; 2532 2533 /* Convert antenna signal to percentage. */ 2534 if (rssi <= -100 || rssi >= 20) 2535 pwdb = 0; 2536 else if (rssi >= 0) 2537 pwdb = 100; 2538 else 2539 pwdb = 100 + rssi; 2540 if (!(sc->chip & URTWN_CHIP_88E)) { 2541 if (rate <= URTWN_RIDX_CCK11) { 2542 /* CCK gain is smaller than OFDM/MCS gain. */ 2543 pwdb += 6; 2544 if (pwdb > 100) 2545 pwdb = 100; 2546 if (pwdb <= 14) 2547 pwdb -= 4; 2548 else if (pwdb <= 26) 2549 pwdb -= 8; 2550 else if (pwdb <= 34) 2551 pwdb -= 6; 2552 else if (pwdb <= 42) 2553 pwdb -= 2; 2554 } 2555 } 2556 if (sc->avg_pwdb == -1) /* Init. */ 2557 sc->avg_pwdb = pwdb; 2558 else if (sc->avg_pwdb < pwdb) 2559 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2560 else 2561 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2562 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: PWDB %d, EMA %d\n", __func__, 2563 pwdb, sc->avg_pwdb); 2564} 2565 2566static int8_t 2567urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2568{ 2569 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2570 struct r92c_rx_phystat *phy; 2571 struct r92c_rx_cck *cck; 2572 uint8_t rpt; 2573 int8_t rssi; 2574 2575 if (rate <= URTWN_RIDX_CCK11) { 2576 cck = (struct r92c_rx_cck *)physt; 2577 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2578 rpt = (cck->agc_rpt >> 5) & 0x3; 2579 rssi = (cck->agc_rpt & 0x1f) << 1; 2580 } else { 2581 rpt = (cck->agc_rpt >> 6) & 0x3; 2582 rssi = cck->agc_rpt & 0x3e; 2583 } 2584 rssi = cckoff[rpt] - rssi; 2585 } else { /* OFDM/HT. */ 2586 phy = (struct r92c_rx_phystat *)physt; 2587 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2588 } 2589 return (rssi); 2590} 2591 2592static int8_t 2593urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2594{ 2595 struct r92c_rx_phystat *phy; 2596 struct r88e_rx_cck *cck; 2597 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2598 int8_t rssi; 2599 2600 rssi = 0; 2601 if (rate <= URTWN_RIDX_CCK11) { 2602 cck = (struct r88e_rx_cck *)physt; 2603 cck_agc_rpt = cck->agc_rpt; 2604 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2605 vga_idx = cck_agc_rpt & 0x1f; 2606 switch (lna_idx) { 2607 case 7: 2608 if (vga_idx <= 27) 2609 rssi = -100 + 2* (27 - vga_idx); 2610 else 2611 rssi = -100; 2612 break; 2613 case 6: 2614 rssi = -48 + 2 * (2 - vga_idx); 2615 break; 2616 case 5: 2617 rssi = -42 + 2 * (7 - vga_idx); 2618 break; 2619 case 4: 2620 rssi = -36 + 2 * (7 - vga_idx); 2621 break; 2622 case 3: 2623 rssi = -24 + 2 * (7 - vga_idx); 2624 break; 2625 case 2: 2626 rssi = -12 + 2 * (5 - vga_idx); 2627 break; 2628 case 1: 2629 rssi = 8 - (2 * vga_idx); 2630 break; 2631 case 0: 2632 rssi = 14 - (2 * vga_idx); 2633 break; 2634 } 2635 rssi += 6; 2636 } else { /* OFDM/HT. */ 2637 phy = (struct r92c_rx_phystat *)physt; 2638 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2639 } 2640 return (rssi); 2641} 2642 2643static __inline uint8_t 2644rate2ridx(uint8_t rate) 2645{ 2646 switch (rate) { 2647 case 12: return 4; 2648 case 18: return 5; 2649 case 24: return 6; 2650 case 36: return 7; 2651 case 48: return 8; 2652 case 72: return 9; 2653 case 96: return 10; 2654 case 108: return 11; 2655 case 2: return 0; 2656 case 4: return 1; 2657 case 11: return 2; 2658 case 22: return 3; 2659 default: return 0; 2660 } 2661} 2662 2663static int 2664urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2665 struct mbuf *m, struct urtwn_data *data) 2666{ 2667 const struct ieee80211_txparam *tp; 2668 struct ieee80211com *ic = &sc->sc_ic; 2669 struct ieee80211vap *vap = ni->ni_vap; 2670 struct ieee80211_key *k = NULL; 2671 struct ieee80211_channel *chan; 2672 struct ieee80211_frame *wh; 2673 struct r92c_tx_desc *txd; 2674 uint8_t macid, raid, rate, ridx, subtype, type, tid, qsel; 2675 int hasqos, ismcast; 2676 2677 URTWN_ASSERT_LOCKED(sc); 2678 2679 /* 2680 * Software crypto. 2681 */ 2682 wh = mtod(m, struct ieee80211_frame *); 2683 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2684 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2685 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2686 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2687 2688 /* Select TX ring for this frame. */ 2689 if (hasqos) { 2690 tid = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2691 tid &= IEEE80211_QOS_TID; 2692 } else 2693 tid = 0; 2694 2695 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2696 ni->ni_chan : ic->ic_curchan; 2697 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2698 2699 /* Choose a TX rate index. */ 2700 if (type == IEEE80211_FC0_TYPE_MGT) 2701 rate = tp->mgmtrate; 2702 else if (ismcast) 2703 rate = tp->mcastrate; 2704 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2705 rate = tp->ucastrate; 2706 else if (m->m_flags & M_EAPOL) 2707 rate = tp->mgmtrate; 2708 else { 2709 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2710 /* XXX pass pktlen */ 2711 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2712 rate = ni->ni_txrate; 2713 } else { 2714 if (ic->ic_curmode != IEEE80211_MODE_11B) 2715 rate = 108; 2716 else 2717 rate = 22; 2718 } 2719 } 2720 2721 ridx = rate2ridx(rate); 2722 if (ic->ic_curmode != IEEE80211_MODE_11B) 2723 raid = R92C_RAID_11BG; 2724 else 2725 raid = R92C_RAID_11B; 2726 2727 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2728 k = ieee80211_crypto_encap(ni, m); 2729 if (k == NULL) { 2730 device_printf(sc->sc_dev, 2731 "ieee80211_crypto_encap returns NULL.\n"); 2732 return (ENOBUFS); 2733 } 2734 2735 /* in case packet header moved, reset pointer */ 2736 wh = mtod(m, struct ieee80211_frame *); 2737 } 2738 2739 /* Fill Tx descriptor. */ 2740 txd = (struct r92c_tx_desc *)data->buf; 2741 memset(txd, 0, sizeof(*txd)); 2742 2743 txd->txdw0 |= htole32( 2744 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2745 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2746 if (ismcast) 2747 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2748 2749 if (!ismcast) { 2750 if (sc->chip & URTWN_CHIP_88E) { 2751 struct urtwn_node *un = URTWN_NODE(ni); 2752 macid = un->id; 2753 } else 2754 macid = URTWN_MACID_BSS; 2755 2756 if (type == IEEE80211_FC0_TYPE_DATA) { 2757 qsel = tid % URTWN_MAX_TID; 2758 2759 if (sc->chip & URTWN_CHIP_88E) { 2760 txd->txdw2 |= htole32( 2761 R88E_TXDW2_AGGBK | 2762 R88E_TXDW2_CCX_RPT); 2763 } else 2764 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2765 2766 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2767 switch (ic->ic_protmode) { 2768 case IEEE80211_PROT_CTSONLY: 2769 txd->txdw4 |= htole32( 2770 R92C_TXDW4_CTS2SELF | 2771 R92C_TXDW4_HWRTSEN); 2772 break; 2773 case IEEE80211_PROT_RTSCTS: 2774 txd->txdw4 |= htole32( 2775 R92C_TXDW4_RTSEN | 2776 R92C_TXDW4_HWRTSEN); 2777 break; 2778 default: 2779 break; 2780 } 2781 } 2782 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2783 URTWN_RIDX_OFDM24)); 2784 txd->txdw5 |= htole32(0x0001ff00); 2785 } else /* IEEE80211_FC0_TYPE_MGT */ 2786 qsel = R92C_TXDW1_QSEL_MGNT; 2787 } else { 2788 macid = URTWN_MACID_BC; 2789 qsel = R92C_TXDW1_QSEL_MGNT; 2790 } 2791 2792 txd->txdw1 |= htole32( 2793 SM(R92C_TXDW1_QSEL, qsel) | 2794 SM(R92C_TXDW1_RAID, raid)); 2795 2796 if (sc->chip & URTWN_CHIP_88E) 2797 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 2798 else 2799 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 2800 2801 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2802 /* Force this rate if needed. */ 2803 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 2804 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 2805 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2806 2807 if (!hasqos) { 2808 /* Use HW sequence numbering for non-QoS frames. */ 2809 if (sc->chip & URTWN_CHIP_88E) 2810 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2811 else 2812 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2813 } else { 2814 /* Set sequence number. */ 2815 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2816 } 2817 2818 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2819 uint8_t cipher; 2820 2821 switch (k->wk_cipher->ic_cipher) { 2822 case IEEE80211_CIPHER_WEP: 2823 case IEEE80211_CIPHER_TKIP: 2824 cipher = R92C_TXDW1_CIPHER_RC4; 2825 break; 2826 case IEEE80211_CIPHER_AES_CCM: 2827 cipher = R92C_TXDW1_CIPHER_AES; 2828 break; 2829 default: 2830 device_printf(sc->sc_dev, "%s: unknown cipher %d\n", 2831 __func__, k->wk_cipher->ic_cipher); 2832 return (EINVAL); 2833 } 2834 2835 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 2836 } 2837 2838 if (ieee80211_radiotap_active_vap(vap)) { 2839 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2840 2841 tap->wt_flags = 0; 2842 if (k != NULL) 2843 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2844 ieee80211_radiotap_tx(vap, m); 2845 } 2846 2847 data->ni = ni; 2848 2849 urtwn_tx_start(sc, m, type, data); 2850 2851 return (0); 2852} 2853 2854static int 2855urtwn_tx_raw(struct urtwn_softc *sc, struct ieee80211_node *ni, 2856 struct mbuf *m, struct urtwn_data *data, 2857 const struct ieee80211_bpf_params *params) 2858{ 2859 struct ieee80211vap *vap = ni->ni_vap; 2860 struct ieee80211_key *k = NULL; 2861 struct ieee80211_frame *wh; 2862 struct r92c_tx_desc *txd; 2863 uint8_t cipher, ridx, type; 2864 2865 /* Encrypt the frame if need be. */ 2866 cipher = R92C_TXDW1_CIPHER_NONE; 2867 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 2868 /* Retrieve key for TX. */ 2869 k = ieee80211_crypto_encap(ni, m); 2870 if (k == NULL) 2871 return (ENOBUFS); 2872 2873 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2874 switch (k->wk_cipher->ic_cipher) { 2875 case IEEE80211_CIPHER_WEP: 2876 case IEEE80211_CIPHER_TKIP: 2877 cipher = R92C_TXDW1_CIPHER_RC4; 2878 break; 2879 case IEEE80211_CIPHER_AES_CCM: 2880 cipher = R92C_TXDW1_CIPHER_AES; 2881 break; 2882 default: 2883 device_printf(sc->sc_dev, 2884 "%s: unknown cipher %d\n", 2885 __func__, k->wk_cipher->ic_cipher); 2886 return (EINVAL); 2887 } 2888 } 2889 } 2890 2891 wh = mtod(m, struct ieee80211_frame *); 2892 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2893 2894 /* Fill Tx descriptor. */ 2895 txd = (struct r92c_tx_desc *)data->buf; 2896 memset(txd, 0, sizeof(*txd)); 2897 2898 txd->txdw0 |= htole32( 2899 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2900 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2901 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2902 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2903 2904 if (params->ibp_flags & IEEE80211_BPF_RTS) 2905 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN); 2906 if (params->ibp_flags & IEEE80211_BPF_CTS) 2907 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF); 2908 if (txd->txdw4 & htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_CTS2SELF)) { 2909 txd->txdw4 |= htole32(R92C_TXDW4_HWRTSEN); 2910 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2911 URTWN_RIDX_OFDM24)); 2912 } 2913 2914 if (sc->chip & URTWN_CHIP_88E) 2915 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 2916 else 2917 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 2918 2919 txd->txdw1 |= htole32(SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT)); 2920 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 2921 2922 /* Choose a TX rate index. */ 2923 ridx = rate2ridx(params->ibp_rate0); 2924 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2925 txd->txdw5 |= htole32(0x0001ff00); 2926 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2927 2928 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 2929 /* Use HW sequence numbering for non-QoS frames. */ 2930 if (sc->chip & URTWN_CHIP_88E) 2931 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2932 else 2933 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2934 } else { 2935 /* Set sequence number. */ 2936 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2937 } 2938 2939 if (ieee80211_radiotap_active_vap(vap)) { 2940 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2941 2942 tap->wt_flags = 0; 2943 if (k != NULL) 2944 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2945 ieee80211_radiotap_tx(vap, m); 2946 } 2947 2948 data->ni = ni; 2949 2950 urtwn_tx_start(sc, m, type, data); 2951 2952 return (0); 2953} 2954 2955static void 2956urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 2957 struct urtwn_data *data) 2958{ 2959 struct usb_xfer *xfer; 2960 struct r92c_tx_desc *txd; 2961 uint16_t ac, sum; 2962 int i, xferlen; 2963 2964 URTWN_ASSERT_LOCKED(sc); 2965 2966 ac = M_WME_GETAC(m); 2967 2968 switch (type) { 2969 case IEEE80211_FC0_TYPE_CTL: 2970 case IEEE80211_FC0_TYPE_MGT: 2971 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 2972 break; 2973 default: 2974 xfer = sc->sc_xfer[wme2queue[ac].qid]; 2975 break; 2976 } 2977 2978 txd = (struct r92c_tx_desc *)data->buf; 2979 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 2980 2981 /* Compute Tx descriptor checksum. */ 2982 sum = 0; 2983 for (i = 0; i < sizeof(*txd) / 2; i++) 2984 sum ^= ((uint16_t *)txd)[i]; 2985 txd->txdsum = sum; /* NB: already little endian. */ 2986 2987 xferlen = sizeof(*txd) + m->m_pkthdr.len; 2988 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 2989 2990 data->buflen = xferlen; 2991 data->m = m; 2992 2993 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 2994 usbd_transfer_start(xfer); 2995} 2996 2997static int 2998urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 2999{ 3000 struct urtwn_softc *sc = ic->ic_softc; 3001 int error; 3002 3003 URTWN_LOCK(sc); 3004 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 3005 URTWN_UNLOCK(sc); 3006 return (ENXIO); 3007 } 3008 error = mbufq_enqueue(&sc->sc_snd, m); 3009 if (error) { 3010 URTWN_UNLOCK(sc); 3011 return (error); 3012 } 3013 urtwn_start(sc); 3014 URTWN_UNLOCK(sc); 3015 3016 return (0); 3017} 3018 3019static void 3020urtwn_start(struct urtwn_softc *sc) 3021{ 3022 struct ieee80211_node *ni; 3023 struct mbuf *m; 3024 struct urtwn_data *bf; 3025 3026 URTWN_ASSERT_LOCKED(sc); 3027 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 3028 bf = urtwn_getbuf(sc); 3029 if (bf == NULL) { 3030 mbufq_prepend(&sc->sc_snd, m); 3031 break; 3032 } 3033 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3034 m->m_pkthdr.rcvif = NULL; 3035 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 3036 if_inc_counter(ni->ni_vap->iv_ifp, 3037 IFCOUNTER_OERRORS, 1); 3038 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3039 m_freem(m); 3040 ieee80211_free_node(ni); 3041 break; 3042 } 3043 sc->sc_txtimer = 5; 3044 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3045 } 3046} 3047 3048static void 3049urtwn_parent(struct ieee80211com *ic) 3050{ 3051 struct urtwn_softc *sc = ic->ic_softc; 3052 3053 URTWN_LOCK(sc); 3054 if (sc->sc_flags & URTWN_DETACHED) { 3055 URTWN_UNLOCK(sc); 3056 return; 3057 } 3058 URTWN_UNLOCK(sc); 3059 3060 if (ic->ic_nrunning > 0) { 3061 if (urtwn_init(sc) != 0) { 3062 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3063 if (vap != NULL) 3064 ieee80211_stop(vap); 3065 } else 3066 ieee80211_start_all(ic); 3067 } else 3068 urtwn_stop(sc); 3069} 3070 3071static __inline int 3072urtwn_power_on(struct urtwn_softc *sc) 3073{ 3074 3075 return sc->sc_power_on(sc); 3076} 3077 3078static int 3079urtwn_r92c_power_on(struct urtwn_softc *sc) 3080{ 3081 uint32_t reg; 3082 usb_error_t error; 3083 int ntries; 3084 3085 /* Wait for autoload done bit. */ 3086 for (ntries = 0; ntries < 1000; ntries++) { 3087 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3088 break; 3089 urtwn_ms_delay(sc); 3090 } 3091 if (ntries == 1000) { 3092 device_printf(sc->sc_dev, 3093 "timeout waiting for chip autoload\n"); 3094 return (ETIMEDOUT); 3095 } 3096 3097 /* Unlock ISO/CLK/Power control register. */ 3098 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3099 if (error != USB_ERR_NORMAL_COMPLETION) 3100 return (EIO); 3101 /* Move SPS into PWM mode. */ 3102 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3103 if (error != USB_ERR_NORMAL_COMPLETION) 3104 return (EIO); 3105 urtwn_ms_delay(sc); 3106 3107 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3108 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3109 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3110 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3111 if (error != USB_ERR_NORMAL_COMPLETION) 3112 return (EIO); 3113 urtwn_ms_delay(sc); 3114 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3115 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3116 ~R92C_SYS_ISO_CTRL_MD2PP); 3117 if (error != USB_ERR_NORMAL_COMPLETION) 3118 return (EIO); 3119 } 3120 3121 /* Auto enable WLAN. */ 3122 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3123 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3124 if (error != USB_ERR_NORMAL_COMPLETION) 3125 return (EIO); 3126 for (ntries = 0; ntries < 1000; ntries++) { 3127 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3128 R92C_APS_FSMCO_APFM_ONMAC)) 3129 break; 3130 urtwn_ms_delay(sc); 3131 } 3132 if (ntries == 1000) { 3133 device_printf(sc->sc_dev, 3134 "timeout waiting for MAC auto ON\n"); 3135 return (ETIMEDOUT); 3136 } 3137 3138 /* Enable radio, GPIO and LED functions. */ 3139 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3140 R92C_APS_FSMCO_AFSM_HSUS | 3141 R92C_APS_FSMCO_PDN_EN | 3142 R92C_APS_FSMCO_PFM_ALDN); 3143 if (error != USB_ERR_NORMAL_COMPLETION) 3144 return (EIO); 3145 /* Release RF digital isolation. */ 3146 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3147 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3148 if (error != USB_ERR_NORMAL_COMPLETION) 3149 return (EIO); 3150 3151 /* Initialize MAC. */ 3152 error = urtwn_write_1(sc, R92C_APSD_CTRL, 3153 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3154 if (error != USB_ERR_NORMAL_COMPLETION) 3155 return (EIO); 3156 for (ntries = 0; ntries < 200; ntries++) { 3157 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3158 R92C_APSD_CTRL_OFF_STATUS)) 3159 break; 3160 urtwn_ms_delay(sc); 3161 } 3162 if (ntries == 200) { 3163 device_printf(sc->sc_dev, 3164 "timeout waiting for MAC initialization\n"); 3165 return (ETIMEDOUT); 3166 } 3167 3168 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3169 reg = urtwn_read_2(sc, R92C_CR); 3170 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3171 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3172 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3173 R92C_CR_ENSEC; 3174 error = urtwn_write_2(sc, R92C_CR, reg); 3175 if (error != USB_ERR_NORMAL_COMPLETION) 3176 return (EIO); 3177 3178 error = urtwn_write_1(sc, 0xfe10, 0x19); 3179 if (error != USB_ERR_NORMAL_COMPLETION) 3180 return (EIO); 3181 return (0); 3182} 3183 3184static int 3185urtwn_r88e_power_on(struct urtwn_softc *sc) 3186{ 3187 uint32_t reg; 3188 usb_error_t error; 3189 int ntries; 3190 3191 /* Wait for power ready bit. */ 3192 for (ntries = 0; ntries < 5000; ntries++) { 3193 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 3194 break; 3195 urtwn_ms_delay(sc); 3196 } 3197 if (ntries == 5000) { 3198 device_printf(sc->sc_dev, 3199 "timeout waiting for chip power up\n"); 3200 return (ETIMEDOUT); 3201 } 3202 3203 /* Reset BB. */ 3204 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3205 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3206 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3207 if (error != USB_ERR_NORMAL_COMPLETION) 3208 return (EIO); 3209 3210 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3211 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3212 if (error != USB_ERR_NORMAL_COMPLETION) 3213 return (EIO); 3214 3215 /* Disable HWPDN. */ 3216 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3217 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3218 if (error != USB_ERR_NORMAL_COMPLETION) 3219 return (EIO); 3220 3221 /* Disable WL suspend. */ 3222 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3223 urtwn_read_2(sc, R92C_APS_FSMCO) & 3224 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 3225 if (error != USB_ERR_NORMAL_COMPLETION) 3226 return (EIO); 3227 3228 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3229 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3230 if (error != USB_ERR_NORMAL_COMPLETION) 3231 return (EIO); 3232 for (ntries = 0; ntries < 5000; ntries++) { 3233 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3234 R92C_APS_FSMCO_APFM_ONMAC)) 3235 break; 3236 urtwn_ms_delay(sc); 3237 } 3238 if (ntries == 5000) 3239 return (ETIMEDOUT); 3240 3241 /* Enable LDO normal mode. */ 3242 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 3243 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~R92C_LPLDO_CTRL_SLEEP); 3244 if (error != USB_ERR_NORMAL_COMPLETION) 3245 return (EIO); 3246 3247 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3248 error = urtwn_write_2(sc, R92C_CR, 0); 3249 if (error != USB_ERR_NORMAL_COMPLETION) 3250 return (EIO); 3251 reg = urtwn_read_2(sc, R92C_CR); 3252 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3253 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3254 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3255 error = urtwn_write_2(sc, R92C_CR, reg); 3256 if (error != USB_ERR_NORMAL_COMPLETION) 3257 return (EIO); 3258 3259 return (0); 3260} 3261 3262static __inline void 3263urtwn_power_off(struct urtwn_softc *sc) 3264{ 3265 3266 return sc->sc_power_off(sc); 3267} 3268 3269static void 3270urtwn_r92c_power_off(struct urtwn_softc *sc) 3271{ 3272 uint32_t reg; 3273 3274 /* Block all Tx queues. */ 3275 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3276 3277 /* Disable RF */ 3278 urtwn_rf_write(sc, 0, 0, 0); 3279 3280 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3281 3282 /* Reset BB state machine */ 3283 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3284 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA | 3285 R92C_SYS_FUNC_EN_BB_GLB_RST); 3286 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3287 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3288 3289 /* 3290 * Reset digital sequence 3291 */ 3292#ifndef URTWN_WITHOUT_UCODE 3293 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3294 /* Reset MCU ready status */ 3295 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3296 3297 /* If firmware in ram code, do reset */ 3298 urtwn_fw_reset(sc); 3299 } 3300#endif 3301 3302 /* Reset MAC and Enable 8051 */ 3303 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 3304 (R92C_SYS_FUNC_EN_CPUEN | 3305 R92C_SYS_FUNC_EN_ELDR | 3306 R92C_SYS_FUNC_EN_HWPDN) >> 8); 3307 3308 /* Reset MCU ready status */ 3309 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3310 3311 /* Disable MAC clock */ 3312 urtwn_write_2(sc, R92C_SYS_CLKR, 3313 R92C_SYS_CLKR_ANAD16V_EN | 3314 R92C_SYS_CLKR_ANA8M | 3315 R92C_SYS_CLKR_LOADER_EN | 3316 R92C_SYS_CLKR_80M_SSC_DIS | 3317 R92C_SYS_CLKR_SYS_EN | 3318 R92C_SYS_CLKR_RING_EN | 3319 0x4000); 3320 3321 /* Disable AFE PLL */ 3322 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3323 3324 /* Gated AFE DIG_CLOCK */ 3325 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3326 3327 /* Isolated digital to PON */ 3328 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3329 R92C_SYS_ISO_CTRL_MD2PP | 3330 R92C_SYS_ISO_CTRL_PA2PCIE | 3331 R92C_SYS_ISO_CTRL_PD2CORE | 3332 R92C_SYS_ISO_CTRL_IP2MAC | 3333 R92C_SYS_ISO_CTRL_DIOP | 3334 R92C_SYS_ISO_CTRL_DIOE); 3335 3336 /* 3337 * Pull GPIO PIN to balance level and LED control 3338 */ 3339 /* 1. Disable GPIO[7:0] */ 3340 urtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000); 3341 3342 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3343 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3344 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3345 3346 /* Disable GPIO[10:8] */ 3347 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x00); 3348 3349 reg = urtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0; 3350 reg |= (((reg & 0x000f) << 4) | 0x0780); 3351 urtwn_write_2(sc, R92C_GPIO_IO_SEL, reg); 3352 3353 /* Disable LED0 & 1 */ 3354 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3355 3356 /* 3357 * Reset digital sequence 3358 */ 3359 /* Disable ELDR clock */ 3360 urtwn_write_2(sc, R92C_SYS_CLKR, 3361 R92C_SYS_CLKR_ANAD16V_EN | 3362 R92C_SYS_CLKR_ANA8M | 3363 R92C_SYS_CLKR_LOADER_EN | 3364 R92C_SYS_CLKR_80M_SSC_DIS | 3365 R92C_SYS_CLKR_SYS_EN | 3366 R92C_SYS_CLKR_RING_EN | 3367 0x4000); 3368 3369 /* Isolated ELDR to PON */ 3370 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 3371 (R92C_SYS_ISO_CTRL_DIOR | 3372 R92C_SYS_ISO_CTRL_PWC_EV12V) >> 8); 3373 3374 /* 3375 * Disable analog sequence 3376 */ 3377 /* Disable A15 power */ 3378 urtwn_write_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_OBUF); 3379 /* Disable digital core power */ 3380 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3381 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3382 ~R92C_LDOV12D_CTRL_LDV12_EN); 3383 3384 /* Enter PFM mode */ 3385 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3386 3387 /* Set USB suspend */ 3388 urtwn_write_2(sc, R92C_APS_FSMCO, 3389 R92C_APS_FSMCO_APDM_HOST | 3390 R92C_APS_FSMCO_AFSM_HSUS | 3391 R92C_APS_FSMCO_PFM_ALDN); 3392 3393 /* Lock ISO/CLK/Power control register. */ 3394 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 3395} 3396 3397static void 3398urtwn_r88e_power_off(struct urtwn_softc *sc) 3399{ 3400 uint8_t reg; 3401 int ntries; 3402 3403 /* Disable any kind of TX reports. */ 3404 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 3405 urtwn_read_1(sc, R88E_TX_RPT_CTRL) & 3406 ~(R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA)); 3407 3408 /* Stop Rx. */ 3409 urtwn_write_1(sc, R92C_CR, 0); 3410 3411 /* Move card to Low Power State. */ 3412 /* Block all Tx queues. */ 3413 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3414 3415 for (ntries = 0; ntries < 20; ntries++) { 3416 /* Should be zero if no packet is transmitting. */ 3417 if (urtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 3418 break; 3419 3420 urtwn_ms_delay(sc); 3421 } 3422 if (ntries == 20) { 3423 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 3424 __func__); 3425 return; 3426 } 3427 3428 /* CCK and OFDM are disabled, and clock are gated. */ 3429 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3430 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_BBRSTB); 3431 3432 urtwn_ms_delay(sc); 3433 3434 /* Reset MAC TRX */ 3435 urtwn_write_1(sc, R92C_CR, 3436 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3437 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | 3438 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN); 3439 3440 /* check if removed later */ 3441 urtwn_write_1(sc, R92C_CR + 1, 3442 urtwn_read_1(sc, R92C_CR + 1) & ~(R92C_CR_ENSEC >> 8)); 3443 3444 /* Respond TxOK to scheduler */ 3445 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 3446 urtwn_read_1(sc, R92C_DUAL_TSF_RST) | 0x20); 3447 3448 /* If firmware in ram code, do reset. */ 3449#ifndef URTWN_WITHOUT_UCODE 3450 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) 3451 urtwn_r88e_fw_reset(sc); 3452#endif 3453 3454 /* Reset MCU ready status. */ 3455 urtwn_write_1(sc, R92C_MCUFWDL, 0x00); 3456 3457 /* Disable 32k. */ 3458 urtwn_write_1(sc, R88E_32K_CTRL, 3459 urtwn_read_1(sc, R88E_32K_CTRL) & ~0x01); 3460 3461 /* Move card to Disabled state. */ 3462 /* Turn off RF. */ 3463 urtwn_write_1(sc, R92C_RF_CTRL, 0); 3464 3465 /* LDO Sleep mode. */ 3466 urtwn_write_1(sc, R92C_LPLDO_CTRL, 3467 urtwn_read_1(sc, R92C_LPLDO_CTRL) | R92C_LPLDO_CTRL_SLEEP); 3468 3469 /* Turn off MAC by HW state machine */ 3470 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3471 urtwn_read_1(sc, R92C_APS_FSMCO + 1) | 3472 (R92C_APS_FSMCO_APFM_OFF >> 8)); 3473 3474 for (ntries = 0; ntries < 20; ntries++) { 3475 /* Wait until it will be disabled. */ 3476 if ((urtwn_read_1(sc, R92C_APS_FSMCO + 1) & 3477 (R92C_APS_FSMCO_APFM_OFF >> 8)) == 0) 3478 break; 3479 3480 urtwn_ms_delay(sc); 3481 } 3482 if (ntries == 20) { 3483 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 3484 __func__); 3485 return; 3486 } 3487 3488 /* schmit trigger */ 3489 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3490 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3491 3492 /* Enable WL suspend. */ 3493 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3494 (urtwn_read_1(sc, R92C_APS_FSMCO + 1) & ~0x10) | 0x08); 3495 3496 /* Enable bandgap mbias in suspend. */ 3497 urtwn_write_1(sc, R92C_APS_FSMCO + 3, 0); 3498 3499 /* Clear SIC_EN register. */ 3500 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 1, 3501 urtwn_read_1(sc, R92C_GPIO_MUXCFG + 1) & ~0x10); 3502 3503 /* Set USB suspend enable local register */ 3504 urtwn_write_1(sc, R92C_USB_SUSPEND, 3505 urtwn_read_1(sc, R92C_USB_SUSPEND) | 0x10); 3506 3507 /* Reset MCU IO Wrapper. */ 3508 reg = urtwn_read_1(sc, R92C_RSV_CTRL + 1); 3509 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08); 3510 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08); 3511 3512 /* marked as 'For Power Consumption' code. */ 3513 urtwn_write_1(sc, R92C_GPIO_OUT, urtwn_read_1(sc, R92C_GPIO_IN)); 3514 urtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff); 3515 3516 urtwn_write_1(sc, R92C_GPIO_IO_SEL, 3517 urtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4); 3518 urtwn_write_1(sc, R92C_GPIO_MOD, 3519 urtwn_read_1(sc, R92C_GPIO_MOD) | 0x0f); 3520 3521 /* Set LNA, TRSW, EX_PA Pin to output mode. */ 3522 urtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808); 3523} 3524 3525static int 3526urtwn_llt_init(struct urtwn_softc *sc) 3527{ 3528 int i, error, page_count, pktbuf_count; 3529 3530 page_count = (sc->chip & URTWN_CHIP_88E) ? 3531 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 3532 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 3533 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 3534 3535 /* Reserve pages [0; page_count]. */ 3536 for (i = 0; i < page_count; i++) { 3537 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3538 return (error); 3539 } 3540 /* NB: 0xff indicates end-of-list. */ 3541 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3542 return (error); 3543 /* 3544 * Use pages [page_count + 1; pktbuf_count - 1] 3545 * as ring buffer. 3546 */ 3547 for (++i; i < pktbuf_count - 1; i++) { 3548 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3549 return (error); 3550 } 3551 /* Make the last page point to the beginning of the ring buffer. */ 3552 error = urtwn_llt_write(sc, i, page_count + 1); 3553 return (error); 3554} 3555 3556#ifndef URTWN_WITHOUT_UCODE 3557static void 3558urtwn_fw_reset(struct urtwn_softc *sc) 3559{ 3560 uint16_t reg; 3561 int ntries; 3562 3563 /* Tell 8051 to reset itself. */ 3564 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3565 3566 /* Wait until 8051 resets by itself. */ 3567 for (ntries = 0; ntries < 100; ntries++) { 3568 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3569 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3570 return; 3571 urtwn_ms_delay(sc); 3572 } 3573 /* Force 8051 reset. */ 3574 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3575} 3576 3577static void 3578urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3579{ 3580 uint16_t reg; 3581 3582 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3583 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3584 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3585} 3586 3587static int 3588urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 3589{ 3590 uint32_t reg; 3591 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 3592 int off, mlen; 3593 3594 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3595 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3596 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3597 3598 off = R92C_FW_START_ADDR; 3599 while (len > 0) { 3600 if (len > 196) 3601 mlen = 196; 3602 else if (len > 4) 3603 mlen = 4; 3604 else 3605 mlen = 1; 3606 /* XXX fix this deconst */ 3607 error = urtwn_write_region_1(sc, off, 3608 __DECONST(uint8_t *, buf), mlen); 3609 if (error != USB_ERR_NORMAL_COMPLETION) 3610 break; 3611 off += mlen; 3612 buf += mlen; 3613 len -= mlen; 3614 } 3615 return (error); 3616} 3617 3618static int 3619urtwn_load_firmware(struct urtwn_softc *sc) 3620{ 3621 const struct firmware *fw; 3622 const struct r92c_fw_hdr *hdr; 3623 const char *imagename; 3624 const u_char *ptr; 3625 size_t len; 3626 uint32_t reg; 3627 int mlen, ntries, page, error; 3628 3629 URTWN_UNLOCK(sc); 3630 /* Read firmware image from the filesystem. */ 3631 if (sc->chip & URTWN_CHIP_88E) 3632 imagename = "urtwn-rtl8188eufw"; 3633 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3634 URTWN_CHIP_UMC_A_CUT) 3635 imagename = "urtwn-rtl8192cfwU"; 3636 else 3637 imagename = "urtwn-rtl8192cfwT"; 3638 3639 fw = firmware_get(imagename); 3640 URTWN_LOCK(sc); 3641 if (fw == NULL) { 3642 device_printf(sc->sc_dev, 3643 "failed loadfirmware of file %s\n", imagename); 3644 return (ENOENT); 3645 } 3646 3647 len = fw->datasize; 3648 3649 if (len < sizeof(*hdr)) { 3650 device_printf(sc->sc_dev, "firmware too short\n"); 3651 error = EINVAL; 3652 goto fail; 3653 } 3654 ptr = fw->data; 3655 hdr = (const struct r92c_fw_hdr *)ptr; 3656 /* Check if there is a valid FW header and skip it. */ 3657 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3658 (le16toh(hdr->signature) >> 4) == 0x88e || 3659 (le16toh(hdr->signature) >> 4) == 0x92c) { 3660 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, 3661 "FW V%d.%d %02d-%02d %02d:%02d\n", 3662 le16toh(hdr->version), le16toh(hdr->subversion), 3663 hdr->month, hdr->date, hdr->hour, hdr->minute); 3664 ptr += sizeof(*hdr); 3665 len -= sizeof(*hdr); 3666 } 3667 3668 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3669 if (sc->chip & URTWN_CHIP_88E) 3670 urtwn_r88e_fw_reset(sc); 3671 else 3672 urtwn_fw_reset(sc); 3673 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3674 } 3675 3676 if (!(sc->chip & URTWN_CHIP_88E)) { 3677 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3678 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3679 R92C_SYS_FUNC_EN_CPUEN); 3680 } 3681 urtwn_write_1(sc, R92C_MCUFWDL, 3682 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3683 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3684 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3685 3686 /* Reset the FWDL checksum. */ 3687 urtwn_write_1(sc, R92C_MCUFWDL, 3688 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3689 3690 for (page = 0; len > 0; page++) { 3691 mlen = min(len, R92C_FW_PAGE_SIZE); 3692 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3693 if (error != 0) { 3694 device_printf(sc->sc_dev, 3695 "could not load firmware page\n"); 3696 goto fail; 3697 } 3698 ptr += mlen; 3699 len -= mlen; 3700 } 3701 urtwn_write_1(sc, R92C_MCUFWDL, 3702 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3703 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3704 3705 /* Wait for checksum report. */ 3706 for (ntries = 0; ntries < 1000; ntries++) { 3707 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3708 break; 3709 urtwn_ms_delay(sc); 3710 } 3711 if (ntries == 1000) { 3712 device_printf(sc->sc_dev, 3713 "timeout waiting for checksum report\n"); 3714 error = ETIMEDOUT; 3715 goto fail; 3716 } 3717 3718 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3719 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3720 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3721 if (sc->chip & URTWN_CHIP_88E) 3722 urtwn_r88e_fw_reset(sc); 3723 /* Wait for firmware readiness. */ 3724 for (ntries = 0; ntries < 1000; ntries++) { 3725 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3726 break; 3727 urtwn_ms_delay(sc); 3728 } 3729 if (ntries == 1000) { 3730 device_printf(sc->sc_dev, 3731 "timeout waiting for firmware readiness\n"); 3732 error = ETIMEDOUT; 3733 goto fail; 3734 } 3735fail: 3736 firmware_put(fw, FIRMWARE_UNLOAD); 3737 return (error); 3738} 3739#endif 3740 3741static int 3742urtwn_dma_init(struct urtwn_softc *sc) 3743{ 3744 struct usb_endpoint *ep, *ep_end; 3745 usb_error_t usb_err; 3746 uint32_t reg; 3747 int hashq, hasnq, haslq, nqueues, ntx; 3748 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 3749 3750 /* Initialize LLT table. */ 3751 error = urtwn_llt_init(sc); 3752 if (error != 0) 3753 return (error); 3754 3755 /* Determine the number of bulk-out pipes. */ 3756 ntx = 0; 3757 ep = sc->sc_udev->endpoints; 3758 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 3759 for (; ep != ep_end; ep++) { 3760 if ((ep->edesc == NULL) || 3761 (ep->iface_index != sc->sc_iface_index)) 3762 continue; 3763 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 3764 ntx++; 3765 } 3766 if (ntx == 0) { 3767 device_printf(sc->sc_dev, 3768 "%d: invalid number of Tx bulk pipes\n", ntx); 3769 return (EIO); 3770 } 3771 3772 /* Get Tx queues to USB endpoints mapping. */ 3773 hashq = hasnq = haslq = nqueues = 0; 3774 switch (ntx) { 3775 case 1: hashq = 1; break; 3776 case 2: hashq = hasnq = 1; break; 3777 case 3: case 4: hashq = hasnq = haslq = 1; break; 3778 } 3779 nqueues = hashq + hasnq + haslq; 3780 if (nqueues == 0) 3781 return (EIO); 3782 3783 npubqpages = nqpages = nrempages = pagecount = 0; 3784 if (sc->chip & URTWN_CHIP_88E) 3785 tx_boundary = R88E_TX_PAGE_BOUNDARY; 3786 else { 3787 pagecount = R92C_TX_PAGE_COUNT; 3788 npubqpages = R92C_PUBQ_NPAGES; 3789 tx_boundary = R92C_TX_PAGE_BOUNDARY; 3790 } 3791 3792 /* Set number of pages for normal priority queue. */ 3793 if (sc->chip & URTWN_CHIP_88E) { 3794 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 3795 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3796 return (EIO); 3797 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3798 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3799 return (EIO); 3800 } else { 3801 /* Get the number of pages for each queue. */ 3802 nqpages = (pagecount - npubqpages) / nqueues; 3803 /* 3804 * The remaining pages are assigned to the high priority 3805 * queue. 3806 */ 3807 nrempages = (pagecount - npubqpages) % nqueues; 3808 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3809 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3810 return (EIO); 3811 usb_err = urtwn_write_4(sc, R92C_RQPN, 3812 /* Set number of pages for public queue. */ 3813 SM(R92C_RQPN_PUBQ, npubqpages) | 3814 /* Set number of pages for high priority queue. */ 3815 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3816 /* Set number of pages for low priority queue. */ 3817 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3818 /* Load values. */ 3819 R92C_RQPN_LD); 3820 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3821 return (EIO); 3822 } 3823 3824 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 3825 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3826 return (EIO); 3827 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 3828 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3829 return (EIO); 3830 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 3831 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3832 return (EIO); 3833 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 3834 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3835 return (EIO); 3836 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 3837 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3838 return (EIO); 3839 3840 /* Set queue to USB pipe mapping. */ 3841 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3842 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3843 if (nqueues == 1) { 3844 if (hashq) 3845 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3846 else if (hasnq) 3847 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3848 else 3849 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3850 } else if (nqueues == 2) { 3851 /* 3852 * All 2-endpoints configs have high and normal 3853 * priority queues. 3854 */ 3855 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3856 } else 3857 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3858 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3859 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3860 return (EIO); 3861 3862 /* Set Tx/Rx transfer page boundary. */ 3863 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 3864 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 3865 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3866 return (EIO); 3867 3868 /* Set Tx/Rx transfer page size. */ 3869 usb_err = urtwn_write_1(sc, R92C_PBP, 3870 SM(R92C_PBP_PSRX, R92C_PBP_128) | 3871 SM(R92C_PBP_PSTX, R92C_PBP_128)); 3872 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3873 return (EIO); 3874 3875 return (0); 3876} 3877 3878static int 3879urtwn_mac_init(struct urtwn_softc *sc) 3880{ 3881 usb_error_t error; 3882 int i; 3883 3884 /* Write MAC initialization values. */ 3885 if (sc->chip & URTWN_CHIP_88E) { 3886 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 3887 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3888 rtl8188eu_mac[i].val); 3889 if (error != USB_ERR_NORMAL_COMPLETION) 3890 return (EIO); 3891 } 3892 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 3893 } else { 3894 for (i = 0; i < nitems(rtl8192cu_mac); i++) 3895 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3896 rtl8192cu_mac[i].val); 3897 if (error != USB_ERR_NORMAL_COMPLETION) 3898 return (EIO); 3899 } 3900 3901 return (0); 3902} 3903 3904static void 3905urtwn_bb_init(struct urtwn_softc *sc) 3906{ 3907 const struct urtwn_bb_prog *prog; 3908 uint32_t reg; 3909 uint8_t crystalcap; 3910 int i; 3911 3912 /* Enable BB and RF. */ 3913 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3914 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3915 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3916 R92C_SYS_FUNC_EN_DIO_RF); 3917 3918 if (!(sc->chip & URTWN_CHIP_88E)) 3919 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 3920 3921 urtwn_write_1(sc, R92C_RF_CTRL, 3922 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3923 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3924 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3925 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3926 3927 if (!(sc->chip & URTWN_CHIP_88E)) { 3928 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3929 urtwn_write_1(sc, 0x15, 0xe9); 3930 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3931 } 3932 3933 /* Select BB programming based on board type. */ 3934 if (sc->chip & URTWN_CHIP_88E) 3935 prog = &rtl8188eu_bb_prog; 3936 else if (!(sc->chip & URTWN_CHIP_92C)) { 3937 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3938 prog = &rtl8188ce_bb_prog; 3939 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3940 prog = &rtl8188ru_bb_prog; 3941 else 3942 prog = &rtl8188cu_bb_prog; 3943 } else { 3944 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3945 prog = &rtl8192ce_bb_prog; 3946 else 3947 prog = &rtl8192cu_bb_prog; 3948 } 3949 /* Write BB initialization values. */ 3950 for (i = 0; i < prog->count; i++) { 3951 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3952 urtwn_ms_delay(sc); 3953 } 3954 3955 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3956 /* 8192C 1T only configuration. */ 3957 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3958 reg = (reg & ~0x00000003) | 0x2; 3959 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3960 3961 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3962 reg = (reg & ~0x00300033) | 0x00200022; 3963 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3964 3965 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3966 reg = (reg & ~0xff000000) | 0x45 << 24; 3967 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3968 3969 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3970 reg = (reg & ~0x000000ff) | 0x23; 3971 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3972 3973 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3974 reg = (reg & ~0x00000030) | 1 << 4; 3975 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3976 3977 reg = urtwn_bb_read(sc, 0xe74); 3978 reg = (reg & ~0x0c000000) | 2 << 26; 3979 urtwn_bb_write(sc, 0xe74, reg); 3980 reg = urtwn_bb_read(sc, 0xe78); 3981 reg = (reg & ~0x0c000000) | 2 << 26; 3982 urtwn_bb_write(sc, 0xe78, reg); 3983 reg = urtwn_bb_read(sc, 0xe7c); 3984 reg = (reg & ~0x0c000000) | 2 << 26; 3985 urtwn_bb_write(sc, 0xe7c, reg); 3986 reg = urtwn_bb_read(sc, 0xe80); 3987 reg = (reg & ~0x0c000000) | 2 << 26; 3988 urtwn_bb_write(sc, 0xe80, reg); 3989 reg = urtwn_bb_read(sc, 0xe88); 3990 reg = (reg & ~0x0c000000) | 2 << 26; 3991 urtwn_bb_write(sc, 0xe88, reg); 3992 } 3993 3994 /* Write AGC values. */ 3995 for (i = 0; i < prog->agccount; i++) { 3996 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 3997 prog->agcvals[i]); 3998 urtwn_ms_delay(sc); 3999 } 4000 4001 if (sc->chip & URTWN_CHIP_88E) { 4002 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4003 urtwn_ms_delay(sc); 4004 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4005 urtwn_ms_delay(sc); 4006 4007 crystalcap = sc->rom.r88e_rom.crystalcap; 4008 if (crystalcap == 0xff) 4009 crystalcap = 0x20; 4010 crystalcap &= 0x3f; 4011 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4012 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4013 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4014 crystalcap | crystalcap << 6)); 4015 } else { 4016 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4017 R92C_HSSI_PARAM2_CCK_HIPWR) 4018 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 4019 } 4020} 4021 4022static void 4023urtwn_rf_init(struct urtwn_softc *sc) 4024{ 4025 const struct urtwn_rf_prog *prog; 4026 uint32_t reg, type; 4027 int i, j, idx, off; 4028 4029 /* Select RF programming based on board type. */ 4030 if (sc->chip & URTWN_CHIP_88E) 4031 prog = rtl8188eu_rf_prog; 4032 else if (!(sc->chip & URTWN_CHIP_92C)) { 4033 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4034 prog = rtl8188ce_rf_prog; 4035 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4036 prog = rtl8188ru_rf_prog; 4037 else 4038 prog = rtl8188cu_rf_prog; 4039 } else 4040 prog = rtl8192ce_rf_prog; 4041 4042 for (i = 0; i < sc->nrxchains; i++) { 4043 /* Save RF_ENV control type. */ 4044 idx = i / 2; 4045 off = (i % 2) * 16; 4046 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4047 type = (reg >> off) & 0x10; 4048 4049 /* Set RF_ENV enable. */ 4050 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4051 reg |= 0x100000; 4052 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4053 urtwn_ms_delay(sc); 4054 /* Set RF_ENV output high. */ 4055 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4056 reg |= 0x10; 4057 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4058 urtwn_ms_delay(sc); 4059 /* Set address and data lengths of RF registers. */ 4060 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4061 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4062 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4063 urtwn_ms_delay(sc); 4064 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4065 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4066 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4067 urtwn_ms_delay(sc); 4068 4069 /* Write RF initialization values for this chain. */ 4070 for (j = 0; j < prog[i].count; j++) { 4071 if (prog[i].regs[j] >= 0xf9 && 4072 prog[i].regs[j] <= 0xfe) { 4073 /* 4074 * These are fake RF registers offsets that 4075 * indicate a delay is required. 4076 */ 4077 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 4078 continue; 4079 } 4080 urtwn_rf_write(sc, i, prog[i].regs[j], 4081 prog[i].vals[j]); 4082 urtwn_ms_delay(sc); 4083 } 4084 4085 /* Restore RF_ENV control type. */ 4086 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4087 reg &= ~(0x10 << off) | (type << off); 4088 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 4089 4090 /* Cache RF register CHNLBW. */ 4091 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4092 } 4093 4094 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4095 URTWN_CHIP_UMC_A_CUT) { 4096 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4097 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4098 } 4099} 4100 4101static void 4102urtwn_cam_init(struct urtwn_softc *sc) 4103{ 4104 /* Invalidate all CAM entries. */ 4105 urtwn_write_4(sc, R92C_CAMCMD, 4106 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4107} 4108 4109static int 4110urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 4111{ 4112 usb_error_t error; 4113 4114 error = urtwn_write_4(sc, R92C_CAMWRITE, data); 4115 if (error != USB_ERR_NORMAL_COMPLETION) 4116 return (EIO); 4117 error = urtwn_write_4(sc, R92C_CAMCMD, 4118 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 4119 SM(R92C_CAMCMD_ADDR, addr)); 4120 if (error != USB_ERR_NORMAL_COMPLETION) 4121 return (EIO); 4122 4123 return (0); 4124} 4125 4126static void 4127urtwn_pa_bias_init(struct urtwn_softc *sc) 4128{ 4129 uint8_t reg; 4130 int i; 4131 4132 for (i = 0; i < sc->nrxchains; i++) { 4133 if (sc->pa_setting & (1 << i)) 4134 continue; 4135 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4136 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4137 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4138 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4139 } 4140 if (!(sc->pa_setting & 0x10)) { 4141 reg = urtwn_read_1(sc, 0x16); 4142 reg = (reg & ~0xf0) | 0x90; 4143 urtwn_write_1(sc, 0x16, reg); 4144 } 4145} 4146 4147static void 4148urtwn_rxfilter_init(struct urtwn_softc *sc) 4149{ 4150 struct ieee80211com *ic = &sc->sc_ic; 4151 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4152 uint32_t rcr; 4153 uint16_t filter; 4154 4155 URTWN_ASSERT_LOCKED(sc); 4156 4157 /* Accept all multicast frames. */ 4158 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4159 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4160 4161 /* Filter for management frames. */ 4162 filter = 0x7f3f; 4163 switch (vap->iv_opmode) { 4164 case IEEE80211_M_STA: 4165 filter &= ~( 4166 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 4167 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 4168 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 4169 break; 4170 case IEEE80211_M_HOSTAP: 4171 filter &= ~( 4172 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 4173 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP)); 4174 break; 4175 case IEEE80211_M_MONITOR: 4176 case IEEE80211_M_IBSS: 4177 break; 4178 default: 4179 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4180 __func__, vap->iv_opmode); 4181 break; 4182 } 4183 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 4184 4185 /* Reject all control frames. */ 4186 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4187 4188 /* Reject all data frames. */ 4189 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 4190 4191 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 4192 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 4193 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 4194 4195 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 4196 /* Accept all frames. */ 4197 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 4198 R92C_RCR_AAP; 4199 } 4200 4201 /* Set Rx filter. */ 4202 urtwn_write_4(sc, R92C_RCR, rcr); 4203 4204 if (ic->ic_promisc != 0) { 4205 /* Update Rx filter. */ 4206 urtwn_set_promisc(sc); 4207 } 4208} 4209 4210static void 4211urtwn_edca_init(struct urtwn_softc *sc) 4212{ 4213 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4214 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4215 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4216 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4217 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4218 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4219 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4220 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4221} 4222 4223static void 4224urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4225 uint16_t power[URTWN_RIDX_COUNT]) 4226{ 4227 uint32_t reg; 4228 4229 /* Write per-CCK rate Tx power. */ 4230 if (chain == 0) { 4231 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4232 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4233 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4234 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4235 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4236 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4237 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4238 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4239 } else { 4240 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4241 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4242 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4243 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4244 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4245 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4246 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4247 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4248 } 4249 /* Write per-OFDM rate Tx power. */ 4250 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4251 SM(R92C_TXAGC_RATE06, power[ 4]) | 4252 SM(R92C_TXAGC_RATE09, power[ 5]) | 4253 SM(R92C_TXAGC_RATE12, power[ 6]) | 4254 SM(R92C_TXAGC_RATE18, power[ 7])); 4255 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4256 SM(R92C_TXAGC_RATE24, power[ 8]) | 4257 SM(R92C_TXAGC_RATE36, power[ 9]) | 4258 SM(R92C_TXAGC_RATE48, power[10]) | 4259 SM(R92C_TXAGC_RATE54, power[11])); 4260 /* Write per-MCS Tx power. */ 4261 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4262 SM(R92C_TXAGC_MCS00, power[12]) | 4263 SM(R92C_TXAGC_MCS01, power[13]) | 4264 SM(R92C_TXAGC_MCS02, power[14]) | 4265 SM(R92C_TXAGC_MCS03, power[15])); 4266 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4267 SM(R92C_TXAGC_MCS04, power[16]) | 4268 SM(R92C_TXAGC_MCS05, power[17]) | 4269 SM(R92C_TXAGC_MCS06, power[18]) | 4270 SM(R92C_TXAGC_MCS07, power[19])); 4271 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4272 SM(R92C_TXAGC_MCS08, power[20]) | 4273 SM(R92C_TXAGC_MCS09, power[21]) | 4274 SM(R92C_TXAGC_MCS10, power[22]) | 4275 SM(R92C_TXAGC_MCS11, power[23])); 4276 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4277 SM(R92C_TXAGC_MCS12, power[24]) | 4278 SM(R92C_TXAGC_MCS13, power[25]) | 4279 SM(R92C_TXAGC_MCS14, power[26]) | 4280 SM(R92C_TXAGC_MCS15, power[27])); 4281} 4282 4283static void 4284urtwn_get_txpower(struct urtwn_softc *sc, int chain, 4285 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4286 uint16_t power[URTWN_RIDX_COUNT]) 4287{ 4288 struct ieee80211com *ic = &sc->sc_ic; 4289 struct r92c_rom *rom = &sc->rom.r92c_rom; 4290 uint16_t cckpow, ofdmpow, htpow, diff, max; 4291 const struct urtwn_txpwr *base; 4292 int ridx, chan, group; 4293 4294 /* Determine channel group. */ 4295 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4296 if (chan <= 3) 4297 group = 0; 4298 else if (chan <= 9) 4299 group = 1; 4300 else 4301 group = 2; 4302 4303 /* Get original Tx power based on board type and RF chain. */ 4304 if (!(sc->chip & URTWN_CHIP_92C)) { 4305 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4306 base = &rtl8188ru_txagc[chain]; 4307 else 4308 base = &rtl8192cu_txagc[chain]; 4309 } else 4310 base = &rtl8192cu_txagc[chain]; 4311 4312 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4313 if (sc->regulatory == 0) { 4314 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4315 power[ridx] = base->pwr[0][ridx]; 4316 } 4317 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4318 if (sc->regulatory == 3) { 4319 power[ridx] = base->pwr[0][ridx]; 4320 /* Apply vendor limits. */ 4321 if (extc != NULL) 4322 max = rom->ht40_max_pwr[group]; 4323 else 4324 max = rom->ht20_max_pwr[group]; 4325 max = (max >> (chain * 4)) & 0xf; 4326 if (power[ridx] > max) 4327 power[ridx] = max; 4328 } else if (sc->regulatory == 1) { 4329 if (extc == NULL) 4330 power[ridx] = base->pwr[group][ridx]; 4331 } else if (sc->regulatory != 2) 4332 power[ridx] = base->pwr[0][ridx]; 4333 } 4334 4335 /* Compute per-CCK rate Tx power. */ 4336 cckpow = rom->cck_tx_pwr[chain][group]; 4337 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4338 power[ridx] += cckpow; 4339 if (power[ridx] > R92C_MAX_TX_PWR) 4340 power[ridx] = R92C_MAX_TX_PWR; 4341 } 4342 4343 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4344 if (sc->ntxchains > 1) { 4345 /* Apply reduction for 2 spatial streams. */ 4346 diff = rom->ht40_2s_tx_pwr_diff[group]; 4347 diff = (diff >> (chain * 4)) & 0xf; 4348 htpow = (htpow > diff) ? htpow - diff : 0; 4349 } 4350 4351 /* Compute per-OFDM rate Tx power. */ 4352 diff = rom->ofdm_tx_pwr_diff[group]; 4353 diff = (diff >> (chain * 4)) & 0xf; 4354 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4355 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4356 power[ridx] += ofdmpow; 4357 if (power[ridx] > R92C_MAX_TX_PWR) 4358 power[ridx] = R92C_MAX_TX_PWR; 4359 } 4360 4361 /* Compute per-MCS Tx power. */ 4362 if (extc == NULL) { 4363 diff = rom->ht20_tx_pwr_diff[group]; 4364 diff = (diff >> (chain * 4)) & 0xf; 4365 htpow += diff; /* HT40->HT20 correction. */ 4366 } 4367 for (ridx = 12; ridx <= 27; ridx++) { 4368 power[ridx] += htpow; 4369 if (power[ridx] > R92C_MAX_TX_PWR) 4370 power[ridx] = R92C_MAX_TX_PWR; 4371 } 4372#ifdef USB_DEBUG 4373 if (sc->sc_debug & URTWN_DEBUG_TXPWR) { 4374 /* Dump per-rate Tx power values. */ 4375 printf("Tx power for chain %d:\n", chain); 4376 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 4377 printf("Rate %d = %u\n", ridx, power[ridx]); 4378 } 4379#endif 4380} 4381 4382static void 4383urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 4384 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4385 uint16_t power[URTWN_RIDX_COUNT]) 4386{ 4387 struct ieee80211com *ic = &sc->sc_ic; 4388 struct r88e_rom *rom = &sc->rom.r88e_rom; 4389 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4390 const struct urtwn_r88e_txpwr *base; 4391 int ridx, chan, group; 4392 4393 /* Determine channel group. */ 4394 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4395 if (chan <= 2) 4396 group = 0; 4397 else if (chan <= 5) 4398 group = 1; 4399 else if (chan <= 8) 4400 group = 2; 4401 else if (chan <= 11) 4402 group = 3; 4403 else if (chan <= 13) 4404 group = 4; 4405 else 4406 group = 5; 4407 4408 /* Get original Tx power based on board type and RF chain. */ 4409 base = &rtl8188eu_txagc[chain]; 4410 4411 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4412 if (sc->regulatory == 0) { 4413 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4414 power[ridx] = base->pwr[0][ridx]; 4415 } 4416 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4417 if (sc->regulatory == 3) 4418 power[ridx] = base->pwr[0][ridx]; 4419 else if (sc->regulatory == 1) { 4420 if (extc == NULL) 4421 power[ridx] = base->pwr[group][ridx]; 4422 } else if (sc->regulatory != 2) 4423 power[ridx] = base->pwr[0][ridx]; 4424 } 4425 4426 /* Compute per-CCK rate Tx power. */ 4427 cckpow = rom->cck_tx_pwr[group]; 4428 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4429 power[ridx] += cckpow; 4430 if (power[ridx] > R92C_MAX_TX_PWR) 4431 power[ridx] = R92C_MAX_TX_PWR; 4432 } 4433 4434 htpow = rom->ht40_tx_pwr[group]; 4435 4436 /* Compute per-OFDM rate Tx power. */ 4437 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4438 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4439 power[ridx] += ofdmpow; 4440 if (power[ridx] > R92C_MAX_TX_PWR) 4441 power[ridx] = R92C_MAX_TX_PWR; 4442 } 4443 4444 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4445 for (ridx = 12; ridx <= 27; ridx++) { 4446 power[ridx] += bw20pow; 4447 if (power[ridx] > R92C_MAX_TX_PWR) 4448 power[ridx] = R92C_MAX_TX_PWR; 4449 } 4450} 4451 4452static void 4453urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 4454 struct ieee80211_channel *extc) 4455{ 4456 uint16_t power[URTWN_RIDX_COUNT]; 4457 int i; 4458 4459 for (i = 0; i < sc->ntxchains; i++) { 4460 /* Compute per-rate Tx power values. */ 4461 if (sc->chip & URTWN_CHIP_88E) 4462 urtwn_r88e_get_txpower(sc, i, c, extc, power); 4463 else 4464 urtwn_get_txpower(sc, i, c, extc, power); 4465 /* Write per-rate Tx power values to hardware. */ 4466 urtwn_write_txpower(sc, i, power); 4467 } 4468} 4469 4470static void 4471urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 4472{ 4473 uint32_t reg; 4474 4475 reg = urtwn_read_4(sc, R92C_RCR); 4476 if (enable) 4477 reg &= ~R92C_RCR_CBSSID_BCN; 4478 else 4479 reg |= R92C_RCR_CBSSID_BCN; 4480 urtwn_write_4(sc, R92C_RCR, reg); 4481} 4482 4483static void 4484urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 4485{ 4486 uint32_t reg; 4487 4488 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 4489 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4490 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 4491 4492 if (!(sc->chip & URTWN_CHIP_88E)) { 4493 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 4494 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4495 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 4496 } 4497} 4498 4499static void 4500urtwn_scan_start(struct ieee80211com *ic) 4501{ 4502 struct urtwn_softc *sc = ic->ic_softc; 4503 4504 URTWN_LOCK(sc); 4505 /* Receive beacons / probe responses from any BSSID. */ 4506 if (ic->ic_opmode != IEEE80211_M_IBSS) 4507 urtwn_set_rx_bssid_all(sc, 1); 4508 4509 /* Set gain for scanning. */ 4510 urtwn_set_gain(sc, 0x20); 4511 URTWN_UNLOCK(sc); 4512} 4513 4514static void 4515urtwn_scan_end(struct ieee80211com *ic) 4516{ 4517 struct urtwn_softc *sc = ic->ic_softc; 4518 4519 URTWN_LOCK(sc); 4520 /* Restore limitations. */ 4521 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 4522 urtwn_set_rx_bssid_all(sc, 0); 4523 4524 /* Set gain under link. */ 4525 urtwn_set_gain(sc, 0x32); 4526 URTWN_UNLOCK(sc); 4527} 4528 4529static void 4530urtwn_set_channel(struct ieee80211com *ic) 4531{ 4532 struct urtwn_softc *sc = ic->ic_softc; 4533 struct ieee80211_channel *c = ic->ic_curchan; 4534 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4535 4536 URTWN_LOCK(sc); 4537 if (vap->iv_state == IEEE80211_S_SCAN) { 4538 /* Make link LED blink during scan. */ 4539 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 4540 } 4541 urtwn_set_chan(sc, c, NULL); 4542 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 4543 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 4544 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 4545 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 4546 URTWN_UNLOCK(sc); 4547} 4548 4549static int 4550urtwn_wme_update(struct ieee80211com *ic) 4551{ 4552 const struct wmeParams *wmep = 4553 ic->ic_wme.wme_chanParams.cap_wmeParams; 4554 struct urtwn_softc *sc = ic->ic_softc; 4555 uint8_t aifs, acm, slottime; 4556 int ac; 4557 4558 acm = 0; 4559 slottime = IEEE80211_GET_SLOTTIME(ic); 4560 4561 URTWN_LOCK(sc); 4562 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4563 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4564 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4565 urtwn_write_4(sc, wme2queue[ac].reg, 4566 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 4567 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 4568 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 4569 SM(R92C_EDCA_PARAM_AIFS, aifs)); 4570 if (ac != WME_AC_BE) 4571 acm |= wmep[ac].wmep_acm << ac; 4572 } 4573 4574 if (acm != 0) 4575 acm |= R92C_ACMHWCTRL_EN; 4576 urtwn_write_1(sc, R92C_ACMHWCTRL, 4577 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 4578 acm); 4579 4580 URTWN_UNLOCK(sc); 4581 4582 return 0; 4583} 4584 4585static void 4586urtwn_update_slot(struct ieee80211com *ic) 4587{ 4588 urtwn_cmd_sleepable(ic->ic_softc, NULL, 0, urtwn_update_slot_cb); 4589} 4590 4591static void 4592urtwn_update_slot_cb(struct urtwn_softc *sc, union sec_param *data) 4593{ 4594 struct ieee80211com *ic = &sc->sc_ic; 4595 uint8_t slottime; 4596 4597 slottime = IEEE80211_GET_SLOTTIME(ic); 4598 4599 URTWN_DPRINTF(sc, URTWN_DEBUG_ANY, "%s: setting slot time to %uus\n", 4600 __func__, slottime); 4601 4602 urtwn_write_1(sc, R92C_SLOT, slottime); 4603 urtwn_update_aifs(sc, slottime); 4604} 4605 4606static void 4607urtwn_update_aifs(struct urtwn_softc *sc, uint8_t slottime) 4608{ 4609 const struct wmeParams *wmep = 4610 sc->sc_ic.ic_wme.wme_chanParams.cap_wmeParams; 4611 uint8_t aifs, ac; 4612 4613 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4614 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4615 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4616 urtwn_write_1(sc, wme2queue[ac].reg, aifs); 4617 } 4618} 4619 4620static void 4621urtwn_set_promisc(struct urtwn_softc *sc) 4622{ 4623 struct ieee80211com *ic = &sc->sc_ic; 4624 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4625 uint32_t rcr, mask1, mask2; 4626 4627 URTWN_ASSERT_LOCKED(sc); 4628 4629 if (vap->iv_opmode == IEEE80211_M_MONITOR) 4630 return; 4631 4632 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 4633 mask2 = R92C_RCR_APM; 4634 4635 if (vap->iv_state == IEEE80211_S_RUN) { 4636 switch (vap->iv_opmode) { 4637 case IEEE80211_M_STA: 4638 mask2 |= R92C_RCR_CBSSID_DATA; 4639 /* FALLTHROUGH */ 4640 case IEEE80211_M_HOSTAP: 4641 mask2 |= R92C_RCR_CBSSID_BCN; 4642 break; 4643 case IEEE80211_M_IBSS: 4644 mask2 |= R92C_RCR_CBSSID_DATA; 4645 break; 4646 default: 4647 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4648 __func__, vap->iv_opmode); 4649 return; 4650 } 4651 } 4652 4653 rcr = urtwn_read_4(sc, R92C_RCR); 4654 if (ic->ic_promisc == 0) 4655 rcr = (rcr & ~mask1) | mask2; 4656 else 4657 rcr = (rcr & ~mask2) | mask1; 4658 urtwn_write_4(sc, R92C_RCR, rcr); 4659} 4660 4661static void 4662urtwn_update_promisc(struct ieee80211com *ic) 4663{ 4664 struct urtwn_softc *sc = ic->ic_softc; 4665 4666 URTWN_LOCK(sc); 4667 if (sc->sc_flags & URTWN_RUNNING) 4668 urtwn_set_promisc(sc); 4669 URTWN_UNLOCK(sc); 4670} 4671 4672static void 4673urtwn_update_mcast(struct ieee80211com *ic) 4674{ 4675 /* XXX do nothing? */ 4676} 4677 4678static struct ieee80211_node * 4679urtwn_r88e_node_alloc(struct ieee80211vap *vap, 4680 const uint8_t mac[IEEE80211_ADDR_LEN]) 4681{ 4682 struct urtwn_node *un; 4683 4684 un = malloc(sizeof (struct urtwn_node), M_80211_NODE, 4685 M_NOWAIT | M_ZERO); 4686 4687 if (un == NULL) 4688 return NULL; 4689 4690 un->id = URTWN_MACID_UNDEFINED; 4691 4692 return &un->ni; 4693} 4694 4695static void 4696urtwn_r88e_newassoc(struct ieee80211_node *ni, int isnew) 4697{ 4698 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4699 struct urtwn_node *un = URTWN_NODE(ni); 4700 uint8_t id; 4701 4702 if (!isnew) 4703 return; 4704 4705 URTWN_NT_LOCK(sc); 4706 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 4707 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 4708 un->id = id; 4709 sc->node_list[id] = ni; 4710 break; 4711 } 4712 } 4713 URTWN_NT_UNLOCK(sc); 4714 4715 if (id > URTWN_MACID_MAX(sc)) { 4716 device_printf(sc->sc_dev, "%s: node table is full\n", 4717 __func__); 4718 } 4719} 4720 4721static void 4722urtwn_r88e_node_free(struct ieee80211_node *ni) 4723{ 4724 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4725 struct urtwn_node *un = URTWN_NODE(ni); 4726 4727 URTWN_NT_LOCK(sc); 4728 if (un->id != URTWN_MACID_UNDEFINED) 4729 sc->node_list[un->id] = NULL; 4730 URTWN_NT_UNLOCK(sc); 4731 4732 sc->sc_node_free(ni); 4733} 4734 4735static void 4736urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 4737 struct ieee80211_channel *extc) 4738{ 4739 struct ieee80211com *ic = &sc->sc_ic; 4740 uint32_t reg; 4741 u_int chan; 4742 int i; 4743 4744 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4745 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 4746 device_printf(sc->sc_dev, 4747 "%s: invalid channel %x\n", __func__, chan); 4748 return; 4749 } 4750 4751 /* Set Tx power for this new channel. */ 4752 urtwn_set_txpower(sc, c, extc); 4753 4754 for (i = 0; i < sc->nrxchains; i++) { 4755 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4756 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4757 } 4758#ifndef IEEE80211_NO_HT 4759 if (extc != NULL) { 4760 /* Is secondary channel below or above primary? */ 4761 int prichlo = c->ic_freq < extc->ic_freq; 4762 4763 urtwn_write_1(sc, R92C_BWOPMODE, 4764 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4765 4766 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4767 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4768 urtwn_write_1(sc, R92C_RRSR + 2, reg); 4769 4770 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4771 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4772 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4773 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4774 4775 /* Set CCK side band. */ 4776 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4777 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4778 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4779 4780 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4781 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4782 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4783 4784 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4785 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4786 ~R92C_FPGA0_ANAPARAM2_CBW20); 4787 4788 reg = urtwn_bb_read(sc, 0x818); 4789 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4790 urtwn_bb_write(sc, 0x818, reg); 4791 4792 /* Select 40MHz bandwidth. */ 4793 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4794 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4795 } else 4796#endif 4797 { 4798 urtwn_write_1(sc, R92C_BWOPMODE, 4799 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4800 4801 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4802 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4803 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4804 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4805 4806 if (!(sc->chip & URTWN_CHIP_88E)) { 4807 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4808 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4809 R92C_FPGA0_ANAPARAM2_CBW20); 4810 } 4811 4812 /* Select 20MHz bandwidth. */ 4813 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4814 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4815 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 4816 R92C_RF_CHNLBW_BW20)); 4817 } 4818} 4819 4820static void 4821urtwn_iq_calib(struct urtwn_softc *sc) 4822{ 4823 /* TODO */ 4824} 4825 4826static void 4827urtwn_lc_calib(struct urtwn_softc *sc) 4828{ 4829 uint32_t rf_ac[2]; 4830 uint8_t txmode; 4831 int i; 4832 4833 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4834 if ((txmode & 0x70) != 0) { 4835 /* Disable all continuous Tx. */ 4836 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4837 4838 /* Set RF mode to standby mode. */ 4839 for (i = 0; i < sc->nrxchains; i++) { 4840 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4841 urtwn_rf_write(sc, i, R92C_RF_AC, 4842 RW(rf_ac[i], R92C_RF_AC_MODE, 4843 R92C_RF_AC_MODE_STANDBY)); 4844 } 4845 } else { 4846 /* Block all Tx queues. */ 4847 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 4848 } 4849 /* Start calibration. */ 4850 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4851 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4852 4853 /* Give calibration the time to complete. */ 4854 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 4855 4856 /* Restore configuration. */ 4857 if ((txmode & 0x70) != 0) { 4858 /* Restore Tx mode. */ 4859 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4860 /* Restore RF mode. */ 4861 for (i = 0; i < sc->nrxchains; i++) 4862 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4863 } else { 4864 /* Unblock all Tx queues. */ 4865 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4866 } 4867} 4868 4869static void 4870urtwn_temp_calib(struct urtwn_softc *sc) 4871{ 4872 uint8_t temp; 4873 4874 URTWN_ASSERT_LOCKED(sc); 4875 4876 if (!(sc->sc_flags & URTWN_TEMP_MEASURED)) { 4877 /* Start measuring temperature. */ 4878 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 4879 "%s: start measuring temperature\n", __func__); 4880 if (sc->chip & URTWN_CHIP_88E) { 4881 urtwn_rf_write(sc, 0, R88E_RF_T_METER, 4882 R88E_RF_T_METER_START); 4883 } else { 4884 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 4885 R92C_RF_T_METER_START); 4886 } 4887 sc->sc_flags |= URTWN_TEMP_MEASURED; 4888 return; 4889 } 4890 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 4891 4892 /* Read measured temperature. */ 4893 if (sc->chip & URTWN_CHIP_88E) { 4894 temp = MS(urtwn_rf_read(sc, 0, R88E_RF_T_METER), 4895 R88E_RF_T_METER_VAL); 4896 } else { 4897 temp = MS(urtwn_rf_read(sc, 0, R92C_RF_T_METER), 4898 R92C_RF_T_METER_VAL); 4899 } 4900 if (temp == 0) { /* Read failed, skip. */ 4901 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 4902 "%s: temperature read failed, skipping\n", __func__); 4903 return; 4904 } 4905 4906 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 4907 "%s: temperature: previous %u, current %u\n", 4908 __func__, sc->thcal_lctemp, temp); 4909 4910 /* 4911 * Redo LC calibration if temperature changed significantly since 4912 * last calibration. 4913 */ 4914 if (sc->thcal_lctemp == 0) { 4915 /* First LC calibration is performed in urtwn_init(). */ 4916 sc->thcal_lctemp = temp; 4917 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4918 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 4919 "%s: LC calib triggered by temp: %u -> %u\n", 4920 __func__, sc->thcal_lctemp, temp); 4921 urtwn_lc_calib(sc); 4922 /* Record temperature of last LC calibration. */ 4923 sc->thcal_lctemp = temp; 4924 } 4925} 4926 4927static int 4928urtwn_init(struct urtwn_softc *sc) 4929{ 4930 struct ieee80211com *ic = &sc->sc_ic; 4931 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4932 uint8_t macaddr[IEEE80211_ADDR_LEN]; 4933 uint32_t reg; 4934 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 4935 int error; 4936 4937 URTWN_LOCK(sc); 4938 if (sc->sc_flags & URTWN_RUNNING) { 4939 URTWN_UNLOCK(sc); 4940 return (0); 4941 } 4942 4943 /* Init firmware commands ring. */ 4944 sc->fwcur = 0; 4945 4946 /* Allocate Tx/Rx buffers. */ 4947 error = urtwn_alloc_rx_list(sc); 4948 if (error != 0) 4949 goto fail; 4950 4951 error = urtwn_alloc_tx_list(sc); 4952 if (error != 0) 4953 goto fail; 4954 4955 /* Power on adapter. */ 4956 error = urtwn_power_on(sc); 4957 if (error != 0) 4958 goto fail; 4959 4960 /* Initialize DMA. */ 4961 error = urtwn_dma_init(sc); 4962 if (error != 0) 4963 goto fail; 4964 4965 /* Set info size in Rx descriptors (in 64-bit words). */ 4966 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4967 4968 /* Init interrupts. */ 4969 if (sc->chip & URTWN_CHIP_88E) { 4970 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4971 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4972 goto fail; 4973 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4974 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4975 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4976 goto fail; 4977 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4978 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4979 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4980 goto fail; 4981 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4982 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4983 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4984 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4985 goto fail; 4986 } else { 4987 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4988 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4989 goto fail; 4990 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4991 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4992 goto fail; 4993 } 4994 4995 /* Set MAC address. */ 4996 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 4997 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 4998 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4999 goto fail; 5000 5001 /* Set initial network type. */ 5002 urtwn_set_mode(sc, R92C_MSR_INFRA); 5003 5004 /* Initialize Rx filter. */ 5005 urtwn_rxfilter_init(sc); 5006 5007 /* Set response rate. */ 5008 reg = urtwn_read_4(sc, R92C_RRSR); 5009 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5010 urtwn_write_4(sc, R92C_RRSR, reg); 5011 5012 /* Set short/long retry limits. */ 5013 urtwn_write_2(sc, R92C_RL, 5014 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5015 5016 /* Initialize EDCA parameters. */ 5017 urtwn_edca_init(sc); 5018 5019 /* Setup rate fallback. */ 5020 if (!(sc->chip & URTWN_CHIP_88E)) { 5021 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5022 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5023 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5024 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5025 } 5026 5027 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5028 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5029 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5030 /* Set ACK timeout. */ 5031 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5032 5033 /* Setup USB aggregation. */ 5034 reg = urtwn_read_4(sc, R92C_TDECTRL); 5035 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5036 urtwn_write_4(sc, R92C_TDECTRL, reg); 5037 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5038 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5039 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5040 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5041 if (sc->chip & URTWN_CHIP_88E) 5042 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5043 else { 5044 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5045 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5046 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5047 R92C_USB_SPECIAL_OPTION_AGG_EN); 5048 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 5049 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 5050 } 5051 5052 /* Initialize beacon parameters. */ 5053 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5054 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5055 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 5056 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 5057 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5058 5059 if (!(sc->chip & URTWN_CHIP_88E)) { 5060 /* Setup AMPDU aggregation. */ 5061 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5062 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5063 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 5064 5065 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5066 } 5067 5068#ifndef URTWN_WITHOUT_UCODE 5069 /* Load 8051 microcode. */ 5070 error = urtwn_load_firmware(sc); 5071 if (error == 0) 5072 sc->sc_flags |= URTWN_FW_LOADED; 5073#endif 5074 5075 /* Initialize MAC/BB/RF blocks. */ 5076 error = urtwn_mac_init(sc); 5077 if (error != 0) { 5078 device_printf(sc->sc_dev, 5079 "%s: error while initializing MAC block\n", __func__); 5080 goto fail; 5081 } 5082 urtwn_bb_init(sc); 5083 urtwn_rf_init(sc); 5084 5085 /* Reinitialize Rx filter (D3845 is not committed yet). */ 5086 urtwn_rxfilter_init(sc); 5087 5088 if (sc->chip & URTWN_CHIP_88E) { 5089 urtwn_write_2(sc, R92C_CR, 5090 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5091 R92C_CR_MACRXEN); 5092 } 5093 5094 /* Turn CCK and OFDM blocks on. */ 5095 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5096 reg |= R92C_RFMOD_CCK_EN; 5097 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5098 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5099 goto fail; 5100 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5101 reg |= R92C_RFMOD_OFDM_EN; 5102 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5103 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5104 goto fail; 5105 5106 /* Clear per-station keys table. */ 5107 urtwn_cam_init(sc); 5108 5109 /* Enable decryption / encryption. */ 5110 urtwn_write_2(sc, R92C_SECCFG, 5111 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 5112 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA | 5113 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 5114 5115 /* 5116 * Install static keys (if any). 5117 * Must be called after urtwn_cam_init(). 5118 */ 5119 ieee80211_runtask(ic, &sc->cmdq_task); 5120 5121 /* Enable hardware sequence numbering. */ 5122 urtwn_write_1(sc, R92C_HWSEQ_CTRL, R92C_TX_QUEUE_ALL); 5123 5124 /* Enable per-packet TX report. */ 5125 if (sc->chip & URTWN_CHIP_88E) { 5126 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 5127 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 5128 } 5129 5130 /* Perform LO and IQ calibrations. */ 5131 urtwn_iq_calib(sc); 5132 /* Perform LC calibration. */ 5133 urtwn_lc_calib(sc); 5134 5135 /* Fix USB interference issue. */ 5136 if (!(sc->chip & URTWN_CHIP_88E)) { 5137 urtwn_write_1(sc, 0xfe40, 0xe0); 5138 urtwn_write_1(sc, 0xfe41, 0x8d); 5139 urtwn_write_1(sc, 0xfe42, 0x80); 5140 5141 urtwn_pa_bias_init(sc); 5142 } 5143 5144 /* Initialize GPIO setting. */ 5145 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5146 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5147 5148 /* Fix for lower temperature. */ 5149 if (!(sc->chip & URTWN_CHIP_88E)) 5150 urtwn_write_1(sc, 0x15, 0xe9); 5151 5152 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 5153 5154 sc->sc_flags |= URTWN_RUNNING; 5155 5156 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5157fail: 5158 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5159 error = EIO; 5160 5161 URTWN_UNLOCK(sc); 5162 5163 return (error); 5164} 5165 5166static void 5167urtwn_stop(struct urtwn_softc *sc) 5168{ 5169 5170 URTWN_LOCK(sc); 5171 if (!(sc->sc_flags & URTWN_RUNNING)) { 5172 URTWN_UNLOCK(sc); 5173 return; 5174 } 5175 5176 sc->sc_flags &= ~(URTWN_RUNNING | URTWN_FW_LOADED | 5177 URTWN_TEMP_MEASURED); 5178 sc->thcal_lctemp = 0; 5179 callout_stop(&sc->sc_watchdog_ch); 5180 5181 urtwn_abort_xfers(sc); 5182 urtwn_drain_mbufq(sc); 5183 urtwn_power_off(sc); 5184 URTWN_UNLOCK(sc); 5185} 5186 5187static void 5188urtwn_abort_xfers(struct urtwn_softc *sc) 5189{ 5190 int i; 5191 5192 URTWN_ASSERT_LOCKED(sc); 5193 5194 /* abort any pending transfers */ 5195 for (i = 0; i < URTWN_N_TRANSFER; i++) 5196 usbd_transfer_stop(sc->sc_xfer[i]); 5197} 5198 5199static int 5200urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5201 const struct ieee80211_bpf_params *params) 5202{ 5203 struct ieee80211com *ic = ni->ni_ic; 5204 struct urtwn_softc *sc = ic->ic_softc; 5205 struct urtwn_data *bf; 5206 int error; 5207 5208 /* prevent management frames from being sent if we're not ready */ 5209 URTWN_LOCK(sc); 5210 if (!(sc->sc_flags & URTWN_RUNNING)) { 5211 error = ENETDOWN; 5212 goto end; 5213 } 5214 5215 bf = urtwn_getbuf(sc); 5216 if (bf == NULL) { 5217 error = ENOBUFS; 5218 goto end; 5219 } 5220 5221 if (params == NULL) { 5222 /* 5223 * Legacy path; interpret frame contents to decide 5224 * precisely how to send the frame. 5225 */ 5226 error = urtwn_tx_data(sc, ni, m, bf); 5227 } else { 5228 /* 5229 * Caller supplied explicit parameters to use in 5230 * sending the frame. 5231 */ 5232 error = urtwn_tx_raw(sc, ni, m, bf, params); 5233 } 5234 if (error != 0) { 5235 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 5236 goto end; 5237 } 5238 5239 sc->sc_txtimer = 5; 5240 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5241 5242end: 5243 if (error != 0) 5244 m_freem(m); 5245 5246 URTWN_UNLOCK(sc); 5247 5248 return (error); 5249} 5250 5251static void 5252urtwn_ms_delay(struct urtwn_softc *sc) 5253{ 5254 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 5255} 5256 5257static device_method_t urtwn_methods[] = { 5258 /* Device interface */ 5259 DEVMETHOD(device_probe, urtwn_match), 5260 DEVMETHOD(device_attach, urtwn_attach), 5261 DEVMETHOD(device_detach, urtwn_detach), 5262 5263 DEVMETHOD_END 5264}; 5265 5266static driver_t urtwn_driver = { 5267 "urtwn", 5268 urtwn_methods, 5269 sizeof(struct urtwn_softc) 5270}; 5271 5272static devclass_t urtwn_devclass; 5273 5274DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 5275MODULE_DEPEND(urtwn, usb, 1, 1, 1); 5276MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 5277#ifndef URTWN_WITHOUT_UCODE 5278MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 5279#endif 5280MODULE_VERSION(urtwn, 1); 5281USB_PNP_HOST_INFO(urtwn_devs); 5282