if_urtwn.c revision 295874
1114414Snyan/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2114414Snyan 3114414Snyan/*- 4114414Snyan * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5114414Snyan * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6114414Snyan * Copyright (c) 2015 Andriy Voskoboinyk <avos@FreeBSD.org> 7114414Snyan * 8114414Snyan * Permission to use, copy, modify, and distribute this software for any 9114414Snyan * purpose with or without fee is hereby granted, provided that the above 10114414Snyan * copyright notice and this permission notice appear in all copies. 11114414Snyan * 12114414Snyan * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13114414Snyan * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14114414Snyan * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15114414Snyan * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16114414Snyan * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17114414Snyan * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18114414Snyan * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19114414Snyan */ 20114414Snyan 21114414Snyan#include <sys/cdefs.h> 22114414Snyan__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 295874 2016-02-22 01:15:02Z avos $"); 23114414Snyan 24114414Snyan/* 25114414Snyan * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 26114414Snyan */ 27116196Sobrien 28116196Sobrien#include "opt_wlan.h" 29116196Sobrien#include "opt_urtwn.h" 30114414Snyan 31114414Snyan#include <sys/param.h> 32114414Snyan#include <sys/sockio.h> 33114414Snyan#include <sys/sysctl.h> 34114414Snyan#include <sys/lock.h> 35114414Snyan#include <sys/mutex.h> 36114414Snyan#include <sys/condvar.h> 37114414Snyan#include <sys/mbuf.h> 38145761Snyan#include <sys/kernel.h> 39114414Snyan#include <sys/socket.h> 40114414Snyan#include <sys/systm.h> 41114414Snyan#include <sys/malloc.h> 42114414Snyan#include <sys/module.h> 43114414Snyan#include <sys/bus.h> 44114414Snyan#include <sys/endian.h> 45114414Snyan#include <sys/linker.h> 46114414Snyan#include <sys/firmware.h> 47114414Snyan#include <sys/kdb.h> 48114414Snyan 49114414Snyan#include <machine/bus.h> 50114414Snyan#include <machine/resource.h> 51114414Snyan#include <sys/rman.h> 52114414Snyan 53114414Snyan#include <net/bpf.h> 54114414Snyan#include <net/if.h> 55114414Snyan#include <net/if_var.h> 56114414Snyan#include <net/if_arp.h> 57114414Snyan#include <net/ethernet.h> 58114414Snyan#include <net/if_dl.h> 59114414Snyan#include <net/if_media.h> 60114414Snyan#include <net/if_types.h> 61145761Snyan 62114414Snyan#include <netinet/in.h> 63114414Snyan#include <netinet/in_systm.h> 64114414Snyan#include <netinet/in_var.h> 65114414Snyan#include <netinet/if_ether.h> 66114414Snyan#include <netinet/ip.h> 67114414Snyan 68114414Snyan#include <net80211/ieee80211_var.h> 69114414Snyan#include <net80211/ieee80211_input.h> 70114414Snyan#include <net80211/ieee80211_regdomain.h> 71114414Snyan#include <net80211/ieee80211_radiotap.h> 72114414Snyan#include <net80211/ieee80211_ratectl.h> 73114414Snyan 74114414Snyan#include <dev/usb/usb.h> 75114414Snyan#include <dev/usb/usbdi.h> 76114414Snyan#include <dev/usb/usb_device.h> 77114414Snyan#include "usbdevs.h" 78114414Snyan 79#include <dev/usb/usb_debug.h> 80 81#include <dev/usb/wlan/if_urtwnreg.h> 82#include <dev/usb/wlan/if_urtwnvar.h> 83 84#ifdef USB_DEBUG 85enum { 86 URTWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 87 URTWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 88 URTWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 89 URTWN_DEBUG_RA = 0x00000008, /* f/w rate adaptation setup */ 90 URTWN_DEBUG_USB = 0x00000010, /* usb requests */ 91 URTWN_DEBUG_FIRMWARE = 0x00000020, /* firmware(9) loading debug */ 92 URTWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 93 URTWN_DEBUG_INTR = 0x00000080, /* ISR */ 94 URTWN_DEBUG_TEMP = 0x00000100, /* temperature calibration */ 95 URTWN_DEBUG_ROM = 0x00000200, /* various ROM info */ 96 URTWN_DEBUG_KEY = 0x00000400, /* crypto keys management */ 97 URTWN_DEBUG_TXPWR = 0x00000800, /* dump Tx power values */ 98 URTWN_DEBUG_ANY = 0xffffffff 99}; 100 101#define URTWN_DPRINTF(_sc, _m, ...) do { \ 102 if ((_sc)->sc_debug & (_m)) \ 103 device_printf((_sc)->sc_dev, __VA_ARGS__); \ 104} while(0) 105 106#else 107#define URTWN_DPRINTF(_sc, _m, ...) do { (void) sc; } while (0) 108#endif 109 110#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 111 112/* various supported device vendors/products */ 113static const STRUCT_USB_HOST_ID urtwn_devs[] = { 114#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 115#define URTWN_RTL8188E_DEV(v,p) \ 116 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 117#define URTWN_RTL8188E 1 118 URTWN_DEV(ABOCOM, RTL8188CU_1), 119 URTWN_DEV(ABOCOM, RTL8188CU_2), 120 URTWN_DEV(ABOCOM, RTL8192CU), 121 URTWN_DEV(ASUS, RTL8192CU), 122 URTWN_DEV(ASUS, USBN10NANO), 123 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 124 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 125 URTWN_DEV(AZUREWAVE, RTL8188CU), 126 URTWN_DEV(BELKIN, F7D2102), 127 URTWN_DEV(BELKIN, RTL8188CU), 128 URTWN_DEV(BELKIN, RTL8192CU), 129 URTWN_DEV(CHICONY, RTL8188CUS_1), 130 URTWN_DEV(CHICONY, RTL8188CUS_2), 131 URTWN_DEV(CHICONY, RTL8188CUS_3), 132 URTWN_DEV(CHICONY, RTL8188CUS_4), 133 URTWN_DEV(CHICONY, RTL8188CUS_5), 134 URTWN_DEV(COREGA, RTL8192CU), 135 URTWN_DEV(DLINK, RTL8188CU), 136 URTWN_DEV(DLINK, RTL8192CU_1), 137 URTWN_DEV(DLINK, RTL8192CU_2), 138 URTWN_DEV(DLINK, RTL8192CU_3), 139 URTWN_DEV(DLINK, DWA131B), 140 URTWN_DEV(EDIMAX, EW7811UN), 141 URTWN_DEV(EDIMAX, RTL8192CU), 142 URTWN_DEV(FEIXUN, RTL8188CU), 143 URTWN_DEV(FEIXUN, RTL8192CU), 144 URTWN_DEV(GUILLEMOT, HWNUP150), 145 URTWN_DEV(HAWKING, RTL8192CU), 146 URTWN_DEV(HP3, RTL8188CU), 147 URTWN_DEV(NETGEAR, WNA1000M), 148 URTWN_DEV(NETGEAR, RTL8192CU), 149 URTWN_DEV(NETGEAR4, RTL8188CU), 150 URTWN_DEV(NOVATECH, RTL8188CU), 151 URTWN_DEV(PLANEX2, RTL8188CU_1), 152 URTWN_DEV(PLANEX2, RTL8188CU_2), 153 URTWN_DEV(PLANEX2, RTL8188CU_3), 154 URTWN_DEV(PLANEX2, RTL8188CU_4), 155 URTWN_DEV(PLANEX2, RTL8188CUS), 156 URTWN_DEV(PLANEX2, RTL8192CU), 157 URTWN_DEV(REALTEK, RTL8188CE_0), 158 URTWN_DEV(REALTEK, RTL8188CE_1), 159 URTWN_DEV(REALTEK, RTL8188CTV), 160 URTWN_DEV(REALTEK, RTL8188CU_0), 161 URTWN_DEV(REALTEK, RTL8188CU_1), 162 URTWN_DEV(REALTEK, RTL8188CU_2), 163 URTWN_DEV(REALTEK, RTL8188CU_3), 164 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 165 URTWN_DEV(REALTEK, RTL8188CUS), 166 URTWN_DEV(REALTEK, RTL8188RU_1), 167 URTWN_DEV(REALTEK, RTL8188RU_2), 168 URTWN_DEV(REALTEK, RTL8188RU_3), 169 URTWN_DEV(REALTEK, RTL8191CU), 170 URTWN_DEV(REALTEK, RTL8192CE), 171 URTWN_DEV(REALTEK, RTL8192CU), 172 URTWN_DEV(SITECOMEU, RTL8188CU_1), 173 URTWN_DEV(SITECOMEU, RTL8188CU_2), 174 URTWN_DEV(SITECOMEU, RTL8192CU), 175 URTWN_DEV(TRENDNET, RTL8188CU), 176 URTWN_DEV(TRENDNET, RTL8192CU), 177 URTWN_DEV(ZYXEL, RTL8192CU), 178 /* URTWN_RTL8188E */ 179 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 180 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 181 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 182 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 183 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 184#undef URTWN_RTL8188E_DEV 185#undef URTWN_DEV 186}; 187 188static device_probe_t urtwn_match; 189static device_attach_t urtwn_attach; 190static device_detach_t urtwn_detach; 191 192static usb_callback_t urtwn_bulk_tx_callback; 193static usb_callback_t urtwn_bulk_rx_callback; 194 195static void urtwn_sysctlattach(struct urtwn_softc *); 196static void urtwn_drain_mbufq(struct urtwn_softc *); 197static usb_error_t urtwn_do_request(struct urtwn_softc *, 198 struct usb_device_request *, void *); 199static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 200 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 201 const uint8_t [IEEE80211_ADDR_LEN], 202 const uint8_t [IEEE80211_ADDR_LEN]); 203static void urtwn_vap_delete(struct ieee80211vap *); 204static struct mbuf * urtwn_rx_copy_to_mbuf(struct urtwn_softc *, 205 struct r92c_rx_stat *, int); 206static struct mbuf * urtwn_report_intr(struct usb_xfer *, 207 struct urtwn_data *); 208static struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int); 209static void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 210 void *); 211static struct ieee80211_node *urtwn_rx_frame(struct urtwn_softc *, 212 struct mbuf *, int8_t *); 213static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 214 int); 215static int urtwn_alloc_list(struct urtwn_softc *, 216 struct urtwn_data[], int, int); 217static int urtwn_alloc_rx_list(struct urtwn_softc *); 218static int urtwn_alloc_tx_list(struct urtwn_softc *); 219static void urtwn_free_list(struct urtwn_softc *, 220 struct urtwn_data data[], int); 221static void urtwn_free_rx_list(struct urtwn_softc *); 222static void urtwn_free_tx_list(struct urtwn_softc *); 223static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 224static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 225static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 226 uint8_t *, int); 227static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 228static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 229static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 230static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 231 uint8_t *, int); 232static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 233static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 234static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 235static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 236 const void *, int); 237static void urtwn_cmdq_cb(void *, int); 238static int urtwn_cmd_sleepable(struct urtwn_softc *, const void *, 239 size_t, CMD_FUNC_PROTO); 240static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 241 uint8_t, uint32_t); 242static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 243 uint8_t, uint32_t); 244static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 245static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 246 uint32_t); 247static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 248static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 249 uint8_t, uint8_t); 250#ifdef USB_DEBUG 251static void urtwn_dump_rom_contents(struct urtwn_softc *, 252 uint8_t *, uint16_t); 253#endif 254static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 255 uint16_t); 256static int urtwn_efuse_switch_power(struct urtwn_softc *); 257static int urtwn_read_chipid(struct urtwn_softc *); 258static int urtwn_read_rom(struct urtwn_softc *); 259static int urtwn_r88e_read_rom(struct urtwn_softc *); 260static int urtwn_ra_init(struct urtwn_softc *); 261static void urtwn_init_beacon(struct urtwn_softc *, 262 struct urtwn_vap *); 263static int urtwn_setup_beacon(struct urtwn_softc *, 264 struct ieee80211_node *); 265static void urtwn_update_beacon(struct ieee80211vap *, int); 266static int urtwn_tx_beacon(struct urtwn_softc *sc, 267 struct urtwn_vap *); 268static int urtwn_key_alloc(struct ieee80211vap *, 269 struct ieee80211_key *, ieee80211_keyix *, 270 ieee80211_keyix *); 271static void urtwn_key_set_cb(struct urtwn_softc *, 272 union sec_param *); 273static void urtwn_key_del_cb(struct urtwn_softc *, 274 union sec_param *); 275static int urtwn_key_set(struct ieee80211vap *, 276 const struct ieee80211_key *); 277static int urtwn_key_delete(struct ieee80211vap *, 278 const struct ieee80211_key *); 279static void urtwn_tsf_task_adhoc(void *, int); 280static void urtwn_tsf_sync_enable(struct urtwn_softc *, 281 struct ieee80211vap *); 282static void urtwn_get_tsf(struct urtwn_softc *, uint64_t *); 283static void urtwn_set_led(struct urtwn_softc *, int, int); 284static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 285static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 286 struct mbuf *, int, 287 const struct ieee80211_rx_stats *, int, int); 288static int urtwn_newstate(struct ieee80211vap *, 289 enum ieee80211_state, int); 290static void urtwn_calib_to(void *); 291static void urtwn_calib_cb(struct urtwn_softc *, 292 union sec_param *); 293static void urtwn_watchdog(void *); 294static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 295static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 296static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 297static int urtwn_tx_data(struct urtwn_softc *, 298 struct ieee80211_node *, struct mbuf *, 299 struct urtwn_data *); 300static int urtwn_tx_raw(struct urtwn_softc *, 301 struct ieee80211_node *, struct mbuf *, 302 struct urtwn_data *, 303 const struct ieee80211_bpf_params *); 304static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 305 uint8_t, struct urtwn_data *); 306static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 307static void urtwn_start(struct urtwn_softc *); 308static void urtwn_parent(struct ieee80211com *); 309static int urtwn_r92c_power_on(struct urtwn_softc *); 310static int urtwn_r88e_power_on(struct urtwn_softc *); 311static void urtwn_r92c_power_off(struct urtwn_softc *); 312static void urtwn_r88e_power_off(struct urtwn_softc *); 313static int urtwn_llt_init(struct urtwn_softc *); 314#ifndef URTWN_WITHOUT_UCODE 315static void urtwn_fw_reset(struct urtwn_softc *); 316static void urtwn_r88e_fw_reset(struct urtwn_softc *); 317static int urtwn_fw_loadpage(struct urtwn_softc *, int, 318 const uint8_t *, int); 319static int urtwn_load_firmware(struct urtwn_softc *); 320#endif 321static int urtwn_dma_init(struct urtwn_softc *); 322static int urtwn_mac_init(struct urtwn_softc *); 323static void urtwn_bb_init(struct urtwn_softc *); 324static void urtwn_rf_init(struct urtwn_softc *); 325static void urtwn_cam_init(struct urtwn_softc *); 326static int urtwn_cam_write(struct urtwn_softc *, uint32_t, 327 uint32_t); 328static void urtwn_pa_bias_init(struct urtwn_softc *); 329static void urtwn_rxfilter_init(struct urtwn_softc *); 330static void urtwn_edca_init(struct urtwn_softc *); 331static void urtwn_write_txpower(struct urtwn_softc *, int, 332 uint16_t[]); 333static void urtwn_get_txpower(struct urtwn_softc *, int, 334 struct ieee80211_channel *, 335 struct ieee80211_channel *, uint16_t[]); 336static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 337 struct ieee80211_channel *, 338 struct ieee80211_channel *, uint16_t[]); 339static void urtwn_set_txpower(struct urtwn_softc *, 340 struct ieee80211_channel *, 341 struct ieee80211_channel *); 342static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 343static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 344static void urtwn_scan_start(struct ieee80211com *); 345static void urtwn_scan_end(struct ieee80211com *); 346static void urtwn_set_channel(struct ieee80211com *); 347static int urtwn_wme_update(struct ieee80211com *); 348static void urtwn_update_slot(struct ieee80211com *); 349static void urtwn_update_slot_cb(struct urtwn_softc *, 350 union sec_param *); 351static void urtwn_update_aifs(struct urtwn_softc *, uint8_t); 352static void urtwn_set_promisc(struct urtwn_softc *); 353static void urtwn_update_promisc(struct ieee80211com *); 354static void urtwn_update_mcast(struct ieee80211com *); 355static struct ieee80211_node *urtwn_r88e_node_alloc(struct ieee80211vap *, 356 const uint8_t mac[IEEE80211_ADDR_LEN]); 357static void urtwn_r88e_newassoc(struct ieee80211_node *, int); 358static void urtwn_r88e_node_free(struct ieee80211_node *); 359static void urtwn_set_chan(struct urtwn_softc *, 360 struct ieee80211_channel *, 361 struct ieee80211_channel *); 362static void urtwn_iq_calib(struct urtwn_softc *); 363static void urtwn_lc_calib(struct urtwn_softc *); 364static void urtwn_temp_calib(struct urtwn_softc *); 365static int urtwn_init(struct urtwn_softc *); 366static void urtwn_stop(struct urtwn_softc *); 367static void urtwn_abort_xfers(struct urtwn_softc *); 368static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 369 const struct ieee80211_bpf_params *); 370static void urtwn_ms_delay(struct urtwn_softc *); 371 372/* Aliases. */ 373#define urtwn_bb_write urtwn_write_4 374#define urtwn_bb_read urtwn_read_4 375 376static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 377 [URTWN_BULK_RX] = { 378 .type = UE_BULK, 379 .endpoint = UE_ADDR_ANY, 380 .direction = UE_DIR_IN, 381 .bufsize = URTWN_RXBUFSZ, 382 .flags = { 383 .pipe_bof = 1, 384 .short_xfer_ok = 1 385 }, 386 .callback = urtwn_bulk_rx_callback, 387 }, 388 [URTWN_BULK_TX_BE] = { 389 .type = UE_BULK, 390 .endpoint = 0x03, 391 .direction = UE_DIR_OUT, 392 .bufsize = URTWN_TXBUFSZ, 393 .flags = { 394 .ext_buffer = 1, 395 .pipe_bof = 1, 396 .force_short_xfer = 1 397 }, 398 .callback = urtwn_bulk_tx_callback, 399 .timeout = URTWN_TX_TIMEOUT, /* ms */ 400 }, 401 [URTWN_BULK_TX_BK] = { 402 .type = UE_BULK, 403 .endpoint = 0x03, 404 .direction = UE_DIR_OUT, 405 .bufsize = URTWN_TXBUFSZ, 406 .flags = { 407 .ext_buffer = 1, 408 .pipe_bof = 1, 409 .force_short_xfer = 1, 410 }, 411 .callback = urtwn_bulk_tx_callback, 412 .timeout = URTWN_TX_TIMEOUT, /* ms */ 413 }, 414 [URTWN_BULK_TX_VI] = { 415 .type = UE_BULK, 416 .endpoint = 0x02, 417 .direction = UE_DIR_OUT, 418 .bufsize = URTWN_TXBUFSZ, 419 .flags = { 420 .ext_buffer = 1, 421 .pipe_bof = 1, 422 .force_short_xfer = 1 423 }, 424 .callback = urtwn_bulk_tx_callback, 425 .timeout = URTWN_TX_TIMEOUT, /* ms */ 426 }, 427 [URTWN_BULK_TX_VO] = { 428 .type = UE_BULK, 429 .endpoint = 0x02, 430 .direction = UE_DIR_OUT, 431 .bufsize = URTWN_TXBUFSZ, 432 .flags = { 433 .ext_buffer = 1, 434 .pipe_bof = 1, 435 .force_short_xfer = 1 436 }, 437 .callback = urtwn_bulk_tx_callback, 438 .timeout = URTWN_TX_TIMEOUT, /* ms */ 439 }, 440}; 441 442static const struct wme_to_queue { 443 uint16_t reg; 444 uint8_t qid; 445} wme2queue[WME_NUM_AC] = { 446 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 447 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 448 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 449 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 450}; 451 452static int 453urtwn_match(device_t self) 454{ 455 struct usb_attach_arg *uaa = device_get_ivars(self); 456 457 if (uaa->usb_mode != USB_MODE_HOST) 458 return (ENXIO); 459 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 460 return (ENXIO); 461 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 462 return (ENXIO); 463 464 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 465} 466 467static int 468urtwn_attach(device_t self) 469{ 470 struct usb_attach_arg *uaa = device_get_ivars(self); 471 struct urtwn_softc *sc = device_get_softc(self); 472 struct ieee80211com *ic = &sc->sc_ic; 473 uint8_t bands[howmany(IEEE80211_MODE_MAX, 8)]; 474 int error; 475 476 device_set_usb_desc(self); 477 sc->sc_udev = uaa->device; 478 sc->sc_dev = self; 479 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 480 sc->chip |= URTWN_CHIP_88E; 481 482#ifdef USB_DEBUG 483 int debug; 484 if (resource_int_value(device_get_name(sc->sc_dev), 485 device_get_unit(sc->sc_dev), "debug", &debug) == 0) 486 sc->sc_debug = debug; 487#endif 488 489 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 490 MTX_NETWORK_LOCK, MTX_DEF); 491 URTWN_CMDQ_LOCK_INIT(sc); 492 URTWN_NT_LOCK_INIT(sc); 493 callout_init(&sc->sc_calib_to, 0); 494 callout_init(&sc->sc_watchdog_ch, 0); 495 mbufq_init(&sc->sc_snd, ifqmaxlen); 496 497 sc->sc_iface_index = URTWN_IFACE_INDEX; 498 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 499 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 500 if (error) { 501 device_printf(self, "could not allocate USB transfers, " 502 "err=%s\n", usbd_errstr(error)); 503 goto detach; 504 } 505 506 URTWN_LOCK(sc); 507 508 error = urtwn_read_chipid(sc); 509 if (error) { 510 device_printf(sc->sc_dev, "unsupported test chip\n"); 511 URTWN_UNLOCK(sc); 512 goto detach; 513 } 514 515 /* Determine number of Tx/Rx chains. */ 516 if (sc->chip & URTWN_CHIP_92C) { 517 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 518 sc->nrxchains = 2; 519 } else { 520 sc->ntxchains = 1; 521 sc->nrxchains = 1; 522 } 523 524 if (sc->chip & URTWN_CHIP_88E) 525 error = urtwn_r88e_read_rom(sc); 526 else 527 error = urtwn_read_rom(sc); 528 if (error != 0) { 529 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 530 __func__, error); 531 URTWN_UNLOCK(sc); 532 goto detach; 533 } 534 535 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 536 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 537 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 538 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 539 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 540 "8188CUS", sc->ntxchains, sc->nrxchains); 541 542 URTWN_UNLOCK(sc); 543 544 ic->ic_softc = sc; 545 ic->ic_name = device_get_nameunit(self); 546 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 547 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 548 549 /* set device capabilities */ 550 ic->ic_caps = 551 IEEE80211_C_STA /* station mode */ 552 | IEEE80211_C_MONITOR /* monitor mode */ 553 | IEEE80211_C_IBSS /* adhoc mode */ 554 | IEEE80211_C_HOSTAP /* hostap mode */ 555 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 556 | IEEE80211_C_SHSLOT /* short slot time supported */ 557 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 558 | IEEE80211_C_WPA /* 802.11i */ 559 | IEEE80211_C_WME /* 802.11e */ 560 ; 561 562 ic->ic_cryptocaps = 563 IEEE80211_CRYPTO_WEP | 564 IEEE80211_CRYPTO_TKIP | 565 IEEE80211_CRYPTO_AES_CCM; 566 567 memset(bands, 0, sizeof(bands)); 568 setbit(bands, IEEE80211_MODE_11B); 569 setbit(bands, IEEE80211_MODE_11G); 570 ieee80211_init_channels(ic, NULL, bands); 571 572 ieee80211_ifattach(ic); 573 ic->ic_raw_xmit = urtwn_raw_xmit; 574 ic->ic_scan_start = urtwn_scan_start; 575 ic->ic_scan_end = urtwn_scan_end; 576 ic->ic_set_channel = urtwn_set_channel; 577 ic->ic_transmit = urtwn_transmit; 578 ic->ic_parent = urtwn_parent; 579 ic->ic_vap_create = urtwn_vap_create; 580 ic->ic_vap_delete = urtwn_vap_delete; 581 ic->ic_wme.wme_update = urtwn_wme_update; 582 ic->ic_updateslot = urtwn_update_slot; 583 ic->ic_update_promisc = urtwn_update_promisc; 584 ic->ic_update_mcast = urtwn_update_mcast; 585 if (sc->chip & URTWN_CHIP_88E) { 586 ic->ic_node_alloc = urtwn_r88e_node_alloc; 587 ic->ic_newassoc = urtwn_r88e_newassoc; 588 sc->sc_node_free = ic->ic_node_free; 589 ic->ic_node_free = urtwn_r88e_node_free; 590 } 591 592 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 593 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 594 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 595 URTWN_RX_RADIOTAP_PRESENT); 596 597 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc); 598 599 urtwn_sysctlattach(sc); 600 601 if (bootverbose) 602 ieee80211_announce(ic); 603 604 return (0); 605 606detach: 607 urtwn_detach(self); 608 return (ENXIO); /* failure */ 609} 610 611static void 612urtwn_sysctlattach(struct urtwn_softc *sc) 613{ 614#ifdef USB_DEBUG 615 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 616 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 617 618 SYSCTL_ADD_U32(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 619 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 620 "control debugging printfs"); 621#endif 622} 623 624static int 625urtwn_detach(device_t self) 626{ 627 struct urtwn_softc *sc = device_get_softc(self); 628 struct ieee80211com *ic = &sc->sc_ic; 629 unsigned int x; 630 631 /* Prevent further ioctls. */ 632 URTWN_LOCK(sc); 633 sc->sc_flags |= URTWN_DETACHED; 634 URTWN_UNLOCK(sc); 635 636 urtwn_stop(sc); 637 638 callout_drain(&sc->sc_watchdog_ch); 639 callout_drain(&sc->sc_calib_to); 640 641 /* stop all USB transfers */ 642 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 643 644 /* Prevent further allocations from RX/TX data lists. */ 645 URTWN_LOCK(sc); 646 STAILQ_INIT(&sc->sc_tx_active); 647 STAILQ_INIT(&sc->sc_tx_inactive); 648 STAILQ_INIT(&sc->sc_tx_pending); 649 650 STAILQ_INIT(&sc->sc_rx_active); 651 STAILQ_INIT(&sc->sc_rx_inactive); 652 URTWN_UNLOCK(sc); 653 654 /* drain USB transfers */ 655 for (x = 0; x != URTWN_N_TRANSFER; x++) 656 usbd_transfer_drain(sc->sc_xfer[x]); 657 658 /* Free data buffers. */ 659 URTWN_LOCK(sc); 660 urtwn_free_tx_list(sc); 661 urtwn_free_rx_list(sc); 662 URTWN_UNLOCK(sc); 663 664 if (ic->ic_softc == sc) { 665 ieee80211_draintask(ic, &sc->cmdq_task); 666 ieee80211_ifdetach(ic); 667 } 668 669 URTWN_NT_LOCK_DESTROY(sc); 670 URTWN_CMDQ_LOCK_DESTROY(sc); 671 mtx_destroy(&sc->sc_mtx); 672 673 return (0); 674} 675 676static void 677urtwn_drain_mbufq(struct urtwn_softc *sc) 678{ 679 struct mbuf *m; 680 struct ieee80211_node *ni; 681 URTWN_ASSERT_LOCKED(sc); 682 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 683 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 684 m->m_pkthdr.rcvif = NULL; 685 ieee80211_free_node(ni); 686 m_freem(m); 687 } 688} 689 690static usb_error_t 691urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 692 void *data) 693{ 694 usb_error_t err; 695 int ntries = 10; 696 697 URTWN_ASSERT_LOCKED(sc); 698 699 while (ntries--) { 700 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 701 req, data, 0, NULL, 250 /* ms */); 702 if (err == 0) 703 break; 704 705 URTWN_DPRINTF(sc, URTWN_DEBUG_USB, 706 "%s: control request failed, %s (retries left: %d)\n", 707 __func__, usbd_errstr(err), ntries); 708 usb_pause_mtx(&sc->sc_mtx, hz / 100); 709 } 710 return (err); 711} 712 713static struct ieee80211vap * 714urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 715 enum ieee80211_opmode opmode, int flags, 716 const uint8_t bssid[IEEE80211_ADDR_LEN], 717 const uint8_t mac[IEEE80211_ADDR_LEN]) 718{ 719 struct urtwn_softc *sc = ic->ic_softc; 720 struct urtwn_vap *uvp; 721 struct ieee80211vap *vap; 722 723 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 724 return (NULL); 725 726 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 727 vap = &uvp->vap; 728 /* enable s/w bmiss handling for sta mode */ 729 730 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 731 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 732 /* out of memory */ 733 free(uvp, M_80211_VAP); 734 return (NULL); 735 } 736 737 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 738 urtwn_init_beacon(sc, uvp); 739 740 /* override state transition machine */ 741 uvp->newstate = vap->iv_newstate; 742 vap->iv_newstate = urtwn_newstate; 743 vap->iv_update_beacon = urtwn_update_beacon; 744 vap->iv_key_alloc = urtwn_key_alloc; 745 vap->iv_key_set = urtwn_key_set; 746 vap->iv_key_delete = urtwn_key_delete; 747 if (opmode == IEEE80211_M_IBSS) { 748 uvp->recv_mgmt = vap->iv_recv_mgmt; 749 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 750 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 751 } 752 753 if (URTWN_CHIP_HAS_RATECTL(sc)) 754 ieee80211_ratectl_init(vap); 755 /* complete setup */ 756 ieee80211_vap_attach(vap, ieee80211_media_change, 757 ieee80211_media_status, mac); 758 ic->ic_opmode = opmode; 759 return (vap); 760} 761 762static void 763urtwn_vap_delete(struct ieee80211vap *vap) 764{ 765 struct ieee80211com *ic = vap->iv_ic; 766 struct urtwn_softc *sc = ic->ic_softc; 767 struct urtwn_vap *uvp = URTWN_VAP(vap); 768 769 if (uvp->bcn_mbuf != NULL) 770 m_freem(uvp->bcn_mbuf); 771 if (vap->iv_opmode == IEEE80211_M_IBSS) 772 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 773 if (URTWN_CHIP_HAS_RATECTL(sc)) 774 ieee80211_ratectl_deinit(vap); 775 ieee80211_vap_detach(vap); 776 free(uvp, M_80211_VAP); 777} 778 779static struct mbuf * 780urtwn_rx_copy_to_mbuf(struct urtwn_softc *sc, struct r92c_rx_stat *stat, 781 int totlen) 782{ 783 struct ieee80211com *ic = &sc->sc_ic; 784 struct mbuf *m; 785 uint32_t rxdw0; 786 int pktlen; 787 788 /* 789 * don't pass packets to the ieee80211 framework if the driver isn't 790 * RUNNING. 791 */ 792 if (!(sc->sc_flags & URTWN_RUNNING)) 793 return (NULL); 794 795 rxdw0 = le32toh(stat->rxdw0); 796 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 797 /* 798 * This should not happen since we setup our Rx filter 799 * to not receive these frames. 800 */ 801 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 802 "%s: RX flags error (%s)\n", __func__, 803 rxdw0 & R92C_RXDW0_CRCERR ? "CRC" : "ICV"); 804 goto fail; 805 } 806 807 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 808 if (pktlen < sizeof(struct ieee80211_frame_ack)) { 809 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 810 "%s: frame is too short: %d\n", __func__, pktlen); 811 goto fail; 812 } 813 814 if (__predict_false(totlen > MCLBYTES)) { 815 /* convert to m_getjcl if this happens */ 816 device_printf(sc->sc_dev, "%s: frame too long: %d (%d)\n", 817 __func__, pktlen, totlen); 818 goto fail; 819 } 820 821 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 822 if (__predict_false(m == NULL)) { 823 device_printf(sc->sc_dev, "%s: could not allocate RX mbuf\n", 824 __func__); 825 goto fail; 826 } 827 828 /* Finalize mbuf. */ 829 memcpy(mtod(m, uint8_t *), (uint8_t *)stat, totlen); 830 m->m_pkthdr.len = m->m_len = totlen; 831 832 return (m); 833fail: 834 counter_u64_add(ic->ic_ierrors, 1); 835 return (NULL); 836} 837 838static struct mbuf * 839urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data) 840{ 841 struct urtwn_softc *sc = data->sc; 842 struct ieee80211com *ic = &sc->sc_ic; 843 struct r92c_rx_stat *stat; 844 uint8_t *buf; 845 int len; 846 847 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 848 849 if (len < sizeof(*stat)) { 850 counter_u64_add(ic->ic_ierrors, 1); 851 return (NULL); 852 } 853 854 buf = data->buf; 855 stat = (struct r92c_rx_stat *)buf; 856 857 if (sc->chip & URTWN_CHIP_88E) { 858 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 859 860 switch (report_sel) { 861 case R88E_RXDW3_RPT_RX: 862 return (urtwn_rxeof(sc, buf, len)); 863 case R88E_RXDW3_RPT_TX1: 864 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 865 break; 866 default: 867 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, 868 "%s: case %d was not handled\n", __func__, 869 report_sel); 870 break; 871 } 872 } else 873 return (urtwn_rxeof(sc, buf, len)); 874 875 return (NULL); 876} 877 878static struct mbuf * 879urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len) 880{ 881 struct r92c_rx_stat *stat; 882 struct mbuf *m, *m0 = NULL, *prevm = NULL; 883 uint32_t rxdw0; 884 int totlen, pktlen, infosz, npkts; 885 886 /* Get the number of encapsulated frames. */ 887 stat = (struct r92c_rx_stat *)buf; 888 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 889 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 890 "%s: Rx %d frames in one chunk\n", __func__, npkts); 891 892 /* Process all of them. */ 893 while (npkts-- > 0) { 894 if (len < sizeof(*stat)) 895 break; 896 stat = (struct r92c_rx_stat *)buf; 897 rxdw0 = le32toh(stat->rxdw0); 898 899 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 900 if (pktlen == 0) 901 break; 902 903 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 904 905 /* Make sure everything fits in xfer. */ 906 totlen = sizeof(*stat) + infosz + pktlen; 907 if (totlen > len) 908 break; 909 910 m = urtwn_rx_copy_to_mbuf(sc, stat, totlen); 911 if (m0 == NULL) 912 m0 = m; 913 if (prevm == NULL) 914 prevm = m; 915 else { 916 prevm->m_next = m; 917 prevm = m; 918 } 919 920 /* Next chunk is 128-byte aligned. */ 921 totlen = (totlen + 127) & ~127; 922 buf += totlen; 923 len -= totlen; 924 } 925 926 return (m0); 927} 928 929static void 930urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 931{ 932 struct r88e_tx_rpt_ccx *rpt = arg; 933 struct ieee80211vap *vap; 934 struct ieee80211_node *ni; 935 uint8_t macid; 936 int ntries; 937 938 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 939 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 940 941 URTWN_NT_LOCK(sc); 942 ni = sc->node_list[macid]; 943 if (ni != NULL) { 944 vap = ni->ni_vap; 945 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: frame for macid %d was" 946 "%s sent (%d retries)\n", __func__, macid, 947 (rpt->rptb1 & R88E_RPTB1_PKT_OK) ? "" : " not", 948 ntries); 949 950 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 951 ieee80211_ratectl_tx_complete(vap, ni, 952 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 953 } else { 954 ieee80211_ratectl_tx_complete(vap, ni, 955 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 956 } 957 } else { 958 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: macid %d, ni is NULL\n", 959 __func__, macid); 960 } 961 URTWN_NT_UNLOCK(sc); 962} 963 964static struct ieee80211_node * 965urtwn_rx_frame(struct urtwn_softc *sc, struct mbuf *m, int8_t *rssi_p) 966{ 967 struct ieee80211com *ic = &sc->sc_ic; 968 struct ieee80211_frame_min *wh; 969 struct r92c_rx_stat *stat; 970 uint32_t rxdw0, rxdw3; 971 uint8_t rate, cipher; 972 int8_t rssi = URTWN_NOISE_FLOOR + 1; 973 int infosz; 974 975 stat = mtod(m, struct r92c_rx_stat *); 976 rxdw0 = le32toh(stat->rxdw0); 977 rxdw3 = le32toh(stat->rxdw3); 978 979 rate = MS(rxdw3, R92C_RXDW3_RATE); 980 cipher = MS(rxdw0, R92C_RXDW0_CIPHER); 981 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 982 983 /* Get RSSI from PHY status descriptor if present. */ 984 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 985 if (sc->chip & URTWN_CHIP_88E) 986 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 987 else 988 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 989 /* Update our average RSSI. */ 990 urtwn_update_avgrssi(sc, rate, rssi); 991 } 992 993 if (ieee80211_radiotap_active(ic)) { 994 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 995 996 tap->wr_flags = 0; 997 998 urtwn_get_tsf(sc, &tap->wr_tsft); 999 if (__predict_false(le32toh((uint32_t)tap->wr_tsft) < 1000 le32toh(stat->rxdw5))) { 1001 tap->wr_tsft = le32toh(tap->wr_tsft >> 32) - 1; 1002 tap->wr_tsft = (uint64_t)htole32(tap->wr_tsft) << 32; 1003 } else 1004 tap->wr_tsft &= 0xffffffff00000000; 1005 tap->wr_tsft += stat->rxdw5; 1006 1007 /* Map HW rate index to 802.11 rate. */ 1008 if (!(rxdw3 & R92C_RXDW3_HT)) { 1009 tap->wr_rate = ridx2rate[rate]; 1010 } else if (rate >= 12) { /* MCS0~15. */ 1011 /* Bit 7 set means HT MCS instead of rate. */ 1012 tap->wr_rate = 0x80 | (rate - 12); 1013 } 1014 tap->wr_dbm_antsignal = rssi; 1015 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 1016 } 1017 1018 *rssi_p = rssi; 1019 1020 /* Drop descriptor. */ 1021 m_adj(m, sizeof(*stat) + infosz); 1022 wh = mtod(m, struct ieee80211_frame_min *); 1023 1024 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1025 cipher != R92C_CAM_ALGO_NONE) { 1026 m->m_flags |= M_WEP; 1027 } 1028 1029 if (m->m_len >= sizeof(*wh)) 1030 return (ieee80211_find_rxnode(ic, wh)); 1031 1032 return (NULL); 1033} 1034 1035static void 1036urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 1037{ 1038 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1039 struct ieee80211com *ic = &sc->sc_ic; 1040 struct ieee80211_node *ni; 1041 struct mbuf *m = NULL, *next; 1042 struct urtwn_data *data; 1043 int8_t nf, rssi; 1044 1045 URTWN_ASSERT_LOCKED(sc); 1046 1047 switch (USB_GET_STATE(xfer)) { 1048 case USB_ST_TRANSFERRED: 1049 data = STAILQ_FIRST(&sc->sc_rx_active); 1050 if (data == NULL) 1051 goto tr_setup; 1052 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1053 m = urtwn_report_intr(xfer, data); 1054 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1055 /* FALLTHROUGH */ 1056 case USB_ST_SETUP: 1057tr_setup: 1058 data = STAILQ_FIRST(&sc->sc_rx_inactive); 1059 if (data == NULL) { 1060 KASSERT(m == NULL, ("mbuf isn't NULL")); 1061 return; 1062 } 1063 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 1064 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 1065 usbd_xfer_set_frame_data(xfer, 0, data->buf, 1066 usbd_xfer_max_len(xfer)); 1067 usbd_transfer_submit(xfer); 1068 1069 /* 1070 * To avoid LOR we should unlock our private mutex here to call 1071 * ieee80211_input() because here is at the end of a USB 1072 * callback and safe to unlock. 1073 */ 1074 while (m != NULL) { 1075 next = m->m_next; 1076 m->m_next = NULL; 1077 1078 ni = urtwn_rx_frame(sc, m, &rssi); 1079 URTWN_UNLOCK(sc); 1080 1081 nf = URTWN_NOISE_FLOOR; 1082 if (ni != NULL) { 1083 (void)ieee80211_input(ni, m, rssi - nf, nf); 1084 ieee80211_free_node(ni); 1085 } else { 1086 (void)ieee80211_input_all(ic, m, rssi - nf, 1087 nf); 1088 } 1089 1090 URTWN_LOCK(sc); 1091 m = next; 1092 } 1093 break; 1094 default: 1095 /* needs it to the inactive queue due to a error. */ 1096 data = STAILQ_FIRST(&sc->sc_rx_active); 1097 if (data != NULL) { 1098 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1099 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1100 } 1101 if (error != USB_ERR_CANCELLED) { 1102 usbd_xfer_set_stall(xfer); 1103 counter_u64_add(ic->ic_ierrors, 1); 1104 goto tr_setup; 1105 } 1106 break; 1107 } 1108} 1109 1110static void 1111urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 1112{ 1113 1114 URTWN_ASSERT_LOCKED(sc); 1115 1116 if (data->ni != NULL) /* not a beacon frame */ 1117 ieee80211_tx_complete(data->ni, data->m, status); 1118 1119 data->ni = NULL; 1120 data->m = NULL; 1121 1122 sc->sc_txtimer = 0; 1123 1124 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 1125} 1126 1127static int 1128urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1129 int ndata, int maxsz) 1130{ 1131 int i, error; 1132 1133 for (i = 0; i < ndata; i++) { 1134 struct urtwn_data *dp = &data[i]; 1135 dp->sc = sc; 1136 dp->m = NULL; 1137 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1138 if (dp->buf == NULL) { 1139 device_printf(sc->sc_dev, 1140 "could not allocate buffer\n"); 1141 error = ENOMEM; 1142 goto fail; 1143 } 1144 dp->ni = NULL; 1145 } 1146 1147 return (0); 1148fail: 1149 urtwn_free_list(sc, data, ndata); 1150 return (error); 1151} 1152 1153static int 1154urtwn_alloc_rx_list(struct urtwn_softc *sc) 1155{ 1156 int error, i; 1157 1158 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1159 URTWN_RXBUFSZ); 1160 if (error != 0) 1161 return (error); 1162 1163 STAILQ_INIT(&sc->sc_rx_active); 1164 STAILQ_INIT(&sc->sc_rx_inactive); 1165 1166 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1167 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1168 1169 return (0); 1170} 1171 1172static int 1173urtwn_alloc_tx_list(struct urtwn_softc *sc) 1174{ 1175 int error, i; 1176 1177 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1178 URTWN_TXBUFSZ); 1179 if (error != 0) 1180 return (error); 1181 1182 STAILQ_INIT(&sc->sc_tx_active); 1183 STAILQ_INIT(&sc->sc_tx_inactive); 1184 STAILQ_INIT(&sc->sc_tx_pending); 1185 1186 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1187 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1188 1189 return (0); 1190} 1191 1192static void 1193urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1194{ 1195 int i; 1196 1197 for (i = 0; i < ndata; i++) { 1198 struct urtwn_data *dp = &data[i]; 1199 1200 if (dp->buf != NULL) { 1201 free(dp->buf, M_USBDEV); 1202 dp->buf = NULL; 1203 } 1204 if (dp->ni != NULL) { 1205 ieee80211_free_node(dp->ni); 1206 dp->ni = NULL; 1207 } 1208 } 1209} 1210 1211static void 1212urtwn_free_rx_list(struct urtwn_softc *sc) 1213{ 1214 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1215} 1216 1217static void 1218urtwn_free_tx_list(struct urtwn_softc *sc) 1219{ 1220 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1221} 1222 1223static void 1224urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1225{ 1226 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1227 struct urtwn_data *data; 1228 1229 URTWN_ASSERT_LOCKED(sc); 1230 1231 switch (USB_GET_STATE(xfer)){ 1232 case USB_ST_TRANSFERRED: 1233 data = STAILQ_FIRST(&sc->sc_tx_active); 1234 if (data == NULL) 1235 goto tr_setup; 1236 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1237 urtwn_txeof(sc, data, 0); 1238 /* FALLTHROUGH */ 1239 case USB_ST_SETUP: 1240tr_setup: 1241 data = STAILQ_FIRST(&sc->sc_tx_pending); 1242 if (data == NULL) { 1243 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1244 "%s: empty pending queue\n", __func__); 1245 goto finish; 1246 } 1247 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1248 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1249 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1250 usbd_transfer_submit(xfer); 1251 break; 1252 default: 1253 data = STAILQ_FIRST(&sc->sc_tx_active); 1254 if (data == NULL) 1255 goto tr_setup; 1256 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1257 urtwn_txeof(sc, data, 1); 1258 if (error != USB_ERR_CANCELLED) { 1259 usbd_xfer_set_stall(xfer); 1260 goto tr_setup; 1261 } 1262 break; 1263 } 1264finish: 1265 /* Kick-start more transmit */ 1266 urtwn_start(sc); 1267} 1268 1269static struct urtwn_data * 1270_urtwn_getbuf(struct urtwn_softc *sc) 1271{ 1272 struct urtwn_data *bf; 1273 1274 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1275 if (bf != NULL) 1276 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1277 else { 1278 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1279 "%s: out of xmit buffers\n", __func__); 1280 } 1281 return (bf); 1282} 1283 1284static struct urtwn_data * 1285urtwn_getbuf(struct urtwn_softc *sc) 1286{ 1287 struct urtwn_data *bf; 1288 1289 URTWN_ASSERT_LOCKED(sc); 1290 1291 bf = _urtwn_getbuf(sc); 1292 if (bf == NULL) { 1293 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: stop queue\n", 1294 __func__); 1295 } 1296 return (bf); 1297} 1298 1299static usb_error_t 1300urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1301 int len) 1302{ 1303 usb_device_request_t req; 1304 1305 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1306 req.bRequest = R92C_REQ_REGS; 1307 USETW(req.wValue, addr); 1308 USETW(req.wIndex, 0); 1309 USETW(req.wLength, len); 1310 return (urtwn_do_request(sc, &req, buf)); 1311} 1312 1313static usb_error_t 1314urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1315{ 1316 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1317} 1318 1319static usb_error_t 1320urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1321{ 1322 val = htole16(val); 1323 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1324} 1325 1326static usb_error_t 1327urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1328{ 1329 val = htole32(val); 1330 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1331} 1332 1333static usb_error_t 1334urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1335 int len) 1336{ 1337 usb_device_request_t req; 1338 1339 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1340 req.bRequest = R92C_REQ_REGS; 1341 USETW(req.wValue, addr); 1342 USETW(req.wIndex, 0); 1343 USETW(req.wLength, len); 1344 return (urtwn_do_request(sc, &req, buf)); 1345} 1346 1347static uint8_t 1348urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1349{ 1350 uint8_t val; 1351 1352 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1353 return (0xff); 1354 return (val); 1355} 1356 1357static uint16_t 1358urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1359{ 1360 uint16_t val; 1361 1362 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1363 return (0xffff); 1364 return (le16toh(val)); 1365} 1366 1367static uint32_t 1368urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1369{ 1370 uint32_t val; 1371 1372 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1373 return (0xffffffff); 1374 return (le32toh(val)); 1375} 1376 1377static int 1378urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1379{ 1380 struct r92c_fw_cmd cmd; 1381 usb_error_t error; 1382 int ntries; 1383 1384 if (!(sc->sc_flags & URTWN_FW_LOADED)) { 1385 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, "%s: firmware " 1386 "was not loaded; command (id %d) will be discarded\n", 1387 __func__, id); 1388 return (0); 1389 } 1390 1391 /* Wait for current FW box to be empty. */ 1392 for (ntries = 0; ntries < 100; ntries++) { 1393 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1394 break; 1395 urtwn_ms_delay(sc); 1396 } 1397 if (ntries == 100) { 1398 device_printf(sc->sc_dev, 1399 "could not send firmware command\n"); 1400 return (ETIMEDOUT); 1401 } 1402 memset(&cmd, 0, sizeof(cmd)); 1403 cmd.id = id; 1404 if (len > 3) 1405 cmd.id |= R92C_CMD_FLAG_EXT; 1406 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1407 memcpy(cmd.msg, buf, len); 1408 1409 /* Write the first word last since that will trigger the FW. */ 1410 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1411 (uint8_t *)&cmd + 4, 2); 1412 if (error != USB_ERR_NORMAL_COMPLETION) 1413 return (EIO); 1414 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1415 (uint8_t *)&cmd + 0, 4); 1416 if (error != USB_ERR_NORMAL_COMPLETION) 1417 return (EIO); 1418 1419 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1420 return (0); 1421} 1422 1423static void 1424urtwn_cmdq_cb(void *arg, int pending) 1425{ 1426 struct urtwn_softc *sc = arg; 1427 struct urtwn_cmdq *item; 1428 1429 /* 1430 * Device must be powered on (via urtwn_power_on()) 1431 * before any command may be sent. 1432 */ 1433 URTWN_LOCK(sc); 1434 if (!(sc->sc_flags & URTWN_RUNNING)) { 1435 URTWN_UNLOCK(sc); 1436 return; 1437 } 1438 1439 URTWN_CMDQ_LOCK(sc); 1440 while (sc->cmdq[sc->cmdq_first].func != NULL) { 1441 item = &sc->cmdq[sc->cmdq_first]; 1442 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE; 1443 URTWN_CMDQ_UNLOCK(sc); 1444 1445 item->func(sc, &item->data); 1446 1447 URTWN_CMDQ_LOCK(sc); 1448 memset(item, 0, sizeof (*item)); 1449 } 1450 URTWN_CMDQ_UNLOCK(sc); 1451 URTWN_UNLOCK(sc); 1452} 1453 1454static int 1455urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len, 1456 CMD_FUNC_PROTO) 1457{ 1458 struct ieee80211com *ic = &sc->sc_ic; 1459 1460 KASSERT(len <= sizeof(union sec_param), ("buffer overflow")); 1461 1462 URTWN_CMDQ_LOCK(sc); 1463 if (sc->cmdq[sc->cmdq_last].func != NULL) { 1464 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__); 1465 URTWN_CMDQ_UNLOCK(sc); 1466 1467 return (EAGAIN); 1468 } 1469 1470 if (ptr != NULL) 1471 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len); 1472 sc->cmdq[sc->cmdq_last].func = func; 1473 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE; 1474 URTWN_CMDQ_UNLOCK(sc); 1475 1476 ieee80211_runtask(ic, &sc->cmdq_task); 1477 1478 return (0); 1479} 1480 1481static __inline void 1482urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1483{ 1484 1485 sc->sc_rf_write(sc, chain, addr, val); 1486} 1487 1488static void 1489urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1490 uint32_t val) 1491{ 1492 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1493 SM(R92C_LSSI_PARAM_ADDR, addr) | 1494 SM(R92C_LSSI_PARAM_DATA, val)); 1495} 1496 1497static void 1498urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1499uint32_t val) 1500{ 1501 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1502 SM(R88E_LSSI_PARAM_ADDR, addr) | 1503 SM(R92C_LSSI_PARAM_DATA, val)); 1504} 1505 1506static uint32_t 1507urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1508{ 1509 uint32_t reg[R92C_MAX_CHAINS], val; 1510 1511 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1512 if (chain != 0) 1513 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1514 1515 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1516 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1517 urtwn_ms_delay(sc); 1518 1519 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1520 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1521 R92C_HSSI_PARAM2_READ_EDGE); 1522 urtwn_ms_delay(sc); 1523 1524 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1525 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1526 urtwn_ms_delay(sc); 1527 1528 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1529 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1530 else 1531 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1532 return (MS(val, R92C_LSSI_READBACK_DATA)); 1533} 1534 1535static int 1536urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1537{ 1538 usb_error_t error; 1539 int ntries; 1540 1541 error = urtwn_write_4(sc, R92C_LLT_INIT, 1542 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1543 SM(R92C_LLT_INIT_ADDR, addr) | 1544 SM(R92C_LLT_INIT_DATA, data)); 1545 if (error != USB_ERR_NORMAL_COMPLETION) 1546 return (EIO); 1547 /* Wait for write operation to complete. */ 1548 for (ntries = 0; ntries < 20; ntries++) { 1549 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1550 R92C_LLT_INIT_OP_NO_ACTIVE) 1551 return (0); 1552 urtwn_ms_delay(sc); 1553 } 1554 return (ETIMEDOUT); 1555} 1556 1557static int 1558urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1559{ 1560 uint32_t reg; 1561 usb_error_t error; 1562 int ntries; 1563 1564 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1565 return (EFAULT); 1566 1567 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1568 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1569 reg &= ~R92C_EFUSE_CTRL_VALID; 1570 1571 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1572 if (error != USB_ERR_NORMAL_COMPLETION) 1573 return (EIO); 1574 /* Wait for read operation to complete. */ 1575 for (ntries = 0; ntries < 100; ntries++) { 1576 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1577 if (reg & R92C_EFUSE_CTRL_VALID) 1578 break; 1579 urtwn_ms_delay(sc); 1580 } 1581 if (ntries == 100) { 1582 device_printf(sc->sc_dev, 1583 "could not read efuse byte at address 0x%x\n", 1584 sc->last_rom_addr); 1585 return (ETIMEDOUT); 1586 } 1587 1588 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1589 sc->last_rom_addr++; 1590 1591 return (0); 1592} 1593 1594static int 1595urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1596 uint8_t msk) 1597{ 1598 uint8_t reg; 1599 int i, error; 1600 1601 for (i = 0; i < 4; i++) { 1602 if (msk & (1 << i)) 1603 continue; 1604 error = urtwn_efuse_read_next(sc, ®); 1605 if (error != 0) 1606 return (error); 1607 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1608 off * 8 + i * 2, reg); 1609 rom[off * 8 + i * 2 + 0] = reg; 1610 1611 error = urtwn_efuse_read_next(sc, ®); 1612 if (error != 0) 1613 return (error); 1614 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1615 off * 8 + i * 2 + 1, reg); 1616 rom[off * 8 + i * 2 + 1] = reg; 1617 } 1618 1619 return (0); 1620} 1621 1622#ifdef USB_DEBUG 1623static void 1624urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1625{ 1626 int i; 1627 1628 /* Dump ROM contents. */ 1629 device_printf(sc->sc_dev, "%s:", __func__); 1630 for (i = 0; i < size; i++) { 1631 if (i % 32 == 0) 1632 printf("\n%03X: ", i); 1633 else if (i % 4 == 0) 1634 printf(" "); 1635 1636 printf("%02X", rom[i]); 1637 } 1638 printf("\n"); 1639} 1640#endif 1641 1642static int 1643urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1644{ 1645#define URTWN_CHK(res) do { \ 1646 if ((error = res) != 0) \ 1647 goto end; \ 1648} while(0) 1649 uint8_t msk, off, reg; 1650 int error; 1651 1652 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1653 1654 /* Read full ROM image. */ 1655 sc->last_rom_addr = 0; 1656 memset(rom, 0xff, size); 1657 1658 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1659 while (reg != 0xff) { 1660 /* check for extended header */ 1661 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1662 off = reg >> 5; 1663 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1664 1665 if ((reg & 0x0f) != 0x0f) 1666 off = ((reg & 0xf0) >> 1) | off; 1667 else 1668 continue; 1669 } else 1670 off = reg >> 4; 1671 msk = reg & 0xf; 1672 1673 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1674 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1675 } 1676 1677end: 1678 1679#ifdef USB_DEBUG 1680 if (sc->sc_debug & URTWN_DEBUG_ROM) 1681 urtwn_dump_rom_contents(sc, rom, size); 1682#endif 1683 1684 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1685 1686 if (error != 0) { 1687 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1688 __func__); 1689 } 1690 1691 return (error); 1692#undef URTWN_CHK 1693} 1694 1695static int 1696urtwn_efuse_switch_power(struct urtwn_softc *sc) 1697{ 1698 usb_error_t error; 1699 uint32_t reg; 1700 1701 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1702 if (error != USB_ERR_NORMAL_COMPLETION) 1703 return (EIO); 1704 1705 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1706 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1707 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1708 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1709 if (error != USB_ERR_NORMAL_COMPLETION) 1710 return (EIO); 1711 } 1712 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1713 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1714 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1715 reg | R92C_SYS_FUNC_EN_ELDR); 1716 if (error != USB_ERR_NORMAL_COMPLETION) 1717 return (EIO); 1718 } 1719 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1720 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1721 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1722 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1723 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1724 if (error != USB_ERR_NORMAL_COMPLETION) 1725 return (EIO); 1726 } 1727 1728 return (0); 1729} 1730 1731static int 1732urtwn_read_chipid(struct urtwn_softc *sc) 1733{ 1734 uint32_t reg; 1735 1736 if (sc->chip & URTWN_CHIP_88E) 1737 return (0); 1738 1739 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1740 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1741 return (EIO); 1742 1743 if (reg & R92C_SYS_CFG_TYPE_92C) { 1744 sc->chip |= URTWN_CHIP_92C; 1745 /* Check if it is a castrated 8192C. */ 1746 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1747 R92C_HPON_FSM_CHIP_BONDING_ID) == 1748 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1749 sc->chip |= URTWN_CHIP_92C_1T2R; 1750 } 1751 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1752 sc->chip |= URTWN_CHIP_UMC; 1753 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1754 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1755 } 1756 return (0); 1757} 1758 1759static int 1760urtwn_read_rom(struct urtwn_softc *sc) 1761{ 1762 struct r92c_rom *rom = &sc->rom.r92c_rom; 1763 int error; 1764 1765 /* Read full ROM image. */ 1766 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1767 if (error != 0) 1768 return (error); 1769 1770 /* XXX Weird but this is what the vendor driver does. */ 1771 sc->last_rom_addr = 0x1fa; 1772 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1773 if (error != 0) 1774 return (error); 1775 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: PA setting=0x%x\n", __func__, 1776 sc->pa_setting); 1777 1778 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1779 1780 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1781 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type=%d\n", 1782 __func__, sc->regulatory); 1783 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1784 1785 sc->sc_rf_write = urtwn_r92c_rf_write; 1786 sc->sc_power_on = urtwn_r92c_power_on; 1787 sc->sc_power_off = urtwn_r92c_power_off; 1788 1789 return (0); 1790} 1791 1792static int 1793urtwn_r88e_read_rom(struct urtwn_softc *sc) 1794{ 1795 struct r88e_rom *rom = &sc->rom.r88e_rom; 1796 int error; 1797 1798 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(sc->rom.r88e_rom)); 1799 if (error != 0) 1800 return (error); 1801 1802 sc->bw20_tx_pwr_diff = (rom->tx_pwr_diff >> 4); 1803 if (sc->bw20_tx_pwr_diff & 0x08) 1804 sc->bw20_tx_pwr_diff |= 0xf0; 1805 sc->ofdm_tx_pwr_diff = (rom->tx_pwr_diff & 0xf); 1806 if (sc->ofdm_tx_pwr_diff & 0x08) 1807 sc->ofdm_tx_pwr_diff |= 0xf0; 1808 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 1809 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type %d\n", 1810 __func__,sc->regulatory); 1811 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1812 1813 sc->sc_rf_write = urtwn_r88e_rf_write; 1814 sc->sc_power_on = urtwn_r88e_power_on; 1815 sc->sc_power_off = urtwn_r88e_power_off; 1816 1817 return (0); 1818} 1819 1820/* 1821 * Initialize rate adaptation in firmware. 1822 */ 1823static int 1824urtwn_ra_init(struct urtwn_softc *sc) 1825{ 1826 struct ieee80211com *ic = &sc->sc_ic; 1827 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1828 struct ieee80211_node *ni; 1829 struct ieee80211_rateset *rs; 1830 struct r92c_fw_cmd_macid_cfg cmd; 1831 uint32_t rates, basicrates; 1832 uint8_t mode; 1833 int maxrate, maxbasicrate, error, i, j; 1834 1835 ni = ieee80211_ref_node(vap->iv_bss); 1836 rs = &ni->ni_rates; 1837 1838 /* Get normal and basic rates mask. */ 1839 rates = basicrates = 0; 1840 maxrate = maxbasicrate = 0; 1841 for (i = 0; i < rs->rs_nrates; i++) { 1842 /* Convert 802.11 rate to HW rate index. */ 1843 for (j = 0; j < nitems(ridx2rate); j++) 1844 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1845 ridx2rate[j]) 1846 break; 1847 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1848 continue; 1849 rates |= 1 << j; 1850 if (j > maxrate) 1851 maxrate = j; 1852 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1853 basicrates |= 1 << j; 1854 if (j > maxbasicrate) 1855 maxbasicrate = j; 1856 } 1857 } 1858 if (ic->ic_curmode == IEEE80211_MODE_11B) 1859 mode = R92C_RAID_11B; 1860 else 1861 mode = R92C_RAID_11BG; 1862 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, 1863 "%s: mode 0x%x, rates 0x%08x, basicrates 0x%08x\n", __func__, 1864 mode, rates, basicrates); 1865 1866 /* Set rates mask for group addressed frames. */ 1867 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1868 cmd.mask = htole32(mode << 28 | basicrates); 1869 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1870 if (error != 0) { 1871 ieee80211_free_node(ni); 1872 device_printf(sc->sc_dev, 1873 "could not add broadcast station\n"); 1874 return (error); 1875 } 1876 /* Set initial MRR rate. */ 1877 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxbasicrate %d\n", __func__, 1878 maxbasicrate); 1879 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1880 maxbasicrate); 1881 1882 /* Set rates mask for unicast frames. */ 1883 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1884 cmd.mask = htole32(mode << 28 | rates); 1885 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1886 if (error != 0) { 1887 ieee80211_free_node(ni); 1888 device_printf(sc->sc_dev, "could not add BSS station\n"); 1889 return (error); 1890 } 1891 /* Set initial MRR rate. */ 1892 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxrate %d\n", __func__, 1893 maxrate); 1894 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1895 maxrate); 1896 1897 /* Indicate highest supported rate. */ 1898 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1899 ieee80211_free_node(ni); 1900 1901 return (0); 1902} 1903 1904static void 1905urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1906{ 1907 struct r92c_tx_desc *txd = &uvp->bcn_desc; 1908 1909 txd->txdw0 = htole32( 1910 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 1911 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1912 txd->txdw1 = htole32( 1913 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 1914 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1915 1916 if (sc->chip & URTWN_CHIP_88E) { 1917 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 1918 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 1919 } else { 1920 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 1921 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 1922 } 1923 1924 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 1925 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 1926} 1927 1928static int 1929urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 1930{ 1931 struct ieee80211vap *vap = ni->ni_vap; 1932 struct urtwn_vap *uvp = URTWN_VAP(vap); 1933 struct mbuf *m; 1934 int error; 1935 1936 URTWN_ASSERT_LOCKED(sc); 1937 1938 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 1939 return (EINVAL); 1940 1941 m = ieee80211_beacon_alloc(ni); 1942 if (m == NULL) { 1943 device_printf(sc->sc_dev, 1944 "%s: could not allocate beacon frame\n", __func__); 1945 return (ENOMEM); 1946 } 1947 1948 if (uvp->bcn_mbuf != NULL) 1949 m_freem(uvp->bcn_mbuf); 1950 1951 uvp->bcn_mbuf = m; 1952 1953 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1954 return (error); 1955 1956 /* XXX bcnq stuck workaround */ 1957 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1958 return (error); 1959 1960 URTWN_DPRINTF(sc, URTWN_DEBUG_BEACON, "%s: beacon was %srecognized\n", 1961 __func__, urtwn_read_1(sc, R92C_TDECTRL + 2) & 1962 (R92C_TDECTRL_BCN_VALID >> 16) ? "" : "not "); 1963 1964 return (0); 1965} 1966 1967static void 1968urtwn_update_beacon(struct ieee80211vap *vap, int item) 1969{ 1970 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1971 struct urtwn_vap *uvp = URTWN_VAP(vap); 1972 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 1973 struct ieee80211_node *ni = vap->iv_bss; 1974 int mcast = 0; 1975 1976 URTWN_LOCK(sc); 1977 if (uvp->bcn_mbuf == NULL) { 1978 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 1979 if (uvp->bcn_mbuf == NULL) { 1980 device_printf(sc->sc_dev, 1981 "%s: could not allocate beacon frame\n", __func__); 1982 URTWN_UNLOCK(sc); 1983 return; 1984 } 1985 } 1986 URTWN_UNLOCK(sc); 1987 1988 if (item == IEEE80211_BEACON_TIM) 1989 mcast = 1; /* XXX */ 1990 1991 setbit(bo->bo_flags, item); 1992 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 1993 1994 URTWN_LOCK(sc); 1995 urtwn_tx_beacon(sc, uvp); 1996 URTWN_UNLOCK(sc); 1997} 1998 1999/* 2000 * Push a beacon frame into the chip. Beacon will 2001 * be repeated by the chip every R92C_BCN_INTERVAL. 2002 */ 2003static int 2004urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2005{ 2006 struct r92c_tx_desc *desc = &uvp->bcn_desc; 2007 struct urtwn_data *bf; 2008 2009 URTWN_ASSERT_LOCKED(sc); 2010 2011 bf = urtwn_getbuf(sc); 2012 if (bf == NULL) 2013 return (ENOMEM); 2014 2015 memcpy(bf->buf, desc, sizeof(*desc)); 2016 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 2017 2018 sc->sc_txtimer = 5; 2019 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2020 2021 return (0); 2022} 2023 2024static int 2025urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2026 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2027{ 2028 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2029 uint8_t i; 2030 2031 if (!(&vap->iv_nw_keys[0] <= k && 2032 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2033 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2034 URTWN_LOCK(sc); 2035 /* 2036 * First 4 slots for group keys, 2037 * what is left - for pairwise. 2038 * XXX incompatible with IBSS RSN. 2039 */ 2040 for (i = IEEE80211_WEP_NKID; 2041 i < R92C_CAM_ENTRY_COUNT; i++) { 2042 if ((sc->keys_bmap & (1 << i)) == 0) { 2043 sc->keys_bmap |= 1 << i; 2044 *keyix = i; 2045 break; 2046 } 2047 } 2048 URTWN_UNLOCK(sc); 2049 if (i == R92C_CAM_ENTRY_COUNT) { 2050 device_printf(sc->sc_dev, 2051 "%s: no free space in the key table\n", 2052 __func__); 2053 return 0; 2054 } 2055 } else 2056 *keyix = 0; 2057 } else { 2058 *keyix = k - vap->iv_nw_keys; 2059 } 2060 *rxkeyix = *keyix; 2061 return 1; 2062} 2063 2064static void 2065urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data) 2066{ 2067 struct ieee80211_key *k = &data->key; 2068 uint8_t algo, keyid; 2069 int i, error; 2070 2071 if (k->wk_keyix < IEEE80211_WEP_NKID) 2072 keyid = k->wk_keyix; 2073 else 2074 keyid = 0; 2075 2076 /* Map net80211 cipher to HW crypto algorithm. */ 2077 switch (k->wk_cipher->ic_cipher) { 2078 case IEEE80211_CIPHER_WEP: 2079 if (k->wk_keylen < 8) 2080 algo = R92C_CAM_ALGO_WEP40; 2081 else 2082 algo = R92C_CAM_ALGO_WEP104; 2083 break; 2084 case IEEE80211_CIPHER_TKIP: 2085 algo = R92C_CAM_ALGO_TKIP; 2086 break; 2087 case IEEE80211_CIPHER_AES_CCM: 2088 algo = R92C_CAM_ALGO_AES; 2089 break; 2090 default: 2091 device_printf(sc->sc_dev, "%s: undefined cipher %d\n", 2092 __func__, k->wk_cipher->ic_cipher); 2093 return; 2094 } 2095 2096 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2097 "%s: keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, " 2098 "macaddr %s\n", __func__, k->wk_keyix, keyid, 2099 k->wk_cipher->ic_cipher, algo, k->wk_flags, k->wk_keylen, 2100 ether_sprintf(k->wk_macaddr)); 2101 2102 /* Write key. */ 2103 for (i = 0; i < 4; i++) { 2104 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 2105 LE_READ_4(&k->wk_key[i * 4])); 2106 if (error != 0) 2107 goto fail; 2108 } 2109 2110 /* Write CTL0 last since that will validate the CAM entry. */ 2111 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 2112 LE_READ_4(&k->wk_macaddr[2])); 2113 if (error != 0) 2114 goto fail; 2115 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 2116 SM(R92C_CAM_ALGO, algo) | 2117 SM(R92C_CAM_KEYID, keyid) | 2118 SM(R92C_CAM_MACLO, LE_READ_2(&k->wk_macaddr[0])) | 2119 R92C_CAM_VALID); 2120 if (error != 0) 2121 goto fail; 2122 2123 return; 2124 2125fail: 2126 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error); 2127} 2128 2129static void 2130urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data) 2131{ 2132 struct ieee80211_key *k = &data->key; 2133 int i; 2134 2135 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2136 "%s: keyix %d, flags %04X, macaddr %s\n", __func__, 2137 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr)); 2138 2139 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0); 2140 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0); 2141 2142 /* Clear key. */ 2143 for (i = 0; i < 4; i++) 2144 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0); 2145 sc->keys_bmap &= ~(1 << k->wk_keyix); 2146} 2147 2148static int 2149urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 2150{ 2151 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2152 2153 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2154 /* Not for us. */ 2155 return (1); 2156 } 2157 2158 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb)); 2159} 2160 2161static int 2162urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2163{ 2164 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2165 2166 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2167 /* Not for us. */ 2168 return (1); 2169 } 2170 2171 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb)); 2172} 2173 2174static void 2175urtwn_tsf_task_adhoc(void *arg, int pending) 2176{ 2177 struct ieee80211vap *vap = arg; 2178 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2179 struct ieee80211_node *ni; 2180 uint32_t reg; 2181 2182 URTWN_LOCK(sc); 2183 ni = ieee80211_ref_node(vap->iv_bss); 2184 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 2185 2186 /* Accept beacons with the same BSSID. */ 2187 urtwn_set_rx_bssid_all(sc, 0); 2188 2189 /* Enable synchronization. */ 2190 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 2191 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2192 2193 /* Synchronize. */ 2194 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 2195 2196 /* Disable synchronization. */ 2197 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 2198 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2199 2200 /* Remove beacon filter. */ 2201 urtwn_set_rx_bssid_all(sc, 1); 2202 2203 /* Enable beaconing. */ 2204 urtwn_write_1(sc, R92C_MBID_NUM, 2205 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2206 reg |= R92C_BCN_CTRL_EN_BCN; 2207 2208 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2209 ieee80211_free_node(ni); 2210 URTWN_UNLOCK(sc); 2211} 2212 2213static void 2214urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 2215{ 2216 struct ieee80211com *ic = &sc->sc_ic; 2217 struct urtwn_vap *uvp = URTWN_VAP(vap); 2218 2219 /* Reset TSF. */ 2220 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2221 2222 switch (vap->iv_opmode) { 2223 case IEEE80211_M_STA: 2224 /* Enable TSF synchronization. */ 2225 urtwn_write_1(sc, R92C_BCN_CTRL, 2226 urtwn_read_1(sc, R92C_BCN_CTRL) & 2227 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 2228 break; 2229 case IEEE80211_M_IBSS: 2230 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 2231 break; 2232 case IEEE80211_M_HOSTAP: 2233 /* Enable beaconing. */ 2234 urtwn_write_1(sc, R92C_MBID_NUM, 2235 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2236 urtwn_write_1(sc, R92C_BCN_CTRL, 2237 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 2238 break; 2239 default: 2240 device_printf(sc->sc_dev, "undefined opmode %d\n", 2241 vap->iv_opmode); 2242 return; 2243 } 2244} 2245 2246static void 2247urtwn_get_tsf(struct urtwn_softc *sc, uint64_t *buf) 2248{ 2249 urtwn_read_region_1(sc, R92C_TSFTR, (uint8_t *)buf, sizeof(*buf)); 2250} 2251 2252static void 2253urtwn_set_led(struct urtwn_softc *sc, int led, int on) 2254{ 2255 uint8_t reg; 2256 2257 if (led == URTWN_LED_LINK) { 2258 if (sc->chip & URTWN_CHIP_88E) { 2259 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 2260 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 2261 if (!on) { 2262 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 2263 urtwn_write_1(sc, R92C_LEDCFG2, 2264 reg | R92C_LEDCFG0_DIS); 2265 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 2266 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 2267 0xfe); 2268 } 2269 } else { 2270 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 2271 if (!on) 2272 reg |= R92C_LEDCFG0_DIS; 2273 urtwn_write_1(sc, R92C_LEDCFG0, reg); 2274 } 2275 sc->ledlink = on; /* Save LED state. */ 2276 } 2277} 2278 2279static void 2280urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 2281{ 2282 uint8_t reg; 2283 2284 reg = urtwn_read_1(sc, R92C_MSR); 2285 reg = (reg & ~R92C_MSR_MASK) | mode; 2286 urtwn_write_1(sc, R92C_MSR, reg); 2287} 2288 2289static void 2290urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 2291 const struct ieee80211_rx_stats *rxs, 2292 int rssi, int nf) 2293{ 2294 struct ieee80211vap *vap = ni->ni_vap; 2295 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2296 struct urtwn_vap *uvp = URTWN_VAP(vap); 2297 uint64_t ni_tstamp, curr_tstamp; 2298 2299 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 2300 2301 if (vap->iv_state == IEEE80211_S_RUN && 2302 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 2303 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 2304 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 2305 URTWN_LOCK(sc); 2306 urtwn_get_tsf(sc, &curr_tstamp); 2307 URTWN_UNLOCK(sc); 2308 curr_tstamp = le64toh(curr_tstamp); 2309 2310 if (ni_tstamp >= curr_tstamp) 2311 (void) ieee80211_ibss_merge(ni); 2312 } 2313} 2314 2315static int 2316urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2317{ 2318 struct urtwn_vap *uvp = URTWN_VAP(vap); 2319 struct ieee80211com *ic = vap->iv_ic; 2320 struct urtwn_softc *sc = ic->ic_softc; 2321 struct ieee80211_node *ni; 2322 enum ieee80211_state ostate; 2323 uint32_t reg; 2324 uint8_t mode; 2325 int error = 0; 2326 2327 ostate = vap->iv_state; 2328 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s -> %s\n", 2329 ieee80211_state_name[ostate], ieee80211_state_name[nstate]); 2330 2331 IEEE80211_UNLOCK(ic); 2332 URTWN_LOCK(sc); 2333 callout_stop(&sc->sc_watchdog_ch); 2334 2335 if (ostate == IEEE80211_S_RUN) { 2336 /* Stop calibration. */ 2337 callout_stop(&sc->sc_calib_to); 2338 2339 /* Turn link LED off. */ 2340 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2341 2342 /* Set media status to 'No Link'. */ 2343 urtwn_set_mode(sc, R92C_MSR_NOLINK); 2344 2345 /* Stop Rx of data frames. */ 2346 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2347 2348 /* Disable TSF synchronization. */ 2349 urtwn_write_1(sc, R92C_BCN_CTRL, 2350 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 2351 R92C_BCN_CTRL_DIS_TSF_UDT0); 2352 2353 /* Disable beaconing. */ 2354 urtwn_write_1(sc, R92C_MBID_NUM, 2355 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 2356 2357 /* Reset TSF. */ 2358 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2359 2360 /* Reset EDCA parameters. */ 2361 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2362 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2363 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2364 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2365 } 2366 2367 switch (nstate) { 2368 case IEEE80211_S_INIT: 2369 /* Turn link LED off. */ 2370 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2371 break; 2372 case IEEE80211_S_SCAN: 2373 /* Pause AC Tx queues. */ 2374 urtwn_write_1(sc, R92C_TXPAUSE, 2375 urtwn_read_1(sc, R92C_TXPAUSE) | R92C_TX_QUEUE_AC); 2376 break; 2377 case IEEE80211_S_AUTH: 2378 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2379 break; 2380 case IEEE80211_S_RUN: 2381 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2382 /* Turn link LED on. */ 2383 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2384 break; 2385 } 2386 2387 ni = ieee80211_ref_node(vap->iv_bss); 2388 2389 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2390 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2391 device_printf(sc->sc_dev, 2392 "%s: could not move to RUN state\n", __func__); 2393 error = EINVAL; 2394 goto end_run; 2395 } 2396 2397 switch (vap->iv_opmode) { 2398 case IEEE80211_M_STA: 2399 mode = R92C_MSR_INFRA; 2400 break; 2401 case IEEE80211_M_IBSS: 2402 mode = R92C_MSR_ADHOC; 2403 break; 2404 case IEEE80211_M_HOSTAP: 2405 mode = R92C_MSR_AP; 2406 break; 2407 default: 2408 device_printf(sc->sc_dev, "undefined opmode %d\n", 2409 vap->iv_opmode); 2410 error = EINVAL; 2411 goto end_run; 2412 } 2413 2414 /* Set media status to 'Associated'. */ 2415 urtwn_set_mode(sc, mode); 2416 2417 /* Set BSSID. */ 2418 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2419 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2420 2421 if (ic->ic_curmode == IEEE80211_MODE_11B) 2422 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2423 else /* 802.11b/g */ 2424 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2425 2426 /* Enable Rx of data frames. */ 2427 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2428 2429 /* Flush all AC queues. */ 2430 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2431 2432 /* Set beacon interval. */ 2433 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2434 2435 /* Allow Rx from our BSSID only. */ 2436 if (ic->ic_promisc == 0) { 2437 reg = urtwn_read_4(sc, R92C_RCR); 2438 2439 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 2440 reg |= R92C_RCR_CBSSID_DATA; 2441 if (vap->iv_opmode != IEEE80211_M_IBSS) 2442 reg |= R92C_RCR_CBSSID_BCN; 2443 2444 urtwn_write_4(sc, R92C_RCR, reg); 2445 } 2446 2447 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2448 vap->iv_opmode == IEEE80211_M_IBSS) { 2449 error = urtwn_setup_beacon(sc, ni); 2450 if (error != 0) { 2451 device_printf(sc->sc_dev, 2452 "unable to push beacon into the chip, " 2453 "error %d\n", error); 2454 goto end_run; 2455 } 2456 } 2457 2458 /* Enable TSF synchronization. */ 2459 urtwn_tsf_sync_enable(sc, vap); 2460 2461 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2462 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2463 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2464 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2465 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2466 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2467 2468 /* Intialize rate adaptation. */ 2469 if (!(sc->chip & URTWN_CHIP_88E)) 2470 urtwn_ra_init(sc); 2471 /* Turn link LED on. */ 2472 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2473 2474 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2475 /* Reset temperature calibration state machine. */ 2476 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 2477 sc->thcal_lctemp = 0; 2478 /* Start periodic calibration. */ 2479 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2480 2481end_run: 2482 ieee80211_free_node(ni); 2483 break; 2484 default: 2485 break; 2486 } 2487 2488 URTWN_UNLOCK(sc); 2489 IEEE80211_LOCK(ic); 2490 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2491} 2492 2493static void 2494urtwn_calib_to(void *arg) 2495{ 2496 struct urtwn_softc *sc = arg; 2497 2498 /* Do it in a process context. */ 2499 urtwn_cmd_sleepable(sc, NULL, 0, urtwn_calib_cb); 2500} 2501 2502static void 2503urtwn_calib_cb(struct urtwn_softc *sc, union sec_param *data) 2504{ 2505 /* Do temperature compensation. */ 2506 urtwn_temp_calib(sc); 2507 2508 if ((urtwn_read_1(sc, R92C_MSR) & R92C_MSR_MASK) != R92C_MSR_NOLINK) 2509 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2510} 2511 2512static void 2513urtwn_watchdog(void *arg) 2514{ 2515 struct urtwn_softc *sc = arg; 2516 2517 if (sc->sc_txtimer > 0) { 2518 if (--sc->sc_txtimer == 0) { 2519 device_printf(sc->sc_dev, "device timeout\n"); 2520 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2521 return; 2522 } 2523 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2524 } 2525} 2526 2527static void 2528urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2529{ 2530 int pwdb; 2531 2532 /* Convert antenna signal to percentage. */ 2533 if (rssi <= -100 || rssi >= 20) 2534 pwdb = 0; 2535 else if (rssi >= 0) 2536 pwdb = 100; 2537 else 2538 pwdb = 100 + rssi; 2539 if (!(sc->chip & URTWN_CHIP_88E)) { 2540 if (rate <= URTWN_RIDX_CCK11) { 2541 /* CCK gain is smaller than OFDM/MCS gain. */ 2542 pwdb += 6; 2543 if (pwdb > 100) 2544 pwdb = 100; 2545 if (pwdb <= 14) 2546 pwdb -= 4; 2547 else if (pwdb <= 26) 2548 pwdb -= 8; 2549 else if (pwdb <= 34) 2550 pwdb -= 6; 2551 else if (pwdb <= 42) 2552 pwdb -= 2; 2553 } 2554 } 2555 if (sc->avg_pwdb == -1) /* Init. */ 2556 sc->avg_pwdb = pwdb; 2557 else if (sc->avg_pwdb < pwdb) 2558 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2559 else 2560 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2561 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: PWDB %d, EMA %d\n", __func__, 2562 pwdb, sc->avg_pwdb); 2563} 2564 2565static int8_t 2566urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2567{ 2568 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2569 struct r92c_rx_phystat *phy; 2570 struct r92c_rx_cck *cck; 2571 uint8_t rpt; 2572 int8_t rssi; 2573 2574 if (rate <= URTWN_RIDX_CCK11) { 2575 cck = (struct r92c_rx_cck *)physt; 2576 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2577 rpt = (cck->agc_rpt >> 5) & 0x3; 2578 rssi = (cck->agc_rpt & 0x1f) << 1; 2579 } else { 2580 rpt = (cck->agc_rpt >> 6) & 0x3; 2581 rssi = cck->agc_rpt & 0x3e; 2582 } 2583 rssi = cckoff[rpt] - rssi; 2584 } else { /* OFDM/HT. */ 2585 phy = (struct r92c_rx_phystat *)physt; 2586 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2587 } 2588 return (rssi); 2589} 2590 2591static int8_t 2592urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2593{ 2594 struct r92c_rx_phystat *phy; 2595 struct r88e_rx_cck *cck; 2596 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2597 int8_t rssi; 2598 2599 rssi = 0; 2600 if (rate <= URTWN_RIDX_CCK11) { 2601 cck = (struct r88e_rx_cck *)physt; 2602 cck_agc_rpt = cck->agc_rpt; 2603 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2604 vga_idx = cck_agc_rpt & 0x1f; 2605 switch (lna_idx) { 2606 case 7: 2607 if (vga_idx <= 27) 2608 rssi = -100 + 2* (27 - vga_idx); 2609 else 2610 rssi = -100; 2611 break; 2612 case 6: 2613 rssi = -48 + 2 * (2 - vga_idx); 2614 break; 2615 case 5: 2616 rssi = -42 + 2 * (7 - vga_idx); 2617 break; 2618 case 4: 2619 rssi = -36 + 2 * (7 - vga_idx); 2620 break; 2621 case 3: 2622 rssi = -24 + 2 * (7 - vga_idx); 2623 break; 2624 case 2: 2625 rssi = -12 + 2 * (5 - vga_idx); 2626 break; 2627 case 1: 2628 rssi = 8 - (2 * vga_idx); 2629 break; 2630 case 0: 2631 rssi = 14 - (2 * vga_idx); 2632 break; 2633 } 2634 rssi += 6; 2635 } else { /* OFDM/HT. */ 2636 phy = (struct r92c_rx_phystat *)physt; 2637 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2638 } 2639 return (rssi); 2640} 2641 2642static __inline uint8_t 2643rate2ridx(uint8_t rate) 2644{ 2645 switch (rate) { 2646 case 12: return 4; 2647 case 18: return 5; 2648 case 24: return 6; 2649 case 36: return 7; 2650 case 48: return 8; 2651 case 72: return 9; 2652 case 96: return 10; 2653 case 108: return 11; 2654 case 2: return 0; 2655 case 4: return 1; 2656 case 11: return 2; 2657 case 22: return 3; 2658 default: return 0; 2659 } 2660} 2661 2662static int 2663urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2664 struct mbuf *m, struct urtwn_data *data) 2665{ 2666 const struct ieee80211_txparam *tp; 2667 struct ieee80211com *ic = &sc->sc_ic; 2668 struct ieee80211vap *vap = ni->ni_vap; 2669 struct ieee80211_key *k = NULL; 2670 struct ieee80211_channel *chan; 2671 struct ieee80211_frame *wh; 2672 struct r92c_tx_desc *txd; 2673 uint8_t macid, raid, rate, ridx, subtype, type, tid, qsel; 2674 int hasqos, ismcast; 2675 2676 URTWN_ASSERT_LOCKED(sc); 2677 2678 /* 2679 * Software crypto. 2680 */ 2681 wh = mtod(m, struct ieee80211_frame *); 2682 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2683 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2684 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2685 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2686 2687 /* Select TX ring for this frame. */ 2688 if (hasqos) { 2689 tid = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2690 tid &= IEEE80211_QOS_TID; 2691 } else 2692 tid = 0; 2693 2694 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2695 ni->ni_chan : ic->ic_curchan; 2696 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2697 2698 /* Choose a TX rate index. */ 2699 if (type == IEEE80211_FC0_TYPE_MGT) 2700 rate = tp->mgmtrate; 2701 else if (ismcast) 2702 rate = tp->mcastrate; 2703 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2704 rate = tp->ucastrate; 2705 else if (m->m_flags & M_EAPOL) 2706 rate = tp->mgmtrate; 2707 else { 2708 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2709 /* XXX pass pktlen */ 2710 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2711 rate = ni->ni_txrate; 2712 } else { 2713 if (ic->ic_curmode != IEEE80211_MODE_11B) 2714 rate = 108; 2715 else 2716 rate = 22; 2717 } 2718 } 2719 2720 ridx = rate2ridx(rate); 2721 if (ic->ic_curmode != IEEE80211_MODE_11B) 2722 raid = R92C_RAID_11BG; 2723 else 2724 raid = R92C_RAID_11B; 2725 2726 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2727 k = ieee80211_crypto_encap(ni, m); 2728 if (k == NULL) { 2729 device_printf(sc->sc_dev, 2730 "ieee80211_crypto_encap returns NULL.\n"); 2731 return (ENOBUFS); 2732 } 2733 2734 /* in case packet header moved, reset pointer */ 2735 wh = mtod(m, struct ieee80211_frame *); 2736 } 2737 2738 /* Fill Tx descriptor. */ 2739 txd = (struct r92c_tx_desc *)data->buf; 2740 memset(txd, 0, sizeof(*txd)); 2741 2742 txd->txdw0 |= htole32( 2743 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2744 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2745 if (ismcast) 2746 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2747 2748 if (!ismcast) { 2749 if (sc->chip & URTWN_CHIP_88E) { 2750 struct urtwn_node *un = URTWN_NODE(ni); 2751 macid = un->id; 2752 } else 2753 macid = URTWN_MACID_BSS; 2754 2755 if (type == IEEE80211_FC0_TYPE_DATA) { 2756 qsel = tid % URTWN_MAX_TID; 2757 2758 if (sc->chip & URTWN_CHIP_88E) { 2759 txd->txdw2 |= htole32( 2760 R88E_TXDW2_AGGBK | 2761 R88E_TXDW2_CCX_RPT); 2762 } else 2763 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2764 2765 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2766 switch (ic->ic_protmode) { 2767 case IEEE80211_PROT_CTSONLY: 2768 txd->txdw4 |= htole32( 2769 R92C_TXDW4_CTS2SELF | 2770 R92C_TXDW4_HWRTSEN); 2771 break; 2772 case IEEE80211_PROT_RTSCTS: 2773 txd->txdw4 |= htole32( 2774 R92C_TXDW4_RTSEN | 2775 R92C_TXDW4_HWRTSEN); 2776 break; 2777 default: 2778 break; 2779 } 2780 } 2781 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2782 URTWN_RIDX_OFDM24)); 2783 txd->txdw5 |= htole32(0x0001ff00); 2784 } else /* IEEE80211_FC0_TYPE_MGT */ 2785 qsel = R92C_TXDW1_QSEL_MGNT; 2786 } else { 2787 macid = URTWN_MACID_BC; 2788 qsel = R92C_TXDW1_QSEL_MGNT; 2789 } 2790 2791 txd->txdw1 |= htole32( 2792 SM(R92C_TXDW1_QSEL, qsel) | 2793 SM(R92C_TXDW1_RAID, raid)); 2794 2795 if (sc->chip & URTWN_CHIP_88E) 2796 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 2797 else 2798 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 2799 2800 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2801 /* Force this rate if needed. */ 2802 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 2803 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 2804 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2805 2806 if (!hasqos) { 2807 /* Use HW sequence numbering for non-QoS frames. */ 2808 if (sc->chip & URTWN_CHIP_88E) 2809 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2810 else 2811 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2812 } else { 2813 /* Set sequence number. */ 2814 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2815 } 2816 2817 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2818 uint8_t cipher; 2819 2820 switch (k->wk_cipher->ic_cipher) { 2821 case IEEE80211_CIPHER_WEP: 2822 case IEEE80211_CIPHER_TKIP: 2823 cipher = R92C_TXDW1_CIPHER_RC4; 2824 break; 2825 case IEEE80211_CIPHER_AES_CCM: 2826 cipher = R92C_TXDW1_CIPHER_AES; 2827 break; 2828 default: 2829 device_printf(sc->sc_dev, "%s: unknown cipher %d\n", 2830 __func__, k->wk_cipher->ic_cipher); 2831 return (EINVAL); 2832 } 2833 2834 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 2835 } 2836 2837 if (ieee80211_radiotap_active_vap(vap)) { 2838 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2839 2840 tap->wt_flags = 0; 2841 if (k != NULL) 2842 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2843 ieee80211_radiotap_tx(vap, m); 2844 } 2845 2846 data->ni = ni; 2847 2848 urtwn_tx_start(sc, m, type, data); 2849 2850 return (0); 2851} 2852 2853static int 2854urtwn_tx_raw(struct urtwn_softc *sc, struct ieee80211_node *ni, 2855 struct mbuf *m, struct urtwn_data *data, 2856 const struct ieee80211_bpf_params *params) 2857{ 2858 struct ieee80211vap *vap = ni->ni_vap; 2859 struct ieee80211_key *k = NULL; 2860 struct ieee80211_frame *wh; 2861 struct r92c_tx_desc *txd; 2862 uint8_t cipher, ridx, type; 2863 2864 /* Encrypt the frame if need be. */ 2865 cipher = R92C_TXDW1_CIPHER_NONE; 2866 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 2867 /* Retrieve key for TX. */ 2868 k = ieee80211_crypto_encap(ni, m); 2869 if (k == NULL) 2870 return (ENOBUFS); 2871 2872 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2873 switch (k->wk_cipher->ic_cipher) { 2874 case IEEE80211_CIPHER_WEP: 2875 case IEEE80211_CIPHER_TKIP: 2876 cipher = R92C_TXDW1_CIPHER_RC4; 2877 break; 2878 case IEEE80211_CIPHER_AES_CCM: 2879 cipher = R92C_TXDW1_CIPHER_AES; 2880 break; 2881 default: 2882 device_printf(sc->sc_dev, 2883 "%s: unknown cipher %d\n", 2884 __func__, k->wk_cipher->ic_cipher); 2885 return (EINVAL); 2886 } 2887 } 2888 } 2889 2890 wh = mtod(m, struct ieee80211_frame *); 2891 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2892 2893 /* Fill Tx descriptor. */ 2894 txd = (struct r92c_tx_desc *)data->buf; 2895 memset(txd, 0, sizeof(*txd)); 2896 2897 txd->txdw0 |= htole32( 2898 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2899 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2900 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2901 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2902 2903 if (params->ibp_flags & IEEE80211_BPF_RTS) 2904 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN); 2905 if (params->ibp_flags & IEEE80211_BPF_CTS) 2906 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF); 2907 if (txd->txdw4 & htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_CTS2SELF)) { 2908 txd->txdw4 |= htole32(R92C_TXDW4_HWRTSEN); 2909 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2910 URTWN_RIDX_OFDM24)); 2911 } 2912 2913 if (sc->chip & URTWN_CHIP_88E) 2914 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 2915 else 2916 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 2917 2918 txd->txdw1 |= htole32(SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT)); 2919 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 2920 2921 /* Choose a TX rate index. */ 2922 ridx = rate2ridx(params->ibp_rate0); 2923 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2924 txd->txdw5 |= htole32(0x0001ff00); 2925 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2926 2927 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 2928 /* Use HW sequence numbering for non-QoS frames. */ 2929 if (sc->chip & URTWN_CHIP_88E) 2930 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2931 else 2932 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2933 } else { 2934 /* Set sequence number. */ 2935 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2936 } 2937 2938 if (ieee80211_radiotap_active_vap(vap)) { 2939 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2940 2941 tap->wt_flags = 0; 2942 if (k != NULL) 2943 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2944 ieee80211_radiotap_tx(vap, m); 2945 } 2946 2947 data->ni = ni; 2948 2949 urtwn_tx_start(sc, m, type, data); 2950 2951 return (0); 2952} 2953 2954static void 2955urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 2956 struct urtwn_data *data) 2957{ 2958 struct usb_xfer *xfer; 2959 struct r92c_tx_desc *txd; 2960 uint16_t ac, sum; 2961 int i, xferlen; 2962 2963 URTWN_ASSERT_LOCKED(sc); 2964 2965 ac = M_WME_GETAC(m); 2966 2967 switch (type) { 2968 case IEEE80211_FC0_TYPE_CTL: 2969 case IEEE80211_FC0_TYPE_MGT: 2970 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 2971 break; 2972 default: 2973 xfer = sc->sc_xfer[wme2queue[ac].qid]; 2974 break; 2975 } 2976 2977 txd = (struct r92c_tx_desc *)data->buf; 2978 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 2979 2980 /* Compute Tx descriptor checksum. */ 2981 sum = 0; 2982 for (i = 0; i < sizeof(*txd) / 2; i++) 2983 sum ^= ((uint16_t *)txd)[i]; 2984 txd->txdsum = sum; /* NB: already little endian. */ 2985 2986 xferlen = sizeof(*txd) + m->m_pkthdr.len; 2987 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 2988 2989 data->buflen = xferlen; 2990 data->m = m; 2991 2992 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 2993 usbd_transfer_start(xfer); 2994} 2995 2996static int 2997urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 2998{ 2999 struct urtwn_softc *sc = ic->ic_softc; 3000 int error; 3001 3002 URTWN_LOCK(sc); 3003 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 3004 URTWN_UNLOCK(sc); 3005 return (ENXIO); 3006 } 3007 error = mbufq_enqueue(&sc->sc_snd, m); 3008 if (error) { 3009 URTWN_UNLOCK(sc); 3010 return (error); 3011 } 3012 urtwn_start(sc); 3013 URTWN_UNLOCK(sc); 3014 3015 return (0); 3016} 3017 3018static void 3019urtwn_start(struct urtwn_softc *sc) 3020{ 3021 struct ieee80211_node *ni; 3022 struct mbuf *m; 3023 struct urtwn_data *bf; 3024 3025 URTWN_ASSERT_LOCKED(sc); 3026 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 3027 bf = urtwn_getbuf(sc); 3028 if (bf == NULL) { 3029 mbufq_prepend(&sc->sc_snd, m); 3030 break; 3031 } 3032 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3033 m->m_pkthdr.rcvif = NULL; 3034 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 3035 if_inc_counter(ni->ni_vap->iv_ifp, 3036 IFCOUNTER_OERRORS, 1); 3037 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3038 m_freem(m); 3039 ieee80211_free_node(ni); 3040 break; 3041 } 3042 sc->sc_txtimer = 5; 3043 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3044 } 3045} 3046 3047static void 3048urtwn_parent(struct ieee80211com *ic) 3049{ 3050 struct urtwn_softc *sc = ic->ic_softc; 3051 3052 URTWN_LOCK(sc); 3053 if (sc->sc_flags & URTWN_DETACHED) { 3054 URTWN_UNLOCK(sc); 3055 return; 3056 } 3057 URTWN_UNLOCK(sc); 3058 3059 if (ic->ic_nrunning > 0) { 3060 if (urtwn_init(sc) != 0) { 3061 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3062 if (vap != NULL) 3063 ieee80211_stop(vap); 3064 } else 3065 ieee80211_start_all(ic); 3066 } else 3067 urtwn_stop(sc); 3068} 3069 3070static __inline int 3071urtwn_power_on(struct urtwn_softc *sc) 3072{ 3073 3074 return sc->sc_power_on(sc); 3075} 3076 3077static int 3078urtwn_r92c_power_on(struct urtwn_softc *sc) 3079{ 3080 uint32_t reg; 3081 usb_error_t error; 3082 int ntries; 3083 3084 /* Wait for autoload done bit. */ 3085 for (ntries = 0; ntries < 1000; ntries++) { 3086 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3087 break; 3088 urtwn_ms_delay(sc); 3089 } 3090 if (ntries == 1000) { 3091 device_printf(sc->sc_dev, 3092 "timeout waiting for chip autoload\n"); 3093 return (ETIMEDOUT); 3094 } 3095 3096 /* Unlock ISO/CLK/Power control register. */ 3097 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3098 if (error != USB_ERR_NORMAL_COMPLETION) 3099 return (EIO); 3100 /* Move SPS into PWM mode. */ 3101 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3102 if (error != USB_ERR_NORMAL_COMPLETION) 3103 return (EIO); 3104 urtwn_ms_delay(sc); 3105 3106 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3107 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3108 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3109 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3110 if (error != USB_ERR_NORMAL_COMPLETION) 3111 return (EIO); 3112 urtwn_ms_delay(sc); 3113 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3114 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3115 ~R92C_SYS_ISO_CTRL_MD2PP); 3116 if (error != USB_ERR_NORMAL_COMPLETION) 3117 return (EIO); 3118 } 3119 3120 /* Auto enable WLAN. */ 3121 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3122 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3123 if (error != USB_ERR_NORMAL_COMPLETION) 3124 return (EIO); 3125 for (ntries = 0; ntries < 1000; ntries++) { 3126 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3127 R92C_APS_FSMCO_APFM_ONMAC)) 3128 break; 3129 urtwn_ms_delay(sc); 3130 } 3131 if (ntries == 1000) { 3132 device_printf(sc->sc_dev, 3133 "timeout waiting for MAC auto ON\n"); 3134 return (ETIMEDOUT); 3135 } 3136 3137 /* Enable radio, GPIO and LED functions. */ 3138 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3139 R92C_APS_FSMCO_AFSM_HSUS | 3140 R92C_APS_FSMCO_PDN_EN | 3141 R92C_APS_FSMCO_PFM_ALDN); 3142 if (error != USB_ERR_NORMAL_COMPLETION) 3143 return (EIO); 3144 /* Release RF digital isolation. */ 3145 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3146 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3147 if (error != USB_ERR_NORMAL_COMPLETION) 3148 return (EIO); 3149 3150 /* Initialize MAC. */ 3151 error = urtwn_write_1(sc, R92C_APSD_CTRL, 3152 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3153 if (error != USB_ERR_NORMAL_COMPLETION) 3154 return (EIO); 3155 for (ntries = 0; ntries < 200; ntries++) { 3156 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3157 R92C_APSD_CTRL_OFF_STATUS)) 3158 break; 3159 urtwn_ms_delay(sc); 3160 } 3161 if (ntries == 200) { 3162 device_printf(sc->sc_dev, 3163 "timeout waiting for MAC initialization\n"); 3164 return (ETIMEDOUT); 3165 } 3166 3167 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3168 reg = urtwn_read_2(sc, R92C_CR); 3169 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3170 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3171 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3172 R92C_CR_ENSEC; 3173 error = urtwn_write_2(sc, R92C_CR, reg); 3174 if (error != USB_ERR_NORMAL_COMPLETION) 3175 return (EIO); 3176 3177 error = urtwn_write_1(sc, 0xfe10, 0x19); 3178 if (error != USB_ERR_NORMAL_COMPLETION) 3179 return (EIO); 3180 return (0); 3181} 3182 3183static int 3184urtwn_r88e_power_on(struct urtwn_softc *sc) 3185{ 3186 uint32_t reg; 3187 usb_error_t error; 3188 int ntries; 3189 3190 /* Wait for power ready bit. */ 3191 for (ntries = 0; ntries < 5000; ntries++) { 3192 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 3193 break; 3194 urtwn_ms_delay(sc); 3195 } 3196 if (ntries == 5000) { 3197 device_printf(sc->sc_dev, 3198 "timeout waiting for chip power up\n"); 3199 return (ETIMEDOUT); 3200 } 3201 3202 /* Reset BB. */ 3203 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3204 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3205 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3206 if (error != USB_ERR_NORMAL_COMPLETION) 3207 return (EIO); 3208 3209 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3210 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3211 if (error != USB_ERR_NORMAL_COMPLETION) 3212 return (EIO); 3213 3214 /* Disable HWPDN. */ 3215 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3216 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3217 if (error != USB_ERR_NORMAL_COMPLETION) 3218 return (EIO); 3219 3220 /* Disable WL suspend. */ 3221 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3222 urtwn_read_2(sc, R92C_APS_FSMCO) & 3223 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 3224 if (error != USB_ERR_NORMAL_COMPLETION) 3225 return (EIO); 3226 3227 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3228 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3229 if (error != USB_ERR_NORMAL_COMPLETION) 3230 return (EIO); 3231 for (ntries = 0; ntries < 5000; ntries++) { 3232 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3233 R92C_APS_FSMCO_APFM_ONMAC)) 3234 break; 3235 urtwn_ms_delay(sc); 3236 } 3237 if (ntries == 5000) 3238 return (ETIMEDOUT); 3239 3240 /* Enable LDO normal mode. */ 3241 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 3242 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~R92C_LPLDO_CTRL_SLEEP); 3243 if (error != USB_ERR_NORMAL_COMPLETION) 3244 return (EIO); 3245 3246 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3247 error = urtwn_write_2(sc, R92C_CR, 0); 3248 if (error != USB_ERR_NORMAL_COMPLETION) 3249 return (EIO); 3250 reg = urtwn_read_2(sc, R92C_CR); 3251 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3252 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3253 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3254 error = urtwn_write_2(sc, R92C_CR, reg); 3255 if (error != USB_ERR_NORMAL_COMPLETION) 3256 return (EIO); 3257 3258 return (0); 3259} 3260 3261static __inline void 3262urtwn_power_off(struct urtwn_softc *sc) 3263{ 3264 3265 return sc->sc_power_off(sc); 3266} 3267 3268static void 3269urtwn_r92c_power_off(struct urtwn_softc *sc) 3270{ 3271 uint32_t reg; 3272 3273 /* Block all Tx queues. */ 3274 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3275 3276 /* Disable RF */ 3277 urtwn_rf_write(sc, 0, 0, 0); 3278 3279 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 3280 3281 /* Reset BB state machine */ 3282 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3283 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA | 3284 R92C_SYS_FUNC_EN_BB_GLB_RST); 3285 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3286 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 3287 3288 /* 3289 * Reset digital sequence 3290 */ 3291#ifndef URTWN_WITHOUT_UCODE 3292 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 3293 /* Reset MCU ready status */ 3294 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3295 3296 /* If firmware in ram code, do reset */ 3297 urtwn_fw_reset(sc); 3298 } 3299#endif 3300 3301 /* Reset MAC and Enable 8051 */ 3302 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 3303 (R92C_SYS_FUNC_EN_CPUEN | 3304 R92C_SYS_FUNC_EN_ELDR | 3305 R92C_SYS_FUNC_EN_HWPDN) >> 8); 3306 3307 /* Reset MCU ready status */ 3308 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3309 3310 /* Disable MAC clock */ 3311 urtwn_write_2(sc, R92C_SYS_CLKR, 3312 R92C_SYS_CLKR_ANAD16V_EN | 3313 R92C_SYS_CLKR_ANA8M | 3314 R92C_SYS_CLKR_LOADER_EN | 3315 R92C_SYS_CLKR_80M_SSC_DIS | 3316 R92C_SYS_CLKR_SYS_EN | 3317 R92C_SYS_CLKR_RING_EN | 3318 0x4000); 3319 3320 /* Disable AFE PLL */ 3321 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 3322 3323 /* Gated AFE DIG_CLOCK */ 3324 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 3325 3326 /* Isolated digital to PON */ 3327 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3328 R92C_SYS_ISO_CTRL_MD2PP | 3329 R92C_SYS_ISO_CTRL_PA2PCIE | 3330 R92C_SYS_ISO_CTRL_PD2CORE | 3331 R92C_SYS_ISO_CTRL_IP2MAC | 3332 R92C_SYS_ISO_CTRL_DIOP | 3333 R92C_SYS_ISO_CTRL_DIOE); 3334 3335 /* 3336 * Pull GPIO PIN to balance level and LED control 3337 */ 3338 /* 1. Disable GPIO[7:0] */ 3339 urtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000); 3340 3341 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 3342 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 3343 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 3344 3345 /* Disable GPIO[10:8] */ 3346 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x00); 3347 3348 reg = urtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0; 3349 reg |= (((reg & 0x000f) << 4) | 0x0780); 3350 urtwn_write_2(sc, R92C_GPIO_IO_SEL, reg); 3351 3352 /* Disable LED0 & 1 */ 3353 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 3354 3355 /* 3356 * Reset digital sequence 3357 */ 3358 /* Disable ELDR clock */ 3359 urtwn_write_2(sc, R92C_SYS_CLKR, 3360 R92C_SYS_CLKR_ANAD16V_EN | 3361 R92C_SYS_CLKR_ANA8M | 3362 R92C_SYS_CLKR_LOADER_EN | 3363 R92C_SYS_CLKR_80M_SSC_DIS | 3364 R92C_SYS_CLKR_SYS_EN | 3365 R92C_SYS_CLKR_RING_EN | 3366 0x4000); 3367 3368 /* Isolated ELDR to PON */ 3369 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 3370 (R92C_SYS_ISO_CTRL_DIOR | 3371 R92C_SYS_ISO_CTRL_PWC_EV12V) >> 8); 3372 3373 /* 3374 * Disable analog sequence 3375 */ 3376 /* Disable A15 power */ 3377 urtwn_write_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_OBUF); 3378 /* Disable digital core power */ 3379 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3380 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 3381 ~R92C_LDOV12D_CTRL_LDV12_EN); 3382 3383 /* Enter PFM mode */ 3384 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 3385 3386 /* Set USB suspend */ 3387 urtwn_write_2(sc, R92C_APS_FSMCO, 3388 R92C_APS_FSMCO_APDM_HOST | 3389 R92C_APS_FSMCO_AFSM_HSUS | 3390 R92C_APS_FSMCO_PFM_ALDN); 3391 3392 /* Lock ISO/CLK/Power control register. */ 3393 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 3394} 3395 3396static void 3397urtwn_r88e_power_off(struct urtwn_softc *sc) 3398{ 3399 uint8_t reg; 3400 int ntries; 3401 3402 /* Disable any kind of TX reports. */ 3403 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 3404 urtwn_read_1(sc, R88E_TX_RPT_CTRL) & 3405 ~(R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA)); 3406 3407 /* Stop Rx. */ 3408 urtwn_write_1(sc, R92C_CR, 0); 3409 3410 /* Move card to Low Power State. */ 3411 /* Block all Tx queues. */ 3412 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 3413 3414 for (ntries = 0; ntries < 20; ntries++) { 3415 /* Should be zero if no packet is transmitting. */ 3416 if (urtwn_read_4(sc, R88E_SCH_TXCMD) == 0) 3417 break; 3418 3419 urtwn_ms_delay(sc); 3420 } 3421 if (ntries == 20) { 3422 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n", 3423 __func__); 3424 return; 3425 } 3426 3427 /* CCK and OFDM are disabled, and clock are gated. */ 3428 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3429 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_BBRSTB); 3430 3431 urtwn_ms_delay(sc); 3432 3433 /* Reset MAC TRX */ 3434 urtwn_write_1(sc, R92C_CR, 3435 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3436 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | 3437 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN); 3438 3439 /* check if removed later */ 3440 urtwn_write_1(sc, R92C_CR + 1, 3441 urtwn_read_1(sc, R92C_CR + 1) & ~(R92C_CR_ENSEC >> 8)); 3442 3443 /* Respond TxOK to scheduler */ 3444 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 3445 urtwn_read_1(sc, R92C_DUAL_TSF_RST) | 0x20); 3446 3447 /* If firmware in ram code, do reset. */ 3448#ifndef URTWN_WITHOUT_UCODE 3449 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) 3450 urtwn_r88e_fw_reset(sc); 3451#endif 3452 3453 /* Reset MCU ready status. */ 3454 urtwn_write_1(sc, R92C_MCUFWDL, 0x00); 3455 3456 /* Disable 32k. */ 3457 urtwn_write_1(sc, R88E_32K_CTRL, 3458 urtwn_read_1(sc, R88E_32K_CTRL) & ~0x01); 3459 3460 /* Move card to Disabled state. */ 3461 /* Turn off RF. */ 3462 urtwn_write_1(sc, R92C_RF_CTRL, 0); 3463 3464 /* LDO Sleep mode. */ 3465 urtwn_write_1(sc, R92C_LPLDO_CTRL, 3466 urtwn_read_1(sc, R92C_LPLDO_CTRL) | R92C_LPLDO_CTRL_SLEEP); 3467 3468 /* Turn off MAC by HW state machine */ 3469 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3470 urtwn_read_1(sc, R92C_APS_FSMCO + 1) | 3471 (R92C_APS_FSMCO_APFM_OFF >> 8)); 3472 3473 for (ntries = 0; ntries < 20; ntries++) { 3474 /* Wait until it will be disabled. */ 3475 if ((urtwn_read_1(sc, R92C_APS_FSMCO + 1) & 3476 (R92C_APS_FSMCO_APFM_OFF >> 8)) == 0) 3477 break; 3478 3479 urtwn_ms_delay(sc); 3480 } 3481 if (ntries == 20) { 3482 device_printf(sc->sc_dev, "%s: could not turn off MAC\n", 3483 __func__); 3484 return; 3485 } 3486 3487 /* schmit trigger */ 3488 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3489 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3490 3491 /* Enable WL suspend. */ 3492 urtwn_write_1(sc, R92C_APS_FSMCO + 1, 3493 (urtwn_read_1(sc, R92C_APS_FSMCO + 1) & ~0x10) | 0x08); 3494 3495 /* Enable bandgap mbias in suspend. */ 3496 urtwn_write_1(sc, R92C_APS_FSMCO + 3, 0); 3497 3498 /* Clear SIC_EN register. */ 3499 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 1, 3500 urtwn_read_1(sc, R92C_GPIO_MUXCFG + 1) & ~0x10); 3501 3502 /* Set USB suspend enable local register */ 3503 urtwn_write_1(sc, R92C_USB_SUSPEND, 3504 urtwn_read_1(sc, R92C_USB_SUSPEND) | 0x10); 3505 3506 /* Reset MCU IO Wrapper. */ 3507 reg = urtwn_read_1(sc, R92C_RSV_CTRL + 1); 3508 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08); 3509 urtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08); 3510 3511 /* marked as 'For Power Consumption' code. */ 3512 urtwn_write_1(sc, R92C_GPIO_OUT, urtwn_read_1(sc, R92C_GPIO_IN)); 3513 urtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff); 3514 3515 urtwn_write_1(sc, R92C_GPIO_IO_SEL, 3516 urtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4); 3517 urtwn_write_1(sc, R92C_GPIO_MOD, 3518 urtwn_read_1(sc, R92C_GPIO_MOD) | 0x0f); 3519 3520 /* Set LNA, TRSW, EX_PA Pin to output mode. */ 3521 urtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808); 3522} 3523 3524static int 3525urtwn_llt_init(struct urtwn_softc *sc) 3526{ 3527 int i, error, page_count, pktbuf_count; 3528 3529 page_count = (sc->chip & URTWN_CHIP_88E) ? 3530 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 3531 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 3532 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 3533 3534 /* Reserve pages [0; page_count]. */ 3535 for (i = 0; i < page_count; i++) { 3536 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3537 return (error); 3538 } 3539 /* NB: 0xff indicates end-of-list. */ 3540 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3541 return (error); 3542 /* 3543 * Use pages [page_count + 1; pktbuf_count - 1] 3544 * as ring buffer. 3545 */ 3546 for (++i; i < pktbuf_count - 1; i++) { 3547 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3548 return (error); 3549 } 3550 /* Make the last page point to the beginning of the ring buffer. */ 3551 error = urtwn_llt_write(sc, i, page_count + 1); 3552 return (error); 3553} 3554 3555#ifndef URTWN_WITHOUT_UCODE 3556static void 3557urtwn_fw_reset(struct urtwn_softc *sc) 3558{ 3559 uint16_t reg; 3560 int ntries; 3561 3562 /* Tell 8051 to reset itself. */ 3563 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3564 3565 /* Wait until 8051 resets by itself. */ 3566 for (ntries = 0; ntries < 100; ntries++) { 3567 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3568 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3569 return; 3570 urtwn_ms_delay(sc); 3571 } 3572 /* Force 8051 reset. */ 3573 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3574} 3575 3576static void 3577urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3578{ 3579 uint16_t reg; 3580 3581 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3582 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3583 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3584} 3585 3586static int 3587urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 3588{ 3589 uint32_t reg; 3590 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 3591 int off, mlen; 3592 3593 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3594 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3595 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3596 3597 off = R92C_FW_START_ADDR; 3598 while (len > 0) { 3599 if (len > 196) 3600 mlen = 196; 3601 else if (len > 4) 3602 mlen = 4; 3603 else 3604 mlen = 1; 3605 /* XXX fix this deconst */ 3606 error = urtwn_write_region_1(sc, off, 3607 __DECONST(uint8_t *, buf), mlen); 3608 if (error != USB_ERR_NORMAL_COMPLETION) 3609 break; 3610 off += mlen; 3611 buf += mlen; 3612 len -= mlen; 3613 } 3614 return (error); 3615} 3616 3617static int 3618urtwn_load_firmware(struct urtwn_softc *sc) 3619{ 3620 const struct firmware *fw; 3621 const struct r92c_fw_hdr *hdr; 3622 const char *imagename; 3623 const u_char *ptr; 3624 size_t len; 3625 uint32_t reg; 3626 int mlen, ntries, page, error; 3627 3628 URTWN_UNLOCK(sc); 3629 /* Read firmware image from the filesystem. */ 3630 if (sc->chip & URTWN_CHIP_88E) 3631 imagename = "urtwn-rtl8188eufw"; 3632 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3633 URTWN_CHIP_UMC_A_CUT) 3634 imagename = "urtwn-rtl8192cfwU"; 3635 else 3636 imagename = "urtwn-rtl8192cfwT"; 3637 3638 fw = firmware_get(imagename); 3639 URTWN_LOCK(sc); 3640 if (fw == NULL) { 3641 device_printf(sc->sc_dev, 3642 "failed loadfirmware of file %s\n", imagename); 3643 return (ENOENT); 3644 } 3645 3646 len = fw->datasize; 3647 3648 if (len < sizeof(*hdr)) { 3649 device_printf(sc->sc_dev, "firmware too short\n"); 3650 error = EINVAL; 3651 goto fail; 3652 } 3653 ptr = fw->data; 3654 hdr = (const struct r92c_fw_hdr *)ptr; 3655 /* Check if there is a valid FW header and skip it. */ 3656 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3657 (le16toh(hdr->signature) >> 4) == 0x88e || 3658 (le16toh(hdr->signature) >> 4) == 0x92c) { 3659 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, 3660 "FW V%d.%d %02d-%02d %02d:%02d\n", 3661 le16toh(hdr->version), le16toh(hdr->subversion), 3662 hdr->month, hdr->date, hdr->hour, hdr->minute); 3663 ptr += sizeof(*hdr); 3664 len -= sizeof(*hdr); 3665 } 3666 3667 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3668 if (sc->chip & URTWN_CHIP_88E) 3669 urtwn_r88e_fw_reset(sc); 3670 else 3671 urtwn_fw_reset(sc); 3672 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3673 } 3674 3675 if (!(sc->chip & URTWN_CHIP_88E)) { 3676 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3677 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3678 R92C_SYS_FUNC_EN_CPUEN); 3679 } 3680 urtwn_write_1(sc, R92C_MCUFWDL, 3681 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3682 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3683 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3684 3685 /* Reset the FWDL checksum. */ 3686 urtwn_write_1(sc, R92C_MCUFWDL, 3687 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3688 3689 for (page = 0; len > 0; page++) { 3690 mlen = min(len, R92C_FW_PAGE_SIZE); 3691 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3692 if (error != 0) { 3693 device_printf(sc->sc_dev, 3694 "could not load firmware page\n"); 3695 goto fail; 3696 } 3697 ptr += mlen; 3698 len -= mlen; 3699 } 3700 urtwn_write_1(sc, R92C_MCUFWDL, 3701 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3702 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3703 3704 /* Wait for checksum report. */ 3705 for (ntries = 0; ntries < 1000; ntries++) { 3706 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3707 break; 3708 urtwn_ms_delay(sc); 3709 } 3710 if (ntries == 1000) { 3711 device_printf(sc->sc_dev, 3712 "timeout waiting for checksum report\n"); 3713 error = ETIMEDOUT; 3714 goto fail; 3715 } 3716 3717 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3718 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3719 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3720 if (sc->chip & URTWN_CHIP_88E) 3721 urtwn_r88e_fw_reset(sc); 3722 /* Wait for firmware readiness. */ 3723 for (ntries = 0; ntries < 1000; ntries++) { 3724 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3725 break; 3726 urtwn_ms_delay(sc); 3727 } 3728 if (ntries == 1000) { 3729 device_printf(sc->sc_dev, 3730 "timeout waiting for firmware readiness\n"); 3731 error = ETIMEDOUT; 3732 goto fail; 3733 } 3734fail: 3735 firmware_put(fw, FIRMWARE_UNLOAD); 3736 return (error); 3737} 3738#endif 3739 3740static int 3741urtwn_dma_init(struct urtwn_softc *sc) 3742{ 3743 struct usb_endpoint *ep, *ep_end; 3744 usb_error_t usb_err; 3745 uint32_t reg; 3746 int hashq, hasnq, haslq, nqueues, ntx; 3747 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 3748 3749 /* Initialize LLT table. */ 3750 error = urtwn_llt_init(sc); 3751 if (error != 0) 3752 return (error); 3753 3754 /* Determine the number of bulk-out pipes. */ 3755 ntx = 0; 3756 ep = sc->sc_udev->endpoints; 3757 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 3758 for (; ep != ep_end; ep++) { 3759 if ((ep->edesc == NULL) || 3760 (ep->iface_index != sc->sc_iface_index)) 3761 continue; 3762 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 3763 ntx++; 3764 } 3765 if (ntx == 0) { 3766 device_printf(sc->sc_dev, 3767 "%d: invalid number of Tx bulk pipes\n", ntx); 3768 return (EIO); 3769 } 3770 3771 /* Get Tx queues to USB endpoints mapping. */ 3772 hashq = hasnq = haslq = nqueues = 0; 3773 switch (ntx) { 3774 case 1: hashq = 1; break; 3775 case 2: hashq = hasnq = 1; break; 3776 case 3: case 4: hashq = hasnq = haslq = 1; break; 3777 } 3778 nqueues = hashq + hasnq + haslq; 3779 if (nqueues == 0) 3780 return (EIO); 3781 3782 npubqpages = nqpages = nrempages = pagecount = 0; 3783 if (sc->chip & URTWN_CHIP_88E) 3784 tx_boundary = R88E_TX_PAGE_BOUNDARY; 3785 else { 3786 pagecount = R92C_TX_PAGE_COUNT; 3787 npubqpages = R92C_PUBQ_NPAGES; 3788 tx_boundary = R92C_TX_PAGE_BOUNDARY; 3789 } 3790 3791 /* Set number of pages for normal priority queue. */ 3792 if (sc->chip & URTWN_CHIP_88E) { 3793 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 3794 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3795 return (EIO); 3796 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3797 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3798 return (EIO); 3799 } else { 3800 /* Get the number of pages for each queue. */ 3801 nqpages = (pagecount - npubqpages) / nqueues; 3802 /* 3803 * The remaining pages are assigned to the high priority 3804 * queue. 3805 */ 3806 nrempages = (pagecount - npubqpages) % nqueues; 3807 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3808 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3809 return (EIO); 3810 usb_err = urtwn_write_4(sc, R92C_RQPN, 3811 /* Set number of pages for public queue. */ 3812 SM(R92C_RQPN_PUBQ, npubqpages) | 3813 /* Set number of pages for high priority queue. */ 3814 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3815 /* Set number of pages for low priority queue. */ 3816 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3817 /* Load values. */ 3818 R92C_RQPN_LD); 3819 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3820 return (EIO); 3821 } 3822 3823 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 3824 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3825 return (EIO); 3826 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 3827 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3828 return (EIO); 3829 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 3830 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3831 return (EIO); 3832 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 3833 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3834 return (EIO); 3835 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 3836 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3837 return (EIO); 3838 3839 /* Set queue to USB pipe mapping. */ 3840 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3841 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3842 if (nqueues == 1) { 3843 if (hashq) 3844 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3845 else if (hasnq) 3846 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3847 else 3848 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3849 } else if (nqueues == 2) { 3850 /* 3851 * All 2-endpoints configs have high and normal 3852 * priority queues. 3853 */ 3854 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3855 } else 3856 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3857 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3858 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3859 return (EIO); 3860 3861 /* Set Tx/Rx transfer page boundary. */ 3862 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 3863 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 3864 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3865 return (EIO); 3866 3867 /* Set Tx/Rx transfer page size. */ 3868 usb_err = urtwn_write_1(sc, R92C_PBP, 3869 SM(R92C_PBP_PSRX, R92C_PBP_128) | 3870 SM(R92C_PBP_PSTX, R92C_PBP_128)); 3871 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3872 return (EIO); 3873 3874 return (0); 3875} 3876 3877static int 3878urtwn_mac_init(struct urtwn_softc *sc) 3879{ 3880 usb_error_t error; 3881 int i; 3882 3883 /* Write MAC initialization values. */ 3884 if (sc->chip & URTWN_CHIP_88E) { 3885 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 3886 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3887 rtl8188eu_mac[i].val); 3888 if (error != USB_ERR_NORMAL_COMPLETION) 3889 return (EIO); 3890 } 3891 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 3892 } else { 3893 for (i = 0; i < nitems(rtl8192cu_mac); i++) 3894 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3895 rtl8192cu_mac[i].val); 3896 if (error != USB_ERR_NORMAL_COMPLETION) 3897 return (EIO); 3898 } 3899 3900 return (0); 3901} 3902 3903static void 3904urtwn_bb_init(struct urtwn_softc *sc) 3905{ 3906 const struct urtwn_bb_prog *prog; 3907 uint32_t reg; 3908 uint8_t crystalcap; 3909 int i; 3910 3911 /* Enable BB and RF. */ 3912 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3913 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3914 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3915 R92C_SYS_FUNC_EN_DIO_RF); 3916 3917 if (!(sc->chip & URTWN_CHIP_88E)) 3918 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 3919 3920 urtwn_write_1(sc, R92C_RF_CTRL, 3921 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3922 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3923 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3924 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3925 3926 if (!(sc->chip & URTWN_CHIP_88E)) { 3927 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3928 urtwn_write_1(sc, 0x15, 0xe9); 3929 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3930 } 3931 3932 /* Select BB programming based on board type. */ 3933 if (sc->chip & URTWN_CHIP_88E) 3934 prog = &rtl8188eu_bb_prog; 3935 else if (!(sc->chip & URTWN_CHIP_92C)) { 3936 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3937 prog = &rtl8188ce_bb_prog; 3938 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3939 prog = &rtl8188ru_bb_prog; 3940 else 3941 prog = &rtl8188cu_bb_prog; 3942 } else { 3943 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3944 prog = &rtl8192ce_bb_prog; 3945 else 3946 prog = &rtl8192cu_bb_prog; 3947 } 3948 /* Write BB initialization values. */ 3949 for (i = 0; i < prog->count; i++) { 3950 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3951 urtwn_ms_delay(sc); 3952 } 3953 3954 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3955 /* 8192C 1T only configuration. */ 3956 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3957 reg = (reg & ~0x00000003) | 0x2; 3958 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3959 3960 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3961 reg = (reg & ~0x00300033) | 0x00200022; 3962 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3963 3964 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3965 reg = (reg & ~0xff000000) | 0x45 << 24; 3966 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3967 3968 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3969 reg = (reg & ~0x000000ff) | 0x23; 3970 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3971 3972 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3973 reg = (reg & ~0x00000030) | 1 << 4; 3974 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3975 3976 reg = urtwn_bb_read(sc, 0xe74); 3977 reg = (reg & ~0x0c000000) | 2 << 26; 3978 urtwn_bb_write(sc, 0xe74, reg); 3979 reg = urtwn_bb_read(sc, 0xe78); 3980 reg = (reg & ~0x0c000000) | 2 << 26; 3981 urtwn_bb_write(sc, 0xe78, reg); 3982 reg = urtwn_bb_read(sc, 0xe7c); 3983 reg = (reg & ~0x0c000000) | 2 << 26; 3984 urtwn_bb_write(sc, 0xe7c, reg); 3985 reg = urtwn_bb_read(sc, 0xe80); 3986 reg = (reg & ~0x0c000000) | 2 << 26; 3987 urtwn_bb_write(sc, 0xe80, reg); 3988 reg = urtwn_bb_read(sc, 0xe88); 3989 reg = (reg & ~0x0c000000) | 2 << 26; 3990 urtwn_bb_write(sc, 0xe88, reg); 3991 } 3992 3993 /* Write AGC values. */ 3994 for (i = 0; i < prog->agccount; i++) { 3995 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 3996 prog->agcvals[i]); 3997 urtwn_ms_delay(sc); 3998 } 3999 4000 if (sc->chip & URTWN_CHIP_88E) { 4001 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 4002 urtwn_ms_delay(sc); 4003 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 4004 urtwn_ms_delay(sc); 4005 4006 crystalcap = sc->rom.r88e_rom.crystalcap; 4007 if (crystalcap == 0xff) 4008 crystalcap = 0x20; 4009 crystalcap &= 0x3f; 4010 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 4011 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 4012 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 4013 crystalcap | crystalcap << 6)); 4014 } else { 4015 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 4016 R92C_HSSI_PARAM2_CCK_HIPWR) 4017 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 4018 } 4019} 4020 4021static void 4022urtwn_rf_init(struct urtwn_softc *sc) 4023{ 4024 const struct urtwn_rf_prog *prog; 4025 uint32_t reg, type; 4026 int i, j, idx, off; 4027 4028 /* Select RF programming based on board type. */ 4029 if (sc->chip & URTWN_CHIP_88E) 4030 prog = rtl8188eu_rf_prog; 4031 else if (!(sc->chip & URTWN_CHIP_92C)) { 4032 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 4033 prog = rtl8188ce_rf_prog; 4034 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4035 prog = rtl8188ru_rf_prog; 4036 else 4037 prog = rtl8188cu_rf_prog; 4038 } else 4039 prog = rtl8192ce_rf_prog; 4040 4041 for (i = 0; i < sc->nrxchains; i++) { 4042 /* Save RF_ENV control type. */ 4043 idx = i / 2; 4044 off = (i % 2) * 16; 4045 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4046 type = (reg >> off) & 0x10; 4047 4048 /* Set RF_ENV enable. */ 4049 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4050 reg |= 0x100000; 4051 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4052 urtwn_ms_delay(sc); 4053 /* Set RF_ENV output high. */ 4054 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4055 reg |= 0x10; 4056 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4057 urtwn_ms_delay(sc); 4058 /* Set address and data lengths of RF registers. */ 4059 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4060 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4061 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4062 urtwn_ms_delay(sc); 4063 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4064 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4065 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4066 urtwn_ms_delay(sc); 4067 4068 /* Write RF initialization values for this chain. */ 4069 for (j = 0; j < prog[i].count; j++) { 4070 if (prog[i].regs[j] >= 0xf9 && 4071 prog[i].regs[j] <= 0xfe) { 4072 /* 4073 * These are fake RF registers offsets that 4074 * indicate a delay is required. 4075 */ 4076 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 4077 continue; 4078 } 4079 urtwn_rf_write(sc, i, prog[i].regs[j], 4080 prog[i].vals[j]); 4081 urtwn_ms_delay(sc); 4082 } 4083 4084 /* Restore RF_ENV control type. */ 4085 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 4086 reg &= ~(0x10 << off) | (type << off); 4087 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 4088 4089 /* Cache RF register CHNLBW. */ 4090 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4091 } 4092 4093 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4094 URTWN_CHIP_UMC_A_CUT) { 4095 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4096 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4097 } 4098} 4099 4100static void 4101urtwn_cam_init(struct urtwn_softc *sc) 4102{ 4103 /* Invalidate all CAM entries. */ 4104 urtwn_write_4(sc, R92C_CAMCMD, 4105 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4106} 4107 4108static int 4109urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 4110{ 4111 usb_error_t error; 4112 4113 error = urtwn_write_4(sc, R92C_CAMWRITE, data); 4114 if (error != USB_ERR_NORMAL_COMPLETION) 4115 return (EIO); 4116 error = urtwn_write_4(sc, R92C_CAMCMD, 4117 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 4118 SM(R92C_CAMCMD_ADDR, addr)); 4119 if (error != USB_ERR_NORMAL_COMPLETION) 4120 return (EIO); 4121 4122 return (0); 4123} 4124 4125static void 4126urtwn_pa_bias_init(struct urtwn_softc *sc) 4127{ 4128 uint8_t reg; 4129 int i; 4130 4131 for (i = 0; i < sc->nrxchains; i++) { 4132 if (sc->pa_setting & (1 << i)) 4133 continue; 4134 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4135 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4136 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4137 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4138 } 4139 if (!(sc->pa_setting & 0x10)) { 4140 reg = urtwn_read_1(sc, 0x16); 4141 reg = (reg & ~0xf0) | 0x90; 4142 urtwn_write_1(sc, 0x16, reg); 4143 } 4144} 4145 4146static void 4147urtwn_rxfilter_init(struct urtwn_softc *sc) 4148{ 4149 struct ieee80211com *ic = &sc->sc_ic; 4150 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4151 uint32_t rcr; 4152 uint16_t filter; 4153 4154 URTWN_ASSERT_LOCKED(sc); 4155 4156 /* Accept all multicast frames. */ 4157 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4158 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4159 4160 /* Filter for management frames. */ 4161 filter = 0x7f3f; 4162 switch (vap->iv_opmode) { 4163 case IEEE80211_M_STA: 4164 filter &= ~( 4165 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 4166 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 4167 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 4168 break; 4169 case IEEE80211_M_HOSTAP: 4170 filter &= ~( 4171 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 4172 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP) | 4173 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_BEACON)); 4174 break; 4175 case IEEE80211_M_MONITOR: 4176 case IEEE80211_M_IBSS: 4177 break; 4178 default: 4179 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4180 __func__, vap->iv_opmode); 4181 break; 4182 } 4183 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 4184 4185 /* Reject all control frames. */ 4186 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4187 4188 /* Reject all data frames. */ 4189 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 4190 4191 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 4192 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 4193 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 4194 4195 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 4196 /* Accept all frames. */ 4197 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 4198 R92C_RCR_AAP; 4199 } 4200 4201 /* Set Rx filter. */ 4202 urtwn_write_4(sc, R92C_RCR, rcr); 4203 4204 if (ic->ic_promisc != 0) { 4205 /* Update Rx filter. */ 4206 urtwn_set_promisc(sc); 4207 } 4208} 4209 4210static void 4211urtwn_edca_init(struct urtwn_softc *sc) 4212{ 4213 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4214 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4215 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4216 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4217 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4218 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4219 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4220 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4221} 4222 4223static void 4224urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4225 uint16_t power[URTWN_RIDX_COUNT]) 4226{ 4227 uint32_t reg; 4228 4229 /* Write per-CCK rate Tx power. */ 4230 if (chain == 0) { 4231 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4232 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4233 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4234 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4235 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4236 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4237 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4238 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4239 } else { 4240 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4241 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4242 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4243 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4244 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4245 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4246 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4247 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4248 } 4249 /* Write per-OFDM rate Tx power. */ 4250 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4251 SM(R92C_TXAGC_RATE06, power[ 4]) | 4252 SM(R92C_TXAGC_RATE09, power[ 5]) | 4253 SM(R92C_TXAGC_RATE12, power[ 6]) | 4254 SM(R92C_TXAGC_RATE18, power[ 7])); 4255 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4256 SM(R92C_TXAGC_RATE24, power[ 8]) | 4257 SM(R92C_TXAGC_RATE36, power[ 9]) | 4258 SM(R92C_TXAGC_RATE48, power[10]) | 4259 SM(R92C_TXAGC_RATE54, power[11])); 4260 /* Write per-MCS Tx power. */ 4261 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4262 SM(R92C_TXAGC_MCS00, power[12]) | 4263 SM(R92C_TXAGC_MCS01, power[13]) | 4264 SM(R92C_TXAGC_MCS02, power[14]) | 4265 SM(R92C_TXAGC_MCS03, power[15])); 4266 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4267 SM(R92C_TXAGC_MCS04, power[16]) | 4268 SM(R92C_TXAGC_MCS05, power[17]) | 4269 SM(R92C_TXAGC_MCS06, power[18]) | 4270 SM(R92C_TXAGC_MCS07, power[19])); 4271 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4272 SM(R92C_TXAGC_MCS08, power[20]) | 4273 SM(R92C_TXAGC_MCS09, power[21]) | 4274 SM(R92C_TXAGC_MCS10, power[22]) | 4275 SM(R92C_TXAGC_MCS11, power[23])); 4276 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4277 SM(R92C_TXAGC_MCS12, power[24]) | 4278 SM(R92C_TXAGC_MCS13, power[25]) | 4279 SM(R92C_TXAGC_MCS14, power[26]) | 4280 SM(R92C_TXAGC_MCS15, power[27])); 4281} 4282 4283static void 4284urtwn_get_txpower(struct urtwn_softc *sc, int chain, 4285 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4286 uint16_t power[URTWN_RIDX_COUNT]) 4287{ 4288 struct ieee80211com *ic = &sc->sc_ic; 4289 struct r92c_rom *rom = &sc->rom.r92c_rom; 4290 uint16_t cckpow, ofdmpow, htpow, diff, max; 4291 const struct urtwn_txpwr *base; 4292 int ridx, chan, group; 4293 4294 /* Determine channel group. */ 4295 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4296 if (chan <= 3) 4297 group = 0; 4298 else if (chan <= 9) 4299 group = 1; 4300 else 4301 group = 2; 4302 4303 /* Get original Tx power based on board type and RF chain. */ 4304 if (!(sc->chip & URTWN_CHIP_92C)) { 4305 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4306 base = &rtl8188ru_txagc[chain]; 4307 else 4308 base = &rtl8192cu_txagc[chain]; 4309 } else 4310 base = &rtl8192cu_txagc[chain]; 4311 4312 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4313 if (sc->regulatory == 0) { 4314 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4315 power[ridx] = base->pwr[0][ridx]; 4316 } 4317 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4318 if (sc->regulatory == 3) { 4319 power[ridx] = base->pwr[0][ridx]; 4320 /* Apply vendor limits. */ 4321 if (extc != NULL) 4322 max = rom->ht40_max_pwr[group]; 4323 else 4324 max = rom->ht20_max_pwr[group]; 4325 max = (max >> (chain * 4)) & 0xf; 4326 if (power[ridx] > max) 4327 power[ridx] = max; 4328 } else if (sc->regulatory == 1) { 4329 if (extc == NULL) 4330 power[ridx] = base->pwr[group][ridx]; 4331 } else if (sc->regulatory != 2) 4332 power[ridx] = base->pwr[0][ridx]; 4333 } 4334 4335 /* Compute per-CCK rate Tx power. */ 4336 cckpow = rom->cck_tx_pwr[chain][group]; 4337 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4338 power[ridx] += cckpow; 4339 if (power[ridx] > R92C_MAX_TX_PWR) 4340 power[ridx] = R92C_MAX_TX_PWR; 4341 } 4342 4343 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4344 if (sc->ntxchains > 1) { 4345 /* Apply reduction for 2 spatial streams. */ 4346 diff = rom->ht40_2s_tx_pwr_diff[group]; 4347 diff = (diff >> (chain * 4)) & 0xf; 4348 htpow = (htpow > diff) ? htpow - diff : 0; 4349 } 4350 4351 /* Compute per-OFDM rate Tx power. */ 4352 diff = rom->ofdm_tx_pwr_diff[group]; 4353 diff = (diff >> (chain * 4)) & 0xf; 4354 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4355 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4356 power[ridx] += ofdmpow; 4357 if (power[ridx] > R92C_MAX_TX_PWR) 4358 power[ridx] = R92C_MAX_TX_PWR; 4359 } 4360 4361 /* Compute per-MCS Tx power. */ 4362 if (extc == NULL) { 4363 diff = rom->ht20_tx_pwr_diff[group]; 4364 diff = (diff >> (chain * 4)) & 0xf; 4365 htpow += diff; /* HT40->HT20 correction. */ 4366 } 4367 for (ridx = 12; ridx <= 27; ridx++) { 4368 power[ridx] += htpow; 4369 if (power[ridx] > R92C_MAX_TX_PWR) 4370 power[ridx] = R92C_MAX_TX_PWR; 4371 } 4372#ifdef USB_DEBUG 4373 if (sc->sc_debug & URTWN_DEBUG_TXPWR) { 4374 /* Dump per-rate Tx power values. */ 4375 printf("Tx power for chain %d:\n", chain); 4376 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 4377 printf("Rate %d = %u\n", ridx, power[ridx]); 4378 } 4379#endif 4380} 4381 4382static void 4383urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 4384 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4385 uint16_t power[URTWN_RIDX_COUNT]) 4386{ 4387 struct ieee80211com *ic = &sc->sc_ic; 4388 struct r88e_rom *rom = &sc->rom.r88e_rom; 4389 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4390 const struct urtwn_r88e_txpwr *base; 4391 int ridx, chan, group; 4392 4393 /* Determine channel group. */ 4394 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4395 if (chan <= 2) 4396 group = 0; 4397 else if (chan <= 5) 4398 group = 1; 4399 else if (chan <= 8) 4400 group = 2; 4401 else if (chan <= 11) 4402 group = 3; 4403 else if (chan <= 13) 4404 group = 4; 4405 else 4406 group = 5; 4407 4408 /* Get original Tx power based on board type and RF chain. */ 4409 base = &rtl8188eu_txagc[chain]; 4410 4411 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4412 if (sc->regulatory == 0) { 4413 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4414 power[ridx] = base->pwr[0][ridx]; 4415 } 4416 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4417 if (sc->regulatory == 3) 4418 power[ridx] = base->pwr[0][ridx]; 4419 else if (sc->regulatory == 1) { 4420 if (extc == NULL) 4421 power[ridx] = base->pwr[group][ridx]; 4422 } else if (sc->regulatory != 2) 4423 power[ridx] = base->pwr[0][ridx]; 4424 } 4425 4426 /* Compute per-CCK rate Tx power. */ 4427 cckpow = rom->cck_tx_pwr[group]; 4428 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4429 power[ridx] += cckpow; 4430 if (power[ridx] > R92C_MAX_TX_PWR) 4431 power[ridx] = R92C_MAX_TX_PWR; 4432 } 4433 4434 htpow = rom->ht40_tx_pwr[group]; 4435 4436 /* Compute per-OFDM rate Tx power. */ 4437 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4438 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4439 power[ridx] += ofdmpow; 4440 if (power[ridx] > R92C_MAX_TX_PWR) 4441 power[ridx] = R92C_MAX_TX_PWR; 4442 } 4443 4444 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4445 for (ridx = 12; ridx <= 27; ridx++) { 4446 power[ridx] += bw20pow; 4447 if (power[ridx] > R92C_MAX_TX_PWR) 4448 power[ridx] = R92C_MAX_TX_PWR; 4449 } 4450} 4451 4452static void 4453urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 4454 struct ieee80211_channel *extc) 4455{ 4456 uint16_t power[URTWN_RIDX_COUNT]; 4457 int i; 4458 4459 for (i = 0; i < sc->ntxchains; i++) { 4460 /* Compute per-rate Tx power values. */ 4461 if (sc->chip & URTWN_CHIP_88E) 4462 urtwn_r88e_get_txpower(sc, i, c, extc, power); 4463 else 4464 urtwn_get_txpower(sc, i, c, extc, power); 4465 /* Write per-rate Tx power values to hardware. */ 4466 urtwn_write_txpower(sc, i, power); 4467 } 4468} 4469 4470static void 4471urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 4472{ 4473 uint32_t reg; 4474 4475 reg = urtwn_read_4(sc, R92C_RCR); 4476 if (enable) 4477 reg &= ~R92C_RCR_CBSSID_BCN; 4478 else 4479 reg |= R92C_RCR_CBSSID_BCN; 4480 urtwn_write_4(sc, R92C_RCR, reg); 4481} 4482 4483static void 4484urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 4485{ 4486 uint32_t reg; 4487 4488 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 4489 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4490 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 4491 4492 if (!(sc->chip & URTWN_CHIP_88E)) { 4493 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 4494 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4495 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 4496 } 4497} 4498 4499static void 4500urtwn_scan_start(struct ieee80211com *ic) 4501{ 4502 struct urtwn_softc *sc = ic->ic_softc; 4503 4504 URTWN_LOCK(sc); 4505 /* Receive beacons / probe responses from any BSSID. */ 4506 if (ic->ic_opmode != IEEE80211_M_IBSS) 4507 urtwn_set_rx_bssid_all(sc, 1); 4508 4509 /* Set gain for scanning. */ 4510 urtwn_set_gain(sc, 0x20); 4511 URTWN_UNLOCK(sc); 4512} 4513 4514static void 4515urtwn_scan_end(struct ieee80211com *ic) 4516{ 4517 struct urtwn_softc *sc = ic->ic_softc; 4518 4519 URTWN_LOCK(sc); 4520 /* Restore limitations. */ 4521 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 4522 urtwn_set_rx_bssid_all(sc, 0); 4523 4524 /* Set gain under link. */ 4525 urtwn_set_gain(sc, 0x32); 4526 URTWN_UNLOCK(sc); 4527} 4528 4529static void 4530urtwn_set_channel(struct ieee80211com *ic) 4531{ 4532 struct urtwn_softc *sc = ic->ic_softc; 4533 struct ieee80211_channel *c = ic->ic_curchan; 4534 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4535 4536 URTWN_LOCK(sc); 4537 if (vap->iv_state == IEEE80211_S_SCAN) { 4538 /* Make link LED blink during scan. */ 4539 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 4540 } 4541 urtwn_set_chan(sc, c, NULL); 4542 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 4543 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 4544 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 4545 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 4546 URTWN_UNLOCK(sc); 4547} 4548 4549static int 4550urtwn_wme_update(struct ieee80211com *ic) 4551{ 4552 const struct wmeParams *wmep = 4553 ic->ic_wme.wme_chanParams.cap_wmeParams; 4554 struct urtwn_softc *sc = ic->ic_softc; 4555 uint8_t aifs, acm, slottime; 4556 int ac; 4557 4558 acm = 0; 4559 slottime = IEEE80211_GET_SLOTTIME(ic); 4560 4561 URTWN_LOCK(sc); 4562 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4563 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4564 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4565 urtwn_write_4(sc, wme2queue[ac].reg, 4566 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 4567 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 4568 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 4569 SM(R92C_EDCA_PARAM_AIFS, aifs)); 4570 if (ac != WME_AC_BE) 4571 acm |= wmep[ac].wmep_acm << ac; 4572 } 4573 4574 if (acm != 0) 4575 acm |= R92C_ACMHWCTRL_EN; 4576 urtwn_write_1(sc, R92C_ACMHWCTRL, 4577 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 4578 acm); 4579 4580 URTWN_UNLOCK(sc); 4581 4582 return 0; 4583} 4584 4585static void 4586urtwn_update_slot(struct ieee80211com *ic) 4587{ 4588 urtwn_cmd_sleepable(ic->ic_softc, NULL, 0, urtwn_update_slot_cb); 4589} 4590 4591static void 4592urtwn_update_slot_cb(struct urtwn_softc *sc, union sec_param *data) 4593{ 4594 struct ieee80211com *ic = &sc->sc_ic; 4595 uint8_t slottime; 4596 4597 slottime = IEEE80211_GET_SLOTTIME(ic); 4598 4599 URTWN_DPRINTF(sc, URTWN_DEBUG_ANY, "%s: setting slot time to %uus\n", 4600 __func__, slottime); 4601 4602 urtwn_write_1(sc, R92C_SLOT, slottime); 4603 urtwn_update_aifs(sc, slottime); 4604} 4605 4606static void 4607urtwn_update_aifs(struct urtwn_softc *sc, uint8_t slottime) 4608{ 4609 const struct wmeParams *wmep = 4610 sc->sc_ic.ic_wme.wme_chanParams.cap_wmeParams; 4611 uint8_t aifs, ac; 4612 4613 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4614 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4615 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4616 urtwn_write_1(sc, wme2queue[ac].reg, aifs); 4617 } 4618} 4619 4620static void 4621urtwn_set_promisc(struct urtwn_softc *sc) 4622{ 4623 struct ieee80211com *ic = &sc->sc_ic; 4624 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4625 uint32_t rcr, mask1, mask2; 4626 4627 URTWN_ASSERT_LOCKED(sc); 4628 4629 if (vap->iv_opmode == IEEE80211_M_MONITOR) 4630 return; 4631 4632 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 4633 mask2 = R92C_RCR_APM; 4634 4635 if (vap->iv_state == IEEE80211_S_RUN) { 4636 switch (vap->iv_opmode) { 4637 case IEEE80211_M_STA: 4638 mask2 |= R92C_RCR_CBSSID_DATA; 4639 /* FALLTHROUGH */ 4640 case IEEE80211_M_HOSTAP: 4641 mask2 |= R92C_RCR_CBSSID_BCN; 4642 break; 4643 case IEEE80211_M_IBSS: 4644 mask2 |= R92C_RCR_CBSSID_DATA; 4645 break; 4646 default: 4647 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4648 __func__, vap->iv_opmode); 4649 return; 4650 } 4651 } 4652 4653 rcr = urtwn_read_4(sc, R92C_RCR); 4654 if (ic->ic_promisc == 0) 4655 rcr = (rcr & ~mask1) | mask2; 4656 else 4657 rcr = (rcr & ~mask2) | mask1; 4658 urtwn_write_4(sc, R92C_RCR, rcr); 4659} 4660 4661static void 4662urtwn_update_promisc(struct ieee80211com *ic) 4663{ 4664 struct urtwn_softc *sc = ic->ic_softc; 4665 4666 URTWN_LOCK(sc); 4667 if (sc->sc_flags & URTWN_RUNNING) 4668 urtwn_set_promisc(sc); 4669 URTWN_UNLOCK(sc); 4670} 4671 4672static void 4673urtwn_update_mcast(struct ieee80211com *ic) 4674{ 4675 /* XXX do nothing? */ 4676} 4677 4678static struct ieee80211_node * 4679urtwn_r88e_node_alloc(struct ieee80211vap *vap, 4680 const uint8_t mac[IEEE80211_ADDR_LEN]) 4681{ 4682 struct urtwn_node *un; 4683 4684 un = malloc(sizeof (struct urtwn_node), M_80211_NODE, 4685 M_NOWAIT | M_ZERO); 4686 4687 if (un == NULL) 4688 return NULL; 4689 4690 un->id = URTWN_MACID_UNDEFINED; 4691 4692 return &un->ni; 4693} 4694 4695static void 4696urtwn_r88e_newassoc(struct ieee80211_node *ni, int isnew) 4697{ 4698 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4699 struct urtwn_node *un = URTWN_NODE(ni); 4700 uint8_t id; 4701 4702 if (!isnew) 4703 return; 4704 4705 URTWN_NT_LOCK(sc); 4706 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 4707 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 4708 un->id = id; 4709 sc->node_list[id] = ni; 4710 break; 4711 } 4712 } 4713 URTWN_NT_UNLOCK(sc); 4714 4715 if (id > URTWN_MACID_MAX(sc)) { 4716 device_printf(sc->sc_dev, "%s: node table is full\n", 4717 __func__); 4718 } 4719} 4720 4721static void 4722urtwn_r88e_node_free(struct ieee80211_node *ni) 4723{ 4724 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4725 struct urtwn_node *un = URTWN_NODE(ni); 4726 4727 URTWN_NT_LOCK(sc); 4728 if (un->id != URTWN_MACID_UNDEFINED) 4729 sc->node_list[un->id] = NULL; 4730 URTWN_NT_UNLOCK(sc); 4731 4732 sc->sc_node_free(ni); 4733} 4734 4735static void 4736urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 4737 struct ieee80211_channel *extc) 4738{ 4739 struct ieee80211com *ic = &sc->sc_ic; 4740 uint32_t reg; 4741 u_int chan; 4742 int i; 4743 4744 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4745 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 4746 device_printf(sc->sc_dev, 4747 "%s: invalid channel %x\n", __func__, chan); 4748 return; 4749 } 4750 4751 /* Set Tx power for this new channel. */ 4752 urtwn_set_txpower(sc, c, extc); 4753 4754 for (i = 0; i < sc->nrxchains; i++) { 4755 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4756 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4757 } 4758#ifndef IEEE80211_NO_HT 4759 if (extc != NULL) { 4760 /* Is secondary channel below or above primary? */ 4761 int prichlo = c->ic_freq < extc->ic_freq; 4762 4763 urtwn_write_1(sc, R92C_BWOPMODE, 4764 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4765 4766 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4767 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4768 urtwn_write_1(sc, R92C_RRSR + 2, reg); 4769 4770 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4771 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4772 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4773 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4774 4775 /* Set CCK side band. */ 4776 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4777 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4778 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4779 4780 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4781 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4782 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4783 4784 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4785 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4786 ~R92C_FPGA0_ANAPARAM2_CBW20); 4787 4788 reg = urtwn_bb_read(sc, 0x818); 4789 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4790 urtwn_bb_write(sc, 0x818, reg); 4791 4792 /* Select 40MHz bandwidth. */ 4793 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4794 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4795 } else 4796#endif 4797 { 4798 urtwn_write_1(sc, R92C_BWOPMODE, 4799 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4800 4801 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4802 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4803 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4804 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4805 4806 if (!(sc->chip & URTWN_CHIP_88E)) { 4807 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4808 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4809 R92C_FPGA0_ANAPARAM2_CBW20); 4810 } 4811 4812 /* Select 20MHz bandwidth. */ 4813 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4814 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4815 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 4816 R92C_RF_CHNLBW_BW20)); 4817 } 4818} 4819 4820static void 4821urtwn_iq_calib(struct urtwn_softc *sc) 4822{ 4823 /* TODO */ 4824} 4825 4826static void 4827urtwn_lc_calib(struct urtwn_softc *sc) 4828{ 4829 uint32_t rf_ac[2]; 4830 uint8_t txmode; 4831 int i; 4832 4833 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4834 if ((txmode & 0x70) != 0) { 4835 /* Disable all continuous Tx. */ 4836 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4837 4838 /* Set RF mode to standby mode. */ 4839 for (i = 0; i < sc->nrxchains; i++) { 4840 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4841 urtwn_rf_write(sc, i, R92C_RF_AC, 4842 RW(rf_ac[i], R92C_RF_AC_MODE, 4843 R92C_RF_AC_MODE_STANDBY)); 4844 } 4845 } else { 4846 /* Block all Tx queues. */ 4847 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 4848 } 4849 /* Start calibration. */ 4850 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4851 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4852 4853 /* Give calibration the time to complete. */ 4854 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 4855 4856 /* Restore configuration. */ 4857 if ((txmode & 0x70) != 0) { 4858 /* Restore Tx mode. */ 4859 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4860 /* Restore RF mode. */ 4861 for (i = 0; i < sc->nrxchains; i++) 4862 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4863 } else { 4864 /* Unblock all Tx queues. */ 4865 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4866 } 4867} 4868 4869static void 4870urtwn_temp_calib(struct urtwn_softc *sc) 4871{ 4872 uint8_t temp; 4873 4874 URTWN_ASSERT_LOCKED(sc); 4875 4876 if (!(sc->sc_flags & URTWN_TEMP_MEASURED)) { 4877 /* Start measuring temperature. */ 4878 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 4879 "%s: start measuring temperature\n", __func__); 4880 if (sc->chip & URTWN_CHIP_88E) { 4881 urtwn_rf_write(sc, 0, R88E_RF_T_METER, 4882 R88E_RF_T_METER_START); 4883 } else { 4884 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 4885 R92C_RF_T_METER_START); 4886 } 4887 sc->sc_flags |= URTWN_TEMP_MEASURED; 4888 return; 4889 } 4890 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 4891 4892 /* Read measured temperature. */ 4893 if (sc->chip & URTWN_CHIP_88E) { 4894 temp = MS(urtwn_rf_read(sc, 0, R88E_RF_T_METER), 4895 R88E_RF_T_METER_VAL); 4896 } else { 4897 temp = MS(urtwn_rf_read(sc, 0, R92C_RF_T_METER), 4898 R92C_RF_T_METER_VAL); 4899 } 4900 if (temp == 0) { /* Read failed, skip. */ 4901 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 4902 "%s: temperature read failed, skipping\n", __func__); 4903 return; 4904 } 4905 4906 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 4907 "%s: temperature: previous %u, current %u\n", 4908 __func__, sc->thcal_lctemp, temp); 4909 4910 /* 4911 * Redo LC calibration if temperature changed significantly since 4912 * last calibration. 4913 */ 4914 if (sc->thcal_lctemp == 0) { 4915 /* First LC calibration is performed in urtwn_init(). */ 4916 sc->thcal_lctemp = temp; 4917 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4918 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 4919 "%s: LC calib triggered by temp: %u -> %u\n", 4920 __func__, sc->thcal_lctemp, temp); 4921 urtwn_lc_calib(sc); 4922 /* Record temperature of last LC calibration. */ 4923 sc->thcal_lctemp = temp; 4924 } 4925} 4926 4927static int 4928urtwn_init(struct urtwn_softc *sc) 4929{ 4930 struct ieee80211com *ic = &sc->sc_ic; 4931 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4932 uint8_t macaddr[IEEE80211_ADDR_LEN]; 4933 uint32_t reg; 4934 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 4935 int error; 4936 4937 URTWN_LOCK(sc); 4938 if (sc->sc_flags & URTWN_RUNNING) { 4939 URTWN_UNLOCK(sc); 4940 return (0); 4941 } 4942 4943 /* Init firmware commands ring. */ 4944 sc->fwcur = 0; 4945 4946 /* Allocate Tx/Rx buffers. */ 4947 error = urtwn_alloc_rx_list(sc); 4948 if (error != 0) 4949 goto fail; 4950 4951 error = urtwn_alloc_tx_list(sc); 4952 if (error != 0) 4953 goto fail; 4954 4955 /* Power on adapter. */ 4956 error = urtwn_power_on(sc); 4957 if (error != 0) 4958 goto fail; 4959 4960 /* Initialize DMA. */ 4961 error = urtwn_dma_init(sc); 4962 if (error != 0) 4963 goto fail; 4964 4965 /* Set info size in Rx descriptors (in 64-bit words). */ 4966 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4967 4968 /* Init interrupts. */ 4969 if (sc->chip & URTWN_CHIP_88E) { 4970 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4971 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4972 goto fail; 4973 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4974 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4975 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4976 goto fail; 4977 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4978 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4979 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4980 goto fail; 4981 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4982 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4983 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4984 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4985 goto fail; 4986 } else { 4987 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4988 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4989 goto fail; 4990 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4991 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4992 goto fail; 4993 } 4994 4995 /* Set MAC address. */ 4996 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 4997 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 4998 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4999 goto fail; 5000 5001 /* Set initial network type. */ 5002 urtwn_set_mode(sc, R92C_MSR_INFRA); 5003 5004 /* Initialize Rx filter. */ 5005 urtwn_rxfilter_init(sc); 5006 5007 /* Set response rate. */ 5008 reg = urtwn_read_4(sc, R92C_RRSR); 5009 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 5010 urtwn_write_4(sc, R92C_RRSR, reg); 5011 5012 /* Set short/long retry limits. */ 5013 urtwn_write_2(sc, R92C_RL, 5014 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 5015 5016 /* Initialize EDCA parameters. */ 5017 urtwn_edca_init(sc); 5018 5019 /* Setup rate fallback. */ 5020 if (!(sc->chip & URTWN_CHIP_88E)) { 5021 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 5022 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 5023 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 5024 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 5025 } 5026 5027 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 5028 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 5029 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 5030 /* Set ACK timeout. */ 5031 urtwn_write_1(sc, R92C_ACKTO, 0x40); 5032 5033 /* Setup USB aggregation. */ 5034 reg = urtwn_read_4(sc, R92C_TDECTRL); 5035 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 5036 urtwn_write_4(sc, R92C_TDECTRL, reg); 5037 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 5038 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 5039 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 5040 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 5041 if (sc->chip & URTWN_CHIP_88E) 5042 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 5043 else { 5044 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 5045 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 5046 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 5047 R92C_USB_SPECIAL_OPTION_AGG_EN); 5048 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 5049 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 5050 } 5051 5052 /* Initialize beacon parameters. */ 5053 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 5054 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 5055 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 5056 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 5057 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 5058 5059 if (!(sc->chip & URTWN_CHIP_88E)) { 5060 /* Setup AMPDU aggregation. */ 5061 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 5062 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 5063 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 5064 5065 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 5066 } 5067 5068#ifndef URTWN_WITHOUT_UCODE 5069 /* Load 8051 microcode. */ 5070 error = urtwn_load_firmware(sc); 5071 if (error == 0) 5072 sc->sc_flags |= URTWN_FW_LOADED; 5073#endif 5074 5075 /* Initialize MAC/BB/RF blocks. */ 5076 error = urtwn_mac_init(sc); 5077 if (error != 0) { 5078 device_printf(sc->sc_dev, 5079 "%s: error while initializing MAC block\n", __func__); 5080 goto fail; 5081 } 5082 urtwn_bb_init(sc); 5083 urtwn_rf_init(sc); 5084 5085 /* Reinitialize Rx filter (D3845 is not committed yet). */ 5086 urtwn_rxfilter_init(sc); 5087 5088 if (sc->chip & URTWN_CHIP_88E) { 5089 urtwn_write_2(sc, R92C_CR, 5090 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 5091 R92C_CR_MACRXEN); 5092 } 5093 5094 /* Turn CCK and OFDM blocks on. */ 5095 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5096 reg |= R92C_RFMOD_CCK_EN; 5097 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5098 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5099 goto fail; 5100 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 5101 reg |= R92C_RFMOD_OFDM_EN; 5102 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 5103 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5104 goto fail; 5105 5106 /* Clear per-station keys table. */ 5107 urtwn_cam_init(sc); 5108 5109 /* Enable decryption / encryption. */ 5110 urtwn_write_2(sc, R92C_SECCFG, 5111 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 5112 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA | 5113 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 5114 5115 /* 5116 * Install static keys (if any). 5117 * Must be called after urtwn_cam_init(). 5118 */ 5119 ieee80211_runtask(ic, &sc->cmdq_task); 5120 5121 /* Enable hardware sequence numbering. */ 5122 urtwn_write_1(sc, R92C_HWSEQ_CTRL, R92C_TX_QUEUE_ALL); 5123 5124 /* Enable per-packet TX report. */ 5125 if (sc->chip & URTWN_CHIP_88E) { 5126 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 5127 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 5128 } 5129 5130 /* Perform LO and IQ calibrations. */ 5131 urtwn_iq_calib(sc); 5132 /* Perform LC calibration. */ 5133 urtwn_lc_calib(sc); 5134 5135 /* Fix USB interference issue. */ 5136 if (!(sc->chip & URTWN_CHIP_88E)) { 5137 urtwn_write_1(sc, 0xfe40, 0xe0); 5138 urtwn_write_1(sc, 0xfe41, 0x8d); 5139 urtwn_write_1(sc, 0xfe42, 0x80); 5140 5141 urtwn_pa_bias_init(sc); 5142 } 5143 5144 /* Initialize GPIO setting. */ 5145 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5146 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5147 5148 /* Fix for lower temperature. */ 5149 if (!(sc->chip & URTWN_CHIP_88E)) 5150 urtwn_write_1(sc, 0x15, 0xe9); 5151 5152 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 5153 5154 sc->sc_flags |= URTWN_RUNNING; 5155 5156 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5157fail: 5158 if (usb_err != USB_ERR_NORMAL_COMPLETION) 5159 error = EIO; 5160 5161 URTWN_UNLOCK(sc); 5162 5163 return (error); 5164} 5165 5166static void 5167urtwn_stop(struct urtwn_softc *sc) 5168{ 5169 5170 URTWN_LOCK(sc); 5171 if (!(sc->sc_flags & URTWN_RUNNING)) { 5172 URTWN_UNLOCK(sc); 5173 return; 5174 } 5175 5176 sc->sc_flags &= ~(URTWN_RUNNING | URTWN_FW_LOADED | 5177 URTWN_TEMP_MEASURED); 5178 sc->thcal_lctemp = 0; 5179 callout_stop(&sc->sc_watchdog_ch); 5180 5181 urtwn_abort_xfers(sc); 5182 urtwn_drain_mbufq(sc); 5183 urtwn_power_off(sc); 5184 URTWN_UNLOCK(sc); 5185} 5186 5187static void 5188urtwn_abort_xfers(struct urtwn_softc *sc) 5189{ 5190 int i; 5191 5192 URTWN_ASSERT_LOCKED(sc); 5193 5194 /* abort any pending transfers */ 5195 for (i = 0; i < URTWN_N_TRANSFER; i++) 5196 usbd_transfer_stop(sc->sc_xfer[i]); 5197} 5198 5199static int 5200urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5201 const struct ieee80211_bpf_params *params) 5202{ 5203 struct ieee80211com *ic = ni->ni_ic; 5204 struct urtwn_softc *sc = ic->ic_softc; 5205 struct urtwn_data *bf; 5206 int error; 5207 5208 /* prevent management frames from being sent if we're not ready */ 5209 URTWN_LOCK(sc); 5210 if (!(sc->sc_flags & URTWN_RUNNING)) { 5211 error = ENETDOWN; 5212 goto end; 5213 } 5214 5215 bf = urtwn_getbuf(sc); 5216 if (bf == NULL) { 5217 error = ENOBUFS; 5218 goto end; 5219 } 5220 5221 if (params == NULL) { 5222 /* 5223 * Legacy path; interpret frame contents to decide 5224 * precisely how to send the frame. 5225 */ 5226 error = urtwn_tx_data(sc, ni, m, bf); 5227 } else { 5228 /* 5229 * Caller supplied explicit parameters to use in 5230 * sending the frame. 5231 */ 5232 error = urtwn_tx_raw(sc, ni, m, bf, params); 5233 } 5234 if (error != 0) { 5235 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 5236 goto end; 5237 } 5238 5239 sc->sc_txtimer = 5; 5240 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 5241 5242end: 5243 if (error != 0) 5244 m_freem(m); 5245 5246 URTWN_UNLOCK(sc); 5247 5248 return (error); 5249} 5250 5251static void 5252urtwn_ms_delay(struct urtwn_softc *sc) 5253{ 5254 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 5255} 5256 5257static device_method_t urtwn_methods[] = { 5258 /* Device interface */ 5259 DEVMETHOD(device_probe, urtwn_match), 5260 DEVMETHOD(device_attach, urtwn_attach), 5261 DEVMETHOD(device_detach, urtwn_detach), 5262 5263 DEVMETHOD_END 5264}; 5265 5266static driver_t urtwn_driver = { 5267 "urtwn", 5268 urtwn_methods, 5269 sizeof(struct urtwn_softc) 5270}; 5271 5272static devclass_t urtwn_devclass; 5273 5274DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 5275MODULE_DEPEND(urtwn, usb, 1, 1, 1); 5276MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 5277#ifndef URTWN_WITHOUT_UCODE 5278MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 5279#endif 5280MODULE_VERSION(urtwn, 1); 5281USB_PNP_HOST_INFO(urtwn_devs); 5282