if_urtwn.c revision 295871
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2015 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#include <sys/cdefs.h> 22__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 295871 2016-02-22 00:48:53Z avos $"); 23 24/* 25 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 26 */ 27 28#include "opt_wlan.h" 29#include "opt_urtwn.h" 30 31#include <sys/param.h> 32#include <sys/sockio.h> 33#include <sys/sysctl.h> 34#include <sys/lock.h> 35#include <sys/mutex.h> 36#include <sys/condvar.h> 37#include <sys/mbuf.h> 38#include <sys/kernel.h> 39#include <sys/socket.h> 40#include <sys/systm.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/bus.h> 44#include <sys/endian.h> 45#include <sys/linker.h> 46#include <sys/firmware.h> 47#include <sys/kdb.h> 48 49#include <machine/bus.h> 50#include <machine/resource.h> 51#include <sys/rman.h> 52 53#include <net/bpf.h> 54#include <net/if.h> 55#include <net/if_var.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61 62#include <netinet/in.h> 63#include <netinet/in_systm.h> 64#include <netinet/in_var.h> 65#include <netinet/if_ether.h> 66#include <netinet/ip.h> 67 68#include <net80211/ieee80211_var.h> 69#include <net80211/ieee80211_input.h> 70#include <net80211/ieee80211_regdomain.h> 71#include <net80211/ieee80211_radiotap.h> 72#include <net80211/ieee80211_ratectl.h> 73 74#include <dev/usb/usb.h> 75#include <dev/usb/usbdi.h> 76#include <dev/usb/usb_device.h> 77#include "usbdevs.h" 78 79#include <dev/usb/usb_debug.h> 80 81#include <dev/usb/wlan/if_urtwnreg.h> 82#include <dev/usb/wlan/if_urtwnvar.h> 83 84#ifdef USB_DEBUG 85enum { 86 URTWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 87 URTWN_DEBUG_RECV = 0x00000002, /* basic recv operation */ 88 URTWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */ 89 URTWN_DEBUG_RA = 0x00000008, /* f/w rate adaptation setup */ 90 URTWN_DEBUG_USB = 0x00000010, /* usb requests */ 91 URTWN_DEBUG_FIRMWARE = 0x00000020, /* firmware(9) loading debug */ 92 URTWN_DEBUG_BEACON = 0x00000040, /* beacon handling */ 93 URTWN_DEBUG_INTR = 0x00000080, /* ISR */ 94 URTWN_DEBUG_TEMP = 0x00000100, /* temperature calibration */ 95 URTWN_DEBUG_ROM = 0x00000200, /* various ROM info */ 96 URTWN_DEBUG_KEY = 0x00000400, /* crypto keys management */ 97 URTWN_DEBUG_TXPWR = 0x00000800, /* dump Tx power values */ 98 URTWN_DEBUG_ANY = 0xffffffff 99}; 100 101#define URTWN_DPRINTF(_sc, _m, ...) do { \ 102 if ((_sc)->sc_debug & (_m)) \ 103 device_printf((_sc)->sc_dev, __VA_ARGS__); \ 104} while(0) 105 106#else 107#define URTWN_DPRINTF(_sc, _m, ...) do { (void) sc; } while (0) 108#endif 109 110#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 111 112/* various supported device vendors/products */ 113static const STRUCT_USB_HOST_ID urtwn_devs[] = { 114#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 115#define URTWN_RTL8188E_DEV(v,p) \ 116 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 117#define URTWN_RTL8188E 1 118 URTWN_DEV(ABOCOM, RTL8188CU_1), 119 URTWN_DEV(ABOCOM, RTL8188CU_2), 120 URTWN_DEV(ABOCOM, RTL8192CU), 121 URTWN_DEV(ASUS, RTL8192CU), 122 URTWN_DEV(ASUS, USBN10NANO), 123 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 124 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 125 URTWN_DEV(AZUREWAVE, RTL8188CU), 126 URTWN_DEV(BELKIN, F7D2102), 127 URTWN_DEV(BELKIN, RTL8188CU), 128 URTWN_DEV(BELKIN, RTL8192CU), 129 URTWN_DEV(CHICONY, RTL8188CUS_1), 130 URTWN_DEV(CHICONY, RTL8188CUS_2), 131 URTWN_DEV(CHICONY, RTL8188CUS_3), 132 URTWN_DEV(CHICONY, RTL8188CUS_4), 133 URTWN_DEV(CHICONY, RTL8188CUS_5), 134 URTWN_DEV(COREGA, RTL8192CU), 135 URTWN_DEV(DLINK, RTL8188CU), 136 URTWN_DEV(DLINK, RTL8192CU_1), 137 URTWN_DEV(DLINK, RTL8192CU_2), 138 URTWN_DEV(DLINK, RTL8192CU_3), 139 URTWN_DEV(DLINK, DWA131B), 140 URTWN_DEV(EDIMAX, EW7811UN), 141 URTWN_DEV(EDIMAX, RTL8192CU), 142 URTWN_DEV(FEIXUN, RTL8188CU), 143 URTWN_DEV(FEIXUN, RTL8192CU), 144 URTWN_DEV(GUILLEMOT, HWNUP150), 145 URTWN_DEV(HAWKING, RTL8192CU), 146 URTWN_DEV(HP3, RTL8188CU), 147 URTWN_DEV(NETGEAR, WNA1000M), 148 URTWN_DEV(NETGEAR, RTL8192CU), 149 URTWN_DEV(NETGEAR4, RTL8188CU), 150 URTWN_DEV(NOVATECH, RTL8188CU), 151 URTWN_DEV(PLANEX2, RTL8188CU_1), 152 URTWN_DEV(PLANEX2, RTL8188CU_2), 153 URTWN_DEV(PLANEX2, RTL8188CU_3), 154 URTWN_DEV(PLANEX2, RTL8188CU_4), 155 URTWN_DEV(PLANEX2, RTL8188CUS), 156 URTWN_DEV(PLANEX2, RTL8192CU), 157 URTWN_DEV(REALTEK, RTL8188CE_0), 158 URTWN_DEV(REALTEK, RTL8188CE_1), 159 URTWN_DEV(REALTEK, RTL8188CTV), 160 URTWN_DEV(REALTEK, RTL8188CU_0), 161 URTWN_DEV(REALTEK, RTL8188CU_1), 162 URTWN_DEV(REALTEK, RTL8188CU_2), 163 URTWN_DEV(REALTEK, RTL8188CU_3), 164 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 165 URTWN_DEV(REALTEK, RTL8188CUS), 166 URTWN_DEV(REALTEK, RTL8188RU_1), 167 URTWN_DEV(REALTEK, RTL8188RU_2), 168 URTWN_DEV(REALTEK, RTL8188RU_3), 169 URTWN_DEV(REALTEK, RTL8191CU), 170 URTWN_DEV(REALTEK, RTL8192CE), 171 URTWN_DEV(REALTEK, RTL8192CU), 172 URTWN_DEV(SITECOMEU, RTL8188CU_1), 173 URTWN_DEV(SITECOMEU, RTL8188CU_2), 174 URTWN_DEV(SITECOMEU, RTL8192CU), 175 URTWN_DEV(TRENDNET, RTL8188CU), 176 URTWN_DEV(TRENDNET, RTL8192CU), 177 URTWN_DEV(ZYXEL, RTL8192CU), 178 /* URTWN_RTL8188E */ 179 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 180 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 181 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 182 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 183 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 184#undef URTWN_RTL8188E_DEV 185#undef URTWN_DEV 186}; 187 188static device_probe_t urtwn_match; 189static device_attach_t urtwn_attach; 190static device_detach_t urtwn_detach; 191 192static usb_callback_t urtwn_bulk_tx_callback; 193static usb_callback_t urtwn_bulk_rx_callback; 194 195static void urtwn_sysctlattach(struct urtwn_softc *); 196static void urtwn_drain_mbufq(struct urtwn_softc *); 197static usb_error_t urtwn_do_request(struct urtwn_softc *, 198 struct usb_device_request *, void *); 199static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 200 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 201 const uint8_t [IEEE80211_ADDR_LEN], 202 const uint8_t [IEEE80211_ADDR_LEN]); 203static void urtwn_vap_delete(struct ieee80211vap *); 204static struct mbuf * urtwn_rx_copy_to_mbuf(struct urtwn_softc *, 205 struct r92c_rx_stat *, int); 206static struct mbuf * urtwn_report_intr(struct usb_xfer *, 207 struct urtwn_data *); 208static struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int); 209static void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 210 void *); 211static struct ieee80211_node *urtwn_rx_frame(struct urtwn_softc *, 212 struct mbuf *, int8_t *); 213static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 214 int); 215static int urtwn_alloc_list(struct urtwn_softc *, 216 struct urtwn_data[], int, int); 217static int urtwn_alloc_rx_list(struct urtwn_softc *); 218static int urtwn_alloc_tx_list(struct urtwn_softc *); 219static void urtwn_free_list(struct urtwn_softc *, 220 struct urtwn_data data[], int); 221static void urtwn_free_rx_list(struct urtwn_softc *); 222static void urtwn_free_tx_list(struct urtwn_softc *); 223static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 224static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 225static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 226 uint8_t *, int); 227static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 228static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 229static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 230static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 231 uint8_t *, int); 232static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 233static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 234static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 235static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 236 const void *, int); 237static void urtwn_cmdq_cb(void *, int); 238static int urtwn_cmd_sleepable(struct urtwn_softc *, const void *, 239 size_t, CMD_FUNC_PROTO); 240static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 241 uint8_t, uint32_t); 242static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 243 uint8_t, uint32_t); 244static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 245static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 246 uint32_t); 247static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 248static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 249 uint8_t, uint8_t); 250#ifdef USB_DEBUG 251static void urtwn_dump_rom_contents(struct urtwn_softc *, 252 uint8_t *, uint16_t); 253#endif 254static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 255 uint16_t); 256static int urtwn_efuse_switch_power(struct urtwn_softc *); 257static int urtwn_read_chipid(struct urtwn_softc *); 258static int urtwn_read_rom(struct urtwn_softc *); 259static int urtwn_r88e_read_rom(struct urtwn_softc *); 260static int urtwn_ra_init(struct urtwn_softc *); 261static void urtwn_init_beacon(struct urtwn_softc *, 262 struct urtwn_vap *); 263static int urtwn_setup_beacon(struct urtwn_softc *, 264 struct ieee80211_node *); 265static void urtwn_update_beacon(struct ieee80211vap *, int); 266static int urtwn_tx_beacon(struct urtwn_softc *sc, 267 struct urtwn_vap *); 268static int urtwn_key_alloc(struct ieee80211vap *, 269 struct ieee80211_key *, ieee80211_keyix *, 270 ieee80211_keyix *); 271static void urtwn_key_set_cb(struct urtwn_softc *, 272 union sec_param *); 273static void urtwn_key_del_cb(struct urtwn_softc *, 274 union sec_param *); 275static int urtwn_key_set(struct ieee80211vap *, 276 const struct ieee80211_key *); 277static int urtwn_key_delete(struct ieee80211vap *, 278 const struct ieee80211_key *); 279static void urtwn_tsf_task_adhoc(void *, int); 280static void urtwn_tsf_sync_enable(struct urtwn_softc *, 281 struct ieee80211vap *); 282static void urtwn_get_tsf(struct urtwn_softc *, uint64_t *); 283static void urtwn_set_led(struct urtwn_softc *, int, int); 284static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 285static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 286 struct mbuf *, int, 287 const struct ieee80211_rx_stats *, int, int); 288static int urtwn_newstate(struct ieee80211vap *, 289 enum ieee80211_state, int); 290static void urtwn_calib_to(void *); 291static void urtwn_calib_cb(struct urtwn_softc *, 292 union sec_param *); 293static void urtwn_watchdog(void *); 294static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 295static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 296static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 297static int urtwn_tx_data(struct urtwn_softc *, 298 struct ieee80211_node *, struct mbuf *, 299 struct urtwn_data *); 300static int urtwn_tx_raw(struct urtwn_softc *, 301 struct ieee80211_node *, struct mbuf *, 302 struct urtwn_data *, 303 const struct ieee80211_bpf_params *); 304static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 305 uint8_t, struct urtwn_data *); 306static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 307static void urtwn_start(struct urtwn_softc *); 308static void urtwn_parent(struct ieee80211com *); 309static int urtwn_r92c_power_on(struct urtwn_softc *); 310static int urtwn_r88e_power_on(struct urtwn_softc *); 311static int urtwn_llt_init(struct urtwn_softc *); 312#ifndef URTWN_WITHOUT_UCODE 313static void urtwn_fw_reset(struct urtwn_softc *); 314static void urtwn_r88e_fw_reset(struct urtwn_softc *); 315static int urtwn_fw_loadpage(struct urtwn_softc *, int, 316 const uint8_t *, int); 317static int urtwn_load_firmware(struct urtwn_softc *); 318#endif 319static int urtwn_dma_init(struct urtwn_softc *); 320static int urtwn_mac_init(struct urtwn_softc *); 321static void urtwn_bb_init(struct urtwn_softc *); 322static void urtwn_rf_init(struct urtwn_softc *); 323static void urtwn_cam_init(struct urtwn_softc *); 324static int urtwn_cam_write(struct urtwn_softc *, uint32_t, 325 uint32_t); 326static void urtwn_pa_bias_init(struct urtwn_softc *); 327static void urtwn_rxfilter_init(struct urtwn_softc *); 328static void urtwn_edca_init(struct urtwn_softc *); 329static void urtwn_write_txpower(struct urtwn_softc *, int, 330 uint16_t[]); 331static void urtwn_get_txpower(struct urtwn_softc *, int, 332 struct ieee80211_channel *, 333 struct ieee80211_channel *, uint16_t[]); 334static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 335 struct ieee80211_channel *, 336 struct ieee80211_channel *, uint16_t[]); 337static void urtwn_set_txpower(struct urtwn_softc *, 338 struct ieee80211_channel *, 339 struct ieee80211_channel *); 340static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 341static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 342static void urtwn_scan_start(struct ieee80211com *); 343static void urtwn_scan_end(struct ieee80211com *); 344static void urtwn_set_channel(struct ieee80211com *); 345static int urtwn_wme_update(struct ieee80211com *); 346static void urtwn_update_slot(struct ieee80211com *); 347static void urtwn_update_slot_cb(struct urtwn_softc *, 348 union sec_param *); 349static void urtwn_update_aifs(struct urtwn_softc *, uint8_t); 350static void urtwn_set_promisc(struct urtwn_softc *); 351static void urtwn_update_promisc(struct ieee80211com *); 352static void urtwn_update_mcast(struct ieee80211com *); 353static struct ieee80211_node *urtwn_r88e_node_alloc(struct ieee80211vap *, 354 const uint8_t mac[IEEE80211_ADDR_LEN]); 355static void urtwn_r88e_newassoc(struct ieee80211_node *, int); 356static void urtwn_r88e_node_free(struct ieee80211_node *); 357static void urtwn_set_chan(struct urtwn_softc *, 358 struct ieee80211_channel *, 359 struct ieee80211_channel *); 360static void urtwn_iq_calib(struct urtwn_softc *); 361static void urtwn_lc_calib(struct urtwn_softc *); 362static void urtwn_temp_calib(struct urtwn_softc *); 363static int urtwn_init(struct urtwn_softc *); 364static void urtwn_stop(struct urtwn_softc *); 365static void urtwn_abort_xfers(struct urtwn_softc *); 366static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 367 const struct ieee80211_bpf_params *); 368static void urtwn_ms_delay(struct urtwn_softc *); 369 370/* Aliases. */ 371#define urtwn_bb_write urtwn_write_4 372#define urtwn_bb_read urtwn_read_4 373 374static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 375 [URTWN_BULK_RX] = { 376 .type = UE_BULK, 377 .endpoint = UE_ADDR_ANY, 378 .direction = UE_DIR_IN, 379 .bufsize = URTWN_RXBUFSZ, 380 .flags = { 381 .pipe_bof = 1, 382 .short_xfer_ok = 1 383 }, 384 .callback = urtwn_bulk_rx_callback, 385 }, 386 [URTWN_BULK_TX_BE] = { 387 .type = UE_BULK, 388 .endpoint = 0x03, 389 .direction = UE_DIR_OUT, 390 .bufsize = URTWN_TXBUFSZ, 391 .flags = { 392 .ext_buffer = 1, 393 .pipe_bof = 1, 394 .force_short_xfer = 1 395 }, 396 .callback = urtwn_bulk_tx_callback, 397 .timeout = URTWN_TX_TIMEOUT, /* ms */ 398 }, 399 [URTWN_BULK_TX_BK] = { 400 .type = UE_BULK, 401 .endpoint = 0x03, 402 .direction = UE_DIR_OUT, 403 .bufsize = URTWN_TXBUFSZ, 404 .flags = { 405 .ext_buffer = 1, 406 .pipe_bof = 1, 407 .force_short_xfer = 1, 408 }, 409 .callback = urtwn_bulk_tx_callback, 410 .timeout = URTWN_TX_TIMEOUT, /* ms */ 411 }, 412 [URTWN_BULK_TX_VI] = { 413 .type = UE_BULK, 414 .endpoint = 0x02, 415 .direction = UE_DIR_OUT, 416 .bufsize = URTWN_TXBUFSZ, 417 .flags = { 418 .ext_buffer = 1, 419 .pipe_bof = 1, 420 .force_short_xfer = 1 421 }, 422 .callback = urtwn_bulk_tx_callback, 423 .timeout = URTWN_TX_TIMEOUT, /* ms */ 424 }, 425 [URTWN_BULK_TX_VO] = { 426 .type = UE_BULK, 427 .endpoint = 0x02, 428 .direction = UE_DIR_OUT, 429 .bufsize = URTWN_TXBUFSZ, 430 .flags = { 431 .ext_buffer = 1, 432 .pipe_bof = 1, 433 .force_short_xfer = 1 434 }, 435 .callback = urtwn_bulk_tx_callback, 436 .timeout = URTWN_TX_TIMEOUT, /* ms */ 437 }, 438}; 439 440static const struct wme_to_queue { 441 uint16_t reg; 442 uint8_t qid; 443} wme2queue[WME_NUM_AC] = { 444 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 445 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 446 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 447 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 448}; 449 450static int 451urtwn_match(device_t self) 452{ 453 struct usb_attach_arg *uaa = device_get_ivars(self); 454 455 if (uaa->usb_mode != USB_MODE_HOST) 456 return (ENXIO); 457 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 458 return (ENXIO); 459 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 460 return (ENXIO); 461 462 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 463} 464 465static int 466urtwn_attach(device_t self) 467{ 468 struct usb_attach_arg *uaa = device_get_ivars(self); 469 struct urtwn_softc *sc = device_get_softc(self); 470 struct ieee80211com *ic = &sc->sc_ic; 471 uint8_t bands[howmany(IEEE80211_MODE_MAX, 8)]; 472 int error; 473 474 device_set_usb_desc(self); 475 sc->sc_udev = uaa->device; 476 sc->sc_dev = self; 477 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 478 sc->chip |= URTWN_CHIP_88E; 479 480#ifdef USB_DEBUG 481 int debug; 482 if (resource_int_value(device_get_name(sc->sc_dev), 483 device_get_unit(sc->sc_dev), "debug", &debug) == 0) 484 sc->sc_debug = debug; 485#endif 486 487 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 488 MTX_NETWORK_LOCK, MTX_DEF); 489 URTWN_CMDQ_LOCK_INIT(sc); 490 URTWN_NT_LOCK_INIT(sc); 491 callout_init(&sc->sc_calib_to, 0); 492 callout_init(&sc->sc_watchdog_ch, 0); 493 mbufq_init(&sc->sc_snd, ifqmaxlen); 494 495 sc->sc_iface_index = URTWN_IFACE_INDEX; 496 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 497 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 498 if (error) { 499 device_printf(self, "could not allocate USB transfers, " 500 "err=%s\n", usbd_errstr(error)); 501 goto detach; 502 } 503 504 URTWN_LOCK(sc); 505 506 error = urtwn_read_chipid(sc); 507 if (error) { 508 device_printf(sc->sc_dev, "unsupported test chip\n"); 509 URTWN_UNLOCK(sc); 510 goto detach; 511 } 512 513 /* Determine number of Tx/Rx chains. */ 514 if (sc->chip & URTWN_CHIP_92C) { 515 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 516 sc->nrxchains = 2; 517 } else { 518 sc->ntxchains = 1; 519 sc->nrxchains = 1; 520 } 521 522 if (sc->chip & URTWN_CHIP_88E) 523 error = urtwn_r88e_read_rom(sc); 524 else 525 error = urtwn_read_rom(sc); 526 if (error != 0) { 527 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 528 __func__, error); 529 URTWN_UNLOCK(sc); 530 goto detach; 531 } 532 533 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 534 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 535 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 536 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 537 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 538 "8188CUS", sc->ntxchains, sc->nrxchains); 539 540 URTWN_UNLOCK(sc); 541 542 ic->ic_softc = sc; 543 ic->ic_name = device_get_nameunit(self); 544 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 545 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 546 547 /* set device capabilities */ 548 ic->ic_caps = 549 IEEE80211_C_STA /* station mode */ 550 | IEEE80211_C_MONITOR /* monitor mode */ 551 | IEEE80211_C_IBSS /* adhoc mode */ 552 | IEEE80211_C_HOSTAP /* hostap mode */ 553 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 554 | IEEE80211_C_SHSLOT /* short slot time supported */ 555 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 556 | IEEE80211_C_WPA /* 802.11i */ 557 | IEEE80211_C_WME /* 802.11e */ 558 ; 559 560 ic->ic_cryptocaps = 561 IEEE80211_CRYPTO_WEP | 562 IEEE80211_CRYPTO_TKIP | 563 IEEE80211_CRYPTO_AES_CCM; 564 565 memset(bands, 0, sizeof(bands)); 566 setbit(bands, IEEE80211_MODE_11B); 567 setbit(bands, IEEE80211_MODE_11G); 568 ieee80211_init_channels(ic, NULL, bands); 569 570 ieee80211_ifattach(ic); 571 ic->ic_raw_xmit = urtwn_raw_xmit; 572 ic->ic_scan_start = urtwn_scan_start; 573 ic->ic_scan_end = urtwn_scan_end; 574 ic->ic_set_channel = urtwn_set_channel; 575 ic->ic_transmit = urtwn_transmit; 576 ic->ic_parent = urtwn_parent; 577 ic->ic_vap_create = urtwn_vap_create; 578 ic->ic_vap_delete = urtwn_vap_delete; 579 ic->ic_wme.wme_update = urtwn_wme_update; 580 ic->ic_updateslot = urtwn_update_slot; 581 ic->ic_update_promisc = urtwn_update_promisc; 582 ic->ic_update_mcast = urtwn_update_mcast; 583 if (sc->chip & URTWN_CHIP_88E) { 584 ic->ic_node_alloc = urtwn_r88e_node_alloc; 585 ic->ic_newassoc = urtwn_r88e_newassoc; 586 sc->sc_node_free = ic->ic_node_free; 587 ic->ic_node_free = urtwn_r88e_node_free; 588 } 589 590 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 591 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 592 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 593 URTWN_RX_RADIOTAP_PRESENT); 594 595 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc); 596 597 urtwn_sysctlattach(sc); 598 599 if (bootverbose) 600 ieee80211_announce(ic); 601 602 return (0); 603 604detach: 605 urtwn_detach(self); 606 return (ENXIO); /* failure */ 607} 608 609static void 610urtwn_sysctlattach(struct urtwn_softc *sc) 611{ 612#ifdef USB_DEBUG 613 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 614 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 615 616 SYSCTL_ADD_U32(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 617 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 618 "control debugging printfs"); 619#endif 620} 621 622static int 623urtwn_detach(device_t self) 624{ 625 struct urtwn_softc *sc = device_get_softc(self); 626 struct ieee80211com *ic = &sc->sc_ic; 627 unsigned int x; 628 629 /* Prevent further ioctls. */ 630 URTWN_LOCK(sc); 631 sc->sc_flags |= URTWN_DETACHED; 632 URTWN_UNLOCK(sc); 633 634 urtwn_stop(sc); 635 636 callout_drain(&sc->sc_watchdog_ch); 637 callout_drain(&sc->sc_calib_to); 638 639 /* stop all USB transfers */ 640 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 641 642 /* Prevent further allocations from RX/TX data lists. */ 643 URTWN_LOCK(sc); 644 STAILQ_INIT(&sc->sc_tx_active); 645 STAILQ_INIT(&sc->sc_tx_inactive); 646 STAILQ_INIT(&sc->sc_tx_pending); 647 648 STAILQ_INIT(&sc->sc_rx_active); 649 STAILQ_INIT(&sc->sc_rx_inactive); 650 URTWN_UNLOCK(sc); 651 652 /* drain USB transfers */ 653 for (x = 0; x != URTWN_N_TRANSFER; x++) 654 usbd_transfer_drain(sc->sc_xfer[x]); 655 656 /* Free data buffers. */ 657 URTWN_LOCK(sc); 658 urtwn_free_tx_list(sc); 659 urtwn_free_rx_list(sc); 660 URTWN_UNLOCK(sc); 661 662 if (ic->ic_softc == sc) { 663 ieee80211_draintask(ic, &sc->cmdq_task); 664 ieee80211_ifdetach(ic); 665 } 666 667 URTWN_NT_LOCK_DESTROY(sc); 668 URTWN_CMDQ_LOCK_DESTROY(sc); 669 mtx_destroy(&sc->sc_mtx); 670 671 return (0); 672} 673 674static void 675urtwn_drain_mbufq(struct urtwn_softc *sc) 676{ 677 struct mbuf *m; 678 struct ieee80211_node *ni; 679 URTWN_ASSERT_LOCKED(sc); 680 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 681 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 682 m->m_pkthdr.rcvif = NULL; 683 ieee80211_free_node(ni); 684 m_freem(m); 685 } 686} 687 688static usb_error_t 689urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 690 void *data) 691{ 692 usb_error_t err; 693 int ntries = 10; 694 695 URTWN_ASSERT_LOCKED(sc); 696 697 while (ntries--) { 698 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 699 req, data, 0, NULL, 250 /* ms */); 700 if (err == 0) 701 break; 702 703 URTWN_DPRINTF(sc, URTWN_DEBUG_USB, 704 "%s: control request failed, %s (retries left: %d)\n", 705 __func__, usbd_errstr(err), ntries); 706 usb_pause_mtx(&sc->sc_mtx, hz / 100); 707 } 708 return (err); 709} 710 711static struct ieee80211vap * 712urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 713 enum ieee80211_opmode opmode, int flags, 714 const uint8_t bssid[IEEE80211_ADDR_LEN], 715 const uint8_t mac[IEEE80211_ADDR_LEN]) 716{ 717 struct urtwn_softc *sc = ic->ic_softc; 718 struct urtwn_vap *uvp; 719 struct ieee80211vap *vap; 720 721 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 722 return (NULL); 723 724 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 725 vap = &uvp->vap; 726 /* enable s/w bmiss handling for sta mode */ 727 728 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 729 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 730 /* out of memory */ 731 free(uvp, M_80211_VAP); 732 return (NULL); 733 } 734 735 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 736 urtwn_init_beacon(sc, uvp); 737 738 /* override state transition machine */ 739 uvp->newstate = vap->iv_newstate; 740 vap->iv_newstate = urtwn_newstate; 741 vap->iv_update_beacon = urtwn_update_beacon; 742 vap->iv_key_alloc = urtwn_key_alloc; 743 vap->iv_key_set = urtwn_key_set; 744 vap->iv_key_delete = urtwn_key_delete; 745 if (opmode == IEEE80211_M_IBSS) { 746 uvp->recv_mgmt = vap->iv_recv_mgmt; 747 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 748 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 749 } 750 751 if (URTWN_CHIP_HAS_RATECTL(sc)) 752 ieee80211_ratectl_init(vap); 753 /* complete setup */ 754 ieee80211_vap_attach(vap, ieee80211_media_change, 755 ieee80211_media_status, mac); 756 ic->ic_opmode = opmode; 757 return (vap); 758} 759 760static void 761urtwn_vap_delete(struct ieee80211vap *vap) 762{ 763 struct ieee80211com *ic = vap->iv_ic; 764 struct urtwn_softc *sc = ic->ic_softc; 765 struct urtwn_vap *uvp = URTWN_VAP(vap); 766 767 if (uvp->bcn_mbuf != NULL) 768 m_freem(uvp->bcn_mbuf); 769 if (vap->iv_opmode == IEEE80211_M_IBSS) 770 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 771 if (URTWN_CHIP_HAS_RATECTL(sc)) 772 ieee80211_ratectl_deinit(vap); 773 ieee80211_vap_detach(vap); 774 free(uvp, M_80211_VAP); 775} 776 777static struct mbuf * 778urtwn_rx_copy_to_mbuf(struct urtwn_softc *sc, struct r92c_rx_stat *stat, 779 int totlen) 780{ 781 struct ieee80211com *ic = &sc->sc_ic; 782 struct mbuf *m; 783 uint32_t rxdw0; 784 int pktlen; 785 786 /* 787 * don't pass packets to the ieee80211 framework if the driver isn't 788 * RUNNING. 789 */ 790 if (!(sc->sc_flags & URTWN_RUNNING)) 791 return (NULL); 792 793 rxdw0 = le32toh(stat->rxdw0); 794 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 795 /* 796 * This should not happen since we setup our Rx filter 797 * to not receive these frames. 798 */ 799 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 800 "%s: RX flags error (%s)\n", __func__, 801 rxdw0 & R92C_RXDW0_CRCERR ? "CRC" : "ICV"); 802 goto fail; 803 } 804 805 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 806 if (pktlen < sizeof(struct ieee80211_frame_ack)) { 807 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 808 "%s: frame is too short: %d\n", __func__, pktlen); 809 goto fail; 810 } 811 812 if (__predict_false(totlen > MCLBYTES)) { 813 /* convert to m_getjcl if this happens */ 814 device_printf(sc->sc_dev, "%s: frame too long: %d (%d)\n", 815 __func__, pktlen, totlen); 816 goto fail; 817 } 818 819 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 820 if (__predict_false(m == NULL)) { 821 device_printf(sc->sc_dev, "%s: could not allocate RX mbuf\n", 822 __func__); 823 goto fail; 824 } 825 826 /* Finalize mbuf. */ 827 memcpy(mtod(m, uint8_t *), (uint8_t *)stat, totlen); 828 m->m_pkthdr.len = m->m_len = totlen; 829 830 return (m); 831fail: 832 counter_u64_add(ic->ic_ierrors, 1); 833 return (NULL); 834} 835 836static struct mbuf * 837urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data) 838{ 839 struct urtwn_softc *sc = data->sc; 840 struct ieee80211com *ic = &sc->sc_ic; 841 struct r92c_rx_stat *stat; 842 uint8_t *buf; 843 int len; 844 845 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 846 847 if (len < sizeof(*stat)) { 848 counter_u64_add(ic->ic_ierrors, 1); 849 return (NULL); 850 } 851 852 buf = data->buf; 853 stat = (struct r92c_rx_stat *)buf; 854 855 if (sc->chip & URTWN_CHIP_88E) { 856 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 857 858 switch (report_sel) { 859 case R88E_RXDW3_RPT_RX: 860 return (urtwn_rxeof(sc, buf, len)); 861 case R88E_RXDW3_RPT_TX1: 862 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 863 break; 864 default: 865 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, 866 "%s: case %d was not handled\n", __func__, 867 report_sel); 868 break; 869 } 870 } else 871 return (urtwn_rxeof(sc, buf, len)); 872 873 return (NULL); 874} 875 876static struct mbuf * 877urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len) 878{ 879 struct r92c_rx_stat *stat; 880 struct mbuf *m, *m0 = NULL, *prevm = NULL; 881 uint32_t rxdw0; 882 int totlen, pktlen, infosz, npkts; 883 884 /* Get the number of encapsulated frames. */ 885 stat = (struct r92c_rx_stat *)buf; 886 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 887 URTWN_DPRINTF(sc, URTWN_DEBUG_RECV, 888 "%s: Rx %d frames in one chunk\n", __func__, npkts); 889 890 /* Process all of them. */ 891 while (npkts-- > 0) { 892 if (len < sizeof(*stat)) 893 break; 894 stat = (struct r92c_rx_stat *)buf; 895 rxdw0 = le32toh(stat->rxdw0); 896 897 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 898 if (pktlen == 0) 899 break; 900 901 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 902 903 /* Make sure everything fits in xfer. */ 904 totlen = sizeof(*stat) + infosz + pktlen; 905 if (totlen > len) 906 break; 907 908 m = urtwn_rx_copy_to_mbuf(sc, stat, totlen); 909 if (m0 == NULL) 910 m0 = m; 911 if (prevm == NULL) 912 prevm = m; 913 else { 914 prevm->m_next = m; 915 prevm = m; 916 } 917 918 /* Next chunk is 128-byte aligned. */ 919 totlen = (totlen + 127) & ~127; 920 buf += totlen; 921 len -= totlen; 922 } 923 924 return (m0); 925} 926 927static void 928urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 929{ 930 struct r88e_tx_rpt_ccx *rpt = arg; 931 struct ieee80211vap *vap; 932 struct ieee80211_node *ni; 933 uint8_t macid; 934 int ntries; 935 936 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 937 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 938 939 URTWN_NT_LOCK(sc); 940 ni = sc->node_list[macid]; 941 if (ni != NULL) { 942 vap = ni->ni_vap; 943 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: frame for macid %d was" 944 "%s sent (%d retries)\n", __func__, macid, 945 (rpt->rptb1 & R88E_RPTB1_PKT_OK) ? "" : " not", 946 ntries); 947 948 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 949 ieee80211_ratectl_tx_complete(vap, ni, 950 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 951 } else { 952 ieee80211_ratectl_tx_complete(vap, ni, 953 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 954 } 955 } else { 956 URTWN_DPRINTF(sc, URTWN_DEBUG_INTR, "%s: macid %d, ni is NULL\n", 957 __func__, macid); 958 } 959 URTWN_NT_UNLOCK(sc); 960} 961 962static struct ieee80211_node * 963urtwn_rx_frame(struct urtwn_softc *sc, struct mbuf *m, int8_t *rssi_p) 964{ 965 struct ieee80211com *ic = &sc->sc_ic; 966 struct ieee80211_frame_min *wh; 967 struct r92c_rx_stat *stat; 968 uint32_t rxdw0, rxdw3; 969 uint8_t rate, cipher; 970 int8_t rssi = URTWN_NOISE_FLOOR + 1; 971 int infosz; 972 973 stat = mtod(m, struct r92c_rx_stat *); 974 rxdw0 = le32toh(stat->rxdw0); 975 rxdw3 = le32toh(stat->rxdw3); 976 977 rate = MS(rxdw3, R92C_RXDW3_RATE); 978 cipher = MS(rxdw0, R92C_RXDW0_CIPHER); 979 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 980 981 /* Get RSSI from PHY status descriptor if present. */ 982 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 983 if (sc->chip & URTWN_CHIP_88E) 984 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 985 else 986 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 987 /* Update our average RSSI. */ 988 urtwn_update_avgrssi(sc, rate, rssi); 989 } 990 991 if (ieee80211_radiotap_active(ic)) { 992 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 993 994 tap->wr_flags = 0; 995 996 urtwn_get_tsf(sc, &tap->wr_tsft); 997 if (__predict_false(le32toh((uint32_t)tap->wr_tsft) < 998 le32toh(stat->rxdw5))) { 999 tap->wr_tsft = le32toh(tap->wr_tsft >> 32) - 1; 1000 tap->wr_tsft = (uint64_t)htole32(tap->wr_tsft) << 32; 1001 } else 1002 tap->wr_tsft &= 0xffffffff00000000; 1003 tap->wr_tsft += stat->rxdw5; 1004 1005 /* Map HW rate index to 802.11 rate. */ 1006 if (!(rxdw3 & R92C_RXDW3_HT)) { 1007 tap->wr_rate = ridx2rate[rate]; 1008 } else if (rate >= 12) { /* MCS0~15. */ 1009 /* Bit 7 set means HT MCS instead of rate. */ 1010 tap->wr_rate = 0x80 | (rate - 12); 1011 } 1012 tap->wr_dbm_antsignal = rssi; 1013 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 1014 } 1015 1016 *rssi_p = rssi; 1017 1018 /* Drop descriptor. */ 1019 m_adj(m, sizeof(*stat) + infosz); 1020 wh = mtod(m, struct ieee80211_frame_min *); 1021 1022 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1023 cipher != R92C_CAM_ALGO_NONE) { 1024 m->m_flags |= M_WEP; 1025 } 1026 1027 if (m->m_len >= sizeof(*wh)) 1028 return (ieee80211_find_rxnode(ic, wh)); 1029 1030 return (NULL); 1031} 1032 1033static void 1034urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 1035{ 1036 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1037 struct ieee80211com *ic = &sc->sc_ic; 1038 struct ieee80211_node *ni; 1039 struct mbuf *m = NULL, *next; 1040 struct urtwn_data *data; 1041 int8_t nf, rssi; 1042 1043 URTWN_ASSERT_LOCKED(sc); 1044 1045 switch (USB_GET_STATE(xfer)) { 1046 case USB_ST_TRANSFERRED: 1047 data = STAILQ_FIRST(&sc->sc_rx_active); 1048 if (data == NULL) 1049 goto tr_setup; 1050 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1051 m = urtwn_report_intr(xfer, data); 1052 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1053 /* FALLTHROUGH */ 1054 case USB_ST_SETUP: 1055tr_setup: 1056 data = STAILQ_FIRST(&sc->sc_rx_inactive); 1057 if (data == NULL) { 1058 KASSERT(m == NULL, ("mbuf isn't NULL")); 1059 return; 1060 } 1061 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 1062 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 1063 usbd_xfer_set_frame_data(xfer, 0, data->buf, 1064 usbd_xfer_max_len(xfer)); 1065 usbd_transfer_submit(xfer); 1066 1067 /* 1068 * To avoid LOR we should unlock our private mutex here to call 1069 * ieee80211_input() because here is at the end of a USB 1070 * callback and safe to unlock. 1071 */ 1072 while (m != NULL) { 1073 next = m->m_next; 1074 m->m_next = NULL; 1075 1076 ni = urtwn_rx_frame(sc, m, &rssi); 1077 URTWN_UNLOCK(sc); 1078 1079 nf = URTWN_NOISE_FLOOR; 1080 if (ni != NULL) { 1081 (void)ieee80211_input(ni, m, rssi - nf, nf); 1082 ieee80211_free_node(ni); 1083 } else { 1084 (void)ieee80211_input_all(ic, m, rssi - nf, 1085 nf); 1086 } 1087 1088 URTWN_LOCK(sc); 1089 m = next; 1090 } 1091 break; 1092 default: 1093 /* needs it to the inactive queue due to a error. */ 1094 data = STAILQ_FIRST(&sc->sc_rx_active); 1095 if (data != NULL) { 1096 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1097 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1098 } 1099 if (error != USB_ERR_CANCELLED) { 1100 usbd_xfer_set_stall(xfer); 1101 counter_u64_add(ic->ic_ierrors, 1); 1102 goto tr_setup; 1103 } 1104 break; 1105 } 1106} 1107 1108static void 1109urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 1110{ 1111 1112 URTWN_ASSERT_LOCKED(sc); 1113 1114 if (data->ni != NULL) /* not a beacon frame */ 1115 ieee80211_tx_complete(data->ni, data->m, status); 1116 1117 data->ni = NULL; 1118 data->m = NULL; 1119 1120 sc->sc_txtimer = 0; 1121 1122 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 1123} 1124 1125static int 1126urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1127 int ndata, int maxsz) 1128{ 1129 int i, error; 1130 1131 for (i = 0; i < ndata; i++) { 1132 struct urtwn_data *dp = &data[i]; 1133 dp->sc = sc; 1134 dp->m = NULL; 1135 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1136 if (dp->buf == NULL) { 1137 device_printf(sc->sc_dev, 1138 "could not allocate buffer\n"); 1139 error = ENOMEM; 1140 goto fail; 1141 } 1142 dp->ni = NULL; 1143 } 1144 1145 return (0); 1146fail: 1147 urtwn_free_list(sc, data, ndata); 1148 return (error); 1149} 1150 1151static int 1152urtwn_alloc_rx_list(struct urtwn_softc *sc) 1153{ 1154 int error, i; 1155 1156 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1157 URTWN_RXBUFSZ); 1158 if (error != 0) 1159 return (error); 1160 1161 STAILQ_INIT(&sc->sc_rx_active); 1162 STAILQ_INIT(&sc->sc_rx_inactive); 1163 1164 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1165 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1166 1167 return (0); 1168} 1169 1170static int 1171urtwn_alloc_tx_list(struct urtwn_softc *sc) 1172{ 1173 int error, i; 1174 1175 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1176 URTWN_TXBUFSZ); 1177 if (error != 0) 1178 return (error); 1179 1180 STAILQ_INIT(&sc->sc_tx_active); 1181 STAILQ_INIT(&sc->sc_tx_inactive); 1182 STAILQ_INIT(&sc->sc_tx_pending); 1183 1184 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1185 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1186 1187 return (0); 1188} 1189 1190static void 1191urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1192{ 1193 int i; 1194 1195 for (i = 0; i < ndata; i++) { 1196 struct urtwn_data *dp = &data[i]; 1197 1198 if (dp->buf != NULL) { 1199 free(dp->buf, M_USBDEV); 1200 dp->buf = NULL; 1201 } 1202 if (dp->ni != NULL) { 1203 ieee80211_free_node(dp->ni); 1204 dp->ni = NULL; 1205 } 1206 } 1207} 1208 1209static void 1210urtwn_free_rx_list(struct urtwn_softc *sc) 1211{ 1212 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1213} 1214 1215static void 1216urtwn_free_tx_list(struct urtwn_softc *sc) 1217{ 1218 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1219} 1220 1221static void 1222urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1223{ 1224 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1225 struct urtwn_data *data; 1226 1227 URTWN_ASSERT_LOCKED(sc); 1228 1229 switch (USB_GET_STATE(xfer)){ 1230 case USB_ST_TRANSFERRED: 1231 data = STAILQ_FIRST(&sc->sc_tx_active); 1232 if (data == NULL) 1233 goto tr_setup; 1234 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1235 urtwn_txeof(sc, data, 0); 1236 /* FALLTHROUGH */ 1237 case USB_ST_SETUP: 1238tr_setup: 1239 data = STAILQ_FIRST(&sc->sc_tx_pending); 1240 if (data == NULL) { 1241 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1242 "%s: empty pending queue\n", __func__); 1243 goto finish; 1244 } 1245 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1246 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1247 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1248 usbd_transfer_submit(xfer); 1249 break; 1250 default: 1251 data = STAILQ_FIRST(&sc->sc_tx_active); 1252 if (data == NULL) 1253 goto tr_setup; 1254 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1255 urtwn_txeof(sc, data, 1); 1256 if (error != USB_ERR_CANCELLED) { 1257 usbd_xfer_set_stall(xfer); 1258 goto tr_setup; 1259 } 1260 break; 1261 } 1262finish: 1263 /* Kick-start more transmit */ 1264 urtwn_start(sc); 1265} 1266 1267static struct urtwn_data * 1268_urtwn_getbuf(struct urtwn_softc *sc) 1269{ 1270 struct urtwn_data *bf; 1271 1272 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1273 if (bf != NULL) 1274 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1275 else { 1276 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, 1277 "%s: out of xmit buffers\n", __func__); 1278 } 1279 return (bf); 1280} 1281 1282static struct urtwn_data * 1283urtwn_getbuf(struct urtwn_softc *sc) 1284{ 1285 struct urtwn_data *bf; 1286 1287 URTWN_ASSERT_LOCKED(sc); 1288 1289 bf = _urtwn_getbuf(sc); 1290 if (bf == NULL) { 1291 URTWN_DPRINTF(sc, URTWN_DEBUG_XMIT, "%s: stop queue\n", 1292 __func__); 1293 } 1294 return (bf); 1295} 1296 1297static usb_error_t 1298urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1299 int len) 1300{ 1301 usb_device_request_t req; 1302 1303 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1304 req.bRequest = R92C_REQ_REGS; 1305 USETW(req.wValue, addr); 1306 USETW(req.wIndex, 0); 1307 USETW(req.wLength, len); 1308 return (urtwn_do_request(sc, &req, buf)); 1309} 1310 1311static usb_error_t 1312urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1313{ 1314 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1315} 1316 1317static usb_error_t 1318urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1319{ 1320 val = htole16(val); 1321 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1322} 1323 1324static usb_error_t 1325urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1326{ 1327 val = htole32(val); 1328 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1329} 1330 1331static usb_error_t 1332urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1333 int len) 1334{ 1335 usb_device_request_t req; 1336 1337 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1338 req.bRequest = R92C_REQ_REGS; 1339 USETW(req.wValue, addr); 1340 USETW(req.wIndex, 0); 1341 USETW(req.wLength, len); 1342 return (urtwn_do_request(sc, &req, buf)); 1343} 1344 1345static uint8_t 1346urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1347{ 1348 uint8_t val; 1349 1350 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1351 return (0xff); 1352 return (val); 1353} 1354 1355static uint16_t 1356urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1357{ 1358 uint16_t val; 1359 1360 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1361 return (0xffff); 1362 return (le16toh(val)); 1363} 1364 1365static uint32_t 1366urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1367{ 1368 uint32_t val; 1369 1370 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1371 return (0xffffffff); 1372 return (le32toh(val)); 1373} 1374 1375static int 1376urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1377{ 1378 struct r92c_fw_cmd cmd; 1379 usb_error_t error; 1380 int ntries; 1381 1382 if (!(sc->sc_flags & URTWN_FW_LOADED)) { 1383 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, "%s: firmware " 1384 "was not loaded; command (id %d) will be discarded\n", 1385 __func__, id); 1386 return (0); 1387 } 1388 1389 /* Wait for current FW box to be empty. */ 1390 for (ntries = 0; ntries < 100; ntries++) { 1391 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1392 break; 1393 urtwn_ms_delay(sc); 1394 } 1395 if (ntries == 100) { 1396 device_printf(sc->sc_dev, 1397 "could not send firmware command\n"); 1398 return (ETIMEDOUT); 1399 } 1400 memset(&cmd, 0, sizeof(cmd)); 1401 cmd.id = id; 1402 if (len > 3) 1403 cmd.id |= R92C_CMD_FLAG_EXT; 1404 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1405 memcpy(cmd.msg, buf, len); 1406 1407 /* Write the first word last since that will trigger the FW. */ 1408 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1409 (uint8_t *)&cmd + 4, 2); 1410 if (error != USB_ERR_NORMAL_COMPLETION) 1411 return (EIO); 1412 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1413 (uint8_t *)&cmd + 0, 4); 1414 if (error != USB_ERR_NORMAL_COMPLETION) 1415 return (EIO); 1416 1417 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1418 return (0); 1419} 1420 1421static void 1422urtwn_cmdq_cb(void *arg, int pending) 1423{ 1424 struct urtwn_softc *sc = arg; 1425 struct urtwn_cmdq *item; 1426 1427 /* 1428 * Device must be powered on (via urtwn_power_on()) 1429 * before any command may be sent. 1430 */ 1431 URTWN_LOCK(sc); 1432 if (!(sc->sc_flags & URTWN_RUNNING)) { 1433 URTWN_UNLOCK(sc); 1434 return; 1435 } 1436 1437 URTWN_CMDQ_LOCK(sc); 1438 while (sc->cmdq[sc->cmdq_first].func != NULL) { 1439 item = &sc->cmdq[sc->cmdq_first]; 1440 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE; 1441 URTWN_CMDQ_UNLOCK(sc); 1442 1443 item->func(sc, &item->data); 1444 1445 URTWN_CMDQ_LOCK(sc); 1446 memset(item, 0, sizeof (*item)); 1447 } 1448 URTWN_CMDQ_UNLOCK(sc); 1449 URTWN_UNLOCK(sc); 1450} 1451 1452static int 1453urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len, 1454 CMD_FUNC_PROTO) 1455{ 1456 struct ieee80211com *ic = &sc->sc_ic; 1457 1458 KASSERT(len <= sizeof(union sec_param), ("buffer overflow")); 1459 1460 URTWN_CMDQ_LOCK(sc); 1461 if (sc->cmdq[sc->cmdq_last].func != NULL) { 1462 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__); 1463 URTWN_CMDQ_UNLOCK(sc); 1464 1465 return (EAGAIN); 1466 } 1467 1468 if (ptr != NULL) 1469 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len); 1470 sc->cmdq[sc->cmdq_last].func = func; 1471 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE; 1472 URTWN_CMDQ_UNLOCK(sc); 1473 1474 ieee80211_runtask(ic, &sc->cmdq_task); 1475 1476 return (0); 1477} 1478 1479static __inline void 1480urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1481{ 1482 1483 sc->sc_rf_write(sc, chain, addr, val); 1484} 1485 1486static void 1487urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1488 uint32_t val) 1489{ 1490 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1491 SM(R92C_LSSI_PARAM_ADDR, addr) | 1492 SM(R92C_LSSI_PARAM_DATA, val)); 1493} 1494 1495static void 1496urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1497uint32_t val) 1498{ 1499 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1500 SM(R88E_LSSI_PARAM_ADDR, addr) | 1501 SM(R92C_LSSI_PARAM_DATA, val)); 1502} 1503 1504static uint32_t 1505urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1506{ 1507 uint32_t reg[R92C_MAX_CHAINS], val; 1508 1509 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1510 if (chain != 0) 1511 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1512 1513 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1514 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1515 urtwn_ms_delay(sc); 1516 1517 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1518 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1519 R92C_HSSI_PARAM2_READ_EDGE); 1520 urtwn_ms_delay(sc); 1521 1522 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1523 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1524 urtwn_ms_delay(sc); 1525 1526 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1527 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1528 else 1529 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1530 return (MS(val, R92C_LSSI_READBACK_DATA)); 1531} 1532 1533static int 1534urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1535{ 1536 usb_error_t error; 1537 int ntries; 1538 1539 error = urtwn_write_4(sc, R92C_LLT_INIT, 1540 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1541 SM(R92C_LLT_INIT_ADDR, addr) | 1542 SM(R92C_LLT_INIT_DATA, data)); 1543 if (error != USB_ERR_NORMAL_COMPLETION) 1544 return (EIO); 1545 /* Wait for write operation to complete. */ 1546 for (ntries = 0; ntries < 20; ntries++) { 1547 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1548 R92C_LLT_INIT_OP_NO_ACTIVE) 1549 return (0); 1550 urtwn_ms_delay(sc); 1551 } 1552 return (ETIMEDOUT); 1553} 1554 1555static int 1556urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1557{ 1558 uint32_t reg; 1559 usb_error_t error; 1560 int ntries; 1561 1562 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1563 return (EFAULT); 1564 1565 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1566 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1567 reg &= ~R92C_EFUSE_CTRL_VALID; 1568 1569 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1570 if (error != USB_ERR_NORMAL_COMPLETION) 1571 return (EIO); 1572 /* Wait for read operation to complete. */ 1573 for (ntries = 0; ntries < 100; ntries++) { 1574 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1575 if (reg & R92C_EFUSE_CTRL_VALID) 1576 break; 1577 urtwn_ms_delay(sc); 1578 } 1579 if (ntries == 100) { 1580 device_printf(sc->sc_dev, 1581 "could not read efuse byte at address 0x%x\n", 1582 sc->last_rom_addr); 1583 return (ETIMEDOUT); 1584 } 1585 1586 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1587 sc->last_rom_addr++; 1588 1589 return (0); 1590} 1591 1592static int 1593urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1594 uint8_t msk) 1595{ 1596 uint8_t reg; 1597 int i, error; 1598 1599 for (i = 0; i < 4; i++) { 1600 if (msk & (1 << i)) 1601 continue; 1602 error = urtwn_efuse_read_next(sc, ®); 1603 if (error != 0) 1604 return (error); 1605 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1606 off * 8 + i * 2, reg); 1607 rom[off * 8 + i * 2 + 0] = reg; 1608 1609 error = urtwn_efuse_read_next(sc, ®); 1610 if (error != 0) 1611 return (error); 1612 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "rom[0x%03X] == 0x%02X\n", 1613 off * 8 + i * 2 + 1, reg); 1614 rom[off * 8 + i * 2 + 1] = reg; 1615 } 1616 1617 return (0); 1618} 1619 1620#ifdef USB_DEBUG 1621static void 1622urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1623{ 1624 int i; 1625 1626 /* Dump ROM contents. */ 1627 device_printf(sc->sc_dev, "%s:", __func__); 1628 for (i = 0; i < size; i++) { 1629 if (i % 32 == 0) 1630 printf("\n%03X: ", i); 1631 else if (i % 4 == 0) 1632 printf(" "); 1633 1634 printf("%02X", rom[i]); 1635 } 1636 printf("\n"); 1637} 1638#endif 1639 1640static int 1641urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1642{ 1643#define URTWN_CHK(res) do { \ 1644 if ((error = res) != 0) \ 1645 goto end; \ 1646} while(0) 1647 uint8_t msk, off, reg; 1648 int error; 1649 1650 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1651 1652 /* Read full ROM image. */ 1653 sc->last_rom_addr = 0; 1654 memset(rom, 0xff, size); 1655 1656 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1657 while (reg != 0xff) { 1658 /* check for extended header */ 1659 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1660 off = reg >> 5; 1661 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1662 1663 if ((reg & 0x0f) != 0x0f) 1664 off = ((reg & 0xf0) >> 1) | off; 1665 else 1666 continue; 1667 } else 1668 off = reg >> 4; 1669 msk = reg & 0xf; 1670 1671 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1672 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1673 } 1674 1675end: 1676 1677#ifdef USB_DEBUG 1678 if (sc->sc_debug & URTWN_DEBUG_ROM) 1679 urtwn_dump_rom_contents(sc, rom, size); 1680#endif 1681 1682 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1683 1684 if (error != 0) { 1685 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1686 __func__); 1687 } 1688 1689 return (error); 1690#undef URTWN_CHK 1691} 1692 1693static int 1694urtwn_efuse_switch_power(struct urtwn_softc *sc) 1695{ 1696 usb_error_t error; 1697 uint32_t reg; 1698 1699 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1700 if (error != USB_ERR_NORMAL_COMPLETION) 1701 return (EIO); 1702 1703 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1704 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1705 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1706 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1707 if (error != USB_ERR_NORMAL_COMPLETION) 1708 return (EIO); 1709 } 1710 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1711 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1712 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1713 reg | R92C_SYS_FUNC_EN_ELDR); 1714 if (error != USB_ERR_NORMAL_COMPLETION) 1715 return (EIO); 1716 } 1717 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1718 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1719 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1720 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1721 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1722 if (error != USB_ERR_NORMAL_COMPLETION) 1723 return (EIO); 1724 } 1725 1726 return (0); 1727} 1728 1729static int 1730urtwn_read_chipid(struct urtwn_softc *sc) 1731{ 1732 uint32_t reg; 1733 1734 if (sc->chip & URTWN_CHIP_88E) 1735 return (0); 1736 1737 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1738 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1739 return (EIO); 1740 1741 if (reg & R92C_SYS_CFG_TYPE_92C) { 1742 sc->chip |= URTWN_CHIP_92C; 1743 /* Check if it is a castrated 8192C. */ 1744 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1745 R92C_HPON_FSM_CHIP_BONDING_ID) == 1746 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1747 sc->chip |= URTWN_CHIP_92C_1T2R; 1748 } 1749 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1750 sc->chip |= URTWN_CHIP_UMC; 1751 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1752 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1753 } 1754 return (0); 1755} 1756 1757static int 1758urtwn_read_rom(struct urtwn_softc *sc) 1759{ 1760 struct r92c_rom *rom = &sc->rom.r92c_rom; 1761 int error; 1762 1763 /* Read full ROM image. */ 1764 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1765 if (error != 0) 1766 return (error); 1767 1768 /* XXX Weird but this is what the vendor driver does. */ 1769 sc->last_rom_addr = 0x1fa; 1770 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1771 if (error != 0) 1772 return (error); 1773 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: PA setting=0x%x\n", __func__, 1774 sc->pa_setting); 1775 1776 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1777 1778 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1779 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type=%d\n", 1780 __func__, sc->regulatory); 1781 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1782 1783 sc->sc_rf_write = urtwn_r92c_rf_write; 1784 sc->sc_power_on = urtwn_r92c_power_on; 1785 1786 return (0); 1787} 1788 1789static int 1790urtwn_r88e_read_rom(struct urtwn_softc *sc) 1791{ 1792 struct r88e_rom *rom = &sc->rom.r88e_rom; 1793 int error; 1794 1795 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(sc->rom.r88e_rom)); 1796 if (error != 0) 1797 return (error); 1798 1799 sc->bw20_tx_pwr_diff = (rom->tx_pwr_diff >> 4); 1800 if (sc->bw20_tx_pwr_diff & 0x08) 1801 sc->bw20_tx_pwr_diff |= 0xf0; 1802 sc->ofdm_tx_pwr_diff = (rom->tx_pwr_diff & 0xf); 1803 if (sc->ofdm_tx_pwr_diff & 0x08) 1804 sc->ofdm_tx_pwr_diff |= 0xf0; 1805 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 1806 URTWN_DPRINTF(sc, URTWN_DEBUG_ROM, "%s: regulatory type %d\n", 1807 __func__,sc->regulatory); 1808 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1809 1810 sc->sc_rf_write = urtwn_r88e_rf_write; 1811 sc->sc_power_on = urtwn_r88e_power_on; 1812 1813 return (0); 1814} 1815 1816/* 1817 * Initialize rate adaptation in firmware. 1818 */ 1819static int 1820urtwn_ra_init(struct urtwn_softc *sc) 1821{ 1822 struct ieee80211com *ic = &sc->sc_ic; 1823 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1824 struct ieee80211_node *ni; 1825 struct ieee80211_rateset *rs; 1826 struct r92c_fw_cmd_macid_cfg cmd; 1827 uint32_t rates, basicrates; 1828 uint8_t mode; 1829 int maxrate, maxbasicrate, error, i, j; 1830 1831 ni = ieee80211_ref_node(vap->iv_bss); 1832 rs = &ni->ni_rates; 1833 1834 /* Get normal and basic rates mask. */ 1835 rates = basicrates = 0; 1836 maxrate = maxbasicrate = 0; 1837 for (i = 0; i < rs->rs_nrates; i++) { 1838 /* Convert 802.11 rate to HW rate index. */ 1839 for (j = 0; j < nitems(ridx2rate); j++) 1840 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1841 ridx2rate[j]) 1842 break; 1843 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1844 continue; 1845 rates |= 1 << j; 1846 if (j > maxrate) 1847 maxrate = j; 1848 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1849 basicrates |= 1 << j; 1850 if (j > maxbasicrate) 1851 maxbasicrate = j; 1852 } 1853 } 1854 if (ic->ic_curmode == IEEE80211_MODE_11B) 1855 mode = R92C_RAID_11B; 1856 else 1857 mode = R92C_RAID_11BG; 1858 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, 1859 "%s: mode 0x%x, rates 0x%08x, basicrates 0x%08x\n", __func__, 1860 mode, rates, basicrates); 1861 1862 /* Set rates mask for group addressed frames. */ 1863 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1864 cmd.mask = htole32(mode << 28 | basicrates); 1865 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1866 if (error != 0) { 1867 ieee80211_free_node(ni); 1868 device_printf(sc->sc_dev, 1869 "could not add broadcast station\n"); 1870 return (error); 1871 } 1872 /* Set initial MRR rate. */ 1873 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxbasicrate %d\n", __func__, 1874 maxbasicrate); 1875 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1876 maxbasicrate); 1877 1878 /* Set rates mask for unicast frames. */ 1879 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1880 cmd.mask = htole32(mode << 28 | rates); 1881 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1882 if (error != 0) { 1883 ieee80211_free_node(ni); 1884 device_printf(sc->sc_dev, "could not add BSS station\n"); 1885 return (error); 1886 } 1887 /* Set initial MRR rate. */ 1888 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: maxrate %d\n", __func__, 1889 maxrate); 1890 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1891 maxrate); 1892 1893 /* Indicate highest supported rate. */ 1894 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1895 ieee80211_free_node(ni); 1896 1897 return (0); 1898} 1899 1900static void 1901urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1902{ 1903 struct r92c_tx_desc *txd = &uvp->bcn_desc; 1904 1905 txd->txdw0 = htole32( 1906 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 1907 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1908 txd->txdw1 = htole32( 1909 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 1910 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1911 1912 if (sc->chip & URTWN_CHIP_88E) { 1913 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 1914 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 1915 } else { 1916 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 1917 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 1918 } 1919 1920 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 1921 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 1922} 1923 1924static int 1925urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 1926{ 1927 struct ieee80211vap *vap = ni->ni_vap; 1928 struct urtwn_vap *uvp = URTWN_VAP(vap); 1929 struct mbuf *m; 1930 int error; 1931 1932 URTWN_ASSERT_LOCKED(sc); 1933 1934 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 1935 return (EINVAL); 1936 1937 m = ieee80211_beacon_alloc(ni); 1938 if (m == NULL) { 1939 device_printf(sc->sc_dev, 1940 "%s: could not allocate beacon frame\n", __func__); 1941 return (ENOMEM); 1942 } 1943 1944 if (uvp->bcn_mbuf != NULL) 1945 m_freem(uvp->bcn_mbuf); 1946 1947 uvp->bcn_mbuf = m; 1948 1949 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1950 return (error); 1951 1952 /* XXX bcnq stuck workaround */ 1953 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1954 return (error); 1955 1956 URTWN_DPRINTF(sc, URTWN_DEBUG_BEACON, "%s: beacon was %srecognized\n", 1957 __func__, urtwn_read_1(sc, R92C_TDECTRL + 2) & 1958 (R92C_TDECTRL_BCN_VALID >> 16) ? "" : "not "); 1959 1960 return (0); 1961} 1962 1963static void 1964urtwn_update_beacon(struct ieee80211vap *vap, int item) 1965{ 1966 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1967 struct urtwn_vap *uvp = URTWN_VAP(vap); 1968 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 1969 struct ieee80211_node *ni = vap->iv_bss; 1970 int mcast = 0; 1971 1972 URTWN_LOCK(sc); 1973 if (uvp->bcn_mbuf == NULL) { 1974 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 1975 if (uvp->bcn_mbuf == NULL) { 1976 device_printf(sc->sc_dev, 1977 "%s: could not allocate beacon frame\n", __func__); 1978 URTWN_UNLOCK(sc); 1979 return; 1980 } 1981 } 1982 URTWN_UNLOCK(sc); 1983 1984 if (item == IEEE80211_BEACON_TIM) 1985 mcast = 1; /* XXX */ 1986 1987 setbit(bo->bo_flags, item); 1988 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 1989 1990 URTWN_LOCK(sc); 1991 urtwn_tx_beacon(sc, uvp); 1992 URTWN_UNLOCK(sc); 1993} 1994 1995/* 1996 * Push a beacon frame into the chip. Beacon will 1997 * be repeated by the chip every R92C_BCN_INTERVAL. 1998 */ 1999static int 2000urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 2001{ 2002 struct r92c_tx_desc *desc = &uvp->bcn_desc; 2003 struct urtwn_data *bf; 2004 2005 URTWN_ASSERT_LOCKED(sc); 2006 2007 bf = urtwn_getbuf(sc); 2008 if (bf == NULL) 2009 return (ENOMEM); 2010 2011 memcpy(bf->buf, desc, sizeof(*desc)); 2012 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 2013 2014 sc->sc_txtimer = 5; 2015 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2016 2017 return (0); 2018} 2019 2020static int 2021urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2022 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2023{ 2024 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2025 uint8_t i; 2026 2027 if (!(&vap->iv_nw_keys[0] <= k && 2028 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2029 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2030 URTWN_LOCK(sc); 2031 /* 2032 * First 4 slots for group keys, 2033 * what is left - for pairwise. 2034 * XXX incompatible with IBSS RSN. 2035 */ 2036 for (i = IEEE80211_WEP_NKID; 2037 i < R92C_CAM_ENTRY_COUNT; i++) { 2038 if ((sc->keys_bmap & (1 << i)) == 0) { 2039 sc->keys_bmap |= 1 << i; 2040 *keyix = i; 2041 break; 2042 } 2043 } 2044 URTWN_UNLOCK(sc); 2045 if (i == R92C_CAM_ENTRY_COUNT) { 2046 device_printf(sc->sc_dev, 2047 "%s: no free space in the key table\n", 2048 __func__); 2049 return 0; 2050 } 2051 } else 2052 *keyix = 0; 2053 } else { 2054 *keyix = k - vap->iv_nw_keys; 2055 } 2056 *rxkeyix = *keyix; 2057 return 1; 2058} 2059 2060static void 2061urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data) 2062{ 2063 struct ieee80211_key *k = &data->key; 2064 uint8_t algo, keyid; 2065 int i, error; 2066 2067 if (k->wk_keyix < IEEE80211_WEP_NKID) 2068 keyid = k->wk_keyix; 2069 else 2070 keyid = 0; 2071 2072 /* Map net80211 cipher to HW crypto algorithm. */ 2073 switch (k->wk_cipher->ic_cipher) { 2074 case IEEE80211_CIPHER_WEP: 2075 if (k->wk_keylen < 8) 2076 algo = R92C_CAM_ALGO_WEP40; 2077 else 2078 algo = R92C_CAM_ALGO_WEP104; 2079 break; 2080 case IEEE80211_CIPHER_TKIP: 2081 algo = R92C_CAM_ALGO_TKIP; 2082 break; 2083 case IEEE80211_CIPHER_AES_CCM: 2084 algo = R92C_CAM_ALGO_AES; 2085 break; 2086 default: 2087 device_printf(sc->sc_dev, "%s: undefined cipher %d\n", 2088 __func__, k->wk_cipher->ic_cipher); 2089 return; 2090 } 2091 2092 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2093 "%s: keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, " 2094 "macaddr %s\n", __func__, k->wk_keyix, keyid, 2095 k->wk_cipher->ic_cipher, algo, k->wk_flags, k->wk_keylen, 2096 ether_sprintf(k->wk_macaddr)); 2097 2098 /* Write key. */ 2099 for (i = 0; i < 4; i++) { 2100 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 2101 LE_READ_4(&k->wk_key[i * 4])); 2102 if (error != 0) 2103 goto fail; 2104 } 2105 2106 /* Write CTL0 last since that will validate the CAM entry. */ 2107 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 2108 LE_READ_4(&k->wk_macaddr[2])); 2109 if (error != 0) 2110 goto fail; 2111 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 2112 SM(R92C_CAM_ALGO, algo) | 2113 SM(R92C_CAM_KEYID, keyid) | 2114 SM(R92C_CAM_MACLO, LE_READ_2(&k->wk_macaddr[0])) | 2115 R92C_CAM_VALID); 2116 if (error != 0) 2117 goto fail; 2118 2119 return; 2120 2121fail: 2122 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error); 2123} 2124 2125static void 2126urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data) 2127{ 2128 struct ieee80211_key *k = &data->key; 2129 int i; 2130 2131 URTWN_DPRINTF(sc, URTWN_DEBUG_KEY, 2132 "%s: keyix %d, flags %04X, macaddr %s\n", __func__, 2133 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr)); 2134 2135 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0); 2136 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0); 2137 2138 /* Clear key. */ 2139 for (i = 0; i < 4; i++) 2140 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0); 2141 sc->keys_bmap &= ~(1 << k->wk_keyix); 2142} 2143 2144static int 2145urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 2146{ 2147 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2148 2149 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2150 /* Not for us. */ 2151 return (1); 2152 } 2153 2154 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb)); 2155} 2156 2157static int 2158urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2159{ 2160 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2161 2162 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2163 /* Not for us. */ 2164 return (1); 2165 } 2166 2167 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb)); 2168} 2169 2170static void 2171urtwn_tsf_task_adhoc(void *arg, int pending) 2172{ 2173 struct ieee80211vap *vap = arg; 2174 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2175 struct ieee80211_node *ni; 2176 uint32_t reg; 2177 2178 URTWN_LOCK(sc); 2179 ni = ieee80211_ref_node(vap->iv_bss); 2180 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 2181 2182 /* Accept beacons with the same BSSID. */ 2183 urtwn_set_rx_bssid_all(sc, 0); 2184 2185 /* Enable synchronization. */ 2186 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 2187 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2188 2189 /* Synchronize. */ 2190 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 2191 2192 /* Disable synchronization. */ 2193 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 2194 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2195 2196 /* Remove beacon filter. */ 2197 urtwn_set_rx_bssid_all(sc, 1); 2198 2199 /* Enable beaconing. */ 2200 urtwn_write_1(sc, R92C_MBID_NUM, 2201 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2202 reg |= R92C_BCN_CTRL_EN_BCN; 2203 2204 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2205 ieee80211_free_node(ni); 2206 URTWN_UNLOCK(sc); 2207} 2208 2209static void 2210urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 2211{ 2212 struct ieee80211com *ic = &sc->sc_ic; 2213 struct urtwn_vap *uvp = URTWN_VAP(vap); 2214 2215 /* Reset TSF. */ 2216 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2217 2218 switch (vap->iv_opmode) { 2219 case IEEE80211_M_STA: 2220 /* Enable TSF synchronization. */ 2221 urtwn_write_1(sc, R92C_BCN_CTRL, 2222 urtwn_read_1(sc, R92C_BCN_CTRL) & 2223 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 2224 break; 2225 case IEEE80211_M_IBSS: 2226 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 2227 break; 2228 case IEEE80211_M_HOSTAP: 2229 /* Enable beaconing. */ 2230 urtwn_write_1(sc, R92C_MBID_NUM, 2231 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2232 urtwn_write_1(sc, R92C_BCN_CTRL, 2233 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 2234 break; 2235 default: 2236 device_printf(sc->sc_dev, "undefined opmode %d\n", 2237 vap->iv_opmode); 2238 return; 2239 } 2240} 2241 2242static void 2243urtwn_get_tsf(struct urtwn_softc *sc, uint64_t *buf) 2244{ 2245 urtwn_read_region_1(sc, R92C_TSFTR, (uint8_t *)buf, sizeof(*buf)); 2246} 2247 2248static void 2249urtwn_set_led(struct urtwn_softc *sc, int led, int on) 2250{ 2251 uint8_t reg; 2252 2253 if (led == URTWN_LED_LINK) { 2254 if (sc->chip & URTWN_CHIP_88E) { 2255 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 2256 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 2257 if (!on) { 2258 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 2259 urtwn_write_1(sc, R92C_LEDCFG2, 2260 reg | R92C_LEDCFG0_DIS); 2261 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 2262 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 2263 0xfe); 2264 } 2265 } else { 2266 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 2267 if (!on) 2268 reg |= R92C_LEDCFG0_DIS; 2269 urtwn_write_1(sc, R92C_LEDCFG0, reg); 2270 } 2271 sc->ledlink = on; /* Save LED state. */ 2272 } 2273} 2274 2275static void 2276urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 2277{ 2278 uint8_t reg; 2279 2280 reg = urtwn_read_1(sc, R92C_MSR); 2281 reg = (reg & ~R92C_MSR_MASK) | mode; 2282 urtwn_write_1(sc, R92C_MSR, reg); 2283} 2284 2285static void 2286urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 2287 const struct ieee80211_rx_stats *rxs, 2288 int rssi, int nf) 2289{ 2290 struct ieee80211vap *vap = ni->ni_vap; 2291 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2292 struct urtwn_vap *uvp = URTWN_VAP(vap); 2293 uint64_t ni_tstamp, curr_tstamp; 2294 2295 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 2296 2297 if (vap->iv_state == IEEE80211_S_RUN && 2298 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 2299 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 2300 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 2301 URTWN_LOCK(sc); 2302 urtwn_get_tsf(sc, &curr_tstamp); 2303 URTWN_UNLOCK(sc); 2304 curr_tstamp = le64toh(curr_tstamp); 2305 2306 if (ni_tstamp >= curr_tstamp) 2307 (void) ieee80211_ibss_merge(ni); 2308 } 2309} 2310 2311static int 2312urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2313{ 2314 struct urtwn_vap *uvp = URTWN_VAP(vap); 2315 struct ieee80211com *ic = vap->iv_ic; 2316 struct urtwn_softc *sc = ic->ic_softc; 2317 struct ieee80211_node *ni; 2318 enum ieee80211_state ostate; 2319 uint32_t reg; 2320 uint8_t mode; 2321 int error = 0; 2322 2323 ostate = vap->iv_state; 2324 URTWN_DPRINTF(sc, URTWN_DEBUG_STATE, "%s -> %s\n", 2325 ieee80211_state_name[ostate], ieee80211_state_name[nstate]); 2326 2327 IEEE80211_UNLOCK(ic); 2328 URTWN_LOCK(sc); 2329 callout_stop(&sc->sc_watchdog_ch); 2330 2331 if (ostate == IEEE80211_S_RUN) { 2332 /* Stop calibration. */ 2333 callout_stop(&sc->sc_calib_to); 2334 2335 /* Turn link LED off. */ 2336 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2337 2338 /* Set media status to 'No Link'. */ 2339 urtwn_set_mode(sc, R92C_MSR_NOLINK); 2340 2341 /* Stop Rx of data frames. */ 2342 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2343 2344 /* Disable TSF synchronization. */ 2345 urtwn_write_1(sc, R92C_BCN_CTRL, 2346 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 2347 R92C_BCN_CTRL_DIS_TSF_UDT0); 2348 2349 /* Disable beaconing. */ 2350 urtwn_write_1(sc, R92C_MBID_NUM, 2351 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 2352 2353 /* Reset TSF. */ 2354 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2355 2356 /* Reset EDCA parameters. */ 2357 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2358 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2359 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2360 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2361 } 2362 2363 switch (nstate) { 2364 case IEEE80211_S_INIT: 2365 /* Turn link LED off. */ 2366 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2367 break; 2368 case IEEE80211_S_SCAN: 2369 /* Pause AC Tx queues. */ 2370 urtwn_write_1(sc, R92C_TXPAUSE, 2371 urtwn_read_1(sc, R92C_TXPAUSE) | R92C_TX_QUEUE_AC); 2372 break; 2373 case IEEE80211_S_AUTH: 2374 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2375 break; 2376 case IEEE80211_S_RUN: 2377 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2378 /* Turn link LED on. */ 2379 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2380 break; 2381 } 2382 2383 ni = ieee80211_ref_node(vap->iv_bss); 2384 2385 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2386 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2387 device_printf(sc->sc_dev, 2388 "%s: could not move to RUN state\n", __func__); 2389 error = EINVAL; 2390 goto end_run; 2391 } 2392 2393 switch (vap->iv_opmode) { 2394 case IEEE80211_M_STA: 2395 mode = R92C_MSR_INFRA; 2396 break; 2397 case IEEE80211_M_IBSS: 2398 mode = R92C_MSR_ADHOC; 2399 break; 2400 case IEEE80211_M_HOSTAP: 2401 mode = R92C_MSR_AP; 2402 break; 2403 default: 2404 device_printf(sc->sc_dev, "undefined opmode %d\n", 2405 vap->iv_opmode); 2406 error = EINVAL; 2407 goto end_run; 2408 } 2409 2410 /* Set media status to 'Associated'. */ 2411 urtwn_set_mode(sc, mode); 2412 2413 /* Set BSSID. */ 2414 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2415 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2416 2417 if (ic->ic_curmode == IEEE80211_MODE_11B) 2418 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2419 else /* 802.11b/g */ 2420 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2421 2422 /* Enable Rx of data frames. */ 2423 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2424 2425 /* Flush all AC queues. */ 2426 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2427 2428 /* Set beacon interval. */ 2429 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2430 2431 /* Allow Rx from our BSSID only. */ 2432 if (ic->ic_promisc == 0) { 2433 reg = urtwn_read_4(sc, R92C_RCR); 2434 2435 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 2436 reg |= R92C_RCR_CBSSID_DATA; 2437 if (vap->iv_opmode != IEEE80211_M_IBSS) 2438 reg |= R92C_RCR_CBSSID_BCN; 2439 2440 urtwn_write_4(sc, R92C_RCR, reg); 2441 } 2442 2443 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2444 vap->iv_opmode == IEEE80211_M_IBSS) { 2445 error = urtwn_setup_beacon(sc, ni); 2446 if (error != 0) { 2447 device_printf(sc->sc_dev, 2448 "unable to push beacon into the chip, " 2449 "error %d\n", error); 2450 goto end_run; 2451 } 2452 } 2453 2454 /* Enable TSF synchronization. */ 2455 urtwn_tsf_sync_enable(sc, vap); 2456 2457 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2458 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2459 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2460 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2461 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2462 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2463 2464 /* Intialize rate adaptation. */ 2465 if (!(sc->chip & URTWN_CHIP_88E)) 2466 urtwn_ra_init(sc); 2467 /* Turn link LED on. */ 2468 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2469 2470 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2471 /* Reset temperature calibration state machine. */ 2472 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 2473 sc->thcal_lctemp = 0; 2474 /* Start periodic calibration. */ 2475 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2476 2477end_run: 2478 ieee80211_free_node(ni); 2479 break; 2480 default: 2481 break; 2482 } 2483 2484 URTWN_UNLOCK(sc); 2485 IEEE80211_LOCK(ic); 2486 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2487} 2488 2489static void 2490urtwn_calib_to(void *arg) 2491{ 2492 struct urtwn_softc *sc = arg; 2493 2494 /* Do it in a process context. */ 2495 urtwn_cmd_sleepable(sc, NULL, 0, urtwn_calib_cb); 2496} 2497 2498static void 2499urtwn_calib_cb(struct urtwn_softc *sc, union sec_param *data) 2500{ 2501 /* Do temperature compensation. */ 2502 urtwn_temp_calib(sc); 2503 2504 if ((urtwn_read_1(sc, R92C_MSR) & R92C_MSR_MASK) != R92C_MSR_NOLINK) 2505 callout_reset(&sc->sc_calib_to, 2*hz, urtwn_calib_to, sc); 2506} 2507 2508static void 2509urtwn_watchdog(void *arg) 2510{ 2511 struct urtwn_softc *sc = arg; 2512 2513 if (sc->sc_txtimer > 0) { 2514 if (--sc->sc_txtimer == 0) { 2515 device_printf(sc->sc_dev, "device timeout\n"); 2516 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2517 return; 2518 } 2519 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2520 } 2521} 2522 2523static void 2524urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2525{ 2526 int pwdb; 2527 2528 /* Convert antenna signal to percentage. */ 2529 if (rssi <= -100 || rssi >= 20) 2530 pwdb = 0; 2531 else if (rssi >= 0) 2532 pwdb = 100; 2533 else 2534 pwdb = 100 + rssi; 2535 if (!(sc->chip & URTWN_CHIP_88E)) { 2536 if (rate <= URTWN_RIDX_CCK11) { 2537 /* CCK gain is smaller than OFDM/MCS gain. */ 2538 pwdb += 6; 2539 if (pwdb > 100) 2540 pwdb = 100; 2541 if (pwdb <= 14) 2542 pwdb -= 4; 2543 else if (pwdb <= 26) 2544 pwdb -= 8; 2545 else if (pwdb <= 34) 2546 pwdb -= 6; 2547 else if (pwdb <= 42) 2548 pwdb -= 2; 2549 } 2550 } 2551 if (sc->avg_pwdb == -1) /* Init. */ 2552 sc->avg_pwdb = pwdb; 2553 else if (sc->avg_pwdb < pwdb) 2554 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2555 else 2556 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2557 URTWN_DPRINTF(sc, URTWN_DEBUG_RA, "%s: PWDB %d, EMA %d\n", __func__, 2558 pwdb, sc->avg_pwdb); 2559} 2560 2561static int8_t 2562urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2563{ 2564 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2565 struct r92c_rx_phystat *phy; 2566 struct r92c_rx_cck *cck; 2567 uint8_t rpt; 2568 int8_t rssi; 2569 2570 if (rate <= URTWN_RIDX_CCK11) { 2571 cck = (struct r92c_rx_cck *)physt; 2572 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2573 rpt = (cck->agc_rpt >> 5) & 0x3; 2574 rssi = (cck->agc_rpt & 0x1f) << 1; 2575 } else { 2576 rpt = (cck->agc_rpt >> 6) & 0x3; 2577 rssi = cck->agc_rpt & 0x3e; 2578 } 2579 rssi = cckoff[rpt] - rssi; 2580 } else { /* OFDM/HT. */ 2581 phy = (struct r92c_rx_phystat *)physt; 2582 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2583 } 2584 return (rssi); 2585} 2586 2587static int8_t 2588urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2589{ 2590 struct r92c_rx_phystat *phy; 2591 struct r88e_rx_cck *cck; 2592 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2593 int8_t rssi; 2594 2595 rssi = 0; 2596 if (rate <= URTWN_RIDX_CCK11) { 2597 cck = (struct r88e_rx_cck *)physt; 2598 cck_agc_rpt = cck->agc_rpt; 2599 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2600 vga_idx = cck_agc_rpt & 0x1f; 2601 switch (lna_idx) { 2602 case 7: 2603 if (vga_idx <= 27) 2604 rssi = -100 + 2* (27 - vga_idx); 2605 else 2606 rssi = -100; 2607 break; 2608 case 6: 2609 rssi = -48 + 2 * (2 - vga_idx); 2610 break; 2611 case 5: 2612 rssi = -42 + 2 * (7 - vga_idx); 2613 break; 2614 case 4: 2615 rssi = -36 + 2 * (7 - vga_idx); 2616 break; 2617 case 3: 2618 rssi = -24 + 2 * (7 - vga_idx); 2619 break; 2620 case 2: 2621 rssi = -12 + 2 * (5 - vga_idx); 2622 break; 2623 case 1: 2624 rssi = 8 - (2 * vga_idx); 2625 break; 2626 case 0: 2627 rssi = 14 - (2 * vga_idx); 2628 break; 2629 } 2630 rssi += 6; 2631 } else { /* OFDM/HT. */ 2632 phy = (struct r92c_rx_phystat *)physt; 2633 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2634 } 2635 return (rssi); 2636} 2637 2638static __inline uint8_t 2639rate2ridx(uint8_t rate) 2640{ 2641 switch (rate) { 2642 case 12: return 4; 2643 case 18: return 5; 2644 case 24: return 6; 2645 case 36: return 7; 2646 case 48: return 8; 2647 case 72: return 9; 2648 case 96: return 10; 2649 case 108: return 11; 2650 case 2: return 0; 2651 case 4: return 1; 2652 case 11: return 2; 2653 case 22: return 3; 2654 default: return 0; 2655 } 2656} 2657 2658static int 2659urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2660 struct mbuf *m, struct urtwn_data *data) 2661{ 2662 const struct ieee80211_txparam *tp; 2663 struct ieee80211com *ic = &sc->sc_ic; 2664 struct ieee80211vap *vap = ni->ni_vap; 2665 struct ieee80211_key *k = NULL; 2666 struct ieee80211_channel *chan; 2667 struct ieee80211_frame *wh; 2668 struct r92c_tx_desc *txd; 2669 uint8_t macid, raid, rate, ridx, subtype, type, tid, qsel; 2670 int hasqos, ismcast; 2671 2672 URTWN_ASSERT_LOCKED(sc); 2673 2674 /* 2675 * Software crypto. 2676 */ 2677 wh = mtod(m, struct ieee80211_frame *); 2678 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2679 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2680 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2681 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2682 2683 /* Select TX ring for this frame. */ 2684 if (hasqos) { 2685 tid = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2686 tid &= IEEE80211_QOS_TID; 2687 } else 2688 tid = 0; 2689 2690 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2691 ni->ni_chan : ic->ic_curchan; 2692 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2693 2694 /* Choose a TX rate index. */ 2695 if (type == IEEE80211_FC0_TYPE_MGT) 2696 rate = tp->mgmtrate; 2697 else if (ismcast) 2698 rate = tp->mcastrate; 2699 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2700 rate = tp->ucastrate; 2701 else if (m->m_flags & M_EAPOL) 2702 rate = tp->mgmtrate; 2703 else { 2704 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2705 /* XXX pass pktlen */ 2706 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2707 rate = ni->ni_txrate; 2708 } else { 2709 if (ic->ic_curmode != IEEE80211_MODE_11B) 2710 rate = 108; 2711 else 2712 rate = 22; 2713 } 2714 } 2715 2716 ridx = rate2ridx(rate); 2717 if (ic->ic_curmode != IEEE80211_MODE_11B) 2718 raid = R92C_RAID_11BG; 2719 else 2720 raid = R92C_RAID_11B; 2721 2722 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2723 k = ieee80211_crypto_encap(ni, m); 2724 if (k == NULL) { 2725 device_printf(sc->sc_dev, 2726 "ieee80211_crypto_encap returns NULL.\n"); 2727 return (ENOBUFS); 2728 } 2729 2730 /* in case packet header moved, reset pointer */ 2731 wh = mtod(m, struct ieee80211_frame *); 2732 } 2733 2734 /* Fill Tx descriptor. */ 2735 txd = (struct r92c_tx_desc *)data->buf; 2736 memset(txd, 0, sizeof(*txd)); 2737 2738 txd->txdw0 |= htole32( 2739 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2740 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2741 if (ismcast) 2742 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2743 2744 if (!ismcast) { 2745 if (sc->chip & URTWN_CHIP_88E) { 2746 struct urtwn_node *un = URTWN_NODE(ni); 2747 macid = un->id; 2748 } else 2749 macid = URTWN_MACID_BSS; 2750 2751 if (type == IEEE80211_FC0_TYPE_DATA) { 2752 qsel = tid % URTWN_MAX_TID; 2753 2754 if (sc->chip & URTWN_CHIP_88E) { 2755 txd->txdw2 |= htole32( 2756 R88E_TXDW2_AGGBK | 2757 R88E_TXDW2_CCX_RPT); 2758 } else 2759 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2760 2761 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2762 switch (ic->ic_protmode) { 2763 case IEEE80211_PROT_CTSONLY: 2764 txd->txdw4 |= htole32( 2765 R92C_TXDW4_CTS2SELF | 2766 R92C_TXDW4_HWRTSEN); 2767 break; 2768 case IEEE80211_PROT_RTSCTS: 2769 txd->txdw4 |= htole32( 2770 R92C_TXDW4_RTSEN | 2771 R92C_TXDW4_HWRTSEN); 2772 break; 2773 default: 2774 break; 2775 } 2776 } 2777 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2778 URTWN_RIDX_OFDM24)); 2779 txd->txdw5 |= htole32(0x0001ff00); 2780 } else /* IEEE80211_FC0_TYPE_MGT */ 2781 qsel = R92C_TXDW1_QSEL_MGNT; 2782 } else { 2783 macid = URTWN_MACID_BC; 2784 qsel = R92C_TXDW1_QSEL_MGNT; 2785 } 2786 2787 txd->txdw1 |= htole32( 2788 SM(R92C_TXDW1_QSEL, qsel) | 2789 SM(R92C_TXDW1_RAID, raid)); 2790 2791 if (sc->chip & URTWN_CHIP_88E) 2792 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 2793 else 2794 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 2795 2796 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2797 /* Force this rate if needed. */ 2798 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 2799 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 2800 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2801 2802 if (!hasqos) { 2803 /* Use HW sequence numbering for non-QoS frames. */ 2804 if (sc->chip & URTWN_CHIP_88E) 2805 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2806 else 2807 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2808 } else { 2809 /* Set sequence number. */ 2810 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2811 } 2812 2813 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2814 uint8_t cipher; 2815 2816 switch (k->wk_cipher->ic_cipher) { 2817 case IEEE80211_CIPHER_WEP: 2818 case IEEE80211_CIPHER_TKIP: 2819 cipher = R92C_TXDW1_CIPHER_RC4; 2820 break; 2821 case IEEE80211_CIPHER_AES_CCM: 2822 cipher = R92C_TXDW1_CIPHER_AES; 2823 break; 2824 default: 2825 device_printf(sc->sc_dev, "%s: unknown cipher %d\n", 2826 __func__, k->wk_cipher->ic_cipher); 2827 return (EINVAL); 2828 } 2829 2830 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 2831 } 2832 2833 if (ieee80211_radiotap_active_vap(vap)) { 2834 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2835 2836 tap->wt_flags = 0; 2837 if (k != NULL) 2838 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2839 ieee80211_radiotap_tx(vap, m); 2840 } 2841 2842 data->ni = ni; 2843 2844 urtwn_tx_start(sc, m, type, data); 2845 2846 return (0); 2847} 2848 2849static int 2850urtwn_tx_raw(struct urtwn_softc *sc, struct ieee80211_node *ni, 2851 struct mbuf *m, struct urtwn_data *data, 2852 const struct ieee80211_bpf_params *params) 2853{ 2854 struct ieee80211vap *vap = ni->ni_vap; 2855 struct ieee80211_key *k = NULL; 2856 struct ieee80211_frame *wh; 2857 struct r92c_tx_desc *txd; 2858 uint8_t cipher, ridx, type; 2859 2860 /* Encrypt the frame if need be. */ 2861 cipher = R92C_TXDW1_CIPHER_NONE; 2862 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 2863 /* Retrieve key for TX. */ 2864 k = ieee80211_crypto_encap(ni, m); 2865 if (k == NULL) 2866 return (ENOBUFS); 2867 2868 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2869 switch (k->wk_cipher->ic_cipher) { 2870 case IEEE80211_CIPHER_WEP: 2871 case IEEE80211_CIPHER_TKIP: 2872 cipher = R92C_TXDW1_CIPHER_RC4; 2873 break; 2874 case IEEE80211_CIPHER_AES_CCM: 2875 cipher = R92C_TXDW1_CIPHER_AES; 2876 break; 2877 default: 2878 device_printf(sc->sc_dev, 2879 "%s: unknown cipher %d\n", 2880 __func__, k->wk_cipher->ic_cipher); 2881 return (EINVAL); 2882 } 2883 } 2884 } 2885 2886 wh = mtod(m, struct ieee80211_frame *); 2887 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2888 2889 /* Fill Tx descriptor. */ 2890 txd = (struct r92c_tx_desc *)data->buf; 2891 memset(txd, 0, sizeof(*txd)); 2892 2893 txd->txdw0 |= htole32( 2894 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2895 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2896 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2897 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2898 2899 if (params->ibp_flags & IEEE80211_BPF_RTS) 2900 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN); 2901 if (params->ibp_flags & IEEE80211_BPF_CTS) 2902 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF); 2903 if (txd->txdw4 & htole32(R92C_TXDW4_RTSEN | R92C_TXDW4_CTS2SELF)) { 2904 txd->txdw4 |= htole32(R92C_TXDW4_HWRTSEN); 2905 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2906 URTWN_RIDX_OFDM24)); 2907 } 2908 2909 if (sc->chip & URTWN_CHIP_88E) 2910 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 2911 else 2912 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 2913 2914 txd->txdw1 |= htole32(SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT)); 2915 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 2916 2917 /* Choose a TX rate index. */ 2918 ridx = rate2ridx(params->ibp_rate0); 2919 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2920 txd->txdw5 |= htole32(0x0001ff00); 2921 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2922 2923 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 2924 /* Use HW sequence numbering for non-QoS frames. */ 2925 if (sc->chip & URTWN_CHIP_88E) 2926 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2927 else 2928 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2929 } else { 2930 /* Set sequence number. */ 2931 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2932 } 2933 2934 if (ieee80211_radiotap_active_vap(vap)) { 2935 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2936 2937 tap->wt_flags = 0; 2938 if (k != NULL) 2939 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2940 ieee80211_radiotap_tx(vap, m); 2941 } 2942 2943 data->ni = ni; 2944 2945 urtwn_tx_start(sc, m, type, data); 2946 2947 return (0); 2948} 2949 2950static void 2951urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 2952 struct urtwn_data *data) 2953{ 2954 struct usb_xfer *xfer; 2955 struct r92c_tx_desc *txd; 2956 uint16_t ac, sum; 2957 int i, xferlen; 2958 2959 URTWN_ASSERT_LOCKED(sc); 2960 2961 ac = M_WME_GETAC(m); 2962 2963 switch (type) { 2964 case IEEE80211_FC0_TYPE_CTL: 2965 case IEEE80211_FC0_TYPE_MGT: 2966 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 2967 break; 2968 default: 2969 xfer = sc->sc_xfer[wme2queue[ac].qid]; 2970 break; 2971 } 2972 2973 txd = (struct r92c_tx_desc *)data->buf; 2974 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 2975 2976 /* Compute Tx descriptor checksum. */ 2977 sum = 0; 2978 for (i = 0; i < sizeof(*txd) / 2; i++) 2979 sum ^= ((uint16_t *)txd)[i]; 2980 txd->txdsum = sum; /* NB: already little endian. */ 2981 2982 xferlen = sizeof(*txd) + m->m_pkthdr.len; 2983 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 2984 2985 data->buflen = xferlen; 2986 data->m = m; 2987 2988 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 2989 usbd_transfer_start(xfer); 2990} 2991 2992static int 2993urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 2994{ 2995 struct urtwn_softc *sc = ic->ic_softc; 2996 int error; 2997 2998 URTWN_LOCK(sc); 2999 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 3000 URTWN_UNLOCK(sc); 3001 return (ENXIO); 3002 } 3003 error = mbufq_enqueue(&sc->sc_snd, m); 3004 if (error) { 3005 URTWN_UNLOCK(sc); 3006 return (error); 3007 } 3008 urtwn_start(sc); 3009 URTWN_UNLOCK(sc); 3010 3011 return (0); 3012} 3013 3014static void 3015urtwn_start(struct urtwn_softc *sc) 3016{ 3017 struct ieee80211_node *ni; 3018 struct mbuf *m; 3019 struct urtwn_data *bf; 3020 3021 URTWN_ASSERT_LOCKED(sc); 3022 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 3023 bf = urtwn_getbuf(sc); 3024 if (bf == NULL) { 3025 mbufq_prepend(&sc->sc_snd, m); 3026 break; 3027 } 3028 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 3029 m->m_pkthdr.rcvif = NULL; 3030 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 3031 if_inc_counter(ni->ni_vap->iv_ifp, 3032 IFCOUNTER_OERRORS, 1); 3033 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3034 m_freem(m); 3035 ieee80211_free_node(ni); 3036 break; 3037 } 3038 sc->sc_txtimer = 5; 3039 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3040 } 3041} 3042 3043static void 3044urtwn_parent(struct ieee80211com *ic) 3045{ 3046 struct urtwn_softc *sc = ic->ic_softc; 3047 3048 URTWN_LOCK(sc); 3049 if (sc->sc_flags & URTWN_DETACHED) { 3050 URTWN_UNLOCK(sc); 3051 return; 3052 } 3053 URTWN_UNLOCK(sc); 3054 3055 if (ic->ic_nrunning > 0) { 3056 if (urtwn_init(sc) != 0) { 3057 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3058 if (vap != NULL) 3059 ieee80211_stop(vap); 3060 } else 3061 ieee80211_start_all(ic); 3062 } else 3063 urtwn_stop(sc); 3064} 3065 3066static __inline int 3067urtwn_power_on(struct urtwn_softc *sc) 3068{ 3069 3070 return sc->sc_power_on(sc); 3071} 3072 3073static int 3074urtwn_r92c_power_on(struct urtwn_softc *sc) 3075{ 3076 uint32_t reg; 3077 usb_error_t error; 3078 int ntries; 3079 3080 /* Wait for autoload done bit. */ 3081 for (ntries = 0; ntries < 1000; ntries++) { 3082 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3083 break; 3084 urtwn_ms_delay(sc); 3085 } 3086 if (ntries == 1000) { 3087 device_printf(sc->sc_dev, 3088 "timeout waiting for chip autoload\n"); 3089 return (ETIMEDOUT); 3090 } 3091 3092 /* Unlock ISO/CLK/Power control register. */ 3093 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3094 if (error != USB_ERR_NORMAL_COMPLETION) 3095 return (EIO); 3096 /* Move SPS into PWM mode. */ 3097 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3098 if (error != USB_ERR_NORMAL_COMPLETION) 3099 return (EIO); 3100 urtwn_ms_delay(sc); 3101 3102 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3103 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3104 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3105 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3106 if (error != USB_ERR_NORMAL_COMPLETION) 3107 return (EIO); 3108 urtwn_ms_delay(sc); 3109 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3110 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3111 ~R92C_SYS_ISO_CTRL_MD2PP); 3112 if (error != USB_ERR_NORMAL_COMPLETION) 3113 return (EIO); 3114 } 3115 3116 /* Auto enable WLAN. */ 3117 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3118 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3119 if (error != USB_ERR_NORMAL_COMPLETION) 3120 return (EIO); 3121 for (ntries = 0; ntries < 1000; ntries++) { 3122 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3123 R92C_APS_FSMCO_APFM_ONMAC)) 3124 break; 3125 urtwn_ms_delay(sc); 3126 } 3127 if (ntries == 1000) { 3128 device_printf(sc->sc_dev, 3129 "timeout waiting for MAC auto ON\n"); 3130 return (ETIMEDOUT); 3131 } 3132 3133 /* Enable radio, GPIO and LED functions. */ 3134 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3135 R92C_APS_FSMCO_AFSM_HSUS | 3136 R92C_APS_FSMCO_PDN_EN | 3137 R92C_APS_FSMCO_PFM_ALDN); 3138 if (error != USB_ERR_NORMAL_COMPLETION) 3139 return (EIO); 3140 /* Release RF digital isolation. */ 3141 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3142 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3143 if (error != USB_ERR_NORMAL_COMPLETION) 3144 return (EIO); 3145 3146 /* Initialize MAC. */ 3147 error = urtwn_write_1(sc, R92C_APSD_CTRL, 3148 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3149 if (error != USB_ERR_NORMAL_COMPLETION) 3150 return (EIO); 3151 for (ntries = 0; ntries < 200; ntries++) { 3152 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3153 R92C_APSD_CTRL_OFF_STATUS)) 3154 break; 3155 urtwn_ms_delay(sc); 3156 } 3157 if (ntries == 200) { 3158 device_printf(sc->sc_dev, 3159 "timeout waiting for MAC initialization\n"); 3160 return (ETIMEDOUT); 3161 } 3162 3163 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3164 reg = urtwn_read_2(sc, R92C_CR); 3165 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3166 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3167 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3168 R92C_CR_ENSEC; 3169 error = urtwn_write_2(sc, R92C_CR, reg); 3170 if (error != USB_ERR_NORMAL_COMPLETION) 3171 return (EIO); 3172 3173 error = urtwn_write_1(sc, 0xfe10, 0x19); 3174 if (error != USB_ERR_NORMAL_COMPLETION) 3175 return (EIO); 3176 return (0); 3177} 3178 3179static int 3180urtwn_r88e_power_on(struct urtwn_softc *sc) 3181{ 3182 uint32_t reg; 3183 usb_error_t error; 3184 int ntries; 3185 3186 /* Wait for power ready bit. */ 3187 for (ntries = 0; ntries < 5000; ntries++) { 3188 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 3189 break; 3190 urtwn_ms_delay(sc); 3191 } 3192 if (ntries == 5000) { 3193 device_printf(sc->sc_dev, 3194 "timeout waiting for chip power up\n"); 3195 return (ETIMEDOUT); 3196 } 3197 3198 /* Reset BB. */ 3199 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3200 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3201 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3202 if (error != USB_ERR_NORMAL_COMPLETION) 3203 return (EIO); 3204 3205 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 3206 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 3207 if (error != USB_ERR_NORMAL_COMPLETION) 3208 return (EIO); 3209 3210 /* Disable HWPDN. */ 3211 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3212 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3213 if (error != USB_ERR_NORMAL_COMPLETION) 3214 return (EIO); 3215 3216 /* Disable WL suspend. */ 3217 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3218 urtwn_read_2(sc, R92C_APS_FSMCO) & 3219 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 3220 if (error != USB_ERR_NORMAL_COMPLETION) 3221 return (EIO); 3222 3223 error = urtwn_write_2(sc, R92C_APS_FSMCO, 3224 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3225 if (error != USB_ERR_NORMAL_COMPLETION) 3226 return (EIO); 3227 for (ntries = 0; ntries < 5000; ntries++) { 3228 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3229 R92C_APS_FSMCO_APFM_ONMAC)) 3230 break; 3231 urtwn_ms_delay(sc); 3232 } 3233 if (ntries == 5000) 3234 return (ETIMEDOUT); 3235 3236 /* Enable LDO normal mode. */ 3237 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 3238 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 3239 if (error != USB_ERR_NORMAL_COMPLETION) 3240 return (EIO); 3241 3242 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3243 error = urtwn_write_2(sc, R92C_CR, 0); 3244 if (error != USB_ERR_NORMAL_COMPLETION) 3245 return (EIO); 3246 reg = urtwn_read_2(sc, R92C_CR); 3247 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3248 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3249 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3250 error = urtwn_write_2(sc, R92C_CR, reg); 3251 if (error != USB_ERR_NORMAL_COMPLETION) 3252 return (EIO); 3253 3254 return (0); 3255} 3256 3257static int 3258urtwn_llt_init(struct urtwn_softc *sc) 3259{ 3260 int i, error, page_count, pktbuf_count; 3261 3262 page_count = (sc->chip & URTWN_CHIP_88E) ? 3263 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 3264 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 3265 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 3266 3267 /* Reserve pages [0; page_count]. */ 3268 for (i = 0; i < page_count; i++) { 3269 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3270 return (error); 3271 } 3272 /* NB: 0xff indicates end-of-list. */ 3273 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3274 return (error); 3275 /* 3276 * Use pages [page_count + 1; pktbuf_count - 1] 3277 * as ring buffer. 3278 */ 3279 for (++i; i < pktbuf_count - 1; i++) { 3280 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3281 return (error); 3282 } 3283 /* Make the last page point to the beginning of the ring buffer. */ 3284 error = urtwn_llt_write(sc, i, page_count + 1); 3285 return (error); 3286} 3287 3288#ifndef URTWN_WITHOUT_UCODE 3289static void 3290urtwn_fw_reset(struct urtwn_softc *sc) 3291{ 3292 uint16_t reg; 3293 int ntries; 3294 3295 /* Tell 8051 to reset itself. */ 3296 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3297 3298 /* Wait until 8051 resets by itself. */ 3299 for (ntries = 0; ntries < 100; ntries++) { 3300 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3301 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3302 return; 3303 urtwn_ms_delay(sc); 3304 } 3305 /* Force 8051 reset. */ 3306 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3307} 3308 3309static void 3310urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3311{ 3312 uint16_t reg; 3313 3314 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3315 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3316 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3317} 3318 3319static int 3320urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 3321{ 3322 uint32_t reg; 3323 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 3324 int off, mlen; 3325 3326 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3327 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3328 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3329 3330 off = R92C_FW_START_ADDR; 3331 while (len > 0) { 3332 if (len > 196) 3333 mlen = 196; 3334 else if (len > 4) 3335 mlen = 4; 3336 else 3337 mlen = 1; 3338 /* XXX fix this deconst */ 3339 error = urtwn_write_region_1(sc, off, 3340 __DECONST(uint8_t *, buf), mlen); 3341 if (error != USB_ERR_NORMAL_COMPLETION) 3342 break; 3343 off += mlen; 3344 buf += mlen; 3345 len -= mlen; 3346 } 3347 return (error); 3348} 3349 3350static int 3351urtwn_load_firmware(struct urtwn_softc *sc) 3352{ 3353 const struct firmware *fw; 3354 const struct r92c_fw_hdr *hdr; 3355 const char *imagename; 3356 const u_char *ptr; 3357 size_t len; 3358 uint32_t reg; 3359 int mlen, ntries, page, error; 3360 3361 URTWN_UNLOCK(sc); 3362 /* Read firmware image from the filesystem. */ 3363 if (sc->chip & URTWN_CHIP_88E) 3364 imagename = "urtwn-rtl8188eufw"; 3365 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3366 URTWN_CHIP_UMC_A_CUT) 3367 imagename = "urtwn-rtl8192cfwU"; 3368 else 3369 imagename = "urtwn-rtl8192cfwT"; 3370 3371 fw = firmware_get(imagename); 3372 URTWN_LOCK(sc); 3373 if (fw == NULL) { 3374 device_printf(sc->sc_dev, 3375 "failed loadfirmware of file %s\n", imagename); 3376 return (ENOENT); 3377 } 3378 3379 len = fw->datasize; 3380 3381 if (len < sizeof(*hdr)) { 3382 device_printf(sc->sc_dev, "firmware too short\n"); 3383 error = EINVAL; 3384 goto fail; 3385 } 3386 ptr = fw->data; 3387 hdr = (const struct r92c_fw_hdr *)ptr; 3388 /* Check if there is a valid FW header and skip it. */ 3389 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3390 (le16toh(hdr->signature) >> 4) == 0x88e || 3391 (le16toh(hdr->signature) >> 4) == 0x92c) { 3392 URTWN_DPRINTF(sc, URTWN_DEBUG_FIRMWARE, 3393 "FW V%d.%d %02d-%02d %02d:%02d\n", 3394 le16toh(hdr->version), le16toh(hdr->subversion), 3395 hdr->month, hdr->date, hdr->hour, hdr->minute); 3396 ptr += sizeof(*hdr); 3397 len -= sizeof(*hdr); 3398 } 3399 3400 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3401 if (sc->chip & URTWN_CHIP_88E) 3402 urtwn_r88e_fw_reset(sc); 3403 else 3404 urtwn_fw_reset(sc); 3405 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3406 } 3407 3408 if (!(sc->chip & URTWN_CHIP_88E)) { 3409 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3410 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3411 R92C_SYS_FUNC_EN_CPUEN); 3412 } 3413 urtwn_write_1(sc, R92C_MCUFWDL, 3414 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3415 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3416 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3417 3418 /* Reset the FWDL checksum. */ 3419 urtwn_write_1(sc, R92C_MCUFWDL, 3420 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3421 3422 for (page = 0; len > 0; page++) { 3423 mlen = min(len, R92C_FW_PAGE_SIZE); 3424 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3425 if (error != 0) { 3426 device_printf(sc->sc_dev, 3427 "could not load firmware page\n"); 3428 goto fail; 3429 } 3430 ptr += mlen; 3431 len -= mlen; 3432 } 3433 urtwn_write_1(sc, R92C_MCUFWDL, 3434 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3435 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3436 3437 /* Wait for checksum report. */ 3438 for (ntries = 0; ntries < 1000; ntries++) { 3439 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3440 break; 3441 urtwn_ms_delay(sc); 3442 } 3443 if (ntries == 1000) { 3444 device_printf(sc->sc_dev, 3445 "timeout waiting for checksum report\n"); 3446 error = ETIMEDOUT; 3447 goto fail; 3448 } 3449 3450 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3451 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3452 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3453 if (sc->chip & URTWN_CHIP_88E) 3454 urtwn_r88e_fw_reset(sc); 3455 /* Wait for firmware readiness. */ 3456 for (ntries = 0; ntries < 1000; ntries++) { 3457 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3458 break; 3459 urtwn_ms_delay(sc); 3460 } 3461 if (ntries == 1000) { 3462 device_printf(sc->sc_dev, 3463 "timeout waiting for firmware readiness\n"); 3464 error = ETIMEDOUT; 3465 goto fail; 3466 } 3467fail: 3468 firmware_put(fw, FIRMWARE_UNLOAD); 3469 return (error); 3470} 3471#endif 3472 3473static int 3474urtwn_dma_init(struct urtwn_softc *sc) 3475{ 3476 struct usb_endpoint *ep, *ep_end; 3477 usb_error_t usb_err; 3478 uint32_t reg; 3479 int hashq, hasnq, haslq, nqueues, ntx; 3480 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 3481 3482 /* Initialize LLT table. */ 3483 error = urtwn_llt_init(sc); 3484 if (error != 0) 3485 return (error); 3486 3487 /* Determine the number of bulk-out pipes. */ 3488 ntx = 0; 3489 ep = sc->sc_udev->endpoints; 3490 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 3491 for (; ep != ep_end; ep++) { 3492 if ((ep->edesc == NULL) || 3493 (ep->iface_index != sc->sc_iface_index)) 3494 continue; 3495 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 3496 ntx++; 3497 } 3498 if (ntx == 0) { 3499 device_printf(sc->sc_dev, 3500 "%d: invalid number of Tx bulk pipes\n", ntx); 3501 return (EIO); 3502 } 3503 3504 /* Get Tx queues to USB endpoints mapping. */ 3505 hashq = hasnq = haslq = nqueues = 0; 3506 switch (ntx) { 3507 case 1: hashq = 1; break; 3508 case 2: hashq = hasnq = 1; break; 3509 case 3: case 4: hashq = hasnq = haslq = 1; break; 3510 } 3511 nqueues = hashq + hasnq + haslq; 3512 if (nqueues == 0) 3513 return (EIO); 3514 3515 npubqpages = nqpages = nrempages = pagecount = 0; 3516 if (sc->chip & URTWN_CHIP_88E) 3517 tx_boundary = R88E_TX_PAGE_BOUNDARY; 3518 else { 3519 pagecount = R92C_TX_PAGE_COUNT; 3520 npubqpages = R92C_PUBQ_NPAGES; 3521 tx_boundary = R92C_TX_PAGE_BOUNDARY; 3522 } 3523 3524 /* Set number of pages for normal priority queue. */ 3525 if (sc->chip & URTWN_CHIP_88E) { 3526 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 3527 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3528 return (EIO); 3529 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3530 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3531 return (EIO); 3532 } else { 3533 /* Get the number of pages for each queue. */ 3534 nqpages = (pagecount - npubqpages) / nqueues; 3535 /* 3536 * The remaining pages are assigned to the high priority 3537 * queue. 3538 */ 3539 nrempages = (pagecount - npubqpages) % nqueues; 3540 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3541 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3542 return (EIO); 3543 usb_err = urtwn_write_4(sc, R92C_RQPN, 3544 /* Set number of pages for public queue. */ 3545 SM(R92C_RQPN_PUBQ, npubqpages) | 3546 /* Set number of pages for high priority queue. */ 3547 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3548 /* Set number of pages for low priority queue. */ 3549 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3550 /* Load values. */ 3551 R92C_RQPN_LD); 3552 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3553 return (EIO); 3554 } 3555 3556 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 3557 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3558 return (EIO); 3559 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 3560 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3561 return (EIO); 3562 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 3563 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3564 return (EIO); 3565 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 3566 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3567 return (EIO); 3568 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 3569 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3570 return (EIO); 3571 3572 /* Set queue to USB pipe mapping. */ 3573 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3574 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3575 if (nqueues == 1) { 3576 if (hashq) 3577 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3578 else if (hasnq) 3579 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3580 else 3581 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3582 } else if (nqueues == 2) { 3583 /* 3584 * All 2-endpoints configs have high and normal 3585 * priority queues. 3586 */ 3587 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3588 } else 3589 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3590 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3591 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3592 return (EIO); 3593 3594 /* Set Tx/Rx transfer page boundary. */ 3595 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 3596 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 3597 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3598 return (EIO); 3599 3600 /* Set Tx/Rx transfer page size. */ 3601 usb_err = urtwn_write_1(sc, R92C_PBP, 3602 SM(R92C_PBP_PSRX, R92C_PBP_128) | 3603 SM(R92C_PBP_PSTX, R92C_PBP_128)); 3604 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3605 return (EIO); 3606 3607 return (0); 3608} 3609 3610static int 3611urtwn_mac_init(struct urtwn_softc *sc) 3612{ 3613 usb_error_t error; 3614 int i; 3615 3616 /* Write MAC initialization values. */ 3617 if (sc->chip & URTWN_CHIP_88E) { 3618 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 3619 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3620 rtl8188eu_mac[i].val); 3621 if (error != USB_ERR_NORMAL_COMPLETION) 3622 return (EIO); 3623 } 3624 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 3625 } else { 3626 for (i = 0; i < nitems(rtl8192cu_mac); i++) 3627 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3628 rtl8192cu_mac[i].val); 3629 if (error != USB_ERR_NORMAL_COMPLETION) 3630 return (EIO); 3631 } 3632 3633 return (0); 3634} 3635 3636static void 3637urtwn_bb_init(struct urtwn_softc *sc) 3638{ 3639 const struct urtwn_bb_prog *prog; 3640 uint32_t reg; 3641 uint8_t crystalcap; 3642 int i; 3643 3644 /* Enable BB and RF. */ 3645 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3646 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3647 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3648 R92C_SYS_FUNC_EN_DIO_RF); 3649 3650 if (!(sc->chip & URTWN_CHIP_88E)) 3651 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 3652 3653 urtwn_write_1(sc, R92C_RF_CTRL, 3654 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3655 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3656 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3657 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3658 3659 if (!(sc->chip & URTWN_CHIP_88E)) { 3660 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3661 urtwn_write_1(sc, 0x15, 0xe9); 3662 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3663 } 3664 3665 /* Select BB programming based on board type. */ 3666 if (sc->chip & URTWN_CHIP_88E) 3667 prog = &rtl8188eu_bb_prog; 3668 else if (!(sc->chip & URTWN_CHIP_92C)) { 3669 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3670 prog = &rtl8188ce_bb_prog; 3671 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3672 prog = &rtl8188ru_bb_prog; 3673 else 3674 prog = &rtl8188cu_bb_prog; 3675 } else { 3676 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3677 prog = &rtl8192ce_bb_prog; 3678 else 3679 prog = &rtl8192cu_bb_prog; 3680 } 3681 /* Write BB initialization values. */ 3682 for (i = 0; i < prog->count; i++) { 3683 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3684 urtwn_ms_delay(sc); 3685 } 3686 3687 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3688 /* 8192C 1T only configuration. */ 3689 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3690 reg = (reg & ~0x00000003) | 0x2; 3691 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3692 3693 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3694 reg = (reg & ~0x00300033) | 0x00200022; 3695 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3696 3697 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3698 reg = (reg & ~0xff000000) | 0x45 << 24; 3699 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3700 3701 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3702 reg = (reg & ~0x000000ff) | 0x23; 3703 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3704 3705 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3706 reg = (reg & ~0x00000030) | 1 << 4; 3707 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3708 3709 reg = urtwn_bb_read(sc, 0xe74); 3710 reg = (reg & ~0x0c000000) | 2 << 26; 3711 urtwn_bb_write(sc, 0xe74, reg); 3712 reg = urtwn_bb_read(sc, 0xe78); 3713 reg = (reg & ~0x0c000000) | 2 << 26; 3714 urtwn_bb_write(sc, 0xe78, reg); 3715 reg = urtwn_bb_read(sc, 0xe7c); 3716 reg = (reg & ~0x0c000000) | 2 << 26; 3717 urtwn_bb_write(sc, 0xe7c, reg); 3718 reg = urtwn_bb_read(sc, 0xe80); 3719 reg = (reg & ~0x0c000000) | 2 << 26; 3720 urtwn_bb_write(sc, 0xe80, reg); 3721 reg = urtwn_bb_read(sc, 0xe88); 3722 reg = (reg & ~0x0c000000) | 2 << 26; 3723 urtwn_bb_write(sc, 0xe88, reg); 3724 } 3725 3726 /* Write AGC values. */ 3727 for (i = 0; i < prog->agccount; i++) { 3728 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 3729 prog->agcvals[i]); 3730 urtwn_ms_delay(sc); 3731 } 3732 3733 if (sc->chip & URTWN_CHIP_88E) { 3734 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3735 urtwn_ms_delay(sc); 3736 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3737 urtwn_ms_delay(sc); 3738 3739 crystalcap = sc->rom.r88e_rom.crystalcap; 3740 if (crystalcap == 0xff) 3741 crystalcap = 0x20; 3742 crystalcap &= 0x3f; 3743 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3744 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3745 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3746 crystalcap | crystalcap << 6)); 3747 } else { 3748 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3749 R92C_HSSI_PARAM2_CCK_HIPWR) 3750 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 3751 } 3752} 3753 3754static void 3755urtwn_rf_init(struct urtwn_softc *sc) 3756{ 3757 const struct urtwn_rf_prog *prog; 3758 uint32_t reg, type; 3759 int i, j, idx, off; 3760 3761 /* Select RF programming based on board type. */ 3762 if (sc->chip & URTWN_CHIP_88E) 3763 prog = rtl8188eu_rf_prog; 3764 else if (!(sc->chip & URTWN_CHIP_92C)) { 3765 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3766 prog = rtl8188ce_rf_prog; 3767 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3768 prog = rtl8188ru_rf_prog; 3769 else 3770 prog = rtl8188cu_rf_prog; 3771 } else 3772 prog = rtl8192ce_rf_prog; 3773 3774 for (i = 0; i < sc->nrxchains; i++) { 3775 /* Save RF_ENV control type. */ 3776 idx = i / 2; 3777 off = (i % 2) * 16; 3778 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3779 type = (reg >> off) & 0x10; 3780 3781 /* Set RF_ENV enable. */ 3782 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3783 reg |= 0x100000; 3784 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3785 urtwn_ms_delay(sc); 3786 /* Set RF_ENV output high. */ 3787 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3788 reg |= 0x10; 3789 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3790 urtwn_ms_delay(sc); 3791 /* Set address and data lengths of RF registers. */ 3792 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3793 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3794 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3795 urtwn_ms_delay(sc); 3796 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3797 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3798 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3799 urtwn_ms_delay(sc); 3800 3801 /* Write RF initialization values for this chain. */ 3802 for (j = 0; j < prog[i].count; j++) { 3803 if (prog[i].regs[j] >= 0xf9 && 3804 prog[i].regs[j] <= 0xfe) { 3805 /* 3806 * These are fake RF registers offsets that 3807 * indicate a delay is required. 3808 */ 3809 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 3810 continue; 3811 } 3812 urtwn_rf_write(sc, i, prog[i].regs[j], 3813 prog[i].vals[j]); 3814 urtwn_ms_delay(sc); 3815 } 3816 3817 /* Restore RF_ENV control type. */ 3818 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3819 reg &= ~(0x10 << off) | (type << off); 3820 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 3821 3822 /* Cache RF register CHNLBW. */ 3823 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3824 } 3825 3826 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3827 URTWN_CHIP_UMC_A_CUT) { 3828 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3829 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3830 } 3831} 3832 3833static void 3834urtwn_cam_init(struct urtwn_softc *sc) 3835{ 3836 /* Invalidate all CAM entries. */ 3837 urtwn_write_4(sc, R92C_CAMCMD, 3838 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3839} 3840 3841static int 3842urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 3843{ 3844 usb_error_t error; 3845 3846 error = urtwn_write_4(sc, R92C_CAMWRITE, data); 3847 if (error != USB_ERR_NORMAL_COMPLETION) 3848 return (EIO); 3849 error = urtwn_write_4(sc, R92C_CAMCMD, 3850 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 3851 SM(R92C_CAMCMD_ADDR, addr)); 3852 if (error != USB_ERR_NORMAL_COMPLETION) 3853 return (EIO); 3854 3855 return (0); 3856} 3857 3858static void 3859urtwn_pa_bias_init(struct urtwn_softc *sc) 3860{ 3861 uint8_t reg; 3862 int i; 3863 3864 for (i = 0; i < sc->nrxchains; i++) { 3865 if (sc->pa_setting & (1 << i)) 3866 continue; 3867 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3868 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3869 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3870 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3871 } 3872 if (!(sc->pa_setting & 0x10)) { 3873 reg = urtwn_read_1(sc, 0x16); 3874 reg = (reg & ~0xf0) | 0x90; 3875 urtwn_write_1(sc, 0x16, reg); 3876 } 3877} 3878 3879static void 3880urtwn_rxfilter_init(struct urtwn_softc *sc) 3881{ 3882 struct ieee80211com *ic = &sc->sc_ic; 3883 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3884 uint32_t rcr; 3885 uint16_t filter; 3886 3887 URTWN_ASSERT_LOCKED(sc); 3888 3889 /* Accept all multicast frames. */ 3890 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3891 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3892 3893 /* Filter for management frames. */ 3894 filter = 0x7f3f; 3895 switch (vap->iv_opmode) { 3896 case IEEE80211_M_STA: 3897 filter &= ~( 3898 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 3899 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 3900 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 3901 break; 3902 case IEEE80211_M_HOSTAP: 3903 filter &= ~( 3904 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 3905 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP) | 3906 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_BEACON)); 3907 break; 3908 case IEEE80211_M_MONITOR: 3909 case IEEE80211_M_IBSS: 3910 break; 3911 default: 3912 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3913 __func__, vap->iv_opmode); 3914 break; 3915 } 3916 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 3917 3918 /* Reject all control frames. */ 3919 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3920 3921 /* Reject all data frames. */ 3922 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 3923 3924 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 3925 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 3926 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 3927 3928 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 3929 /* Accept all frames. */ 3930 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 3931 R92C_RCR_AAP; 3932 } 3933 3934 /* Set Rx filter. */ 3935 urtwn_write_4(sc, R92C_RCR, rcr); 3936 3937 if (ic->ic_promisc != 0) { 3938 /* Update Rx filter. */ 3939 urtwn_set_promisc(sc); 3940 } 3941} 3942 3943static void 3944urtwn_edca_init(struct urtwn_softc *sc) 3945{ 3946 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3947 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3948 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3949 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3950 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3951 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3952 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3953 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3954} 3955 3956static void 3957urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3958 uint16_t power[URTWN_RIDX_COUNT]) 3959{ 3960 uint32_t reg; 3961 3962 /* Write per-CCK rate Tx power. */ 3963 if (chain == 0) { 3964 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3965 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3966 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3967 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3968 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3969 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3970 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3971 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3972 } else { 3973 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3974 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3975 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3976 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3977 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3978 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3979 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3980 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3981 } 3982 /* Write per-OFDM rate Tx power. */ 3983 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3984 SM(R92C_TXAGC_RATE06, power[ 4]) | 3985 SM(R92C_TXAGC_RATE09, power[ 5]) | 3986 SM(R92C_TXAGC_RATE12, power[ 6]) | 3987 SM(R92C_TXAGC_RATE18, power[ 7])); 3988 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3989 SM(R92C_TXAGC_RATE24, power[ 8]) | 3990 SM(R92C_TXAGC_RATE36, power[ 9]) | 3991 SM(R92C_TXAGC_RATE48, power[10]) | 3992 SM(R92C_TXAGC_RATE54, power[11])); 3993 /* Write per-MCS Tx power. */ 3994 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3995 SM(R92C_TXAGC_MCS00, power[12]) | 3996 SM(R92C_TXAGC_MCS01, power[13]) | 3997 SM(R92C_TXAGC_MCS02, power[14]) | 3998 SM(R92C_TXAGC_MCS03, power[15])); 3999 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4000 SM(R92C_TXAGC_MCS04, power[16]) | 4001 SM(R92C_TXAGC_MCS05, power[17]) | 4002 SM(R92C_TXAGC_MCS06, power[18]) | 4003 SM(R92C_TXAGC_MCS07, power[19])); 4004 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4005 SM(R92C_TXAGC_MCS08, power[20]) | 4006 SM(R92C_TXAGC_MCS09, power[21]) | 4007 SM(R92C_TXAGC_MCS10, power[22]) | 4008 SM(R92C_TXAGC_MCS11, power[23])); 4009 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4010 SM(R92C_TXAGC_MCS12, power[24]) | 4011 SM(R92C_TXAGC_MCS13, power[25]) | 4012 SM(R92C_TXAGC_MCS14, power[26]) | 4013 SM(R92C_TXAGC_MCS15, power[27])); 4014} 4015 4016static void 4017urtwn_get_txpower(struct urtwn_softc *sc, int chain, 4018 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4019 uint16_t power[URTWN_RIDX_COUNT]) 4020{ 4021 struct ieee80211com *ic = &sc->sc_ic; 4022 struct r92c_rom *rom = &sc->rom.r92c_rom; 4023 uint16_t cckpow, ofdmpow, htpow, diff, max; 4024 const struct urtwn_txpwr *base; 4025 int ridx, chan, group; 4026 4027 /* Determine channel group. */ 4028 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4029 if (chan <= 3) 4030 group = 0; 4031 else if (chan <= 9) 4032 group = 1; 4033 else 4034 group = 2; 4035 4036 /* Get original Tx power based on board type and RF chain. */ 4037 if (!(sc->chip & URTWN_CHIP_92C)) { 4038 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 4039 base = &rtl8188ru_txagc[chain]; 4040 else 4041 base = &rtl8192cu_txagc[chain]; 4042 } else 4043 base = &rtl8192cu_txagc[chain]; 4044 4045 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4046 if (sc->regulatory == 0) { 4047 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4048 power[ridx] = base->pwr[0][ridx]; 4049 } 4050 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4051 if (sc->regulatory == 3) { 4052 power[ridx] = base->pwr[0][ridx]; 4053 /* Apply vendor limits. */ 4054 if (extc != NULL) 4055 max = rom->ht40_max_pwr[group]; 4056 else 4057 max = rom->ht20_max_pwr[group]; 4058 max = (max >> (chain * 4)) & 0xf; 4059 if (power[ridx] > max) 4060 power[ridx] = max; 4061 } else if (sc->regulatory == 1) { 4062 if (extc == NULL) 4063 power[ridx] = base->pwr[group][ridx]; 4064 } else if (sc->regulatory != 2) 4065 power[ridx] = base->pwr[0][ridx]; 4066 } 4067 4068 /* Compute per-CCK rate Tx power. */ 4069 cckpow = rom->cck_tx_pwr[chain][group]; 4070 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4071 power[ridx] += cckpow; 4072 if (power[ridx] > R92C_MAX_TX_PWR) 4073 power[ridx] = R92C_MAX_TX_PWR; 4074 } 4075 4076 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4077 if (sc->ntxchains > 1) { 4078 /* Apply reduction for 2 spatial streams. */ 4079 diff = rom->ht40_2s_tx_pwr_diff[group]; 4080 diff = (diff >> (chain * 4)) & 0xf; 4081 htpow = (htpow > diff) ? htpow - diff : 0; 4082 } 4083 4084 /* Compute per-OFDM rate Tx power. */ 4085 diff = rom->ofdm_tx_pwr_diff[group]; 4086 diff = (diff >> (chain * 4)) & 0xf; 4087 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4088 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4089 power[ridx] += ofdmpow; 4090 if (power[ridx] > R92C_MAX_TX_PWR) 4091 power[ridx] = R92C_MAX_TX_PWR; 4092 } 4093 4094 /* Compute per-MCS Tx power. */ 4095 if (extc == NULL) { 4096 diff = rom->ht20_tx_pwr_diff[group]; 4097 diff = (diff >> (chain * 4)) & 0xf; 4098 htpow += diff; /* HT40->HT20 correction. */ 4099 } 4100 for (ridx = 12; ridx <= 27; ridx++) { 4101 power[ridx] += htpow; 4102 if (power[ridx] > R92C_MAX_TX_PWR) 4103 power[ridx] = R92C_MAX_TX_PWR; 4104 } 4105#ifdef USB_DEBUG 4106 if (sc->sc_debug & URTWN_DEBUG_TXPWR) { 4107 /* Dump per-rate Tx power values. */ 4108 printf("Tx power for chain %d:\n", chain); 4109 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 4110 printf("Rate %d = %u\n", ridx, power[ridx]); 4111 } 4112#endif 4113} 4114 4115static void 4116urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 4117 struct ieee80211_channel *c, struct ieee80211_channel *extc, 4118 uint16_t power[URTWN_RIDX_COUNT]) 4119{ 4120 struct ieee80211com *ic = &sc->sc_ic; 4121 struct r88e_rom *rom = &sc->rom.r88e_rom; 4122 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4123 const struct urtwn_r88e_txpwr *base; 4124 int ridx, chan, group; 4125 4126 /* Determine channel group. */ 4127 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4128 if (chan <= 2) 4129 group = 0; 4130 else if (chan <= 5) 4131 group = 1; 4132 else if (chan <= 8) 4133 group = 2; 4134 else if (chan <= 11) 4135 group = 3; 4136 else if (chan <= 13) 4137 group = 4; 4138 else 4139 group = 5; 4140 4141 /* Get original Tx power based on board type and RF chain. */ 4142 base = &rtl8188eu_txagc[chain]; 4143 4144 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4145 if (sc->regulatory == 0) { 4146 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 4147 power[ridx] = base->pwr[0][ridx]; 4148 } 4149 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 4150 if (sc->regulatory == 3) 4151 power[ridx] = base->pwr[0][ridx]; 4152 else if (sc->regulatory == 1) { 4153 if (extc == NULL) 4154 power[ridx] = base->pwr[group][ridx]; 4155 } else if (sc->regulatory != 2) 4156 power[ridx] = base->pwr[0][ridx]; 4157 } 4158 4159 /* Compute per-CCK rate Tx power. */ 4160 cckpow = rom->cck_tx_pwr[group]; 4161 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 4162 power[ridx] += cckpow; 4163 if (power[ridx] > R92C_MAX_TX_PWR) 4164 power[ridx] = R92C_MAX_TX_PWR; 4165 } 4166 4167 htpow = rom->ht40_tx_pwr[group]; 4168 4169 /* Compute per-OFDM rate Tx power. */ 4170 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4171 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 4172 power[ridx] += ofdmpow; 4173 if (power[ridx] > R92C_MAX_TX_PWR) 4174 power[ridx] = R92C_MAX_TX_PWR; 4175 } 4176 4177 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4178 for (ridx = 12; ridx <= 27; ridx++) { 4179 power[ridx] += bw20pow; 4180 if (power[ridx] > R92C_MAX_TX_PWR) 4181 power[ridx] = R92C_MAX_TX_PWR; 4182 } 4183} 4184 4185static void 4186urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 4187 struct ieee80211_channel *extc) 4188{ 4189 uint16_t power[URTWN_RIDX_COUNT]; 4190 int i; 4191 4192 for (i = 0; i < sc->ntxchains; i++) { 4193 /* Compute per-rate Tx power values. */ 4194 if (sc->chip & URTWN_CHIP_88E) 4195 urtwn_r88e_get_txpower(sc, i, c, extc, power); 4196 else 4197 urtwn_get_txpower(sc, i, c, extc, power); 4198 /* Write per-rate Tx power values to hardware. */ 4199 urtwn_write_txpower(sc, i, power); 4200 } 4201} 4202 4203static void 4204urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 4205{ 4206 uint32_t reg; 4207 4208 reg = urtwn_read_4(sc, R92C_RCR); 4209 if (enable) 4210 reg &= ~R92C_RCR_CBSSID_BCN; 4211 else 4212 reg |= R92C_RCR_CBSSID_BCN; 4213 urtwn_write_4(sc, R92C_RCR, reg); 4214} 4215 4216static void 4217urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 4218{ 4219 uint32_t reg; 4220 4221 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 4222 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4223 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 4224 4225 if (!(sc->chip & URTWN_CHIP_88E)) { 4226 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 4227 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 4228 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 4229 } 4230} 4231 4232static void 4233urtwn_scan_start(struct ieee80211com *ic) 4234{ 4235 struct urtwn_softc *sc = ic->ic_softc; 4236 4237 URTWN_LOCK(sc); 4238 /* Receive beacons / probe responses from any BSSID. */ 4239 if (ic->ic_opmode != IEEE80211_M_IBSS) 4240 urtwn_set_rx_bssid_all(sc, 1); 4241 4242 /* Set gain for scanning. */ 4243 urtwn_set_gain(sc, 0x20); 4244 URTWN_UNLOCK(sc); 4245} 4246 4247static void 4248urtwn_scan_end(struct ieee80211com *ic) 4249{ 4250 struct urtwn_softc *sc = ic->ic_softc; 4251 4252 URTWN_LOCK(sc); 4253 /* Restore limitations. */ 4254 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 4255 urtwn_set_rx_bssid_all(sc, 0); 4256 4257 /* Set gain under link. */ 4258 urtwn_set_gain(sc, 0x32); 4259 URTWN_UNLOCK(sc); 4260} 4261 4262static void 4263urtwn_set_channel(struct ieee80211com *ic) 4264{ 4265 struct urtwn_softc *sc = ic->ic_softc; 4266 struct ieee80211_channel *c = ic->ic_curchan; 4267 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4268 4269 URTWN_LOCK(sc); 4270 if (vap->iv_state == IEEE80211_S_SCAN) { 4271 /* Make link LED blink during scan. */ 4272 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 4273 } 4274 urtwn_set_chan(sc, c, NULL); 4275 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 4276 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 4277 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 4278 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 4279 URTWN_UNLOCK(sc); 4280} 4281 4282static int 4283urtwn_wme_update(struct ieee80211com *ic) 4284{ 4285 const struct wmeParams *wmep = 4286 ic->ic_wme.wme_chanParams.cap_wmeParams; 4287 struct urtwn_softc *sc = ic->ic_softc; 4288 uint8_t aifs, acm, slottime; 4289 int ac; 4290 4291 acm = 0; 4292 slottime = IEEE80211_GET_SLOTTIME(ic); 4293 4294 URTWN_LOCK(sc); 4295 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4296 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4297 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4298 urtwn_write_4(sc, wme2queue[ac].reg, 4299 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 4300 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 4301 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 4302 SM(R92C_EDCA_PARAM_AIFS, aifs)); 4303 if (ac != WME_AC_BE) 4304 acm |= wmep[ac].wmep_acm << ac; 4305 } 4306 4307 if (acm != 0) 4308 acm |= R92C_ACMHWCTRL_EN; 4309 urtwn_write_1(sc, R92C_ACMHWCTRL, 4310 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 4311 acm); 4312 4313 URTWN_UNLOCK(sc); 4314 4315 return 0; 4316} 4317 4318static void 4319urtwn_update_slot(struct ieee80211com *ic) 4320{ 4321 urtwn_cmd_sleepable(ic->ic_softc, NULL, 0, urtwn_update_slot_cb); 4322} 4323 4324static void 4325urtwn_update_slot_cb(struct urtwn_softc *sc, union sec_param *data) 4326{ 4327 struct ieee80211com *ic = &sc->sc_ic; 4328 uint8_t slottime; 4329 4330 slottime = IEEE80211_GET_SLOTTIME(ic); 4331 4332 URTWN_DPRINTF(sc, URTWN_DEBUG_ANY, "%s: setting slot time to %uus\n", 4333 __func__, slottime); 4334 4335 urtwn_write_1(sc, R92C_SLOT, slottime); 4336 urtwn_update_aifs(sc, slottime); 4337} 4338 4339static void 4340urtwn_update_aifs(struct urtwn_softc *sc, uint8_t slottime) 4341{ 4342 const struct wmeParams *wmep = 4343 sc->sc_ic.ic_wme.wme_chanParams.cap_wmeParams; 4344 uint8_t aifs, ac; 4345 4346 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4347 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4348 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4349 urtwn_write_1(sc, wme2queue[ac].reg, aifs); 4350 } 4351} 4352 4353static void 4354urtwn_set_promisc(struct urtwn_softc *sc) 4355{ 4356 struct ieee80211com *ic = &sc->sc_ic; 4357 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4358 uint32_t rcr, mask1, mask2; 4359 4360 URTWN_ASSERT_LOCKED(sc); 4361 4362 if (vap->iv_opmode == IEEE80211_M_MONITOR) 4363 return; 4364 4365 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 4366 mask2 = R92C_RCR_APM; 4367 4368 if (vap->iv_state == IEEE80211_S_RUN) { 4369 switch (vap->iv_opmode) { 4370 case IEEE80211_M_STA: 4371 mask2 |= R92C_RCR_CBSSID_DATA; 4372 /* FALLTHROUGH */ 4373 case IEEE80211_M_HOSTAP: 4374 mask2 |= R92C_RCR_CBSSID_BCN; 4375 break; 4376 case IEEE80211_M_IBSS: 4377 mask2 |= R92C_RCR_CBSSID_DATA; 4378 break; 4379 default: 4380 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4381 __func__, vap->iv_opmode); 4382 return; 4383 } 4384 } 4385 4386 rcr = urtwn_read_4(sc, R92C_RCR); 4387 if (ic->ic_promisc == 0) 4388 rcr = (rcr & ~mask1) | mask2; 4389 else 4390 rcr = (rcr & ~mask2) | mask1; 4391 urtwn_write_4(sc, R92C_RCR, rcr); 4392} 4393 4394static void 4395urtwn_update_promisc(struct ieee80211com *ic) 4396{ 4397 struct urtwn_softc *sc = ic->ic_softc; 4398 4399 URTWN_LOCK(sc); 4400 if (sc->sc_flags & URTWN_RUNNING) 4401 urtwn_set_promisc(sc); 4402 URTWN_UNLOCK(sc); 4403} 4404 4405static void 4406urtwn_update_mcast(struct ieee80211com *ic) 4407{ 4408 /* XXX do nothing? */ 4409} 4410 4411static struct ieee80211_node * 4412urtwn_r88e_node_alloc(struct ieee80211vap *vap, 4413 const uint8_t mac[IEEE80211_ADDR_LEN]) 4414{ 4415 struct urtwn_node *un; 4416 4417 un = malloc(sizeof (struct urtwn_node), M_80211_NODE, 4418 M_NOWAIT | M_ZERO); 4419 4420 if (un == NULL) 4421 return NULL; 4422 4423 un->id = URTWN_MACID_UNDEFINED; 4424 4425 return &un->ni; 4426} 4427 4428static void 4429urtwn_r88e_newassoc(struct ieee80211_node *ni, int isnew) 4430{ 4431 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4432 struct urtwn_node *un = URTWN_NODE(ni); 4433 uint8_t id; 4434 4435 if (!isnew) 4436 return; 4437 4438 URTWN_NT_LOCK(sc); 4439 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 4440 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 4441 un->id = id; 4442 sc->node_list[id] = ni; 4443 break; 4444 } 4445 } 4446 URTWN_NT_UNLOCK(sc); 4447 4448 if (id > URTWN_MACID_MAX(sc)) { 4449 device_printf(sc->sc_dev, "%s: node table is full\n", 4450 __func__); 4451 } 4452} 4453 4454static void 4455urtwn_r88e_node_free(struct ieee80211_node *ni) 4456{ 4457 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4458 struct urtwn_node *un = URTWN_NODE(ni); 4459 4460 URTWN_NT_LOCK(sc); 4461 if (un->id != URTWN_MACID_UNDEFINED) 4462 sc->node_list[un->id] = NULL; 4463 URTWN_NT_UNLOCK(sc); 4464 4465 sc->sc_node_free(ni); 4466} 4467 4468static void 4469urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 4470 struct ieee80211_channel *extc) 4471{ 4472 struct ieee80211com *ic = &sc->sc_ic; 4473 uint32_t reg; 4474 u_int chan; 4475 int i; 4476 4477 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4478 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 4479 device_printf(sc->sc_dev, 4480 "%s: invalid channel %x\n", __func__, chan); 4481 return; 4482 } 4483 4484 /* Set Tx power for this new channel. */ 4485 urtwn_set_txpower(sc, c, extc); 4486 4487 for (i = 0; i < sc->nrxchains; i++) { 4488 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4489 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4490 } 4491#ifndef IEEE80211_NO_HT 4492 if (extc != NULL) { 4493 /* Is secondary channel below or above primary? */ 4494 int prichlo = c->ic_freq < extc->ic_freq; 4495 4496 urtwn_write_1(sc, R92C_BWOPMODE, 4497 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4498 4499 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4500 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4501 urtwn_write_1(sc, R92C_RRSR + 2, reg); 4502 4503 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4504 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4505 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4506 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4507 4508 /* Set CCK side band. */ 4509 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4510 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4511 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4512 4513 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4514 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4515 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4516 4517 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4518 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4519 ~R92C_FPGA0_ANAPARAM2_CBW20); 4520 4521 reg = urtwn_bb_read(sc, 0x818); 4522 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4523 urtwn_bb_write(sc, 0x818, reg); 4524 4525 /* Select 40MHz bandwidth. */ 4526 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4527 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4528 } else 4529#endif 4530 { 4531 urtwn_write_1(sc, R92C_BWOPMODE, 4532 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4533 4534 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4535 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4536 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4537 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4538 4539 if (!(sc->chip & URTWN_CHIP_88E)) { 4540 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4541 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4542 R92C_FPGA0_ANAPARAM2_CBW20); 4543 } 4544 4545 /* Select 20MHz bandwidth. */ 4546 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4547 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4548 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 4549 R92C_RF_CHNLBW_BW20)); 4550 } 4551} 4552 4553static void 4554urtwn_iq_calib(struct urtwn_softc *sc) 4555{ 4556 /* TODO */ 4557} 4558 4559static void 4560urtwn_lc_calib(struct urtwn_softc *sc) 4561{ 4562 uint32_t rf_ac[2]; 4563 uint8_t txmode; 4564 int i; 4565 4566 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4567 if ((txmode & 0x70) != 0) { 4568 /* Disable all continuous Tx. */ 4569 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4570 4571 /* Set RF mode to standby mode. */ 4572 for (i = 0; i < sc->nrxchains; i++) { 4573 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4574 urtwn_rf_write(sc, i, R92C_RF_AC, 4575 RW(rf_ac[i], R92C_RF_AC_MODE, 4576 R92C_RF_AC_MODE_STANDBY)); 4577 } 4578 } else { 4579 /* Block all Tx queues. */ 4580 urtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL); 4581 } 4582 /* Start calibration. */ 4583 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4584 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4585 4586 /* Give calibration the time to complete. */ 4587 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 4588 4589 /* Restore configuration. */ 4590 if ((txmode & 0x70) != 0) { 4591 /* Restore Tx mode. */ 4592 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4593 /* Restore RF mode. */ 4594 for (i = 0; i < sc->nrxchains; i++) 4595 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4596 } else { 4597 /* Unblock all Tx queues. */ 4598 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4599 } 4600} 4601 4602static void 4603urtwn_temp_calib(struct urtwn_softc *sc) 4604{ 4605 uint8_t temp; 4606 4607 URTWN_ASSERT_LOCKED(sc); 4608 4609 if (!(sc->sc_flags & URTWN_TEMP_MEASURED)) { 4610 /* Start measuring temperature. */ 4611 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 4612 "%s: start measuring temperature\n", __func__); 4613 if (sc->chip & URTWN_CHIP_88E) { 4614 urtwn_rf_write(sc, 0, R88E_RF_T_METER, 4615 R88E_RF_T_METER_START); 4616 } else { 4617 urtwn_rf_write(sc, 0, R92C_RF_T_METER, 4618 R92C_RF_T_METER_START); 4619 } 4620 sc->sc_flags |= URTWN_TEMP_MEASURED; 4621 return; 4622 } 4623 sc->sc_flags &= ~URTWN_TEMP_MEASURED; 4624 4625 /* Read measured temperature. */ 4626 if (sc->chip & URTWN_CHIP_88E) { 4627 temp = MS(urtwn_rf_read(sc, 0, R88E_RF_T_METER), 4628 R88E_RF_T_METER_VAL); 4629 } else { 4630 temp = MS(urtwn_rf_read(sc, 0, R92C_RF_T_METER), 4631 R92C_RF_T_METER_VAL); 4632 } 4633 if (temp == 0) { /* Read failed, skip. */ 4634 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 4635 "%s: temperature read failed, skipping\n", __func__); 4636 return; 4637 } 4638 4639 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 4640 "%s: temperature: previous %u, current %u\n", 4641 __func__, sc->thcal_lctemp, temp); 4642 4643 /* 4644 * Redo LC calibration if temperature changed significantly since 4645 * last calibration. 4646 */ 4647 if (sc->thcal_lctemp == 0) { 4648 /* First LC calibration is performed in urtwn_init(). */ 4649 sc->thcal_lctemp = temp; 4650 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4651 URTWN_DPRINTF(sc, URTWN_DEBUG_TEMP, 4652 "%s: LC calib triggered by temp: %u -> %u\n", 4653 __func__, sc->thcal_lctemp, temp); 4654 urtwn_lc_calib(sc); 4655 /* Record temperature of last LC calibration. */ 4656 sc->thcal_lctemp = temp; 4657 } 4658} 4659 4660static int 4661urtwn_init(struct urtwn_softc *sc) 4662{ 4663 struct ieee80211com *ic = &sc->sc_ic; 4664 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4665 uint8_t macaddr[IEEE80211_ADDR_LEN]; 4666 uint32_t reg; 4667 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 4668 int error; 4669 4670 URTWN_LOCK(sc); 4671 if (sc->sc_flags & URTWN_RUNNING) { 4672 URTWN_UNLOCK(sc); 4673 return (0); 4674 } 4675 4676 /* Init firmware commands ring. */ 4677 sc->fwcur = 0; 4678 4679 /* Allocate Tx/Rx buffers. */ 4680 error = urtwn_alloc_rx_list(sc); 4681 if (error != 0) 4682 goto fail; 4683 4684 error = urtwn_alloc_tx_list(sc); 4685 if (error != 0) 4686 goto fail; 4687 4688 /* Power on adapter. */ 4689 error = urtwn_power_on(sc); 4690 if (error != 0) 4691 goto fail; 4692 4693 /* Initialize DMA. */ 4694 error = urtwn_dma_init(sc); 4695 if (error != 0) 4696 goto fail; 4697 4698 /* Set info size in Rx descriptors (in 64-bit words). */ 4699 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4700 4701 /* Init interrupts. */ 4702 if (sc->chip & URTWN_CHIP_88E) { 4703 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4704 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4705 goto fail; 4706 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4707 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4708 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4709 goto fail; 4710 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4711 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4712 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4713 goto fail; 4714 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4715 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4716 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4717 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4718 goto fail; 4719 } else { 4720 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4721 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4722 goto fail; 4723 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4724 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4725 goto fail; 4726 } 4727 4728 /* Set MAC address. */ 4729 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 4730 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 4731 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4732 goto fail; 4733 4734 /* Set initial network type. */ 4735 urtwn_set_mode(sc, R92C_MSR_INFRA); 4736 4737 /* Initialize Rx filter. */ 4738 urtwn_rxfilter_init(sc); 4739 4740 /* Set response rate. */ 4741 reg = urtwn_read_4(sc, R92C_RRSR); 4742 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4743 urtwn_write_4(sc, R92C_RRSR, reg); 4744 4745 /* Set short/long retry limits. */ 4746 urtwn_write_2(sc, R92C_RL, 4747 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4748 4749 /* Initialize EDCA parameters. */ 4750 urtwn_edca_init(sc); 4751 4752 /* Setup rate fallback. */ 4753 if (!(sc->chip & URTWN_CHIP_88E)) { 4754 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4755 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4756 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4757 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4758 } 4759 4760 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4761 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4762 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4763 /* Set ACK timeout. */ 4764 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4765 4766 /* Setup USB aggregation. */ 4767 reg = urtwn_read_4(sc, R92C_TDECTRL); 4768 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4769 urtwn_write_4(sc, R92C_TDECTRL, reg); 4770 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4771 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4772 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4773 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4774 if (sc->chip & URTWN_CHIP_88E) 4775 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4776 else { 4777 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4778 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4779 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4780 R92C_USB_SPECIAL_OPTION_AGG_EN); 4781 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 4782 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 4783 } 4784 4785 /* Initialize beacon parameters. */ 4786 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4787 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4788 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 4789 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 4790 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4791 4792 if (!(sc->chip & URTWN_CHIP_88E)) { 4793 /* Setup AMPDU aggregation. */ 4794 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4795 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4796 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 4797 4798 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4799 } 4800 4801#ifndef URTWN_WITHOUT_UCODE 4802 /* Load 8051 microcode. */ 4803 error = urtwn_load_firmware(sc); 4804 if (error == 0) 4805 sc->sc_flags |= URTWN_FW_LOADED; 4806#endif 4807 4808 /* Initialize MAC/BB/RF blocks. */ 4809 error = urtwn_mac_init(sc); 4810 if (error != 0) { 4811 device_printf(sc->sc_dev, 4812 "%s: error while initializing MAC block\n", __func__); 4813 goto fail; 4814 } 4815 urtwn_bb_init(sc); 4816 urtwn_rf_init(sc); 4817 4818 /* Reinitialize Rx filter (D3845 is not committed yet). */ 4819 urtwn_rxfilter_init(sc); 4820 4821 if (sc->chip & URTWN_CHIP_88E) { 4822 urtwn_write_2(sc, R92C_CR, 4823 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4824 R92C_CR_MACRXEN); 4825 } 4826 4827 /* Turn CCK and OFDM blocks on. */ 4828 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4829 reg |= R92C_RFMOD_CCK_EN; 4830 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4831 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4832 goto fail; 4833 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4834 reg |= R92C_RFMOD_OFDM_EN; 4835 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4836 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4837 goto fail; 4838 4839 /* Clear per-station keys table. */ 4840 urtwn_cam_init(sc); 4841 4842 /* Enable decryption / encryption. */ 4843 urtwn_write_2(sc, R92C_SECCFG, 4844 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 4845 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA | 4846 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 4847 4848 /* 4849 * Install static keys (if any). 4850 * Must be called after urtwn_cam_init(). 4851 */ 4852 ieee80211_runtask(ic, &sc->cmdq_task); 4853 4854 /* Enable hardware sequence numbering. */ 4855 urtwn_write_1(sc, R92C_HWSEQ_CTRL, R92C_TX_QUEUE_ALL); 4856 4857 /* Enable per-packet TX report. */ 4858 if (sc->chip & URTWN_CHIP_88E) { 4859 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 4860 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 4861 } 4862 4863 /* Perform LO and IQ calibrations. */ 4864 urtwn_iq_calib(sc); 4865 /* Perform LC calibration. */ 4866 urtwn_lc_calib(sc); 4867 4868 /* Fix USB interference issue. */ 4869 if (!(sc->chip & URTWN_CHIP_88E)) { 4870 urtwn_write_1(sc, 0xfe40, 0xe0); 4871 urtwn_write_1(sc, 0xfe41, 0x8d); 4872 urtwn_write_1(sc, 0xfe42, 0x80); 4873 4874 urtwn_pa_bias_init(sc); 4875 } 4876 4877 /* Initialize GPIO setting. */ 4878 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4879 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4880 4881 /* Fix for lower temperature. */ 4882 if (!(sc->chip & URTWN_CHIP_88E)) 4883 urtwn_write_1(sc, 0x15, 0xe9); 4884 4885 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 4886 4887 sc->sc_flags |= URTWN_RUNNING; 4888 4889 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4890fail: 4891 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4892 error = EIO; 4893 4894 URTWN_UNLOCK(sc); 4895 4896 return (error); 4897} 4898 4899static void 4900urtwn_stop(struct urtwn_softc *sc) 4901{ 4902 4903 URTWN_LOCK(sc); 4904 if (!(sc->sc_flags & URTWN_RUNNING)) { 4905 URTWN_UNLOCK(sc); 4906 return; 4907 } 4908 4909 sc->sc_flags &= ~(URTWN_RUNNING | URTWN_FW_LOADED | 4910 URTWN_TEMP_MEASURED); 4911 sc->thcal_lctemp = 0; 4912 callout_stop(&sc->sc_watchdog_ch); 4913 urtwn_abort_xfers(sc); 4914 4915 urtwn_drain_mbufq(sc); 4916 URTWN_UNLOCK(sc); 4917} 4918 4919static void 4920urtwn_abort_xfers(struct urtwn_softc *sc) 4921{ 4922 int i; 4923 4924 URTWN_ASSERT_LOCKED(sc); 4925 4926 /* abort any pending transfers */ 4927 for (i = 0; i < URTWN_N_TRANSFER; i++) 4928 usbd_transfer_stop(sc->sc_xfer[i]); 4929} 4930 4931static int 4932urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4933 const struct ieee80211_bpf_params *params) 4934{ 4935 struct ieee80211com *ic = ni->ni_ic; 4936 struct urtwn_softc *sc = ic->ic_softc; 4937 struct urtwn_data *bf; 4938 int error; 4939 4940 /* prevent management frames from being sent if we're not ready */ 4941 URTWN_LOCK(sc); 4942 if (!(sc->sc_flags & URTWN_RUNNING)) { 4943 error = ENETDOWN; 4944 goto end; 4945 } 4946 4947 bf = urtwn_getbuf(sc); 4948 if (bf == NULL) { 4949 error = ENOBUFS; 4950 goto end; 4951 } 4952 4953 if (params == NULL) { 4954 /* 4955 * Legacy path; interpret frame contents to decide 4956 * precisely how to send the frame. 4957 */ 4958 error = urtwn_tx_data(sc, ni, m, bf); 4959 } else { 4960 /* 4961 * Caller supplied explicit parameters to use in 4962 * sending the frame. 4963 */ 4964 error = urtwn_tx_raw(sc, ni, m, bf, params); 4965 } 4966 if (error != 0) { 4967 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 4968 goto end; 4969 } 4970 4971 sc->sc_txtimer = 5; 4972 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4973 4974end: 4975 if (error != 0) 4976 m_freem(m); 4977 4978 URTWN_UNLOCK(sc); 4979 4980 return (error); 4981} 4982 4983static void 4984urtwn_ms_delay(struct urtwn_softc *sc) 4985{ 4986 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 4987} 4988 4989static device_method_t urtwn_methods[] = { 4990 /* Device interface */ 4991 DEVMETHOD(device_probe, urtwn_match), 4992 DEVMETHOD(device_attach, urtwn_attach), 4993 DEVMETHOD(device_detach, urtwn_detach), 4994 4995 DEVMETHOD_END 4996}; 4997 4998static driver_t urtwn_driver = { 4999 "urtwn", 5000 urtwn_methods, 5001 sizeof(struct urtwn_softc) 5002}; 5003 5004static devclass_t urtwn_devclass; 5005 5006DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 5007MODULE_DEPEND(urtwn, usb, 1, 1, 1); 5008MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 5009#ifndef URTWN_WITHOUT_UCODE 5010MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 5011#endif 5012MODULE_VERSION(urtwn, 1); 5013USB_PNP_HOST_INFO(urtwn_devs); 5014