if_urtwn.c revision 292203
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2015 Andriy Voskoboinyk <avos@FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21#include <sys/cdefs.h> 22__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 292203 2015-12-14 12:36:10Z avos $"); 23 24/* 25 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 26 */ 27 28#include "opt_wlan.h" 29 30#include <sys/param.h> 31#include <sys/sockio.h> 32#include <sys/sysctl.h> 33#include <sys/lock.h> 34#include <sys/mutex.h> 35#include <sys/condvar.h> 36#include <sys/mbuf.h> 37#include <sys/kernel.h> 38#include <sys/socket.h> 39#include <sys/systm.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/linker.h> 45#include <sys/firmware.h> 46#include <sys/kdb.h> 47 48#include <machine/bus.h> 49#include <machine/resource.h> 50#include <sys/rman.h> 51 52#include <net/bpf.h> 53#include <net/if.h> 54#include <net/if_var.h> 55#include <net/if_arp.h> 56#include <net/ethernet.h> 57#include <net/if_dl.h> 58#include <net/if_media.h> 59#include <net/if_types.h> 60 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/in_var.h> 64#include <netinet/if_ether.h> 65#include <netinet/ip.h> 66 67#include <net80211/ieee80211_var.h> 68#include <net80211/ieee80211_input.h> 69#include <net80211/ieee80211_regdomain.h> 70#include <net80211/ieee80211_radiotap.h> 71#include <net80211/ieee80211_ratectl.h> 72 73#include <dev/usb/usb.h> 74#include <dev/usb/usbdi.h> 75#include <dev/usb/usb_device.h> 76#include "usbdevs.h" 77 78#define USB_DEBUG_VAR urtwn_debug 79#include <dev/usb/usb_debug.h> 80 81#include <dev/usb/wlan/if_urtwnreg.h> 82#include <dev/usb/wlan/if_urtwnvar.h> 83 84#ifdef USB_DEBUG 85static int urtwn_debug = 0; 86 87SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 88SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 89 "Debug level"); 90#endif 91 92#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 93 94/* various supported device vendors/products */ 95static const STRUCT_USB_HOST_ID urtwn_devs[] = { 96#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 97#define URTWN_RTL8188E_DEV(v,p) \ 98 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 99#define URTWN_RTL8188E 1 100 URTWN_DEV(ABOCOM, RTL8188CU_1), 101 URTWN_DEV(ABOCOM, RTL8188CU_2), 102 URTWN_DEV(ABOCOM, RTL8192CU), 103 URTWN_DEV(ASUS, RTL8192CU), 104 URTWN_DEV(ASUS, USBN10NANO), 105 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 106 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 107 URTWN_DEV(AZUREWAVE, RTL8188CU), 108 URTWN_DEV(BELKIN, F7D2102), 109 URTWN_DEV(BELKIN, RTL8188CU), 110 URTWN_DEV(BELKIN, RTL8192CU), 111 URTWN_DEV(CHICONY, RTL8188CUS_1), 112 URTWN_DEV(CHICONY, RTL8188CUS_2), 113 URTWN_DEV(CHICONY, RTL8188CUS_3), 114 URTWN_DEV(CHICONY, RTL8188CUS_4), 115 URTWN_DEV(CHICONY, RTL8188CUS_5), 116 URTWN_DEV(COREGA, RTL8192CU), 117 URTWN_DEV(DLINK, RTL8188CU), 118 URTWN_DEV(DLINK, RTL8192CU_1), 119 URTWN_DEV(DLINK, RTL8192CU_2), 120 URTWN_DEV(DLINK, RTL8192CU_3), 121 URTWN_DEV(DLINK, DWA131B), 122 URTWN_DEV(EDIMAX, EW7811UN), 123 URTWN_DEV(EDIMAX, RTL8192CU), 124 URTWN_DEV(FEIXUN, RTL8188CU), 125 URTWN_DEV(FEIXUN, RTL8192CU), 126 URTWN_DEV(GUILLEMOT, HWNUP150), 127 URTWN_DEV(HAWKING, RTL8192CU), 128 URTWN_DEV(HP3, RTL8188CU), 129 URTWN_DEV(NETGEAR, WNA1000M), 130 URTWN_DEV(NETGEAR, RTL8192CU), 131 URTWN_DEV(NETGEAR4, RTL8188CU), 132 URTWN_DEV(NOVATECH, RTL8188CU), 133 URTWN_DEV(PLANEX2, RTL8188CU_1), 134 URTWN_DEV(PLANEX2, RTL8188CU_2), 135 URTWN_DEV(PLANEX2, RTL8188CU_3), 136 URTWN_DEV(PLANEX2, RTL8188CU_4), 137 URTWN_DEV(PLANEX2, RTL8188CUS), 138 URTWN_DEV(PLANEX2, RTL8192CU), 139 URTWN_DEV(REALTEK, RTL8188CE_0), 140 URTWN_DEV(REALTEK, RTL8188CE_1), 141 URTWN_DEV(REALTEK, RTL8188CTV), 142 URTWN_DEV(REALTEK, RTL8188CU_0), 143 URTWN_DEV(REALTEK, RTL8188CU_1), 144 URTWN_DEV(REALTEK, RTL8188CU_2), 145 URTWN_DEV(REALTEK, RTL8188CU_3), 146 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 147 URTWN_DEV(REALTEK, RTL8188CUS), 148 URTWN_DEV(REALTEK, RTL8188RU_1), 149 URTWN_DEV(REALTEK, RTL8188RU_2), 150 URTWN_DEV(REALTEK, RTL8188RU_3), 151 URTWN_DEV(REALTEK, RTL8191CU), 152 URTWN_DEV(REALTEK, RTL8192CE), 153 URTWN_DEV(REALTEK, RTL8192CU), 154 URTWN_DEV(SITECOMEU, RTL8188CU_1), 155 URTWN_DEV(SITECOMEU, RTL8188CU_2), 156 URTWN_DEV(SITECOMEU, RTL8192CU), 157 URTWN_DEV(TRENDNET, RTL8188CU), 158 URTWN_DEV(TRENDNET, RTL8192CU), 159 URTWN_DEV(ZYXEL, RTL8192CU), 160 /* URTWN_RTL8188E */ 161 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 162 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 163 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 164 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 165 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 166#undef URTWN_RTL8188E_DEV 167#undef URTWN_DEV 168}; 169 170static device_probe_t urtwn_match; 171static device_attach_t urtwn_attach; 172static device_detach_t urtwn_detach; 173 174static usb_callback_t urtwn_bulk_tx_callback; 175static usb_callback_t urtwn_bulk_rx_callback; 176 177static void urtwn_drain_mbufq(struct urtwn_softc *sc); 178static usb_error_t urtwn_do_request(struct urtwn_softc *, 179 struct usb_device_request *, void *); 180static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 181 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 182 const uint8_t [IEEE80211_ADDR_LEN], 183 const uint8_t [IEEE80211_ADDR_LEN]); 184static void urtwn_vap_delete(struct ieee80211vap *); 185static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 186 int *); 187static struct mbuf * urtwn_report_intr(struct usb_xfer *, struct urtwn_data *, 188 int *, int8_t *); 189static struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int, 190 int *, int8_t *); 191static void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 192 void *); 193static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 194 int); 195static int urtwn_alloc_list(struct urtwn_softc *, 196 struct urtwn_data[], int, int); 197static int urtwn_alloc_rx_list(struct urtwn_softc *); 198static int urtwn_alloc_tx_list(struct urtwn_softc *); 199static void urtwn_free_list(struct urtwn_softc *, 200 struct urtwn_data data[], int); 201static void urtwn_free_rx_list(struct urtwn_softc *); 202static void urtwn_free_tx_list(struct urtwn_softc *); 203static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 204static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 205static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 206 uint8_t *, int); 207static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 208static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 209static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 210static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 211 uint8_t *, int); 212static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 213static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 214static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 215static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 216 const void *, int); 217static void urtwn_cmdq_cb(void *, int); 218static int urtwn_cmd_sleepable(struct urtwn_softc *, const void *, 219 size_t, CMD_FUNC_PROTO); 220static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 221 uint8_t, uint32_t); 222static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 223 uint8_t, uint32_t); 224static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 225static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 226 uint32_t); 227static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 228static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 229 uint8_t, uint8_t); 230#ifdef URTWN_DEBUG 231static void urtwn_dump_rom_contents(struct urtwn_softc *, 232 uint8_t *, uint16_t); 233#endif 234static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 235 uint16_t); 236static int urtwn_efuse_switch_power(struct urtwn_softc *); 237static int urtwn_read_chipid(struct urtwn_softc *); 238static int urtwn_read_rom(struct urtwn_softc *); 239static int urtwn_r88e_read_rom(struct urtwn_softc *); 240static int urtwn_ra_init(struct urtwn_softc *); 241static void urtwn_init_beacon(struct urtwn_softc *, 242 struct urtwn_vap *); 243static int urtwn_setup_beacon(struct urtwn_softc *, 244 struct ieee80211_node *); 245static void urtwn_update_beacon(struct ieee80211vap *, int); 246static int urtwn_tx_beacon(struct urtwn_softc *sc, 247 struct urtwn_vap *); 248static int urtwn_key_alloc(struct ieee80211vap *, 249 struct ieee80211_key *, ieee80211_keyix *, 250 ieee80211_keyix *); 251static void urtwn_key_set_cb(struct urtwn_softc *, 252 union sec_param *); 253static void urtwn_key_del_cb(struct urtwn_softc *, 254 union sec_param *); 255static int urtwn_key_set(struct ieee80211vap *, 256 const struct ieee80211_key *); 257static int urtwn_key_delete(struct ieee80211vap *, 258 const struct ieee80211_key *); 259static void urtwn_tsf_task_adhoc(void *, int); 260static void urtwn_tsf_sync_enable(struct urtwn_softc *, 261 struct ieee80211vap *); 262static void urtwn_get_tsf(struct urtwn_softc *, uint64_t *); 263static void urtwn_set_led(struct urtwn_softc *, int, int); 264static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 265static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 266 struct mbuf *, int, 267 const struct ieee80211_rx_stats *, int, int); 268static int urtwn_newstate(struct ieee80211vap *, 269 enum ieee80211_state, int); 270static void urtwn_watchdog(void *); 271static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 272static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 273static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 274static int urtwn_tx_data(struct urtwn_softc *, 275 struct ieee80211_node *, struct mbuf *, 276 struct urtwn_data *); 277static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 278 uint8_t, struct urtwn_data *); 279static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 280static void urtwn_start(struct urtwn_softc *); 281static void urtwn_parent(struct ieee80211com *); 282static int urtwn_r92c_power_on(struct urtwn_softc *); 283static int urtwn_r88e_power_on(struct urtwn_softc *); 284static int urtwn_llt_init(struct urtwn_softc *); 285static void urtwn_fw_reset(struct urtwn_softc *); 286static void urtwn_r88e_fw_reset(struct urtwn_softc *); 287static int urtwn_fw_loadpage(struct urtwn_softc *, int, 288 const uint8_t *, int); 289static int urtwn_load_firmware(struct urtwn_softc *); 290static int urtwn_dma_init(struct urtwn_softc *); 291static int urtwn_mac_init(struct urtwn_softc *); 292static void urtwn_bb_init(struct urtwn_softc *); 293static void urtwn_rf_init(struct urtwn_softc *); 294static void urtwn_cam_init(struct urtwn_softc *); 295static int urtwn_cam_write(struct urtwn_softc *, uint32_t, 296 uint32_t); 297static void urtwn_pa_bias_init(struct urtwn_softc *); 298static void urtwn_rxfilter_init(struct urtwn_softc *); 299static void urtwn_edca_init(struct urtwn_softc *); 300static void urtwn_write_txpower(struct urtwn_softc *, int, 301 uint16_t[]); 302static void urtwn_get_txpower(struct urtwn_softc *, int, 303 struct ieee80211_channel *, 304 struct ieee80211_channel *, uint16_t[]); 305static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 306 struct ieee80211_channel *, 307 struct ieee80211_channel *, uint16_t[]); 308static void urtwn_set_txpower(struct urtwn_softc *, 309 struct ieee80211_channel *, 310 struct ieee80211_channel *); 311static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 312static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 313static void urtwn_scan_start(struct ieee80211com *); 314static void urtwn_scan_end(struct ieee80211com *); 315static void urtwn_set_channel(struct ieee80211com *); 316static int urtwn_wme_update(struct ieee80211com *); 317static void urtwn_set_promisc(struct urtwn_softc *); 318static void urtwn_update_promisc(struct ieee80211com *); 319static void urtwn_update_mcast(struct ieee80211com *); 320static struct ieee80211_node *urtwn_r88e_node_alloc(struct ieee80211vap *, 321 const uint8_t mac[IEEE80211_ADDR_LEN]); 322static void urtwn_r88e_newassoc(struct ieee80211_node *, int); 323static void urtwn_r88e_node_free(struct ieee80211_node *); 324static void urtwn_set_chan(struct urtwn_softc *, 325 struct ieee80211_channel *, 326 struct ieee80211_channel *); 327static void urtwn_iq_calib(struct urtwn_softc *); 328static void urtwn_lc_calib(struct urtwn_softc *); 329static int urtwn_init(struct urtwn_softc *); 330static void urtwn_stop(struct urtwn_softc *); 331static void urtwn_abort_xfers(struct urtwn_softc *); 332static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 333 const struct ieee80211_bpf_params *); 334static void urtwn_ms_delay(struct urtwn_softc *); 335 336/* Aliases. */ 337#define urtwn_bb_write urtwn_write_4 338#define urtwn_bb_read urtwn_read_4 339 340static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 341 [URTWN_BULK_RX] = { 342 .type = UE_BULK, 343 .endpoint = UE_ADDR_ANY, 344 .direction = UE_DIR_IN, 345 .bufsize = URTWN_RXBUFSZ, 346 .flags = { 347 .pipe_bof = 1, 348 .short_xfer_ok = 1 349 }, 350 .callback = urtwn_bulk_rx_callback, 351 }, 352 [URTWN_BULK_TX_BE] = { 353 .type = UE_BULK, 354 .endpoint = 0x03, 355 .direction = UE_DIR_OUT, 356 .bufsize = URTWN_TXBUFSZ, 357 .flags = { 358 .ext_buffer = 1, 359 .pipe_bof = 1, 360 .force_short_xfer = 1 361 }, 362 .callback = urtwn_bulk_tx_callback, 363 .timeout = URTWN_TX_TIMEOUT, /* ms */ 364 }, 365 [URTWN_BULK_TX_BK] = { 366 .type = UE_BULK, 367 .endpoint = 0x03, 368 .direction = UE_DIR_OUT, 369 .bufsize = URTWN_TXBUFSZ, 370 .flags = { 371 .ext_buffer = 1, 372 .pipe_bof = 1, 373 .force_short_xfer = 1, 374 }, 375 .callback = urtwn_bulk_tx_callback, 376 .timeout = URTWN_TX_TIMEOUT, /* ms */ 377 }, 378 [URTWN_BULK_TX_VI] = { 379 .type = UE_BULK, 380 .endpoint = 0x02, 381 .direction = UE_DIR_OUT, 382 .bufsize = URTWN_TXBUFSZ, 383 .flags = { 384 .ext_buffer = 1, 385 .pipe_bof = 1, 386 .force_short_xfer = 1 387 }, 388 .callback = urtwn_bulk_tx_callback, 389 .timeout = URTWN_TX_TIMEOUT, /* ms */ 390 }, 391 [URTWN_BULK_TX_VO] = { 392 .type = UE_BULK, 393 .endpoint = 0x02, 394 .direction = UE_DIR_OUT, 395 .bufsize = URTWN_TXBUFSZ, 396 .flags = { 397 .ext_buffer = 1, 398 .pipe_bof = 1, 399 .force_short_xfer = 1 400 }, 401 .callback = urtwn_bulk_tx_callback, 402 .timeout = URTWN_TX_TIMEOUT, /* ms */ 403 }, 404}; 405 406static const struct wme_to_queue { 407 uint16_t reg; 408 uint8_t qid; 409} wme2queue[WME_NUM_AC] = { 410 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 411 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 412 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 413 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 414}; 415 416static int 417urtwn_match(device_t self) 418{ 419 struct usb_attach_arg *uaa = device_get_ivars(self); 420 421 if (uaa->usb_mode != USB_MODE_HOST) 422 return (ENXIO); 423 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 424 return (ENXIO); 425 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 426 return (ENXIO); 427 428 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 429} 430 431static int 432urtwn_attach(device_t self) 433{ 434 struct usb_attach_arg *uaa = device_get_ivars(self); 435 struct urtwn_softc *sc = device_get_softc(self); 436 struct ieee80211com *ic = &sc->sc_ic; 437 uint8_t bands; 438 int error; 439 440 device_set_usb_desc(self); 441 sc->sc_udev = uaa->device; 442 sc->sc_dev = self; 443 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 444 sc->chip |= URTWN_CHIP_88E; 445 446 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 447 MTX_NETWORK_LOCK, MTX_DEF); 448 URTWN_CMDQ_LOCK_INIT(sc); 449 URTWN_NT_LOCK_INIT(sc); 450 callout_init(&sc->sc_watchdog_ch, 0); 451 mbufq_init(&sc->sc_snd, ifqmaxlen); 452 453 sc->sc_iface_index = URTWN_IFACE_INDEX; 454 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 455 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 456 if (error) { 457 device_printf(self, "could not allocate USB transfers, " 458 "err=%s\n", usbd_errstr(error)); 459 goto detach; 460 } 461 462 URTWN_LOCK(sc); 463 464 error = urtwn_read_chipid(sc); 465 if (error) { 466 device_printf(sc->sc_dev, "unsupported test chip\n"); 467 URTWN_UNLOCK(sc); 468 goto detach; 469 } 470 471 /* Determine number of Tx/Rx chains. */ 472 if (sc->chip & URTWN_CHIP_92C) { 473 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 474 sc->nrxchains = 2; 475 } else { 476 sc->ntxchains = 1; 477 sc->nrxchains = 1; 478 } 479 480 if (sc->chip & URTWN_CHIP_88E) 481 error = urtwn_r88e_read_rom(sc); 482 else 483 error = urtwn_read_rom(sc); 484 if (error != 0) { 485 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 486 __func__, error); 487 URTWN_UNLOCK(sc); 488 goto detach; 489 } 490 491 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 492 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 493 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 494 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 495 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 496 "8188CUS", sc->ntxchains, sc->nrxchains); 497 498 URTWN_UNLOCK(sc); 499 500 ic->ic_softc = sc; 501 ic->ic_name = device_get_nameunit(self); 502 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 503 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 504 505 /* set device capabilities */ 506 ic->ic_caps = 507 IEEE80211_C_STA /* station mode */ 508 | IEEE80211_C_MONITOR /* monitor mode */ 509 | IEEE80211_C_IBSS /* adhoc mode */ 510 | IEEE80211_C_HOSTAP /* hostap mode */ 511 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 512 | IEEE80211_C_SHSLOT /* short slot time supported */ 513 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 514 | IEEE80211_C_WPA /* 802.11i */ 515 | IEEE80211_C_WME /* 802.11e */ 516 ; 517 518 ic->ic_cryptocaps = 519 IEEE80211_CRYPTO_WEP | 520 IEEE80211_CRYPTO_TKIP | 521 IEEE80211_CRYPTO_AES_CCM; 522 523 bands = 0; 524 setbit(&bands, IEEE80211_MODE_11B); 525 setbit(&bands, IEEE80211_MODE_11G); 526 ieee80211_init_channels(ic, NULL, &bands); 527 528 ieee80211_ifattach(ic); 529 ic->ic_raw_xmit = urtwn_raw_xmit; 530 ic->ic_scan_start = urtwn_scan_start; 531 ic->ic_scan_end = urtwn_scan_end; 532 ic->ic_set_channel = urtwn_set_channel; 533 ic->ic_transmit = urtwn_transmit; 534 ic->ic_parent = urtwn_parent; 535 ic->ic_vap_create = urtwn_vap_create; 536 ic->ic_vap_delete = urtwn_vap_delete; 537 ic->ic_wme.wme_update = urtwn_wme_update; 538 ic->ic_update_promisc = urtwn_update_promisc; 539 ic->ic_update_mcast = urtwn_update_mcast; 540 if (sc->chip & URTWN_CHIP_88E) { 541 ic->ic_node_alloc = urtwn_r88e_node_alloc; 542 ic->ic_newassoc = urtwn_r88e_newassoc; 543 sc->sc_node_free = ic->ic_node_free; 544 ic->ic_node_free = urtwn_r88e_node_free; 545 } 546 547 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 548 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 549 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 550 URTWN_RX_RADIOTAP_PRESENT); 551 552 TASK_INIT(&sc->cmdq_task, 0, urtwn_cmdq_cb, sc); 553 554 if (bootverbose) 555 ieee80211_announce(ic); 556 557 return (0); 558 559detach: 560 urtwn_detach(self); 561 return (ENXIO); /* failure */ 562} 563 564static int 565urtwn_detach(device_t self) 566{ 567 struct urtwn_softc *sc = device_get_softc(self); 568 struct ieee80211com *ic = &sc->sc_ic; 569 unsigned int x; 570 571 /* Prevent further ioctls. */ 572 URTWN_LOCK(sc); 573 sc->sc_flags |= URTWN_DETACHED; 574 URTWN_UNLOCK(sc); 575 576 urtwn_stop(sc); 577 578 callout_drain(&sc->sc_watchdog_ch); 579 580 /* stop all USB transfers */ 581 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 582 583 /* Prevent further allocations from RX/TX data lists. */ 584 URTWN_LOCK(sc); 585 STAILQ_INIT(&sc->sc_tx_active); 586 STAILQ_INIT(&sc->sc_tx_inactive); 587 STAILQ_INIT(&sc->sc_tx_pending); 588 589 STAILQ_INIT(&sc->sc_rx_active); 590 STAILQ_INIT(&sc->sc_rx_inactive); 591 URTWN_UNLOCK(sc); 592 593 /* drain USB transfers */ 594 for (x = 0; x != URTWN_N_TRANSFER; x++) 595 usbd_transfer_drain(sc->sc_xfer[x]); 596 597 /* Free data buffers. */ 598 URTWN_LOCK(sc); 599 urtwn_free_tx_list(sc); 600 urtwn_free_rx_list(sc); 601 URTWN_UNLOCK(sc); 602 603 if (ic->ic_softc == sc) { 604 ieee80211_draintask(ic, &sc->cmdq_task); 605 ieee80211_ifdetach(ic); 606 } 607 608 URTWN_NT_LOCK_DESTROY(sc); 609 URTWN_CMDQ_LOCK_DESTROY(sc); 610 mtx_destroy(&sc->sc_mtx); 611 612 return (0); 613} 614 615static void 616urtwn_drain_mbufq(struct urtwn_softc *sc) 617{ 618 struct mbuf *m; 619 struct ieee80211_node *ni; 620 URTWN_ASSERT_LOCKED(sc); 621 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 622 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 623 m->m_pkthdr.rcvif = NULL; 624 ieee80211_free_node(ni); 625 m_freem(m); 626 } 627} 628 629static usb_error_t 630urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 631 void *data) 632{ 633 usb_error_t err; 634 int ntries = 10; 635 636 URTWN_ASSERT_LOCKED(sc); 637 638 while (ntries--) { 639 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 640 req, data, 0, NULL, 250 /* ms */); 641 if (err == 0) 642 break; 643 644 DPRINTFN(1, "Control request failed, %s (retrying)\n", 645 usbd_errstr(err)); 646 usb_pause_mtx(&sc->sc_mtx, hz / 100); 647 } 648 return (err); 649} 650 651static struct ieee80211vap * 652urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 653 enum ieee80211_opmode opmode, int flags, 654 const uint8_t bssid[IEEE80211_ADDR_LEN], 655 const uint8_t mac[IEEE80211_ADDR_LEN]) 656{ 657 struct urtwn_softc *sc = ic->ic_softc; 658 struct urtwn_vap *uvp; 659 struct ieee80211vap *vap; 660 661 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 662 return (NULL); 663 664 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 665 vap = &uvp->vap; 666 /* enable s/w bmiss handling for sta mode */ 667 668 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 669 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 670 /* out of memory */ 671 free(uvp, M_80211_VAP); 672 return (NULL); 673 } 674 675 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 676 urtwn_init_beacon(sc, uvp); 677 678 /* override state transition machine */ 679 uvp->newstate = vap->iv_newstate; 680 vap->iv_newstate = urtwn_newstate; 681 vap->iv_update_beacon = urtwn_update_beacon; 682 vap->iv_key_alloc = urtwn_key_alloc; 683 vap->iv_key_set = urtwn_key_set; 684 vap->iv_key_delete = urtwn_key_delete; 685 if (opmode == IEEE80211_M_IBSS) { 686 uvp->recv_mgmt = vap->iv_recv_mgmt; 687 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 688 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 689 } 690 691 if (URTWN_CHIP_HAS_RATECTL(sc)) 692 ieee80211_ratectl_init(vap); 693 /* complete setup */ 694 ieee80211_vap_attach(vap, ieee80211_media_change, 695 ieee80211_media_status, mac); 696 ic->ic_opmode = opmode; 697 return (vap); 698} 699 700static void 701urtwn_vap_delete(struct ieee80211vap *vap) 702{ 703 struct ieee80211com *ic = vap->iv_ic; 704 struct urtwn_softc *sc = ic->ic_softc; 705 struct urtwn_vap *uvp = URTWN_VAP(vap); 706 707 if (uvp->bcn_mbuf != NULL) 708 m_freem(uvp->bcn_mbuf); 709 if (vap->iv_opmode == IEEE80211_M_IBSS) 710 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 711 if (URTWN_CHIP_HAS_RATECTL(sc)) 712 ieee80211_ratectl_deinit(vap); 713 ieee80211_vap_detach(vap); 714 free(uvp, M_80211_VAP); 715} 716 717static struct mbuf * 718urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 719{ 720 struct ieee80211com *ic = &sc->sc_ic; 721 struct ieee80211_frame *wh; 722 struct mbuf *m; 723 struct r92c_rx_stat *stat; 724 uint32_t rxdw0, rxdw3; 725 uint8_t rate, cipher; 726 int8_t rssi = 0; 727 int infosz; 728 729 /* 730 * don't pass packets to the ieee80211 framework if the driver isn't 731 * RUNNING. 732 */ 733 if (!(sc->sc_flags & URTWN_RUNNING)) 734 return (NULL); 735 736 stat = (struct r92c_rx_stat *)buf; 737 rxdw0 = le32toh(stat->rxdw0); 738 rxdw3 = le32toh(stat->rxdw3); 739 740 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 741 /* 742 * This should not happen since we setup our Rx filter 743 * to not receive these frames. 744 */ 745 counter_u64_add(ic->ic_ierrors, 1); 746 return (NULL); 747 } 748 if (pktlen < sizeof(struct ieee80211_frame_ack) || 749 pktlen > MCLBYTES) { 750 counter_u64_add(ic->ic_ierrors, 1); 751 return (NULL); 752 } 753 754 rate = MS(rxdw3, R92C_RXDW3_RATE); 755 cipher = MS(rxdw0, R92C_RXDW0_CIPHER); 756 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 757 758 /* Get RSSI from PHY status descriptor if present. */ 759 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 760 if (sc->chip & URTWN_CHIP_88E) 761 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 762 else 763 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 764 /* Update our average RSSI. */ 765 urtwn_update_avgrssi(sc, rate, rssi); 766 } 767 768 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 769 if (m == NULL) { 770 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 771 return (NULL); 772 } 773 774 /* Finalize mbuf. */ 775 memcpy(mtod(m, uint8_t *), (uint8_t *)&stat[1] + infosz, pktlen); 776 m->m_pkthdr.len = m->m_len = pktlen; 777 wh = mtod(m, struct ieee80211_frame *); 778 779 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 780 cipher != R92C_CAM_ALGO_NONE) { 781 m->m_flags |= M_WEP; 782 } 783 784 if (ieee80211_radiotap_active(ic)) { 785 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 786 787 tap->wr_flags = 0; 788 789 urtwn_get_tsf(sc, &tap->wr_tsft); 790 if (__predict_false(le32toh((uint32_t)tap->wr_tsft) < 791 le32toh(stat->rxdw5))) { 792 tap->wr_tsft = le32toh(tap->wr_tsft >> 32) - 1; 793 tap->wr_tsft = (uint64_t)htole32(tap->wr_tsft) << 32; 794 } else 795 tap->wr_tsft &= 0xffffffff00000000; 796 tap->wr_tsft += stat->rxdw5; 797 798 /* Map HW rate index to 802.11 rate. */ 799 if (!(rxdw3 & R92C_RXDW3_HT)) { 800 tap->wr_rate = ridx2rate[rate]; 801 } else if (rate >= 12) { /* MCS0~15. */ 802 /* Bit 7 set means HT MCS instead of rate. */ 803 tap->wr_rate = 0x80 | (rate - 12); 804 } 805 tap->wr_dbm_antsignal = rssi; 806 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 807 } 808 809 *rssi_p = rssi; 810 811 return (m); 812} 813 814static struct mbuf * 815urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 816 int8_t *nf) 817{ 818 struct urtwn_softc *sc = data->sc; 819 struct ieee80211com *ic = &sc->sc_ic; 820 struct r92c_rx_stat *stat; 821 uint8_t *buf; 822 int len; 823 824 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 825 826 if (len < sizeof(*stat)) { 827 counter_u64_add(ic->ic_ierrors, 1); 828 return (NULL); 829 } 830 831 buf = data->buf; 832 stat = (struct r92c_rx_stat *)buf; 833 834 if (sc->chip & URTWN_CHIP_88E) { 835 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 836 837 switch (report_sel) { 838 case R88E_RXDW3_RPT_RX: 839 return (urtwn_rxeof(sc, buf, len, rssi, nf)); 840 case R88E_RXDW3_RPT_TX1: 841 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 842 break; 843 default: 844 DPRINTFN(7, "case %d was not handled\n", report_sel); 845 break; 846 } 847 } else 848 return (urtwn_rxeof(sc, buf, len, rssi, nf)); 849 850 return (NULL); 851} 852 853static struct mbuf * 854urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len, int *rssi, 855 int8_t *nf) 856{ 857 struct r92c_rx_stat *stat; 858 struct mbuf *m, *m0 = NULL, *prevm = NULL; 859 uint32_t rxdw0; 860 int totlen, pktlen, infosz, npkts; 861 862 /* Get the number of encapsulated frames. */ 863 stat = (struct r92c_rx_stat *)buf; 864 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 865 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 866 867 /* Process all of them. */ 868 while (npkts-- > 0) { 869 if (len < sizeof(*stat)) 870 break; 871 stat = (struct r92c_rx_stat *)buf; 872 rxdw0 = le32toh(stat->rxdw0); 873 874 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 875 if (pktlen == 0) 876 break; 877 878 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 879 880 /* Make sure everything fits in xfer. */ 881 totlen = sizeof(*stat) + infosz + pktlen; 882 if (totlen > len) 883 break; 884 885 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 886 if (m0 == NULL) 887 m0 = m; 888 if (prevm == NULL) 889 prevm = m; 890 else { 891 prevm->m_next = m; 892 prevm = m; 893 } 894 895 /* Next chunk is 128-byte aligned. */ 896 totlen = (totlen + 127) & ~127; 897 buf += totlen; 898 len -= totlen; 899 } 900 901 return (m0); 902} 903 904static void 905urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 906{ 907 struct r88e_tx_rpt_ccx *rpt = arg; 908 struct ieee80211vap *vap; 909 struct ieee80211_node *ni; 910 uint8_t macid; 911 int ntries; 912 913 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 914 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 915 916 URTWN_NT_LOCK(sc); 917 ni = sc->node_list[macid]; 918 if (ni != NULL) { 919 vap = ni->ni_vap; 920 921 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 922 ieee80211_ratectl_tx_complete(vap, ni, 923 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 924 } else { 925 ieee80211_ratectl_tx_complete(vap, ni, 926 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 927 } 928 } else 929 DPRINTFN(8, "macid %d, ni is NULL\n", macid); 930 URTWN_NT_UNLOCK(sc); 931} 932 933static void 934urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 935{ 936 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 937 struct ieee80211com *ic = &sc->sc_ic; 938 struct ieee80211_frame_min *wh; 939 struct ieee80211_node *ni; 940 struct mbuf *m = NULL, *next; 941 struct urtwn_data *data; 942 int8_t nf; 943 int rssi = 1; 944 945 URTWN_ASSERT_LOCKED(sc); 946 947 switch (USB_GET_STATE(xfer)) { 948 case USB_ST_TRANSFERRED: 949 data = STAILQ_FIRST(&sc->sc_rx_active); 950 if (data == NULL) 951 goto tr_setup; 952 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 953 m = urtwn_report_intr(xfer, data, &rssi, &nf); 954 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 955 /* FALLTHROUGH */ 956 case USB_ST_SETUP: 957tr_setup: 958 data = STAILQ_FIRST(&sc->sc_rx_inactive); 959 if (data == NULL) { 960 KASSERT(m == NULL, ("mbuf isn't NULL")); 961 return; 962 } 963 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 964 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 965 usbd_xfer_set_frame_data(xfer, 0, data->buf, 966 usbd_xfer_max_len(xfer)); 967 usbd_transfer_submit(xfer); 968 969 /* 970 * To avoid LOR we should unlock our private mutex here to call 971 * ieee80211_input() because here is at the end of a USB 972 * callback and safe to unlock. 973 */ 974 URTWN_UNLOCK(sc); 975 while (m != NULL) { 976 next = m->m_next; 977 m->m_next = NULL; 978 wh = mtod(m, struct ieee80211_frame_min *); 979 if (m->m_len >= sizeof(*wh)) 980 ni = ieee80211_find_rxnode(ic, wh); 981 else 982 ni = NULL; 983 nf = URTWN_NOISE_FLOOR; 984 if (ni != NULL) { 985 (void)ieee80211_input(ni, m, rssi - nf, nf); 986 ieee80211_free_node(ni); 987 } else { 988 (void)ieee80211_input_all(ic, m, rssi - nf, 989 nf); 990 } 991 m = next; 992 } 993 URTWN_LOCK(sc); 994 break; 995 default: 996 /* needs it to the inactive queue due to a error. */ 997 data = STAILQ_FIRST(&sc->sc_rx_active); 998 if (data != NULL) { 999 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1000 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1001 } 1002 if (error != USB_ERR_CANCELLED) { 1003 usbd_xfer_set_stall(xfer); 1004 counter_u64_add(ic->ic_ierrors, 1); 1005 goto tr_setup; 1006 } 1007 break; 1008 } 1009} 1010 1011static void 1012urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 1013{ 1014 1015 URTWN_ASSERT_LOCKED(sc); 1016 1017 if (data->ni != NULL) /* not a beacon frame */ 1018 ieee80211_tx_complete(data->ni, data->m, status); 1019 1020 data->ni = NULL; 1021 data->m = NULL; 1022 1023 sc->sc_txtimer = 0; 1024 1025 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 1026} 1027 1028static int 1029urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1030 int ndata, int maxsz) 1031{ 1032 int i, error; 1033 1034 for (i = 0; i < ndata; i++) { 1035 struct urtwn_data *dp = &data[i]; 1036 dp->sc = sc; 1037 dp->m = NULL; 1038 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1039 if (dp->buf == NULL) { 1040 device_printf(sc->sc_dev, 1041 "could not allocate buffer\n"); 1042 error = ENOMEM; 1043 goto fail; 1044 } 1045 dp->ni = NULL; 1046 } 1047 1048 return (0); 1049fail: 1050 urtwn_free_list(sc, data, ndata); 1051 return (error); 1052} 1053 1054static int 1055urtwn_alloc_rx_list(struct urtwn_softc *sc) 1056{ 1057 int error, i; 1058 1059 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1060 URTWN_RXBUFSZ); 1061 if (error != 0) 1062 return (error); 1063 1064 STAILQ_INIT(&sc->sc_rx_active); 1065 STAILQ_INIT(&sc->sc_rx_inactive); 1066 1067 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1068 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1069 1070 return (0); 1071} 1072 1073static int 1074urtwn_alloc_tx_list(struct urtwn_softc *sc) 1075{ 1076 int error, i; 1077 1078 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1079 URTWN_TXBUFSZ); 1080 if (error != 0) 1081 return (error); 1082 1083 STAILQ_INIT(&sc->sc_tx_active); 1084 STAILQ_INIT(&sc->sc_tx_inactive); 1085 STAILQ_INIT(&sc->sc_tx_pending); 1086 1087 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1088 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1089 1090 return (0); 1091} 1092 1093static void 1094urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1095{ 1096 int i; 1097 1098 for (i = 0; i < ndata; i++) { 1099 struct urtwn_data *dp = &data[i]; 1100 1101 if (dp->buf != NULL) { 1102 free(dp->buf, M_USBDEV); 1103 dp->buf = NULL; 1104 } 1105 if (dp->ni != NULL) { 1106 ieee80211_free_node(dp->ni); 1107 dp->ni = NULL; 1108 } 1109 } 1110} 1111 1112static void 1113urtwn_free_rx_list(struct urtwn_softc *sc) 1114{ 1115 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1116} 1117 1118static void 1119urtwn_free_tx_list(struct urtwn_softc *sc) 1120{ 1121 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1122} 1123 1124static void 1125urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1126{ 1127 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1128 struct urtwn_data *data; 1129 1130 URTWN_ASSERT_LOCKED(sc); 1131 1132 switch (USB_GET_STATE(xfer)){ 1133 case USB_ST_TRANSFERRED: 1134 data = STAILQ_FIRST(&sc->sc_tx_active); 1135 if (data == NULL) 1136 goto tr_setup; 1137 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1138 urtwn_txeof(sc, data, 0); 1139 /* FALLTHROUGH */ 1140 case USB_ST_SETUP: 1141tr_setup: 1142 data = STAILQ_FIRST(&sc->sc_tx_pending); 1143 if (data == NULL) { 1144 DPRINTF("%s: empty pending queue\n", __func__); 1145 goto finish; 1146 } 1147 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1148 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1149 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1150 usbd_transfer_submit(xfer); 1151 break; 1152 default: 1153 data = STAILQ_FIRST(&sc->sc_tx_active); 1154 if (data == NULL) 1155 goto tr_setup; 1156 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1157 urtwn_txeof(sc, data, 1); 1158 if (error != USB_ERR_CANCELLED) { 1159 usbd_xfer_set_stall(xfer); 1160 goto tr_setup; 1161 } 1162 break; 1163 } 1164finish: 1165 /* Kick-start more transmit */ 1166 urtwn_start(sc); 1167} 1168 1169static struct urtwn_data * 1170_urtwn_getbuf(struct urtwn_softc *sc) 1171{ 1172 struct urtwn_data *bf; 1173 1174 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1175 if (bf != NULL) 1176 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1177 else 1178 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 1179 return (bf); 1180} 1181 1182static struct urtwn_data * 1183urtwn_getbuf(struct urtwn_softc *sc) 1184{ 1185 struct urtwn_data *bf; 1186 1187 URTWN_ASSERT_LOCKED(sc); 1188 1189 bf = _urtwn_getbuf(sc); 1190 if (bf == NULL) 1191 DPRINTF("%s: stop queue\n", __func__); 1192 return (bf); 1193} 1194 1195static usb_error_t 1196urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1197 int len) 1198{ 1199 usb_device_request_t req; 1200 1201 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1202 req.bRequest = R92C_REQ_REGS; 1203 USETW(req.wValue, addr); 1204 USETW(req.wIndex, 0); 1205 USETW(req.wLength, len); 1206 return (urtwn_do_request(sc, &req, buf)); 1207} 1208 1209static usb_error_t 1210urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1211{ 1212 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1213} 1214 1215static usb_error_t 1216urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1217{ 1218 val = htole16(val); 1219 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1220} 1221 1222static usb_error_t 1223urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1224{ 1225 val = htole32(val); 1226 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1227} 1228 1229static usb_error_t 1230urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1231 int len) 1232{ 1233 usb_device_request_t req; 1234 1235 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1236 req.bRequest = R92C_REQ_REGS; 1237 USETW(req.wValue, addr); 1238 USETW(req.wIndex, 0); 1239 USETW(req.wLength, len); 1240 return (urtwn_do_request(sc, &req, buf)); 1241} 1242 1243static uint8_t 1244urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1245{ 1246 uint8_t val; 1247 1248 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1249 return (0xff); 1250 return (val); 1251} 1252 1253static uint16_t 1254urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1255{ 1256 uint16_t val; 1257 1258 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1259 return (0xffff); 1260 return (le16toh(val)); 1261} 1262 1263static uint32_t 1264urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1265{ 1266 uint32_t val; 1267 1268 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1269 return (0xffffffff); 1270 return (le32toh(val)); 1271} 1272 1273static int 1274urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1275{ 1276 struct r92c_fw_cmd cmd; 1277 usb_error_t error; 1278 int ntries; 1279 1280 /* Wait for current FW box to be empty. */ 1281 for (ntries = 0; ntries < 100; ntries++) { 1282 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1283 break; 1284 urtwn_ms_delay(sc); 1285 } 1286 if (ntries == 100) { 1287 device_printf(sc->sc_dev, 1288 "could not send firmware command\n"); 1289 return (ETIMEDOUT); 1290 } 1291 memset(&cmd, 0, sizeof(cmd)); 1292 cmd.id = id; 1293 if (len > 3) 1294 cmd.id |= R92C_CMD_FLAG_EXT; 1295 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1296 memcpy(cmd.msg, buf, len); 1297 1298 /* Write the first word last since that will trigger the FW. */ 1299 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1300 (uint8_t *)&cmd + 4, 2); 1301 if (error != USB_ERR_NORMAL_COMPLETION) 1302 return (EIO); 1303 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1304 (uint8_t *)&cmd + 0, 4); 1305 if (error != USB_ERR_NORMAL_COMPLETION) 1306 return (EIO); 1307 1308 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1309 return (0); 1310} 1311 1312static void 1313urtwn_cmdq_cb(void *arg, int pending) 1314{ 1315 struct urtwn_softc *sc = arg; 1316 struct urtwn_cmdq *item; 1317 1318 /* 1319 * Device must be powered on (via urtwn_power_on()) 1320 * before any command may be sent. 1321 */ 1322 URTWN_LOCK(sc); 1323 if (!(sc->sc_flags & URTWN_RUNNING)) { 1324 URTWN_UNLOCK(sc); 1325 return; 1326 } 1327 1328 URTWN_CMDQ_LOCK(sc); 1329 while (sc->cmdq[sc->cmdq_first].func != NULL) { 1330 item = &sc->cmdq[sc->cmdq_first]; 1331 sc->cmdq_first = (sc->cmdq_first + 1) % URTWN_CMDQ_SIZE; 1332 URTWN_CMDQ_UNLOCK(sc); 1333 1334 item->func(sc, &item->data); 1335 1336 URTWN_CMDQ_LOCK(sc); 1337 memset(item, 0, sizeof (*item)); 1338 } 1339 URTWN_CMDQ_UNLOCK(sc); 1340 URTWN_UNLOCK(sc); 1341} 1342 1343static int 1344urtwn_cmd_sleepable(struct urtwn_softc *sc, const void *ptr, size_t len, 1345 CMD_FUNC_PROTO) 1346{ 1347 struct ieee80211com *ic = &sc->sc_ic; 1348 1349 KASSERT(len <= sizeof(union sec_param), ("buffer overflow")); 1350 1351 URTWN_CMDQ_LOCK(sc); 1352 if (sc->cmdq[sc->cmdq_last].func != NULL) { 1353 device_printf(sc->sc_dev, "%s: cmdq overflow\n", __func__); 1354 URTWN_CMDQ_UNLOCK(sc); 1355 1356 return (EAGAIN); 1357 } 1358 1359 if (ptr != NULL) 1360 memcpy(&sc->cmdq[sc->cmdq_last].data, ptr, len); 1361 sc->cmdq[sc->cmdq_last].func = func; 1362 sc->cmdq_last = (sc->cmdq_last + 1) % URTWN_CMDQ_SIZE; 1363 URTWN_CMDQ_UNLOCK(sc); 1364 1365 ieee80211_runtask(ic, &sc->cmdq_task); 1366 1367 return (0); 1368} 1369 1370static __inline void 1371urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1372{ 1373 1374 sc->sc_rf_write(sc, chain, addr, val); 1375} 1376 1377static void 1378urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1379 uint32_t val) 1380{ 1381 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1382 SM(R92C_LSSI_PARAM_ADDR, addr) | 1383 SM(R92C_LSSI_PARAM_DATA, val)); 1384} 1385 1386static void 1387urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1388uint32_t val) 1389{ 1390 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1391 SM(R88E_LSSI_PARAM_ADDR, addr) | 1392 SM(R92C_LSSI_PARAM_DATA, val)); 1393} 1394 1395static uint32_t 1396urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1397{ 1398 uint32_t reg[R92C_MAX_CHAINS], val; 1399 1400 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1401 if (chain != 0) 1402 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1403 1404 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1405 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1406 urtwn_ms_delay(sc); 1407 1408 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1409 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1410 R92C_HSSI_PARAM2_READ_EDGE); 1411 urtwn_ms_delay(sc); 1412 1413 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1414 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1415 urtwn_ms_delay(sc); 1416 1417 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1418 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1419 else 1420 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1421 return (MS(val, R92C_LSSI_READBACK_DATA)); 1422} 1423 1424static int 1425urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1426{ 1427 usb_error_t error; 1428 int ntries; 1429 1430 error = urtwn_write_4(sc, R92C_LLT_INIT, 1431 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1432 SM(R92C_LLT_INIT_ADDR, addr) | 1433 SM(R92C_LLT_INIT_DATA, data)); 1434 if (error != USB_ERR_NORMAL_COMPLETION) 1435 return (EIO); 1436 /* Wait for write operation to complete. */ 1437 for (ntries = 0; ntries < 20; ntries++) { 1438 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1439 R92C_LLT_INIT_OP_NO_ACTIVE) 1440 return (0); 1441 urtwn_ms_delay(sc); 1442 } 1443 return (ETIMEDOUT); 1444} 1445 1446static int 1447urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1448{ 1449 uint32_t reg; 1450 usb_error_t error; 1451 int ntries; 1452 1453 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1454 return (EFAULT); 1455 1456 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1457 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1458 reg &= ~R92C_EFUSE_CTRL_VALID; 1459 1460 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1461 if (error != USB_ERR_NORMAL_COMPLETION) 1462 return (EIO); 1463 /* Wait for read operation to complete. */ 1464 for (ntries = 0; ntries < 100; ntries++) { 1465 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1466 if (reg & R92C_EFUSE_CTRL_VALID) 1467 break; 1468 urtwn_ms_delay(sc); 1469 } 1470 if (ntries == 100) { 1471 device_printf(sc->sc_dev, 1472 "could not read efuse byte at address 0x%x\n", 1473 sc->last_rom_addr); 1474 return (ETIMEDOUT); 1475 } 1476 1477 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1478 sc->last_rom_addr++; 1479 1480 return (0); 1481} 1482 1483static int 1484urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1485 uint8_t msk) 1486{ 1487 uint8_t reg; 1488 int i, error; 1489 1490 for (i = 0; i < 4; i++) { 1491 if (msk & (1 << i)) 1492 continue; 1493 error = urtwn_efuse_read_next(sc, ®); 1494 if (error != 0) 1495 return (error); 1496 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2, reg); 1497 rom[off * 8 + i * 2 + 0] = reg; 1498 1499 error = urtwn_efuse_read_next(sc, ®); 1500 if (error != 0) 1501 return (error); 1502 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2 + 1, reg); 1503 rom[off * 8 + i * 2 + 1] = reg; 1504 } 1505 1506 return (0); 1507} 1508 1509#ifdef URTWN_DEBUG 1510static void 1511urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1512{ 1513 int i; 1514 1515 /* Dump ROM contents. */ 1516 device_printf(sc->sc_dev, "%s:", __func__); 1517 for (i = 0; i < size; i++) { 1518 if (i % 32 == 0) 1519 printf("\n%03X: ", i); 1520 else if (i % 4 == 0) 1521 printf(" "); 1522 1523 printf("%02X", rom[i]); 1524 } 1525 printf("\n"); 1526} 1527#endif 1528 1529static int 1530urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1531{ 1532#define URTWN_CHK(res) do { \ 1533 if ((error = res) != 0) \ 1534 goto end; \ 1535} while(0) 1536 uint8_t msk, off, reg; 1537 int error; 1538 1539 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1540 1541 /* Read full ROM image. */ 1542 sc->last_rom_addr = 0; 1543 memset(rom, 0xff, size); 1544 1545 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1546 while (reg != 0xff) { 1547 /* check for extended header */ 1548 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1549 off = reg >> 5; 1550 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1551 1552 if ((reg & 0x0f) != 0x0f) 1553 off = ((reg & 0xf0) >> 1) | off; 1554 else 1555 continue; 1556 } else 1557 off = reg >> 4; 1558 msk = reg & 0xf; 1559 1560 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1561 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1562 } 1563 1564end: 1565 1566#ifdef URTWN_DEBUG 1567 if (urtwn_debug >= 2) 1568 urtwn_dump_rom_contents(sc, rom, size); 1569#endif 1570 1571 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1572 1573 if (error != 0) { 1574 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1575 __func__); 1576 } 1577 1578 return (error); 1579#undef URTWN_CHK 1580} 1581 1582static int 1583urtwn_efuse_switch_power(struct urtwn_softc *sc) 1584{ 1585 usb_error_t error; 1586 uint32_t reg; 1587 1588 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1589 if (error != USB_ERR_NORMAL_COMPLETION) 1590 return (EIO); 1591 1592 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1593 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1594 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1595 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1596 if (error != USB_ERR_NORMAL_COMPLETION) 1597 return (EIO); 1598 } 1599 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1600 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1601 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1602 reg | R92C_SYS_FUNC_EN_ELDR); 1603 if (error != USB_ERR_NORMAL_COMPLETION) 1604 return (EIO); 1605 } 1606 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1607 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1608 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1609 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1610 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1611 if (error != USB_ERR_NORMAL_COMPLETION) 1612 return (EIO); 1613 } 1614 1615 return (0); 1616} 1617 1618static int 1619urtwn_read_chipid(struct urtwn_softc *sc) 1620{ 1621 uint32_t reg; 1622 1623 if (sc->chip & URTWN_CHIP_88E) 1624 return (0); 1625 1626 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1627 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1628 return (EIO); 1629 1630 if (reg & R92C_SYS_CFG_TYPE_92C) { 1631 sc->chip |= URTWN_CHIP_92C; 1632 /* Check if it is a castrated 8192C. */ 1633 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1634 R92C_HPON_FSM_CHIP_BONDING_ID) == 1635 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1636 sc->chip |= URTWN_CHIP_92C_1T2R; 1637 } 1638 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1639 sc->chip |= URTWN_CHIP_UMC; 1640 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1641 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1642 } 1643 return (0); 1644} 1645 1646static int 1647urtwn_read_rom(struct urtwn_softc *sc) 1648{ 1649 struct r92c_rom *rom = &sc->rom.r92c_rom; 1650 int error; 1651 1652 /* Read full ROM image. */ 1653 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1654 if (error != 0) 1655 return (error); 1656 1657 /* XXX Weird but this is what the vendor driver does. */ 1658 sc->last_rom_addr = 0x1fa; 1659 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1660 if (error != 0) 1661 return (error); 1662 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1663 1664 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1665 1666 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1667 DPRINTF("regulatory type=%d\n", sc->regulatory); 1668 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1669 1670 sc->sc_rf_write = urtwn_r92c_rf_write; 1671 sc->sc_power_on = urtwn_r92c_power_on; 1672 1673 return (0); 1674} 1675 1676static int 1677urtwn_r88e_read_rom(struct urtwn_softc *sc) 1678{ 1679 uint8_t *rom = sc->rom.r88e_rom; 1680 uint16_t addr; 1681 int error, i; 1682 1683 error = urtwn_efuse_read(sc, rom, sizeof(sc->rom.r88e_rom)); 1684 if (error != 0) 1685 return (error); 1686 1687 addr = 0x10; 1688 for (i = 0; i < 6; i++) 1689 sc->cck_tx_pwr[i] = rom[addr++]; 1690 for (i = 0; i < 5; i++) 1691 sc->ht40_tx_pwr[i] = rom[addr++]; 1692 sc->bw20_tx_pwr_diff = (rom[addr] & 0xf0) >> 4; 1693 if (sc->bw20_tx_pwr_diff & 0x08) 1694 sc->bw20_tx_pwr_diff |= 0xf0; 1695 sc->ofdm_tx_pwr_diff = (rom[addr] & 0xf); 1696 if (sc->ofdm_tx_pwr_diff & 0x08) 1697 sc->ofdm_tx_pwr_diff |= 0xf0; 1698 sc->regulatory = MS(rom[0xc1], R92C_ROM_RF1_REGULATORY); 1699 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &rom[0xd7]); 1700 1701 sc->sc_rf_write = urtwn_r88e_rf_write; 1702 sc->sc_power_on = urtwn_r88e_power_on; 1703 1704 return (0); 1705} 1706 1707/* 1708 * Initialize rate adaptation in firmware. 1709 */ 1710static int 1711urtwn_ra_init(struct urtwn_softc *sc) 1712{ 1713 struct ieee80211com *ic = &sc->sc_ic; 1714 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1715 struct ieee80211_node *ni; 1716 struct ieee80211_rateset *rs; 1717 struct r92c_fw_cmd_macid_cfg cmd; 1718 uint32_t rates, basicrates; 1719 uint8_t mode; 1720 int maxrate, maxbasicrate, error, i, j; 1721 1722 ni = ieee80211_ref_node(vap->iv_bss); 1723 rs = &ni->ni_rates; 1724 1725 /* Get normal and basic rates mask. */ 1726 rates = basicrates = 0; 1727 maxrate = maxbasicrate = 0; 1728 for (i = 0; i < rs->rs_nrates; i++) { 1729 /* Convert 802.11 rate to HW rate index. */ 1730 for (j = 0; j < nitems(ridx2rate); j++) 1731 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1732 ridx2rate[j]) 1733 break; 1734 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1735 continue; 1736 rates |= 1 << j; 1737 if (j > maxrate) 1738 maxrate = j; 1739 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1740 basicrates |= 1 << j; 1741 if (j > maxbasicrate) 1742 maxbasicrate = j; 1743 } 1744 } 1745 if (ic->ic_curmode == IEEE80211_MODE_11B) 1746 mode = R92C_RAID_11B; 1747 else 1748 mode = R92C_RAID_11BG; 1749 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1750 mode, rates, basicrates); 1751 1752 /* Set rates mask for group addressed frames. */ 1753 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1754 cmd.mask = htole32(mode << 28 | basicrates); 1755 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1756 if (error != 0) { 1757 ieee80211_free_node(ni); 1758 device_printf(sc->sc_dev, 1759 "could not add broadcast station\n"); 1760 return (error); 1761 } 1762 /* Set initial MRR rate. */ 1763 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1764 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1765 maxbasicrate); 1766 1767 /* Set rates mask for unicast frames. */ 1768 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1769 cmd.mask = htole32(mode << 28 | rates); 1770 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1771 if (error != 0) { 1772 ieee80211_free_node(ni); 1773 device_printf(sc->sc_dev, "could not add BSS station\n"); 1774 return (error); 1775 } 1776 /* Set initial MRR rate. */ 1777 DPRINTF("maxrate=%d\n", maxrate); 1778 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1779 maxrate); 1780 1781 /* Indicate highest supported rate. */ 1782 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1783 ieee80211_free_node(ni); 1784 1785 return (0); 1786} 1787 1788static void 1789urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1790{ 1791 struct r92c_tx_desc *txd = &uvp->bcn_desc; 1792 1793 txd->txdw0 = htole32( 1794 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 1795 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1796 txd->txdw1 = htole32( 1797 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 1798 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1799 1800 if (sc->chip & URTWN_CHIP_88E) { 1801 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 1802 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 1803 } else { 1804 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 1805 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 1806 } 1807 1808 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 1809 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 1810} 1811 1812static int 1813urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 1814{ 1815 struct ieee80211vap *vap = ni->ni_vap; 1816 struct urtwn_vap *uvp = URTWN_VAP(vap); 1817 struct mbuf *m; 1818 int error; 1819 1820 URTWN_ASSERT_LOCKED(sc); 1821 1822 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 1823 return (EINVAL); 1824 1825 m = ieee80211_beacon_alloc(ni); 1826 if (m == NULL) { 1827 device_printf(sc->sc_dev, 1828 "%s: could not allocate beacon frame\n", __func__); 1829 return (ENOMEM); 1830 } 1831 1832 if (uvp->bcn_mbuf != NULL) 1833 m_freem(uvp->bcn_mbuf); 1834 1835 uvp->bcn_mbuf = m; 1836 1837 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1838 return (error); 1839 1840 /* XXX bcnq stuck workaround */ 1841 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1842 return (error); 1843 1844 return (0); 1845} 1846 1847static void 1848urtwn_update_beacon(struct ieee80211vap *vap, int item) 1849{ 1850 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1851 struct urtwn_vap *uvp = URTWN_VAP(vap); 1852 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 1853 struct ieee80211_node *ni = vap->iv_bss; 1854 int mcast = 0; 1855 1856 URTWN_LOCK(sc); 1857 if (uvp->bcn_mbuf == NULL) { 1858 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 1859 if (uvp->bcn_mbuf == NULL) { 1860 device_printf(sc->sc_dev, 1861 "%s: could not allocate beacon frame\n", __func__); 1862 URTWN_UNLOCK(sc); 1863 return; 1864 } 1865 } 1866 URTWN_UNLOCK(sc); 1867 1868 if (item == IEEE80211_BEACON_TIM) 1869 mcast = 1; /* XXX */ 1870 1871 setbit(bo->bo_flags, item); 1872 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 1873 1874 URTWN_LOCK(sc); 1875 urtwn_tx_beacon(sc, uvp); 1876 URTWN_UNLOCK(sc); 1877} 1878 1879/* 1880 * Push a beacon frame into the chip. Beacon will 1881 * be repeated by the chip every R92C_BCN_INTERVAL. 1882 */ 1883static int 1884urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1885{ 1886 struct r92c_tx_desc *desc = &uvp->bcn_desc; 1887 struct urtwn_data *bf; 1888 1889 URTWN_ASSERT_LOCKED(sc); 1890 1891 bf = urtwn_getbuf(sc); 1892 if (bf == NULL) 1893 return (ENOMEM); 1894 1895 memcpy(bf->buf, desc, sizeof(*desc)); 1896 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 1897 1898 sc->sc_txtimer = 5; 1899 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1900 1901 return (0); 1902} 1903 1904static int 1905urtwn_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 1906 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1907{ 1908 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1909 uint8_t i; 1910 1911 if (!(&vap->iv_nw_keys[0] <= k && 1912 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 1913 if (!(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 1914 URTWN_LOCK(sc); 1915 /* 1916 * First 4 slots for group keys, 1917 * what is left - for pairwise. 1918 * XXX incompatible with IBSS RSN. 1919 */ 1920 for (i = IEEE80211_WEP_NKID; 1921 i < R92C_CAM_ENTRY_COUNT; i++) { 1922 if ((sc->keys_bmap & (1 << i)) == 0) { 1923 sc->keys_bmap |= 1 << i; 1924 *keyix = i; 1925 break; 1926 } 1927 } 1928 URTWN_UNLOCK(sc); 1929 if (i == R92C_CAM_ENTRY_COUNT) { 1930 device_printf(sc->sc_dev, 1931 "%s: no free space in the key table\n", 1932 __func__); 1933 return 0; 1934 } 1935 } else 1936 *keyix = 0; 1937 } else { 1938 *keyix = k - vap->iv_nw_keys; 1939 } 1940 *rxkeyix = *keyix; 1941 return 1; 1942} 1943 1944static void 1945urtwn_key_set_cb(struct urtwn_softc *sc, union sec_param *data) 1946{ 1947 struct ieee80211_key *k = &data->key; 1948 uint8_t algo, keyid; 1949 int i, error; 1950 1951 if (k->wk_keyix < IEEE80211_WEP_NKID) 1952 keyid = k->wk_keyix; 1953 else 1954 keyid = 0; 1955 1956 /* Map net80211 cipher to HW crypto algorithm. */ 1957 switch (k->wk_cipher->ic_cipher) { 1958 case IEEE80211_CIPHER_WEP: 1959 if (k->wk_keylen < 8) 1960 algo = R92C_CAM_ALGO_WEP40; 1961 else 1962 algo = R92C_CAM_ALGO_WEP104; 1963 break; 1964 case IEEE80211_CIPHER_TKIP: 1965 algo = R92C_CAM_ALGO_TKIP; 1966 break; 1967 case IEEE80211_CIPHER_AES_CCM: 1968 algo = R92C_CAM_ALGO_AES; 1969 break; 1970 default: 1971 device_printf(sc->sc_dev, "%s: undefined cipher %d\n", 1972 __func__, k->wk_cipher->ic_cipher); 1973 return; 1974 } 1975 1976 DPRINTFN(9, "keyix %d, keyid %d, algo %d/%d, flags %04X, len %d, " 1977 "macaddr %s\n", k->wk_keyix, keyid, k->wk_cipher->ic_cipher, algo, 1978 k->wk_flags, k->wk_keylen, ether_sprintf(k->wk_macaddr)); 1979 1980 /* Write key. */ 1981 for (i = 0; i < 4; i++) { 1982 error = urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 1983 LE_READ_4(&k->wk_key[i * 4])); 1984 if (error != 0) 1985 goto fail; 1986 } 1987 1988 /* Write CTL0 last since that will validate the CAM entry. */ 1989 error = urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 1990 LE_READ_4(&k->wk_macaddr[2])); 1991 if (error != 0) 1992 goto fail; 1993 error = urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 1994 SM(R92C_CAM_ALGO, algo) | 1995 SM(R92C_CAM_KEYID, keyid) | 1996 SM(R92C_CAM_MACLO, LE_READ_2(&k->wk_macaddr[0])) | 1997 R92C_CAM_VALID); 1998 if (error != 0) 1999 goto fail; 2000 2001 return; 2002 2003fail: 2004 device_printf(sc->sc_dev, "%s fails, error %d\n", __func__, error); 2005} 2006 2007static void 2008urtwn_key_del_cb(struct urtwn_softc *sc, union sec_param *data) 2009{ 2010 struct ieee80211_key *k = &data->key; 2011 int i; 2012 2013 DPRINTFN(9, "keyix %d, flags %04X, macaddr %s\n", 2014 k->wk_keyix, k->wk_flags, ether_sprintf(k->wk_macaddr)); 2015 2016 urtwn_cam_write(sc, R92C_CAM_CTL0(k->wk_keyix), 0); 2017 urtwn_cam_write(sc, R92C_CAM_CTL1(k->wk_keyix), 0); 2018 2019 /* Clear key. */ 2020 for (i = 0; i < 4; i++) 2021 urtwn_cam_write(sc, R92C_CAM_KEY(k->wk_keyix, i), 0); 2022 sc->keys_bmap &= ~(1 << k->wk_keyix); 2023} 2024 2025static int 2026urtwn_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k) 2027{ 2028 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2029 2030 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2031 /* Not for us. */ 2032 return (1); 2033 } 2034 2035 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_set_cb)); 2036} 2037 2038static int 2039urtwn_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2040{ 2041 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2042 2043 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2044 /* Not for us. */ 2045 return (1); 2046 } 2047 2048 return (!urtwn_cmd_sleepable(sc, k, sizeof(*k), urtwn_key_del_cb)); 2049} 2050 2051static void 2052urtwn_tsf_task_adhoc(void *arg, int pending) 2053{ 2054 struct ieee80211vap *vap = arg; 2055 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2056 struct ieee80211_node *ni; 2057 uint32_t reg; 2058 2059 URTWN_LOCK(sc); 2060 ni = ieee80211_ref_node(vap->iv_bss); 2061 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 2062 2063 /* Accept beacons with the same BSSID. */ 2064 urtwn_set_rx_bssid_all(sc, 0); 2065 2066 /* Enable synchronization. */ 2067 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 2068 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2069 2070 /* Synchronize. */ 2071 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 2072 2073 /* Disable synchronization. */ 2074 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 2075 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2076 2077 /* Remove beacon filter. */ 2078 urtwn_set_rx_bssid_all(sc, 1); 2079 2080 /* Enable beaconing. */ 2081 urtwn_write_1(sc, R92C_MBID_NUM, 2082 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2083 reg |= R92C_BCN_CTRL_EN_BCN; 2084 2085 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 2086 ieee80211_free_node(ni); 2087 URTWN_UNLOCK(sc); 2088} 2089 2090static void 2091urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 2092{ 2093 struct ieee80211com *ic = &sc->sc_ic; 2094 struct urtwn_vap *uvp = URTWN_VAP(vap); 2095 2096 /* Reset TSF. */ 2097 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2098 2099 switch (vap->iv_opmode) { 2100 case IEEE80211_M_STA: 2101 /* Enable TSF synchronization. */ 2102 urtwn_write_1(sc, R92C_BCN_CTRL, 2103 urtwn_read_1(sc, R92C_BCN_CTRL) & 2104 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 2105 break; 2106 case IEEE80211_M_IBSS: 2107 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 2108 break; 2109 case IEEE80211_M_HOSTAP: 2110 /* Enable beaconing. */ 2111 urtwn_write_1(sc, R92C_MBID_NUM, 2112 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 2113 urtwn_write_1(sc, R92C_BCN_CTRL, 2114 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 2115 break; 2116 default: 2117 device_printf(sc->sc_dev, "undefined opmode %d\n", 2118 vap->iv_opmode); 2119 return; 2120 } 2121} 2122 2123static void 2124urtwn_get_tsf(struct urtwn_softc *sc, uint64_t *buf) 2125{ 2126 urtwn_read_region_1(sc, R92C_TSFTR, (uint8_t *)buf, sizeof(*buf)); 2127} 2128 2129static void 2130urtwn_set_led(struct urtwn_softc *sc, int led, int on) 2131{ 2132 uint8_t reg; 2133 2134 if (led == URTWN_LED_LINK) { 2135 if (sc->chip & URTWN_CHIP_88E) { 2136 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 2137 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 2138 if (!on) { 2139 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 2140 urtwn_write_1(sc, R92C_LEDCFG2, 2141 reg | R92C_LEDCFG0_DIS); 2142 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 2143 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 2144 0xfe); 2145 } 2146 } else { 2147 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 2148 if (!on) 2149 reg |= R92C_LEDCFG0_DIS; 2150 urtwn_write_1(sc, R92C_LEDCFG0, reg); 2151 } 2152 sc->ledlink = on; /* Save LED state. */ 2153 } 2154} 2155 2156static void 2157urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 2158{ 2159 uint8_t reg; 2160 2161 reg = urtwn_read_1(sc, R92C_MSR); 2162 reg = (reg & ~R92C_MSR_MASK) | mode; 2163 urtwn_write_1(sc, R92C_MSR, reg); 2164} 2165 2166static void 2167urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 2168 const struct ieee80211_rx_stats *rxs, 2169 int rssi, int nf) 2170{ 2171 struct ieee80211vap *vap = ni->ni_vap; 2172 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 2173 struct urtwn_vap *uvp = URTWN_VAP(vap); 2174 uint64_t ni_tstamp, curr_tstamp; 2175 2176 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 2177 2178 if (vap->iv_state == IEEE80211_S_RUN && 2179 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 2180 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 2181 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 2182 URTWN_LOCK(sc); 2183 urtwn_get_tsf(sc, &curr_tstamp); 2184 URTWN_UNLOCK(sc); 2185 curr_tstamp = le64toh(curr_tstamp); 2186 2187 if (ni_tstamp >= curr_tstamp) 2188 (void) ieee80211_ibss_merge(ni); 2189 } 2190} 2191 2192static int 2193urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2194{ 2195 struct urtwn_vap *uvp = URTWN_VAP(vap); 2196 struct ieee80211com *ic = vap->iv_ic; 2197 struct urtwn_softc *sc = ic->ic_softc; 2198 struct ieee80211_node *ni; 2199 enum ieee80211_state ostate; 2200 uint32_t reg; 2201 uint8_t mode; 2202 int error = 0; 2203 2204 ostate = vap->iv_state; 2205 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 2206 ieee80211_state_name[nstate]); 2207 2208 IEEE80211_UNLOCK(ic); 2209 URTWN_LOCK(sc); 2210 callout_stop(&sc->sc_watchdog_ch); 2211 2212 if (ostate == IEEE80211_S_RUN) { 2213 /* Turn link LED off. */ 2214 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2215 2216 /* Set media status to 'No Link'. */ 2217 urtwn_set_mode(sc, R92C_MSR_NOLINK); 2218 2219 /* Stop Rx of data frames. */ 2220 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2221 2222 /* Disable TSF synchronization. */ 2223 urtwn_write_1(sc, R92C_BCN_CTRL, 2224 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 2225 R92C_BCN_CTRL_DIS_TSF_UDT0); 2226 2227 /* Disable beaconing. */ 2228 urtwn_write_1(sc, R92C_MBID_NUM, 2229 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 2230 2231 /* Reset TSF. */ 2232 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 2233 2234 /* Reset EDCA parameters. */ 2235 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2236 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2237 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2238 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2239 } 2240 2241 switch (nstate) { 2242 case IEEE80211_S_INIT: 2243 /* Turn link LED off. */ 2244 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2245 break; 2246 case IEEE80211_S_SCAN: 2247 /* Pause AC Tx queues. */ 2248 urtwn_write_1(sc, R92C_TXPAUSE, 2249 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2250 break; 2251 case IEEE80211_S_AUTH: 2252 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2253 break; 2254 case IEEE80211_S_RUN: 2255 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2256 /* Turn link LED on. */ 2257 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2258 break; 2259 } 2260 2261 ni = ieee80211_ref_node(vap->iv_bss); 2262 2263 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2264 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2265 device_printf(sc->sc_dev, 2266 "%s: could not move to RUN state\n", __func__); 2267 error = EINVAL; 2268 goto end_run; 2269 } 2270 2271 switch (vap->iv_opmode) { 2272 case IEEE80211_M_STA: 2273 mode = R92C_MSR_INFRA; 2274 break; 2275 case IEEE80211_M_IBSS: 2276 mode = R92C_MSR_ADHOC; 2277 break; 2278 case IEEE80211_M_HOSTAP: 2279 mode = R92C_MSR_AP; 2280 break; 2281 default: 2282 device_printf(sc->sc_dev, "undefined opmode %d\n", 2283 vap->iv_opmode); 2284 error = EINVAL; 2285 goto end_run; 2286 } 2287 2288 /* Set media status to 'Associated'. */ 2289 urtwn_set_mode(sc, mode); 2290 2291 /* Set BSSID. */ 2292 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2293 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2294 2295 if (ic->ic_curmode == IEEE80211_MODE_11B) 2296 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2297 else /* 802.11b/g */ 2298 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2299 2300 /* Enable Rx of data frames. */ 2301 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2302 2303 /* Flush all AC queues. */ 2304 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2305 2306 /* Set beacon interval. */ 2307 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2308 2309 /* Allow Rx from our BSSID only. */ 2310 if (ic->ic_promisc == 0) { 2311 reg = urtwn_read_4(sc, R92C_RCR); 2312 2313 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 2314 reg |= R92C_RCR_CBSSID_DATA; 2315 if (vap->iv_opmode != IEEE80211_M_IBSS) 2316 reg |= R92C_RCR_CBSSID_BCN; 2317 2318 urtwn_write_4(sc, R92C_RCR, reg); 2319 } 2320 2321 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2322 vap->iv_opmode == IEEE80211_M_IBSS) { 2323 error = urtwn_setup_beacon(sc, ni); 2324 if (error != 0) { 2325 device_printf(sc->sc_dev, 2326 "unable to push beacon into the chip, " 2327 "error %d\n", error); 2328 goto end_run; 2329 } 2330 } 2331 2332 /* Enable TSF synchronization. */ 2333 urtwn_tsf_sync_enable(sc, vap); 2334 2335 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2336 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2337 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2338 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2339 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2340 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2341 2342 /* Intialize rate adaptation. */ 2343 if (!(sc->chip & URTWN_CHIP_88E)) 2344 urtwn_ra_init(sc); 2345 /* Turn link LED on. */ 2346 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2347 2348 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2349 /* Reset temperature calibration state machine. */ 2350 sc->thcal_state = 0; 2351 sc->thcal_lctemp = 0; 2352 2353end_run: 2354 ieee80211_free_node(ni); 2355 break; 2356 default: 2357 break; 2358 } 2359 2360 URTWN_UNLOCK(sc); 2361 IEEE80211_LOCK(ic); 2362 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2363} 2364 2365static void 2366urtwn_watchdog(void *arg) 2367{ 2368 struct urtwn_softc *sc = arg; 2369 2370 if (sc->sc_txtimer > 0) { 2371 if (--sc->sc_txtimer == 0) { 2372 device_printf(sc->sc_dev, "device timeout\n"); 2373 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2374 return; 2375 } 2376 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2377 } 2378} 2379 2380static void 2381urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2382{ 2383 int pwdb; 2384 2385 /* Convert antenna signal to percentage. */ 2386 if (rssi <= -100 || rssi >= 20) 2387 pwdb = 0; 2388 else if (rssi >= 0) 2389 pwdb = 100; 2390 else 2391 pwdb = 100 + rssi; 2392 if (!(sc->chip & URTWN_CHIP_88E)) { 2393 if (rate <= URTWN_RIDX_CCK11) { 2394 /* CCK gain is smaller than OFDM/MCS gain. */ 2395 pwdb += 6; 2396 if (pwdb > 100) 2397 pwdb = 100; 2398 if (pwdb <= 14) 2399 pwdb -= 4; 2400 else if (pwdb <= 26) 2401 pwdb -= 8; 2402 else if (pwdb <= 34) 2403 pwdb -= 6; 2404 else if (pwdb <= 42) 2405 pwdb -= 2; 2406 } 2407 } 2408 if (sc->avg_pwdb == -1) /* Init. */ 2409 sc->avg_pwdb = pwdb; 2410 else if (sc->avg_pwdb < pwdb) 2411 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2412 else 2413 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2414 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 2415} 2416 2417static int8_t 2418urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2419{ 2420 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2421 struct r92c_rx_phystat *phy; 2422 struct r92c_rx_cck *cck; 2423 uint8_t rpt; 2424 int8_t rssi; 2425 2426 if (rate <= URTWN_RIDX_CCK11) { 2427 cck = (struct r92c_rx_cck *)physt; 2428 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2429 rpt = (cck->agc_rpt >> 5) & 0x3; 2430 rssi = (cck->agc_rpt & 0x1f) << 1; 2431 } else { 2432 rpt = (cck->agc_rpt >> 6) & 0x3; 2433 rssi = cck->agc_rpt & 0x3e; 2434 } 2435 rssi = cckoff[rpt] - rssi; 2436 } else { /* OFDM/HT. */ 2437 phy = (struct r92c_rx_phystat *)physt; 2438 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2439 } 2440 return (rssi); 2441} 2442 2443static int8_t 2444urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2445{ 2446 struct r92c_rx_phystat *phy; 2447 struct r88e_rx_cck *cck; 2448 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2449 int8_t rssi; 2450 2451 rssi = 0; 2452 if (rate <= URTWN_RIDX_CCK11) { 2453 cck = (struct r88e_rx_cck *)physt; 2454 cck_agc_rpt = cck->agc_rpt; 2455 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2456 vga_idx = cck_agc_rpt & 0x1f; 2457 switch (lna_idx) { 2458 case 7: 2459 if (vga_idx <= 27) 2460 rssi = -100 + 2* (27 - vga_idx); 2461 else 2462 rssi = -100; 2463 break; 2464 case 6: 2465 rssi = -48 + 2 * (2 - vga_idx); 2466 break; 2467 case 5: 2468 rssi = -42 + 2 * (7 - vga_idx); 2469 break; 2470 case 4: 2471 rssi = -36 + 2 * (7 - vga_idx); 2472 break; 2473 case 3: 2474 rssi = -24 + 2 * (7 - vga_idx); 2475 break; 2476 case 2: 2477 rssi = -12 + 2 * (5 - vga_idx); 2478 break; 2479 case 1: 2480 rssi = 8 - (2 * vga_idx); 2481 break; 2482 case 0: 2483 rssi = 14 - (2 * vga_idx); 2484 break; 2485 } 2486 rssi += 6; 2487 } else { /* OFDM/HT. */ 2488 phy = (struct r92c_rx_phystat *)physt; 2489 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2490 } 2491 return (rssi); 2492} 2493 2494static __inline uint8_t 2495rate2ridx(uint8_t rate) 2496{ 2497 switch (rate) { 2498 case 12: return 4; 2499 case 18: return 5; 2500 case 24: return 6; 2501 case 36: return 7; 2502 case 48: return 8; 2503 case 72: return 9; 2504 case 96: return 10; 2505 case 108: return 11; 2506 case 2: return 0; 2507 case 4: return 1; 2508 case 11: return 2; 2509 case 22: return 3; 2510 default: return 0; 2511 } 2512} 2513 2514static int 2515urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2516 struct mbuf *m, struct urtwn_data *data) 2517{ 2518 const struct ieee80211_txparam *tp; 2519 struct ieee80211com *ic = &sc->sc_ic; 2520 struct ieee80211vap *vap = ni->ni_vap; 2521 struct ieee80211_key *k = NULL; 2522 struct ieee80211_channel *chan; 2523 struct ieee80211_frame *wh; 2524 struct r92c_tx_desc *txd; 2525 uint8_t macid, raid, rate, ridx, subtype, type, tid, qsel; 2526 int hasqos, ismcast; 2527 2528 URTWN_ASSERT_LOCKED(sc); 2529 2530 /* 2531 * Software crypto. 2532 */ 2533 wh = mtod(m, struct ieee80211_frame *); 2534 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2535 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2536 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2537 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2538 2539 /* Select TX ring for this frame. */ 2540 if (hasqos) { 2541 tid = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2542 tid &= IEEE80211_QOS_TID; 2543 } else 2544 tid = 0; 2545 2546 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2547 ni->ni_chan : ic->ic_curchan; 2548 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2549 2550 /* Choose a TX rate index. */ 2551 if (type == IEEE80211_FC0_TYPE_MGT) 2552 rate = tp->mgmtrate; 2553 else if (ismcast) 2554 rate = tp->mcastrate; 2555 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2556 rate = tp->ucastrate; 2557 else if (m->m_flags & M_EAPOL) 2558 rate = tp->mgmtrate; 2559 else { 2560 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2561 /* XXX pass pktlen */ 2562 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2563 rate = ni->ni_txrate; 2564 } else { 2565 if (ic->ic_curmode != IEEE80211_MODE_11B) 2566 rate = 108; 2567 else 2568 rate = 22; 2569 } 2570 } 2571 2572 ridx = rate2ridx(rate); 2573 if (ic->ic_curmode != IEEE80211_MODE_11B) 2574 raid = R92C_RAID_11BG; 2575 else 2576 raid = R92C_RAID_11B; 2577 2578 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2579 k = ieee80211_crypto_encap(ni, m); 2580 if (k == NULL) { 2581 device_printf(sc->sc_dev, 2582 "ieee80211_crypto_encap returns NULL.\n"); 2583 return (ENOBUFS); 2584 } 2585 2586 /* in case packet header moved, reset pointer */ 2587 wh = mtod(m, struct ieee80211_frame *); 2588 } 2589 2590 /* Fill Tx descriptor. */ 2591 txd = (struct r92c_tx_desc *)data->buf; 2592 memset(txd, 0, sizeof(*txd)); 2593 2594 txd->txdw0 |= htole32( 2595 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2596 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2597 if (ismcast) 2598 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2599 2600 if (!ismcast) { 2601 if (sc->chip & URTWN_CHIP_88E) { 2602 struct urtwn_node *un = URTWN_NODE(ni); 2603 macid = un->id; 2604 } else 2605 macid = URTWN_MACID_BSS; 2606 2607 if (type == IEEE80211_FC0_TYPE_DATA) { 2608 qsel = tid % URTWN_MAX_TID; 2609 2610 if (sc->chip & URTWN_CHIP_88E) { 2611 txd->txdw2 |= htole32( 2612 R88E_TXDW2_AGGBK | 2613 R88E_TXDW2_CCX_RPT); 2614 } else 2615 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2616 2617 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2618 switch (ic->ic_protmode) { 2619 case IEEE80211_PROT_CTSONLY: 2620 txd->txdw4 |= htole32( 2621 R92C_TXDW4_CTS2SELF | 2622 R92C_TXDW4_HWRTSEN); 2623 break; 2624 case IEEE80211_PROT_RTSCTS: 2625 txd->txdw4 |= htole32( 2626 R92C_TXDW4_RTSEN | 2627 R92C_TXDW4_HWRTSEN); 2628 break; 2629 default: 2630 break; 2631 } 2632 } 2633 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2634 URTWN_RIDX_OFDM24)); 2635 txd->txdw5 |= htole32(0x0001ff00); 2636 } else /* IEEE80211_FC0_TYPE_MGT */ 2637 qsel = R92C_TXDW1_QSEL_MGNT; 2638 } else { 2639 macid = URTWN_MACID_BC; 2640 qsel = R92C_TXDW1_QSEL_MGNT; 2641 } 2642 2643 txd->txdw1 |= htole32( 2644 SM(R92C_TXDW1_QSEL, qsel) | 2645 SM(R92C_TXDW1_RAID, raid)); 2646 2647 if (sc->chip & URTWN_CHIP_88E) 2648 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 2649 else 2650 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 2651 2652 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2653 /* Force this rate if needed. */ 2654 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 2655 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 2656 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2657 2658 if (!hasqos) { 2659 /* Use HW sequence numbering for non-QoS frames. */ 2660 if (sc->chip & URTWN_CHIP_88E) 2661 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2662 else 2663 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2664 } else { 2665 /* Set sequence number. */ 2666 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2667 } 2668 2669 if (k != NULL && !(k->wk_flags & IEEE80211_KEY_SWCRYPT)) { 2670 uint8_t cipher; 2671 2672 switch (k->wk_cipher->ic_cipher) { 2673 case IEEE80211_CIPHER_WEP: 2674 case IEEE80211_CIPHER_TKIP: 2675 cipher = R92C_TXDW1_CIPHER_RC4; 2676 break; 2677 case IEEE80211_CIPHER_AES_CCM: 2678 cipher = R92C_TXDW1_CIPHER_AES; 2679 break; 2680 default: 2681 device_printf(sc->sc_dev, "%s: unknown cipher %d\n", 2682 __func__, k->wk_cipher->ic_cipher); 2683 return (EINVAL); 2684 } 2685 2686 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 2687 } 2688 2689 if (ieee80211_radiotap_active_vap(vap)) { 2690 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2691 2692 tap->wt_flags = 0; 2693 if (k != NULL) 2694 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2695 ieee80211_radiotap_tx(vap, m); 2696 } 2697 2698 data->ni = ni; 2699 2700 urtwn_tx_start(sc, m, type, data); 2701 2702 return (0); 2703} 2704 2705static void 2706urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 2707 struct urtwn_data *data) 2708{ 2709 struct usb_xfer *xfer; 2710 struct r92c_tx_desc *txd; 2711 uint16_t ac, sum; 2712 int i, xferlen; 2713 2714 URTWN_ASSERT_LOCKED(sc); 2715 2716 ac = M_WME_GETAC(m); 2717 2718 switch (type) { 2719 case IEEE80211_FC0_TYPE_CTL: 2720 case IEEE80211_FC0_TYPE_MGT: 2721 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 2722 break; 2723 default: 2724 xfer = sc->sc_xfer[wme2queue[ac].qid]; 2725 break; 2726 } 2727 2728 txd = (struct r92c_tx_desc *)data->buf; 2729 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 2730 2731 /* Compute Tx descriptor checksum. */ 2732 sum = 0; 2733 for (i = 0; i < sizeof(*txd) / 2; i++) 2734 sum ^= ((uint16_t *)txd)[i]; 2735 txd->txdsum = sum; /* NB: already little endian. */ 2736 2737 xferlen = sizeof(*txd) + m->m_pkthdr.len; 2738 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 2739 2740 data->buflen = xferlen; 2741 data->m = m; 2742 2743 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 2744 usbd_transfer_start(xfer); 2745} 2746 2747static int 2748urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 2749{ 2750 struct urtwn_softc *sc = ic->ic_softc; 2751 int error; 2752 2753 URTWN_LOCK(sc); 2754 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2755 URTWN_UNLOCK(sc); 2756 return (ENXIO); 2757 } 2758 error = mbufq_enqueue(&sc->sc_snd, m); 2759 if (error) { 2760 URTWN_UNLOCK(sc); 2761 return (error); 2762 } 2763 urtwn_start(sc); 2764 URTWN_UNLOCK(sc); 2765 2766 return (0); 2767} 2768 2769static void 2770urtwn_start(struct urtwn_softc *sc) 2771{ 2772 struct ieee80211_node *ni; 2773 struct mbuf *m; 2774 struct urtwn_data *bf; 2775 2776 URTWN_ASSERT_LOCKED(sc); 2777 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2778 bf = urtwn_getbuf(sc); 2779 if (bf == NULL) { 2780 mbufq_prepend(&sc->sc_snd, m); 2781 break; 2782 } 2783 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2784 m->m_pkthdr.rcvif = NULL; 2785 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 2786 if_inc_counter(ni->ni_vap->iv_ifp, 2787 IFCOUNTER_OERRORS, 1); 2788 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2789 m_freem(m); 2790 ieee80211_free_node(ni); 2791 break; 2792 } 2793 sc->sc_txtimer = 5; 2794 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2795 } 2796} 2797 2798static void 2799urtwn_parent(struct ieee80211com *ic) 2800{ 2801 struct urtwn_softc *sc = ic->ic_softc; 2802 2803 URTWN_LOCK(sc); 2804 if (sc->sc_flags & URTWN_DETACHED) { 2805 URTWN_UNLOCK(sc); 2806 return; 2807 } 2808 URTWN_UNLOCK(sc); 2809 2810 if (ic->ic_nrunning > 0) { 2811 if (urtwn_init(sc) != 0) { 2812 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2813 if (vap != NULL) 2814 ieee80211_stop(vap); 2815 } else 2816 ieee80211_start_all(ic); 2817 } else 2818 urtwn_stop(sc); 2819} 2820 2821static __inline int 2822urtwn_power_on(struct urtwn_softc *sc) 2823{ 2824 2825 return sc->sc_power_on(sc); 2826} 2827 2828static int 2829urtwn_r92c_power_on(struct urtwn_softc *sc) 2830{ 2831 uint32_t reg; 2832 usb_error_t error; 2833 int ntries; 2834 2835 /* Wait for autoload done bit. */ 2836 for (ntries = 0; ntries < 1000; ntries++) { 2837 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2838 break; 2839 urtwn_ms_delay(sc); 2840 } 2841 if (ntries == 1000) { 2842 device_printf(sc->sc_dev, 2843 "timeout waiting for chip autoload\n"); 2844 return (ETIMEDOUT); 2845 } 2846 2847 /* Unlock ISO/CLK/Power control register. */ 2848 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2849 if (error != USB_ERR_NORMAL_COMPLETION) 2850 return (EIO); 2851 /* Move SPS into PWM mode. */ 2852 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2853 if (error != USB_ERR_NORMAL_COMPLETION) 2854 return (EIO); 2855 urtwn_ms_delay(sc); 2856 2857 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2858 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2859 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2860 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2861 if (error != USB_ERR_NORMAL_COMPLETION) 2862 return (EIO); 2863 urtwn_ms_delay(sc); 2864 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2865 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2866 ~R92C_SYS_ISO_CTRL_MD2PP); 2867 if (error != USB_ERR_NORMAL_COMPLETION) 2868 return (EIO); 2869 } 2870 2871 /* Auto enable WLAN. */ 2872 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2873 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2874 if (error != USB_ERR_NORMAL_COMPLETION) 2875 return (EIO); 2876 for (ntries = 0; ntries < 1000; ntries++) { 2877 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2878 R92C_APS_FSMCO_APFM_ONMAC)) 2879 break; 2880 urtwn_ms_delay(sc); 2881 } 2882 if (ntries == 1000) { 2883 device_printf(sc->sc_dev, 2884 "timeout waiting for MAC auto ON\n"); 2885 return (ETIMEDOUT); 2886 } 2887 2888 /* Enable radio, GPIO and LED functions. */ 2889 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2890 R92C_APS_FSMCO_AFSM_HSUS | 2891 R92C_APS_FSMCO_PDN_EN | 2892 R92C_APS_FSMCO_PFM_ALDN); 2893 if (error != USB_ERR_NORMAL_COMPLETION) 2894 return (EIO); 2895 /* Release RF digital isolation. */ 2896 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2897 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2898 if (error != USB_ERR_NORMAL_COMPLETION) 2899 return (EIO); 2900 2901 /* Initialize MAC. */ 2902 error = urtwn_write_1(sc, R92C_APSD_CTRL, 2903 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2904 if (error != USB_ERR_NORMAL_COMPLETION) 2905 return (EIO); 2906 for (ntries = 0; ntries < 200; ntries++) { 2907 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2908 R92C_APSD_CTRL_OFF_STATUS)) 2909 break; 2910 urtwn_ms_delay(sc); 2911 } 2912 if (ntries == 200) { 2913 device_printf(sc->sc_dev, 2914 "timeout waiting for MAC initialization\n"); 2915 return (ETIMEDOUT); 2916 } 2917 2918 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2919 reg = urtwn_read_2(sc, R92C_CR); 2920 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2921 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2922 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2923 R92C_CR_ENSEC; 2924 error = urtwn_write_2(sc, R92C_CR, reg); 2925 if (error != USB_ERR_NORMAL_COMPLETION) 2926 return (EIO); 2927 2928 error = urtwn_write_1(sc, 0xfe10, 0x19); 2929 if (error != USB_ERR_NORMAL_COMPLETION) 2930 return (EIO); 2931 return (0); 2932} 2933 2934static int 2935urtwn_r88e_power_on(struct urtwn_softc *sc) 2936{ 2937 uint32_t reg; 2938 usb_error_t error; 2939 int ntries; 2940 2941 /* Wait for power ready bit. */ 2942 for (ntries = 0; ntries < 5000; ntries++) { 2943 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2944 break; 2945 urtwn_ms_delay(sc); 2946 } 2947 if (ntries == 5000) { 2948 device_printf(sc->sc_dev, 2949 "timeout waiting for chip power up\n"); 2950 return (ETIMEDOUT); 2951 } 2952 2953 /* Reset BB. */ 2954 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2955 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2956 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2957 if (error != USB_ERR_NORMAL_COMPLETION) 2958 return (EIO); 2959 2960 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2961 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2962 if (error != USB_ERR_NORMAL_COMPLETION) 2963 return (EIO); 2964 2965 /* Disable HWPDN. */ 2966 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2967 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2968 if (error != USB_ERR_NORMAL_COMPLETION) 2969 return (EIO); 2970 2971 /* Disable WL suspend. */ 2972 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2973 urtwn_read_2(sc, R92C_APS_FSMCO) & 2974 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2975 if (error != USB_ERR_NORMAL_COMPLETION) 2976 return (EIO); 2977 2978 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2979 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2980 if (error != USB_ERR_NORMAL_COMPLETION) 2981 return (EIO); 2982 for (ntries = 0; ntries < 5000; ntries++) { 2983 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2984 R92C_APS_FSMCO_APFM_ONMAC)) 2985 break; 2986 urtwn_ms_delay(sc); 2987 } 2988 if (ntries == 5000) 2989 return (ETIMEDOUT); 2990 2991 /* Enable LDO normal mode. */ 2992 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 2993 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2994 if (error != USB_ERR_NORMAL_COMPLETION) 2995 return (EIO); 2996 2997 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2998 error = urtwn_write_2(sc, R92C_CR, 0); 2999 if (error != USB_ERR_NORMAL_COMPLETION) 3000 return (EIO); 3001 reg = urtwn_read_2(sc, R92C_CR); 3002 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3003 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3004 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3005 error = urtwn_write_2(sc, R92C_CR, reg); 3006 if (error != USB_ERR_NORMAL_COMPLETION) 3007 return (EIO); 3008 3009 return (0); 3010} 3011 3012static int 3013urtwn_llt_init(struct urtwn_softc *sc) 3014{ 3015 int i, error, page_count, pktbuf_count; 3016 3017 page_count = (sc->chip & URTWN_CHIP_88E) ? 3018 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 3019 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 3020 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 3021 3022 /* Reserve pages [0; page_count]. */ 3023 for (i = 0; i < page_count; i++) { 3024 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3025 return (error); 3026 } 3027 /* NB: 0xff indicates end-of-list. */ 3028 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3029 return (error); 3030 /* 3031 * Use pages [page_count + 1; pktbuf_count - 1] 3032 * as ring buffer. 3033 */ 3034 for (++i; i < pktbuf_count - 1; i++) { 3035 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3036 return (error); 3037 } 3038 /* Make the last page point to the beginning of the ring buffer. */ 3039 error = urtwn_llt_write(sc, i, page_count + 1); 3040 return (error); 3041} 3042 3043static void 3044urtwn_fw_reset(struct urtwn_softc *sc) 3045{ 3046 uint16_t reg; 3047 int ntries; 3048 3049 /* Tell 8051 to reset itself. */ 3050 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3051 3052 /* Wait until 8051 resets by itself. */ 3053 for (ntries = 0; ntries < 100; ntries++) { 3054 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3055 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3056 return; 3057 urtwn_ms_delay(sc); 3058 } 3059 /* Force 8051 reset. */ 3060 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3061} 3062 3063static void 3064urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3065{ 3066 uint16_t reg; 3067 3068 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3069 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3070 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3071} 3072 3073static int 3074urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 3075{ 3076 uint32_t reg; 3077 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 3078 int off, mlen; 3079 3080 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3081 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3082 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3083 3084 off = R92C_FW_START_ADDR; 3085 while (len > 0) { 3086 if (len > 196) 3087 mlen = 196; 3088 else if (len > 4) 3089 mlen = 4; 3090 else 3091 mlen = 1; 3092 /* XXX fix this deconst */ 3093 error = urtwn_write_region_1(sc, off, 3094 __DECONST(uint8_t *, buf), mlen); 3095 if (error != USB_ERR_NORMAL_COMPLETION) 3096 break; 3097 off += mlen; 3098 buf += mlen; 3099 len -= mlen; 3100 } 3101 return (error); 3102} 3103 3104static int 3105urtwn_load_firmware(struct urtwn_softc *sc) 3106{ 3107 const struct firmware *fw; 3108 const struct r92c_fw_hdr *hdr; 3109 const char *imagename; 3110 const u_char *ptr; 3111 size_t len; 3112 uint32_t reg; 3113 int mlen, ntries, page, error; 3114 3115 URTWN_UNLOCK(sc); 3116 /* Read firmware image from the filesystem. */ 3117 if (sc->chip & URTWN_CHIP_88E) 3118 imagename = "urtwn-rtl8188eufw"; 3119 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3120 URTWN_CHIP_UMC_A_CUT) 3121 imagename = "urtwn-rtl8192cfwU"; 3122 else 3123 imagename = "urtwn-rtl8192cfwT"; 3124 3125 fw = firmware_get(imagename); 3126 URTWN_LOCK(sc); 3127 if (fw == NULL) { 3128 device_printf(sc->sc_dev, 3129 "failed loadfirmware of file %s\n", imagename); 3130 return (ENOENT); 3131 } 3132 3133 len = fw->datasize; 3134 3135 if (len < sizeof(*hdr)) { 3136 device_printf(sc->sc_dev, "firmware too short\n"); 3137 error = EINVAL; 3138 goto fail; 3139 } 3140 ptr = fw->data; 3141 hdr = (const struct r92c_fw_hdr *)ptr; 3142 /* Check if there is a valid FW header and skip it. */ 3143 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3144 (le16toh(hdr->signature) >> 4) == 0x88e || 3145 (le16toh(hdr->signature) >> 4) == 0x92c) { 3146 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 3147 le16toh(hdr->version), le16toh(hdr->subversion), 3148 hdr->month, hdr->date, hdr->hour, hdr->minute); 3149 ptr += sizeof(*hdr); 3150 len -= sizeof(*hdr); 3151 } 3152 3153 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3154 if (sc->chip & URTWN_CHIP_88E) 3155 urtwn_r88e_fw_reset(sc); 3156 else 3157 urtwn_fw_reset(sc); 3158 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3159 } 3160 3161 if (!(sc->chip & URTWN_CHIP_88E)) { 3162 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3163 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3164 R92C_SYS_FUNC_EN_CPUEN); 3165 } 3166 urtwn_write_1(sc, R92C_MCUFWDL, 3167 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3168 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3169 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3170 3171 /* Reset the FWDL checksum. */ 3172 urtwn_write_1(sc, R92C_MCUFWDL, 3173 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3174 3175 for (page = 0; len > 0; page++) { 3176 mlen = min(len, R92C_FW_PAGE_SIZE); 3177 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3178 if (error != 0) { 3179 device_printf(sc->sc_dev, 3180 "could not load firmware page\n"); 3181 goto fail; 3182 } 3183 ptr += mlen; 3184 len -= mlen; 3185 } 3186 urtwn_write_1(sc, R92C_MCUFWDL, 3187 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3188 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3189 3190 /* Wait for checksum report. */ 3191 for (ntries = 0; ntries < 1000; ntries++) { 3192 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3193 break; 3194 urtwn_ms_delay(sc); 3195 } 3196 if (ntries == 1000) { 3197 device_printf(sc->sc_dev, 3198 "timeout waiting for checksum report\n"); 3199 error = ETIMEDOUT; 3200 goto fail; 3201 } 3202 3203 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3204 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3205 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3206 if (sc->chip & URTWN_CHIP_88E) 3207 urtwn_r88e_fw_reset(sc); 3208 /* Wait for firmware readiness. */ 3209 for (ntries = 0; ntries < 1000; ntries++) { 3210 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3211 break; 3212 urtwn_ms_delay(sc); 3213 } 3214 if (ntries == 1000) { 3215 device_printf(sc->sc_dev, 3216 "timeout waiting for firmware readiness\n"); 3217 error = ETIMEDOUT; 3218 goto fail; 3219 } 3220fail: 3221 firmware_put(fw, FIRMWARE_UNLOAD); 3222 return (error); 3223} 3224 3225static int 3226urtwn_dma_init(struct urtwn_softc *sc) 3227{ 3228 struct usb_endpoint *ep, *ep_end; 3229 usb_error_t usb_err; 3230 uint32_t reg; 3231 int hashq, hasnq, haslq, nqueues, ntx; 3232 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 3233 3234 /* Initialize LLT table. */ 3235 error = urtwn_llt_init(sc); 3236 if (error != 0) 3237 return (error); 3238 3239 /* Determine the number of bulk-out pipes. */ 3240 ntx = 0; 3241 ep = sc->sc_udev->endpoints; 3242 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 3243 for (; ep != ep_end; ep++) { 3244 if ((ep->edesc == NULL) || 3245 (ep->iface_index != sc->sc_iface_index)) 3246 continue; 3247 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 3248 ntx++; 3249 } 3250 if (ntx == 0) { 3251 device_printf(sc->sc_dev, 3252 "%d: invalid number of Tx bulk pipes\n", ntx); 3253 return (EIO); 3254 } 3255 3256 /* Get Tx queues to USB endpoints mapping. */ 3257 hashq = hasnq = haslq = nqueues = 0; 3258 switch (ntx) { 3259 case 1: hashq = 1; break; 3260 case 2: hashq = hasnq = 1; break; 3261 case 3: case 4: hashq = hasnq = haslq = 1; break; 3262 } 3263 nqueues = hashq + hasnq + haslq; 3264 if (nqueues == 0) 3265 return (EIO); 3266 3267 npubqpages = nqpages = nrempages = pagecount = 0; 3268 if (sc->chip & URTWN_CHIP_88E) 3269 tx_boundary = R88E_TX_PAGE_BOUNDARY; 3270 else { 3271 pagecount = R92C_TX_PAGE_COUNT; 3272 npubqpages = R92C_PUBQ_NPAGES; 3273 tx_boundary = R92C_TX_PAGE_BOUNDARY; 3274 } 3275 3276 /* Set number of pages for normal priority queue. */ 3277 if (sc->chip & URTWN_CHIP_88E) { 3278 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 3279 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3280 return (EIO); 3281 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3282 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3283 return (EIO); 3284 } else { 3285 /* Get the number of pages for each queue. */ 3286 nqpages = (pagecount - npubqpages) / nqueues; 3287 /* 3288 * The remaining pages are assigned to the high priority 3289 * queue. 3290 */ 3291 nrempages = (pagecount - npubqpages) % nqueues; 3292 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3293 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3294 return (EIO); 3295 usb_err = urtwn_write_4(sc, R92C_RQPN, 3296 /* Set number of pages for public queue. */ 3297 SM(R92C_RQPN_PUBQ, npubqpages) | 3298 /* Set number of pages for high priority queue. */ 3299 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3300 /* Set number of pages for low priority queue. */ 3301 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3302 /* Load values. */ 3303 R92C_RQPN_LD); 3304 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3305 return (EIO); 3306 } 3307 3308 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 3309 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3310 return (EIO); 3311 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 3312 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3313 return (EIO); 3314 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 3315 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3316 return (EIO); 3317 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 3318 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3319 return (EIO); 3320 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 3321 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3322 return (EIO); 3323 3324 /* Set queue to USB pipe mapping. */ 3325 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3326 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3327 if (nqueues == 1) { 3328 if (hashq) 3329 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3330 else if (hasnq) 3331 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3332 else 3333 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3334 } else if (nqueues == 2) { 3335 /* 3336 * All 2-endpoints configs have high and normal 3337 * priority queues. 3338 */ 3339 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3340 } else 3341 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3342 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3343 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3344 return (EIO); 3345 3346 /* Set Tx/Rx transfer page boundary. */ 3347 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 3348 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 3349 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3350 return (EIO); 3351 3352 /* Set Tx/Rx transfer page size. */ 3353 usb_err = urtwn_write_1(sc, R92C_PBP, 3354 SM(R92C_PBP_PSRX, R92C_PBP_128) | 3355 SM(R92C_PBP_PSTX, R92C_PBP_128)); 3356 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3357 return (EIO); 3358 3359 return (0); 3360} 3361 3362static int 3363urtwn_mac_init(struct urtwn_softc *sc) 3364{ 3365 usb_error_t error; 3366 int i; 3367 3368 /* Write MAC initialization values. */ 3369 if (sc->chip & URTWN_CHIP_88E) { 3370 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 3371 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3372 rtl8188eu_mac[i].val); 3373 if (error != USB_ERR_NORMAL_COMPLETION) 3374 return (EIO); 3375 } 3376 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 3377 } else { 3378 for (i = 0; i < nitems(rtl8192cu_mac); i++) 3379 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3380 rtl8192cu_mac[i].val); 3381 if (error != USB_ERR_NORMAL_COMPLETION) 3382 return (EIO); 3383 } 3384 3385 return (0); 3386} 3387 3388static void 3389urtwn_bb_init(struct urtwn_softc *sc) 3390{ 3391 const struct urtwn_bb_prog *prog; 3392 uint32_t reg; 3393 uint8_t crystalcap; 3394 int i; 3395 3396 /* Enable BB and RF. */ 3397 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3398 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3399 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3400 R92C_SYS_FUNC_EN_DIO_RF); 3401 3402 if (!(sc->chip & URTWN_CHIP_88E)) 3403 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 3404 3405 urtwn_write_1(sc, R92C_RF_CTRL, 3406 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3407 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3408 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3409 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3410 3411 if (!(sc->chip & URTWN_CHIP_88E)) { 3412 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3413 urtwn_write_1(sc, 0x15, 0xe9); 3414 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3415 } 3416 3417 /* Select BB programming based on board type. */ 3418 if (sc->chip & URTWN_CHIP_88E) 3419 prog = &rtl8188eu_bb_prog; 3420 else if (!(sc->chip & URTWN_CHIP_92C)) { 3421 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3422 prog = &rtl8188ce_bb_prog; 3423 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3424 prog = &rtl8188ru_bb_prog; 3425 else 3426 prog = &rtl8188cu_bb_prog; 3427 } else { 3428 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3429 prog = &rtl8192ce_bb_prog; 3430 else 3431 prog = &rtl8192cu_bb_prog; 3432 } 3433 /* Write BB initialization values. */ 3434 for (i = 0; i < prog->count; i++) { 3435 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3436 urtwn_ms_delay(sc); 3437 } 3438 3439 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3440 /* 8192C 1T only configuration. */ 3441 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3442 reg = (reg & ~0x00000003) | 0x2; 3443 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3444 3445 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3446 reg = (reg & ~0x00300033) | 0x00200022; 3447 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3448 3449 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3450 reg = (reg & ~0xff000000) | 0x45 << 24; 3451 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3452 3453 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3454 reg = (reg & ~0x000000ff) | 0x23; 3455 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3456 3457 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3458 reg = (reg & ~0x00000030) | 1 << 4; 3459 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3460 3461 reg = urtwn_bb_read(sc, 0xe74); 3462 reg = (reg & ~0x0c000000) | 2 << 26; 3463 urtwn_bb_write(sc, 0xe74, reg); 3464 reg = urtwn_bb_read(sc, 0xe78); 3465 reg = (reg & ~0x0c000000) | 2 << 26; 3466 urtwn_bb_write(sc, 0xe78, reg); 3467 reg = urtwn_bb_read(sc, 0xe7c); 3468 reg = (reg & ~0x0c000000) | 2 << 26; 3469 urtwn_bb_write(sc, 0xe7c, reg); 3470 reg = urtwn_bb_read(sc, 0xe80); 3471 reg = (reg & ~0x0c000000) | 2 << 26; 3472 urtwn_bb_write(sc, 0xe80, reg); 3473 reg = urtwn_bb_read(sc, 0xe88); 3474 reg = (reg & ~0x0c000000) | 2 << 26; 3475 urtwn_bb_write(sc, 0xe88, reg); 3476 } 3477 3478 /* Write AGC values. */ 3479 for (i = 0; i < prog->agccount; i++) { 3480 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 3481 prog->agcvals[i]); 3482 urtwn_ms_delay(sc); 3483 } 3484 3485 if (sc->chip & URTWN_CHIP_88E) { 3486 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3487 urtwn_ms_delay(sc); 3488 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3489 urtwn_ms_delay(sc); 3490 3491 crystalcap = sc->rom.r88e_rom[0xb9]; 3492 if (crystalcap == 0xff) 3493 crystalcap = 0x20; 3494 crystalcap &= 0x3f; 3495 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3496 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3497 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3498 crystalcap | crystalcap << 6)); 3499 } else { 3500 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3501 R92C_HSSI_PARAM2_CCK_HIPWR) 3502 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 3503 } 3504} 3505 3506static void 3507urtwn_rf_init(struct urtwn_softc *sc) 3508{ 3509 const struct urtwn_rf_prog *prog; 3510 uint32_t reg, type; 3511 int i, j, idx, off; 3512 3513 /* Select RF programming based on board type. */ 3514 if (sc->chip & URTWN_CHIP_88E) 3515 prog = rtl8188eu_rf_prog; 3516 else if (!(sc->chip & URTWN_CHIP_92C)) { 3517 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3518 prog = rtl8188ce_rf_prog; 3519 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3520 prog = rtl8188ru_rf_prog; 3521 else 3522 prog = rtl8188cu_rf_prog; 3523 } else 3524 prog = rtl8192ce_rf_prog; 3525 3526 for (i = 0; i < sc->nrxchains; i++) { 3527 /* Save RF_ENV control type. */ 3528 idx = i / 2; 3529 off = (i % 2) * 16; 3530 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3531 type = (reg >> off) & 0x10; 3532 3533 /* Set RF_ENV enable. */ 3534 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3535 reg |= 0x100000; 3536 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3537 urtwn_ms_delay(sc); 3538 /* Set RF_ENV output high. */ 3539 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3540 reg |= 0x10; 3541 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3542 urtwn_ms_delay(sc); 3543 /* Set address and data lengths of RF registers. */ 3544 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3545 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3546 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3547 urtwn_ms_delay(sc); 3548 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3549 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3550 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3551 urtwn_ms_delay(sc); 3552 3553 /* Write RF initialization values for this chain. */ 3554 for (j = 0; j < prog[i].count; j++) { 3555 if (prog[i].regs[j] >= 0xf9 && 3556 prog[i].regs[j] <= 0xfe) { 3557 /* 3558 * These are fake RF registers offsets that 3559 * indicate a delay is required. 3560 */ 3561 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 3562 continue; 3563 } 3564 urtwn_rf_write(sc, i, prog[i].regs[j], 3565 prog[i].vals[j]); 3566 urtwn_ms_delay(sc); 3567 } 3568 3569 /* Restore RF_ENV control type. */ 3570 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3571 reg &= ~(0x10 << off) | (type << off); 3572 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 3573 3574 /* Cache RF register CHNLBW. */ 3575 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3576 } 3577 3578 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3579 URTWN_CHIP_UMC_A_CUT) { 3580 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3581 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3582 } 3583} 3584 3585static void 3586urtwn_cam_init(struct urtwn_softc *sc) 3587{ 3588 /* Invalidate all CAM entries. */ 3589 urtwn_write_4(sc, R92C_CAMCMD, 3590 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3591} 3592 3593static int 3594urtwn_cam_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 3595{ 3596 usb_error_t error; 3597 3598 error = urtwn_write_4(sc, R92C_CAMWRITE, data); 3599 if (error != USB_ERR_NORMAL_COMPLETION) 3600 return (EIO); 3601 error = urtwn_write_4(sc, R92C_CAMCMD, 3602 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 3603 SM(R92C_CAMCMD_ADDR, addr)); 3604 if (error != USB_ERR_NORMAL_COMPLETION) 3605 return (EIO); 3606 3607 return (0); 3608} 3609 3610static void 3611urtwn_pa_bias_init(struct urtwn_softc *sc) 3612{ 3613 uint8_t reg; 3614 int i; 3615 3616 for (i = 0; i < sc->nrxchains; i++) { 3617 if (sc->pa_setting & (1 << i)) 3618 continue; 3619 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3620 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3621 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3622 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3623 } 3624 if (!(sc->pa_setting & 0x10)) { 3625 reg = urtwn_read_1(sc, 0x16); 3626 reg = (reg & ~0xf0) | 0x90; 3627 urtwn_write_1(sc, 0x16, reg); 3628 } 3629} 3630 3631static void 3632urtwn_rxfilter_init(struct urtwn_softc *sc) 3633{ 3634 struct ieee80211com *ic = &sc->sc_ic; 3635 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3636 uint32_t rcr; 3637 uint16_t filter; 3638 3639 URTWN_ASSERT_LOCKED(sc); 3640 3641 /* Accept all multicast frames. */ 3642 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3643 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3644 3645 /* Filter for management frames. */ 3646 filter = 0x7f3f; 3647 switch (vap->iv_opmode) { 3648 case IEEE80211_M_STA: 3649 filter &= ~( 3650 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 3651 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 3652 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 3653 break; 3654 case IEEE80211_M_HOSTAP: 3655 filter &= ~( 3656 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 3657 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP) | 3658 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_BEACON)); 3659 break; 3660 case IEEE80211_M_MONITOR: 3661 case IEEE80211_M_IBSS: 3662 break; 3663 default: 3664 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3665 __func__, vap->iv_opmode); 3666 break; 3667 } 3668 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 3669 3670 /* Reject all control frames. */ 3671 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3672 3673 /* Reject all data frames. */ 3674 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 3675 3676 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 3677 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 3678 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 3679 3680 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 3681 /* Accept all frames. */ 3682 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 3683 R92C_RCR_AAP; 3684 } 3685 3686 /* Set Rx filter. */ 3687 urtwn_write_4(sc, R92C_RCR, rcr); 3688 3689 if (ic->ic_promisc != 0) { 3690 /* Update Rx filter. */ 3691 urtwn_set_promisc(sc); 3692 } 3693} 3694 3695static void 3696urtwn_edca_init(struct urtwn_softc *sc) 3697{ 3698 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3699 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3700 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3701 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3702 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3703 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3704 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3705 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3706} 3707 3708static void 3709urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3710 uint16_t power[URTWN_RIDX_COUNT]) 3711{ 3712 uint32_t reg; 3713 3714 /* Write per-CCK rate Tx power. */ 3715 if (chain == 0) { 3716 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3717 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3718 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3719 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3720 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3721 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3722 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3723 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3724 } else { 3725 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3726 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3727 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3728 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3729 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3730 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3731 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3732 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3733 } 3734 /* Write per-OFDM rate Tx power. */ 3735 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3736 SM(R92C_TXAGC_RATE06, power[ 4]) | 3737 SM(R92C_TXAGC_RATE09, power[ 5]) | 3738 SM(R92C_TXAGC_RATE12, power[ 6]) | 3739 SM(R92C_TXAGC_RATE18, power[ 7])); 3740 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3741 SM(R92C_TXAGC_RATE24, power[ 8]) | 3742 SM(R92C_TXAGC_RATE36, power[ 9]) | 3743 SM(R92C_TXAGC_RATE48, power[10]) | 3744 SM(R92C_TXAGC_RATE54, power[11])); 3745 /* Write per-MCS Tx power. */ 3746 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3747 SM(R92C_TXAGC_MCS00, power[12]) | 3748 SM(R92C_TXAGC_MCS01, power[13]) | 3749 SM(R92C_TXAGC_MCS02, power[14]) | 3750 SM(R92C_TXAGC_MCS03, power[15])); 3751 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3752 SM(R92C_TXAGC_MCS04, power[16]) | 3753 SM(R92C_TXAGC_MCS05, power[17]) | 3754 SM(R92C_TXAGC_MCS06, power[18]) | 3755 SM(R92C_TXAGC_MCS07, power[19])); 3756 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3757 SM(R92C_TXAGC_MCS08, power[20]) | 3758 SM(R92C_TXAGC_MCS09, power[21]) | 3759 SM(R92C_TXAGC_MCS10, power[22]) | 3760 SM(R92C_TXAGC_MCS11, power[23])); 3761 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3762 SM(R92C_TXAGC_MCS12, power[24]) | 3763 SM(R92C_TXAGC_MCS13, power[25]) | 3764 SM(R92C_TXAGC_MCS14, power[26]) | 3765 SM(R92C_TXAGC_MCS15, power[27])); 3766} 3767 3768static void 3769urtwn_get_txpower(struct urtwn_softc *sc, int chain, 3770 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3771 uint16_t power[URTWN_RIDX_COUNT]) 3772{ 3773 struct ieee80211com *ic = &sc->sc_ic; 3774 struct r92c_rom *rom = &sc->rom.r92c_rom; 3775 uint16_t cckpow, ofdmpow, htpow, diff, max; 3776 const struct urtwn_txpwr *base; 3777 int ridx, chan, group; 3778 3779 /* Determine channel group. */ 3780 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3781 if (chan <= 3) 3782 group = 0; 3783 else if (chan <= 9) 3784 group = 1; 3785 else 3786 group = 2; 3787 3788 /* Get original Tx power based on board type and RF chain. */ 3789 if (!(sc->chip & URTWN_CHIP_92C)) { 3790 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3791 base = &rtl8188ru_txagc[chain]; 3792 else 3793 base = &rtl8192cu_txagc[chain]; 3794 } else 3795 base = &rtl8192cu_txagc[chain]; 3796 3797 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3798 if (sc->regulatory == 0) { 3799 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3800 power[ridx] = base->pwr[0][ridx]; 3801 } 3802 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3803 if (sc->regulatory == 3) { 3804 power[ridx] = base->pwr[0][ridx]; 3805 /* Apply vendor limits. */ 3806 if (extc != NULL) 3807 max = rom->ht40_max_pwr[group]; 3808 else 3809 max = rom->ht20_max_pwr[group]; 3810 max = (max >> (chain * 4)) & 0xf; 3811 if (power[ridx] > max) 3812 power[ridx] = max; 3813 } else if (sc->regulatory == 1) { 3814 if (extc == NULL) 3815 power[ridx] = base->pwr[group][ridx]; 3816 } else if (sc->regulatory != 2) 3817 power[ridx] = base->pwr[0][ridx]; 3818 } 3819 3820 /* Compute per-CCK rate Tx power. */ 3821 cckpow = rom->cck_tx_pwr[chain][group]; 3822 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3823 power[ridx] += cckpow; 3824 if (power[ridx] > R92C_MAX_TX_PWR) 3825 power[ridx] = R92C_MAX_TX_PWR; 3826 } 3827 3828 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3829 if (sc->ntxchains > 1) { 3830 /* Apply reduction for 2 spatial streams. */ 3831 diff = rom->ht40_2s_tx_pwr_diff[group]; 3832 diff = (diff >> (chain * 4)) & 0xf; 3833 htpow = (htpow > diff) ? htpow - diff : 0; 3834 } 3835 3836 /* Compute per-OFDM rate Tx power. */ 3837 diff = rom->ofdm_tx_pwr_diff[group]; 3838 diff = (diff >> (chain * 4)) & 0xf; 3839 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3840 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3841 power[ridx] += ofdmpow; 3842 if (power[ridx] > R92C_MAX_TX_PWR) 3843 power[ridx] = R92C_MAX_TX_PWR; 3844 } 3845 3846 /* Compute per-MCS Tx power. */ 3847 if (extc == NULL) { 3848 diff = rom->ht20_tx_pwr_diff[group]; 3849 diff = (diff >> (chain * 4)) & 0xf; 3850 htpow += diff; /* HT40->HT20 correction. */ 3851 } 3852 for (ridx = 12; ridx <= 27; ridx++) { 3853 power[ridx] += htpow; 3854 if (power[ridx] > R92C_MAX_TX_PWR) 3855 power[ridx] = R92C_MAX_TX_PWR; 3856 } 3857#ifdef URTWN_DEBUG 3858 if (urtwn_debug >= 4) { 3859 /* Dump per-rate Tx power values. */ 3860 printf("Tx power for chain %d:\n", chain); 3861 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 3862 printf("Rate %d = %u\n", ridx, power[ridx]); 3863 } 3864#endif 3865} 3866 3867static void 3868urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3869 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3870 uint16_t power[URTWN_RIDX_COUNT]) 3871{ 3872 struct ieee80211com *ic = &sc->sc_ic; 3873 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3874 const struct urtwn_r88e_txpwr *base; 3875 int ridx, chan, group; 3876 3877 /* Determine channel group. */ 3878 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3879 if (chan <= 2) 3880 group = 0; 3881 else if (chan <= 5) 3882 group = 1; 3883 else if (chan <= 8) 3884 group = 2; 3885 else if (chan <= 11) 3886 group = 3; 3887 else if (chan <= 13) 3888 group = 4; 3889 else 3890 group = 5; 3891 3892 /* Get original Tx power based on board type and RF chain. */ 3893 base = &rtl8188eu_txagc[chain]; 3894 3895 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3896 if (sc->regulatory == 0) { 3897 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3898 power[ridx] = base->pwr[0][ridx]; 3899 } 3900 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3901 if (sc->regulatory == 3) 3902 power[ridx] = base->pwr[0][ridx]; 3903 else if (sc->regulatory == 1) { 3904 if (extc == NULL) 3905 power[ridx] = base->pwr[group][ridx]; 3906 } else if (sc->regulatory != 2) 3907 power[ridx] = base->pwr[0][ridx]; 3908 } 3909 3910 /* Compute per-CCK rate Tx power. */ 3911 cckpow = sc->cck_tx_pwr[group]; 3912 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3913 power[ridx] += cckpow; 3914 if (power[ridx] > R92C_MAX_TX_PWR) 3915 power[ridx] = R92C_MAX_TX_PWR; 3916 } 3917 3918 htpow = sc->ht40_tx_pwr[group]; 3919 3920 /* Compute per-OFDM rate Tx power. */ 3921 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3922 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3923 power[ridx] += ofdmpow; 3924 if (power[ridx] > R92C_MAX_TX_PWR) 3925 power[ridx] = R92C_MAX_TX_PWR; 3926 } 3927 3928 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3929 for (ridx = 12; ridx <= 27; ridx++) { 3930 power[ridx] += bw20pow; 3931 if (power[ridx] > R92C_MAX_TX_PWR) 3932 power[ridx] = R92C_MAX_TX_PWR; 3933 } 3934} 3935 3936static void 3937urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3938 struct ieee80211_channel *extc) 3939{ 3940 uint16_t power[URTWN_RIDX_COUNT]; 3941 int i; 3942 3943 for (i = 0; i < sc->ntxchains; i++) { 3944 /* Compute per-rate Tx power values. */ 3945 if (sc->chip & URTWN_CHIP_88E) 3946 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3947 else 3948 urtwn_get_txpower(sc, i, c, extc, power); 3949 /* Write per-rate Tx power values to hardware. */ 3950 urtwn_write_txpower(sc, i, power); 3951 } 3952} 3953 3954static void 3955urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 3956{ 3957 uint32_t reg; 3958 3959 reg = urtwn_read_4(sc, R92C_RCR); 3960 if (enable) 3961 reg &= ~R92C_RCR_CBSSID_BCN; 3962 else 3963 reg |= R92C_RCR_CBSSID_BCN; 3964 urtwn_write_4(sc, R92C_RCR, reg); 3965} 3966 3967static void 3968urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 3969{ 3970 uint32_t reg; 3971 3972 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3973 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3974 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3975 3976 if (!(sc->chip & URTWN_CHIP_88E)) { 3977 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3978 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3979 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3980 } 3981} 3982 3983static void 3984urtwn_scan_start(struct ieee80211com *ic) 3985{ 3986 struct urtwn_softc *sc = ic->ic_softc; 3987 3988 URTWN_LOCK(sc); 3989 /* Receive beacons / probe responses from any BSSID. */ 3990 if (ic->ic_opmode != IEEE80211_M_IBSS) 3991 urtwn_set_rx_bssid_all(sc, 1); 3992 3993 /* Set gain for scanning. */ 3994 urtwn_set_gain(sc, 0x20); 3995 URTWN_UNLOCK(sc); 3996} 3997 3998static void 3999urtwn_scan_end(struct ieee80211com *ic) 4000{ 4001 struct urtwn_softc *sc = ic->ic_softc; 4002 4003 URTWN_LOCK(sc); 4004 /* Restore limitations. */ 4005 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 4006 urtwn_set_rx_bssid_all(sc, 0); 4007 4008 /* Set gain under link. */ 4009 urtwn_set_gain(sc, 0x32); 4010 URTWN_UNLOCK(sc); 4011} 4012 4013static void 4014urtwn_set_channel(struct ieee80211com *ic) 4015{ 4016 struct urtwn_softc *sc = ic->ic_softc; 4017 struct ieee80211_channel *c = ic->ic_curchan; 4018 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4019 4020 URTWN_LOCK(sc); 4021 if (vap->iv_state == IEEE80211_S_SCAN) { 4022 /* Make link LED blink during scan. */ 4023 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 4024 } 4025 urtwn_set_chan(sc, c, NULL); 4026 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 4027 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 4028 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 4029 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 4030 URTWN_UNLOCK(sc); 4031} 4032 4033static int 4034urtwn_wme_update(struct ieee80211com *ic) 4035{ 4036 const struct wmeParams *wmep = 4037 ic->ic_wme.wme_chanParams.cap_wmeParams; 4038 struct urtwn_softc *sc = ic->ic_softc; 4039 uint8_t aifs, acm, slottime; 4040 int ac; 4041 4042 acm = 0; 4043 slottime = IEEE80211_GET_SLOTTIME(ic); 4044 4045 URTWN_LOCK(sc); 4046 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 4047 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 4048 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 4049 urtwn_write_4(sc, wme2queue[ac].reg, 4050 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 4051 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 4052 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 4053 SM(R92C_EDCA_PARAM_AIFS, aifs)); 4054 if (ac != WME_AC_BE) 4055 acm |= wmep[ac].wmep_acm << ac; 4056 } 4057 4058 if (acm != 0) 4059 acm |= R92C_ACMHWCTRL_EN; 4060 urtwn_write_1(sc, R92C_ACMHWCTRL, 4061 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 4062 acm); 4063 4064 URTWN_UNLOCK(sc); 4065 4066 return 0; 4067} 4068 4069static void 4070urtwn_set_promisc(struct urtwn_softc *sc) 4071{ 4072 struct ieee80211com *ic = &sc->sc_ic; 4073 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4074 uint32_t rcr, mask1, mask2; 4075 4076 URTWN_ASSERT_LOCKED(sc); 4077 4078 if (vap->iv_opmode == IEEE80211_M_MONITOR) 4079 return; 4080 4081 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 4082 mask2 = R92C_RCR_APM; 4083 4084 if (vap->iv_state == IEEE80211_S_RUN) { 4085 switch (vap->iv_opmode) { 4086 case IEEE80211_M_STA: 4087 mask2 |= R92C_RCR_CBSSID_DATA; 4088 /* FALLTHROUGH */ 4089 case IEEE80211_M_HOSTAP: 4090 mask2 |= R92C_RCR_CBSSID_BCN; 4091 break; 4092 case IEEE80211_M_IBSS: 4093 mask2 |= R92C_RCR_CBSSID_DATA; 4094 break; 4095 default: 4096 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 4097 __func__, vap->iv_opmode); 4098 return; 4099 } 4100 } 4101 4102 rcr = urtwn_read_4(sc, R92C_RCR); 4103 if (ic->ic_promisc == 0) 4104 rcr = (rcr & ~mask1) | mask2; 4105 else 4106 rcr = (rcr & ~mask2) | mask1; 4107 urtwn_write_4(sc, R92C_RCR, rcr); 4108} 4109 4110static void 4111urtwn_update_promisc(struct ieee80211com *ic) 4112{ 4113 struct urtwn_softc *sc = ic->ic_softc; 4114 4115 URTWN_LOCK(sc); 4116 if (sc->sc_flags & URTWN_RUNNING) 4117 urtwn_set_promisc(sc); 4118 URTWN_UNLOCK(sc); 4119} 4120 4121static void 4122urtwn_update_mcast(struct ieee80211com *ic) 4123{ 4124 /* XXX do nothing? */ 4125} 4126 4127static struct ieee80211_node * 4128urtwn_r88e_node_alloc(struct ieee80211vap *vap, 4129 const uint8_t mac[IEEE80211_ADDR_LEN]) 4130{ 4131 struct urtwn_node *un; 4132 4133 un = malloc(sizeof (struct urtwn_node), M_80211_NODE, 4134 M_NOWAIT | M_ZERO); 4135 4136 if (un == NULL) 4137 return NULL; 4138 4139 un->id = URTWN_MACID_UNDEFINED; 4140 4141 return &un->ni; 4142} 4143 4144static void 4145urtwn_r88e_newassoc(struct ieee80211_node *ni, int isnew) 4146{ 4147 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4148 struct urtwn_node *un = URTWN_NODE(ni); 4149 uint8_t id; 4150 4151 if (!isnew) 4152 return; 4153 4154 URTWN_NT_LOCK(sc); 4155 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 4156 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 4157 un->id = id; 4158 sc->node_list[id] = ni; 4159 break; 4160 } 4161 } 4162 URTWN_NT_UNLOCK(sc); 4163 4164 if (id > URTWN_MACID_MAX(sc)) { 4165 device_printf(sc->sc_dev, "%s: node table is full\n", 4166 __func__); 4167 } 4168} 4169 4170static void 4171urtwn_r88e_node_free(struct ieee80211_node *ni) 4172{ 4173 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 4174 struct urtwn_node *un = URTWN_NODE(ni); 4175 4176 URTWN_NT_LOCK(sc); 4177 if (un->id != URTWN_MACID_UNDEFINED) 4178 sc->node_list[un->id] = NULL; 4179 URTWN_NT_UNLOCK(sc); 4180 4181 sc->sc_node_free(ni); 4182} 4183 4184static void 4185urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 4186 struct ieee80211_channel *extc) 4187{ 4188 struct ieee80211com *ic = &sc->sc_ic; 4189 uint32_t reg; 4190 u_int chan; 4191 int i; 4192 4193 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4194 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 4195 device_printf(sc->sc_dev, 4196 "%s: invalid channel %x\n", __func__, chan); 4197 return; 4198 } 4199 4200 /* Set Tx power for this new channel. */ 4201 urtwn_set_txpower(sc, c, extc); 4202 4203 for (i = 0; i < sc->nrxchains; i++) { 4204 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4205 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4206 } 4207#ifndef IEEE80211_NO_HT 4208 if (extc != NULL) { 4209 /* Is secondary channel below or above primary? */ 4210 int prichlo = c->ic_freq < extc->ic_freq; 4211 4212 urtwn_write_1(sc, R92C_BWOPMODE, 4213 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4214 4215 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4216 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4217 urtwn_write_1(sc, R92C_RRSR + 2, reg); 4218 4219 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4220 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4221 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4222 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4223 4224 /* Set CCK side band. */ 4225 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4226 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4227 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4228 4229 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4230 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4231 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4232 4233 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4234 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4235 ~R92C_FPGA0_ANAPARAM2_CBW20); 4236 4237 reg = urtwn_bb_read(sc, 0x818); 4238 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4239 urtwn_bb_write(sc, 0x818, reg); 4240 4241 /* Select 40MHz bandwidth. */ 4242 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4243 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4244 } else 4245#endif 4246 { 4247 urtwn_write_1(sc, R92C_BWOPMODE, 4248 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4249 4250 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4251 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4252 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4253 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4254 4255 if (!(sc->chip & URTWN_CHIP_88E)) { 4256 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4257 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4258 R92C_FPGA0_ANAPARAM2_CBW20); 4259 } 4260 4261 /* Select 20MHz bandwidth. */ 4262 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4263 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4264 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 4265 R92C_RF_CHNLBW_BW20)); 4266 } 4267} 4268 4269static void 4270urtwn_iq_calib(struct urtwn_softc *sc) 4271{ 4272 /* TODO */ 4273} 4274 4275static void 4276urtwn_lc_calib(struct urtwn_softc *sc) 4277{ 4278 uint32_t rf_ac[2]; 4279 uint8_t txmode; 4280 int i; 4281 4282 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4283 if ((txmode & 0x70) != 0) { 4284 /* Disable all continuous Tx. */ 4285 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4286 4287 /* Set RF mode to standby mode. */ 4288 for (i = 0; i < sc->nrxchains; i++) { 4289 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4290 urtwn_rf_write(sc, i, R92C_RF_AC, 4291 RW(rf_ac[i], R92C_RF_AC_MODE, 4292 R92C_RF_AC_MODE_STANDBY)); 4293 } 4294 } else { 4295 /* Block all Tx queues. */ 4296 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4297 } 4298 /* Start calibration. */ 4299 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4300 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4301 4302 /* Give calibration the time to complete. */ 4303 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 4304 4305 /* Restore configuration. */ 4306 if ((txmode & 0x70) != 0) { 4307 /* Restore Tx mode. */ 4308 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4309 /* Restore RF mode. */ 4310 for (i = 0; i < sc->nrxchains; i++) 4311 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4312 } else { 4313 /* Unblock all Tx queues. */ 4314 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4315 } 4316} 4317 4318static int 4319urtwn_init(struct urtwn_softc *sc) 4320{ 4321 struct ieee80211com *ic = &sc->sc_ic; 4322 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4323 uint8_t macaddr[IEEE80211_ADDR_LEN]; 4324 uint32_t reg; 4325 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 4326 int error; 4327 4328 URTWN_LOCK(sc); 4329 if (sc->sc_flags & URTWN_RUNNING) { 4330 URTWN_UNLOCK(sc); 4331 return (0); 4332 } 4333 4334 /* Init firmware commands ring. */ 4335 sc->fwcur = 0; 4336 4337 /* Allocate Tx/Rx buffers. */ 4338 error = urtwn_alloc_rx_list(sc); 4339 if (error != 0) 4340 goto fail; 4341 4342 error = urtwn_alloc_tx_list(sc); 4343 if (error != 0) 4344 goto fail; 4345 4346 /* Power on adapter. */ 4347 error = urtwn_power_on(sc); 4348 if (error != 0) 4349 goto fail; 4350 4351 /* Initialize DMA. */ 4352 error = urtwn_dma_init(sc); 4353 if (error != 0) 4354 goto fail; 4355 4356 /* Set info size in Rx descriptors (in 64-bit words). */ 4357 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4358 4359 /* Init interrupts. */ 4360 if (sc->chip & URTWN_CHIP_88E) { 4361 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4362 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4363 goto fail; 4364 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4365 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4366 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4367 goto fail; 4368 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4369 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4370 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4371 goto fail; 4372 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4373 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4374 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4375 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4376 goto fail; 4377 } else { 4378 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4379 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4380 goto fail; 4381 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4382 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4383 goto fail; 4384 } 4385 4386 /* Set MAC address. */ 4387 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 4388 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 4389 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4390 goto fail; 4391 4392 /* Set initial network type. */ 4393 urtwn_set_mode(sc, R92C_MSR_INFRA); 4394 4395 /* Initialize Rx filter. */ 4396 urtwn_rxfilter_init(sc); 4397 4398 /* Set response rate. */ 4399 reg = urtwn_read_4(sc, R92C_RRSR); 4400 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4401 urtwn_write_4(sc, R92C_RRSR, reg); 4402 4403 /* Set short/long retry limits. */ 4404 urtwn_write_2(sc, R92C_RL, 4405 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4406 4407 /* Initialize EDCA parameters. */ 4408 urtwn_edca_init(sc); 4409 4410 /* Setup rate fallback. */ 4411 if (!(sc->chip & URTWN_CHIP_88E)) { 4412 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4413 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4414 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4415 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4416 } 4417 4418 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4419 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4420 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4421 /* Set ACK timeout. */ 4422 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4423 4424 /* Setup USB aggregation. */ 4425 reg = urtwn_read_4(sc, R92C_TDECTRL); 4426 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4427 urtwn_write_4(sc, R92C_TDECTRL, reg); 4428 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4429 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4430 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4431 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4432 if (sc->chip & URTWN_CHIP_88E) 4433 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4434 else { 4435 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4436 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4437 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4438 R92C_USB_SPECIAL_OPTION_AGG_EN); 4439 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 4440 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 4441 } 4442 4443 /* Initialize beacon parameters. */ 4444 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4445 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4446 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 4447 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 4448 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4449 4450 if (!(sc->chip & URTWN_CHIP_88E)) { 4451 /* Setup AMPDU aggregation. */ 4452 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4453 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4454 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 4455 4456 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4457 } 4458 4459 /* Load 8051 microcode. */ 4460 error = urtwn_load_firmware(sc); 4461 if (error != 0) 4462 goto fail; 4463 4464 /* Initialize MAC/BB/RF blocks. */ 4465 error = urtwn_mac_init(sc); 4466 if (error != 0) { 4467 device_printf(sc->sc_dev, 4468 "%s: error while initializing MAC block\n", __func__); 4469 goto fail; 4470 } 4471 urtwn_bb_init(sc); 4472 urtwn_rf_init(sc); 4473 4474 /* Reinitialize Rx filter (D3845 is not committed yet). */ 4475 urtwn_rxfilter_init(sc); 4476 4477 if (sc->chip & URTWN_CHIP_88E) { 4478 urtwn_write_2(sc, R92C_CR, 4479 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4480 R92C_CR_MACRXEN); 4481 } 4482 4483 /* Turn CCK and OFDM blocks on. */ 4484 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4485 reg |= R92C_RFMOD_CCK_EN; 4486 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4487 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4488 goto fail; 4489 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4490 reg |= R92C_RFMOD_OFDM_EN; 4491 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4492 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4493 goto fail; 4494 4495 /* Clear per-station keys table. */ 4496 urtwn_cam_init(sc); 4497 4498 /* Enable decryption / encryption. */ 4499 urtwn_write_2(sc, R92C_SECCFG, 4500 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 4501 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXDEC_ENA | 4502 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 4503 4504 /* 4505 * Install static keys (if any). 4506 * Must be called after urtwn_cam_init(). 4507 */ 4508 ieee80211_runtask(ic, &sc->cmdq_task); 4509 4510 /* Enable hardware sequence numbering. */ 4511 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4512 4513 /* Enable per-packet TX report. */ 4514 if (sc->chip & URTWN_CHIP_88E) { 4515 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 4516 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 4517 } 4518 4519 /* Perform LO and IQ calibrations. */ 4520 urtwn_iq_calib(sc); 4521 /* Perform LC calibration. */ 4522 urtwn_lc_calib(sc); 4523 4524 /* Fix USB interference issue. */ 4525 if (!(sc->chip & URTWN_CHIP_88E)) { 4526 urtwn_write_1(sc, 0xfe40, 0xe0); 4527 urtwn_write_1(sc, 0xfe41, 0x8d); 4528 urtwn_write_1(sc, 0xfe42, 0x80); 4529 4530 urtwn_pa_bias_init(sc); 4531 } 4532 4533 /* Initialize GPIO setting. */ 4534 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4535 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4536 4537 /* Fix for lower temperature. */ 4538 if (!(sc->chip & URTWN_CHIP_88E)) 4539 urtwn_write_1(sc, 0x15, 0xe9); 4540 4541 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 4542 4543 sc->sc_flags |= URTWN_RUNNING; 4544 4545 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4546fail: 4547 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4548 error = EIO; 4549 4550 URTWN_UNLOCK(sc); 4551 4552 return (error); 4553} 4554 4555static void 4556urtwn_stop(struct urtwn_softc *sc) 4557{ 4558 4559 URTWN_LOCK(sc); 4560 if (!(sc->sc_flags & URTWN_RUNNING)) { 4561 URTWN_UNLOCK(sc); 4562 return; 4563 } 4564 4565 sc->sc_flags &= ~URTWN_RUNNING; 4566 callout_stop(&sc->sc_watchdog_ch); 4567 urtwn_abort_xfers(sc); 4568 4569 urtwn_drain_mbufq(sc); 4570 URTWN_UNLOCK(sc); 4571} 4572 4573static void 4574urtwn_abort_xfers(struct urtwn_softc *sc) 4575{ 4576 int i; 4577 4578 URTWN_ASSERT_LOCKED(sc); 4579 4580 /* abort any pending transfers */ 4581 for (i = 0; i < URTWN_N_TRANSFER; i++) 4582 usbd_transfer_stop(sc->sc_xfer[i]); 4583} 4584 4585static int 4586urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4587 const struct ieee80211_bpf_params *params) 4588{ 4589 struct ieee80211com *ic = ni->ni_ic; 4590 struct urtwn_softc *sc = ic->ic_softc; 4591 struct urtwn_data *bf; 4592 int error; 4593 4594 /* prevent management frames from being sent if we're not ready */ 4595 URTWN_LOCK(sc); 4596 if (!(sc->sc_flags & URTWN_RUNNING)) { 4597 error = ENETDOWN; 4598 goto end; 4599 } 4600 4601 bf = urtwn_getbuf(sc); 4602 if (bf == NULL) { 4603 error = ENOBUFS; 4604 goto end; 4605 } 4606 4607 if ((error = urtwn_tx_data(sc, ni, m, bf)) != 0) { 4608 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 4609 goto end; 4610 } 4611 4612 sc->sc_txtimer = 5; 4613 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4614 4615end: 4616 if (error != 0) 4617 m_freem(m); 4618 4619 URTWN_UNLOCK(sc); 4620 4621 return (error); 4622} 4623 4624static void 4625urtwn_ms_delay(struct urtwn_softc *sc) 4626{ 4627 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 4628} 4629 4630static device_method_t urtwn_methods[] = { 4631 /* Device interface */ 4632 DEVMETHOD(device_probe, urtwn_match), 4633 DEVMETHOD(device_attach, urtwn_attach), 4634 DEVMETHOD(device_detach, urtwn_detach), 4635 4636 DEVMETHOD_END 4637}; 4638 4639static driver_t urtwn_driver = { 4640 "urtwn", 4641 urtwn_methods, 4642 sizeof(struct urtwn_softc) 4643}; 4644 4645static devclass_t urtwn_devclass; 4646 4647DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 4648MODULE_DEPEND(urtwn, usb, 1, 1, 1); 4649MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 4650MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 4651MODULE_VERSION(urtwn, 1); 4652USB_PNP_HOST_INFO(urtwn_devs); 4653