if_urtwn.c revision 292167
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 292167 2015-12-13 21:00:21Z avos $"); 22 23/* 24 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25 */ 26 27#include "opt_wlan.h" 28 29#include <sys/param.h> 30#include <sys/sockio.h> 31#include <sys/sysctl.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/condvar.h> 35#include <sys/mbuf.h> 36#include <sys/kernel.h> 37#include <sys/socket.h> 38#include <sys/systm.h> 39#include <sys/malloc.h> 40#include <sys/module.h> 41#include <sys/bus.h> 42#include <sys/endian.h> 43#include <sys/linker.h> 44#include <sys/firmware.h> 45#include <sys/kdb.h> 46 47#include <machine/bus.h> 48#include <machine/resource.h> 49#include <sys/rman.h> 50 51#include <net/bpf.h> 52#include <net/if.h> 53#include <net/if_var.h> 54#include <net/if_arp.h> 55#include <net/ethernet.h> 56#include <net/if_dl.h> 57#include <net/if_media.h> 58#include <net/if_types.h> 59 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/in_var.h> 63#include <netinet/if_ether.h> 64#include <netinet/ip.h> 65 66#include <net80211/ieee80211_var.h> 67#include <net80211/ieee80211_input.h> 68#include <net80211/ieee80211_regdomain.h> 69#include <net80211/ieee80211_radiotap.h> 70#include <net80211/ieee80211_ratectl.h> 71 72#include <dev/usb/usb.h> 73#include <dev/usb/usbdi.h> 74#include <dev/usb/usb_device.h> 75#include "usbdevs.h" 76 77#define USB_DEBUG_VAR urtwn_debug 78#include <dev/usb/usb_debug.h> 79 80#include <dev/usb/wlan/if_urtwnreg.h> 81#include <dev/usb/wlan/if_urtwnvar.h> 82 83#ifdef USB_DEBUG 84static int urtwn_debug = 0; 85 86SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 87SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 88 "Debug level"); 89#endif 90 91#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 92 93/* various supported device vendors/products */ 94static const STRUCT_USB_HOST_ID urtwn_devs[] = { 95#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 96#define URTWN_RTL8188E_DEV(v,p) \ 97 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 98#define URTWN_RTL8188E 1 99 URTWN_DEV(ABOCOM, RTL8188CU_1), 100 URTWN_DEV(ABOCOM, RTL8188CU_2), 101 URTWN_DEV(ABOCOM, RTL8192CU), 102 URTWN_DEV(ASUS, RTL8192CU), 103 URTWN_DEV(ASUS, USBN10NANO), 104 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 105 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 106 URTWN_DEV(AZUREWAVE, RTL8188CU), 107 URTWN_DEV(BELKIN, F7D2102), 108 URTWN_DEV(BELKIN, RTL8188CU), 109 URTWN_DEV(BELKIN, RTL8192CU), 110 URTWN_DEV(CHICONY, RTL8188CUS_1), 111 URTWN_DEV(CHICONY, RTL8188CUS_2), 112 URTWN_DEV(CHICONY, RTL8188CUS_3), 113 URTWN_DEV(CHICONY, RTL8188CUS_4), 114 URTWN_DEV(CHICONY, RTL8188CUS_5), 115 URTWN_DEV(COREGA, RTL8192CU), 116 URTWN_DEV(DLINK, RTL8188CU), 117 URTWN_DEV(DLINK, RTL8192CU_1), 118 URTWN_DEV(DLINK, RTL8192CU_2), 119 URTWN_DEV(DLINK, RTL8192CU_3), 120 URTWN_DEV(DLINK, DWA131B), 121 URTWN_DEV(EDIMAX, EW7811UN), 122 URTWN_DEV(EDIMAX, RTL8192CU), 123 URTWN_DEV(FEIXUN, RTL8188CU), 124 URTWN_DEV(FEIXUN, RTL8192CU), 125 URTWN_DEV(GUILLEMOT, HWNUP150), 126 URTWN_DEV(HAWKING, RTL8192CU), 127 URTWN_DEV(HP3, RTL8188CU), 128 URTWN_DEV(NETGEAR, WNA1000M), 129 URTWN_DEV(NETGEAR, RTL8192CU), 130 URTWN_DEV(NETGEAR4, RTL8188CU), 131 URTWN_DEV(NOVATECH, RTL8188CU), 132 URTWN_DEV(PLANEX2, RTL8188CU_1), 133 URTWN_DEV(PLANEX2, RTL8188CU_2), 134 URTWN_DEV(PLANEX2, RTL8188CU_3), 135 URTWN_DEV(PLANEX2, RTL8188CU_4), 136 URTWN_DEV(PLANEX2, RTL8188CUS), 137 URTWN_DEV(PLANEX2, RTL8192CU), 138 URTWN_DEV(REALTEK, RTL8188CE_0), 139 URTWN_DEV(REALTEK, RTL8188CE_1), 140 URTWN_DEV(REALTEK, RTL8188CTV), 141 URTWN_DEV(REALTEK, RTL8188CU_0), 142 URTWN_DEV(REALTEK, RTL8188CU_1), 143 URTWN_DEV(REALTEK, RTL8188CU_2), 144 URTWN_DEV(REALTEK, RTL8188CU_3), 145 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 146 URTWN_DEV(REALTEK, RTL8188CUS), 147 URTWN_DEV(REALTEK, RTL8188RU_1), 148 URTWN_DEV(REALTEK, RTL8188RU_2), 149 URTWN_DEV(REALTEK, RTL8188RU_3), 150 URTWN_DEV(REALTEK, RTL8191CU), 151 URTWN_DEV(REALTEK, RTL8192CE), 152 URTWN_DEV(REALTEK, RTL8192CU), 153 URTWN_DEV(SITECOMEU, RTL8188CU_1), 154 URTWN_DEV(SITECOMEU, RTL8188CU_2), 155 URTWN_DEV(SITECOMEU, RTL8192CU), 156 URTWN_DEV(TRENDNET, RTL8188CU), 157 URTWN_DEV(TRENDNET, RTL8192CU), 158 URTWN_DEV(ZYXEL, RTL8192CU), 159 /* URTWN_RTL8188E */ 160 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 161 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 162 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 163 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 164 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 165#undef URTWN_RTL8188E_DEV 166#undef URTWN_DEV 167}; 168 169static device_probe_t urtwn_match; 170static device_attach_t urtwn_attach; 171static device_detach_t urtwn_detach; 172 173static usb_callback_t urtwn_bulk_tx_callback; 174static usb_callback_t urtwn_bulk_rx_callback; 175 176static void urtwn_drain_mbufq(struct urtwn_softc *sc); 177static usb_error_t urtwn_do_request(struct urtwn_softc *, 178 struct usb_device_request *, void *); 179static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 180 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 181 const uint8_t [IEEE80211_ADDR_LEN], 182 const uint8_t [IEEE80211_ADDR_LEN]); 183static void urtwn_vap_delete(struct ieee80211vap *); 184static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 185 int *); 186static struct mbuf * urtwn_report_intr(struct usb_xfer *, struct urtwn_data *, 187 int *, int8_t *); 188static struct mbuf * urtwn_rxeof(struct urtwn_softc *, uint8_t *, int, 189 int *, int8_t *); 190static void urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *, 191 void *); 192static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 193 int); 194static int urtwn_alloc_list(struct urtwn_softc *, 195 struct urtwn_data[], int, int); 196static int urtwn_alloc_rx_list(struct urtwn_softc *); 197static int urtwn_alloc_tx_list(struct urtwn_softc *); 198static void urtwn_free_list(struct urtwn_softc *, 199 struct urtwn_data data[], int); 200static void urtwn_free_rx_list(struct urtwn_softc *); 201static void urtwn_free_tx_list(struct urtwn_softc *); 202static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 203static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 204static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 205 uint8_t *, int); 206static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 207static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 208static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 209static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 210 uint8_t *, int); 211static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 212static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 213static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 214static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 215 const void *, int); 216static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 217 uint8_t, uint32_t); 218static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 219 uint8_t, uint32_t); 220static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 221static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 222 uint32_t); 223static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 224static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 225 uint8_t, uint8_t); 226#ifdef URTWN_DEBUG 227static void urtwn_dump_rom_contents(struct urtwn_softc *, 228 uint8_t *, uint16_t); 229#endif 230static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 231 uint16_t); 232static int urtwn_efuse_switch_power(struct urtwn_softc *); 233static int urtwn_read_chipid(struct urtwn_softc *); 234static int urtwn_read_rom(struct urtwn_softc *); 235static int urtwn_r88e_read_rom(struct urtwn_softc *); 236static int urtwn_ra_init(struct urtwn_softc *); 237static void urtwn_init_beacon(struct urtwn_softc *, 238 struct urtwn_vap *); 239static int urtwn_setup_beacon(struct urtwn_softc *, 240 struct ieee80211_node *); 241static void urtwn_update_beacon(struct ieee80211vap *, int); 242static int urtwn_tx_beacon(struct urtwn_softc *sc, 243 struct urtwn_vap *); 244static void urtwn_tsf_task_adhoc(void *, int); 245static void urtwn_tsf_sync_enable(struct urtwn_softc *, 246 struct ieee80211vap *); 247static void urtwn_set_led(struct urtwn_softc *, int, int); 248static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 249static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 250 struct mbuf *, int, 251 const struct ieee80211_rx_stats *, int, int); 252static int urtwn_newstate(struct ieee80211vap *, 253 enum ieee80211_state, int); 254static void urtwn_watchdog(void *); 255static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 256static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 257static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 258static int urtwn_tx_data(struct urtwn_softc *, 259 struct ieee80211_node *, struct mbuf *, 260 struct urtwn_data *); 261static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 262 uint8_t, struct urtwn_data *); 263static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 264static void urtwn_start(struct urtwn_softc *); 265static void urtwn_parent(struct ieee80211com *); 266static int urtwn_r92c_power_on(struct urtwn_softc *); 267static int urtwn_r88e_power_on(struct urtwn_softc *); 268static int urtwn_llt_init(struct urtwn_softc *); 269static void urtwn_fw_reset(struct urtwn_softc *); 270static void urtwn_r88e_fw_reset(struct urtwn_softc *); 271static int urtwn_fw_loadpage(struct urtwn_softc *, int, 272 const uint8_t *, int); 273static int urtwn_load_firmware(struct urtwn_softc *); 274static int urtwn_dma_init(struct urtwn_softc *); 275static int urtwn_mac_init(struct urtwn_softc *); 276static void urtwn_bb_init(struct urtwn_softc *); 277static void urtwn_rf_init(struct urtwn_softc *); 278static void urtwn_cam_init(struct urtwn_softc *); 279static void urtwn_pa_bias_init(struct urtwn_softc *); 280static void urtwn_rxfilter_init(struct urtwn_softc *); 281static void urtwn_edca_init(struct urtwn_softc *); 282static void urtwn_write_txpower(struct urtwn_softc *, int, 283 uint16_t[]); 284static void urtwn_get_txpower(struct urtwn_softc *, int, 285 struct ieee80211_channel *, 286 struct ieee80211_channel *, uint16_t[]); 287static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 288 struct ieee80211_channel *, 289 struct ieee80211_channel *, uint16_t[]); 290static void urtwn_set_txpower(struct urtwn_softc *, 291 struct ieee80211_channel *, 292 struct ieee80211_channel *); 293static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 294static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 295static void urtwn_scan_start(struct ieee80211com *); 296static void urtwn_scan_end(struct ieee80211com *); 297static void urtwn_set_channel(struct ieee80211com *); 298static int urtwn_wme_update(struct ieee80211com *); 299static void urtwn_set_promisc(struct urtwn_softc *); 300static void urtwn_update_promisc(struct ieee80211com *); 301static void urtwn_update_mcast(struct ieee80211com *); 302static struct ieee80211_node *urtwn_r88e_node_alloc(struct ieee80211vap *, 303 const uint8_t mac[IEEE80211_ADDR_LEN]); 304static void urtwn_r88e_newassoc(struct ieee80211_node *, int); 305static void urtwn_r88e_node_free(struct ieee80211_node *); 306static void urtwn_set_chan(struct urtwn_softc *, 307 struct ieee80211_channel *, 308 struct ieee80211_channel *); 309static void urtwn_iq_calib(struct urtwn_softc *); 310static void urtwn_lc_calib(struct urtwn_softc *); 311static int urtwn_init(struct urtwn_softc *); 312static void urtwn_stop(struct urtwn_softc *); 313static void urtwn_abort_xfers(struct urtwn_softc *); 314static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 315 const struct ieee80211_bpf_params *); 316static void urtwn_ms_delay(struct urtwn_softc *); 317 318/* Aliases. */ 319#define urtwn_bb_write urtwn_write_4 320#define urtwn_bb_read urtwn_read_4 321 322static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 323 [URTWN_BULK_RX] = { 324 .type = UE_BULK, 325 .endpoint = UE_ADDR_ANY, 326 .direction = UE_DIR_IN, 327 .bufsize = URTWN_RXBUFSZ, 328 .flags = { 329 .pipe_bof = 1, 330 .short_xfer_ok = 1 331 }, 332 .callback = urtwn_bulk_rx_callback, 333 }, 334 [URTWN_BULK_TX_BE] = { 335 .type = UE_BULK, 336 .endpoint = 0x03, 337 .direction = UE_DIR_OUT, 338 .bufsize = URTWN_TXBUFSZ, 339 .flags = { 340 .ext_buffer = 1, 341 .pipe_bof = 1, 342 .force_short_xfer = 1 343 }, 344 .callback = urtwn_bulk_tx_callback, 345 .timeout = URTWN_TX_TIMEOUT, /* ms */ 346 }, 347 [URTWN_BULK_TX_BK] = { 348 .type = UE_BULK, 349 .endpoint = 0x03, 350 .direction = UE_DIR_OUT, 351 .bufsize = URTWN_TXBUFSZ, 352 .flags = { 353 .ext_buffer = 1, 354 .pipe_bof = 1, 355 .force_short_xfer = 1, 356 }, 357 .callback = urtwn_bulk_tx_callback, 358 .timeout = URTWN_TX_TIMEOUT, /* ms */ 359 }, 360 [URTWN_BULK_TX_VI] = { 361 .type = UE_BULK, 362 .endpoint = 0x02, 363 .direction = UE_DIR_OUT, 364 .bufsize = URTWN_TXBUFSZ, 365 .flags = { 366 .ext_buffer = 1, 367 .pipe_bof = 1, 368 .force_short_xfer = 1 369 }, 370 .callback = urtwn_bulk_tx_callback, 371 .timeout = URTWN_TX_TIMEOUT, /* ms */ 372 }, 373 [URTWN_BULK_TX_VO] = { 374 .type = UE_BULK, 375 .endpoint = 0x02, 376 .direction = UE_DIR_OUT, 377 .bufsize = URTWN_TXBUFSZ, 378 .flags = { 379 .ext_buffer = 1, 380 .pipe_bof = 1, 381 .force_short_xfer = 1 382 }, 383 .callback = urtwn_bulk_tx_callback, 384 .timeout = URTWN_TX_TIMEOUT, /* ms */ 385 }, 386}; 387 388static const struct wme_to_queue { 389 uint16_t reg; 390 uint8_t qid; 391} wme2queue[WME_NUM_AC] = { 392 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 393 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 394 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 395 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 396}; 397 398static int 399urtwn_match(device_t self) 400{ 401 struct usb_attach_arg *uaa = device_get_ivars(self); 402 403 if (uaa->usb_mode != USB_MODE_HOST) 404 return (ENXIO); 405 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 406 return (ENXIO); 407 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 408 return (ENXIO); 409 410 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 411} 412 413static int 414urtwn_attach(device_t self) 415{ 416 struct usb_attach_arg *uaa = device_get_ivars(self); 417 struct urtwn_softc *sc = device_get_softc(self); 418 struct ieee80211com *ic = &sc->sc_ic; 419 uint8_t bands; 420 int error; 421 422 device_set_usb_desc(self); 423 sc->sc_udev = uaa->device; 424 sc->sc_dev = self; 425 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 426 sc->chip |= URTWN_CHIP_88E; 427 428 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 429 MTX_NETWORK_LOCK, MTX_DEF); 430 URTWN_NT_LOCK_INIT(sc); 431 callout_init(&sc->sc_watchdog_ch, 0); 432 mbufq_init(&sc->sc_snd, ifqmaxlen); 433 434 sc->sc_iface_index = URTWN_IFACE_INDEX; 435 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 436 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 437 if (error) { 438 device_printf(self, "could not allocate USB transfers, " 439 "err=%s\n", usbd_errstr(error)); 440 goto detach; 441 } 442 443 URTWN_LOCK(sc); 444 445 error = urtwn_read_chipid(sc); 446 if (error) { 447 device_printf(sc->sc_dev, "unsupported test chip\n"); 448 URTWN_UNLOCK(sc); 449 goto detach; 450 } 451 452 /* Determine number of Tx/Rx chains. */ 453 if (sc->chip & URTWN_CHIP_92C) { 454 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 455 sc->nrxchains = 2; 456 } else { 457 sc->ntxchains = 1; 458 sc->nrxchains = 1; 459 } 460 461 if (sc->chip & URTWN_CHIP_88E) 462 error = urtwn_r88e_read_rom(sc); 463 else 464 error = urtwn_read_rom(sc); 465 if (error != 0) { 466 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 467 __func__, error); 468 URTWN_UNLOCK(sc); 469 goto detach; 470 } 471 472 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 473 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 474 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 475 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 476 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 477 "8188CUS", sc->ntxchains, sc->nrxchains); 478 479 URTWN_UNLOCK(sc); 480 481 ic->ic_softc = sc; 482 ic->ic_name = device_get_nameunit(self); 483 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 484 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 485 486 /* set device capabilities */ 487 ic->ic_caps = 488 IEEE80211_C_STA /* station mode */ 489 | IEEE80211_C_MONITOR /* monitor mode */ 490 | IEEE80211_C_IBSS /* adhoc mode */ 491 | IEEE80211_C_HOSTAP /* hostap mode */ 492 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 493 | IEEE80211_C_SHSLOT /* short slot time supported */ 494 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 495 | IEEE80211_C_WPA /* 802.11i */ 496 | IEEE80211_C_WME /* 802.11e */ 497 ; 498 499 bands = 0; 500 setbit(&bands, IEEE80211_MODE_11B); 501 setbit(&bands, IEEE80211_MODE_11G); 502 ieee80211_init_channels(ic, NULL, &bands); 503 504 ieee80211_ifattach(ic); 505 ic->ic_raw_xmit = urtwn_raw_xmit; 506 ic->ic_scan_start = urtwn_scan_start; 507 ic->ic_scan_end = urtwn_scan_end; 508 ic->ic_set_channel = urtwn_set_channel; 509 ic->ic_transmit = urtwn_transmit; 510 ic->ic_parent = urtwn_parent; 511 ic->ic_vap_create = urtwn_vap_create; 512 ic->ic_vap_delete = urtwn_vap_delete; 513 ic->ic_wme.wme_update = urtwn_wme_update; 514 ic->ic_update_promisc = urtwn_update_promisc; 515 ic->ic_update_mcast = urtwn_update_mcast; 516 if (sc->chip & URTWN_CHIP_88E) { 517 ic->ic_node_alloc = urtwn_r88e_node_alloc; 518 ic->ic_newassoc = urtwn_r88e_newassoc; 519 sc->sc_node_free = ic->ic_node_free; 520 ic->ic_node_free = urtwn_r88e_node_free; 521 } 522 523 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 524 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 525 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 526 URTWN_RX_RADIOTAP_PRESENT); 527 528 if (bootverbose) 529 ieee80211_announce(ic); 530 531 return (0); 532 533detach: 534 urtwn_detach(self); 535 return (ENXIO); /* failure */ 536} 537 538static int 539urtwn_detach(device_t self) 540{ 541 struct urtwn_softc *sc = device_get_softc(self); 542 struct ieee80211com *ic = &sc->sc_ic; 543 unsigned int x; 544 545 /* Prevent further ioctls. */ 546 URTWN_LOCK(sc); 547 sc->sc_flags |= URTWN_DETACHED; 548 URTWN_UNLOCK(sc); 549 550 urtwn_stop(sc); 551 552 callout_drain(&sc->sc_watchdog_ch); 553 554 /* stop all USB transfers */ 555 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 556 557 /* Prevent further allocations from RX/TX data lists. */ 558 URTWN_LOCK(sc); 559 STAILQ_INIT(&sc->sc_tx_active); 560 STAILQ_INIT(&sc->sc_tx_inactive); 561 STAILQ_INIT(&sc->sc_tx_pending); 562 563 STAILQ_INIT(&sc->sc_rx_active); 564 STAILQ_INIT(&sc->sc_rx_inactive); 565 URTWN_UNLOCK(sc); 566 567 /* drain USB transfers */ 568 for (x = 0; x != URTWN_N_TRANSFER; x++) 569 usbd_transfer_drain(sc->sc_xfer[x]); 570 571 /* Free data buffers. */ 572 URTWN_LOCK(sc); 573 urtwn_free_tx_list(sc); 574 urtwn_free_rx_list(sc); 575 URTWN_UNLOCK(sc); 576 577 ieee80211_ifdetach(ic); 578 URTWN_NT_LOCK_DESTROY(sc); 579 mtx_destroy(&sc->sc_mtx); 580 581 return (0); 582} 583 584static void 585urtwn_drain_mbufq(struct urtwn_softc *sc) 586{ 587 struct mbuf *m; 588 struct ieee80211_node *ni; 589 URTWN_ASSERT_LOCKED(sc); 590 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 591 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 592 m->m_pkthdr.rcvif = NULL; 593 ieee80211_free_node(ni); 594 m_freem(m); 595 } 596} 597 598static usb_error_t 599urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 600 void *data) 601{ 602 usb_error_t err; 603 int ntries = 10; 604 605 URTWN_ASSERT_LOCKED(sc); 606 607 while (ntries--) { 608 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 609 req, data, 0, NULL, 250 /* ms */); 610 if (err == 0) 611 break; 612 613 DPRINTFN(1, "Control request failed, %s (retrying)\n", 614 usbd_errstr(err)); 615 usb_pause_mtx(&sc->sc_mtx, hz / 100); 616 } 617 return (err); 618} 619 620static struct ieee80211vap * 621urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 622 enum ieee80211_opmode opmode, int flags, 623 const uint8_t bssid[IEEE80211_ADDR_LEN], 624 const uint8_t mac[IEEE80211_ADDR_LEN]) 625{ 626 struct urtwn_softc *sc = ic->ic_softc; 627 struct urtwn_vap *uvp; 628 struct ieee80211vap *vap; 629 630 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 631 return (NULL); 632 633 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 634 vap = &uvp->vap; 635 /* enable s/w bmiss handling for sta mode */ 636 637 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 638 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 639 /* out of memory */ 640 free(uvp, M_80211_VAP); 641 return (NULL); 642 } 643 644 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 645 urtwn_init_beacon(sc, uvp); 646 647 /* override state transition machine */ 648 uvp->newstate = vap->iv_newstate; 649 vap->iv_newstate = urtwn_newstate; 650 vap->iv_update_beacon = urtwn_update_beacon; 651 if (opmode == IEEE80211_M_IBSS) { 652 uvp->recv_mgmt = vap->iv_recv_mgmt; 653 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 654 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 655 } 656 657 if (URTWN_CHIP_HAS_RATECTL(sc)) 658 ieee80211_ratectl_init(vap); 659 /* complete setup */ 660 ieee80211_vap_attach(vap, ieee80211_media_change, 661 ieee80211_media_status, mac); 662 ic->ic_opmode = opmode; 663 return (vap); 664} 665 666static void 667urtwn_vap_delete(struct ieee80211vap *vap) 668{ 669 struct ieee80211com *ic = vap->iv_ic; 670 struct urtwn_softc *sc = ic->ic_softc; 671 struct urtwn_vap *uvp = URTWN_VAP(vap); 672 673 if (uvp->bcn_mbuf != NULL) 674 m_freem(uvp->bcn_mbuf); 675 if (vap->iv_opmode == IEEE80211_M_IBSS) 676 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 677 if (URTWN_CHIP_HAS_RATECTL(sc)) 678 ieee80211_ratectl_deinit(vap); 679 ieee80211_vap_detach(vap); 680 free(uvp, M_80211_VAP); 681} 682 683static struct mbuf * 684urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 685{ 686 struct ieee80211com *ic = &sc->sc_ic; 687 struct ieee80211_frame *wh; 688 struct mbuf *m; 689 struct r92c_rx_stat *stat; 690 uint32_t rxdw0, rxdw3; 691 uint8_t rate; 692 int8_t rssi = 0; 693 int infosz; 694 695 /* 696 * don't pass packets to the ieee80211 framework if the driver isn't 697 * RUNNING. 698 */ 699 if (!(sc->sc_flags & URTWN_RUNNING)) 700 return (NULL); 701 702 stat = (struct r92c_rx_stat *)buf; 703 rxdw0 = le32toh(stat->rxdw0); 704 rxdw3 = le32toh(stat->rxdw3); 705 706 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 707 /* 708 * This should not happen since we setup our Rx filter 709 * to not receive these frames. 710 */ 711 counter_u64_add(ic->ic_ierrors, 1); 712 return (NULL); 713 } 714 if (pktlen < sizeof(struct ieee80211_frame_ack) || 715 pktlen > MCLBYTES) { 716 counter_u64_add(ic->ic_ierrors, 1); 717 return (NULL); 718 } 719 720 rate = MS(rxdw3, R92C_RXDW3_RATE); 721 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 722 723 /* Get RSSI from PHY status descriptor if present. */ 724 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 725 if (sc->chip & URTWN_CHIP_88E) 726 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 727 else 728 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 729 /* Update our average RSSI. */ 730 urtwn_update_avgrssi(sc, rate, rssi); 731 } 732 733 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 734 if (m == NULL) { 735 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 736 return (NULL); 737 } 738 739 /* Finalize mbuf. */ 740 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 741 memcpy(mtod(m, uint8_t *), wh, pktlen); 742 m->m_pkthdr.len = m->m_len = pktlen; 743 744 if (ieee80211_radiotap_active(ic)) { 745 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 746 747 tap->wr_flags = 0; 748 /* Map HW rate index to 802.11 rate. */ 749 if (!(rxdw3 & R92C_RXDW3_HT)) { 750 tap->wr_rate = ridx2rate[rate]; 751 } else if (rate >= 12) { /* MCS0~15. */ 752 /* Bit 7 set means HT MCS instead of rate. */ 753 tap->wr_rate = 0x80 | (rate - 12); 754 } 755 tap->wr_dbm_antsignal = rssi; 756 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 757 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 758 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 759 } 760 761 *rssi_p = rssi; 762 763 return (m); 764} 765 766static struct mbuf * 767urtwn_report_intr(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 768 int8_t *nf) 769{ 770 struct urtwn_softc *sc = data->sc; 771 struct ieee80211com *ic = &sc->sc_ic; 772 struct r92c_rx_stat *stat; 773 uint8_t *buf; 774 int len; 775 776 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 777 778 if (len < sizeof(*stat)) { 779 counter_u64_add(ic->ic_ierrors, 1); 780 return (NULL); 781 } 782 783 buf = data->buf; 784 stat = (struct r92c_rx_stat *)buf; 785 786 if (sc->chip & URTWN_CHIP_88E) { 787 int report_sel = MS(le32toh(stat->rxdw3), R88E_RXDW3_RPT); 788 789 switch (report_sel) { 790 case R88E_RXDW3_RPT_RX: 791 return (urtwn_rxeof(sc, buf, len, rssi, nf)); 792 case R88E_RXDW3_RPT_TX1: 793 urtwn_r88e_ratectl_tx_complete(sc, &stat[1]); 794 break; 795 default: 796 DPRINTFN(7, "case %d was not handled\n", report_sel); 797 break; 798 } 799 } else 800 return (urtwn_rxeof(sc, buf, len, rssi, nf)); 801 802 return (NULL); 803} 804 805static struct mbuf * 806urtwn_rxeof(struct urtwn_softc *sc, uint8_t *buf, int len, int *rssi, 807 int8_t *nf) 808{ 809 struct r92c_rx_stat *stat; 810 struct mbuf *m, *m0 = NULL, *prevm = NULL; 811 uint32_t rxdw0; 812 int totlen, pktlen, infosz, npkts; 813 814 /* Get the number of encapsulated frames. */ 815 stat = (struct r92c_rx_stat *)buf; 816 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 817 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 818 819 /* Process all of them. */ 820 while (npkts-- > 0) { 821 if (len < sizeof(*stat)) 822 break; 823 stat = (struct r92c_rx_stat *)buf; 824 rxdw0 = le32toh(stat->rxdw0); 825 826 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 827 if (pktlen == 0) 828 break; 829 830 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 831 832 /* Make sure everything fits in xfer. */ 833 totlen = sizeof(*stat) + infosz + pktlen; 834 if (totlen > len) 835 break; 836 837 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 838 if (m0 == NULL) 839 m0 = m; 840 if (prevm == NULL) 841 prevm = m; 842 else { 843 prevm->m_next = m; 844 prevm = m; 845 } 846 847 /* Next chunk is 128-byte aligned. */ 848 totlen = (totlen + 127) & ~127; 849 buf += totlen; 850 len -= totlen; 851 } 852 853 return (m0); 854} 855 856static void 857urtwn_r88e_ratectl_tx_complete(struct urtwn_softc *sc, void *arg) 858{ 859 struct r88e_tx_rpt_ccx *rpt = arg; 860 struct ieee80211vap *vap; 861 struct ieee80211_node *ni; 862 uint8_t macid; 863 int ntries; 864 865 macid = MS(rpt->rptb1, R88E_RPTB1_MACID); 866 ntries = MS(rpt->rptb2, R88E_RPTB2_RETRY_CNT); 867 868 URTWN_NT_LOCK(sc); 869 ni = sc->node_list[macid]; 870 if (ni != NULL) { 871 vap = ni->ni_vap; 872 873 if (rpt->rptb1 & R88E_RPTB1_PKT_OK) { 874 ieee80211_ratectl_tx_complete(vap, ni, 875 IEEE80211_RATECTL_TX_SUCCESS, &ntries, NULL); 876 } else { 877 ieee80211_ratectl_tx_complete(vap, ni, 878 IEEE80211_RATECTL_TX_FAILURE, &ntries, NULL); 879 } 880 } else 881 DPRINTFN(8, "macid %d, ni is NULL\n", macid); 882 URTWN_NT_UNLOCK(sc); 883} 884 885static void 886urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 887{ 888 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 889 struct ieee80211com *ic = &sc->sc_ic; 890 struct ieee80211_frame_min *wh; 891 struct ieee80211_node *ni; 892 struct mbuf *m = NULL, *next; 893 struct urtwn_data *data; 894 int8_t nf; 895 int rssi = 1; 896 897 URTWN_ASSERT_LOCKED(sc); 898 899 switch (USB_GET_STATE(xfer)) { 900 case USB_ST_TRANSFERRED: 901 data = STAILQ_FIRST(&sc->sc_rx_active); 902 if (data == NULL) 903 goto tr_setup; 904 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 905 m = urtwn_report_intr(xfer, data, &rssi, &nf); 906 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 907 /* FALLTHROUGH */ 908 case USB_ST_SETUP: 909tr_setup: 910 data = STAILQ_FIRST(&sc->sc_rx_inactive); 911 if (data == NULL) { 912 KASSERT(m == NULL, ("mbuf isn't NULL")); 913 return; 914 } 915 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 916 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 917 usbd_xfer_set_frame_data(xfer, 0, data->buf, 918 usbd_xfer_max_len(xfer)); 919 usbd_transfer_submit(xfer); 920 921 /* 922 * To avoid LOR we should unlock our private mutex here to call 923 * ieee80211_input() because here is at the end of a USB 924 * callback and safe to unlock. 925 */ 926 URTWN_UNLOCK(sc); 927 while (m != NULL) { 928 next = m->m_next; 929 m->m_next = NULL; 930 wh = mtod(m, struct ieee80211_frame_min *); 931 if (m->m_len >= sizeof(*wh)) 932 ni = ieee80211_find_rxnode(ic, wh); 933 else 934 ni = NULL; 935 nf = URTWN_NOISE_FLOOR; 936 if (ni != NULL) { 937 (void)ieee80211_input(ni, m, rssi - nf, nf); 938 ieee80211_free_node(ni); 939 } else { 940 (void)ieee80211_input_all(ic, m, rssi - nf, 941 nf); 942 } 943 m = next; 944 } 945 URTWN_LOCK(sc); 946 break; 947 default: 948 /* needs it to the inactive queue due to a error. */ 949 data = STAILQ_FIRST(&sc->sc_rx_active); 950 if (data != NULL) { 951 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 952 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 953 } 954 if (error != USB_ERR_CANCELLED) { 955 usbd_xfer_set_stall(xfer); 956 counter_u64_add(ic->ic_ierrors, 1); 957 goto tr_setup; 958 } 959 break; 960 } 961} 962 963static void 964urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 965{ 966 967 URTWN_ASSERT_LOCKED(sc); 968 969 if (data->ni != NULL) /* not a beacon frame */ 970 ieee80211_tx_complete(data->ni, data->m, status); 971 972 data->ni = NULL; 973 data->m = NULL; 974 975 sc->sc_txtimer = 0; 976 977 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 978} 979 980static int 981urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 982 int ndata, int maxsz) 983{ 984 int i, error; 985 986 for (i = 0; i < ndata; i++) { 987 struct urtwn_data *dp = &data[i]; 988 dp->sc = sc; 989 dp->m = NULL; 990 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 991 if (dp->buf == NULL) { 992 device_printf(sc->sc_dev, 993 "could not allocate buffer\n"); 994 error = ENOMEM; 995 goto fail; 996 } 997 dp->ni = NULL; 998 } 999 1000 return (0); 1001fail: 1002 urtwn_free_list(sc, data, ndata); 1003 return (error); 1004} 1005 1006static int 1007urtwn_alloc_rx_list(struct urtwn_softc *sc) 1008{ 1009 int error, i; 1010 1011 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1012 URTWN_RXBUFSZ); 1013 if (error != 0) 1014 return (error); 1015 1016 STAILQ_INIT(&sc->sc_rx_active); 1017 STAILQ_INIT(&sc->sc_rx_inactive); 1018 1019 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1020 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1021 1022 return (0); 1023} 1024 1025static int 1026urtwn_alloc_tx_list(struct urtwn_softc *sc) 1027{ 1028 int error, i; 1029 1030 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1031 URTWN_TXBUFSZ); 1032 if (error != 0) 1033 return (error); 1034 1035 STAILQ_INIT(&sc->sc_tx_active); 1036 STAILQ_INIT(&sc->sc_tx_inactive); 1037 STAILQ_INIT(&sc->sc_tx_pending); 1038 1039 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1040 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1041 1042 return (0); 1043} 1044 1045static void 1046urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 1047{ 1048 int i; 1049 1050 for (i = 0; i < ndata; i++) { 1051 struct urtwn_data *dp = &data[i]; 1052 1053 if (dp->buf != NULL) { 1054 free(dp->buf, M_USBDEV); 1055 dp->buf = NULL; 1056 } 1057 if (dp->ni != NULL) { 1058 ieee80211_free_node(dp->ni); 1059 dp->ni = NULL; 1060 } 1061 } 1062} 1063 1064static void 1065urtwn_free_rx_list(struct urtwn_softc *sc) 1066{ 1067 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 1068} 1069 1070static void 1071urtwn_free_tx_list(struct urtwn_softc *sc) 1072{ 1073 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 1074} 1075 1076static void 1077urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1078{ 1079 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1080 struct urtwn_data *data; 1081 1082 URTWN_ASSERT_LOCKED(sc); 1083 1084 switch (USB_GET_STATE(xfer)){ 1085 case USB_ST_TRANSFERRED: 1086 data = STAILQ_FIRST(&sc->sc_tx_active); 1087 if (data == NULL) 1088 goto tr_setup; 1089 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1090 urtwn_txeof(sc, data, 0); 1091 /* FALLTHROUGH */ 1092 case USB_ST_SETUP: 1093tr_setup: 1094 data = STAILQ_FIRST(&sc->sc_tx_pending); 1095 if (data == NULL) { 1096 DPRINTF("%s: empty pending queue\n", __func__); 1097 goto finish; 1098 } 1099 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1100 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1101 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1102 usbd_transfer_submit(xfer); 1103 break; 1104 default: 1105 data = STAILQ_FIRST(&sc->sc_tx_active); 1106 if (data == NULL) 1107 goto tr_setup; 1108 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1109 urtwn_txeof(sc, data, 1); 1110 if (error != USB_ERR_CANCELLED) { 1111 usbd_xfer_set_stall(xfer); 1112 goto tr_setup; 1113 } 1114 break; 1115 } 1116finish: 1117 /* Kick-start more transmit */ 1118 urtwn_start(sc); 1119} 1120 1121static struct urtwn_data * 1122_urtwn_getbuf(struct urtwn_softc *sc) 1123{ 1124 struct urtwn_data *bf; 1125 1126 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1127 if (bf != NULL) 1128 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1129 else 1130 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 1131 return (bf); 1132} 1133 1134static struct urtwn_data * 1135urtwn_getbuf(struct urtwn_softc *sc) 1136{ 1137 struct urtwn_data *bf; 1138 1139 URTWN_ASSERT_LOCKED(sc); 1140 1141 bf = _urtwn_getbuf(sc); 1142 if (bf == NULL) 1143 DPRINTF("%s: stop queue\n", __func__); 1144 return (bf); 1145} 1146 1147static usb_error_t 1148urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1149 int len) 1150{ 1151 usb_device_request_t req; 1152 1153 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1154 req.bRequest = R92C_REQ_REGS; 1155 USETW(req.wValue, addr); 1156 USETW(req.wIndex, 0); 1157 USETW(req.wLength, len); 1158 return (urtwn_do_request(sc, &req, buf)); 1159} 1160 1161static usb_error_t 1162urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1163{ 1164 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1165} 1166 1167static usb_error_t 1168urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1169{ 1170 val = htole16(val); 1171 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1172} 1173 1174static usb_error_t 1175urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1176{ 1177 val = htole32(val); 1178 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1179} 1180 1181static usb_error_t 1182urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1183 int len) 1184{ 1185 usb_device_request_t req; 1186 1187 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1188 req.bRequest = R92C_REQ_REGS; 1189 USETW(req.wValue, addr); 1190 USETW(req.wIndex, 0); 1191 USETW(req.wLength, len); 1192 return (urtwn_do_request(sc, &req, buf)); 1193} 1194 1195static uint8_t 1196urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1197{ 1198 uint8_t val; 1199 1200 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1201 return (0xff); 1202 return (val); 1203} 1204 1205static uint16_t 1206urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1207{ 1208 uint16_t val; 1209 1210 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1211 return (0xffff); 1212 return (le16toh(val)); 1213} 1214 1215static uint32_t 1216urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1217{ 1218 uint32_t val; 1219 1220 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1221 return (0xffffffff); 1222 return (le32toh(val)); 1223} 1224 1225static int 1226urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1227{ 1228 struct r92c_fw_cmd cmd; 1229 usb_error_t error; 1230 int ntries; 1231 1232 /* Wait for current FW box to be empty. */ 1233 for (ntries = 0; ntries < 100; ntries++) { 1234 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1235 break; 1236 urtwn_ms_delay(sc); 1237 } 1238 if (ntries == 100) { 1239 device_printf(sc->sc_dev, 1240 "could not send firmware command\n"); 1241 return (ETIMEDOUT); 1242 } 1243 memset(&cmd, 0, sizeof(cmd)); 1244 cmd.id = id; 1245 if (len > 3) 1246 cmd.id |= R92C_CMD_FLAG_EXT; 1247 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1248 memcpy(cmd.msg, buf, len); 1249 1250 /* Write the first word last since that will trigger the FW. */ 1251 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1252 (uint8_t *)&cmd + 4, 2); 1253 if (error != USB_ERR_NORMAL_COMPLETION) 1254 return (EIO); 1255 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1256 (uint8_t *)&cmd + 0, 4); 1257 if (error != USB_ERR_NORMAL_COMPLETION) 1258 return (EIO); 1259 1260 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1261 return (0); 1262} 1263 1264static __inline void 1265urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1266{ 1267 1268 sc->sc_rf_write(sc, chain, addr, val); 1269} 1270 1271static void 1272urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1273 uint32_t val) 1274{ 1275 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1276 SM(R92C_LSSI_PARAM_ADDR, addr) | 1277 SM(R92C_LSSI_PARAM_DATA, val)); 1278} 1279 1280static void 1281urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1282uint32_t val) 1283{ 1284 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1285 SM(R88E_LSSI_PARAM_ADDR, addr) | 1286 SM(R92C_LSSI_PARAM_DATA, val)); 1287} 1288 1289static uint32_t 1290urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1291{ 1292 uint32_t reg[R92C_MAX_CHAINS], val; 1293 1294 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1295 if (chain != 0) 1296 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1297 1298 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1299 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1300 urtwn_ms_delay(sc); 1301 1302 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1303 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1304 R92C_HSSI_PARAM2_READ_EDGE); 1305 urtwn_ms_delay(sc); 1306 1307 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1308 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1309 urtwn_ms_delay(sc); 1310 1311 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1312 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1313 else 1314 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1315 return (MS(val, R92C_LSSI_READBACK_DATA)); 1316} 1317 1318static int 1319urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1320{ 1321 usb_error_t error; 1322 int ntries; 1323 1324 error = urtwn_write_4(sc, R92C_LLT_INIT, 1325 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1326 SM(R92C_LLT_INIT_ADDR, addr) | 1327 SM(R92C_LLT_INIT_DATA, data)); 1328 if (error != USB_ERR_NORMAL_COMPLETION) 1329 return (EIO); 1330 /* Wait for write operation to complete. */ 1331 for (ntries = 0; ntries < 20; ntries++) { 1332 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1333 R92C_LLT_INIT_OP_NO_ACTIVE) 1334 return (0); 1335 urtwn_ms_delay(sc); 1336 } 1337 return (ETIMEDOUT); 1338} 1339 1340static int 1341urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1342{ 1343 uint32_t reg; 1344 usb_error_t error; 1345 int ntries; 1346 1347 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1348 return (EFAULT); 1349 1350 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1351 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1352 reg &= ~R92C_EFUSE_CTRL_VALID; 1353 1354 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1355 if (error != USB_ERR_NORMAL_COMPLETION) 1356 return (EIO); 1357 /* Wait for read operation to complete. */ 1358 for (ntries = 0; ntries < 100; ntries++) { 1359 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1360 if (reg & R92C_EFUSE_CTRL_VALID) 1361 break; 1362 urtwn_ms_delay(sc); 1363 } 1364 if (ntries == 100) { 1365 device_printf(sc->sc_dev, 1366 "could not read efuse byte at address 0x%x\n", 1367 sc->last_rom_addr); 1368 return (ETIMEDOUT); 1369 } 1370 1371 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1372 sc->last_rom_addr++; 1373 1374 return (0); 1375} 1376 1377static int 1378urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1379 uint8_t msk) 1380{ 1381 uint8_t reg; 1382 int i, error; 1383 1384 for (i = 0; i < 4; i++) { 1385 if (msk & (1 << i)) 1386 continue; 1387 error = urtwn_efuse_read_next(sc, ®); 1388 if (error != 0) 1389 return (error); 1390 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2, reg); 1391 rom[off * 8 + i * 2 + 0] = reg; 1392 1393 error = urtwn_efuse_read_next(sc, ®); 1394 if (error != 0) 1395 return (error); 1396 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2 + 1, reg); 1397 rom[off * 8 + i * 2 + 1] = reg; 1398 } 1399 1400 return (0); 1401} 1402 1403#ifdef URTWN_DEBUG 1404static void 1405urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1406{ 1407 int i; 1408 1409 /* Dump ROM contents. */ 1410 device_printf(sc->sc_dev, "%s:", __func__); 1411 for (i = 0; i < size; i++) { 1412 if (i % 32 == 0) 1413 printf("\n%03X: ", i); 1414 else if (i % 4 == 0) 1415 printf(" "); 1416 1417 printf("%02X", rom[i]); 1418 } 1419 printf("\n"); 1420} 1421#endif 1422 1423static int 1424urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1425{ 1426#define URTWN_CHK(res) do { \ 1427 if ((error = res) != 0) \ 1428 goto end; \ 1429} while(0) 1430 uint8_t msk, off, reg; 1431 int error; 1432 1433 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1434 1435 /* Read full ROM image. */ 1436 sc->last_rom_addr = 0; 1437 memset(rom, 0xff, size); 1438 1439 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1440 while (reg != 0xff) { 1441 /* check for extended header */ 1442 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1443 off = reg >> 5; 1444 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1445 1446 if ((reg & 0x0f) != 0x0f) 1447 off = ((reg & 0xf0) >> 1) | off; 1448 else 1449 continue; 1450 } else 1451 off = reg >> 4; 1452 msk = reg & 0xf; 1453 1454 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1455 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1456 } 1457 1458end: 1459 1460#ifdef URTWN_DEBUG 1461 if (urtwn_debug >= 2) 1462 urtwn_dump_rom_contents(sc, rom, size); 1463#endif 1464 1465 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1466 1467 if (error != 0) { 1468 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1469 __func__); 1470 } 1471 1472 return (error); 1473#undef URTWN_CHK 1474} 1475 1476static int 1477urtwn_efuse_switch_power(struct urtwn_softc *sc) 1478{ 1479 usb_error_t error; 1480 uint32_t reg; 1481 1482 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1483 if (error != USB_ERR_NORMAL_COMPLETION) 1484 return (EIO); 1485 1486 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1487 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1488 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1489 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1490 if (error != USB_ERR_NORMAL_COMPLETION) 1491 return (EIO); 1492 } 1493 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1494 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1495 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1496 reg | R92C_SYS_FUNC_EN_ELDR); 1497 if (error != USB_ERR_NORMAL_COMPLETION) 1498 return (EIO); 1499 } 1500 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1501 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1502 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1503 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1504 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1505 if (error != USB_ERR_NORMAL_COMPLETION) 1506 return (EIO); 1507 } 1508 1509 return (0); 1510} 1511 1512static int 1513urtwn_read_chipid(struct urtwn_softc *sc) 1514{ 1515 uint32_t reg; 1516 1517 if (sc->chip & URTWN_CHIP_88E) 1518 return (0); 1519 1520 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1521 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1522 return (EIO); 1523 1524 if (reg & R92C_SYS_CFG_TYPE_92C) { 1525 sc->chip |= URTWN_CHIP_92C; 1526 /* Check if it is a castrated 8192C. */ 1527 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1528 R92C_HPON_FSM_CHIP_BONDING_ID) == 1529 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1530 sc->chip |= URTWN_CHIP_92C_1T2R; 1531 } 1532 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1533 sc->chip |= URTWN_CHIP_UMC; 1534 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1535 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1536 } 1537 return (0); 1538} 1539 1540static int 1541urtwn_read_rom(struct urtwn_softc *sc) 1542{ 1543 struct r92c_rom *rom = &sc->rom.r92c_rom; 1544 int error; 1545 1546 /* Read full ROM image. */ 1547 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1548 if (error != 0) 1549 return (error); 1550 1551 /* XXX Weird but this is what the vendor driver does. */ 1552 sc->last_rom_addr = 0x1fa; 1553 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1554 if (error != 0) 1555 return (error); 1556 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1557 1558 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1559 1560 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1561 DPRINTF("regulatory type=%d\n", sc->regulatory); 1562 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1563 1564 sc->sc_rf_write = urtwn_r92c_rf_write; 1565 sc->sc_power_on = urtwn_r92c_power_on; 1566 1567 return (0); 1568} 1569 1570static int 1571urtwn_r88e_read_rom(struct urtwn_softc *sc) 1572{ 1573 uint8_t *rom = sc->rom.r88e_rom; 1574 uint16_t addr; 1575 int error, i; 1576 1577 error = urtwn_efuse_read(sc, rom, sizeof(sc->rom.r88e_rom)); 1578 if (error != 0) 1579 return (error); 1580 1581 addr = 0x10; 1582 for (i = 0; i < 6; i++) 1583 sc->cck_tx_pwr[i] = rom[addr++]; 1584 for (i = 0; i < 5; i++) 1585 sc->ht40_tx_pwr[i] = rom[addr++]; 1586 sc->bw20_tx_pwr_diff = (rom[addr] & 0xf0) >> 4; 1587 if (sc->bw20_tx_pwr_diff & 0x08) 1588 sc->bw20_tx_pwr_diff |= 0xf0; 1589 sc->ofdm_tx_pwr_diff = (rom[addr] & 0xf); 1590 if (sc->ofdm_tx_pwr_diff & 0x08) 1591 sc->ofdm_tx_pwr_diff |= 0xf0; 1592 sc->regulatory = MS(rom[0xc1], R92C_ROM_RF1_REGULATORY); 1593 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &rom[0xd7]); 1594 1595 sc->sc_rf_write = urtwn_r88e_rf_write; 1596 sc->sc_power_on = urtwn_r88e_power_on; 1597 1598 return (0); 1599} 1600 1601/* 1602 * Initialize rate adaptation in firmware. 1603 */ 1604static int 1605urtwn_ra_init(struct urtwn_softc *sc) 1606{ 1607 struct ieee80211com *ic = &sc->sc_ic; 1608 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1609 struct ieee80211_node *ni; 1610 struct ieee80211_rateset *rs; 1611 struct r92c_fw_cmd_macid_cfg cmd; 1612 uint32_t rates, basicrates; 1613 uint8_t mode; 1614 int maxrate, maxbasicrate, error, i, j; 1615 1616 ni = ieee80211_ref_node(vap->iv_bss); 1617 rs = &ni->ni_rates; 1618 1619 /* Get normal and basic rates mask. */ 1620 rates = basicrates = 0; 1621 maxrate = maxbasicrate = 0; 1622 for (i = 0; i < rs->rs_nrates; i++) { 1623 /* Convert 802.11 rate to HW rate index. */ 1624 for (j = 0; j < nitems(ridx2rate); j++) 1625 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1626 ridx2rate[j]) 1627 break; 1628 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1629 continue; 1630 rates |= 1 << j; 1631 if (j > maxrate) 1632 maxrate = j; 1633 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1634 basicrates |= 1 << j; 1635 if (j > maxbasicrate) 1636 maxbasicrate = j; 1637 } 1638 } 1639 if (ic->ic_curmode == IEEE80211_MODE_11B) 1640 mode = R92C_RAID_11B; 1641 else 1642 mode = R92C_RAID_11BG; 1643 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1644 mode, rates, basicrates); 1645 1646 /* Set rates mask for group addressed frames. */ 1647 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1648 cmd.mask = htole32(mode << 28 | basicrates); 1649 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1650 if (error != 0) { 1651 ieee80211_free_node(ni); 1652 device_printf(sc->sc_dev, 1653 "could not add broadcast station\n"); 1654 return (error); 1655 } 1656 /* Set initial MRR rate. */ 1657 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1658 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1659 maxbasicrate); 1660 1661 /* Set rates mask for unicast frames. */ 1662 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1663 cmd.mask = htole32(mode << 28 | rates); 1664 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1665 if (error != 0) { 1666 ieee80211_free_node(ni); 1667 device_printf(sc->sc_dev, "could not add BSS station\n"); 1668 return (error); 1669 } 1670 /* Set initial MRR rate. */ 1671 DPRINTF("maxrate=%d\n", maxrate); 1672 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1673 maxrate); 1674 1675 /* Indicate highest supported rate. */ 1676 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1677 ieee80211_free_node(ni); 1678 1679 return (0); 1680} 1681 1682static void 1683urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1684{ 1685 struct r92c_tx_desc *txd = &uvp->bcn_desc; 1686 1687 txd->txdw0 = htole32( 1688 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 1689 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1690 txd->txdw1 = htole32( 1691 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 1692 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1693 1694 if (sc->chip & URTWN_CHIP_88E) { 1695 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 1696 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 1697 } else { 1698 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 1699 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 1700 } 1701 1702 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 1703 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 1704} 1705 1706static int 1707urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 1708{ 1709 struct ieee80211vap *vap = ni->ni_vap; 1710 struct urtwn_vap *uvp = URTWN_VAP(vap); 1711 struct mbuf *m; 1712 int error; 1713 1714 URTWN_ASSERT_LOCKED(sc); 1715 1716 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 1717 return (EINVAL); 1718 1719 m = ieee80211_beacon_alloc(ni); 1720 if (m == NULL) { 1721 device_printf(sc->sc_dev, 1722 "%s: could not allocate beacon frame\n", __func__); 1723 return (ENOMEM); 1724 } 1725 1726 if (uvp->bcn_mbuf != NULL) 1727 m_freem(uvp->bcn_mbuf); 1728 1729 uvp->bcn_mbuf = m; 1730 1731 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1732 return (error); 1733 1734 /* XXX bcnq stuck workaround */ 1735 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1736 return (error); 1737 1738 return (0); 1739} 1740 1741static void 1742urtwn_update_beacon(struct ieee80211vap *vap, int item) 1743{ 1744 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1745 struct urtwn_vap *uvp = URTWN_VAP(vap); 1746 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 1747 struct ieee80211_node *ni = vap->iv_bss; 1748 int mcast = 0; 1749 1750 URTWN_LOCK(sc); 1751 if (uvp->bcn_mbuf == NULL) { 1752 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 1753 if (uvp->bcn_mbuf == NULL) { 1754 device_printf(sc->sc_dev, 1755 "%s: could not allocate beacon frame\n", __func__); 1756 URTWN_UNLOCK(sc); 1757 return; 1758 } 1759 } 1760 URTWN_UNLOCK(sc); 1761 1762 if (item == IEEE80211_BEACON_TIM) 1763 mcast = 1; /* XXX */ 1764 1765 setbit(bo->bo_flags, item); 1766 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 1767 1768 URTWN_LOCK(sc); 1769 urtwn_tx_beacon(sc, uvp); 1770 URTWN_UNLOCK(sc); 1771} 1772 1773/* 1774 * Push a beacon frame into the chip. Beacon will 1775 * be repeated by the chip every R92C_BCN_INTERVAL. 1776 */ 1777static int 1778urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1779{ 1780 struct r92c_tx_desc *desc = &uvp->bcn_desc; 1781 struct urtwn_data *bf; 1782 1783 URTWN_ASSERT_LOCKED(sc); 1784 1785 bf = urtwn_getbuf(sc); 1786 if (bf == NULL) 1787 return (ENOMEM); 1788 1789 memcpy(bf->buf, desc, sizeof(*desc)); 1790 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 1791 1792 sc->sc_txtimer = 5; 1793 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1794 1795 return (0); 1796} 1797 1798static void 1799urtwn_tsf_task_adhoc(void *arg, int pending) 1800{ 1801 struct ieee80211vap *vap = arg; 1802 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1803 struct ieee80211_node *ni; 1804 uint32_t reg; 1805 1806 URTWN_LOCK(sc); 1807 ni = ieee80211_ref_node(vap->iv_bss); 1808 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 1809 1810 /* Accept beacons with the same BSSID. */ 1811 urtwn_set_rx_bssid_all(sc, 0); 1812 1813 /* Enable synchronization. */ 1814 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 1815 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1816 1817 /* Synchronize. */ 1818 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 1819 1820 /* Disable synchronization. */ 1821 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 1822 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1823 1824 /* Remove beacon filter. */ 1825 urtwn_set_rx_bssid_all(sc, 1); 1826 1827 /* Enable beaconing. */ 1828 urtwn_write_1(sc, R92C_MBID_NUM, 1829 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 1830 reg |= R92C_BCN_CTRL_EN_BCN; 1831 1832 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1833 ieee80211_free_node(ni); 1834 URTWN_UNLOCK(sc); 1835} 1836 1837static void 1838urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 1839{ 1840 struct ieee80211com *ic = &sc->sc_ic; 1841 struct urtwn_vap *uvp = URTWN_VAP(vap); 1842 1843 /* Reset TSF. */ 1844 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 1845 1846 switch (vap->iv_opmode) { 1847 case IEEE80211_M_STA: 1848 /* Enable TSF synchronization. */ 1849 urtwn_write_1(sc, R92C_BCN_CTRL, 1850 urtwn_read_1(sc, R92C_BCN_CTRL) & 1851 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1852 break; 1853 case IEEE80211_M_IBSS: 1854 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 1855 break; 1856 case IEEE80211_M_HOSTAP: 1857 /* Enable beaconing. */ 1858 urtwn_write_1(sc, R92C_MBID_NUM, 1859 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 1860 urtwn_write_1(sc, R92C_BCN_CTRL, 1861 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1862 break; 1863 default: 1864 device_printf(sc->sc_dev, "undefined opmode %d\n", 1865 vap->iv_opmode); 1866 return; 1867 } 1868} 1869 1870static void 1871urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1872{ 1873 uint8_t reg; 1874 1875 if (led == URTWN_LED_LINK) { 1876 if (sc->chip & URTWN_CHIP_88E) { 1877 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1878 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1879 if (!on) { 1880 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1881 urtwn_write_1(sc, R92C_LEDCFG2, 1882 reg | R92C_LEDCFG0_DIS); 1883 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1884 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1885 0xfe); 1886 } 1887 } else { 1888 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1889 if (!on) 1890 reg |= R92C_LEDCFG0_DIS; 1891 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1892 } 1893 sc->ledlink = on; /* Save LED state. */ 1894 } 1895} 1896 1897static void 1898urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 1899{ 1900 uint8_t reg; 1901 1902 reg = urtwn_read_1(sc, R92C_MSR); 1903 reg = (reg & ~R92C_MSR_MASK) | mode; 1904 urtwn_write_1(sc, R92C_MSR, reg); 1905} 1906 1907static void 1908urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 1909 const struct ieee80211_rx_stats *rxs, 1910 int rssi, int nf) 1911{ 1912 struct ieee80211vap *vap = ni->ni_vap; 1913 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1914 struct urtwn_vap *uvp = URTWN_VAP(vap); 1915 uint64_t ni_tstamp, curr_tstamp; 1916 1917 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 1918 1919 if (vap->iv_state == IEEE80211_S_RUN && 1920 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 1921 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 1922 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 1923#ifdef D3831 1924 URTWN_LOCK(sc); 1925 urtwn_get_tsf(sc, &curr_tstamp); 1926 URTWN_UNLOCK(sc); 1927 curr_tstamp = le64toh(curr_tstamp); 1928 1929 if (ni_tstamp >= curr_tstamp) 1930 (void) ieee80211_ibss_merge(ni); 1931#else 1932 (void) sc; 1933 (void) curr_tstamp; 1934#endif 1935 } 1936} 1937 1938static int 1939urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1940{ 1941 struct urtwn_vap *uvp = URTWN_VAP(vap); 1942 struct ieee80211com *ic = vap->iv_ic; 1943 struct urtwn_softc *sc = ic->ic_softc; 1944 struct ieee80211_node *ni; 1945 enum ieee80211_state ostate; 1946 uint32_t reg; 1947 uint8_t mode; 1948 int error = 0; 1949 1950 ostate = vap->iv_state; 1951 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1952 ieee80211_state_name[nstate]); 1953 1954 IEEE80211_UNLOCK(ic); 1955 URTWN_LOCK(sc); 1956 callout_stop(&sc->sc_watchdog_ch); 1957 1958 if (ostate == IEEE80211_S_RUN) { 1959 /* Turn link LED off. */ 1960 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1961 1962 /* Set media status to 'No Link'. */ 1963 urtwn_set_mode(sc, R92C_MSR_NOLINK); 1964 1965 /* Stop Rx of data frames. */ 1966 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1967 1968 /* Disable TSF synchronization. */ 1969 urtwn_write_1(sc, R92C_BCN_CTRL, 1970 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 1971 R92C_BCN_CTRL_DIS_TSF_UDT0); 1972 1973 /* Disable beaconing. */ 1974 urtwn_write_1(sc, R92C_MBID_NUM, 1975 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 1976 1977 /* Reset TSF. */ 1978 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 1979 1980 /* Reset EDCA parameters. */ 1981 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1982 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1983 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1984 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1985 } 1986 1987 switch (nstate) { 1988 case IEEE80211_S_INIT: 1989 /* Turn link LED off. */ 1990 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1991 break; 1992 case IEEE80211_S_SCAN: 1993 /* Pause AC Tx queues. */ 1994 urtwn_write_1(sc, R92C_TXPAUSE, 1995 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1996 break; 1997 case IEEE80211_S_AUTH: 1998 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1999 break; 2000 case IEEE80211_S_RUN: 2001 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2002 /* Turn link LED on. */ 2003 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2004 break; 2005 } 2006 2007 ni = ieee80211_ref_node(vap->iv_bss); 2008 2009 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 2010 ni->ni_chan == IEEE80211_CHAN_ANYC) { 2011 device_printf(sc->sc_dev, 2012 "%s: could not move to RUN state\n", __func__); 2013 error = EINVAL; 2014 goto end_run; 2015 } 2016 2017 switch (vap->iv_opmode) { 2018 case IEEE80211_M_STA: 2019 mode = R92C_MSR_INFRA; 2020 break; 2021 case IEEE80211_M_IBSS: 2022 mode = R92C_MSR_ADHOC; 2023 break; 2024 case IEEE80211_M_HOSTAP: 2025 mode = R92C_MSR_AP; 2026 break; 2027 default: 2028 device_printf(sc->sc_dev, "undefined opmode %d\n", 2029 vap->iv_opmode); 2030 error = EINVAL; 2031 goto end_run; 2032 } 2033 2034 /* Set media status to 'Associated'. */ 2035 urtwn_set_mode(sc, mode); 2036 2037 /* Set BSSID. */ 2038 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2039 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2040 2041 if (ic->ic_curmode == IEEE80211_MODE_11B) 2042 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2043 else /* 802.11b/g */ 2044 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2045 2046 /* Enable Rx of data frames. */ 2047 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2048 2049 /* Flush all AC queues. */ 2050 urtwn_write_1(sc, R92C_TXPAUSE, 0); 2051 2052 /* Set beacon interval. */ 2053 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2054 2055 /* Allow Rx from our BSSID only. */ 2056 if (ic->ic_promisc == 0) { 2057 reg = urtwn_read_4(sc, R92C_RCR); 2058 2059 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 2060 reg |= R92C_RCR_CBSSID_DATA; 2061 if (vap->iv_opmode != IEEE80211_M_IBSS) 2062 reg |= R92C_RCR_CBSSID_BCN; 2063 2064 urtwn_write_4(sc, R92C_RCR, reg); 2065 } 2066 2067 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 2068 vap->iv_opmode == IEEE80211_M_IBSS) { 2069 error = urtwn_setup_beacon(sc, ni); 2070 if (error != 0) { 2071 device_printf(sc->sc_dev, 2072 "unable to push beacon into the chip, " 2073 "error %d\n", error); 2074 goto end_run; 2075 } 2076 } 2077 2078 /* Enable TSF synchronization. */ 2079 urtwn_tsf_sync_enable(sc, vap); 2080 2081 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2082 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2083 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2084 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2085 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2086 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2087 2088 /* Intialize rate adaptation. */ 2089 if (!(sc->chip & URTWN_CHIP_88E)) 2090 urtwn_ra_init(sc); 2091 /* Turn link LED on. */ 2092 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2093 2094 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2095 /* Reset temperature calibration state machine. */ 2096 sc->thcal_state = 0; 2097 sc->thcal_lctemp = 0; 2098 2099end_run: 2100 ieee80211_free_node(ni); 2101 break; 2102 default: 2103 break; 2104 } 2105 2106 URTWN_UNLOCK(sc); 2107 IEEE80211_LOCK(ic); 2108 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2109} 2110 2111static void 2112urtwn_watchdog(void *arg) 2113{ 2114 struct urtwn_softc *sc = arg; 2115 2116 if (sc->sc_txtimer > 0) { 2117 if (--sc->sc_txtimer == 0) { 2118 device_printf(sc->sc_dev, "device timeout\n"); 2119 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2120 return; 2121 } 2122 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2123 } 2124} 2125 2126static void 2127urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2128{ 2129 int pwdb; 2130 2131 /* Convert antenna signal to percentage. */ 2132 if (rssi <= -100 || rssi >= 20) 2133 pwdb = 0; 2134 else if (rssi >= 0) 2135 pwdb = 100; 2136 else 2137 pwdb = 100 + rssi; 2138 if (!(sc->chip & URTWN_CHIP_88E)) { 2139 if (rate <= URTWN_RIDX_CCK11) { 2140 /* CCK gain is smaller than OFDM/MCS gain. */ 2141 pwdb += 6; 2142 if (pwdb > 100) 2143 pwdb = 100; 2144 if (pwdb <= 14) 2145 pwdb -= 4; 2146 else if (pwdb <= 26) 2147 pwdb -= 8; 2148 else if (pwdb <= 34) 2149 pwdb -= 6; 2150 else if (pwdb <= 42) 2151 pwdb -= 2; 2152 } 2153 } 2154 if (sc->avg_pwdb == -1) /* Init. */ 2155 sc->avg_pwdb = pwdb; 2156 else if (sc->avg_pwdb < pwdb) 2157 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2158 else 2159 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2160 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 2161} 2162 2163static int8_t 2164urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2165{ 2166 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2167 struct r92c_rx_phystat *phy; 2168 struct r92c_rx_cck *cck; 2169 uint8_t rpt; 2170 int8_t rssi; 2171 2172 if (rate <= URTWN_RIDX_CCK11) { 2173 cck = (struct r92c_rx_cck *)physt; 2174 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2175 rpt = (cck->agc_rpt >> 5) & 0x3; 2176 rssi = (cck->agc_rpt & 0x1f) << 1; 2177 } else { 2178 rpt = (cck->agc_rpt >> 6) & 0x3; 2179 rssi = cck->agc_rpt & 0x3e; 2180 } 2181 rssi = cckoff[rpt] - rssi; 2182 } else { /* OFDM/HT. */ 2183 phy = (struct r92c_rx_phystat *)physt; 2184 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2185 } 2186 return (rssi); 2187} 2188 2189static int8_t 2190urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2191{ 2192 struct r92c_rx_phystat *phy; 2193 struct r88e_rx_cck *cck; 2194 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2195 int8_t rssi; 2196 2197 rssi = 0; 2198 if (rate <= URTWN_RIDX_CCK11) { 2199 cck = (struct r88e_rx_cck *)physt; 2200 cck_agc_rpt = cck->agc_rpt; 2201 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2202 vga_idx = cck_agc_rpt & 0x1f; 2203 switch (lna_idx) { 2204 case 7: 2205 if (vga_idx <= 27) 2206 rssi = -100 + 2* (27 - vga_idx); 2207 else 2208 rssi = -100; 2209 break; 2210 case 6: 2211 rssi = -48 + 2 * (2 - vga_idx); 2212 break; 2213 case 5: 2214 rssi = -42 + 2 * (7 - vga_idx); 2215 break; 2216 case 4: 2217 rssi = -36 + 2 * (7 - vga_idx); 2218 break; 2219 case 3: 2220 rssi = -24 + 2 * (7 - vga_idx); 2221 break; 2222 case 2: 2223 rssi = -12 + 2 * (5 - vga_idx); 2224 break; 2225 case 1: 2226 rssi = 8 - (2 * vga_idx); 2227 break; 2228 case 0: 2229 rssi = 14 - (2 * vga_idx); 2230 break; 2231 } 2232 rssi += 6; 2233 } else { /* OFDM/HT. */ 2234 phy = (struct r92c_rx_phystat *)physt; 2235 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2236 } 2237 return (rssi); 2238} 2239 2240static __inline uint8_t 2241rate2ridx(uint8_t rate) 2242{ 2243 switch (rate) { 2244 case 12: return 4; 2245 case 18: return 5; 2246 case 24: return 6; 2247 case 36: return 7; 2248 case 48: return 8; 2249 case 72: return 9; 2250 case 96: return 10; 2251 case 108: return 11; 2252 case 2: return 0; 2253 case 4: return 1; 2254 case 11: return 2; 2255 case 22: return 3; 2256 default: return 0; 2257 } 2258} 2259 2260static int 2261urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2262 struct mbuf *m, struct urtwn_data *data) 2263{ 2264 const struct ieee80211_txparam *tp; 2265 struct ieee80211com *ic = &sc->sc_ic; 2266 struct ieee80211vap *vap = ni->ni_vap; 2267 struct ieee80211_key *k = NULL; 2268 struct ieee80211_channel *chan; 2269 struct ieee80211_frame *wh; 2270 struct r92c_tx_desc *txd; 2271 uint8_t macid, raid, rate, ridx, subtype, type, tid, qsel; 2272 int hasqos, ismcast; 2273 2274 URTWN_ASSERT_LOCKED(sc); 2275 2276 /* 2277 * Software crypto. 2278 */ 2279 wh = mtod(m, struct ieee80211_frame *); 2280 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2281 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2282 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2283 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2284 2285 /* Select TX ring for this frame. */ 2286 if (hasqos) { 2287 tid = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2288 tid &= IEEE80211_QOS_TID; 2289 } else 2290 tid = 0; 2291 2292 chan = (ni->ni_chan != IEEE80211_CHAN_ANYC) ? 2293 ni->ni_chan : ic->ic_curchan; 2294 tp = &vap->iv_txparms[ieee80211_chan2mode(chan)]; 2295 2296 /* Choose a TX rate index. */ 2297 if (type == IEEE80211_FC0_TYPE_MGT) 2298 rate = tp->mgmtrate; 2299 else if (ismcast) 2300 rate = tp->mcastrate; 2301 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 2302 rate = tp->ucastrate; 2303 else if (m->m_flags & M_EAPOL) 2304 rate = tp->mgmtrate; 2305 else { 2306 if (URTWN_CHIP_HAS_RATECTL(sc)) { 2307 /* XXX pass pktlen */ 2308 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2309 rate = ni->ni_txrate; 2310 } else { 2311 if (ic->ic_curmode != IEEE80211_MODE_11B) 2312 rate = 108; 2313 else 2314 rate = 22; 2315 } 2316 } 2317 2318 ridx = rate2ridx(rate); 2319 if (ic->ic_curmode != IEEE80211_MODE_11B) 2320 raid = R92C_RAID_11BG; 2321 else 2322 raid = R92C_RAID_11B; 2323 2324 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2325 k = ieee80211_crypto_encap(ni, m); 2326 if (k == NULL) { 2327 device_printf(sc->sc_dev, 2328 "ieee80211_crypto_encap returns NULL.\n"); 2329 return (ENOBUFS); 2330 } 2331 2332 /* in case packet header moved, reset pointer */ 2333 wh = mtod(m, struct ieee80211_frame *); 2334 } 2335 2336 /* Fill Tx descriptor. */ 2337 txd = (struct r92c_tx_desc *)data->buf; 2338 memset(txd, 0, sizeof(*txd)); 2339 2340 txd->txdw0 |= htole32( 2341 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2342 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2343 if (ismcast) 2344 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2345 2346 if (!ismcast) { 2347 if (sc->chip & URTWN_CHIP_88E) { 2348 struct urtwn_node *un = URTWN_NODE(ni); 2349 macid = un->id; 2350 } else 2351 macid = URTWN_MACID_BSS; 2352 2353 if (type == IEEE80211_FC0_TYPE_DATA) { 2354 qsel = tid % URTWN_MAX_TID; 2355 2356 if (sc->chip & URTWN_CHIP_88E) { 2357 txd->txdw2 |= htole32( 2358 R88E_TXDW2_AGGBK | 2359 R88E_TXDW2_CCX_RPT); 2360 } else 2361 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2362 2363 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2364 switch (ic->ic_protmode) { 2365 case IEEE80211_PROT_CTSONLY: 2366 txd->txdw4 |= htole32( 2367 R92C_TXDW4_CTS2SELF | 2368 R92C_TXDW4_HWRTSEN); 2369 break; 2370 case IEEE80211_PROT_RTSCTS: 2371 txd->txdw4 |= htole32( 2372 R92C_TXDW4_RTSEN | 2373 R92C_TXDW4_HWRTSEN); 2374 break; 2375 default: 2376 break; 2377 } 2378 } 2379 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2380 URTWN_RIDX_OFDM24)); 2381 txd->txdw5 |= htole32(0x0001ff00); 2382 } else /* IEEE80211_FC0_TYPE_MGT */ 2383 qsel = R92C_TXDW1_QSEL_MGNT; 2384 } else { 2385 macid = URTWN_MACID_BC; 2386 qsel = R92C_TXDW1_QSEL_MGNT; 2387 } 2388 2389 txd->txdw1 |= htole32( 2390 SM(R92C_TXDW1_QSEL, qsel) | 2391 SM(R92C_TXDW1_RAID, raid)); 2392 2393 if (sc->chip & URTWN_CHIP_88E) 2394 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 2395 else 2396 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 2397 2398 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2399 /* Force this rate if needed. */ 2400 if (URTWN_CHIP_HAS_RATECTL(sc) || ismcast || 2401 (m->m_flags & M_EAPOL) || type != IEEE80211_FC0_TYPE_DATA) 2402 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2403 2404 if (!hasqos) { 2405 /* Use HW sequence numbering for non-QoS frames. */ 2406 if (sc->chip & URTWN_CHIP_88E) 2407 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2408 else 2409 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2410 } else { 2411 /* Set sequence number. */ 2412 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2413 } 2414 2415 if (ieee80211_radiotap_active_vap(vap)) { 2416 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2417 2418 tap->wt_flags = 0; 2419 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2420 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2421 if (k != NULL) 2422 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2423 ieee80211_radiotap_tx(vap, m); 2424 } 2425 2426 data->ni = ni; 2427 2428 urtwn_tx_start(sc, m, type, data); 2429 2430 return (0); 2431} 2432 2433static void 2434urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 2435 struct urtwn_data *data) 2436{ 2437 struct usb_xfer *xfer; 2438 struct r92c_tx_desc *txd; 2439 uint16_t ac, sum; 2440 int i, xferlen; 2441 2442 URTWN_ASSERT_LOCKED(sc); 2443 2444 ac = M_WME_GETAC(m); 2445 2446 switch (type) { 2447 case IEEE80211_FC0_TYPE_CTL: 2448 case IEEE80211_FC0_TYPE_MGT: 2449 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 2450 break; 2451 default: 2452 xfer = sc->sc_xfer[wme2queue[ac].qid]; 2453 break; 2454 } 2455 2456 txd = (struct r92c_tx_desc *)data->buf; 2457 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 2458 2459 /* Compute Tx descriptor checksum. */ 2460 sum = 0; 2461 for (i = 0; i < sizeof(*txd) / 2; i++) 2462 sum ^= ((uint16_t *)txd)[i]; 2463 txd->txdsum = sum; /* NB: already little endian. */ 2464 2465 xferlen = sizeof(*txd) + m->m_pkthdr.len; 2466 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 2467 2468 data->buflen = xferlen; 2469 data->m = m; 2470 2471 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 2472 usbd_transfer_start(xfer); 2473} 2474 2475static int 2476urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 2477{ 2478 struct urtwn_softc *sc = ic->ic_softc; 2479 int error; 2480 2481 URTWN_LOCK(sc); 2482 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2483 URTWN_UNLOCK(sc); 2484 return (ENXIO); 2485 } 2486 error = mbufq_enqueue(&sc->sc_snd, m); 2487 if (error) { 2488 URTWN_UNLOCK(sc); 2489 return (error); 2490 } 2491 urtwn_start(sc); 2492 URTWN_UNLOCK(sc); 2493 2494 return (0); 2495} 2496 2497static void 2498urtwn_start(struct urtwn_softc *sc) 2499{ 2500 struct ieee80211_node *ni; 2501 struct mbuf *m; 2502 struct urtwn_data *bf; 2503 2504 URTWN_ASSERT_LOCKED(sc); 2505 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2506 bf = urtwn_getbuf(sc); 2507 if (bf == NULL) { 2508 mbufq_prepend(&sc->sc_snd, m); 2509 break; 2510 } 2511 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2512 m->m_pkthdr.rcvif = NULL; 2513 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 2514 if_inc_counter(ni->ni_vap->iv_ifp, 2515 IFCOUNTER_OERRORS, 1); 2516 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2517 m_freem(m); 2518 ieee80211_free_node(ni); 2519 break; 2520 } 2521 sc->sc_txtimer = 5; 2522 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2523 } 2524} 2525 2526static void 2527urtwn_parent(struct ieee80211com *ic) 2528{ 2529 struct urtwn_softc *sc = ic->ic_softc; 2530 2531 URTWN_LOCK(sc); 2532 if (sc->sc_flags & URTWN_DETACHED) { 2533 URTWN_UNLOCK(sc); 2534 return; 2535 } 2536 URTWN_UNLOCK(sc); 2537 2538 if (ic->ic_nrunning > 0) { 2539 if (urtwn_init(sc) != 0) { 2540 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2541 if (vap != NULL) 2542 ieee80211_stop(vap); 2543 } else 2544 ieee80211_start_all(ic); 2545 } else 2546 urtwn_stop(sc); 2547} 2548 2549static __inline int 2550urtwn_power_on(struct urtwn_softc *sc) 2551{ 2552 2553 return sc->sc_power_on(sc); 2554} 2555 2556static int 2557urtwn_r92c_power_on(struct urtwn_softc *sc) 2558{ 2559 uint32_t reg; 2560 usb_error_t error; 2561 int ntries; 2562 2563 /* Wait for autoload done bit. */ 2564 for (ntries = 0; ntries < 1000; ntries++) { 2565 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2566 break; 2567 urtwn_ms_delay(sc); 2568 } 2569 if (ntries == 1000) { 2570 device_printf(sc->sc_dev, 2571 "timeout waiting for chip autoload\n"); 2572 return (ETIMEDOUT); 2573 } 2574 2575 /* Unlock ISO/CLK/Power control register. */ 2576 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2577 if (error != USB_ERR_NORMAL_COMPLETION) 2578 return (EIO); 2579 /* Move SPS into PWM mode. */ 2580 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2581 if (error != USB_ERR_NORMAL_COMPLETION) 2582 return (EIO); 2583 urtwn_ms_delay(sc); 2584 2585 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2586 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2587 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2588 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2589 if (error != USB_ERR_NORMAL_COMPLETION) 2590 return (EIO); 2591 urtwn_ms_delay(sc); 2592 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2593 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2594 ~R92C_SYS_ISO_CTRL_MD2PP); 2595 if (error != USB_ERR_NORMAL_COMPLETION) 2596 return (EIO); 2597 } 2598 2599 /* Auto enable WLAN. */ 2600 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2601 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2602 if (error != USB_ERR_NORMAL_COMPLETION) 2603 return (EIO); 2604 for (ntries = 0; ntries < 1000; ntries++) { 2605 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2606 R92C_APS_FSMCO_APFM_ONMAC)) 2607 break; 2608 urtwn_ms_delay(sc); 2609 } 2610 if (ntries == 1000) { 2611 device_printf(sc->sc_dev, 2612 "timeout waiting for MAC auto ON\n"); 2613 return (ETIMEDOUT); 2614 } 2615 2616 /* Enable radio, GPIO and LED functions. */ 2617 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2618 R92C_APS_FSMCO_AFSM_HSUS | 2619 R92C_APS_FSMCO_PDN_EN | 2620 R92C_APS_FSMCO_PFM_ALDN); 2621 if (error != USB_ERR_NORMAL_COMPLETION) 2622 return (EIO); 2623 /* Release RF digital isolation. */ 2624 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2625 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2626 if (error != USB_ERR_NORMAL_COMPLETION) 2627 return (EIO); 2628 2629 /* Initialize MAC. */ 2630 error = urtwn_write_1(sc, R92C_APSD_CTRL, 2631 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2632 if (error != USB_ERR_NORMAL_COMPLETION) 2633 return (EIO); 2634 for (ntries = 0; ntries < 200; ntries++) { 2635 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2636 R92C_APSD_CTRL_OFF_STATUS)) 2637 break; 2638 urtwn_ms_delay(sc); 2639 } 2640 if (ntries == 200) { 2641 device_printf(sc->sc_dev, 2642 "timeout waiting for MAC initialization\n"); 2643 return (ETIMEDOUT); 2644 } 2645 2646 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2647 reg = urtwn_read_2(sc, R92C_CR); 2648 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2649 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2650 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2651 R92C_CR_ENSEC; 2652 error = urtwn_write_2(sc, R92C_CR, reg); 2653 if (error != USB_ERR_NORMAL_COMPLETION) 2654 return (EIO); 2655 2656 error = urtwn_write_1(sc, 0xfe10, 0x19); 2657 if (error != USB_ERR_NORMAL_COMPLETION) 2658 return (EIO); 2659 return (0); 2660} 2661 2662static int 2663urtwn_r88e_power_on(struct urtwn_softc *sc) 2664{ 2665 uint32_t reg; 2666 usb_error_t error; 2667 int ntries; 2668 2669 /* Wait for power ready bit. */ 2670 for (ntries = 0; ntries < 5000; ntries++) { 2671 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2672 break; 2673 urtwn_ms_delay(sc); 2674 } 2675 if (ntries == 5000) { 2676 device_printf(sc->sc_dev, 2677 "timeout waiting for chip power up\n"); 2678 return (ETIMEDOUT); 2679 } 2680 2681 /* Reset BB. */ 2682 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2683 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2684 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2685 if (error != USB_ERR_NORMAL_COMPLETION) 2686 return (EIO); 2687 2688 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2689 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2690 if (error != USB_ERR_NORMAL_COMPLETION) 2691 return (EIO); 2692 2693 /* Disable HWPDN. */ 2694 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2695 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2696 if (error != USB_ERR_NORMAL_COMPLETION) 2697 return (EIO); 2698 2699 /* Disable WL suspend. */ 2700 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2701 urtwn_read_2(sc, R92C_APS_FSMCO) & 2702 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2703 if (error != USB_ERR_NORMAL_COMPLETION) 2704 return (EIO); 2705 2706 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2707 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2708 if (error != USB_ERR_NORMAL_COMPLETION) 2709 return (EIO); 2710 for (ntries = 0; ntries < 5000; ntries++) { 2711 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2712 R92C_APS_FSMCO_APFM_ONMAC)) 2713 break; 2714 urtwn_ms_delay(sc); 2715 } 2716 if (ntries == 5000) 2717 return (ETIMEDOUT); 2718 2719 /* Enable LDO normal mode. */ 2720 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 2721 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2722 if (error != USB_ERR_NORMAL_COMPLETION) 2723 return (EIO); 2724 2725 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2726 error = urtwn_write_2(sc, R92C_CR, 0); 2727 if (error != USB_ERR_NORMAL_COMPLETION) 2728 return (EIO); 2729 reg = urtwn_read_2(sc, R92C_CR); 2730 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2731 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2732 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2733 error = urtwn_write_2(sc, R92C_CR, reg); 2734 if (error != USB_ERR_NORMAL_COMPLETION) 2735 return (EIO); 2736 2737 return (0); 2738} 2739 2740static int 2741urtwn_llt_init(struct urtwn_softc *sc) 2742{ 2743 int i, error, page_count, pktbuf_count; 2744 2745 page_count = (sc->chip & URTWN_CHIP_88E) ? 2746 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2747 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2748 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2749 2750 /* Reserve pages [0; page_count]. */ 2751 for (i = 0; i < page_count; i++) { 2752 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2753 return (error); 2754 } 2755 /* NB: 0xff indicates end-of-list. */ 2756 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2757 return (error); 2758 /* 2759 * Use pages [page_count + 1; pktbuf_count - 1] 2760 * as ring buffer. 2761 */ 2762 for (++i; i < pktbuf_count - 1; i++) { 2763 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2764 return (error); 2765 } 2766 /* Make the last page point to the beginning of the ring buffer. */ 2767 error = urtwn_llt_write(sc, i, page_count + 1); 2768 return (error); 2769} 2770 2771static void 2772urtwn_fw_reset(struct urtwn_softc *sc) 2773{ 2774 uint16_t reg; 2775 int ntries; 2776 2777 /* Tell 8051 to reset itself. */ 2778 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2779 2780 /* Wait until 8051 resets by itself. */ 2781 for (ntries = 0; ntries < 100; ntries++) { 2782 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2783 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2784 return; 2785 urtwn_ms_delay(sc); 2786 } 2787 /* Force 8051 reset. */ 2788 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2789} 2790 2791static void 2792urtwn_r88e_fw_reset(struct urtwn_softc *sc) 2793{ 2794 uint16_t reg; 2795 2796 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2797 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2798 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2799} 2800 2801static int 2802urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2803{ 2804 uint32_t reg; 2805 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 2806 int off, mlen; 2807 2808 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2809 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2810 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2811 2812 off = R92C_FW_START_ADDR; 2813 while (len > 0) { 2814 if (len > 196) 2815 mlen = 196; 2816 else if (len > 4) 2817 mlen = 4; 2818 else 2819 mlen = 1; 2820 /* XXX fix this deconst */ 2821 error = urtwn_write_region_1(sc, off, 2822 __DECONST(uint8_t *, buf), mlen); 2823 if (error != USB_ERR_NORMAL_COMPLETION) 2824 break; 2825 off += mlen; 2826 buf += mlen; 2827 len -= mlen; 2828 } 2829 return (error); 2830} 2831 2832static int 2833urtwn_load_firmware(struct urtwn_softc *sc) 2834{ 2835 const struct firmware *fw; 2836 const struct r92c_fw_hdr *hdr; 2837 const char *imagename; 2838 const u_char *ptr; 2839 size_t len; 2840 uint32_t reg; 2841 int mlen, ntries, page, error; 2842 2843 URTWN_UNLOCK(sc); 2844 /* Read firmware image from the filesystem. */ 2845 if (sc->chip & URTWN_CHIP_88E) 2846 imagename = "urtwn-rtl8188eufw"; 2847 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2848 URTWN_CHIP_UMC_A_CUT) 2849 imagename = "urtwn-rtl8192cfwU"; 2850 else 2851 imagename = "urtwn-rtl8192cfwT"; 2852 2853 fw = firmware_get(imagename); 2854 URTWN_LOCK(sc); 2855 if (fw == NULL) { 2856 device_printf(sc->sc_dev, 2857 "failed loadfirmware of file %s\n", imagename); 2858 return (ENOENT); 2859 } 2860 2861 len = fw->datasize; 2862 2863 if (len < sizeof(*hdr)) { 2864 device_printf(sc->sc_dev, "firmware too short\n"); 2865 error = EINVAL; 2866 goto fail; 2867 } 2868 ptr = fw->data; 2869 hdr = (const struct r92c_fw_hdr *)ptr; 2870 /* Check if there is a valid FW header and skip it. */ 2871 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2872 (le16toh(hdr->signature) >> 4) == 0x88e || 2873 (le16toh(hdr->signature) >> 4) == 0x92c) { 2874 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2875 le16toh(hdr->version), le16toh(hdr->subversion), 2876 hdr->month, hdr->date, hdr->hour, hdr->minute); 2877 ptr += sizeof(*hdr); 2878 len -= sizeof(*hdr); 2879 } 2880 2881 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2882 if (sc->chip & URTWN_CHIP_88E) 2883 urtwn_r88e_fw_reset(sc); 2884 else 2885 urtwn_fw_reset(sc); 2886 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2887 } 2888 2889 if (!(sc->chip & URTWN_CHIP_88E)) { 2890 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2891 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2892 R92C_SYS_FUNC_EN_CPUEN); 2893 } 2894 urtwn_write_1(sc, R92C_MCUFWDL, 2895 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2896 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2897 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2898 2899 /* Reset the FWDL checksum. */ 2900 urtwn_write_1(sc, R92C_MCUFWDL, 2901 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2902 2903 for (page = 0; len > 0; page++) { 2904 mlen = min(len, R92C_FW_PAGE_SIZE); 2905 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2906 if (error != 0) { 2907 device_printf(sc->sc_dev, 2908 "could not load firmware page\n"); 2909 goto fail; 2910 } 2911 ptr += mlen; 2912 len -= mlen; 2913 } 2914 urtwn_write_1(sc, R92C_MCUFWDL, 2915 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2916 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2917 2918 /* Wait for checksum report. */ 2919 for (ntries = 0; ntries < 1000; ntries++) { 2920 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2921 break; 2922 urtwn_ms_delay(sc); 2923 } 2924 if (ntries == 1000) { 2925 device_printf(sc->sc_dev, 2926 "timeout waiting for checksum report\n"); 2927 error = ETIMEDOUT; 2928 goto fail; 2929 } 2930 2931 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2932 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2933 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2934 if (sc->chip & URTWN_CHIP_88E) 2935 urtwn_r88e_fw_reset(sc); 2936 /* Wait for firmware readiness. */ 2937 for (ntries = 0; ntries < 1000; ntries++) { 2938 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2939 break; 2940 urtwn_ms_delay(sc); 2941 } 2942 if (ntries == 1000) { 2943 device_printf(sc->sc_dev, 2944 "timeout waiting for firmware readiness\n"); 2945 error = ETIMEDOUT; 2946 goto fail; 2947 } 2948fail: 2949 firmware_put(fw, FIRMWARE_UNLOAD); 2950 return (error); 2951} 2952 2953static int 2954urtwn_dma_init(struct urtwn_softc *sc) 2955{ 2956 struct usb_endpoint *ep, *ep_end; 2957 usb_error_t usb_err; 2958 uint32_t reg; 2959 int hashq, hasnq, haslq, nqueues, ntx; 2960 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 2961 2962 /* Initialize LLT table. */ 2963 error = urtwn_llt_init(sc); 2964 if (error != 0) 2965 return (error); 2966 2967 /* Determine the number of bulk-out pipes. */ 2968 ntx = 0; 2969 ep = sc->sc_udev->endpoints; 2970 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 2971 for (; ep != ep_end; ep++) { 2972 if ((ep->edesc == NULL) || 2973 (ep->iface_index != sc->sc_iface_index)) 2974 continue; 2975 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 2976 ntx++; 2977 } 2978 if (ntx == 0) { 2979 device_printf(sc->sc_dev, 2980 "%d: invalid number of Tx bulk pipes\n", ntx); 2981 return (EIO); 2982 } 2983 2984 /* Get Tx queues to USB endpoints mapping. */ 2985 hashq = hasnq = haslq = nqueues = 0; 2986 switch (ntx) { 2987 case 1: hashq = 1; break; 2988 case 2: hashq = hasnq = 1; break; 2989 case 3: case 4: hashq = hasnq = haslq = 1; break; 2990 } 2991 nqueues = hashq + hasnq + haslq; 2992 if (nqueues == 0) 2993 return (EIO); 2994 2995 npubqpages = nqpages = nrempages = pagecount = 0; 2996 if (sc->chip & URTWN_CHIP_88E) 2997 tx_boundary = R88E_TX_PAGE_BOUNDARY; 2998 else { 2999 pagecount = R92C_TX_PAGE_COUNT; 3000 npubqpages = R92C_PUBQ_NPAGES; 3001 tx_boundary = R92C_TX_PAGE_BOUNDARY; 3002 } 3003 3004 /* Set number of pages for normal priority queue. */ 3005 if (sc->chip & URTWN_CHIP_88E) { 3006 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 3007 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3008 return (EIO); 3009 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3010 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3011 return (EIO); 3012 } else { 3013 /* Get the number of pages for each queue. */ 3014 nqpages = (pagecount - npubqpages) / nqueues; 3015 /* 3016 * The remaining pages are assigned to the high priority 3017 * queue. 3018 */ 3019 nrempages = (pagecount - npubqpages) % nqueues; 3020 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3021 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3022 return (EIO); 3023 usb_err = urtwn_write_4(sc, R92C_RQPN, 3024 /* Set number of pages for public queue. */ 3025 SM(R92C_RQPN_PUBQ, npubqpages) | 3026 /* Set number of pages for high priority queue. */ 3027 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3028 /* Set number of pages for low priority queue. */ 3029 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3030 /* Load values. */ 3031 R92C_RQPN_LD); 3032 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3033 return (EIO); 3034 } 3035 3036 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 3037 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3038 return (EIO); 3039 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 3040 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3041 return (EIO); 3042 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 3043 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3044 return (EIO); 3045 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 3046 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3047 return (EIO); 3048 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 3049 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3050 return (EIO); 3051 3052 /* Set queue to USB pipe mapping. */ 3053 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3054 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3055 if (nqueues == 1) { 3056 if (hashq) 3057 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3058 else if (hasnq) 3059 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3060 else 3061 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3062 } else if (nqueues == 2) { 3063 /* 3064 * All 2-endpoints configs have high and normal 3065 * priority queues. 3066 */ 3067 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3068 } else 3069 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3070 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3071 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3072 return (EIO); 3073 3074 /* Set Tx/Rx transfer page boundary. */ 3075 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 3076 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 3077 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3078 return (EIO); 3079 3080 /* Set Tx/Rx transfer page size. */ 3081 usb_err = urtwn_write_1(sc, R92C_PBP, 3082 SM(R92C_PBP_PSRX, R92C_PBP_128) | 3083 SM(R92C_PBP_PSTX, R92C_PBP_128)); 3084 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3085 return (EIO); 3086 3087 return (0); 3088} 3089 3090static int 3091urtwn_mac_init(struct urtwn_softc *sc) 3092{ 3093 usb_error_t error; 3094 int i; 3095 3096 /* Write MAC initialization values. */ 3097 if (sc->chip & URTWN_CHIP_88E) { 3098 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 3099 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3100 rtl8188eu_mac[i].val); 3101 if (error != USB_ERR_NORMAL_COMPLETION) 3102 return (EIO); 3103 } 3104 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 3105 } else { 3106 for (i = 0; i < nitems(rtl8192cu_mac); i++) 3107 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3108 rtl8192cu_mac[i].val); 3109 if (error != USB_ERR_NORMAL_COMPLETION) 3110 return (EIO); 3111 } 3112 3113 return (0); 3114} 3115 3116static void 3117urtwn_bb_init(struct urtwn_softc *sc) 3118{ 3119 const struct urtwn_bb_prog *prog; 3120 uint32_t reg; 3121 uint8_t crystalcap; 3122 int i; 3123 3124 /* Enable BB and RF. */ 3125 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3126 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3127 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3128 R92C_SYS_FUNC_EN_DIO_RF); 3129 3130 if (!(sc->chip & URTWN_CHIP_88E)) 3131 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 3132 3133 urtwn_write_1(sc, R92C_RF_CTRL, 3134 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3135 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3136 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3137 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3138 3139 if (!(sc->chip & URTWN_CHIP_88E)) { 3140 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3141 urtwn_write_1(sc, 0x15, 0xe9); 3142 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3143 } 3144 3145 /* Select BB programming based on board type. */ 3146 if (sc->chip & URTWN_CHIP_88E) 3147 prog = &rtl8188eu_bb_prog; 3148 else if (!(sc->chip & URTWN_CHIP_92C)) { 3149 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3150 prog = &rtl8188ce_bb_prog; 3151 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3152 prog = &rtl8188ru_bb_prog; 3153 else 3154 prog = &rtl8188cu_bb_prog; 3155 } else { 3156 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3157 prog = &rtl8192ce_bb_prog; 3158 else 3159 prog = &rtl8192cu_bb_prog; 3160 } 3161 /* Write BB initialization values. */ 3162 for (i = 0; i < prog->count; i++) { 3163 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3164 urtwn_ms_delay(sc); 3165 } 3166 3167 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3168 /* 8192C 1T only configuration. */ 3169 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3170 reg = (reg & ~0x00000003) | 0x2; 3171 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3172 3173 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3174 reg = (reg & ~0x00300033) | 0x00200022; 3175 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3176 3177 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3178 reg = (reg & ~0xff000000) | 0x45 << 24; 3179 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3180 3181 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3182 reg = (reg & ~0x000000ff) | 0x23; 3183 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3184 3185 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3186 reg = (reg & ~0x00000030) | 1 << 4; 3187 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3188 3189 reg = urtwn_bb_read(sc, 0xe74); 3190 reg = (reg & ~0x0c000000) | 2 << 26; 3191 urtwn_bb_write(sc, 0xe74, reg); 3192 reg = urtwn_bb_read(sc, 0xe78); 3193 reg = (reg & ~0x0c000000) | 2 << 26; 3194 urtwn_bb_write(sc, 0xe78, reg); 3195 reg = urtwn_bb_read(sc, 0xe7c); 3196 reg = (reg & ~0x0c000000) | 2 << 26; 3197 urtwn_bb_write(sc, 0xe7c, reg); 3198 reg = urtwn_bb_read(sc, 0xe80); 3199 reg = (reg & ~0x0c000000) | 2 << 26; 3200 urtwn_bb_write(sc, 0xe80, reg); 3201 reg = urtwn_bb_read(sc, 0xe88); 3202 reg = (reg & ~0x0c000000) | 2 << 26; 3203 urtwn_bb_write(sc, 0xe88, reg); 3204 } 3205 3206 /* Write AGC values. */ 3207 for (i = 0; i < prog->agccount; i++) { 3208 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 3209 prog->agcvals[i]); 3210 urtwn_ms_delay(sc); 3211 } 3212 3213 if (sc->chip & URTWN_CHIP_88E) { 3214 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3215 urtwn_ms_delay(sc); 3216 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3217 urtwn_ms_delay(sc); 3218 3219 crystalcap = sc->rom.r88e_rom[0xb9]; 3220 if (crystalcap == 0xff) 3221 crystalcap = 0x20; 3222 crystalcap &= 0x3f; 3223 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3224 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3225 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3226 crystalcap | crystalcap << 6)); 3227 } else { 3228 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3229 R92C_HSSI_PARAM2_CCK_HIPWR) 3230 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 3231 } 3232} 3233 3234static void 3235urtwn_rf_init(struct urtwn_softc *sc) 3236{ 3237 const struct urtwn_rf_prog *prog; 3238 uint32_t reg, type; 3239 int i, j, idx, off; 3240 3241 /* Select RF programming based on board type. */ 3242 if (sc->chip & URTWN_CHIP_88E) 3243 prog = rtl8188eu_rf_prog; 3244 else if (!(sc->chip & URTWN_CHIP_92C)) { 3245 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3246 prog = rtl8188ce_rf_prog; 3247 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3248 prog = rtl8188ru_rf_prog; 3249 else 3250 prog = rtl8188cu_rf_prog; 3251 } else 3252 prog = rtl8192ce_rf_prog; 3253 3254 for (i = 0; i < sc->nrxchains; i++) { 3255 /* Save RF_ENV control type. */ 3256 idx = i / 2; 3257 off = (i % 2) * 16; 3258 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3259 type = (reg >> off) & 0x10; 3260 3261 /* Set RF_ENV enable. */ 3262 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3263 reg |= 0x100000; 3264 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3265 urtwn_ms_delay(sc); 3266 /* Set RF_ENV output high. */ 3267 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3268 reg |= 0x10; 3269 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3270 urtwn_ms_delay(sc); 3271 /* Set address and data lengths of RF registers. */ 3272 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3273 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3274 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3275 urtwn_ms_delay(sc); 3276 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3277 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3278 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3279 urtwn_ms_delay(sc); 3280 3281 /* Write RF initialization values for this chain. */ 3282 for (j = 0; j < prog[i].count; j++) { 3283 if (prog[i].regs[j] >= 0xf9 && 3284 prog[i].regs[j] <= 0xfe) { 3285 /* 3286 * These are fake RF registers offsets that 3287 * indicate a delay is required. 3288 */ 3289 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 3290 continue; 3291 } 3292 urtwn_rf_write(sc, i, prog[i].regs[j], 3293 prog[i].vals[j]); 3294 urtwn_ms_delay(sc); 3295 } 3296 3297 /* Restore RF_ENV control type. */ 3298 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3299 reg &= ~(0x10 << off) | (type << off); 3300 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 3301 3302 /* Cache RF register CHNLBW. */ 3303 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3304 } 3305 3306 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3307 URTWN_CHIP_UMC_A_CUT) { 3308 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3309 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3310 } 3311} 3312 3313static void 3314urtwn_cam_init(struct urtwn_softc *sc) 3315{ 3316 /* Invalidate all CAM entries. */ 3317 urtwn_write_4(sc, R92C_CAMCMD, 3318 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3319} 3320 3321static void 3322urtwn_pa_bias_init(struct urtwn_softc *sc) 3323{ 3324 uint8_t reg; 3325 int i; 3326 3327 for (i = 0; i < sc->nrxchains; i++) { 3328 if (sc->pa_setting & (1 << i)) 3329 continue; 3330 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3331 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3332 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3333 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3334 } 3335 if (!(sc->pa_setting & 0x10)) { 3336 reg = urtwn_read_1(sc, 0x16); 3337 reg = (reg & ~0xf0) | 0x90; 3338 urtwn_write_1(sc, 0x16, reg); 3339 } 3340} 3341 3342static void 3343urtwn_rxfilter_init(struct urtwn_softc *sc) 3344{ 3345 struct ieee80211com *ic = &sc->sc_ic; 3346 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3347 uint32_t rcr; 3348 uint16_t filter; 3349 3350 URTWN_ASSERT_LOCKED(sc); 3351 3352 /* Accept all multicast frames. */ 3353 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3354 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3355 3356 /* Filter for management frames. */ 3357 filter = 0x7f3f; 3358 switch (vap->iv_opmode) { 3359 case IEEE80211_M_STA: 3360 filter &= ~( 3361 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 3362 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 3363 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 3364 break; 3365 case IEEE80211_M_HOSTAP: 3366 filter &= ~( 3367 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 3368 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP) | 3369 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_BEACON)); 3370 break; 3371 case IEEE80211_M_MONITOR: 3372 case IEEE80211_M_IBSS: 3373 break; 3374 default: 3375 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3376 __func__, vap->iv_opmode); 3377 break; 3378 } 3379 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 3380 3381 /* Reject all control frames. */ 3382 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3383 3384 /* Reject all data frames. */ 3385 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 3386 3387 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 3388 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 3389 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 3390 3391 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 3392 /* Accept all frames. */ 3393 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 3394 R92C_RCR_AAP; 3395 } 3396 3397 /* Set Rx filter. */ 3398 urtwn_write_4(sc, R92C_RCR, rcr); 3399 3400 if (ic->ic_promisc != 0) { 3401 /* Update Rx filter. */ 3402 urtwn_set_promisc(sc); 3403 } 3404} 3405 3406static void 3407urtwn_edca_init(struct urtwn_softc *sc) 3408{ 3409 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3410 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3411 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3412 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3413 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3414 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3415 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3416 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3417} 3418 3419static void 3420urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3421 uint16_t power[URTWN_RIDX_COUNT]) 3422{ 3423 uint32_t reg; 3424 3425 /* Write per-CCK rate Tx power. */ 3426 if (chain == 0) { 3427 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3428 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3429 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3430 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3431 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3432 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3433 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3434 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3435 } else { 3436 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3437 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3438 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3439 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3440 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3441 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3442 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3443 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3444 } 3445 /* Write per-OFDM rate Tx power. */ 3446 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3447 SM(R92C_TXAGC_RATE06, power[ 4]) | 3448 SM(R92C_TXAGC_RATE09, power[ 5]) | 3449 SM(R92C_TXAGC_RATE12, power[ 6]) | 3450 SM(R92C_TXAGC_RATE18, power[ 7])); 3451 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3452 SM(R92C_TXAGC_RATE24, power[ 8]) | 3453 SM(R92C_TXAGC_RATE36, power[ 9]) | 3454 SM(R92C_TXAGC_RATE48, power[10]) | 3455 SM(R92C_TXAGC_RATE54, power[11])); 3456 /* Write per-MCS Tx power. */ 3457 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3458 SM(R92C_TXAGC_MCS00, power[12]) | 3459 SM(R92C_TXAGC_MCS01, power[13]) | 3460 SM(R92C_TXAGC_MCS02, power[14]) | 3461 SM(R92C_TXAGC_MCS03, power[15])); 3462 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3463 SM(R92C_TXAGC_MCS04, power[16]) | 3464 SM(R92C_TXAGC_MCS05, power[17]) | 3465 SM(R92C_TXAGC_MCS06, power[18]) | 3466 SM(R92C_TXAGC_MCS07, power[19])); 3467 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3468 SM(R92C_TXAGC_MCS08, power[20]) | 3469 SM(R92C_TXAGC_MCS09, power[21]) | 3470 SM(R92C_TXAGC_MCS10, power[22]) | 3471 SM(R92C_TXAGC_MCS11, power[23])); 3472 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3473 SM(R92C_TXAGC_MCS12, power[24]) | 3474 SM(R92C_TXAGC_MCS13, power[25]) | 3475 SM(R92C_TXAGC_MCS14, power[26]) | 3476 SM(R92C_TXAGC_MCS15, power[27])); 3477} 3478 3479static void 3480urtwn_get_txpower(struct urtwn_softc *sc, int chain, 3481 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3482 uint16_t power[URTWN_RIDX_COUNT]) 3483{ 3484 struct ieee80211com *ic = &sc->sc_ic; 3485 struct r92c_rom *rom = &sc->rom.r92c_rom; 3486 uint16_t cckpow, ofdmpow, htpow, diff, max; 3487 const struct urtwn_txpwr *base; 3488 int ridx, chan, group; 3489 3490 /* Determine channel group. */ 3491 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3492 if (chan <= 3) 3493 group = 0; 3494 else if (chan <= 9) 3495 group = 1; 3496 else 3497 group = 2; 3498 3499 /* Get original Tx power based on board type and RF chain. */ 3500 if (!(sc->chip & URTWN_CHIP_92C)) { 3501 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3502 base = &rtl8188ru_txagc[chain]; 3503 else 3504 base = &rtl8192cu_txagc[chain]; 3505 } else 3506 base = &rtl8192cu_txagc[chain]; 3507 3508 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3509 if (sc->regulatory == 0) { 3510 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3511 power[ridx] = base->pwr[0][ridx]; 3512 } 3513 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3514 if (sc->regulatory == 3) { 3515 power[ridx] = base->pwr[0][ridx]; 3516 /* Apply vendor limits. */ 3517 if (extc != NULL) 3518 max = rom->ht40_max_pwr[group]; 3519 else 3520 max = rom->ht20_max_pwr[group]; 3521 max = (max >> (chain * 4)) & 0xf; 3522 if (power[ridx] > max) 3523 power[ridx] = max; 3524 } else if (sc->regulatory == 1) { 3525 if (extc == NULL) 3526 power[ridx] = base->pwr[group][ridx]; 3527 } else if (sc->regulatory != 2) 3528 power[ridx] = base->pwr[0][ridx]; 3529 } 3530 3531 /* Compute per-CCK rate Tx power. */ 3532 cckpow = rom->cck_tx_pwr[chain][group]; 3533 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3534 power[ridx] += cckpow; 3535 if (power[ridx] > R92C_MAX_TX_PWR) 3536 power[ridx] = R92C_MAX_TX_PWR; 3537 } 3538 3539 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3540 if (sc->ntxchains > 1) { 3541 /* Apply reduction for 2 spatial streams. */ 3542 diff = rom->ht40_2s_tx_pwr_diff[group]; 3543 diff = (diff >> (chain * 4)) & 0xf; 3544 htpow = (htpow > diff) ? htpow - diff : 0; 3545 } 3546 3547 /* Compute per-OFDM rate Tx power. */ 3548 diff = rom->ofdm_tx_pwr_diff[group]; 3549 diff = (diff >> (chain * 4)) & 0xf; 3550 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3551 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3552 power[ridx] += ofdmpow; 3553 if (power[ridx] > R92C_MAX_TX_PWR) 3554 power[ridx] = R92C_MAX_TX_PWR; 3555 } 3556 3557 /* Compute per-MCS Tx power. */ 3558 if (extc == NULL) { 3559 diff = rom->ht20_tx_pwr_diff[group]; 3560 diff = (diff >> (chain * 4)) & 0xf; 3561 htpow += diff; /* HT40->HT20 correction. */ 3562 } 3563 for (ridx = 12; ridx <= 27; ridx++) { 3564 power[ridx] += htpow; 3565 if (power[ridx] > R92C_MAX_TX_PWR) 3566 power[ridx] = R92C_MAX_TX_PWR; 3567 } 3568#ifdef URTWN_DEBUG 3569 if (urtwn_debug >= 4) { 3570 /* Dump per-rate Tx power values. */ 3571 printf("Tx power for chain %d:\n", chain); 3572 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 3573 printf("Rate %d = %u\n", ridx, power[ridx]); 3574 } 3575#endif 3576} 3577 3578static void 3579urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3580 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3581 uint16_t power[URTWN_RIDX_COUNT]) 3582{ 3583 struct ieee80211com *ic = &sc->sc_ic; 3584 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3585 const struct urtwn_r88e_txpwr *base; 3586 int ridx, chan, group; 3587 3588 /* Determine channel group. */ 3589 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3590 if (chan <= 2) 3591 group = 0; 3592 else if (chan <= 5) 3593 group = 1; 3594 else if (chan <= 8) 3595 group = 2; 3596 else if (chan <= 11) 3597 group = 3; 3598 else if (chan <= 13) 3599 group = 4; 3600 else 3601 group = 5; 3602 3603 /* Get original Tx power based on board type and RF chain. */ 3604 base = &rtl8188eu_txagc[chain]; 3605 3606 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3607 if (sc->regulatory == 0) { 3608 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3609 power[ridx] = base->pwr[0][ridx]; 3610 } 3611 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3612 if (sc->regulatory == 3) 3613 power[ridx] = base->pwr[0][ridx]; 3614 else if (sc->regulatory == 1) { 3615 if (extc == NULL) 3616 power[ridx] = base->pwr[group][ridx]; 3617 } else if (sc->regulatory != 2) 3618 power[ridx] = base->pwr[0][ridx]; 3619 } 3620 3621 /* Compute per-CCK rate Tx power. */ 3622 cckpow = sc->cck_tx_pwr[group]; 3623 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3624 power[ridx] += cckpow; 3625 if (power[ridx] > R92C_MAX_TX_PWR) 3626 power[ridx] = R92C_MAX_TX_PWR; 3627 } 3628 3629 htpow = sc->ht40_tx_pwr[group]; 3630 3631 /* Compute per-OFDM rate Tx power. */ 3632 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3633 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3634 power[ridx] += ofdmpow; 3635 if (power[ridx] > R92C_MAX_TX_PWR) 3636 power[ridx] = R92C_MAX_TX_PWR; 3637 } 3638 3639 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3640 for (ridx = 12; ridx <= 27; ridx++) { 3641 power[ridx] += bw20pow; 3642 if (power[ridx] > R92C_MAX_TX_PWR) 3643 power[ridx] = R92C_MAX_TX_PWR; 3644 } 3645} 3646 3647static void 3648urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3649 struct ieee80211_channel *extc) 3650{ 3651 uint16_t power[URTWN_RIDX_COUNT]; 3652 int i; 3653 3654 for (i = 0; i < sc->ntxchains; i++) { 3655 /* Compute per-rate Tx power values. */ 3656 if (sc->chip & URTWN_CHIP_88E) 3657 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3658 else 3659 urtwn_get_txpower(sc, i, c, extc, power); 3660 /* Write per-rate Tx power values to hardware. */ 3661 urtwn_write_txpower(sc, i, power); 3662 } 3663} 3664 3665static void 3666urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 3667{ 3668 uint32_t reg; 3669 3670 reg = urtwn_read_4(sc, R92C_RCR); 3671 if (enable) 3672 reg &= ~R92C_RCR_CBSSID_BCN; 3673 else 3674 reg |= R92C_RCR_CBSSID_BCN; 3675 urtwn_write_4(sc, R92C_RCR, reg); 3676} 3677 3678static void 3679urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 3680{ 3681 uint32_t reg; 3682 3683 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3684 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3685 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3686 3687 if (!(sc->chip & URTWN_CHIP_88E)) { 3688 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3689 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3690 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3691 } 3692} 3693 3694static void 3695urtwn_scan_start(struct ieee80211com *ic) 3696{ 3697 struct urtwn_softc *sc = ic->ic_softc; 3698 3699 URTWN_LOCK(sc); 3700 /* Receive beacons / probe responses from any BSSID. */ 3701 if (ic->ic_opmode != IEEE80211_M_IBSS) 3702 urtwn_set_rx_bssid_all(sc, 1); 3703 3704 /* Set gain for scanning. */ 3705 urtwn_set_gain(sc, 0x20); 3706 URTWN_UNLOCK(sc); 3707} 3708 3709static void 3710urtwn_scan_end(struct ieee80211com *ic) 3711{ 3712 struct urtwn_softc *sc = ic->ic_softc; 3713 3714 URTWN_LOCK(sc); 3715 /* Restore limitations. */ 3716 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 3717 urtwn_set_rx_bssid_all(sc, 0); 3718 3719 /* Set gain under link. */ 3720 urtwn_set_gain(sc, 0x32); 3721 URTWN_UNLOCK(sc); 3722} 3723 3724static void 3725urtwn_set_channel(struct ieee80211com *ic) 3726{ 3727 struct urtwn_softc *sc = ic->ic_softc; 3728 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3729 3730 URTWN_LOCK(sc); 3731 if (vap->iv_state == IEEE80211_S_SCAN) { 3732 /* Make link LED blink during scan. */ 3733 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3734 } 3735 urtwn_set_chan(sc, ic->ic_curchan, NULL); 3736 URTWN_UNLOCK(sc); 3737} 3738 3739static int 3740urtwn_wme_update(struct ieee80211com *ic) 3741{ 3742 const struct wmeParams *wmep = 3743 ic->ic_wme.wme_chanParams.cap_wmeParams; 3744 struct urtwn_softc *sc = ic->ic_softc; 3745 uint8_t aifs, acm, slottime; 3746 int ac; 3747 3748 acm = 0; 3749 slottime = IEEE80211_GET_SLOTTIME(ic); 3750 3751 URTWN_LOCK(sc); 3752 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 3753 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 3754 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 3755 urtwn_write_4(sc, wme2queue[ac].reg, 3756 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 3757 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 3758 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 3759 SM(R92C_EDCA_PARAM_AIFS, aifs)); 3760 if (ac != WME_AC_BE) 3761 acm |= wmep[ac].wmep_acm << ac; 3762 } 3763 3764 if (acm != 0) 3765 acm |= R92C_ACMHWCTRL_EN; 3766 urtwn_write_1(sc, R92C_ACMHWCTRL, 3767 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 3768 acm); 3769 3770 URTWN_UNLOCK(sc); 3771 3772 return 0; 3773} 3774 3775static void 3776urtwn_set_promisc(struct urtwn_softc *sc) 3777{ 3778 struct ieee80211com *ic = &sc->sc_ic; 3779 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3780 uint32_t rcr, mask1, mask2; 3781 3782 URTWN_ASSERT_LOCKED(sc); 3783 3784 if (vap->iv_opmode == IEEE80211_M_MONITOR) 3785 return; 3786 3787 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 3788 mask2 = R92C_RCR_APM; 3789 3790 if (vap->iv_state == IEEE80211_S_RUN) { 3791 switch (vap->iv_opmode) { 3792 case IEEE80211_M_STA: 3793 mask2 |= R92C_RCR_CBSSID_DATA; 3794 /* FALLTHROUGH */ 3795 case IEEE80211_M_HOSTAP: 3796 mask2 |= R92C_RCR_CBSSID_BCN; 3797 break; 3798 case IEEE80211_M_IBSS: 3799 mask2 |= R92C_RCR_CBSSID_DATA; 3800 break; 3801 default: 3802 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3803 __func__, vap->iv_opmode); 3804 return; 3805 } 3806 } 3807 3808 rcr = urtwn_read_4(sc, R92C_RCR); 3809 if (ic->ic_promisc == 0) 3810 rcr = (rcr & ~mask1) | mask2; 3811 else 3812 rcr = (rcr & ~mask2) | mask1; 3813 urtwn_write_4(sc, R92C_RCR, rcr); 3814} 3815 3816static void 3817urtwn_update_promisc(struct ieee80211com *ic) 3818{ 3819 struct urtwn_softc *sc = ic->ic_softc; 3820 3821 URTWN_LOCK(sc); 3822 if (sc->sc_flags & URTWN_RUNNING) 3823 urtwn_set_promisc(sc); 3824 URTWN_UNLOCK(sc); 3825} 3826 3827static void 3828urtwn_update_mcast(struct ieee80211com *ic) 3829{ 3830 /* XXX do nothing? */ 3831} 3832 3833static struct ieee80211_node * 3834urtwn_r88e_node_alloc(struct ieee80211vap *vap, 3835 const uint8_t mac[IEEE80211_ADDR_LEN]) 3836{ 3837 struct urtwn_node *un; 3838 3839 un = malloc(sizeof (struct urtwn_node), M_80211_NODE, 3840 M_NOWAIT | M_ZERO); 3841 3842 if (un == NULL) 3843 return NULL; 3844 3845 un->id = URTWN_MACID_UNDEFINED; 3846 3847 return &un->ni; 3848} 3849 3850static void 3851urtwn_r88e_newassoc(struct ieee80211_node *ni, int isnew) 3852{ 3853 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 3854 struct urtwn_node *un = URTWN_NODE(ni); 3855 uint8_t id; 3856 3857 if (!isnew) 3858 return; 3859 3860 URTWN_NT_LOCK(sc); 3861 for (id = 0; id <= URTWN_MACID_MAX(sc); id++) { 3862 if (id != URTWN_MACID_BC && sc->node_list[id] == NULL) { 3863 un->id = id; 3864 sc->node_list[id] = ni; 3865 break; 3866 } 3867 } 3868 URTWN_NT_UNLOCK(sc); 3869 3870 if (id > URTWN_MACID_MAX(sc)) { 3871 device_printf(sc->sc_dev, "%s: node table is full\n", 3872 __func__); 3873 } 3874} 3875 3876static void 3877urtwn_r88e_node_free(struct ieee80211_node *ni) 3878{ 3879 struct urtwn_softc *sc = ni->ni_ic->ic_softc; 3880 struct urtwn_node *un = URTWN_NODE(ni); 3881 3882 URTWN_NT_LOCK(sc); 3883 if (un->id != URTWN_MACID_UNDEFINED) 3884 sc->node_list[un->id] = NULL; 3885 URTWN_NT_UNLOCK(sc); 3886 3887 sc->sc_node_free(ni); 3888} 3889 3890static void 3891urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3892 struct ieee80211_channel *extc) 3893{ 3894 struct ieee80211com *ic = &sc->sc_ic; 3895 uint32_t reg; 3896 u_int chan; 3897 int i; 3898 3899 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3900 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3901 device_printf(sc->sc_dev, 3902 "%s: invalid channel %x\n", __func__, chan); 3903 return; 3904 } 3905 3906 /* Set Tx power for this new channel. */ 3907 urtwn_set_txpower(sc, c, extc); 3908 3909 for (i = 0; i < sc->nrxchains; i++) { 3910 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3911 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3912 } 3913#ifndef IEEE80211_NO_HT 3914 if (extc != NULL) { 3915 /* Is secondary channel below or above primary? */ 3916 int prichlo = c->ic_freq < extc->ic_freq; 3917 3918 urtwn_write_1(sc, R92C_BWOPMODE, 3919 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3920 3921 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3922 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3923 urtwn_write_1(sc, R92C_RRSR + 2, reg); 3924 3925 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3926 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3927 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3928 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3929 3930 /* Set CCK side band. */ 3931 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3932 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3933 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3934 3935 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3936 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3937 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3938 3939 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3940 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3941 ~R92C_FPGA0_ANAPARAM2_CBW20); 3942 3943 reg = urtwn_bb_read(sc, 0x818); 3944 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3945 urtwn_bb_write(sc, 0x818, reg); 3946 3947 /* Select 40MHz bandwidth. */ 3948 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3949 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3950 } else 3951#endif 3952 { 3953 urtwn_write_1(sc, R92C_BWOPMODE, 3954 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3955 3956 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3957 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3958 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3959 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3960 3961 if (!(sc->chip & URTWN_CHIP_88E)) { 3962 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3963 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3964 R92C_FPGA0_ANAPARAM2_CBW20); 3965 } 3966 3967 /* Select 20MHz bandwidth. */ 3968 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3969 (sc->rf_chnlbw[0] & ~0xfff) | chan | 3970 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3971 R92C_RF_CHNLBW_BW20)); 3972 } 3973} 3974 3975static void 3976urtwn_iq_calib(struct urtwn_softc *sc) 3977{ 3978 /* TODO */ 3979} 3980 3981static void 3982urtwn_lc_calib(struct urtwn_softc *sc) 3983{ 3984 uint32_t rf_ac[2]; 3985 uint8_t txmode; 3986 int i; 3987 3988 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3989 if ((txmode & 0x70) != 0) { 3990 /* Disable all continuous Tx. */ 3991 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3992 3993 /* Set RF mode to standby mode. */ 3994 for (i = 0; i < sc->nrxchains; i++) { 3995 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3996 urtwn_rf_write(sc, i, R92C_RF_AC, 3997 RW(rf_ac[i], R92C_RF_AC_MODE, 3998 R92C_RF_AC_MODE_STANDBY)); 3999 } 4000 } else { 4001 /* Block all Tx queues. */ 4002 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4003 } 4004 /* Start calibration. */ 4005 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4006 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4007 4008 /* Give calibration the time to complete. */ 4009 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 4010 4011 /* Restore configuration. */ 4012 if ((txmode & 0x70) != 0) { 4013 /* Restore Tx mode. */ 4014 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4015 /* Restore RF mode. */ 4016 for (i = 0; i < sc->nrxchains; i++) 4017 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4018 } else { 4019 /* Unblock all Tx queues. */ 4020 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4021 } 4022} 4023 4024static int 4025urtwn_init(struct urtwn_softc *sc) 4026{ 4027 struct ieee80211com *ic = &sc->sc_ic; 4028 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4029 uint8_t macaddr[IEEE80211_ADDR_LEN]; 4030 uint32_t reg; 4031 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 4032 int error; 4033 4034 URTWN_LOCK(sc); 4035 if (sc->sc_flags & URTWN_RUNNING) { 4036 URTWN_UNLOCK(sc); 4037 return (0); 4038 } 4039 4040 /* Init firmware commands ring. */ 4041 sc->fwcur = 0; 4042 4043 /* Allocate Tx/Rx buffers. */ 4044 error = urtwn_alloc_rx_list(sc); 4045 if (error != 0) 4046 goto fail; 4047 4048 error = urtwn_alloc_tx_list(sc); 4049 if (error != 0) 4050 goto fail; 4051 4052 /* Power on adapter. */ 4053 error = urtwn_power_on(sc); 4054 if (error != 0) 4055 goto fail; 4056 4057 /* Initialize DMA. */ 4058 error = urtwn_dma_init(sc); 4059 if (error != 0) 4060 goto fail; 4061 4062 /* Set info size in Rx descriptors (in 64-bit words). */ 4063 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4064 4065 /* Init interrupts. */ 4066 if (sc->chip & URTWN_CHIP_88E) { 4067 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4068 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4069 goto fail; 4070 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4071 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4072 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4073 goto fail; 4074 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4075 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4076 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4077 goto fail; 4078 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4079 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4080 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4081 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4082 goto fail; 4083 } else { 4084 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4085 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4086 goto fail; 4087 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4088 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4089 goto fail; 4090 } 4091 4092 /* Set MAC address. */ 4093 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 4094 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 4095 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4096 goto fail; 4097 4098 /* Set initial network type. */ 4099 urtwn_set_mode(sc, R92C_MSR_INFRA); 4100 4101 /* Initialize Rx filter. */ 4102 urtwn_rxfilter_init(sc); 4103 4104 /* Set response rate. */ 4105 reg = urtwn_read_4(sc, R92C_RRSR); 4106 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4107 urtwn_write_4(sc, R92C_RRSR, reg); 4108 4109 /* Set short/long retry limits. */ 4110 urtwn_write_2(sc, R92C_RL, 4111 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4112 4113 /* Initialize EDCA parameters. */ 4114 urtwn_edca_init(sc); 4115 4116 /* Setup rate fallback. */ 4117 if (!(sc->chip & URTWN_CHIP_88E)) { 4118 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4119 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4120 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4121 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4122 } 4123 4124 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4125 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4126 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4127 /* Set ACK timeout. */ 4128 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4129 4130 /* Setup USB aggregation. */ 4131 reg = urtwn_read_4(sc, R92C_TDECTRL); 4132 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4133 urtwn_write_4(sc, R92C_TDECTRL, reg); 4134 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4135 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4136 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4137 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4138 if (sc->chip & URTWN_CHIP_88E) 4139 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4140 else { 4141 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4142 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4143 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4144 R92C_USB_SPECIAL_OPTION_AGG_EN); 4145 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 4146 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 4147 } 4148 4149 /* Initialize beacon parameters. */ 4150 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4151 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4152 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 4153 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 4154 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4155 4156 if (!(sc->chip & URTWN_CHIP_88E)) { 4157 /* Setup AMPDU aggregation. */ 4158 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4159 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4160 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 4161 4162 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4163 } 4164 4165 /* Load 8051 microcode. */ 4166 error = urtwn_load_firmware(sc); 4167 if (error != 0) 4168 goto fail; 4169 4170 /* Initialize MAC/BB/RF blocks. */ 4171 error = urtwn_mac_init(sc); 4172 if (error != 0) { 4173 device_printf(sc->sc_dev, 4174 "%s: error while initializing MAC block\n", __func__); 4175 goto fail; 4176 } 4177 urtwn_bb_init(sc); 4178 urtwn_rf_init(sc); 4179 4180 /* Reinitialize Rx filter (D3845 is not committed yet). */ 4181 urtwn_rxfilter_init(sc); 4182 4183 if (sc->chip & URTWN_CHIP_88E) { 4184 urtwn_write_2(sc, R92C_CR, 4185 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4186 R92C_CR_MACRXEN); 4187 } 4188 4189 /* Turn CCK and OFDM blocks on. */ 4190 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4191 reg |= R92C_RFMOD_CCK_EN; 4192 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4193 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4194 goto fail; 4195 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4196 reg |= R92C_RFMOD_OFDM_EN; 4197 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4198 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4199 goto fail; 4200 4201 /* Clear per-station keys table. */ 4202 urtwn_cam_init(sc); 4203 4204 /* Enable hardware sequence numbering. */ 4205 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4206 4207 /* Enable per-packet TX report. */ 4208 if (sc->chip & URTWN_CHIP_88E) { 4209 urtwn_write_1(sc, R88E_TX_RPT_CTRL, 4210 urtwn_read_1(sc, R88E_TX_RPT_CTRL) | R88E_TX_RPT1_ENA); 4211 } 4212 4213 /* Perform LO and IQ calibrations. */ 4214 urtwn_iq_calib(sc); 4215 /* Perform LC calibration. */ 4216 urtwn_lc_calib(sc); 4217 4218 /* Fix USB interference issue. */ 4219 if (!(sc->chip & URTWN_CHIP_88E)) { 4220 urtwn_write_1(sc, 0xfe40, 0xe0); 4221 urtwn_write_1(sc, 0xfe41, 0x8d); 4222 urtwn_write_1(sc, 0xfe42, 0x80); 4223 4224 urtwn_pa_bias_init(sc); 4225 } 4226 4227 /* Initialize GPIO setting. */ 4228 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4229 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4230 4231 /* Fix for lower temperature. */ 4232 if (!(sc->chip & URTWN_CHIP_88E)) 4233 urtwn_write_1(sc, 0x15, 0xe9); 4234 4235 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 4236 4237 sc->sc_flags |= URTWN_RUNNING; 4238 4239 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4240fail: 4241 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4242 error = EIO; 4243 4244 URTWN_UNLOCK(sc); 4245 4246 return (error); 4247} 4248 4249static void 4250urtwn_stop(struct urtwn_softc *sc) 4251{ 4252 4253 URTWN_LOCK(sc); 4254 if (!(sc->sc_flags & URTWN_RUNNING)) { 4255 URTWN_UNLOCK(sc); 4256 return; 4257 } 4258 4259 sc->sc_flags &= ~URTWN_RUNNING; 4260 callout_stop(&sc->sc_watchdog_ch); 4261 urtwn_abort_xfers(sc); 4262 4263 urtwn_drain_mbufq(sc); 4264 URTWN_UNLOCK(sc); 4265} 4266 4267static void 4268urtwn_abort_xfers(struct urtwn_softc *sc) 4269{ 4270 int i; 4271 4272 URTWN_ASSERT_LOCKED(sc); 4273 4274 /* abort any pending transfers */ 4275 for (i = 0; i < URTWN_N_TRANSFER; i++) 4276 usbd_transfer_stop(sc->sc_xfer[i]); 4277} 4278 4279static int 4280urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4281 const struct ieee80211_bpf_params *params) 4282{ 4283 struct ieee80211com *ic = ni->ni_ic; 4284 struct urtwn_softc *sc = ic->ic_softc; 4285 struct urtwn_data *bf; 4286 int error; 4287 4288 /* prevent management frames from being sent if we're not ready */ 4289 URTWN_LOCK(sc); 4290 if (!(sc->sc_flags & URTWN_RUNNING)) { 4291 error = ENETDOWN; 4292 goto end; 4293 } 4294 4295 bf = urtwn_getbuf(sc); 4296 if (bf == NULL) { 4297 error = ENOBUFS; 4298 goto end; 4299 } 4300 4301 if ((error = urtwn_tx_data(sc, ni, m, bf)) != 0) { 4302 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 4303 goto end; 4304 } 4305 4306 sc->sc_txtimer = 5; 4307 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4308 4309end: 4310 if (error != 0) 4311 m_freem(m); 4312 4313 URTWN_UNLOCK(sc); 4314 4315 return (error); 4316} 4317 4318static void 4319urtwn_ms_delay(struct urtwn_softc *sc) 4320{ 4321 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 4322} 4323 4324static device_method_t urtwn_methods[] = { 4325 /* Device interface */ 4326 DEVMETHOD(device_probe, urtwn_match), 4327 DEVMETHOD(device_attach, urtwn_attach), 4328 DEVMETHOD(device_detach, urtwn_detach), 4329 4330 DEVMETHOD_END 4331}; 4332 4333static driver_t urtwn_driver = { 4334 "urtwn", 4335 urtwn_methods, 4336 sizeof(struct urtwn_softc) 4337}; 4338 4339static devclass_t urtwn_devclass; 4340 4341DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 4342MODULE_DEPEND(urtwn, usb, 1, 1, 1); 4343MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 4344MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 4345MODULE_VERSION(urtwn, 1); 4346USB_PNP_HOST_INFO(urtwn_devs); 4347