if_urtwn.c revision 292056
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 292056 2015-12-10 07:45:58Z kevlo $"); 22 23/* 24 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25 */ 26 27#include "opt_wlan.h" 28 29#include <sys/param.h> 30#include <sys/sockio.h> 31#include <sys/sysctl.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/condvar.h> 35#include <sys/mbuf.h> 36#include <sys/kernel.h> 37#include <sys/socket.h> 38#include <sys/systm.h> 39#include <sys/malloc.h> 40#include <sys/module.h> 41#include <sys/bus.h> 42#include <sys/endian.h> 43#include <sys/linker.h> 44#include <sys/firmware.h> 45#include <sys/kdb.h> 46 47#include <machine/bus.h> 48#include <machine/resource.h> 49#include <sys/rman.h> 50 51#include <net/bpf.h> 52#include <net/if.h> 53#include <net/if_var.h> 54#include <net/if_arp.h> 55#include <net/ethernet.h> 56#include <net/if_dl.h> 57#include <net/if_media.h> 58#include <net/if_types.h> 59 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/in_var.h> 63#include <netinet/if_ether.h> 64#include <netinet/ip.h> 65 66#include <net80211/ieee80211_var.h> 67#include <net80211/ieee80211_input.h> 68#include <net80211/ieee80211_regdomain.h> 69#include <net80211/ieee80211_radiotap.h> 70#include <net80211/ieee80211_ratectl.h> 71 72#include <dev/usb/usb.h> 73#include <dev/usb/usbdi.h> 74#include <dev/usb/usb_device.h> 75#include "usbdevs.h" 76 77#define USB_DEBUG_VAR urtwn_debug 78#include <dev/usb/usb_debug.h> 79 80#include <dev/usb/wlan/if_urtwnreg.h> 81#include <dev/usb/wlan/if_urtwnvar.h> 82 83#ifdef USB_DEBUG 84static int urtwn_debug = 0; 85 86SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 87SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 88 "Debug level"); 89#endif 90 91#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 92 93/* various supported device vendors/products */ 94static const STRUCT_USB_HOST_ID urtwn_devs[] = { 95#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 96#define URTWN_RTL8188E_DEV(v,p) \ 97 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 98#define URTWN_RTL8188E 1 99 URTWN_DEV(ABOCOM, RTL8188CU_1), 100 URTWN_DEV(ABOCOM, RTL8188CU_2), 101 URTWN_DEV(ABOCOM, RTL8192CU), 102 URTWN_DEV(ASUS, RTL8192CU), 103 URTWN_DEV(ASUS, USBN10NANO), 104 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 105 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 106 URTWN_DEV(AZUREWAVE, RTL8188CU), 107 URTWN_DEV(BELKIN, F7D2102), 108 URTWN_DEV(BELKIN, RTL8188CU), 109 URTWN_DEV(BELKIN, RTL8192CU), 110 URTWN_DEV(CHICONY, RTL8188CUS_1), 111 URTWN_DEV(CHICONY, RTL8188CUS_2), 112 URTWN_DEV(CHICONY, RTL8188CUS_3), 113 URTWN_DEV(CHICONY, RTL8188CUS_4), 114 URTWN_DEV(CHICONY, RTL8188CUS_5), 115 URTWN_DEV(COREGA, RTL8192CU), 116 URTWN_DEV(DLINK, RTL8188CU), 117 URTWN_DEV(DLINK, RTL8192CU_1), 118 URTWN_DEV(DLINK, RTL8192CU_2), 119 URTWN_DEV(DLINK, RTL8192CU_3), 120 URTWN_DEV(DLINK, DWA131B), 121 URTWN_DEV(EDIMAX, EW7811UN), 122 URTWN_DEV(EDIMAX, RTL8192CU), 123 URTWN_DEV(FEIXUN, RTL8188CU), 124 URTWN_DEV(FEIXUN, RTL8192CU), 125 URTWN_DEV(GUILLEMOT, HWNUP150), 126 URTWN_DEV(HAWKING, RTL8192CU), 127 URTWN_DEV(HP3, RTL8188CU), 128 URTWN_DEV(NETGEAR, WNA1000M), 129 URTWN_DEV(NETGEAR, RTL8192CU), 130 URTWN_DEV(NETGEAR4, RTL8188CU), 131 URTWN_DEV(NOVATECH, RTL8188CU), 132 URTWN_DEV(PLANEX2, RTL8188CU_1), 133 URTWN_DEV(PLANEX2, RTL8188CU_2), 134 URTWN_DEV(PLANEX2, RTL8188CU_3), 135 URTWN_DEV(PLANEX2, RTL8188CU_4), 136 URTWN_DEV(PLANEX2, RTL8188CUS), 137 URTWN_DEV(PLANEX2, RTL8192CU), 138 URTWN_DEV(REALTEK, RTL8188CE_0), 139 URTWN_DEV(REALTEK, RTL8188CE_1), 140 URTWN_DEV(REALTEK, RTL8188CTV), 141 URTWN_DEV(REALTEK, RTL8188CU_0), 142 URTWN_DEV(REALTEK, RTL8188CU_1), 143 URTWN_DEV(REALTEK, RTL8188CU_2), 144 URTWN_DEV(REALTEK, RTL8188CU_3), 145 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 146 URTWN_DEV(REALTEK, RTL8188CUS), 147 URTWN_DEV(REALTEK, RTL8188RU_1), 148 URTWN_DEV(REALTEK, RTL8188RU_2), 149 URTWN_DEV(REALTEK, RTL8188RU_3), 150 URTWN_DEV(REALTEK, RTL8191CU), 151 URTWN_DEV(REALTEK, RTL8192CE), 152 URTWN_DEV(REALTEK, RTL8192CU), 153 URTWN_DEV(SITECOMEU, RTL8188CU_1), 154 URTWN_DEV(SITECOMEU, RTL8188CU_2), 155 URTWN_DEV(SITECOMEU, RTL8192CU), 156 URTWN_DEV(TRENDNET, RTL8188CU), 157 URTWN_DEV(TRENDNET, RTL8192CU), 158 URTWN_DEV(ZYXEL, RTL8192CU), 159 /* URTWN_RTL8188E */ 160 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 161 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 162 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 163 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 164 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 165#undef URTWN_RTL8188E_DEV 166#undef URTWN_DEV 167}; 168 169static device_probe_t urtwn_match; 170static device_attach_t urtwn_attach; 171static device_detach_t urtwn_detach; 172 173static usb_callback_t urtwn_bulk_tx_callback; 174static usb_callback_t urtwn_bulk_rx_callback; 175 176static void urtwn_drain_mbufq(struct urtwn_softc *sc); 177static usb_error_t urtwn_do_request(struct urtwn_softc *, 178 struct usb_device_request *, void *); 179static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 180 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 181 const uint8_t [IEEE80211_ADDR_LEN], 182 const uint8_t [IEEE80211_ADDR_LEN]); 183static void urtwn_vap_delete(struct ieee80211vap *); 184static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 185 int *); 186static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 187 int *, int8_t *); 188static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 189 int); 190static int urtwn_alloc_list(struct urtwn_softc *, 191 struct urtwn_data[], int, int); 192static int urtwn_alloc_rx_list(struct urtwn_softc *); 193static int urtwn_alloc_tx_list(struct urtwn_softc *); 194static void urtwn_free_list(struct urtwn_softc *, 195 struct urtwn_data data[], int); 196static void urtwn_free_rx_list(struct urtwn_softc *); 197static void urtwn_free_tx_list(struct urtwn_softc *); 198static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 199static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 200static usb_error_t urtwn_write_region_1(struct urtwn_softc *, uint16_t, 201 uint8_t *, int); 202static usb_error_t urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 203static usb_error_t urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 204static usb_error_t urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 205static usb_error_t urtwn_read_region_1(struct urtwn_softc *, uint16_t, 206 uint8_t *, int); 207static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 208static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 209static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 210static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 211 const void *, int); 212static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 213 uint8_t, uint32_t); 214static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 215 uint8_t, uint32_t); 216static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 217static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 218 uint32_t); 219static int urtwn_efuse_read_next(struct urtwn_softc *, uint8_t *); 220static int urtwn_efuse_read_data(struct urtwn_softc *, uint8_t *, 221 uint8_t, uint8_t); 222#ifdef URTWN_DEBUG 223static void urtwn_dump_rom_contents(struct urtwn_softc *, 224 uint8_t *, uint16_t); 225#endif 226static int urtwn_efuse_read(struct urtwn_softc *, uint8_t *, 227 uint16_t); 228static int urtwn_efuse_switch_power(struct urtwn_softc *); 229static int urtwn_read_chipid(struct urtwn_softc *); 230static int urtwn_read_rom(struct urtwn_softc *); 231static int urtwn_r88e_read_rom(struct urtwn_softc *); 232static int urtwn_ra_init(struct urtwn_softc *); 233static void urtwn_init_beacon(struct urtwn_softc *, 234 struct urtwn_vap *); 235static int urtwn_setup_beacon(struct urtwn_softc *, 236 struct ieee80211_node *); 237static void urtwn_update_beacon(struct ieee80211vap *, int); 238static int urtwn_tx_beacon(struct urtwn_softc *sc, 239 struct urtwn_vap *); 240static void urtwn_tsf_task_adhoc(void *, int); 241static void urtwn_tsf_sync_enable(struct urtwn_softc *, 242 struct ieee80211vap *); 243static void urtwn_set_led(struct urtwn_softc *, int, int); 244static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 245static void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 246 struct mbuf *, int, 247 const struct ieee80211_rx_stats *, int, int); 248static int urtwn_newstate(struct ieee80211vap *, 249 enum ieee80211_state, int); 250static void urtwn_watchdog(void *); 251static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 252static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 253static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 254static int urtwn_tx_data(struct urtwn_softc *, 255 struct ieee80211_node *, struct mbuf *, 256 struct urtwn_data *); 257static void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 258 uint8_t, struct urtwn_data *); 259static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 260static void urtwn_start(struct urtwn_softc *); 261static void urtwn_parent(struct ieee80211com *); 262static int urtwn_r92c_power_on(struct urtwn_softc *); 263static int urtwn_r88e_power_on(struct urtwn_softc *); 264static int urtwn_llt_init(struct urtwn_softc *); 265static void urtwn_fw_reset(struct urtwn_softc *); 266static void urtwn_r88e_fw_reset(struct urtwn_softc *); 267static int urtwn_fw_loadpage(struct urtwn_softc *, int, 268 const uint8_t *, int); 269static int urtwn_load_firmware(struct urtwn_softc *); 270static int urtwn_dma_init(struct urtwn_softc *); 271static int urtwn_mac_init(struct urtwn_softc *); 272static void urtwn_bb_init(struct urtwn_softc *); 273static void urtwn_rf_init(struct urtwn_softc *); 274static void urtwn_cam_init(struct urtwn_softc *); 275static void urtwn_pa_bias_init(struct urtwn_softc *); 276static void urtwn_rxfilter_init(struct urtwn_softc *); 277static void urtwn_edca_init(struct urtwn_softc *); 278static void urtwn_write_txpower(struct urtwn_softc *, int, 279 uint16_t[]); 280static void urtwn_get_txpower(struct urtwn_softc *, int, 281 struct ieee80211_channel *, 282 struct ieee80211_channel *, uint16_t[]); 283static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 284 struct ieee80211_channel *, 285 struct ieee80211_channel *, uint16_t[]); 286static void urtwn_set_txpower(struct urtwn_softc *, 287 struct ieee80211_channel *, 288 struct ieee80211_channel *); 289static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 290static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 291static void urtwn_scan_start(struct ieee80211com *); 292static void urtwn_scan_end(struct ieee80211com *); 293static void urtwn_set_channel(struct ieee80211com *); 294static int urtwn_wme_update(struct ieee80211com *); 295static void urtwn_set_promisc(struct urtwn_softc *); 296static void urtwn_update_promisc(struct ieee80211com *); 297static void urtwn_update_mcast(struct ieee80211com *); 298static void urtwn_set_chan(struct urtwn_softc *, 299 struct ieee80211_channel *, 300 struct ieee80211_channel *); 301static void urtwn_iq_calib(struct urtwn_softc *); 302static void urtwn_lc_calib(struct urtwn_softc *); 303static int urtwn_init(struct urtwn_softc *); 304static void urtwn_stop(struct urtwn_softc *); 305static void urtwn_abort_xfers(struct urtwn_softc *); 306static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 307 const struct ieee80211_bpf_params *); 308static void urtwn_ms_delay(struct urtwn_softc *); 309 310/* Aliases. */ 311#define urtwn_bb_write urtwn_write_4 312#define urtwn_bb_read urtwn_read_4 313 314static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 315 [URTWN_BULK_RX] = { 316 .type = UE_BULK, 317 .endpoint = UE_ADDR_ANY, 318 .direction = UE_DIR_IN, 319 .bufsize = URTWN_RXBUFSZ, 320 .flags = { 321 .pipe_bof = 1, 322 .short_xfer_ok = 1 323 }, 324 .callback = urtwn_bulk_rx_callback, 325 }, 326 [URTWN_BULK_TX_BE] = { 327 .type = UE_BULK, 328 .endpoint = 0x03, 329 .direction = UE_DIR_OUT, 330 .bufsize = URTWN_TXBUFSZ, 331 .flags = { 332 .ext_buffer = 1, 333 .pipe_bof = 1, 334 .force_short_xfer = 1 335 }, 336 .callback = urtwn_bulk_tx_callback, 337 .timeout = URTWN_TX_TIMEOUT, /* ms */ 338 }, 339 [URTWN_BULK_TX_BK] = { 340 .type = UE_BULK, 341 .endpoint = 0x03, 342 .direction = UE_DIR_OUT, 343 .bufsize = URTWN_TXBUFSZ, 344 .flags = { 345 .ext_buffer = 1, 346 .pipe_bof = 1, 347 .force_short_xfer = 1, 348 }, 349 .callback = urtwn_bulk_tx_callback, 350 .timeout = URTWN_TX_TIMEOUT, /* ms */ 351 }, 352 [URTWN_BULK_TX_VI] = { 353 .type = UE_BULK, 354 .endpoint = 0x02, 355 .direction = UE_DIR_OUT, 356 .bufsize = URTWN_TXBUFSZ, 357 .flags = { 358 .ext_buffer = 1, 359 .pipe_bof = 1, 360 .force_short_xfer = 1 361 }, 362 .callback = urtwn_bulk_tx_callback, 363 .timeout = URTWN_TX_TIMEOUT, /* ms */ 364 }, 365 [URTWN_BULK_TX_VO] = { 366 .type = UE_BULK, 367 .endpoint = 0x02, 368 .direction = UE_DIR_OUT, 369 .bufsize = URTWN_TXBUFSZ, 370 .flags = { 371 .ext_buffer = 1, 372 .pipe_bof = 1, 373 .force_short_xfer = 1 374 }, 375 .callback = urtwn_bulk_tx_callback, 376 .timeout = URTWN_TX_TIMEOUT, /* ms */ 377 }, 378}; 379 380static const struct wme_to_queue { 381 uint16_t reg; 382 uint8_t qid; 383} wme2queue[WME_NUM_AC] = { 384 { R92C_EDCA_BE_PARAM, URTWN_BULK_TX_BE}, 385 { R92C_EDCA_BK_PARAM, URTWN_BULK_TX_BK}, 386 { R92C_EDCA_VI_PARAM, URTWN_BULK_TX_VI}, 387 { R92C_EDCA_VO_PARAM, URTWN_BULK_TX_VO} 388}; 389 390static int 391urtwn_match(device_t self) 392{ 393 struct usb_attach_arg *uaa = device_get_ivars(self); 394 395 if (uaa->usb_mode != USB_MODE_HOST) 396 return (ENXIO); 397 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 398 return (ENXIO); 399 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 400 return (ENXIO); 401 402 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 403} 404 405static int 406urtwn_attach(device_t self) 407{ 408 struct usb_attach_arg *uaa = device_get_ivars(self); 409 struct urtwn_softc *sc = device_get_softc(self); 410 struct ieee80211com *ic = &sc->sc_ic; 411 uint8_t bands; 412 int error; 413 414 device_set_usb_desc(self); 415 sc->sc_udev = uaa->device; 416 sc->sc_dev = self; 417 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 418 sc->chip |= URTWN_CHIP_88E; 419 420 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 421 MTX_NETWORK_LOCK, MTX_DEF); 422 callout_init(&sc->sc_watchdog_ch, 0); 423 mbufq_init(&sc->sc_snd, ifqmaxlen); 424 425 sc->sc_iface_index = URTWN_IFACE_INDEX; 426 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index, 427 sc->sc_xfer, urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 428 if (error) { 429 device_printf(self, "could not allocate USB transfers, " 430 "err=%s\n", usbd_errstr(error)); 431 goto detach; 432 } 433 434 URTWN_LOCK(sc); 435 436 error = urtwn_read_chipid(sc); 437 if (error) { 438 device_printf(sc->sc_dev, "unsupported test chip\n"); 439 URTWN_UNLOCK(sc); 440 goto detach; 441 } 442 443 /* Determine number of Tx/Rx chains. */ 444 if (sc->chip & URTWN_CHIP_92C) { 445 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 446 sc->nrxchains = 2; 447 } else { 448 sc->ntxchains = 1; 449 sc->nrxchains = 1; 450 } 451 452 if (sc->chip & URTWN_CHIP_88E) 453 error = urtwn_r88e_read_rom(sc); 454 else 455 error = urtwn_read_rom(sc); 456 if (error != 0) { 457 device_printf(sc->sc_dev, "%s: cannot read rom, error %d\n", 458 __func__, error); 459 URTWN_UNLOCK(sc); 460 goto detach; 461 } 462 463 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 464 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 465 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 466 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 467 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 468 "8188CUS", sc->ntxchains, sc->nrxchains); 469 470 URTWN_UNLOCK(sc); 471 472 ic->ic_softc = sc; 473 ic->ic_name = device_get_nameunit(self); 474 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 475 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 476 477 /* set device capabilities */ 478 ic->ic_caps = 479 IEEE80211_C_STA /* station mode */ 480 | IEEE80211_C_MONITOR /* monitor mode */ 481 | IEEE80211_C_IBSS /* adhoc mode */ 482 | IEEE80211_C_HOSTAP /* hostap mode */ 483 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 484 | IEEE80211_C_SHSLOT /* short slot time supported */ 485 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 486 | IEEE80211_C_WPA /* 802.11i */ 487 | IEEE80211_C_WME /* 802.11e */ 488 ; 489 490 bands = 0; 491 setbit(&bands, IEEE80211_MODE_11B); 492 setbit(&bands, IEEE80211_MODE_11G); 493 ieee80211_init_channels(ic, NULL, &bands); 494 495 ieee80211_ifattach(ic); 496 ic->ic_raw_xmit = urtwn_raw_xmit; 497 ic->ic_scan_start = urtwn_scan_start; 498 ic->ic_scan_end = urtwn_scan_end; 499 ic->ic_set_channel = urtwn_set_channel; 500 ic->ic_transmit = urtwn_transmit; 501 ic->ic_parent = urtwn_parent; 502 ic->ic_vap_create = urtwn_vap_create; 503 ic->ic_vap_delete = urtwn_vap_delete; 504 ic->ic_wme.wme_update = urtwn_wme_update; 505 ic->ic_update_promisc = urtwn_update_promisc; 506 ic->ic_update_mcast = urtwn_update_mcast; 507 508 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 509 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 510 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 511 URTWN_RX_RADIOTAP_PRESENT); 512 513 if (bootverbose) 514 ieee80211_announce(ic); 515 516 return (0); 517 518detach: 519 urtwn_detach(self); 520 return (ENXIO); /* failure */ 521} 522 523static int 524urtwn_detach(device_t self) 525{ 526 struct urtwn_softc *sc = device_get_softc(self); 527 struct ieee80211com *ic = &sc->sc_ic; 528 unsigned int x; 529 530 /* Prevent further ioctls. */ 531 URTWN_LOCK(sc); 532 sc->sc_flags |= URTWN_DETACHED; 533 URTWN_UNLOCK(sc); 534 535 urtwn_stop(sc); 536 537 callout_drain(&sc->sc_watchdog_ch); 538 539 /* stop all USB transfers */ 540 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 541 542 /* Prevent further allocations from RX/TX data lists. */ 543 URTWN_LOCK(sc); 544 STAILQ_INIT(&sc->sc_tx_active); 545 STAILQ_INIT(&sc->sc_tx_inactive); 546 STAILQ_INIT(&sc->sc_tx_pending); 547 548 STAILQ_INIT(&sc->sc_rx_active); 549 STAILQ_INIT(&sc->sc_rx_inactive); 550 URTWN_UNLOCK(sc); 551 552 /* drain USB transfers */ 553 for (x = 0; x != URTWN_N_TRANSFER; x++) 554 usbd_transfer_drain(sc->sc_xfer[x]); 555 556 /* Free data buffers. */ 557 URTWN_LOCK(sc); 558 urtwn_free_tx_list(sc); 559 urtwn_free_rx_list(sc); 560 URTWN_UNLOCK(sc); 561 562 ieee80211_ifdetach(ic); 563 mtx_destroy(&sc->sc_mtx); 564 565 return (0); 566} 567 568static void 569urtwn_drain_mbufq(struct urtwn_softc *sc) 570{ 571 struct mbuf *m; 572 struct ieee80211_node *ni; 573 URTWN_ASSERT_LOCKED(sc); 574 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 575 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 576 m->m_pkthdr.rcvif = NULL; 577 ieee80211_free_node(ni); 578 m_freem(m); 579 } 580} 581 582static usb_error_t 583urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 584 void *data) 585{ 586 usb_error_t err; 587 int ntries = 10; 588 589 URTWN_ASSERT_LOCKED(sc); 590 591 while (ntries--) { 592 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 593 req, data, 0, NULL, 250 /* ms */); 594 if (err == 0) 595 break; 596 597 DPRINTFN(1, "Control request failed, %s (retrying)\n", 598 usbd_errstr(err)); 599 usb_pause_mtx(&sc->sc_mtx, hz / 100); 600 } 601 return (err); 602} 603 604static struct ieee80211vap * 605urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 606 enum ieee80211_opmode opmode, int flags, 607 const uint8_t bssid[IEEE80211_ADDR_LEN], 608 const uint8_t mac[IEEE80211_ADDR_LEN]) 609{ 610 struct urtwn_softc *sc = ic->ic_softc; 611 struct urtwn_vap *uvp; 612 struct ieee80211vap *vap; 613 614 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 615 return (NULL); 616 617 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 618 vap = &uvp->vap; 619 /* enable s/w bmiss handling for sta mode */ 620 621 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 622 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 623 /* out of memory */ 624 free(uvp, M_80211_VAP); 625 return (NULL); 626 } 627 628 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 629 urtwn_init_beacon(sc, uvp); 630 631 /* override state transition machine */ 632 uvp->newstate = vap->iv_newstate; 633 vap->iv_newstate = urtwn_newstate; 634 vap->iv_update_beacon = urtwn_update_beacon; 635 if (opmode == IEEE80211_M_IBSS) { 636 uvp->recv_mgmt = vap->iv_recv_mgmt; 637 vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 638 TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 639 } 640 641 /* complete setup */ 642 ieee80211_vap_attach(vap, ieee80211_media_change, 643 ieee80211_media_status, mac); 644 ic->ic_opmode = opmode; 645 return (vap); 646} 647 648static void 649urtwn_vap_delete(struct ieee80211vap *vap) 650{ 651 struct ieee80211com *ic = vap->iv_ic; 652 struct urtwn_vap *uvp = URTWN_VAP(vap); 653 654 if (uvp->bcn_mbuf != NULL) 655 m_freem(uvp->bcn_mbuf); 656 if (vap->iv_opmode == IEEE80211_M_IBSS) 657 ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 658 ieee80211_vap_detach(vap); 659 free(uvp, M_80211_VAP); 660} 661 662static struct mbuf * 663urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 664{ 665 struct ieee80211com *ic = &sc->sc_ic; 666 struct ieee80211_frame *wh; 667 struct mbuf *m; 668 struct r92c_rx_stat *stat; 669 uint32_t rxdw0, rxdw3; 670 uint8_t rate; 671 int8_t rssi = 0; 672 int infosz; 673 674 /* 675 * don't pass packets to the ieee80211 framework if the driver isn't 676 * RUNNING. 677 */ 678 if (!(sc->sc_flags & URTWN_RUNNING)) 679 return (NULL); 680 681 stat = (struct r92c_rx_stat *)buf; 682 rxdw0 = le32toh(stat->rxdw0); 683 rxdw3 = le32toh(stat->rxdw3); 684 685 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 686 /* 687 * This should not happen since we setup our Rx filter 688 * to not receive these frames. 689 */ 690 counter_u64_add(ic->ic_ierrors, 1); 691 return (NULL); 692 } 693 if (pktlen < sizeof(struct ieee80211_frame_ack) || 694 pktlen > MCLBYTES) { 695 counter_u64_add(ic->ic_ierrors, 1); 696 return (NULL); 697 } 698 699 rate = MS(rxdw3, R92C_RXDW3_RATE); 700 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 701 702 /* Get RSSI from PHY status descriptor if present. */ 703 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 704 if (sc->chip & URTWN_CHIP_88E) 705 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 706 else 707 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 708 /* Update our average RSSI. */ 709 urtwn_update_avgrssi(sc, rate, rssi); 710 } 711 712 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 713 if (m == NULL) { 714 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 715 return (NULL); 716 } 717 718 /* Finalize mbuf. */ 719 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 720 memcpy(mtod(m, uint8_t *), wh, pktlen); 721 m->m_pkthdr.len = m->m_len = pktlen; 722 723 if (ieee80211_radiotap_active(ic)) { 724 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 725 726 tap->wr_flags = 0; 727 /* Map HW rate index to 802.11 rate. */ 728 if (!(rxdw3 & R92C_RXDW3_HT)) { 729 tap->wr_rate = ridx2rate[rate]; 730 } else if (rate >= 12) { /* MCS0~15. */ 731 /* Bit 7 set means HT MCS instead of rate. */ 732 tap->wr_rate = 0x80 | (rate - 12); 733 } 734 tap->wr_dbm_antsignal = rssi; 735 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 736 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 737 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 738 } 739 740 *rssi_p = rssi; 741 742 return (m); 743} 744 745static struct mbuf * 746urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 747 int8_t *nf) 748{ 749 struct urtwn_softc *sc = data->sc; 750 struct ieee80211com *ic = &sc->sc_ic; 751 struct r92c_rx_stat *stat; 752 struct mbuf *m, *m0 = NULL, *prevm = NULL; 753 uint32_t rxdw0; 754 uint8_t *buf; 755 int len, totlen, pktlen, infosz, npkts; 756 757 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 758 759 if (len < sizeof(*stat)) { 760 counter_u64_add(ic->ic_ierrors, 1); 761 return (NULL); 762 } 763 764 buf = data->buf; 765 /* Get the number of encapsulated frames. */ 766 stat = (struct r92c_rx_stat *)buf; 767 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 768 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 769 770 /* Process all of them. */ 771 while (npkts-- > 0) { 772 if (len < sizeof(*stat)) 773 break; 774 stat = (struct r92c_rx_stat *)buf; 775 rxdw0 = le32toh(stat->rxdw0); 776 777 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 778 if (pktlen == 0) 779 break; 780 781 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 782 783 /* Make sure everything fits in xfer. */ 784 totlen = sizeof(*stat) + infosz + pktlen; 785 if (totlen > len) 786 break; 787 788 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 789 if (m0 == NULL) 790 m0 = m; 791 if (prevm == NULL) 792 prevm = m; 793 else { 794 prevm->m_next = m; 795 prevm = m; 796 } 797 798 /* Next chunk is 128-byte aligned. */ 799 totlen = (totlen + 127) & ~127; 800 buf += totlen; 801 len -= totlen; 802 } 803 804 return (m0); 805} 806 807static void 808urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 809{ 810 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 811 struct ieee80211com *ic = &sc->sc_ic; 812 struct ieee80211_frame_min *wh; 813 struct ieee80211_node *ni; 814 struct mbuf *m = NULL, *next; 815 struct urtwn_data *data; 816 int8_t nf; 817 int rssi = 1; 818 819 URTWN_ASSERT_LOCKED(sc); 820 821 switch (USB_GET_STATE(xfer)) { 822 case USB_ST_TRANSFERRED: 823 data = STAILQ_FIRST(&sc->sc_rx_active); 824 if (data == NULL) 825 goto tr_setup; 826 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 827 m = urtwn_rxeof(xfer, data, &rssi, &nf); 828 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 829 /* FALLTHROUGH */ 830 case USB_ST_SETUP: 831tr_setup: 832 data = STAILQ_FIRST(&sc->sc_rx_inactive); 833 if (data == NULL) { 834 KASSERT(m == NULL, ("mbuf isn't NULL")); 835 return; 836 } 837 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 838 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 839 usbd_xfer_set_frame_data(xfer, 0, data->buf, 840 usbd_xfer_max_len(xfer)); 841 usbd_transfer_submit(xfer); 842 843 /* 844 * To avoid LOR we should unlock our private mutex here to call 845 * ieee80211_input() because here is at the end of a USB 846 * callback and safe to unlock. 847 */ 848 URTWN_UNLOCK(sc); 849 while (m != NULL) { 850 next = m->m_next; 851 m->m_next = NULL; 852 wh = mtod(m, struct ieee80211_frame_min *); 853 if (m->m_len >= sizeof(*wh)) 854 ni = ieee80211_find_rxnode(ic, wh); 855 else 856 ni = NULL; 857 nf = URTWN_NOISE_FLOOR; 858 if (ni != NULL) { 859 (void)ieee80211_input(ni, m, rssi - nf, nf); 860 ieee80211_free_node(ni); 861 } else { 862 (void)ieee80211_input_all(ic, m, rssi - nf, 863 nf); 864 } 865 m = next; 866 } 867 URTWN_LOCK(sc); 868 break; 869 default: 870 /* needs it to the inactive queue due to a error. */ 871 data = STAILQ_FIRST(&sc->sc_rx_active); 872 if (data != NULL) { 873 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 874 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 875 } 876 if (error != USB_ERR_CANCELLED) { 877 usbd_xfer_set_stall(xfer); 878 counter_u64_add(ic->ic_ierrors, 1); 879 goto tr_setup; 880 } 881 break; 882 } 883} 884 885static void 886urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 887{ 888 889 URTWN_ASSERT_LOCKED(sc); 890 891 if (data->ni != NULL) /* not a beacon frame */ 892 ieee80211_tx_complete(data->ni, data->m, status); 893 894 data->ni = NULL; 895 data->m = NULL; 896 897 sc->sc_txtimer = 0; 898 899 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 900} 901 902static int 903urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 904 int ndata, int maxsz) 905{ 906 int i, error; 907 908 for (i = 0; i < ndata; i++) { 909 struct urtwn_data *dp = &data[i]; 910 dp->sc = sc; 911 dp->m = NULL; 912 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 913 if (dp->buf == NULL) { 914 device_printf(sc->sc_dev, 915 "could not allocate buffer\n"); 916 error = ENOMEM; 917 goto fail; 918 } 919 dp->ni = NULL; 920 } 921 922 return (0); 923fail: 924 urtwn_free_list(sc, data, ndata); 925 return (error); 926} 927 928static int 929urtwn_alloc_rx_list(struct urtwn_softc *sc) 930{ 931 int error, i; 932 933 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 934 URTWN_RXBUFSZ); 935 if (error != 0) 936 return (error); 937 938 STAILQ_INIT(&sc->sc_rx_active); 939 STAILQ_INIT(&sc->sc_rx_inactive); 940 941 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 942 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 943 944 return (0); 945} 946 947static int 948urtwn_alloc_tx_list(struct urtwn_softc *sc) 949{ 950 int error, i; 951 952 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 953 URTWN_TXBUFSZ); 954 if (error != 0) 955 return (error); 956 957 STAILQ_INIT(&sc->sc_tx_active); 958 STAILQ_INIT(&sc->sc_tx_inactive); 959 STAILQ_INIT(&sc->sc_tx_pending); 960 961 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 962 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 963 964 return (0); 965} 966 967static void 968urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 969{ 970 int i; 971 972 for (i = 0; i < ndata; i++) { 973 struct urtwn_data *dp = &data[i]; 974 975 if (dp->buf != NULL) { 976 free(dp->buf, M_USBDEV); 977 dp->buf = NULL; 978 } 979 if (dp->ni != NULL) { 980 ieee80211_free_node(dp->ni); 981 dp->ni = NULL; 982 } 983 } 984} 985 986static void 987urtwn_free_rx_list(struct urtwn_softc *sc) 988{ 989 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 990} 991 992static void 993urtwn_free_tx_list(struct urtwn_softc *sc) 994{ 995 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 996} 997 998static void 999urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 1000{ 1001 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 1002 struct urtwn_data *data; 1003 1004 URTWN_ASSERT_LOCKED(sc); 1005 1006 switch (USB_GET_STATE(xfer)){ 1007 case USB_ST_TRANSFERRED: 1008 data = STAILQ_FIRST(&sc->sc_tx_active); 1009 if (data == NULL) 1010 goto tr_setup; 1011 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1012 urtwn_txeof(sc, data, 0); 1013 /* FALLTHROUGH */ 1014 case USB_ST_SETUP: 1015tr_setup: 1016 data = STAILQ_FIRST(&sc->sc_tx_pending); 1017 if (data == NULL) { 1018 DPRINTF("%s: empty pending queue\n", __func__); 1019 goto finish; 1020 } 1021 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 1022 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 1023 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1024 usbd_transfer_submit(xfer); 1025 break; 1026 default: 1027 data = STAILQ_FIRST(&sc->sc_tx_active); 1028 if (data == NULL) 1029 goto tr_setup; 1030 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1031 urtwn_txeof(sc, data, 1); 1032 if (error != USB_ERR_CANCELLED) { 1033 usbd_xfer_set_stall(xfer); 1034 goto tr_setup; 1035 } 1036 break; 1037 } 1038finish: 1039 /* Kick-start more transmit */ 1040 urtwn_start(sc); 1041} 1042 1043static struct urtwn_data * 1044_urtwn_getbuf(struct urtwn_softc *sc) 1045{ 1046 struct urtwn_data *bf; 1047 1048 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1049 if (bf != NULL) 1050 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1051 else 1052 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 1053 return (bf); 1054} 1055 1056static struct urtwn_data * 1057urtwn_getbuf(struct urtwn_softc *sc) 1058{ 1059 struct urtwn_data *bf; 1060 1061 URTWN_ASSERT_LOCKED(sc); 1062 1063 bf = _urtwn_getbuf(sc); 1064 if (bf == NULL) 1065 DPRINTF("%s: stop queue\n", __func__); 1066 return (bf); 1067} 1068 1069static usb_error_t 1070urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1071 int len) 1072{ 1073 usb_device_request_t req; 1074 1075 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1076 req.bRequest = R92C_REQ_REGS; 1077 USETW(req.wValue, addr); 1078 USETW(req.wIndex, 0); 1079 USETW(req.wLength, len); 1080 return (urtwn_do_request(sc, &req, buf)); 1081} 1082 1083static usb_error_t 1084urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1085{ 1086 return (urtwn_write_region_1(sc, addr, &val, sizeof(val))); 1087} 1088 1089static usb_error_t 1090urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1091{ 1092 val = htole16(val); 1093 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1094} 1095 1096static usb_error_t 1097urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1098{ 1099 val = htole32(val); 1100 return (urtwn_write_region_1(sc, addr, (uint8_t *)&val, sizeof(val))); 1101} 1102 1103static usb_error_t 1104urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1105 int len) 1106{ 1107 usb_device_request_t req; 1108 1109 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1110 req.bRequest = R92C_REQ_REGS; 1111 USETW(req.wValue, addr); 1112 USETW(req.wIndex, 0); 1113 USETW(req.wLength, len); 1114 return (urtwn_do_request(sc, &req, buf)); 1115} 1116 1117static uint8_t 1118urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1119{ 1120 uint8_t val; 1121 1122 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1123 return (0xff); 1124 return (val); 1125} 1126 1127static uint16_t 1128urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1129{ 1130 uint16_t val; 1131 1132 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1133 return (0xffff); 1134 return (le16toh(val)); 1135} 1136 1137static uint32_t 1138urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1139{ 1140 uint32_t val; 1141 1142 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1143 return (0xffffffff); 1144 return (le32toh(val)); 1145} 1146 1147static int 1148urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1149{ 1150 struct r92c_fw_cmd cmd; 1151 usb_error_t error; 1152 int ntries; 1153 1154 /* Wait for current FW box to be empty. */ 1155 for (ntries = 0; ntries < 100; ntries++) { 1156 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1157 break; 1158 urtwn_ms_delay(sc); 1159 } 1160 if (ntries == 100) { 1161 device_printf(sc->sc_dev, 1162 "could not send firmware command\n"); 1163 return (ETIMEDOUT); 1164 } 1165 memset(&cmd, 0, sizeof(cmd)); 1166 cmd.id = id; 1167 if (len > 3) 1168 cmd.id |= R92C_CMD_FLAG_EXT; 1169 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1170 memcpy(cmd.msg, buf, len); 1171 1172 /* Write the first word last since that will trigger the FW. */ 1173 error = urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1174 (uint8_t *)&cmd + 4, 2); 1175 if (error != USB_ERR_NORMAL_COMPLETION) 1176 return (EIO); 1177 error = urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1178 (uint8_t *)&cmd + 0, 4); 1179 if (error != USB_ERR_NORMAL_COMPLETION) 1180 return (EIO); 1181 1182 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1183 return (0); 1184} 1185 1186static __inline void 1187urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1188{ 1189 1190 sc->sc_rf_write(sc, chain, addr, val); 1191} 1192 1193static void 1194urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1195 uint32_t val) 1196{ 1197 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1198 SM(R92C_LSSI_PARAM_ADDR, addr) | 1199 SM(R92C_LSSI_PARAM_DATA, val)); 1200} 1201 1202static void 1203urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1204uint32_t val) 1205{ 1206 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1207 SM(R88E_LSSI_PARAM_ADDR, addr) | 1208 SM(R92C_LSSI_PARAM_DATA, val)); 1209} 1210 1211static uint32_t 1212urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1213{ 1214 uint32_t reg[R92C_MAX_CHAINS], val; 1215 1216 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1217 if (chain != 0) 1218 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1219 1220 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1221 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1222 urtwn_ms_delay(sc); 1223 1224 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1225 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1226 R92C_HSSI_PARAM2_READ_EDGE); 1227 urtwn_ms_delay(sc); 1228 1229 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1230 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1231 urtwn_ms_delay(sc); 1232 1233 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1234 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1235 else 1236 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1237 return (MS(val, R92C_LSSI_READBACK_DATA)); 1238} 1239 1240static int 1241urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1242{ 1243 usb_error_t error; 1244 int ntries; 1245 1246 error = urtwn_write_4(sc, R92C_LLT_INIT, 1247 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1248 SM(R92C_LLT_INIT_ADDR, addr) | 1249 SM(R92C_LLT_INIT_DATA, data)); 1250 if (error != USB_ERR_NORMAL_COMPLETION) 1251 return (EIO); 1252 /* Wait for write operation to complete. */ 1253 for (ntries = 0; ntries < 20; ntries++) { 1254 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1255 R92C_LLT_INIT_OP_NO_ACTIVE) 1256 return (0); 1257 urtwn_ms_delay(sc); 1258 } 1259 return (ETIMEDOUT); 1260} 1261 1262static int 1263urtwn_efuse_read_next(struct urtwn_softc *sc, uint8_t *val) 1264{ 1265 uint32_t reg; 1266 usb_error_t error; 1267 int ntries; 1268 1269 if (sc->last_rom_addr >= URTWN_EFUSE_MAX_LEN) 1270 return (EFAULT); 1271 1272 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1273 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->last_rom_addr); 1274 reg &= ~R92C_EFUSE_CTRL_VALID; 1275 1276 error = urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1277 if (error != USB_ERR_NORMAL_COMPLETION) 1278 return (EIO); 1279 /* Wait for read operation to complete. */ 1280 for (ntries = 0; ntries < 100; ntries++) { 1281 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1282 if (reg & R92C_EFUSE_CTRL_VALID) 1283 break; 1284 urtwn_ms_delay(sc); 1285 } 1286 if (ntries == 100) { 1287 device_printf(sc->sc_dev, 1288 "could not read efuse byte at address 0x%x\n", 1289 sc->last_rom_addr); 1290 return (ETIMEDOUT); 1291 } 1292 1293 *val = MS(reg, R92C_EFUSE_CTRL_DATA); 1294 sc->last_rom_addr++; 1295 1296 return (0); 1297} 1298 1299static int 1300urtwn_efuse_read_data(struct urtwn_softc *sc, uint8_t *rom, uint8_t off, 1301 uint8_t msk) 1302{ 1303 uint8_t reg; 1304 int i, error; 1305 1306 for (i = 0; i < 4; i++) { 1307 if (msk & (1 << i)) 1308 continue; 1309 error = urtwn_efuse_read_next(sc, ®); 1310 if (error != 0) 1311 return (error); 1312 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2, reg); 1313 rom[off * 8 + i * 2 + 0] = reg; 1314 1315 error = urtwn_efuse_read_next(sc, ®); 1316 if (error != 0) 1317 return (error); 1318 DPRINTF("rom[0x%03X] == 0x%02X\n", off * 8 + i * 2 + 1, reg); 1319 rom[off * 8 + i * 2 + 1] = reg; 1320 } 1321 1322 return (0); 1323} 1324 1325#ifdef URTWN_DEBUG 1326static void 1327urtwn_dump_rom_contents(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1328{ 1329 int i; 1330 1331 /* Dump ROM contents. */ 1332 device_printf(sc->sc_dev, "%s:", __func__); 1333 for (i = 0; i < size; i++) { 1334 if (i % 32 == 0) 1335 printf("\n%03X: ", i); 1336 else if (i % 4 == 0) 1337 printf(" "); 1338 1339 printf("%02X", rom[i]); 1340 } 1341 printf("\n"); 1342} 1343#endif 1344 1345static int 1346urtwn_efuse_read(struct urtwn_softc *sc, uint8_t *rom, uint16_t size) 1347{ 1348#define URTWN_CHK(res) do { \ 1349 if ((error = res) != 0) \ 1350 goto end; \ 1351} while(0) 1352 uint8_t msk, off, reg; 1353 int error; 1354 1355 URTWN_CHK(urtwn_efuse_switch_power(sc)); 1356 1357 /* Read full ROM image. */ 1358 sc->last_rom_addr = 0; 1359 memset(rom, 0xff, size); 1360 1361 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1362 while (reg != 0xff) { 1363 /* check for extended header */ 1364 if ((sc->chip & URTWN_CHIP_88E) && (reg & 0x1f) == 0x0f) { 1365 off = reg >> 5; 1366 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1367 1368 if ((reg & 0x0f) != 0x0f) 1369 off = ((reg & 0xf0) >> 1) | off; 1370 else 1371 continue; 1372 } else 1373 off = reg >> 4; 1374 msk = reg & 0xf; 1375 1376 URTWN_CHK(urtwn_efuse_read_data(sc, rom, off, msk)); 1377 URTWN_CHK(urtwn_efuse_read_next(sc, ®)); 1378 } 1379 1380end: 1381 1382#ifdef URTWN_DEBUG 1383 if (urtwn_debug >= 2) 1384 urtwn_dump_rom_contents(sc, rom, size); 1385#endif 1386 1387 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1388 1389 if (error != 0) { 1390 device_printf(sc->sc_dev, "%s: error while reading ROM\n", 1391 __func__); 1392 } 1393 1394 return (error); 1395#undef URTWN_CHK 1396} 1397 1398static int 1399urtwn_efuse_switch_power(struct urtwn_softc *sc) 1400{ 1401 usb_error_t error; 1402 uint32_t reg; 1403 1404 error = urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1405 if (error != USB_ERR_NORMAL_COMPLETION) 1406 return (EIO); 1407 1408 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1409 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1410 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1411 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1412 if (error != USB_ERR_NORMAL_COMPLETION) 1413 return (EIO); 1414 } 1415 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1416 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1417 error = urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1418 reg | R92C_SYS_FUNC_EN_ELDR); 1419 if (error != USB_ERR_NORMAL_COMPLETION) 1420 return (EIO); 1421 } 1422 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1423 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1424 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1425 error = urtwn_write_2(sc, R92C_SYS_CLKR, 1426 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1427 if (error != USB_ERR_NORMAL_COMPLETION) 1428 return (EIO); 1429 } 1430 1431 return (0); 1432} 1433 1434static int 1435urtwn_read_chipid(struct urtwn_softc *sc) 1436{ 1437 uint32_t reg; 1438 1439 if (sc->chip & URTWN_CHIP_88E) 1440 return (0); 1441 1442 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1443 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1444 return (EIO); 1445 1446 if (reg & R92C_SYS_CFG_TYPE_92C) { 1447 sc->chip |= URTWN_CHIP_92C; 1448 /* Check if it is a castrated 8192C. */ 1449 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1450 R92C_HPON_FSM_CHIP_BONDING_ID) == 1451 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1452 sc->chip |= URTWN_CHIP_92C_1T2R; 1453 } 1454 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1455 sc->chip |= URTWN_CHIP_UMC; 1456 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1457 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1458 } 1459 return (0); 1460} 1461 1462static int 1463urtwn_read_rom(struct urtwn_softc *sc) 1464{ 1465 struct r92c_rom *rom = &sc->rom.r92c_rom; 1466 int error; 1467 1468 /* Read full ROM image. */ 1469 error = urtwn_efuse_read(sc, (uint8_t *)rom, sizeof(*rom)); 1470 if (error != 0) 1471 return (error); 1472 1473 /* XXX Weird but this is what the vendor driver does. */ 1474 sc->last_rom_addr = 0x1fa; 1475 error = urtwn_efuse_read_next(sc, &sc->pa_setting); 1476 if (error != 0) 1477 return (error); 1478 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1479 1480 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1481 1482 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1483 DPRINTF("regulatory type=%d\n", sc->regulatory); 1484 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1485 1486 sc->sc_rf_write = urtwn_r92c_rf_write; 1487 sc->sc_power_on = urtwn_r92c_power_on; 1488 1489 return (0); 1490} 1491 1492static int 1493urtwn_r88e_read_rom(struct urtwn_softc *sc) 1494{ 1495 uint8_t *rom = sc->rom.r88e_rom; 1496 uint16_t addr; 1497 int error, i; 1498 1499 error = urtwn_efuse_read(sc, rom, sizeof(sc->rom.r88e_rom)); 1500 if (error != 0) 1501 return (error); 1502 1503 addr = 0x10; 1504 for (i = 0; i < 6; i++) 1505 sc->cck_tx_pwr[i] = rom[addr++]; 1506 for (i = 0; i < 5; i++) 1507 sc->ht40_tx_pwr[i] = rom[addr++]; 1508 sc->bw20_tx_pwr_diff = (rom[addr] & 0xf0) >> 4; 1509 if (sc->bw20_tx_pwr_diff & 0x08) 1510 sc->bw20_tx_pwr_diff |= 0xf0; 1511 sc->ofdm_tx_pwr_diff = (rom[addr] & 0xf); 1512 if (sc->ofdm_tx_pwr_diff & 0x08) 1513 sc->ofdm_tx_pwr_diff |= 0xf0; 1514 sc->regulatory = MS(rom[0xc1], R92C_ROM_RF1_REGULATORY); 1515 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &rom[0xd7]); 1516 1517 sc->sc_rf_write = urtwn_r88e_rf_write; 1518 sc->sc_power_on = urtwn_r88e_power_on; 1519 1520 return (0); 1521} 1522 1523/* 1524 * Initialize rate adaptation in firmware. 1525 */ 1526static int 1527urtwn_ra_init(struct urtwn_softc *sc) 1528{ 1529 struct ieee80211com *ic = &sc->sc_ic; 1530 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1531 struct ieee80211_node *ni; 1532 struct ieee80211_rateset *rs; 1533 struct r92c_fw_cmd_macid_cfg cmd; 1534 uint32_t rates, basicrates; 1535 uint8_t mode; 1536 int maxrate, maxbasicrate, error, i, j; 1537 1538 ni = ieee80211_ref_node(vap->iv_bss); 1539 rs = &ni->ni_rates; 1540 1541 /* Get normal and basic rates mask. */ 1542 rates = basicrates = 0; 1543 maxrate = maxbasicrate = 0; 1544 for (i = 0; i < rs->rs_nrates; i++) { 1545 /* Convert 802.11 rate to HW rate index. */ 1546 for (j = 0; j < nitems(ridx2rate); j++) 1547 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1548 ridx2rate[j]) 1549 break; 1550 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1551 continue; 1552 rates |= 1 << j; 1553 if (j > maxrate) 1554 maxrate = j; 1555 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1556 basicrates |= 1 << j; 1557 if (j > maxbasicrate) 1558 maxbasicrate = j; 1559 } 1560 } 1561 if (ic->ic_curmode == IEEE80211_MODE_11B) 1562 mode = R92C_RAID_11B; 1563 else 1564 mode = R92C_RAID_11BG; 1565 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1566 mode, rates, basicrates); 1567 1568 /* Set rates mask for group addressed frames. */ 1569 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1570 cmd.mask = htole32(mode << 28 | basicrates); 1571 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1572 if (error != 0) { 1573 ieee80211_free_node(ni); 1574 device_printf(sc->sc_dev, 1575 "could not add broadcast station\n"); 1576 return (error); 1577 } 1578 /* Set initial MRR rate. */ 1579 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1580 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1581 maxbasicrate); 1582 1583 /* Set rates mask for unicast frames. */ 1584 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1585 cmd.mask = htole32(mode << 28 | rates); 1586 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1587 if (error != 0) { 1588 ieee80211_free_node(ni); 1589 device_printf(sc->sc_dev, "could not add BSS station\n"); 1590 return (error); 1591 } 1592 /* Set initial MRR rate. */ 1593 DPRINTF("maxrate=%d\n", maxrate); 1594 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1595 maxrate); 1596 1597 /* Indicate highest supported rate. */ 1598 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1599 ieee80211_free_node(ni); 1600 1601 return (0); 1602} 1603 1604static void 1605urtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1606{ 1607 struct r92c_tx_desc *txd = &uvp->bcn_desc; 1608 1609 txd->txdw0 = htole32( 1610 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 1611 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1612 txd->txdw1 = htole32( 1613 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 1614 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1615 1616 if (sc->chip & URTWN_CHIP_88E) { 1617 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 1618 txd->txdseq |= htole16(R88E_TXDSEQ_HWSEQ_EN); 1619 } else { 1620 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 1621 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 1622 } 1623 1624 txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 1625 txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 1626} 1627 1628static int 1629urtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 1630{ 1631 struct ieee80211vap *vap = ni->ni_vap; 1632 struct urtwn_vap *uvp = URTWN_VAP(vap); 1633 struct mbuf *m; 1634 int error; 1635 1636 URTWN_ASSERT_LOCKED(sc); 1637 1638 if (ni->ni_chan == IEEE80211_CHAN_ANYC) 1639 return (EINVAL); 1640 1641 m = ieee80211_beacon_alloc(ni); 1642 if (m == NULL) { 1643 device_printf(sc->sc_dev, 1644 "%s: could not allocate beacon frame\n", __func__); 1645 return (ENOMEM); 1646 } 1647 1648 if (uvp->bcn_mbuf != NULL) 1649 m_freem(uvp->bcn_mbuf); 1650 1651 uvp->bcn_mbuf = m; 1652 1653 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1654 return (error); 1655 1656 /* XXX bcnq stuck workaround */ 1657 if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1658 return (error); 1659 1660 return (0); 1661} 1662 1663static void 1664urtwn_update_beacon(struct ieee80211vap *vap, int item) 1665{ 1666 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1667 struct urtwn_vap *uvp = URTWN_VAP(vap); 1668 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 1669 struct ieee80211_node *ni = vap->iv_bss; 1670 int mcast = 0; 1671 1672 URTWN_LOCK(sc); 1673 if (uvp->bcn_mbuf == NULL) { 1674 uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 1675 if (uvp->bcn_mbuf == NULL) { 1676 device_printf(sc->sc_dev, 1677 "%s: could not allocate beacon frame\n", __func__); 1678 URTWN_UNLOCK(sc); 1679 return; 1680 } 1681 } 1682 URTWN_UNLOCK(sc); 1683 1684 if (item == IEEE80211_BEACON_TIM) 1685 mcast = 1; /* XXX */ 1686 1687 setbit(bo->bo_flags, item); 1688 ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 1689 1690 URTWN_LOCK(sc); 1691 urtwn_tx_beacon(sc, uvp); 1692 URTWN_UNLOCK(sc); 1693} 1694 1695/* 1696 * Push a beacon frame into the chip. Beacon will 1697 * be repeated by the chip every R92C_BCN_INTERVAL. 1698 */ 1699static int 1700urtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1701{ 1702 struct r92c_tx_desc *desc = &uvp->bcn_desc; 1703 struct urtwn_data *bf; 1704 1705 URTWN_ASSERT_LOCKED(sc); 1706 1707 bf = urtwn_getbuf(sc); 1708 if (bf == NULL) 1709 return (ENOMEM); 1710 1711 memcpy(bf->buf, desc, sizeof(*desc)); 1712 urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 1713 1714 sc->sc_txtimer = 5; 1715 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1716 1717 return (0); 1718} 1719 1720static void 1721urtwn_tsf_task_adhoc(void *arg, int pending) 1722{ 1723 struct ieee80211vap *vap = arg; 1724 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1725 struct ieee80211_node *ni; 1726 uint32_t reg; 1727 1728 URTWN_LOCK(sc); 1729 ni = ieee80211_ref_node(vap->iv_bss); 1730 reg = urtwn_read_1(sc, R92C_BCN_CTRL); 1731 1732 /* Accept beacons with the same BSSID. */ 1733 urtwn_set_rx_bssid_all(sc, 0); 1734 1735 /* Enable synchronization. */ 1736 reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 1737 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1738 1739 /* Synchronize. */ 1740 usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 1741 1742 /* Disable synchronization. */ 1743 reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 1744 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1745 1746 /* Remove beacon filter. */ 1747 urtwn_set_rx_bssid_all(sc, 1); 1748 1749 /* Enable beaconing. */ 1750 urtwn_write_1(sc, R92C_MBID_NUM, 1751 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 1752 reg |= R92C_BCN_CTRL_EN_BCN; 1753 1754 urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1755 ieee80211_free_node(ni); 1756 URTWN_UNLOCK(sc); 1757} 1758 1759static void 1760urtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 1761{ 1762 struct ieee80211com *ic = &sc->sc_ic; 1763 struct urtwn_vap *uvp = URTWN_VAP(vap); 1764 1765 /* Reset TSF. */ 1766 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 1767 1768 switch (vap->iv_opmode) { 1769 case IEEE80211_M_STA: 1770 /* Enable TSF synchronization. */ 1771 urtwn_write_1(sc, R92C_BCN_CTRL, 1772 urtwn_read_1(sc, R92C_BCN_CTRL) & 1773 ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1774 break; 1775 case IEEE80211_M_IBSS: 1776 ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 1777 break; 1778 case IEEE80211_M_HOSTAP: 1779 /* Enable beaconing. */ 1780 urtwn_write_1(sc, R92C_MBID_NUM, 1781 urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 1782 urtwn_write_1(sc, R92C_BCN_CTRL, 1783 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1784 break; 1785 default: 1786 device_printf(sc->sc_dev, "undefined opmode %d\n", 1787 vap->iv_opmode); 1788 return; 1789 } 1790} 1791 1792static void 1793urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1794{ 1795 uint8_t reg; 1796 1797 if (led == URTWN_LED_LINK) { 1798 if (sc->chip & URTWN_CHIP_88E) { 1799 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1800 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1801 if (!on) { 1802 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1803 urtwn_write_1(sc, R92C_LEDCFG2, 1804 reg | R92C_LEDCFG0_DIS); 1805 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1806 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1807 0xfe); 1808 } 1809 } else { 1810 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1811 if (!on) 1812 reg |= R92C_LEDCFG0_DIS; 1813 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1814 } 1815 sc->ledlink = on; /* Save LED state. */ 1816 } 1817} 1818 1819static void 1820urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 1821{ 1822 uint8_t reg; 1823 1824 reg = urtwn_read_1(sc, R92C_MSR); 1825 reg = (reg & ~R92C_MSR_MASK) | mode; 1826 urtwn_write_1(sc, R92C_MSR, reg); 1827} 1828 1829static void 1830urtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 1831 const struct ieee80211_rx_stats *rxs, 1832 int rssi, int nf) 1833{ 1834 struct ieee80211vap *vap = ni->ni_vap; 1835 struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1836 struct urtwn_vap *uvp = URTWN_VAP(vap); 1837 uint64_t ni_tstamp, curr_tstamp; 1838 1839 uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 1840 1841 if (vap->iv_state == IEEE80211_S_RUN && 1842 (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 1843 subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 1844 ni_tstamp = le64toh(ni->ni_tstamp.tsf); 1845#ifdef D3831 1846 URTWN_LOCK(sc); 1847 urtwn_get_tsf(sc, &curr_tstamp); 1848 URTWN_UNLOCK(sc); 1849 curr_tstamp = le64toh(curr_tstamp); 1850 1851 if (ni_tstamp >= curr_tstamp) 1852 (void) ieee80211_ibss_merge(ni); 1853#else 1854 (void) sc; 1855 (void) curr_tstamp; 1856#endif 1857 } 1858} 1859 1860static int 1861urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1862{ 1863 struct urtwn_vap *uvp = URTWN_VAP(vap); 1864 struct ieee80211com *ic = vap->iv_ic; 1865 struct urtwn_softc *sc = ic->ic_softc; 1866 struct ieee80211_node *ni; 1867 enum ieee80211_state ostate; 1868 uint32_t reg; 1869 uint8_t mode; 1870 int error = 0; 1871 1872 ostate = vap->iv_state; 1873 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1874 ieee80211_state_name[nstate]); 1875 1876 IEEE80211_UNLOCK(ic); 1877 URTWN_LOCK(sc); 1878 callout_stop(&sc->sc_watchdog_ch); 1879 1880 if (ostate == IEEE80211_S_RUN) { 1881 /* Turn link LED off. */ 1882 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1883 1884 /* Set media status to 'No Link'. */ 1885 urtwn_set_mode(sc, R92C_MSR_NOLINK); 1886 1887 /* Stop Rx of data frames. */ 1888 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1889 1890 /* Disable TSF synchronization. */ 1891 urtwn_write_1(sc, R92C_BCN_CTRL, 1892 (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 1893 R92C_BCN_CTRL_DIS_TSF_UDT0); 1894 1895 /* Disable beaconing. */ 1896 urtwn_write_1(sc, R92C_MBID_NUM, 1897 urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 1898 1899 /* Reset TSF. */ 1900 urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 1901 1902 /* Reset EDCA parameters. */ 1903 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1904 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1905 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1906 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1907 } 1908 1909 switch (nstate) { 1910 case IEEE80211_S_INIT: 1911 /* Turn link LED off. */ 1912 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1913 break; 1914 case IEEE80211_S_SCAN: 1915 /* Pause AC Tx queues. */ 1916 urtwn_write_1(sc, R92C_TXPAUSE, 1917 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1918 break; 1919 case IEEE80211_S_AUTH: 1920 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1921 break; 1922 case IEEE80211_S_RUN: 1923 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1924 /* Turn link LED on. */ 1925 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1926 break; 1927 } 1928 1929 ni = ieee80211_ref_node(vap->iv_bss); 1930 1931 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 1932 ni->ni_chan == IEEE80211_CHAN_ANYC) { 1933 device_printf(sc->sc_dev, 1934 "%s: could not move to RUN state\n", __func__); 1935 error = EINVAL; 1936 goto end_run; 1937 } 1938 1939 switch (vap->iv_opmode) { 1940 case IEEE80211_M_STA: 1941 mode = R92C_MSR_INFRA; 1942 break; 1943 case IEEE80211_M_IBSS: 1944 mode = R92C_MSR_ADHOC; 1945 break; 1946 case IEEE80211_M_HOSTAP: 1947 mode = R92C_MSR_AP; 1948 break; 1949 default: 1950 device_printf(sc->sc_dev, "undefined opmode %d\n", 1951 vap->iv_opmode); 1952 error = EINVAL; 1953 goto end_run; 1954 } 1955 1956 /* Set media status to 'Associated'. */ 1957 urtwn_set_mode(sc, mode); 1958 1959 /* Set BSSID. */ 1960 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1961 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1962 1963 if (ic->ic_curmode == IEEE80211_MODE_11B) 1964 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1965 else /* 802.11b/g */ 1966 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1967 1968 /* Enable Rx of data frames. */ 1969 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1970 1971 /* Flush all AC queues. */ 1972 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1973 1974 /* Set beacon interval. */ 1975 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1976 1977 /* Allow Rx from our BSSID only. */ 1978 if (ic->ic_promisc == 0) { 1979 reg = urtwn_read_4(sc, R92C_RCR); 1980 1981 if (vap->iv_opmode != IEEE80211_M_HOSTAP) 1982 reg |= R92C_RCR_CBSSID_DATA; 1983 if (vap->iv_opmode != IEEE80211_M_IBSS) 1984 reg |= R92C_RCR_CBSSID_BCN; 1985 1986 urtwn_write_4(sc, R92C_RCR, reg); 1987 } 1988 1989 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1990 vap->iv_opmode == IEEE80211_M_IBSS) { 1991 error = urtwn_setup_beacon(sc, ni); 1992 if (error != 0) { 1993 device_printf(sc->sc_dev, 1994 "unable to push beacon into the chip, " 1995 "error %d\n", error); 1996 goto end_run; 1997 } 1998 } 1999 2000 /* Enable TSF synchronization. */ 2001 urtwn_tsf_sync_enable(sc, vap); 2002 2003 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 2004 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 2005 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 2006 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 2007 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 2008 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 2009 2010 /* Intialize rate adaptation. */ 2011 if (sc->chip & URTWN_CHIP_88E) 2012 ni->ni_txrate = 2013 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 2014 else 2015 urtwn_ra_init(sc); 2016 /* Turn link LED on. */ 2017 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2018 2019 sc->avg_pwdb = -1; /* Reset average RSSI. */ 2020 /* Reset temperature calibration state machine. */ 2021 sc->thcal_state = 0; 2022 sc->thcal_lctemp = 0; 2023 2024end_run: 2025 ieee80211_free_node(ni); 2026 break; 2027 default: 2028 break; 2029 } 2030 2031 URTWN_UNLOCK(sc); 2032 IEEE80211_LOCK(ic); 2033 return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 2034} 2035 2036static void 2037urtwn_watchdog(void *arg) 2038{ 2039 struct urtwn_softc *sc = arg; 2040 2041 if (sc->sc_txtimer > 0) { 2042 if (--sc->sc_txtimer == 0) { 2043 device_printf(sc->sc_dev, "device timeout\n"); 2044 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2045 return; 2046 } 2047 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2048 } 2049} 2050 2051static void 2052urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2053{ 2054 int pwdb; 2055 2056 /* Convert antenna signal to percentage. */ 2057 if (rssi <= -100 || rssi >= 20) 2058 pwdb = 0; 2059 else if (rssi >= 0) 2060 pwdb = 100; 2061 else 2062 pwdb = 100 + rssi; 2063 if (!(sc->chip & URTWN_CHIP_88E)) { 2064 if (rate <= URTWN_RIDX_CCK11) { 2065 /* CCK gain is smaller than OFDM/MCS gain. */ 2066 pwdb += 6; 2067 if (pwdb > 100) 2068 pwdb = 100; 2069 if (pwdb <= 14) 2070 pwdb -= 4; 2071 else if (pwdb <= 26) 2072 pwdb -= 8; 2073 else if (pwdb <= 34) 2074 pwdb -= 6; 2075 else if (pwdb <= 42) 2076 pwdb -= 2; 2077 } 2078 } 2079 if (sc->avg_pwdb == -1) /* Init. */ 2080 sc->avg_pwdb = pwdb; 2081 else if (sc->avg_pwdb < pwdb) 2082 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2083 else 2084 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2085 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 2086} 2087 2088static int8_t 2089urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2090{ 2091 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2092 struct r92c_rx_phystat *phy; 2093 struct r92c_rx_cck *cck; 2094 uint8_t rpt; 2095 int8_t rssi; 2096 2097 if (rate <= URTWN_RIDX_CCK11) { 2098 cck = (struct r92c_rx_cck *)physt; 2099 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2100 rpt = (cck->agc_rpt >> 5) & 0x3; 2101 rssi = (cck->agc_rpt & 0x1f) << 1; 2102 } else { 2103 rpt = (cck->agc_rpt >> 6) & 0x3; 2104 rssi = cck->agc_rpt & 0x3e; 2105 } 2106 rssi = cckoff[rpt] - rssi; 2107 } else { /* OFDM/HT. */ 2108 phy = (struct r92c_rx_phystat *)physt; 2109 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2110 } 2111 return (rssi); 2112} 2113 2114static int8_t 2115urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2116{ 2117 struct r92c_rx_phystat *phy; 2118 struct r88e_rx_cck *cck; 2119 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2120 int8_t rssi; 2121 2122 rssi = 0; 2123 if (rate <= URTWN_RIDX_CCK11) { 2124 cck = (struct r88e_rx_cck *)physt; 2125 cck_agc_rpt = cck->agc_rpt; 2126 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2127 vga_idx = cck_agc_rpt & 0x1f; 2128 switch (lna_idx) { 2129 case 7: 2130 if (vga_idx <= 27) 2131 rssi = -100 + 2* (27 - vga_idx); 2132 else 2133 rssi = -100; 2134 break; 2135 case 6: 2136 rssi = -48 + 2 * (2 - vga_idx); 2137 break; 2138 case 5: 2139 rssi = -42 + 2 * (7 - vga_idx); 2140 break; 2141 case 4: 2142 rssi = -36 + 2 * (7 - vga_idx); 2143 break; 2144 case 3: 2145 rssi = -24 + 2 * (7 - vga_idx); 2146 break; 2147 case 2: 2148 rssi = -12 + 2 * (5 - vga_idx); 2149 break; 2150 case 1: 2151 rssi = 8 - (2 * vga_idx); 2152 break; 2153 case 0: 2154 rssi = 14 - (2 * vga_idx); 2155 break; 2156 } 2157 rssi += 6; 2158 } else { /* OFDM/HT. */ 2159 phy = (struct r92c_rx_phystat *)physt; 2160 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2161 } 2162 return (rssi); 2163} 2164 2165static int 2166urtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2167 struct mbuf *m, struct urtwn_data *data) 2168{ 2169 struct ieee80211_frame *wh; 2170 struct ieee80211_key *k = NULL; 2171 struct ieee80211com *ic = &sc->sc_ic; 2172 struct ieee80211vap *vap = ni->ni_vap; 2173 struct r92c_tx_desc *txd; 2174 uint8_t macid, raid, ridx, subtype, type, tid, qsel; 2175 int hasqos, ismcast; 2176 2177 URTWN_ASSERT_LOCKED(sc); 2178 2179 /* 2180 * Software crypto. 2181 */ 2182 wh = mtod(m, struct ieee80211_frame *); 2183 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2184 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2185 hasqos = IEEE80211_QOS_HAS_SEQ(wh); 2186 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2187 2188 /* Select TX ring for this frame. */ 2189 if (hasqos) { 2190 tid = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 2191 tid &= IEEE80211_QOS_TID; 2192 } else 2193 tid = 0; 2194 2195 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2196 k = ieee80211_crypto_encap(ni, m); 2197 if (k == NULL) { 2198 device_printf(sc->sc_dev, 2199 "ieee80211_crypto_encap returns NULL.\n"); 2200 return (ENOBUFS); 2201 } 2202 2203 /* in case packet header moved, reset pointer */ 2204 wh = mtod(m, struct ieee80211_frame *); 2205 } 2206 2207 /* Fill Tx descriptor. */ 2208 txd = (struct r92c_tx_desc *)data->buf; 2209 memset(txd, 0, sizeof(*txd)); 2210 2211 txd->txdw0 |= htole32( 2212 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2213 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2214 if (ismcast) 2215 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2216 2217 raid = R92C_RAID_11B; /* by default */ 2218 ridx = URTWN_RIDX_CCK1; 2219 if (!ismcast) { 2220 macid = URTWN_MACID_BSS; 2221 2222 if (type == IEEE80211_FC0_TYPE_DATA) { 2223 qsel = tid % URTWN_MAX_TID; 2224 2225 if (!(m->m_flags & M_EAPOL)) { 2226 if (ic->ic_curmode != IEEE80211_MODE_11B) { 2227 raid = R92C_RAID_11BG; 2228 ridx = URTWN_RIDX_OFDM54; 2229 } else 2230 ridx = URTWN_RIDX_CCK11; 2231 } 2232 2233 if (sc->chip & URTWN_CHIP_88E) 2234 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2235 else 2236 txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2237 2238 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2239 switch (ic->ic_protmode) { 2240 case IEEE80211_PROT_CTSONLY: 2241 txd->txdw4 |= htole32( 2242 R92C_TXDW4_CTS2SELF | 2243 R92C_TXDW4_HWRTSEN); 2244 break; 2245 case IEEE80211_PROT_RTSCTS: 2246 txd->txdw4 |= htole32( 2247 R92C_TXDW4_RTSEN | 2248 R92C_TXDW4_HWRTSEN); 2249 break; 2250 default: 2251 break; 2252 } 2253 } 2254 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2255 URTWN_RIDX_OFDM24)); 2256 txd->txdw5 |= htole32(0x0001ff00); 2257 } else /* IEEE80211_FC0_TYPE_MGT */ 2258 qsel = R92C_TXDW1_QSEL_MGNT; 2259 } else { 2260 macid = URTWN_MACID_BC; 2261 qsel = R92C_TXDW1_QSEL_MGNT; 2262 } 2263 2264 txd->txdw1 |= htole32( 2265 SM(R92C_TXDW1_QSEL, qsel) | 2266 SM(R92C_TXDW1_RAID, raid)); 2267 2268 if (sc->chip & URTWN_CHIP_88E) 2269 txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 2270 else 2271 txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 2272 2273 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2274 /* Force this rate if needed. */ 2275 if (ismcast || type != IEEE80211_FC0_TYPE_DATA || 2276 (m->m_flags & M_EAPOL)) 2277 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2278 2279 if (!hasqos) { 2280 /* Use HW sequence numbering for non-QoS frames. */ 2281 if (sc->chip & URTWN_CHIP_88E) 2282 txd->txdseq = htole16(R88E_TXDSEQ_HWSEQ_EN); 2283 else 2284 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ_EN); 2285 } else { 2286 /* Set sequence number. */ 2287 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2288 } 2289 2290 if (ieee80211_radiotap_active_vap(vap)) { 2291 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2292 2293 tap->wt_flags = 0; 2294 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2295 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2296 if (k != NULL) 2297 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2298 ieee80211_radiotap_tx(vap, m); 2299 } 2300 2301 data->ni = ni; 2302 2303 urtwn_tx_start(sc, m, type, data); 2304 2305 return (0); 2306} 2307 2308static void 2309urtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 2310 struct urtwn_data *data) 2311{ 2312 struct usb_xfer *xfer; 2313 struct r92c_tx_desc *txd; 2314 uint16_t ac, sum; 2315 int i, xferlen; 2316 2317 URTWN_ASSERT_LOCKED(sc); 2318 2319 ac = M_WME_GETAC(m); 2320 2321 switch (type) { 2322 case IEEE80211_FC0_TYPE_CTL: 2323 case IEEE80211_FC0_TYPE_MGT: 2324 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 2325 break; 2326 default: 2327 xfer = sc->sc_xfer[wme2queue[ac].qid]; 2328 break; 2329 } 2330 2331 txd = (struct r92c_tx_desc *)data->buf; 2332 txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 2333 2334 /* Compute Tx descriptor checksum. */ 2335 sum = 0; 2336 for (i = 0; i < sizeof(*txd) / 2; i++) 2337 sum ^= ((uint16_t *)txd)[i]; 2338 txd->txdsum = sum; /* NB: already little endian. */ 2339 2340 xferlen = sizeof(*txd) + m->m_pkthdr.len; 2341 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 2342 2343 data->buflen = xferlen; 2344 data->m = m; 2345 2346 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 2347 usbd_transfer_start(xfer); 2348} 2349 2350static int 2351urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 2352{ 2353 struct urtwn_softc *sc = ic->ic_softc; 2354 int error; 2355 2356 URTWN_LOCK(sc); 2357 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2358 URTWN_UNLOCK(sc); 2359 return (ENXIO); 2360 } 2361 error = mbufq_enqueue(&sc->sc_snd, m); 2362 if (error) { 2363 URTWN_UNLOCK(sc); 2364 return (error); 2365 } 2366 urtwn_start(sc); 2367 URTWN_UNLOCK(sc); 2368 2369 return (0); 2370} 2371 2372static void 2373urtwn_start(struct urtwn_softc *sc) 2374{ 2375 struct ieee80211_node *ni; 2376 struct mbuf *m; 2377 struct urtwn_data *bf; 2378 2379 URTWN_ASSERT_LOCKED(sc); 2380 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2381 bf = urtwn_getbuf(sc); 2382 if (bf == NULL) { 2383 mbufq_prepend(&sc->sc_snd, m); 2384 break; 2385 } 2386 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2387 m->m_pkthdr.rcvif = NULL; 2388 if (urtwn_tx_data(sc, ni, m, bf) != 0) { 2389 if_inc_counter(ni->ni_vap->iv_ifp, 2390 IFCOUNTER_OERRORS, 1); 2391 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2392 m_freem(m); 2393 ieee80211_free_node(ni); 2394 break; 2395 } 2396 sc->sc_txtimer = 5; 2397 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2398 } 2399} 2400 2401static void 2402urtwn_parent(struct ieee80211com *ic) 2403{ 2404 struct urtwn_softc *sc = ic->ic_softc; 2405 2406 URTWN_LOCK(sc); 2407 if (sc->sc_flags & URTWN_DETACHED) { 2408 URTWN_UNLOCK(sc); 2409 return; 2410 } 2411 URTWN_UNLOCK(sc); 2412 2413 if (ic->ic_nrunning > 0) { 2414 if (urtwn_init(sc) != 0) { 2415 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2416 if (vap != NULL) 2417 ieee80211_stop(vap); 2418 } else 2419 ieee80211_start_all(ic); 2420 } else 2421 urtwn_stop(sc); 2422} 2423 2424static __inline int 2425urtwn_power_on(struct urtwn_softc *sc) 2426{ 2427 2428 return sc->sc_power_on(sc); 2429} 2430 2431static int 2432urtwn_r92c_power_on(struct urtwn_softc *sc) 2433{ 2434 uint32_t reg; 2435 usb_error_t error; 2436 int ntries; 2437 2438 /* Wait for autoload done bit. */ 2439 for (ntries = 0; ntries < 1000; ntries++) { 2440 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2441 break; 2442 urtwn_ms_delay(sc); 2443 } 2444 if (ntries == 1000) { 2445 device_printf(sc->sc_dev, 2446 "timeout waiting for chip autoload\n"); 2447 return (ETIMEDOUT); 2448 } 2449 2450 /* Unlock ISO/CLK/Power control register. */ 2451 error = urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2452 if (error != USB_ERR_NORMAL_COMPLETION) 2453 return (EIO); 2454 /* Move SPS into PWM mode. */ 2455 error = urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2456 if (error != USB_ERR_NORMAL_COMPLETION) 2457 return (EIO); 2458 urtwn_ms_delay(sc); 2459 2460 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2461 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2462 error = urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2463 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2464 if (error != USB_ERR_NORMAL_COMPLETION) 2465 return (EIO); 2466 urtwn_ms_delay(sc); 2467 error = urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2468 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2469 ~R92C_SYS_ISO_CTRL_MD2PP); 2470 if (error != USB_ERR_NORMAL_COMPLETION) 2471 return (EIO); 2472 } 2473 2474 /* Auto enable WLAN. */ 2475 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2476 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2477 if (error != USB_ERR_NORMAL_COMPLETION) 2478 return (EIO); 2479 for (ntries = 0; ntries < 1000; ntries++) { 2480 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2481 R92C_APS_FSMCO_APFM_ONMAC)) 2482 break; 2483 urtwn_ms_delay(sc); 2484 } 2485 if (ntries == 1000) { 2486 device_printf(sc->sc_dev, 2487 "timeout waiting for MAC auto ON\n"); 2488 return (ETIMEDOUT); 2489 } 2490 2491 /* Enable radio, GPIO and LED functions. */ 2492 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2493 R92C_APS_FSMCO_AFSM_HSUS | 2494 R92C_APS_FSMCO_PDN_EN | 2495 R92C_APS_FSMCO_PFM_ALDN); 2496 if (error != USB_ERR_NORMAL_COMPLETION) 2497 return (EIO); 2498 /* Release RF digital isolation. */ 2499 error = urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2500 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2501 if (error != USB_ERR_NORMAL_COMPLETION) 2502 return (EIO); 2503 2504 /* Initialize MAC. */ 2505 error = urtwn_write_1(sc, R92C_APSD_CTRL, 2506 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2507 if (error != USB_ERR_NORMAL_COMPLETION) 2508 return (EIO); 2509 for (ntries = 0; ntries < 200; ntries++) { 2510 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2511 R92C_APSD_CTRL_OFF_STATUS)) 2512 break; 2513 urtwn_ms_delay(sc); 2514 } 2515 if (ntries == 200) { 2516 device_printf(sc->sc_dev, 2517 "timeout waiting for MAC initialization\n"); 2518 return (ETIMEDOUT); 2519 } 2520 2521 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2522 reg = urtwn_read_2(sc, R92C_CR); 2523 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2524 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2525 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2526 R92C_CR_ENSEC; 2527 error = urtwn_write_2(sc, R92C_CR, reg); 2528 if (error != USB_ERR_NORMAL_COMPLETION) 2529 return (EIO); 2530 2531 error = urtwn_write_1(sc, 0xfe10, 0x19); 2532 if (error != USB_ERR_NORMAL_COMPLETION) 2533 return (EIO); 2534 return (0); 2535} 2536 2537static int 2538urtwn_r88e_power_on(struct urtwn_softc *sc) 2539{ 2540 uint32_t reg; 2541 usb_error_t error; 2542 int ntries; 2543 2544 /* Wait for power ready bit. */ 2545 for (ntries = 0; ntries < 5000; ntries++) { 2546 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2547 break; 2548 urtwn_ms_delay(sc); 2549 } 2550 if (ntries == 5000) { 2551 device_printf(sc->sc_dev, 2552 "timeout waiting for chip power up\n"); 2553 return (ETIMEDOUT); 2554 } 2555 2556 /* Reset BB. */ 2557 error = urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2558 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2559 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2560 if (error != USB_ERR_NORMAL_COMPLETION) 2561 return (EIO); 2562 2563 error = urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2564 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2565 if (error != USB_ERR_NORMAL_COMPLETION) 2566 return (EIO); 2567 2568 /* Disable HWPDN. */ 2569 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2570 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2571 if (error != USB_ERR_NORMAL_COMPLETION) 2572 return (EIO); 2573 2574 /* Disable WL suspend. */ 2575 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2576 urtwn_read_2(sc, R92C_APS_FSMCO) & 2577 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2578 if (error != USB_ERR_NORMAL_COMPLETION) 2579 return (EIO); 2580 2581 error = urtwn_write_2(sc, R92C_APS_FSMCO, 2582 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2583 if (error != USB_ERR_NORMAL_COMPLETION) 2584 return (EIO); 2585 for (ntries = 0; ntries < 5000; ntries++) { 2586 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2587 R92C_APS_FSMCO_APFM_ONMAC)) 2588 break; 2589 urtwn_ms_delay(sc); 2590 } 2591 if (ntries == 5000) 2592 return (ETIMEDOUT); 2593 2594 /* Enable LDO normal mode. */ 2595 error = urtwn_write_1(sc, R92C_LPLDO_CTRL, 2596 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2597 if (error != USB_ERR_NORMAL_COMPLETION) 2598 return (EIO); 2599 2600 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2601 error = urtwn_write_2(sc, R92C_CR, 0); 2602 if (error != USB_ERR_NORMAL_COMPLETION) 2603 return (EIO); 2604 reg = urtwn_read_2(sc, R92C_CR); 2605 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2606 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2607 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2608 error = urtwn_write_2(sc, R92C_CR, reg); 2609 if (error != USB_ERR_NORMAL_COMPLETION) 2610 return (EIO); 2611 2612 return (0); 2613} 2614 2615static int 2616urtwn_llt_init(struct urtwn_softc *sc) 2617{ 2618 int i, error, page_count, pktbuf_count; 2619 2620 page_count = (sc->chip & URTWN_CHIP_88E) ? 2621 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2622 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2623 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2624 2625 /* Reserve pages [0; page_count]. */ 2626 for (i = 0; i < page_count; i++) { 2627 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2628 return (error); 2629 } 2630 /* NB: 0xff indicates end-of-list. */ 2631 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2632 return (error); 2633 /* 2634 * Use pages [page_count + 1; pktbuf_count - 1] 2635 * as ring buffer. 2636 */ 2637 for (++i; i < pktbuf_count - 1; i++) { 2638 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2639 return (error); 2640 } 2641 /* Make the last page point to the beginning of the ring buffer. */ 2642 error = urtwn_llt_write(sc, i, page_count + 1); 2643 return (error); 2644} 2645 2646static void 2647urtwn_fw_reset(struct urtwn_softc *sc) 2648{ 2649 uint16_t reg; 2650 int ntries; 2651 2652 /* Tell 8051 to reset itself. */ 2653 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2654 2655 /* Wait until 8051 resets by itself. */ 2656 for (ntries = 0; ntries < 100; ntries++) { 2657 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2658 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2659 return; 2660 urtwn_ms_delay(sc); 2661 } 2662 /* Force 8051 reset. */ 2663 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2664} 2665 2666static void 2667urtwn_r88e_fw_reset(struct urtwn_softc *sc) 2668{ 2669 uint16_t reg; 2670 2671 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2672 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2673 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2674} 2675 2676static int 2677urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2678{ 2679 uint32_t reg; 2680 usb_error_t error = USB_ERR_NORMAL_COMPLETION; 2681 int off, mlen; 2682 2683 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2684 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2685 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2686 2687 off = R92C_FW_START_ADDR; 2688 while (len > 0) { 2689 if (len > 196) 2690 mlen = 196; 2691 else if (len > 4) 2692 mlen = 4; 2693 else 2694 mlen = 1; 2695 /* XXX fix this deconst */ 2696 error = urtwn_write_region_1(sc, off, 2697 __DECONST(uint8_t *, buf), mlen); 2698 if (error != USB_ERR_NORMAL_COMPLETION) 2699 break; 2700 off += mlen; 2701 buf += mlen; 2702 len -= mlen; 2703 } 2704 return (error); 2705} 2706 2707static int 2708urtwn_load_firmware(struct urtwn_softc *sc) 2709{ 2710 const struct firmware *fw; 2711 const struct r92c_fw_hdr *hdr; 2712 const char *imagename; 2713 const u_char *ptr; 2714 size_t len; 2715 uint32_t reg; 2716 int mlen, ntries, page, error; 2717 2718 URTWN_UNLOCK(sc); 2719 /* Read firmware image from the filesystem. */ 2720 if (sc->chip & URTWN_CHIP_88E) 2721 imagename = "urtwn-rtl8188eufw"; 2722 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2723 URTWN_CHIP_UMC_A_CUT) 2724 imagename = "urtwn-rtl8192cfwU"; 2725 else 2726 imagename = "urtwn-rtl8192cfwT"; 2727 2728 fw = firmware_get(imagename); 2729 URTWN_LOCK(sc); 2730 if (fw == NULL) { 2731 device_printf(sc->sc_dev, 2732 "failed loadfirmware of file %s\n", imagename); 2733 return (ENOENT); 2734 } 2735 2736 len = fw->datasize; 2737 2738 if (len < sizeof(*hdr)) { 2739 device_printf(sc->sc_dev, "firmware too short\n"); 2740 error = EINVAL; 2741 goto fail; 2742 } 2743 ptr = fw->data; 2744 hdr = (const struct r92c_fw_hdr *)ptr; 2745 /* Check if there is a valid FW header and skip it. */ 2746 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2747 (le16toh(hdr->signature) >> 4) == 0x88e || 2748 (le16toh(hdr->signature) >> 4) == 0x92c) { 2749 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2750 le16toh(hdr->version), le16toh(hdr->subversion), 2751 hdr->month, hdr->date, hdr->hour, hdr->minute); 2752 ptr += sizeof(*hdr); 2753 len -= sizeof(*hdr); 2754 } 2755 2756 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2757 if (sc->chip & URTWN_CHIP_88E) 2758 urtwn_r88e_fw_reset(sc); 2759 else 2760 urtwn_fw_reset(sc); 2761 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2762 } 2763 2764 if (!(sc->chip & URTWN_CHIP_88E)) { 2765 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2766 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2767 R92C_SYS_FUNC_EN_CPUEN); 2768 } 2769 urtwn_write_1(sc, R92C_MCUFWDL, 2770 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2771 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2772 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2773 2774 /* Reset the FWDL checksum. */ 2775 urtwn_write_1(sc, R92C_MCUFWDL, 2776 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2777 2778 for (page = 0; len > 0; page++) { 2779 mlen = min(len, R92C_FW_PAGE_SIZE); 2780 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2781 if (error != 0) { 2782 device_printf(sc->sc_dev, 2783 "could not load firmware page\n"); 2784 goto fail; 2785 } 2786 ptr += mlen; 2787 len -= mlen; 2788 } 2789 urtwn_write_1(sc, R92C_MCUFWDL, 2790 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2791 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2792 2793 /* Wait for checksum report. */ 2794 for (ntries = 0; ntries < 1000; ntries++) { 2795 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2796 break; 2797 urtwn_ms_delay(sc); 2798 } 2799 if (ntries == 1000) { 2800 device_printf(sc->sc_dev, 2801 "timeout waiting for checksum report\n"); 2802 error = ETIMEDOUT; 2803 goto fail; 2804 } 2805 2806 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2807 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2808 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2809 if (sc->chip & URTWN_CHIP_88E) 2810 urtwn_r88e_fw_reset(sc); 2811 /* Wait for firmware readiness. */ 2812 for (ntries = 0; ntries < 1000; ntries++) { 2813 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2814 break; 2815 urtwn_ms_delay(sc); 2816 } 2817 if (ntries == 1000) { 2818 device_printf(sc->sc_dev, 2819 "timeout waiting for firmware readiness\n"); 2820 error = ETIMEDOUT; 2821 goto fail; 2822 } 2823fail: 2824 firmware_put(fw, FIRMWARE_UNLOAD); 2825 return (error); 2826} 2827 2828static int 2829urtwn_dma_init(struct urtwn_softc *sc) 2830{ 2831 struct usb_endpoint *ep, *ep_end; 2832 usb_error_t usb_err; 2833 uint32_t reg; 2834 int hashq, hasnq, haslq, nqueues, ntx; 2835 int error, pagecount, npubqpages, nqpages, nrempages, tx_boundary; 2836 2837 /* Initialize LLT table. */ 2838 error = urtwn_llt_init(sc); 2839 if (error != 0) 2840 return (error); 2841 2842 /* Determine the number of bulk-out pipes. */ 2843 ntx = 0; 2844 ep = sc->sc_udev->endpoints; 2845 ep_end = sc->sc_udev->endpoints + sc->sc_udev->endpoints_max; 2846 for (; ep != ep_end; ep++) { 2847 if ((ep->edesc == NULL) || 2848 (ep->iface_index != sc->sc_iface_index)) 2849 continue; 2850 if (UE_GET_DIR(ep->edesc->bEndpointAddress) == UE_DIR_OUT) 2851 ntx++; 2852 } 2853 if (ntx == 0) { 2854 device_printf(sc->sc_dev, 2855 "%d: invalid number of Tx bulk pipes\n", ntx); 2856 return (EIO); 2857 } 2858 2859 /* Get Tx queues to USB endpoints mapping. */ 2860 hashq = hasnq = haslq = nqueues = 0; 2861 switch (ntx) { 2862 case 1: hashq = 1; break; 2863 case 2: hashq = hasnq = 1; break; 2864 case 3: case 4: hashq = hasnq = haslq = 1; break; 2865 } 2866 nqueues = hashq + hasnq + haslq; 2867 if (nqueues == 0) 2868 return (EIO); 2869 2870 npubqpages = nqpages = nrempages = pagecount = 0; 2871 if (sc->chip & URTWN_CHIP_88E) 2872 tx_boundary = R88E_TX_PAGE_BOUNDARY; 2873 else { 2874 pagecount = R92C_TX_PAGE_COUNT; 2875 npubqpages = R92C_PUBQ_NPAGES; 2876 tx_boundary = R92C_TX_PAGE_BOUNDARY; 2877 } 2878 2879 /* Set number of pages for normal priority queue. */ 2880 if (sc->chip & URTWN_CHIP_88E) { 2881 usb_err = urtwn_write_2(sc, R92C_RQPN_NPQ, 0xd); 2882 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2883 return (EIO); 2884 usb_err = urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2885 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2886 return (EIO); 2887 } else { 2888 /* Get the number of pages for each queue. */ 2889 nqpages = (pagecount - npubqpages) / nqueues; 2890 /* 2891 * The remaining pages are assigned to the high priority 2892 * queue. 2893 */ 2894 nrempages = (pagecount - npubqpages) % nqueues; 2895 usb_err = urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2896 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2897 return (EIO); 2898 usb_err = urtwn_write_4(sc, R92C_RQPN, 2899 /* Set number of pages for public queue. */ 2900 SM(R92C_RQPN_PUBQ, npubqpages) | 2901 /* Set number of pages for high priority queue. */ 2902 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2903 /* Set number of pages for low priority queue. */ 2904 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2905 /* Load values. */ 2906 R92C_RQPN_LD); 2907 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2908 return (EIO); 2909 } 2910 2911 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, tx_boundary); 2912 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2913 return (EIO); 2914 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, tx_boundary); 2915 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2916 return (EIO); 2917 usb_err = urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, tx_boundary); 2918 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2919 return (EIO); 2920 usb_err = urtwn_write_1(sc, R92C_TRXFF_BNDY, tx_boundary); 2921 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2922 return (EIO); 2923 usb_err = urtwn_write_1(sc, R92C_TDECTRL + 1, tx_boundary); 2924 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2925 return (EIO); 2926 2927 /* Set queue to USB pipe mapping. */ 2928 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2929 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2930 if (nqueues == 1) { 2931 if (hashq) 2932 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2933 else if (hasnq) 2934 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2935 else 2936 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2937 } else if (nqueues == 2) { 2938 /* 2939 * All 2-endpoints configs have high and normal 2940 * priority queues. 2941 */ 2942 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2943 } else 2944 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2945 usb_err = urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2946 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2947 return (EIO); 2948 2949 /* Set Tx/Rx transfer page boundary. */ 2950 usb_err = urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 2951 (sc->chip & URTWN_CHIP_88E) ? 0x23ff : 0x27ff); 2952 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2953 return (EIO); 2954 2955 /* Set Tx/Rx transfer page size. */ 2956 usb_err = urtwn_write_1(sc, R92C_PBP, 2957 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2958 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2959 if (usb_err != USB_ERR_NORMAL_COMPLETION) 2960 return (EIO); 2961 2962 return (0); 2963} 2964 2965static int 2966urtwn_mac_init(struct urtwn_softc *sc) 2967{ 2968 usb_error_t error; 2969 int i; 2970 2971 /* Write MAC initialization values. */ 2972 if (sc->chip & URTWN_CHIP_88E) { 2973 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2974 error = urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2975 rtl8188eu_mac[i].val); 2976 if (error != USB_ERR_NORMAL_COMPLETION) 2977 return (EIO); 2978 } 2979 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2980 } else { 2981 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2982 error = urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2983 rtl8192cu_mac[i].val); 2984 if (error != USB_ERR_NORMAL_COMPLETION) 2985 return (EIO); 2986 } 2987 2988 return (0); 2989} 2990 2991static void 2992urtwn_bb_init(struct urtwn_softc *sc) 2993{ 2994 const struct urtwn_bb_prog *prog; 2995 uint32_t reg; 2996 uint8_t crystalcap; 2997 int i; 2998 2999 /* Enable BB and RF. */ 3000 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3001 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3002 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3003 R92C_SYS_FUNC_EN_DIO_RF); 3004 3005 if (!(sc->chip & URTWN_CHIP_88E)) 3006 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 3007 3008 urtwn_write_1(sc, R92C_RF_CTRL, 3009 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3010 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3011 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3012 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3013 3014 if (!(sc->chip & URTWN_CHIP_88E)) { 3015 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3016 urtwn_write_1(sc, 0x15, 0xe9); 3017 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3018 } 3019 3020 /* Select BB programming based on board type. */ 3021 if (sc->chip & URTWN_CHIP_88E) 3022 prog = &rtl8188eu_bb_prog; 3023 else if (!(sc->chip & URTWN_CHIP_92C)) { 3024 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3025 prog = &rtl8188ce_bb_prog; 3026 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3027 prog = &rtl8188ru_bb_prog; 3028 else 3029 prog = &rtl8188cu_bb_prog; 3030 } else { 3031 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3032 prog = &rtl8192ce_bb_prog; 3033 else 3034 prog = &rtl8192cu_bb_prog; 3035 } 3036 /* Write BB initialization values. */ 3037 for (i = 0; i < prog->count; i++) { 3038 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3039 urtwn_ms_delay(sc); 3040 } 3041 3042 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3043 /* 8192C 1T only configuration. */ 3044 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3045 reg = (reg & ~0x00000003) | 0x2; 3046 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3047 3048 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3049 reg = (reg & ~0x00300033) | 0x00200022; 3050 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3051 3052 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3053 reg = (reg & ~0xff000000) | 0x45 << 24; 3054 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3055 3056 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3057 reg = (reg & ~0x000000ff) | 0x23; 3058 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3059 3060 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3061 reg = (reg & ~0x00000030) | 1 << 4; 3062 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3063 3064 reg = urtwn_bb_read(sc, 0xe74); 3065 reg = (reg & ~0x0c000000) | 2 << 26; 3066 urtwn_bb_write(sc, 0xe74, reg); 3067 reg = urtwn_bb_read(sc, 0xe78); 3068 reg = (reg & ~0x0c000000) | 2 << 26; 3069 urtwn_bb_write(sc, 0xe78, reg); 3070 reg = urtwn_bb_read(sc, 0xe7c); 3071 reg = (reg & ~0x0c000000) | 2 << 26; 3072 urtwn_bb_write(sc, 0xe7c, reg); 3073 reg = urtwn_bb_read(sc, 0xe80); 3074 reg = (reg & ~0x0c000000) | 2 << 26; 3075 urtwn_bb_write(sc, 0xe80, reg); 3076 reg = urtwn_bb_read(sc, 0xe88); 3077 reg = (reg & ~0x0c000000) | 2 << 26; 3078 urtwn_bb_write(sc, 0xe88, reg); 3079 } 3080 3081 /* Write AGC values. */ 3082 for (i = 0; i < prog->agccount; i++) { 3083 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 3084 prog->agcvals[i]); 3085 urtwn_ms_delay(sc); 3086 } 3087 3088 if (sc->chip & URTWN_CHIP_88E) { 3089 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3090 urtwn_ms_delay(sc); 3091 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3092 urtwn_ms_delay(sc); 3093 3094 crystalcap = sc->rom.r88e_rom[0xb9]; 3095 if (crystalcap == 0xff) 3096 crystalcap = 0x20; 3097 crystalcap &= 0x3f; 3098 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3099 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3100 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3101 crystalcap | crystalcap << 6)); 3102 } else { 3103 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3104 R92C_HSSI_PARAM2_CCK_HIPWR) 3105 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 3106 } 3107} 3108 3109static void 3110urtwn_rf_init(struct urtwn_softc *sc) 3111{ 3112 const struct urtwn_rf_prog *prog; 3113 uint32_t reg, type; 3114 int i, j, idx, off; 3115 3116 /* Select RF programming based on board type. */ 3117 if (sc->chip & URTWN_CHIP_88E) 3118 prog = rtl8188eu_rf_prog; 3119 else if (!(sc->chip & URTWN_CHIP_92C)) { 3120 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 3121 prog = rtl8188ce_rf_prog; 3122 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3123 prog = rtl8188ru_rf_prog; 3124 else 3125 prog = rtl8188cu_rf_prog; 3126 } else 3127 prog = rtl8192ce_rf_prog; 3128 3129 for (i = 0; i < sc->nrxchains; i++) { 3130 /* Save RF_ENV control type. */ 3131 idx = i / 2; 3132 off = (i % 2) * 16; 3133 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3134 type = (reg >> off) & 0x10; 3135 3136 /* Set RF_ENV enable. */ 3137 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3138 reg |= 0x100000; 3139 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3140 urtwn_ms_delay(sc); 3141 /* Set RF_ENV output high. */ 3142 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 3143 reg |= 0x10; 3144 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 3145 urtwn_ms_delay(sc); 3146 /* Set address and data lengths of RF registers. */ 3147 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3148 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3149 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3150 urtwn_ms_delay(sc); 3151 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3152 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3153 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3154 urtwn_ms_delay(sc); 3155 3156 /* Write RF initialization values for this chain. */ 3157 for (j = 0; j < prog[i].count; j++) { 3158 if (prog[i].regs[j] >= 0xf9 && 3159 prog[i].regs[j] <= 0xfe) { 3160 /* 3161 * These are fake RF registers offsets that 3162 * indicate a delay is required. 3163 */ 3164 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 3165 continue; 3166 } 3167 urtwn_rf_write(sc, i, prog[i].regs[j], 3168 prog[i].vals[j]); 3169 urtwn_ms_delay(sc); 3170 } 3171 3172 /* Restore RF_ENV control type. */ 3173 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3174 reg &= ~(0x10 << off) | (type << off); 3175 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 3176 3177 /* Cache RF register CHNLBW. */ 3178 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3179 } 3180 3181 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3182 URTWN_CHIP_UMC_A_CUT) { 3183 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3184 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3185 } 3186} 3187 3188static void 3189urtwn_cam_init(struct urtwn_softc *sc) 3190{ 3191 /* Invalidate all CAM entries. */ 3192 urtwn_write_4(sc, R92C_CAMCMD, 3193 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3194} 3195 3196static void 3197urtwn_pa_bias_init(struct urtwn_softc *sc) 3198{ 3199 uint8_t reg; 3200 int i; 3201 3202 for (i = 0; i < sc->nrxchains; i++) { 3203 if (sc->pa_setting & (1 << i)) 3204 continue; 3205 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3206 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3207 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3208 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3209 } 3210 if (!(sc->pa_setting & 0x10)) { 3211 reg = urtwn_read_1(sc, 0x16); 3212 reg = (reg & ~0xf0) | 0x90; 3213 urtwn_write_1(sc, 0x16, reg); 3214 } 3215} 3216 3217static void 3218urtwn_rxfilter_init(struct urtwn_softc *sc) 3219{ 3220 struct ieee80211com *ic = &sc->sc_ic; 3221 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3222 uint32_t rcr; 3223 uint16_t filter; 3224 3225 URTWN_ASSERT_LOCKED(sc); 3226 3227 /* Accept all multicast frames. */ 3228 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3229 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3230 3231 /* Filter for management frames. */ 3232 filter = 0x7f3f; 3233 switch (vap->iv_opmode) { 3234 case IEEE80211_M_STA: 3235 filter &= ~( 3236 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 3237 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 3238 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 3239 break; 3240 case IEEE80211_M_HOSTAP: 3241 filter &= ~( 3242 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 3243 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP) | 3244 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_BEACON)); 3245 break; 3246 case IEEE80211_M_MONITOR: 3247 case IEEE80211_M_IBSS: 3248 break; 3249 default: 3250 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3251 __func__, vap->iv_opmode); 3252 break; 3253 } 3254 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 3255 3256 /* Reject all control frames. */ 3257 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3258 3259 /* Reject all data frames. */ 3260 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 3261 3262 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 3263 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 3264 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 3265 3266 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 3267 /* Accept all frames. */ 3268 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 3269 R92C_RCR_AAP; 3270 } 3271 3272 /* Set Rx filter. */ 3273 urtwn_write_4(sc, R92C_RCR, rcr); 3274 3275 if (ic->ic_promisc != 0) { 3276 /* Update Rx filter. */ 3277 urtwn_set_promisc(sc); 3278 } 3279} 3280 3281static void 3282urtwn_edca_init(struct urtwn_softc *sc) 3283{ 3284 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3285 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3286 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3287 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3288 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3289 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3290 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3291 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3292} 3293 3294static void 3295urtwn_write_txpower(struct urtwn_softc *sc, int chain, 3296 uint16_t power[URTWN_RIDX_COUNT]) 3297{ 3298 uint32_t reg; 3299 3300 /* Write per-CCK rate Tx power. */ 3301 if (chain == 0) { 3302 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3303 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3304 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3305 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3306 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3307 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3308 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3309 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3310 } else { 3311 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3312 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3313 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3314 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3315 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3316 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3317 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3318 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3319 } 3320 /* Write per-OFDM rate Tx power. */ 3321 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3322 SM(R92C_TXAGC_RATE06, power[ 4]) | 3323 SM(R92C_TXAGC_RATE09, power[ 5]) | 3324 SM(R92C_TXAGC_RATE12, power[ 6]) | 3325 SM(R92C_TXAGC_RATE18, power[ 7])); 3326 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3327 SM(R92C_TXAGC_RATE24, power[ 8]) | 3328 SM(R92C_TXAGC_RATE36, power[ 9]) | 3329 SM(R92C_TXAGC_RATE48, power[10]) | 3330 SM(R92C_TXAGC_RATE54, power[11])); 3331 /* Write per-MCS Tx power. */ 3332 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3333 SM(R92C_TXAGC_MCS00, power[12]) | 3334 SM(R92C_TXAGC_MCS01, power[13]) | 3335 SM(R92C_TXAGC_MCS02, power[14]) | 3336 SM(R92C_TXAGC_MCS03, power[15])); 3337 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3338 SM(R92C_TXAGC_MCS04, power[16]) | 3339 SM(R92C_TXAGC_MCS05, power[17]) | 3340 SM(R92C_TXAGC_MCS06, power[18]) | 3341 SM(R92C_TXAGC_MCS07, power[19])); 3342 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3343 SM(R92C_TXAGC_MCS08, power[20]) | 3344 SM(R92C_TXAGC_MCS09, power[21]) | 3345 SM(R92C_TXAGC_MCS10, power[22]) | 3346 SM(R92C_TXAGC_MCS11, power[23])); 3347 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3348 SM(R92C_TXAGC_MCS12, power[24]) | 3349 SM(R92C_TXAGC_MCS13, power[25]) | 3350 SM(R92C_TXAGC_MCS14, power[26]) | 3351 SM(R92C_TXAGC_MCS15, power[27])); 3352} 3353 3354static void 3355urtwn_get_txpower(struct urtwn_softc *sc, int chain, 3356 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3357 uint16_t power[URTWN_RIDX_COUNT]) 3358{ 3359 struct ieee80211com *ic = &sc->sc_ic; 3360 struct r92c_rom *rom = &sc->rom.r92c_rom; 3361 uint16_t cckpow, ofdmpow, htpow, diff, max; 3362 const struct urtwn_txpwr *base; 3363 int ridx, chan, group; 3364 3365 /* Determine channel group. */ 3366 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3367 if (chan <= 3) 3368 group = 0; 3369 else if (chan <= 9) 3370 group = 1; 3371 else 3372 group = 2; 3373 3374 /* Get original Tx power based on board type and RF chain. */ 3375 if (!(sc->chip & URTWN_CHIP_92C)) { 3376 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3377 base = &rtl8188ru_txagc[chain]; 3378 else 3379 base = &rtl8192cu_txagc[chain]; 3380 } else 3381 base = &rtl8192cu_txagc[chain]; 3382 3383 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3384 if (sc->regulatory == 0) { 3385 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3386 power[ridx] = base->pwr[0][ridx]; 3387 } 3388 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3389 if (sc->regulatory == 3) { 3390 power[ridx] = base->pwr[0][ridx]; 3391 /* Apply vendor limits. */ 3392 if (extc != NULL) 3393 max = rom->ht40_max_pwr[group]; 3394 else 3395 max = rom->ht20_max_pwr[group]; 3396 max = (max >> (chain * 4)) & 0xf; 3397 if (power[ridx] > max) 3398 power[ridx] = max; 3399 } else if (sc->regulatory == 1) { 3400 if (extc == NULL) 3401 power[ridx] = base->pwr[group][ridx]; 3402 } else if (sc->regulatory != 2) 3403 power[ridx] = base->pwr[0][ridx]; 3404 } 3405 3406 /* Compute per-CCK rate Tx power. */ 3407 cckpow = rom->cck_tx_pwr[chain][group]; 3408 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3409 power[ridx] += cckpow; 3410 if (power[ridx] > R92C_MAX_TX_PWR) 3411 power[ridx] = R92C_MAX_TX_PWR; 3412 } 3413 3414 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3415 if (sc->ntxchains > 1) { 3416 /* Apply reduction for 2 spatial streams. */ 3417 diff = rom->ht40_2s_tx_pwr_diff[group]; 3418 diff = (diff >> (chain * 4)) & 0xf; 3419 htpow = (htpow > diff) ? htpow - diff : 0; 3420 } 3421 3422 /* Compute per-OFDM rate Tx power. */ 3423 diff = rom->ofdm_tx_pwr_diff[group]; 3424 diff = (diff >> (chain * 4)) & 0xf; 3425 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3426 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3427 power[ridx] += ofdmpow; 3428 if (power[ridx] > R92C_MAX_TX_PWR) 3429 power[ridx] = R92C_MAX_TX_PWR; 3430 } 3431 3432 /* Compute per-MCS Tx power. */ 3433 if (extc == NULL) { 3434 diff = rom->ht20_tx_pwr_diff[group]; 3435 diff = (diff >> (chain * 4)) & 0xf; 3436 htpow += diff; /* HT40->HT20 correction. */ 3437 } 3438 for (ridx = 12; ridx <= 27; ridx++) { 3439 power[ridx] += htpow; 3440 if (power[ridx] > R92C_MAX_TX_PWR) 3441 power[ridx] = R92C_MAX_TX_PWR; 3442 } 3443#ifdef URTWN_DEBUG 3444 if (urtwn_debug >= 4) { 3445 /* Dump per-rate Tx power values. */ 3446 printf("Tx power for chain %d:\n", chain); 3447 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 3448 printf("Rate %d = %u\n", ridx, power[ridx]); 3449 } 3450#endif 3451} 3452 3453static void 3454urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3455 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3456 uint16_t power[URTWN_RIDX_COUNT]) 3457{ 3458 struct ieee80211com *ic = &sc->sc_ic; 3459 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3460 const struct urtwn_r88e_txpwr *base; 3461 int ridx, chan, group; 3462 3463 /* Determine channel group. */ 3464 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3465 if (chan <= 2) 3466 group = 0; 3467 else if (chan <= 5) 3468 group = 1; 3469 else if (chan <= 8) 3470 group = 2; 3471 else if (chan <= 11) 3472 group = 3; 3473 else if (chan <= 13) 3474 group = 4; 3475 else 3476 group = 5; 3477 3478 /* Get original Tx power based on board type and RF chain. */ 3479 base = &rtl8188eu_txagc[chain]; 3480 3481 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3482 if (sc->regulatory == 0) { 3483 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3484 power[ridx] = base->pwr[0][ridx]; 3485 } 3486 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3487 if (sc->regulatory == 3) 3488 power[ridx] = base->pwr[0][ridx]; 3489 else if (sc->regulatory == 1) { 3490 if (extc == NULL) 3491 power[ridx] = base->pwr[group][ridx]; 3492 } else if (sc->regulatory != 2) 3493 power[ridx] = base->pwr[0][ridx]; 3494 } 3495 3496 /* Compute per-CCK rate Tx power. */ 3497 cckpow = sc->cck_tx_pwr[group]; 3498 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3499 power[ridx] += cckpow; 3500 if (power[ridx] > R92C_MAX_TX_PWR) 3501 power[ridx] = R92C_MAX_TX_PWR; 3502 } 3503 3504 htpow = sc->ht40_tx_pwr[group]; 3505 3506 /* Compute per-OFDM rate Tx power. */ 3507 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3508 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3509 power[ridx] += ofdmpow; 3510 if (power[ridx] > R92C_MAX_TX_PWR) 3511 power[ridx] = R92C_MAX_TX_PWR; 3512 } 3513 3514 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3515 for (ridx = 12; ridx <= 27; ridx++) { 3516 power[ridx] += bw20pow; 3517 if (power[ridx] > R92C_MAX_TX_PWR) 3518 power[ridx] = R92C_MAX_TX_PWR; 3519 } 3520} 3521 3522static void 3523urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3524 struct ieee80211_channel *extc) 3525{ 3526 uint16_t power[URTWN_RIDX_COUNT]; 3527 int i; 3528 3529 for (i = 0; i < sc->ntxchains; i++) { 3530 /* Compute per-rate Tx power values. */ 3531 if (sc->chip & URTWN_CHIP_88E) 3532 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3533 else 3534 urtwn_get_txpower(sc, i, c, extc, power); 3535 /* Write per-rate Tx power values to hardware. */ 3536 urtwn_write_txpower(sc, i, power); 3537 } 3538} 3539 3540static void 3541urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 3542{ 3543 uint32_t reg; 3544 3545 reg = urtwn_read_4(sc, R92C_RCR); 3546 if (enable) 3547 reg &= ~R92C_RCR_CBSSID_BCN; 3548 else 3549 reg |= R92C_RCR_CBSSID_BCN; 3550 urtwn_write_4(sc, R92C_RCR, reg); 3551} 3552 3553static void 3554urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 3555{ 3556 uint32_t reg; 3557 3558 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3559 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3560 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3561 3562 if (!(sc->chip & URTWN_CHIP_88E)) { 3563 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3564 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3565 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3566 } 3567} 3568 3569static void 3570urtwn_scan_start(struct ieee80211com *ic) 3571{ 3572 struct urtwn_softc *sc = ic->ic_softc; 3573 3574 URTWN_LOCK(sc); 3575 /* Receive beacons / probe responses from any BSSID. */ 3576 if (ic->ic_opmode != IEEE80211_M_IBSS) 3577 urtwn_set_rx_bssid_all(sc, 1); 3578 3579 /* Set gain for scanning. */ 3580 urtwn_set_gain(sc, 0x20); 3581 URTWN_UNLOCK(sc); 3582} 3583 3584static void 3585urtwn_scan_end(struct ieee80211com *ic) 3586{ 3587 struct urtwn_softc *sc = ic->ic_softc; 3588 3589 URTWN_LOCK(sc); 3590 /* Restore limitations. */ 3591 if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 3592 urtwn_set_rx_bssid_all(sc, 0); 3593 3594 /* Set gain under link. */ 3595 urtwn_set_gain(sc, 0x32); 3596 URTWN_UNLOCK(sc); 3597} 3598 3599static void 3600urtwn_set_channel(struct ieee80211com *ic) 3601{ 3602 struct urtwn_softc *sc = ic->ic_softc; 3603 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3604 3605 URTWN_LOCK(sc); 3606 if (vap->iv_state == IEEE80211_S_SCAN) { 3607 /* Make link LED blink during scan. */ 3608 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3609 } 3610 urtwn_set_chan(sc, ic->ic_curchan, NULL); 3611 URTWN_UNLOCK(sc); 3612} 3613 3614static int 3615urtwn_wme_update(struct ieee80211com *ic) 3616{ 3617 const struct wmeParams *wmep = 3618 ic->ic_wme.wme_chanParams.cap_wmeParams; 3619 struct urtwn_softc *sc = ic->ic_softc; 3620 uint8_t aifs, acm, slottime; 3621 int ac; 3622 3623 acm = 0; 3624 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 3625 IEEE80211_DUR_SHSLOT : IEEE80211_DUR_SLOT; 3626 3627 URTWN_LOCK(sc); 3628 for (ac = WME_AC_BE; ac < WME_NUM_AC; ac++) { 3629 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 3630 aifs = wmep[ac].wmep_aifsn * slottime + IEEE80211_DUR_SIFS; 3631 urtwn_write_4(sc, wme2queue[ac].reg, 3632 SM(R92C_EDCA_PARAM_TXOP, wmep[ac].wmep_txopLimit) | 3633 SM(R92C_EDCA_PARAM_ECWMIN, wmep[ac].wmep_logcwmin) | 3634 SM(R92C_EDCA_PARAM_ECWMAX, wmep[ac].wmep_logcwmax) | 3635 SM(R92C_EDCA_PARAM_AIFS, aifs)); 3636 if (ac != WME_AC_BE) 3637 acm |= wmep[ac].wmep_acm << ac; 3638 } 3639 3640 if (acm != 0) 3641 acm |= R92C_ACMHWCTRL_EN; 3642 urtwn_write_1(sc, R92C_ACMHWCTRL, 3643 (urtwn_read_1(sc, R92C_ACMHWCTRL) & ~R92C_ACMHWCTRL_ACM_MASK) | 3644 acm); 3645 3646 URTWN_UNLOCK(sc); 3647 3648 return 0; 3649} 3650 3651static void 3652urtwn_set_promisc(struct urtwn_softc *sc) 3653{ 3654 struct ieee80211com *ic = &sc->sc_ic; 3655 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3656 uint32_t rcr, mask1, mask2; 3657 3658 URTWN_ASSERT_LOCKED(sc); 3659 3660 if (vap->iv_opmode == IEEE80211_M_MONITOR) 3661 return; 3662 3663 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 3664 mask2 = R92C_RCR_APM; 3665 3666 if (vap->iv_state == IEEE80211_S_RUN) { 3667 switch (vap->iv_opmode) { 3668 case IEEE80211_M_STA: 3669 mask2 |= R92C_RCR_CBSSID_DATA; 3670 /* FALLTHROUGH */ 3671 case IEEE80211_M_HOSTAP: 3672 mask2 |= R92C_RCR_CBSSID_BCN; 3673 break; 3674 case IEEE80211_M_IBSS: 3675 mask2 |= R92C_RCR_CBSSID_DATA; 3676 break; 3677 default: 3678 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3679 __func__, vap->iv_opmode); 3680 return; 3681 } 3682 } 3683 3684 rcr = urtwn_read_4(sc, R92C_RCR); 3685 if (ic->ic_promisc == 0) 3686 rcr = (rcr & ~mask1) | mask2; 3687 else 3688 rcr = (rcr & ~mask2) | mask1; 3689 urtwn_write_4(sc, R92C_RCR, rcr); 3690} 3691 3692static void 3693urtwn_update_promisc(struct ieee80211com *ic) 3694{ 3695 struct urtwn_softc *sc = ic->ic_softc; 3696 3697 URTWN_LOCK(sc); 3698 if (sc->sc_flags & URTWN_RUNNING) 3699 urtwn_set_promisc(sc); 3700 URTWN_UNLOCK(sc); 3701} 3702 3703static void 3704urtwn_update_mcast(struct ieee80211com *ic) 3705{ 3706 /* XXX do nothing? */ 3707} 3708 3709static void 3710urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3711 struct ieee80211_channel *extc) 3712{ 3713 struct ieee80211com *ic = &sc->sc_ic; 3714 uint32_t reg; 3715 u_int chan; 3716 int i; 3717 3718 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3719 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3720 device_printf(sc->sc_dev, 3721 "%s: invalid channel %x\n", __func__, chan); 3722 return; 3723 } 3724 3725 /* Set Tx power for this new channel. */ 3726 urtwn_set_txpower(sc, c, extc); 3727 3728 for (i = 0; i < sc->nrxchains; i++) { 3729 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3730 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3731 } 3732#ifndef IEEE80211_NO_HT 3733 if (extc != NULL) { 3734 /* Is secondary channel below or above primary? */ 3735 int prichlo = c->ic_freq < extc->ic_freq; 3736 3737 urtwn_write_1(sc, R92C_BWOPMODE, 3738 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3739 3740 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3741 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3742 urtwn_write_1(sc, R92C_RRSR + 2, reg); 3743 3744 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3745 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3746 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3747 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3748 3749 /* Set CCK side band. */ 3750 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3751 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3752 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3753 3754 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3755 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3756 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3757 3758 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3759 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3760 ~R92C_FPGA0_ANAPARAM2_CBW20); 3761 3762 reg = urtwn_bb_read(sc, 0x818); 3763 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3764 urtwn_bb_write(sc, 0x818, reg); 3765 3766 /* Select 40MHz bandwidth. */ 3767 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3768 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3769 } else 3770#endif 3771 { 3772 urtwn_write_1(sc, R92C_BWOPMODE, 3773 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3774 3775 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3776 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3777 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3778 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3779 3780 if (!(sc->chip & URTWN_CHIP_88E)) { 3781 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3782 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3783 R92C_FPGA0_ANAPARAM2_CBW20); 3784 } 3785 3786 /* Select 20MHz bandwidth. */ 3787 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3788 (sc->rf_chnlbw[0] & ~0xfff) | chan | 3789 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3790 R92C_RF_CHNLBW_BW20)); 3791 } 3792} 3793 3794static void 3795urtwn_iq_calib(struct urtwn_softc *sc) 3796{ 3797 /* TODO */ 3798} 3799 3800static void 3801urtwn_lc_calib(struct urtwn_softc *sc) 3802{ 3803 uint32_t rf_ac[2]; 3804 uint8_t txmode; 3805 int i; 3806 3807 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3808 if ((txmode & 0x70) != 0) { 3809 /* Disable all continuous Tx. */ 3810 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3811 3812 /* Set RF mode to standby mode. */ 3813 for (i = 0; i < sc->nrxchains; i++) { 3814 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3815 urtwn_rf_write(sc, i, R92C_RF_AC, 3816 RW(rf_ac[i], R92C_RF_AC_MODE, 3817 R92C_RF_AC_MODE_STANDBY)); 3818 } 3819 } else { 3820 /* Block all Tx queues. */ 3821 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3822 } 3823 /* Start calibration. */ 3824 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3825 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3826 3827 /* Give calibration the time to complete. */ 3828 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3829 3830 /* Restore configuration. */ 3831 if ((txmode & 0x70) != 0) { 3832 /* Restore Tx mode. */ 3833 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3834 /* Restore RF mode. */ 3835 for (i = 0; i < sc->nrxchains; i++) 3836 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3837 } else { 3838 /* Unblock all Tx queues. */ 3839 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3840 } 3841} 3842 3843static int 3844urtwn_init(struct urtwn_softc *sc) 3845{ 3846 struct ieee80211com *ic = &sc->sc_ic; 3847 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3848 uint8_t macaddr[IEEE80211_ADDR_LEN]; 3849 uint32_t reg; 3850 usb_error_t usb_err = USB_ERR_NORMAL_COMPLETION; 3851 int error; 3852 3853 URTWN_LOCK(sc); 3854 if (sc->sc_flags & URTWN_RUNNING) { 3855 URTWN_UNLOCK(sc); 3856 return (0); 3857 } 3858 3859 /* Init firmware commands ring. */ 3860 sc->fwcur = 0; 3861 3862 /* Allocate Tx/Rx buffers. */ 3863 error = urtwn_alloc_rx_list(sc); 3864 if (error != 0) 3865 goto fail; 3866 3867 error = urtwn_alloc_tx_list(sc); 3868 if (error != 0) 3869 goto fail; 3870 3871 /* Power on adapter. */ 3872 error = urtwn_power_on(sc); 3873 if (error != 0) 3874 goto fail; 3875 3876 /* Initialize DMA. */ 3877 error = urtwn_dma_init(sc); 3878 if (error != 0) 3879 goto fail; 3880 3881 /* Set info size in Rx descriptors (in 64-bit words). */ 3882 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3883 3884 /* Init interrupts. */ 3885 if (sc->chip & URTWN_CHIP_88E) { 3886 usb_err = urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3887 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3888 goto fail; 3889 usb_err = urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3890 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3891 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3892 goto fail; 3893 usb_err = urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3894 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3895 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3896 goto fail; 3897 usb_err = urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3898 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3899 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3900 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3901 goto fail; 3902 } else { 3903 usb_err = urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3904 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3905 goto fail; 3906 usb_err = urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3907 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3908 goto fail; 3909 } 3910 3911 /* Set MAC address. */ 3912 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3913 usb_err = urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3914 if (usb_err != USB_ERR_NORMAL_COMPLETION) 3915 goto fail; 3916 3917 /* Set initial network type. */ 3918 urtwn_set_mode(sc, R92C_MSR_INFRA); 3919 3920 /* Initialize Rx filter. */ 3921 urtwn_rxfilter_init(sc); 3922 3923 /* Set response rate. */ 3924 reg = urtwn_read_4(sc, R92C_RRSR); 3925 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3926 urtwn_write_4(sc, R92C_RRSR, reg); 3927 3928 /* Set short/long retry limits. */ 3929 urtwn_write_2(sc, R92C_RL, 3930 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3931 3932 /* Initialize EDCA parameters. */ 3933 urtwn_edca_init(sc); 3934 3935 /* Setup rate fallback. */ 3936 if (!(sc->chip & URTWN_CHIP_88E)) { 3937 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3938 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3939 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3940 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3941 } 3942 3943 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3944 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3945 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3946 /* Set ACK timeout. */ 3947 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3948 3949 /* Setup USB aggregation. */ 3950 reg = urtwn_read_4(sc, R92C_TDECTRL); 3951 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3952 urtwn_write_4(sc, R92C_TDECTRL, reg); 3953 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3954 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3955 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3956 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3957 if (sc->chip & URTWN_CHIP_88E) 3958 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3959 else { 3960 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3961 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3962 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3963 R92C_USB_SPECIAL_OPTION_AGG_EN); 3964 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3965 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3966 } 3967 3968 /* Initialize beacon parameters. */ 3969 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3970 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3971 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3972 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3973 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3974 3975 if (!(sc->chip & URTWN_CHIP_88E)) { 3976 /* Setup AMPDU aggregation. */ 3977 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3978 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3979 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3980 3981 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3982 } 3983 3984 /* Load 8051 microcode. */ 3985 error = urtwn_load_firmware(sc); 3986 if (error != 0) 3987 goto fail; 3988 3989 /* Initialize MAC/BB/RF blocks. */ 3990 error = urtwn_mac_init(sc); 3991 if (error != 0) { 3992 device_printf(sc->sc_dev, 3993 "%s: error while initializing MAC block\n", __func__); 3994 goto fail; 3995 } 3996 urtwn_bb_init(sc); 3997 urtwn_rf_init(sc); 3998 3999 /* Reinitialize Rx filter (D3845 is not committed yet). */ 4000 urtwn_rxfilter_init(sc); 4001 4002 if (sc->chip & URTWN_CHIP_88E) { 4003 urtwn_write_2(sc, R92C_CR, 4004 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4005 R92C_CR_MACRXEN); 4006 } 4007 4008 /* Turn CCK and OFDM blocks on. */ 4009 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4010 reg |= R92C_RFMOD_CCK_EN; 4011 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4012 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4013 goto fail; 4014 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4015 reg |= R92C_RFMOD_OFDM_EN; 4016 usb_err = urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4017 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4018 goto fail; 4019 4020 /* Clear per-station keys table. */ 4021 urtwn_cam_init(sc); 4022 4023 /* Enable hardware sequence numbering. */ 4024 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4025 4026 /* Perform LO and IQ calibrations. */ 4027 urtwn_iq_calib(sc); 4028 /* Perform LC calibration. */ 4029 urtwn_lc_calib(sc); 4030 4031 /* Fix USB interference issue. */ 4032 if (!(sc->chip & URTWN_CHIP_88E)) { 4033 urtwn_write_1(sc, 0xfe40, 0xe0); 4034 urtwn_write_1(sc, 0xfe41, 0x8d); 4035 urtwn_write_1(sc, 0xfe42, 0x80); 4036 4037 urtwn_pa_bias_init(sc); 4038 } 4039 4040 /* Initialize GPIO setting. */ 4041 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 4042 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 4043 4044 /* Fix for lower temperature. */ 4045 if (!(sc->chip & URTWN_CHIP_88E)) 4046 urtwn_write_1(sc, 0x15, 0xe9); 4047 4048 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 4049 4050 sc->sc_flags |= URTWN_RUNNING; 4051 4052 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4053fail: 4054 if (usb_err != USB_ERR_NORMAL_COMPLETION) 4055 error = EIO; 4056 4057 URTWN_UNLOCK(sc); 4058 4059 return (error); 4060} 4061 4062static void 4063urtwn_stop(struct urtwn_softc *sc) 4064{ 4065 4066 URTWN_LOCK(sc); 4067 if (!(sc->sc_flags & URTWN_RUNNING)) { 4068 URTWN_UNLOCK(sc); 4069 return; 4070 } 4071 4072 sc->sc_flags &= ~URTWN_RUNNING; 4073 callout_stop(&sc->sc_watchdog_ch); 4074 urtwn_abort_xfers(sc); 4075 4076 urtwn_drain_mbufq(sc); 4077 URTWN_UNLOCK(sc); 4078} 4079 4080static void 4081urtwn_abort_xfers(struct urtwn_softc *sc) 4082{ 4083 int i; 4084 4085 URTWN_ASSERT_LOCKED(sc); 4086 4087 /* abort any pending transfers */ 4088 for (i = 0; i < URTWN_N_TRANSFER; i++) 4089 usbd_transfer_stop(sc->sc_xfer[i]); 4090} 4091 4092static int 4093urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4094 const struct ieee80211_bpf_params *params) 4095{ 4096 struct ieee80211com *ic = ni->ni_ic; 4097 struct urtwn_softc *sc = ic->ic_softc; 4098 struct urtwn_data *bf; 4099 int error; 4100 4101 /* prevent management frames from being sent if we're not ready */ 4102 URTWN_LOCK(sc); 4103 if (!(sc->sc_flags & URTWN_RUNNING)) { 4104 error = ENETDOWN; 4105 goto end; 4106 } 4107 4108 bf = urtwn_getbuf(sc); 4109 if (bf == NULL) { 4110 error = ENOBUFS; 4111 goto end; 4112 } 4113 4114 if ((error = urtwn_tx_data(sc, ni, m, bf)) != 0) { 4115 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 4116 goto end; 4117 } 4118 4119 sc->sc_txtimer = 5; 4120 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 4121 4122end: 4123 if (error != 0) 4124 m_freem(m); 4125 4126 URTWN_UNLOCK(sc); 4127 4128 return (error); 4129} 4130 4131static void 4132urtwn_ms_delay(struct urtwn_softc *sc) 4133{ 4134 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 4135} 4136 4137static device_method_t urtwn_methods[] = { 4138 /* Device interface */ 4139 DEVMETHOD(device_probe, urtwn_match), 4140 DEVMETHOD(device_attach, urtwn_attach), 4141 DEVMETHOD(device_detach, urtwn_detach), 4142 4143 DEVMETHOD_END 4144}; 4145 4146static driver_t urtwn_driver = { 4147 "urtwn", 4148 urtwn_methods, 4149 sizeof(struct urtwn_softc) 4150}; 4151 4152static devclass_t urtwn_devclass; 4153 4154DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 4155MODULE_DEPEND(urtwn, usb, 1, 1, 1); 4156MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 4157MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 4158MODULE_VERSION(urtwn, 1); 4159