if_urtwn.c revision 290651
1251538Srpaulo/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2251538Srpaulo 3251538Srpaulo/*- 4251538Srpaulo * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5264912Skevlo * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6251538Srpaulo * 7251538Srpaulo * Permission to use, copy, modify, and distribute this software for any 8251538Srpaulo * purpose with or without fee is hereby granted, provided that the above 9251538Srpaulo * copyright notice and this permission notice appear in all copies. 10251538Srpaulo * 11251538Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12251538Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13251538Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14251538Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15251538Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16251538Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17251538Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18251538Srpaulo */ 19251538Srpaulo 20251538Srpaulo#include <sys/cdefs.h> 21251538Srpaulo__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 290651 2015-11-10 12:52:26Z avos $"); 22251538Srpaulo 23251538Srpaulo/* 24264912Skevlo * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25251538Srpaulo */ 26251538Srpaulo 27288353Sadrian#include "opt_wlan.h" 28288353Sadrian 29251538Srpaulo#include <sys/param.h> 30251538Srpaulo#include <sys/sockio.h> 31251538Srpaulo#include <sys/sysctl.h> 32251538Srpaulo#include <sys/lock.h> 33251538Srpaulo#include <sys/mutex.h> 34251538Srpaulo#include <sys/mbuf.h> 35251538Srpaulo#include <sys/kernel.h> 36251538Srpaulo#include <sys/socket.h> 37251538Srpaulo#include <sys/systm.h> 38251538Srpaulo#include <sys/malloc.h> 39251538Srpaulo#include <sys/module.h> 40251538Srpaulo#include <sys/bus.h> 41251538Srpaulo#include <sys/endian.h> 42251538Srpaulo#include <sys/linker.h> 43251538Srpaulo#include <sys/firmware.h> 44251538Srpaulo#include <sys/kdb.h> 45251538Srpaulo 46251538Srpaulo#include <machine/bus.h> 47251538Srpaulo#include <machine/resource.h> 48251538Srpaulo#include <sys/rman.h> 49251538Srpaulo 50251538Srpaulo#include <net/bpf.h> 51251538Srpaulo#include <net/if.h> 52257176Sglebius#include <net/if_var.h> 53251538Srpaulo#include <net/if_arp.h> 54251538Srpaulo#include <net/ethernet.h> 55251538Srpaulo#include <net/if_dl.h> 56251538Srpaulo#include <net/if_media.h> 57251538Srpaulo#include <net/if_types.h> 58251538Srpaulo 59251538Srpaulo#include <netinet/in.h> 60251538Srpaulo#include <netinet/in_systm.h> 61251538Srpaulo#include <netinet/in_var.h> 62251538Srpaulo#include <netinet/if_ether.h> 63251538Srpaulo#include <netinet/ip.h> 64251538Srpaulo 65251538Srpaulo#include <net80211/ieee80211_var.h> 66288088Sadrian#include <net80211/ieee80211_input.h> 67251538Srpaulo#include <net80211/ieee80211_regdomain.h> 68251538Srpaulo#include <net80211/ieee80211_radiotap.h> 69251538Srpaulo#include <net80211/ieee80211_ratectl.h> 70251538Srpaulo 71251538Srpaulo#include <dev/usb/usb.h> 72251538Srpaulo#include <dev/usb/usbdi.h> 73251538Srpaulo#include "usbdevs.h" 74251538Srpaulo 75251538Srpaulo#define USB_DEBUG_VAR urtwn_debug 76251538Srpaulo#include <dev/usb/usb_debug.h> 77251538Srpaulo 78251538Srpaulo#include <dev/usb/wlan/if_urtwnreg.h> 79289167Sadrian#include <dev/usb/wlan/if_urtwnvar.h> 80251538Srpaulo 81251538Srpaulo#ifdef USB_DEBUG 82251538Srpaulostatic int urtwn_debug = 0; 83251538Srpaulo 84251538SrpauloSYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 85276701ShselaskySYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 86251538Srpaulo "Debug level"); 87251538Srpaulo#endif 88251538Srpaulo 89288088Sadrian#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 90251538Srpaulo 91251538Srpaulo/* various supported device vendors/products */ 92251596Srpaulostatic const STRUCT_USB_HOST_ID urtwn_devs[] = { 93251538Srpaulo#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 94264912Skevlo#define URTWN_RTL8188E_DEV(v,p) \ 95264912Skevlo { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 96264912Skevlo#define URTWN_RTL8188E 1 97251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_1), 98251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_2), 99251538Srpaulo URTWN_DEV(ABOCOM, RTL8192CU), 100251538Srpaulo URTWN_DEV(ASUS, RTL8192CU), 101266721Skevlo URTWN_DEV(ASUS, USBN10NANO), 102251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_1), 103251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_2), 104251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CU), 105251538Srpaulo URTWN_DEV(BELKIN, F7D2102), 106251538Srpaulo URTWN_DEV(BELKIN, RTL8188CU), 107251538Srpaulo URTWN_DEV(BELKIN, RTL8192CU), 108251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_1), 109251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_2), 110251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_3), 111251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_4), 112251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_5), 113251538Srpaulo URTWN_DEV(COREGA, RTL8192CU), 114251538Srpaulo URTWN_DEV(DLINK, RTL8188CU), 115251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_1), 116251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_2), 117251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_3), 118252196Skevlo URTWN_DEV(DLINK, DWA131B), 119251538Srpaulo URTWN_DEV(EDIMAX, EW7811UN), 120251538Srpaulo URTWN_DEV(EDIMAX, RTL8192CU), 121251538Srpaulo URTWN_DEV(FEIXUN, RTL8188CU), 122251538Srpaulo URTWN_DEV(FEIXUN, RTL8192CU), 123251538Srpaulo URTWN_DEV(GUILLEMOT, HWNUP150), 124251538Srpaulo URTWN_DEV(HAWKING, RTL8192CU), 125251538Srpaulo URTWN_DEV(HP3, RTL8188CU), 126251538Srpaulo URTWN_DEV(NETGEAR, WNA1000M), 127251538Srpaulo URTWN_DEV(NETGEAR, RTL8192CU), 128251538Srpaulo URTWN_DEV(NETGEAR4, RTL8188CU), 129251538Srpaulo URTWN_DEV(NOVATECH, RTL8188CU), 130251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_1), 131251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_2), 132251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_3), 133251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_4), 134251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CUS), 135251538Srpaulo URTWN_DEV(PLANEX2, RTL8192CU), 136251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_0), 137251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_1), 138251538Srpaulo URTWN_DEV(REALTEK, RTL8188CTV), 139251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_0), 140251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_1), 141251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_2), 142282119Skevlo URTWN_DEV(REALTEK, RTL8188CU_3), 143251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_COMBO), 144251538Srpaulo URTWN_DEV(REALTEK, RTL8188CUS), 145251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_1), 146251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_2), 147272410Shselasky URTWN_DEV(REALTEK, RTL8188RU_3), 148251538Srpaulo URTWN_DEV(REALTEK, RTL8191CU), 149251538Srpaulo URTWN_DEV(REALTEK, RTL8192CE), 150251538Srpaulo URTWN_DEV(REALTEK, RTL8192CU), 151251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_1), 152251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_2), 153251538Srpaulo URTWN_DEV(SITECOMEU, RTL8192CU), 154251538Srpaulo URTWN_DEV(TRENDNET, RTL8188CU), 155251538Srpaulo URTWN_DEV(TRENDNET, RTL8192CU), 156251538Srpaulo URTWN_DEV(ZYXEL, RTL8192CU), 157264912Skevlo /* URTWN_RTL8188E */ 158273589Skevlo URTWN_RTL8188E_DEV(DLINK, DWA123D1), 159270191Skevlo URTWN_RTL8188E_DEV(DLINK, DWA125D1), 160273589Skevlo URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 161264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 162264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 163264912Skevlo#undef URTWN_RTL8188E_DEV 164251538Srpaulo#undef URTWN_DEV 165251538Srpaulo}; 166251538Srpaulo 167251538Srpaulostatic device_probe_t urtwn_match; 168251538Srpaulostatic device_attach_t urtwn_attach; 169251538Srpaulostatic device_detach_t urtwn_detach; 170251538Srpaulo 171251538Srpaulostatic usb_callback_t urtwn_bulk_tx_callback; 172251538Srpaulostatic usb_callback_t urtwn_bulk_rx_callback; 173251538Srpaulo 174288353Sadrianstatic void urtwn_drain_mbufq(struct urtwn_softc *sc); 175287197Sglebiusstatic usb_error_t urtwn_do_request(struct urtwn_softc *, 176287197Sglebius struct usb_device_request *, void *); 177251538Srpaulostatic struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 178251538Srpaulo const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 179251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN], 180251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN]); 181251538Srpaulostatic void urtwn_vap_delete(struct ieee80211vap *); 182281069Srpaulostatic struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 183251538Srpaulo int *); 184281069Srpaulostatic struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 185251538Srpaulo int *, int8_t *); 186289891Savosstatic void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 187289891Savos int); 188281069Srpaulostatic int urtwn_alloc_list(struct urtwn_softc *, 189251538Srpaulo struct urtwn_data[], int, int); 190251538Srpaulostatic int urtwn_alloc_rx_list(struct urtwn_softc *); 191251538Srpaulostatic int urtwn_alloc_tx_list(struct urtwn_softc *); 192251538Srpaulostatic void urtwn_free_list(struct urtwn_softc *, 193251538Srpaulo struct urtwn_data data[], int); 194289066Skevlostatic void urtwn_free_rx_list(struct urtwn_softc *); 195289066Skevlostatic void urtwn_free_tx_list(struct urtwn_softc *); 196251538Srpaulostatic struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 197251538Srpaulostatic struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 198281069Srpaulostatic int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 199251538Srpaulo uint8_t *, int); 200251538Srpaulostatic void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 201251538Srpaulostatic void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 202251538Srpaulostatic void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 203281069Srpaulostatic int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 204251538Srpaulo uint8_t *, int); 205251538Srpaulostatic uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 206251538Srpaulostatic uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 207251538Srpaulostatic uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 208281069Srpaulostatic int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 209251538Srpaulo const void *, int); 210264912Skevlostatic void urtwn_r92c_rf_write(struct urtwn_softc *, int, 211264912Skevlo uint8_t, uint32_t); 212281069Srpaulostatic void urtwn_r88e_rf_write(struct urtwn_softc *, int, 213264912Skevlo uint8_t, uint32_t); 214251538Srpaulostatic uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 215281069Srpaulostatic int urtwn_llt_write(struct urtwn_softc *, uint32_t, 216251538Srpaulo uint32_t); 217251538Srpaulostatic uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 218251538Srpaulostatic void urtwn_efuse_read(struct urtwn_softc *); 219264912Skevlostatic void urtwn_efuse_switch_power(struct urtwn_softc *); 220251538Srpaulostatic int urtwn_read_chipid(struct urtwn_softc *); 221251538Srpaulostatic void urtwn_read_rom(struct urtwn_softc *); 222264912Skevlostatic void urtwn_r88e_read_rom(struct urtwn_softc *); 223251538Srpaulostatic int urtwn_ra_init(struct urtwn_softc *); 224290631Savosstatic void urtwn_init_beacon(struct urtwn_softc *, 225290631Savos struct urtwn_vap *); 226290631Savosstatic int urtwn_setup_beacon(struct urtwn_softc *, 227290631Savos struct ieee80211_node *); 228290631Savosstatic void urtwn_update_beacon(struct ieee80211vap *, int); 229290631Savosstatic int urtwn_tx_beacon(struct urtwn_softc *sc, 230290631Savos struct urtwn_vap *); 231290651Savosstatic void urtwn_tsf_task_adhoc(void *, int); 232290631Savosstatic void urtwn_tsf_sync_enable(struct urtwn_softc *, 233290631Savos struct ieee80211vap *); 234251538Srpaulostatic void urtwn_set_led(struct urtwn_softc *, int, int); 235289811Savosstatic void urtwn_set_mode(struct urtwn_softc *, uint8_t); 236290651Savosstatic void urtwn_ibss_recv_mgmt(struct ieee80211_node *, 237290651Savos struct mbuf *, int, 238290651Savos const struct ieee80211_rx_stats *, int, int); 239281069Srpaulostatic int urtwn_newstate(struct ieee80211vap *, 240251538Srpaulo enum ieee80211_state, int); 241251538Srpaulostatic void urtwn_watchdog(void *); 242251538Srpaulostatic void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 243251538Srpaulostatic int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 244264912Skevlostatic int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 245290630Savosstatic int urtwn_tx_data(struct urtwn_softc *, 246251538Srpaulo struct ieee80211_node *, struct mbuf *, 247251538Srpaulo struct urtwn_data *); 248290630Savosstatic void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 249290630Savos uint8_t, struct urtwn_data *); 250287197Sglebiusstatic int urtwn_transmit(struct ieee80211com *, struct mbuf *); 251287197Sglebiusstatic void urtwn_start(struct urtwn_softc *); 252287197Sglebiusstatic void urtwn_parent(struct ieee80211com *); 253264912Skevlostatic int urtwn_r92c_power_on(struct urtwn_softc *); 254264912Skevlostatic int urtwn_r88e_power_on(struct urtwn_softc *); 255251538Srpaulostatic int urtwn_llt_init(struct urtwn_softc *); 256251538Srpaulostatic void urtwn_fw_reset(struct urtwn_softc *); 257264912Skevlostatic void urtwn_r88e_fw_reset(struct urtwn_softc *); 258281069Srpaulostatic int urtwn_fw_loadpage(struct urtwn_softc *, int, 259251538Srpaulo const uint8_t *, int); 260251538Srpaulostatic int urtwn_load_firmware(struct urtwn_softc *); 261264912Skevlostatic int urtwn_r92c_dma_init(struct urtwn_softc *); 262264912Skevlostatic int urtwn_r88e_dma_init(struct urtwn_softc *); 263251538Srpaulostatic void urtwn_mac_init(struct urtwn_softc *); 264251538Srpaulostatic void urtwn_bb_init(struct urtwn_softc *); 265251538Srpaulostatic void urtwn_rf_init(struct urtwn_softc *); 266251538Srpaulostatic void urtwn_cam_init(struct urtwn_softc *); 267251538Srpaulostatic void urtwn_pa_bias_init(struct urtwn_softc *); 268251538Srpaulostatic void urtwn_rxfilter_init(struct urtwn_softc *); 269251538Srpaulostatic void urtwn_edca_init(struct urtwn_softc *); 270281069Srpaulostatic void urtwn_write_txpower(struct urtwn_softc *, int, 271251538Srpaulo uint16_t[]); 272251538Srpaulostatic void urtwn_get_txpower(struct urtwn_softc *, int, 273281069Srpaulo struct ieee80211_channel *, 274251538Srpaulo struct ieee80211_channel *, uint16_t[]); 275264912Skevlostatic void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 276281069Srpaulo struct ieee80211_channel *, 277264912Skevlo struct ieee80211_channel *, uint16_t[]); 278251538Srpaulostatic void urtwn_set_txpower(struct urtwn_softc *, 279281069Srpaulo struct ieee80211_channel *, 280251538Srpaulo struct ieee80211_channel *); 281290048Savosstatic void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 282290048Savosstatic void urtwn_set_gain(struct urtwn_softc *, uint8_t); 283251538Srpaulostatic void urtwn_scan_start(struct ieee80211com *); 284251538Srpaulostatic void urtwn_scan_end(struct ieee80211com *); 285251538Srpaulostatic void urtwn_set_channel(struct ieee80211com *); 286290564Savosstatic void urtwn_set_promisc(struct urtwn_softc *); 287290564Savosstatic void urtwn_update_promisc(struct ieee80211com *); 288289066Skevlostatic void urtwn_update_mcast(struct ieee80211com *); 289251538Srpaulostatic void urtwn_set_chan(struct urtwn_softc *, 290281069Srpaulo struct ieee80211_channel *, 291251538Srpaulo struct ieee80211_channel *); 292251538Srpaulostatic void urtwn_iq_calib(struct urtwn_softc *); 293251538Srpaulostatic void urtwn_lc_calib(struct urtwn_softc *); 294287197Sglebiusstatic void urtwn_init(struct urtwn_softc *); 295287197Sglebiusstatic void urtwn_stop(struct urtwn_softc *); 296251538Srpaulostatic void urtwn_abort_xfers(struct urtwn_softc *); 297251538Srpaulostatic int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 298251538Srpaulo const struct ieee80211_bpf_params *); 299266472Shselaskystatic void urtwn_ms_delay(struct urtwn_softc *); 300251538Srpaulo 301251538Srpaulo/* Aliases. */ 302251538Srpaulo#define urtwn_bb_write urtwn_write_4 303251538Srpaulo#define urtwn_bb_read urtwn_read_4 304251538Srpaulo 305251538Srpaulostatic const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 306251538Srpaulo [URTWN_BULK_RX] = { 307251538Srpaulo .type = UE_BULK, 308251538Srpaulo .endpoint = UE_ADDR_ANY, 309251538Srpaulo .direction = UE_DIR_IN, 310251538Srpaulo .bufsize = URTWN_RXBUFSZ, 311251538Srpaulo .flags = { 312251538Srpaulo .pipe_bof = 1, 313251538Srpaulo .short_xfer_ok = 1 314251538Srpaulo }, 315251538Srpaulo .callback = urtwn_bulk_rx_callback, 316251538Srpaulo }, 317251538Srpaulo [URTWN_BULK_TX_BE] = { 318251538Srpaulo .type = UE_BULK, 319251538Srpaulo .endpoint = 0x03, 320251538Srpaulo .direction = UE_DIR_OUT, 321251538Srpaulo .bufsize = URTWN_TXBUFSZ, 322251538Srpaulo .flags = { 323251538Srpaulo .ext_buffer = 1, 324251538Srpaulo .pipe_bof = 1, 325251538Srpaulo .force_short_xfer = 1 326251538Srpaulo }, 327251538Srpaulo .callback = urtwn_bulk_tx_callback, 328251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 329251538Srpaulo }, 330251538Srpaulo [URTWN_BULK_TX_BK] = { 331251538Srpaulo .type = UE_BULK, 332251538Srpaulo .endpoint = 0x03, 333251538Srpaulo .direction = UE_DIR_OUT, 334251538Srpaulo .bufsize = URTWN_TXBUFSZ, 335251538Srpaulo .flags = { 336251538Srpaulo .ext_buffer = 1, 337251538Srpaulo .pipe_bof = 1, 338251538Srpaulo .force_short_xfer = 1, 339251538Srpaulo }, 340251538Srpaulo .callback = urtwn_bulk_tx_callback, 341251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 342251538Srpaulo }, 343251538Srpaulo [URTWN_BULK_TX_VI] = { 344251538Srpaulo .type = UE_BULK, 345251538Srpaulo .endpoint = 0x02, 346251538Srpaulo .direction = UE_DIR_OUT, 347251538Srpaulo .bufsize = URTWN_TXBUFSZ, 348251538Srpaulo .flags = { 349251538Srpaulo .ext_buffer = 1, 350251538Srpaulo .pipe_bof = 1, 351251538Srpaulo .force_short_xfer = 1 352251538Srpaulo }, 353251538Srpaulo .callback = urtwn_bulk_tx_callback, 354251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 355251538Srpaulo }, 356251538Srpaulo [URTWN_BULK_TX_VO] = { 357251538Srpaulo .type = UE_BULK, 358251538Srpaulo .endpoint = 0x02, 359251538Srpaulo .direction = UE_DIR_OUT, 360251538Srpaulo .bufsize = URTWN_TXBUFSZ, 361251538Srpaulo .flags = { 362251538Srpaulo .ext_buffer = 1, 363251538Srpaulo .pipe_bof = 1, 364251538Srpaulo .force_short_xfer = 1 365251538Srpaulo }, 366251538Srpaulo .callback = urtwn_bulk_tx_callback, 367251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 368251538Srpaulo }, 369251538Srpaulo}; 370251538Srpaulo 371251538Srpaulostatic int 372251538Srpaulourtwn_match(device_t self) 373251538Srpaulo{ 374251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 375251538Srpaulo 376251538Srpaulo if (uaa->usb_mode != USB_MODE_HOST) 377251538Srpaulo return (ENXIO); 378251538Srpaulo if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 379251538Srpaulo return (ENXIO); 380251538Srpaulo if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 381251538Srpaulo return (ENXIO); 382251538Srpaulo 383251538Srpaulo return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 384251538Srpaulo} 385251538Srpaulo 386251538Srpaulostatic int 387251538Srpaulourtwn_attach(device_t self) 388251538Srpaulo{ 389251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 390251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 391287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 392251538Srpaulo uint8_t iface_index, bands; 393251538Srpaulo int error; 394251538Srpaulo 395251538Srpaulo device_set_usb_desc(self); 396251538Srpaulo sc->sc_udev = uaa->device; 397251538Srpaulo sc->sc_dev = self; 398264912Skevlo if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 399264912Skevlo sc->chip |= URTWN_CHIP_88E; 400251538Srpaulo 401251538Srpaulo mtx_init(&sc->sc_mtx, device_get_nameunit(self), 402251538Srpaulo MTX_NETWORK_LOCK, MTX_DEF); 403251538Srpaulo callout_init(&sc->sc_watchdog_ch, 0); 404287197Sglebius mbufq_init(&sc->sc_snd, ifqmaxlen); 405251538Srpaulo 406251538Srpaulo iface_index = URTWN_IFACE_INDEX; 407251538Srpaulo error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 408251538Srpaulo urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 409251538Srpaulo if (error) { 410251538Srpaulo device_printf(self, "could not allocate USB transfers, " 411251538Srpaulo "err=%s\n", usbd_errstr(error)); 412251538Srpaulo goto detach; 413251538Srpaulo } 414251538Srpaulo 415251538Srpaulo URTWN_LOCK(sc); 416251538Srpaulo 417251538Srpaulo error = urtwn_read_chipid(sc); 418251538Srpaulo if (error) { 419251538Srpaulo device_printf(sc->sc_dev, "unsupported test chip\n"); 420251538Srpaulo URTWN_UNLOCK(sc); 421251538Srpaulo goto detach; 422251538Srpaulo } 423251538Srpaulo 424251538Srpaulo /* Determine number of Tx/Rx chains. */ 425251538Srpaulo if (sc->chip & URTWN_CHIP_92C) { 426251538Srpaulo sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 427251538Srpaulo sc->nrxchains = 2; 428251538Srpaulo } else { 429251538Srpaulo sc->ntxchains = 1; 430251538Srpaulo sc->nrxchains = 1; 431251538Srpaulo } 432251538Srpaulo 433264912Skevlo if (sc->chip & URTWN_CHIP_88E) 434264912Skevlo urtwn_r88e_read_rom(sc); 435264912Skevlo else 436264912Skevlo urtwn_read_rom(sc); 437264912Skevlo 438251538Srpaulo device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 439251538Srpaulo (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 440264912Skevlo (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 441251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 442251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 443251538Srpaulo "8188CUS", sc->ntxchains, sc->nrxchains); 444251538Srpaulo 445251538Srpaulo URTWN_UNLOCK(sc); 446251538Srpaulo 447283537Sglebius ic->ic_softc = sc; 448283527Sglebius ic->ic_name = device_get_nameunit(self); 449251538Srpaulo ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 450251538Srpaulo ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 451251538Srpaulo 452251538Srpaulo /* set device capabilities */ 453251538Srpaulo ic->ic_caps = 454251538Srpaulo IEEE80211_C_STA /* station mode */ 455251538Srpaulo | IEEE80211_C_MONITOR /* monitor mode */ 456290651Savos | IEEE80211_C_IBSS /* adhoc mode */ 457290631Savos | IEEE80211_C_HOSTAP /* hostap mode */ 458251538Srpaulo | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 459251538Srpaulo | IEEE80211_C_SHSLOT /* short slot time supported */ 460251538Srpaulo | IEEE80211_C_BGSCAN /* capable of bg scanning */ 461251538Srpaulo | IEEE80211_C_WPA /* 802.11i */ 462251538Srpaulo ; 463251538Srpaulo 464251538Srpaulo bands = 0; 465251538Srpaulo setbit(&bands, IEEE80211_MODE_11B); 466251538Srpaulo setbit(&bands, IEEE80211_MODE_11G); 467251538Srpaulo ieee80211_init_channels(ic, NULL, &bands); 468251538Srpaulo 469287197Sglebius ieee80211_ifattach(ic); 470251538Srpaulo ic->ic_raw_xmit = urtwn_raw_xmit; 471251538Srpaulo ic->ic_scan_start = urtwn_scan_start; 472251538Srpaulo ic->ic_scan_end = urtwn_scan_end; 473251538Srpaulo ic->ic_set_channel = urtwn_set_channel; 474287197Sglebius ic->ic_transmit = urtwn_transmit; 475287197Sglebius ic->ic_parent = urtwn_parent; 476251538Srpaulo ic->ic_vap_create = urtwn_vap_create; 477251538Srpaulo ic->ic_vap_delete = urtwn_vap_delete; 478290564Savos ic->ic_update_promisc = urtwn_update_promisc; 479251538Srpaulo ic->ic_update_mcast = urtwn_update_mcast; 480251538Srpaulo 481281069Srpaulo ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 482251538Srpaulo sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 483251538Srpaulo &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 484251538Srpaulo URTWN_RX_RADIOTAP_PRESENT); 485251538Srpaulo 486251538Srpaulo if (bootverbose) 487251538Srpaulo ieee80211_announce(ic); 488251538Srpaulo 489251538Srpaulo return (0); 490251538Srpaulo 491251538Srpaulodetach: 492251538Srpaulo urtwn_detach(self); 493251538Srpaulo return (ENXIO); /* failure */ 494251538Srpaulo} 495251538Srpaulo 496251538Srpaulostatic int 497251538Srpaulourtwn_detach(device_t self) 498251538Srpaulo{ 499251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 500287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 501263153Skevlo unsigned int x; 502281069Srpaulo 503263153Skevlo /* Prevent further ioctls. */ 504263153Skevlo URTWN_LOCK(sc); 505263153Skevlo sc->sc_flags |= URTWN_DETACHED; 506287197Sglebius urtwn_stop(sc); 507263153Skevlo URTWN_UNLOCK(sc); 508251538Srpaulo 509251538Srpaulo callout_drain(&sc->sc_watchdog_ch); 510251538Srpaulo 511288353Sadrian /* stop all USB transfers */ 512288353Sadrian usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 513288353Sadrian 514263153Skevlo /* Prevent further allocations from RX/TX data lists. */ 515263153Skevlo URTWN_LOCK(sc); 516263153Skevlo STAILQ_INIT(&sc->sc_tx_active); 517263153Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 518263153Skevlo STAILQ_INIT(&sc->sc_tx_pending); 519263153Skevlo 520263153Skevlo STAILQ_INIT(&sc->sc_rx_active); 521263153Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 522263153Skevlo URTWN_UNLOCK(sc); 523263153Skevlo 524263153Skevlo /* drain USB transfers */ 525263153Skevlo for (x = 0; x != URTWN_N_TRANSFER; x++) 526263153Skevlo usbd_transfer_drain(sc->sc_xfer[x]); 527263153Skevlo 528263153Skevlo /* Free data buffers. */ 529263153Skevlo URTWN_LOCK(sc); 530263153Skevlo urtwn_free_tx_list(sc); 531263153Skevlo urtwn_free_rx_list(sc); 532263153Skevlo URTWN_UNLOCK(sc); 533263153Skevlo 534251538Srpaulo ieee80211_ifdetach(ic); 535251538Srpaulo mtx_destroy(&sc->sc_mtx); 536251538Srpaulo 537251538Srpaulo return (0); 538251538Srpaulo} 539251538Srpaulo 540251538Srpaulostatic void 541289066Skevlourtwn_drain_mbufq(struct urtwn_softc *sc) 542251538Srpaulo{ 543289066Skevlo struct mbuf *m; 544289066Skevlo struct ieee80211_node *ni; 545289066Skevlo URTWN_ASSERT_LOCKED(sc); 546289066Skevlo while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 547289066Skevlo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 548289066Skevlo m->m_pkthdr.rcvif = NULL; 549289066Skevlo ieee80211_free_node(ni); 550289066Skevlo m_freem(m); 551251538Srpaulo } 552251538Srpaulo} 553251538Srpaulo 554251538Srpaulostatic usb_error_t 555251538Srpaulourtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 556251538Srpaulo void *data) 557251538Srpaulo{ 558251538Srpaulo usb_error_t err; 559251538Srpaulo int ntries = 10; 560251538Srpaulo 561251538Srpaulo URTWN_ASSERT_LOCKED(sc); 562251538Srpaulo 563251538Srpaulo while (ntries--) { 564251538Srpaulo err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 565251538Srpaulo req, data, 0, NULL, 250 /* ms */); 566251538Srpaulo if (err == 0) 567251538Srpaulo break; 568251538Srpaulo 569251538Srpaulo DPRINTFN(1, "Control request failed, %s (retrying)\n", 570251538Srpaulo usbd_errstr(err)); 571251538Srpaulo usb_pause_mtx(&sc->sc_mtx, hz / 100); 572251538Srpaulo } 573251538Srpaulo return (err); 574251538Srpaulo} 575251538Srpaulo 576251538Srpaulostatic struct ieee80211vap * 577251538Srpaulourtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 578251538Srpaulo enum ieee80211_opmode opmode, int flags, 579251538Srpaulo const uint8_t bssid[IEEE80211_ADDR_LEN], 580251538Srpaulo const uint8_t mac[IEEE80211_ADDR_LEN]) 581251538Srpaulo{ 582290631Savos struct urtwn_softc *sc = ic->ic_softc; 583251538Srpaulo struct urtwn_vap *uvp; 584251538Srpaulo struct ieee80211vap *vap; 585251538Srpaulo 586251538Srpaulo if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 587251538Srpaulo return (NULL); 588251538Srpaulo 589287197Sglebius uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 590251538Srpaulo vap = &uvp->vap; 591251538Srpaulo /* enable s/w bmiss handling for sta mode */ 592251538Srpaulo 593281069Srpaulo if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 594287197Sglebius flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 595257743Shselasky /* out of memory */ 596257743Shselasky free(uvp, M_80211_VAP); 597257743Shselasky return (NULL); 598257743Shselasky } 599257743Shselasky 600290651Savos if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_IBSS) 601290631Savos urtwn_init_beacon(sc, uvp); 602290631Savos 603251538Srpaulo /* override state transition machine */ 604251538Srpaulo uvp->newstate = vap->iv_newstate; 605251538Srpaulo vap->iv_newstate = urtwn_newstate; 606290631Savos vap->iv_update_beacon = urtwn_update_beacon; 607290651Savos if (opmode == IEEE80211_M_IBSS) { 608290651Savos uvp->recv_mgmt = vap->iv_recv_mgmt; 609290651Savos vap->iv_recv_mgmt = urtwn_ibss_recv_mgmt; 610290651Savos TASK_INIT(&uvp->tsf_task_adhoc, 0, urtwn_tsf_task_adhoc, vap); 611290651Savos } 612251538Srpaulo 613251538Srpaulo /* complete setup */ 614251538Srpaulo ieee80211_vap_attach(vap, ieee80211_media_change, 615287197Sglebius ieee80211_media_status, mac); 616251538Srpaulo ic->ic_opmode = opmode; 617251538Srpaulo return (vap); 618251538Srpaulo} 619251538Srpaulo 620251538Srpaulostatic void 621251538Srpaulourtwn_vap_delete(struct ieee80211vap *vap) 622251538Srpaulo{ 623290651Savos struct ieee80211com *ic = vap->iv_ic; 624251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 625251538Srpaulo 626290651Savos if (uvp->bcn_mbuf != NULL) 627290651Savos m_freem(uvp->bcn_mbuf); 628290651Savos if (vap->iv_opmode == IEEE80211_M_IBSS) 629290651Savos ieee80211_draintask(ic, &uvp->tsf_task_adhoc); 630251538Srpaulo ieee80211_vap_detach(vap); 631251538Srpaulo free(uvp, M_80211_VAP); 632251538Srpaulo} 633251538Srpaulo 634251538Srpaulostatic struct mbuf * 635251538Srpaulourtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 636251538Srpaulo{ 637287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 638251538Srpaulo struct ieee80211_frame *wh; 639251538Srpaulo struct mbuf *m; 640251538Srpaulo struct r92c_rx_stat *stat; 641251538Srpaulo uint32_t rxdw0, rxdw3; 642251538Srpaulo uint8_t rate; 643251538Srpaulo int8_t rssi = 0; 644251538Srpaulo int infosz; 645251538Srpaulo 646251538Srpaulo /* 647251538Srpaulo * don't pass packets to the ieee80211 framework if the driver isn't 648251538Srpaulo * RUNNING. 649251538Srpaulo */ 650287197Sglebius if (!(sc->sc_flags & URTWN_RUNNING)) 651251538Srpaulo return (NULL); 652251538Srpaulo 653251538Srpaulo stat = (struct r92c_rx_stat *)buf; 654251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 655251538Srpaulo rxdw3 = le32toh(stat->rxdw3); 656251538Srpaulo 657251538Srpaulo if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 658251538Srpaulo /* 659251538Srpaulo * This should not happen since we setup our Rx filter 660251538Srpaulo * to not receive these frames. 661251538Srpaulo */ 662287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 663251538Srpaulo return (NULL); 664251538Srpaulo } 665290022Savos if (pktlen < sizeof(struct ieee80211_frame_ack) || 666290022Savos pktlen > MCLBYTES) { 667287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 668271303Skevlo return (NULL); 669271303Skevlo } 670251538Srpaulo 671251538Srpaulo rate = MS(rxdw3, R92C_RXDW3_RATE); 672251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 673251538Srpaulo 674251538Srpaulo /* Get RSSI from PHY status descriptor if present. */ 675251538Srpaulo if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 676281069Srpaulo if (sc->chip & URTWN_CHIP_88E) 677264912Skevlo rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 678264912Skevlo else 679264912Skevlo rssi = urtwn_get_rssi(sc, rate, &stat[1]); 680251538Srpaulo /* Update our average RSSI. */ 681251538Srpaulo urtwn_update_avgrssi(sc, rate, rssi); 682251538Srpaulo } 683251538Srpaulo 684260463Skevlo m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 685251538Srpaulo if (m == NULL) { 686251538Srpaulo device_printf(sc->sc_dev, "could not create RX mbuf\n"); 687251538Srpaulo return (NULL); 688251538Srpaulo } 689251538Srpaulo 690251538Srpaulo /* Finalize mbuf. */ 691251538Srpaulo wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 692251538Srpaulo memcpy(mtod(m, uint8_t *), wh, pktlen); 693251538Srpaulo m->m_pkthdr.len = m->m_len = pktlen; 694251538Srpaulo 695251538Srpaulo if (ieee80211_radiotap_active(ic)) { 696251538Srpaulo struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 697251538Srpaulo 698251538Srpaulo tap->wr_flags = 0; 699251538Srpaulo /* Map HW rate index to 802.11 rate. */ 700251538Srpaulo if (!(rxdw3 & R92C_RXDW3_HT)) { 701289758Savos tap->wr_rate = ridx2rate[rate]; 702251538Srpaulo } else if (rate >= 12) { /* MCS0~15. */ 703251538Srpaulo /* Bit 7 set means HT MCS instead of rate. */ 704251538Srpaulo tap->wr_rate = 0x80 | (rate - 12); 705251538Srpaulo } 706251538Srpaulo tap->wr_dbm_antsignal = rssi; 707289816Savos tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 708251538Srpaulo tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 709251538Srpaulo tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 710251538Srpaulo } 711251538Srpaulo 712251538Srpaulo *rssi_p = rssi; 713251538Srpaulo 714251538Srpaulo return (m); 715251538Srpaulo} 716251538Srpaulo 717251538Srpaulostatic struct mbuf * 718251538Srpaulourtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 719251538Srpaulo int8_t *nf) 720251538Srpaulo{ 721251538Srpaulo struct urtwn_softc *sc = data->sc; 722287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 723251538Srpaulo struct r92c_rx_stat *stat; 724251538Srpaulo struct mbuf *m, *m0 = NULL, *prevm = NULL; 725251538Srpaulo uint32_t rxdw0; 726251538Srpaulo uint8_t *buf; 727251538Srpaulo int len, totlen, pktlen, infosz, npkts; 728251538Srpaulo 729251538Srpaulo usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 730251538Srpaulo 731251538Srpaulo if (len < sizeof(*stat)) { 732287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 733251538Srpaulo return (NULL); 734251538Srpaulo } 735251538Srpaulo 736251538Srpaulo buf = data->buf; 737251538Srpaulo /* Get the number of encapsulated frames. */ 738251538Srpaulo stat = (struct r92c_rx_stat *)buf; 739251538Srpaulo npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 740251538Srpaulo DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 741251538Srpaulo 742251538Srpaulo /* Process all of them. */ 743251538Srpaulo while (npkts-- > 0) { 744251538Srpaulo if (len < sizeof(*stat)) 745251538Srpaulo break; 746251538Srpaulo stat = (struct r92c_rx_stat *)buf; 747251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 748251538Srpaulo 749251538Srpaulo pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 750251538Srpaulo if (pktlen == 0) 751251538Srpaulo break; 752251538Srpaulo 753251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 754251538Srpaulo 755251538Srpaulo /* Make sure everything fits in xfer. */ 756251538Srpaulo totlen = sizeof(*stat) + infosz + pktlen; 757251538Srpaulo if (totlen > len) 758251538Srpaulo break; 759251538Srpaulo 760251538Srpaulo m = urtwn_rx_frame(sc, buf, pktlen, rssi); 761251538Srpaulo if (m0 == NULL) 762251538Srpaulo m0 = m; 763251538Srpaulo if (prevm == NULL) 764251538Srpaulo prevm = m; 765251538Srpaulo else { 766251538Srpaulo prevm->m_next = m; 767251538Srpaulo prevm = m; 768251538Srpaulo } 769251538Srpaulo 770251538Srpaulo /* Next chunk is 128-byte aligned. */ 771251538Srpaulo totlen = (totlen + 127) & ~127; 772251538Srpaulo buf += totlen; 773251538Srpaulo len -= totlen; 774251538Srpaulo } 775251538Srpaulo 776251538Srpaulo return (m0); 777251538Srpaulo} 778251538Srpaulo 779251538Srpaulostatic void 780251538Srpaulourtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 781251538Srpaulo{ 782251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 783287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 784290022Savos struct ieee80211_frame_min *wh; 785251538Srpaulo struct ieee80211_node *ni; 786251538Srpaulo struct mbuf *m = NULL, *next; 787251538Srpaulo struct urtwn_data *data; 788251538Srpaulo int8_t nf; 789251538Srpaulo int rssi = 1; 790251538Srpaulo 791251538Srpaulo URTWN_ASSERT_LOCKED(sc); 792251538Srpaulo 793251538Srpaulo switch (USB_GET_STATE(xfer)) { 794251538Srpaulo case USB_ST_TRANSFERRED: 795251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 796251538Srpaulo if (data == NULL) 797251538Srpaulo goto tr_setup; 798251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 799251538Srpaulo m = urtwn_rxeof(xfer, data, &rssi, &nf); 800251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 801251538Srpaulo /* FALLTHROUGH */ 802251538Srpaulo case USB_ST_SETUP: 803251538Srpaulotr_setup: 804251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_inactive); 805251538Srpaulo if (data == NULL) { 806251538Srpaulo KASSERT(m == NULL, ("mbuf isn't NULL")); 807251538Srpaulo return; 808251538Srpaulo } 809251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 810251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 811251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, 812251538Srpaulo usbd_xfer_max_len(xfer)); 813251538Srpaulo usbd_transfer_submit(xfer); 814251538Srpaulo 815251538Srpaulo /* 816251538Srpaulo * To avoid LOR we should unlock our private mutex here to call 817251538Srpaulo * ieee80211_input() because here is at the end of a USB 818251538Srpaulo * callback and safe to unlock. 819251538Srpaulo */ 820251538Srpaulo URTWN_UNLOCK(sc); 821251538Srpaulo while (m != NULL) { 822251538Srpaulo next = m->m_next; 823251538Srpaulo m->m_next = NULL; 824290022Savos wh = mtod(m, struct ieee80211_frame_min *); 825290022Savos if (m->m_len >= sizeof(*wh)) 826290022Savos ni = ieee80211_find_rxnode(ic, wh); 827290022Savos else 828290022Savos ni = NULL; 829251538Srpaulo nf = URTWN_NOISE_FLOOR; 830251538Srpaulo if (ni != NULL) { 831289799Savos (void)ieee80211_input(ni, m, rssi - nf, nf); 832251538Srpaulo ieee80211_free_node(ni); 833289799Savos } else { 834289799Savos (void)ieee80211_input_all(ic, m, rssi - nf, 835289799Savos nf); 836289799Savos } 837251538Srpaulo m = next; 838251538Srpaulo } 839251538Srpaulo URTWN_LOCK(sc); 840251538Srpaulo break; 841251538Srpaulo default: 842251538Srpaulo /* needs it to the inactive queue due to a error. */ 843251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 844251538Srpaulo if (data != NULL) { 845251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 846251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 847251538Srpaulo } 848251538Srpaulo if (error != USB_ERR_CANCELLED) { 849251538Srpaulo usbd_xfer_set_stall(xfer); 850287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 851251538Srpaulo goto tr_setup; 852251538Srpaulo } 853251538Srpaulo break; 854251538Srpaulo } 855251538Srpaulo} 856251538Srpaulo 857251538Srpaulostatic void 858289891Savosurtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 859251538Srpaulo{ 860251538Srpaulo 861251538Srpaulo URTWN_ASSERT_LOCKED(sc); 862289891Savos 863290631Savos if (data->ni != NULL) /* not a beacon frame */ 864290631Savos ieee80211_tx_complete(data->ni, data->m, status); 865289891Savos 866287197Sglebius data->ni = NULL; 867287197Sglebius data->m = NULL; 868289891Savos 869251538Srpaulo sc->sc_txtimer = 0; 870289891Savos 871289891Savos STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 872251538Srpaulo} 873251538Srpaulo 874289066Skevlostatic int 875289066Skevlourtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 876289066Skevlo int ndata, int maxsz) 877289066Skevlo{ 878289066Skevlo int i, error; 879289066Skevlo 880289066Skevlo for (i = 0; i < ndata; i++) { 881289066Skevlo struct urtwn_data *dp = &data[i]; 882289066Skevlo dp->sc = sc; 883289066Skevlo dp->m = NULL; 884289066Skevlo dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 885289066Skevlo if (dp->buf == NULL) { 886289066Skevlo device_printf(sc->sc_dev, 887289066Skevlo "could not allocate buffer\n"); 888289066Skevlo error = ENOMEM; 889289066Skevlo goto fail; 890289066Skevlo } 891289066Skevlo dp->ni = NULL; 892289066Skevlo } 893289066Skevlo 894289066Skevlo return (0); 895289066Skevlofail: 896289066Skevlo urtwn_free_list(sc, data, ndata); 897289066Skevlo return (error); 898289066Skevlo} 899289066Skevlo 900289066Skevlostatic int 901289066Skevlourtwn_alloc_rx_list(struct urtwn_softc *sc) 902289066Skevlo{ 903289066Skevlo int error, i; 904289066Skevlo 905289066Skevlo error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 906289066Skevlo URTWN_RXBUFSZ); 907289066Skevlo if (error != 0) 908289066Skevlo return (error); 909289066Skevlo 910289066Skevlo STAILQ_INIT(&sc->sc_rx_active); 911289066Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 912289066Skevlo 913289066Skevlo for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 914289066Skevlo STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 915289066Skevlo 916289066Skevlo return (0); 917289066Skevlo} 918289066Skevlo 919289066Skevlostatic int 920289066Skevlourtwn_alloc_tx_list(struct urtwn_softc *sc) 921289066Skevlo{ 922289066Skevlo int error, i; 923289066Skevlo 924289066Skevlo error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 925289066Skevlo URTWN_TXBUFSZ); 926289066Skevlo if (error != 0) 927289066Skevlo return (error); 928289066Skevlo 929289066Skevlo STAILQ_INIT(&sc->sc_tx_active); 930289066Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 931289066Skevlo STAILQ_INIT(&sc->sc_tx_pending); 932289066Skevlo 933289066Skevlo for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 934289066Skevlo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 935289066Skevlo 936289066Skevlo return (0); 937289066Skevlo} 938289066Skevlo 939251538Srpaulostatic void 940289066Skevlourtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 941289066Skevlo{ 942289066Skevlo int i; 943289066Skevlo 944289066Skevlo for (i = 0; i < ndata; i++) { 945289066Skevlo struct urtwn_data *dp = &data[i]; 946289066Skevlo 947289066Skevlo if (dp->buf != NULL) { 948289066Skevlo free(dp->buf, M_USBDEV); 949289066Skevlo dp->buf = NULL; 950289066Skevlo } 951289066Skevlo if (dp->ni != NULL) { 952289066Skevlo ieee80211_free_node(dp->ni); 953289066Skevlo dp->ni = NULL; 954289066Skevlo } 955289066Skevlo } 956289066Skevlo} 957289066Skevlo 958289066Skevlostatic void 959289066Skevlourtwn_free_rx_list(struct urtwn_softc *sc) 960289066Skevlo{ 961289066Skevlo urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 962289066Skevlo} 963289066Skevlo 964289066Skevlostatic void 965289066Skevlourtwn_free_tx_list(struct urtwn_softc *sc) 966289066Skevlo{ 967289066Skevlo urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 968289066Skevlo} 969289066Skevlo 970289066Skevlostatic void 971251538Srpaulourtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 972251538Srpaulo{ 973251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 974251538Srpaulo struct urtwn_data *data; 975251538Srpaulo 976251538Srpaulo URTWN_ASSERT_LOCKED(sc); 977251538Srpaulo 978251538Srpaulo switch (USB_GET_STATE(xfer)){ 979251538Srpaulo case USB_ST_TRANSFERRED: 980251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 981251538Srpaulo if (data == NULL) 982251538Srpaulo goto tr_setup; 983251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 984289891Savos urtwn_txeof(sc, data, 0); 985251538Srpaulo /* FALLTHROUGH */ 986251538Srpaulo case USB_ST_SETUP: 987251538Srpaulotr_setup: 988251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_pending); 989251538Srpaulo if (data == NULL) { 990251538Srpaulo DPRINTF("%s: empty pending queue\n", __func__); 991288353Sadrian goto finish; 992251538Srpaulo } 993251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 994251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 995251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 996251538Srpaulo usbd_transfer_submit(xfer); 997251538Srpaulo break; 998251538Srpaulo default: 999251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 1000251538Srpaulo if (data == NULL) 1001251538Srpaulo goto tr_setup; 1002289891Savos STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 1003289891Savos urtwn_txeof(sc, data, 1); 1004251538Srpaulo if (error != USB_ERR_CANCELLED) { 1005251538Srpaulo usbd_xfer_set_stall(xfer); 1006251538Srpaulo goto tr_setup; 1007251538Srpaulo } 1008251538Srpaulo break; 1009251538Srpaulo } 1010288353Sadrianfinish: 1011288353Sadrian /* Kick-start more transmit */ 1012288353Sadrian urtwn_start(sc); 1013251538Srpaulo} 1014251538Srpaulo 1015251538Srpaulostatic struct urtwn_data * 1016251538Srpaulo_urtwn_getbuf(struct urtwn_softc *sc) 1017251538Srpaulo{ 1018251538Srpaulo struct urtwn_data *bf; 1019251538Srpaulo 1020251538Srpaulo bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1021251538Srpaulo if (bf != NULL) 1022251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1023251538Srpaulo else 1024251538Srpaulo DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 1025251538Srpaulo return (bf); 1026251538Srpaulo} 1027251538Srpaulo 1028251538Srpaulostatic struct urtwn_data * 1029251538Srpaulourtwn_getbuf(struct urtwn_softc *sc) 1030251538Srpaulo{ 1031251538Srpaulo struct urtwn_data *bf; 1032251538Srpaulo 1033251538Srpaulo URTWN_ASSERT_LOCKED(sc); 1034251538Srpaulo 1035251538Srpaulo bf = _urtwn_getbuf(sc); 1036287197Sglebius if (bf == NULL) 1037251538Srpaulo DPRINTF("%s: stop queue\n", __func__); 1038251538Srpaulo return (bf); 1039251538Srpaulo} 1040251538Srpaulo 1041251538Srpaulostatic int 1042251538Srpaulourtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1043251538Srpaulo int len) 1044251538Srpaulo{ 1045251538Srpaulo usb_device_request_t req; 1046251538Srpaulo 1047251538Srpaulo req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1048251538Srpaulo req.bRequest = R92C_REQ_REGS; 1049251538Srpaulo USETW(req.wValue, addr); 1050251538Srpaulo USETW(req.wIndex, 0); 1051251538Srpaulo USETW(req.wLength, len); 1052251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 1053251538Srpaulo} 1054251538Srpaulo 1055251538Srpaulostatic void 1056251538Srpaulourtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1057251538Srpaulo{ 1058251538Srpaulo urtwn_write_region_1(sc, addr, &val, 1); 1059251538Srpaulo} 1060251538Srpaulo 1061251538Srpaulo 1062251538Srpaulostatic void 1063251538Srpaulourtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1064251538Srpaulo{ 1065251538Srpaulo val = htole16(val); 1066251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1067251538Srpaulo} 1068251538Srpaulo 1069251538Srpaulostatic void 1070251538Srpaulourtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1071251538Srpaulo{ 1072251538Srpaulo val = htole32(val); 1073251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1074251538Srpaulo} 1075251538Srpaulo 1076251538Srpaulostatic int 1077251538Srpaulourtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1078251538Srpaulo int len) 1079251538Srpaulo{ 1080251538Srpaulo usb_device_request_t req; 1081251538Srpaulo 1082251538Srpaulo req.bmRequestType = UT_READ_VENDOR_DEVICE; 1083251538Srpaulo req.bRequest = R92C_REQ_REGS; 1084251538Srpaulo USETW(req.wValue, addr); 1085251538Srpaulo USETW(req.wIndex, 0); 1086251538Srpaulo USETW(req.wLength, len); 1087251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 1088251538Srpaulo} 1089251538Srpaulo 1090251538Srpaulostatic uint8_t 1091251538Srpaulourtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1092251538Srpaulo{ 1093251538Srpaulo uint8_t val; 1094251538Srpaulo 1095251538Srpaulo if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1096251538Srpaulo return (0xff); 1097251538Srpaulo return (val); 1098251538Srpaulo} 1099251538Srpaulo 1100251538Srpaulostatic uint16_t 1101251538Srpaulourtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1102251538Srpaulo{ 1103251538Srpaulo uint16_t val; 1104251538Srpaulo 1105251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1106251538Srpaulo return (0xffff); 1107251538Srpaulo return (le16toh(val)); 1108251538Srpaulo} 1109251538Srpaulo 1110251538Srpaulostatic uint32_t 1111251538Srpaulourtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1112251538Srpaulo{ 1113251538Srpaulo uint32_t val; 1114251538Srpaulo 1115251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1116251538Srpaulo return (0xffffffff); 1117251538Srpaulo return (le32toh(val)); 1118251538Srpaulo} 1119251538Srpaulo 1120251538Srpaulostatic int 1121251538Srpaulourtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1122251538Srpaulo{ 1123251538Srpaulo struct r92c_fw_cmd cmd; 1124251538Srpaulo int ntries; 1125251538Srpaulo 1126251538Srpaulo /* Wait for current FW box to be empty. */ 1127251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1128251538Srpaulo if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1129251538Srpaulo break; 1130266472Shselasky urtwn_ms_delay(sc); 1131251538Srpaulo } 1132251538Srpaulo if (ntries == 100) { 1133251538Srpaulo device_printf(sc->sc_dev, 1134251538Srpaulo "could not send firmware command\n"); 1135251538Srpaulo return (ETIMEDOUT); 1136251538Srpaulo } 1137251538Srpaulo memset(&cmd, 0, sizeof(cmd)); 1138251538Srpaulo cmd.id = id; 1139251538Srpaulo if (len > 3) 1140251538Srpaulo cmd.id |= R92C_CMD_FLAG_EXT; 1141251538Srpaulo KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1142251538Srpaulo memcpy(cmd.msg, buf, len); 1143251538Srpaulo 1144251538Srpaulo /* Write the first word last since that will trigger the FW. */ 1145251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1146251538Srpaulo (uint8_t *)&cmd + 4, 2); 1147251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1148251538Srpaulo (uint8_t *)&cmd + 0, 4); 1149251538Srpaulo 1150251538Srpaulo sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1151251538Srpaulo return (0); 1152251538Srpaulo} 1153251538Srpaulo 1154264912Skevlostatic __inline void 1155251538Srpaulourtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1156251538Srpaulo{ 1157264912Skevlo 1158264912Skevlo sc->sc_rf_write(sc, chain, addr, val); 1159264912Skevlo} 1160264912Skevlo 1161264912Skevlostatic void 1162264912Skevlourtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1163264912Skevlo uint32_t val) 1164264912Skevlo{ 1165251538Srpaulo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1166251538Srpaulo SM(R92C_LSSI_PARAM_ADDR, addr) | 1167251538Srpaulo SM(R92C_LSSI_PARAM_DATA, val)); 1168251538Srpaulo} 1169251538Srpaulo 1170264912Skevlostatic void 1171264912Skevlourtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1172264912Skevlouint32_t val) 1173264912Skevlo{ 1174264912Skevlo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1175264912Skevlo SM(R88E_LSSI_PARAM_ADDR, addr) | 1176264912Skevlo SM(R92C_LSSI_PARAM_DATA, val)); 1177264912Skevlo} 1178264912Skevlo 1179251538Srpaulostatic uint32_t 1180251538Srpaulourtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1181251538Srpaulo{ 1182251538Srpaulo uint32_t reg[R92C_MAX_CHAINS], val; 1183251538Srpaulo 1184251538Srpaulo reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1185251538Srpaulo if (chain != 0) 1186251538Srpaulo reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1187251538Srpaulo 1188251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1189251538Srpaulo reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1190266472Shselasky urtwn_ms_delay(sc); 1191251538Srpaulo 1192251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1193251538Srpaulo RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1194251538Srpaulo R92C_HSSI_PARAM2_READ_EDGE); 1195266472Shselasky urtwn_ms_delay(sc); 1196251538Srpaulo 1197251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1198251538Srpaulo reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1199266472Shselasky urtwn_ms_delay(sc); 1200251538Srpaulo 1201251538Srpaulo if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1202251538Srpaulo val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1203251538Srpaulo else 1204251538Srpaulo val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1205251538Srpaulo return (MS(val, R92C_LSSI_READBACK_DATA)); 1206251538Srpaulo} 1207251538Srpaulo 1208251538Srpaulostatic int 1209251538Srpaulourtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1210251538Srpaulo{ 1211251538Srpaulo int ntries; 1212251538Srpaulo 1213251538Srpaulo urtwn_write_4(sc, R92C_LLT_INIT, 1214251538Srpaulo SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1215251538Srpaulo SM(R92C_LLT_INIT_ADDR, addr) | 1216251538Srpaulo SM(R92C_LLT_INIT_DATA, data)); 1217251538Srpaulo /* Wait for write operation to complete. */ 1218251538Srpaulo for (ntries = 0; ntries < 20; ntries++) { 1219251538Srpaulo if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1220251538Srpaulo R92C_LLT_INIT_OP_NO_ACTIVE) 1221251538Srpaulo return (0); 1222266472Shselasky urtwn_ms_delay(sc); 1223251538Srpaulo } 1224251538Srpaulo return (ETIMEDOUT); 1225251538Srpaulo} 1226251538Srpaulo 1227251538Srpaulostatic uint8_t 1228251538Srpaulourtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1229251538Srpaulo{ 1230251538Srpaulo uint32_t reg; 1231251538Srpaulo int ntries; 1232251538Srpaulo 1233251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1234251538Srpaulo reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1235251538Srpaulo reg &= ~R92C_EFUSE_CTRL_VALID; 1236251538Srpaulo urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1237251538Srpaulo /* Wait for read operation to complete. */ 1238251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1239251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1240251538Srpaulo if (reg & R92C_EFUSE_CTRL_VALID) 1241251538Srpaulo return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1242266472Shselasky urtwn_ms_delay(sc); 1243251538Srpaulo } 1244281069Srpaulo device_printf(sc->sc_dev, 1245251538Srpaulo "could not read efuse byte at address 0x%x\n", addr); 1246251538Srpaulo return (0xff); 1247251538Srpaulo} 1248251538Srpaulo 1249251538Srpaulostatic void 1250251538Srpaulourtwn_efuse_read(struct urtwn_softc *sc) 1251251538Srpaulo{ 1252251538Srpaulo uint8_t *rom = (uint8_t *)&sc->rom; 1253251538Srpaulo uint16_t addr = 0; 1254251538Srpaulo uint32_t reg; 1255282623Skevlo uint8_t off, msk; 1256251538Srpaulo int i; 1257251538Srpaulo 1258264912Skevlo urtwn_efuse_switch_power(sc); 1259264912Skevlo 1260251538Srpaulo memset(&sc->rom, 0xff, sizeof(sc->rom)); 1261251538Srpaulo while (addr < 512) { 1262251538Srpaulo reg = urtwn_efuse_read_1(sc, addr); 1263251538Srpaulo if (reg == 0xff) 1264251538Srpaulo break; 1265251538Srpaulo addr++; 1266251538Srpaulo off = reg >> 4; 1267251538Srpaulo msk = reg & 0xf; 1268251538Srpaulo for (i = 0; i < 4; i++) { 1269251538Srpaulo if (msk & (1 << i)) 1270251538Srpaulo continue; 1271251538Srpaulo rom[off * 8 + i * 2 + 0] = 1272251538Srpaulo urtwn_efuse_read_1(sc, addr); 1273251538Srpaulo addr++; 1274251538Srpaulo rom[off * 8 + i * 2 + 1] = 1275251538Srpaulo urtwn_efuse_read_1(sc, addr); 1276251538Srpaulo addr++; 1277251538Srpaulo } 1278251538Srpaulo } 1279251538Srpaulo#ifdef URTWN_DEBUG 1280251538Srpaulo if (urtwn_debug >= 2) { 1281251538Srpaulo /* Dump ROM content. */ 1282251538Srpaulo printf("\n"); 1283251538Srpaulo for (i = 0; i < sizeof(sc->rom); i++) 1284251538Srpaulo printf("%02x:", rom[i]); 1285251538Srpaulo printf("\n"); 1286251538Srpaulo } 1287251538Srpaulo#endif 1288282623Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1289282623Skevlo} 1290281592Skevlo 1291264912Skevlostatic void 1292264912Skevlourtwn_efuse_switch_power(struct urtwn_softc *sc) 1293264912Skevlo{ 1294264912Skevlo uint32_t reg; 1295251538Srpaulo 1296282623Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1297281918Skevlo 1298264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1299264912Skevlo if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1300264912Skevlo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1301264912Skevlo reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1302264912Skevlo } 1303264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1304264912Skevlo if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1305264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1306264912Skevlo reg | R92C_SYS_FUNC_EN_ELDR); 1307264912Skevlo } 1308264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1309264912Skevlo if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1310264912Skevlo (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1311264912Skevlo urtwn_write_2(sc, R92C_SYS_CLKR, 1312264912Skevlo reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1313264912Skevlo } 1314264912Skevlo} 1315264912Skevlo 1316251538Srpaulostatic int 1317251538Srpaulourtwn_read_chipid(struct urtwn_softc *sc) 1318251538Srpaulo{ 1319251538Srpaulo uint32_t reg; 1320251538Srpaulo 1321264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1322264912Skevlo return (0); 1323264912Skevlo 1324251538Srpaulo reg = urtwn_read_4(sc, R92C_SYS_CFG); 1325251538Srpaulo if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1326251538Srpaulo return (EIO); 1327251538Srpaulo 1328251538Srpaulo if (reg & R92C_SYS_CFG_TYPE_92C) { 1329251538Srpaulo sc->chip |= URTWN_CHIP_92C; 1330251538Srpaulo /* Check if it is a castrated 8192C. */ 1331251538Srpaulo if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1332251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID) == 1333251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1334251538Srpaulo sc->chip |= URTWN_CHIP_92C_1T2R; 1335251538Srpaulo } 1336251538Srpaulo if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1337251538Srpaulo sc->chip |= URTWN_CHIP_UMC; 1338251538Srpaulo if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1339251538Srpaulo sc->chip |= URTWN_CHIP_UMC_A_CUT; 1340251538Srpaulo } 1341251538Srpaulo return (0); 1342251538Srpaulo} 1343251538Srpaulo 1344251538Srpaulostatic void 1345251538Srpaulourtwn_read_rom(struct urtwn_softc *sc) 1346251538Srpaulo{ 1347251538Srpaulo struct r92c_rom *rom = &sc->rom; 1348251538Srpaulo 1349251538Srpaulo /* Read full ROM image. */ 1350251538Srpaulo urtwn_efuse_read(sc); 1351251538Srpaulo 1352251538Srpaulo /* XXX Weird but this is what the vendor driver does. */ 1353251538Srpaulo sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1354251538Srpaulo DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1355251538Srpaulo 1356251538Srpaulo sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1357251538Srpaulo 1358251538Srpaulo sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1359251538Srpaulo DPRINTF("regulatory type=%d\n", sc->regulatory); 1360287197Sglebius IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1361251538Srpaulo 1362264912Skevlo sc->sc_rf_write = urtwn_r92c_rf_write; 1363264912Skevlo sc->sc_power_on = urtwn_r92c_power_on; 1364264912Skevlo sc->sc_dma_init = urtwn_r92c_dma_init; 1365251538Srpaulo} 1366251538Srpaulo 1367264912Skevlostatic void 1368264912Skevlourtwn_r88e_read_rom(struct urtwn_softc *sc) 1369264912Skevlo{ 1370264912Skevlo uint8_t *rom = sc->r88e_rom; 1371264912Skevlo uint16_t addr = 0; 1372264912Skevlo uint32_t reg; 1373264912Skevlo uint8_t off, msk, tmp; 1374264912Skevlo int i; 1375264912Skevlo 1376264982Sandreast off = 0; 1377264912Skevlo urtwn_efuse_switch_power(sc); 1378264912Skevlo 1379264912Skevlo /* Read full ROM image. */ 1380264912Skevlo memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1381281918Skevlo while (addr < 512) { 1382264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1383264912Skevlo if (reg == 0xff) 1384264912Skevlo break; 1385264912Skevlo addr++; 1386264912Skevlo if ((reg & 0x1f) == 0x0f) { 1387264912Skevlo tmp = (reg & 0xe0) >> 5; 1388264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1389264912Skevlo if ((reg & 0x0f) != 0x0f) 1390264912Skevlo off = ((reg & 0xf0) >> 1) | tmp; 1391264912Skevlo addr++; 1392264912Skevlo } else 1393264912Skevlo off = reg >> 4; 1394264912Skevlo msk = reg & 0xf; 1395264912Skevlo for (i = 0; i < 4; i++) { 1396264912Skevlo if (msk & (1 << i)) 1397264912Skevlo continue; 1398264912Skevlo rom[off * 8 + i * 2 + 0] = 1399264912Skevlo urtwn_efuse_read_1(sc, addr); 1400264912Skevlo addr++; 1401264912Skevlo rom[off * 8 + i * 2 + 1] = 1402264912Skevlo urtwn_efuse_read_1(sc, addr); 1403264912Skevlo addr++; 1404264912Skevlo } 1405264912Skevlo } 1406264912Skevlo 1407281918Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1408281918Skevlo 1409264912Skevlo addr = 0x10; 1410264912Skevlo for (i = 0; i < 6; i++) 1411264912Skevlo sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1412264912Skevlo for (i = 0; i < 5; i++) 1413264912Skevlo sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1414264912Skevlo sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1415264912Skevlo if (sc->bw20_tx_pwr_diff & 0x08) 1416264912Skevlo sc->bw20_tx_pwr_diff |= 0xf0; 1417264912Skevlo sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1418264912Skevlo if (sc->ofdm_tx_pwr_diff & 0x08) 1419264912Skevlo sc->ofdm_tx_pwr_diff |= 0xf0; 1420264912Skevlo sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1421287197Sglebius IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &sc->r88e_rom[0xd7]); 1422264912Skevlo 1423264912Skevlo sc->sc_rf_write = urtwn_r88e_rf_write; 1424264912Skevlo sc->sc_power_on = urtwn_r88e_power_on; 1425264912Skevlo sc->sc_dma_init = urtwn_r88e_dma_init; 1426264912Skevlo} 1427264912Skevlo 1428251538Srpaulo/* 1429251538Srpaulo * Initialize rate adaptation in firmware. 1430251538Srpaulo */ 1431251538Srpaulostatic int 1432251538Srpaulourtwn_ra_init(struct urtwn_softc *sc) 1433251538Srpaulo{ 1434287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1435251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1436251538Srpaulo struct ieee80211_node *ni; 1437251538Srpaulo struct ieee80211_rateset *rs; 1438251538Srpaulo struct r92c_fw_cmd_macid_cfg cmd; 1439251538Srpaulo uint32_t rates, basicrates; 1440251538Srpaulo uint8_t mode; 1441251538Srpaulo int maxrate, maxbasicrate, error, i, j; 1442251538Srpaulo 1443251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1444251538Srpaulo rs = &ni->ni_rates; 1445251538Srpaulo 1446251538Srpaulo /* Get normal and basic rates mask. */ 1447251538Srpaulo rates = basicrates = 0; 1448251538Srpaulo maxrate = maxbasicrate = 0; 1449251538Srpaulo for (i = 0; i < rs->rs_nrates; i++) { 1450251538Srpaulo /* Convert 802.11 rate to HW rate index. */ 1451289758Savos for (j = 0; j < nitems(ridx2rate); j++) 1452289758Savos if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1453289758Savos ridx2rate[j]) 1454251538Srpaulo break; 1455289758Savos if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1456251538Srpaulo continue; 1457251538Srpaulo rates |= 1 << j; 1458251538Srpaulo if (j > maxrate) 1459251538Srpaulo maxrate = j; 1460251538Srpaulo if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1461251538Srpaulo basicrates |= 1 << j; 1462251538Srpaulo if (j > maxbasicrate) 1463251538Srpaulo maxbasicrate = j; 1464251538Srpaulo } 1465251538Srpaulo } 1466251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1467251538Srpaulo mode = R92C_RAID_11B; 1468251538Srpaulo else 1469251538Srpaulo mode = R92C_RAID_11BG; 1470251538Srpaulo DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1471251538Srpaulo mode, rates, basicrates); 1472251538Srpaulo 1473251538Srpaulo /* Set rates mask for group addressed frames. */ 1474251538Srpaulo cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1475251538Srpaulo cmd.mask = htole32(mode << 28 | basicrates); 1476251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1477251538Srpaulo if (error != 0) { 1478252401Srpaulo ieee80211_free_node(ni); 1479251538Srpaulo device_printf(sc->sc_dev, 1480251538Srpaulo "could not add broadcast station\n"); 1481251538Srpaulo return (error); 1482251538Srpaulo } 1483251538Srpaulo /* Set initial MRR rate. */ 1484251538Srpaulo DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1485251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1486251538Srpaulo maxbasicrate); 1487251538Srpaulo 1488251538Srpaulo /* Set rates mask for unicast frames. */ 1489251538Srpaulo cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1490251538Srpaulo cmd.mask = htole32(mode << 28 | rates); 1491251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1492251538Srpaulo if (error != 0) { 1493252401Srpaulo ieee80211_free_node(ni); 1494251538Srpaulo device_printf(sc->sc_dev, "could not add BSS station\n"); 1495251538Srpaulo return (error); 1496251538Srpaulo } 1497251538Srpaulo /* Set initial MRR rate. */ 1498251538Srpaulo DPRINTF("maxrate=%d\n", maxrate); 1499251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1500251538Srpaulo maxrate); 1501251538Srpaulo 1502251538Srpaulo /* Indicate highest supported rate. */ 1503252403Srpaulo ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1504252401Srpaulo ieee80211_free_node(ni); 1505252401Srpaulo 1506251538Srpaulo return (0); 1507251538Srpaulo} 1508251538Srpaulo 1509290439Savosstatic void 1510290631Savosurtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1511251538Srpaulo{ 1512290631Savos struct r92c_tx_desc *txd = &uvp->bcn_desc; 1513290631Savos 1514290631Savos txd->txdw0 = htole32( 1515290631Savos SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 1516290631Savos R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1517290631Savos txd->txdw1 = htole32( 1518290631Savos SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 1519290631Savos SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1520290631Savos 1521290631Savos if (sc->chip & URTWN_CHIP_88E) 1522290631Savos txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 1523290631Savos else 1524290631Savos txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 1525290631Savos 1526290631Savos txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 1527290631Savos txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 1528290631Savos txd->txdseq = htole16(R92C_TXDSEQ_HWSEQ_EN); 1529251538Srpaulo} 1530251538Srpaulo 1531290631Savosstatic int 1532290631Savosurtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 1533290631Savos{ 1534290631Savos struct ieee80211vap *vap = ni->ni_vap; 1535290631Savos struct urtwn_vap *uvp = URTWN_VAP(vap); 1536290631Savos struct mbuf *m; 1537290631Savos int error; 1538290631Savos 1539290631Savos URTWN_ASSERT_LOCKED(sc); 1540290631Savos 1541290631Savos if (ni->ni_chan == IEEE80211_CHAN_ANYC) 1542290631Savos return (EINVAL); 1543290631Savos 1544290631Savos m = ieee80211_beacon_alloc(ni); 1545290631Savos if (m == NULL) { 1546290631Savos device_printf(sc->sc_dev, 1547290631Savos "%s: could not allocate beacon frame\n", __func__); 1548290631Savos return (ENOMEM); 1549290631Savos } 1550290631Savos 1551290631Savos if (uvp->bcn_mbuf != NULL) 1552290631Savos m_freem(uvp->bcn_mbuf); 1553290631Savos 1554290631Savos uvp->bcn_mbuf = m; 1555290631Savos 1556290631Savos if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1557290631Savos return (error); 1558290631Savos 1559290631Savos /* XXX bcnq stuck workaround */ 1560290631Savos if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1561290631Savos return (error); 1562290631Savos 1563290631Savos return (0); 1564290631Savos} 1565290631Savos 1566251538Srpaulostatic void 1567290631Savosurtwn_update_beacon(struct ieee80211vap *vap, int item) 1568290631Savos{ 1569290631Savos struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1570290631Savos struct urtwn_vap *uvp = URTWN_VAP(vap); 1571290631Savos struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 1572290631Savos struct ieee80211_node *ni = vap->iv_bss; 1573290631Savos int mcast = 0; 1574290631Savos 1575290631Savos URTWN_LOCK(sc); 1576290631Savos if (uvp->bcn_mbuf == NULL) { 1577290631Savos uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 1578290631Savos if (uvp->bcn_mbuf == NULL) { 1579290631Savos device_printf(sc->sc_dev, 1580290631Savos "%s: could not allocate beacon frame\n", __func__); 1581290631Savos URTWN_UNLOCK(sc); 1582290631Savos return; 1583290631Savos } 1584290631Savos } 1585290631Savos URTWN_UNLOCK(sc); 1586290631Savos 1587290631Savos if (item == IEEE80211_BEACON_TIM) 1588290631Savos mcast = 1; /* XXX */ 1589290631Savos 1590290631Savos setbit(bo->bo_flags, item); 1591290631Savos ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 1592290631Savos 1593290631Savos URTWN_LOCK(sc); 1594290631Savos urtwn_tx_beacon(sc, uvp); 1595290631Savos URTWN_UNLOCK(sc); 1596290631Savos} 1597290631Savos 1598290631Savos/* 1599290631Savos * Push a beacon frame into the chip. Beacon will 1600290631Savos * be repeated by the chip every R92C_BCN_INTERVAL. 1601290631Savos */ 1602290631Savosstatic int 1603290631Savosurtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1604290631Savos{ 1605290631Savos struct r92c_tx_desc *desc = &uvp->bcn_desc; 1606290631Savos struct urtwn_data *bf; 1607290631Savos 1608290631Savos URTWN_ASSERT_LOCKED(sc); 1609290631Savos 1610290631Savos bf = urtwn_getbuf(sc); 1611290631Savos if (bf == NULL) 1612290631Savos return (ENOMEM); 1613290631Savos 1614290631Savos memcpy(bf->buf, desc, sizeof(*desc)); 1615290631Savos urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 1616290631Savos 1617290631Savos sc->sc_txtimer = 5; 1618290631Savos callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1619290631Savos 1620290631Savos return (0); 1621290631Savos} 1622290631Savos 1623290631Savosstatic void 1624290651Savosurtwn_tsf_task_adhoc(void *arg, int pending) 1625290651Savos{ 1626290651Savos struct ieee80211vap *vap = arg; 1627290651Savos struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1628290651Savos struct ieee80211_node *ni; 1629290651Savos uint32_t reg; 1630290651Savos 1631290651Savos URTWN_LOCK(sc); 1632290651Savos ni = ieee80211_ref_node(vap->iv_bss); 1633290651Savos reg = urtwn_read_1(sc, R92C_BCN_CTRL); 1634290651Savos 1635290651Savos /* Accept beacons with the same BSSID. */ 1636290651Savos urtwn_set_rx_bssid_all(sc, 0); 1637290651Savos 1638290651Savos /* Enable synchronization. */ 1639290651Savos reg &= ~R92C_BCN_CTRL_DIS_TSF_UDT0; 1640290651Savos urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1641290651Savos 1642290651Savos /* Synchronize. */ 1643290651Savos usb_pause_mtx(&sc->sc_mtx, hz * ni->ni_intval * 5 / 1000); 1644290651Savos 1645290651Savos /* Disable synchronization. */ 1646290651Savos reg |= R92C_BCN_CTRL_DIS_TSF_UDT0; 1647290651Savos urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1648290651Savos 1649290651Savos /* Remove beacon filter. */ 1650290651Savos urtwn_set_rx_bssid_all(sc, 1); 1651290651Savos 1652290651Savos /* Enable beaconing. */ 1653290651Savos urtwn_write_1(sc, R92C_MBID_NUM, 1654290651Savos urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 1655290651Savos reg |= R92C_BCN_CTRL_EN_BCN; 1656290651Savos 1657290651Savos urtwn_write_1(sc, R92C_BCN_CTRL, reg); 1658290651Savos ieee80211_free_node(ni); 1659290651Savos URTWN_UNLOCK(sc); 1660290651Savos} 1661290651Savos 1662290651Savosstatic void 1663290631Savosurtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 1664290631Savos{ 1665290651Savos struct ieee80211com *ic = &sc->sc_ic; 1666290651Savos struct urtwn_vap *uvp = URTWN_VAP(vap); 1667290651Savos 1668290631Savos /* Reset TSF. */ 1669290631Savos urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 1670290631Savos 1671290631Savos switch (vap->iv_opmode) { 1672290631Savos case IEEE80211_M_STA: 1673290631Savos /* Enable TSF synchronization. */ 1674290631Savos urtwn_write_1(sc, R92C_BCN_CTRL, 1675290631Savos urtwn_read_1(sc, R92C_BCN_CTRL) & 1676290631Savos ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1677290631Savos break; 1678290651Savos case IEEE80211_M_IBSS: 1679290651Savos ieee80211_runtask(ic, &uvp->tsf_task_adhoc); 1680290651Savos break; 1681290631Savos case IEEE80211_M_HOSTAP: 1682290631Savos /* Enable beaconing. */ 1683290631Savos urtwn_write_1(sc, R92C_MBID_NUM, 1684290631Savos urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 1685290631Savos urtwn_write_1(sc, R92C_BCN_CTRL, 1686290631Savos urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1687290631Savos break; 1688290631Savos default: 1689290631Savos device_printf(sc->sc_dev, "undefined opmode %d\n", 1690290631Savos vap->iv_opmode); 1691290631Savos return; 1692290631Savos } 1693290631Savos} 1694290631Savos 1695290631Savosstatic void 1696251538Srpaulourtwn_set_led(struct urtwn_softc *sc, int led, int on) 1697251538Srpaulo{ 1698251538Srpaulo uint8_t reg; 1699281069Srpaulo 1700251538Srpaulo if (led == URTWN_LED_LINK) { 1701264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 1702264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1703264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1704264912Skevlo if (!on) { 1705264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1706264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, 1707264912Skevlo reg | R92C_LEDCFG0_DIS); 1708264912Skevlo urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1709264912Skevlo urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1710264912Skevlo 0xfe); 1711264912Skevlo } 1712264912Skevlo } else { 1713264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1714264912Skevlo if (!on) 1715264912Skevlo reg |= R92C_LEDCFG0_DIS; 1716264912Skevlo urtwn_write_1(sc, R92C_LEDCFG0, reg); 1717264912Skevlo } 1718264912Skevlo sc->ledlink = on; /* Save LED state. */ 1719251538Srpaulo } 1720251538Srpaulo} 1721251538Srpaulo 1722289811Savosstatic void 1723289811Savosurtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 1724289811Savos{ 1725289811Savos uint8_t reg; 1726289811Savos 1727289811Savos reg = urtwn_read_1(sc, R92C_MSR); 1728289811Savos reg = (reg & ~R92C_MSR_MASK) | mode; 1729289811Savos urtwn_write_1(sc, R92C_MSR, reg); 1730289811Savos} 1731289811Savos 1732290651Savosstatic void 1733290651Savosurtwn_ibss_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, int subtype, 1734290651Savos const struct ieee80211_rx_stats *rxs, 1735290651Savos int rssi, int nf) 1736290651Savos{ 1737290651Savos struct ieee80211vap *vap = ni->ni_vap; 1738290651Savos struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1739290651Savos struct urtwn_vap *uvp = URTWN_VAP(vap); 1740290651Savos uint64_t ni_tstamp, curr_tstamp; 1741290651Savos 1742290651Savos uvp->recv_mgmt(ni, m, subtype, rxs, rssi, nf); 1743290651Savos 1744290651Savos if (vap->iv_state == IEEE80211_S_RUN && 1745290651Savos (subtype == IEEE80211_FC0_SUBTYPE_BEACON || 1746290651Savos subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)) { 1747290651Savos ni_tstamp = le64toh(ni->ni_tstamp.tsf); 1748290651Savos#ifdef D3831 1749290651Savos URTWN_LOCK(sc); 1750290651Savos urtwn_get_tsf(sc, &curr_tstamp); 1751290651Savos URTWN_UNLOCK(sc); 1752290651Savos curr_tstamp = le64toh(curr_tstamp); 1753290651Savos 1754290651Savos if (ni_tstamp >= curr_tstamp) 1755290651Savos (void) ieee80211_ibss_merge(ni); 1756290651Savos#else 1757290651Savos (void) sc; 1758290651Savos (void) curr_tstamp; 1759290651Savos#endif 1760290651Savos } 1761290651Savos} 1762290651Savos 1763251538Srpaulostatic int 1764251538Srpaulourtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1765251538Srpaulo{ 1766251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 1767251538Srpaulo struct ieee80211com *ic = vap->iv_ic; 1768286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 1769251538Srpaulo struct ieee80211_node *ni; 1770251538Srpaulo enum ieee80211_state ostate; 1771290631Savos uint32_t reg; 1772290631Savos uint8_t mode; 1773290631Savos int error = 0; 1774251538Srpaulo 1775251538Srpaulo ostate = vap->iv_state; 1776251538Srpaulo DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1777251538Srpaulo ieee80211_state_name[nstate]); 1778251538Srpaulo 1779251538Srpaulo IEEE80211_UNLOCK(ic); 1780251538Srpaulo URTWN_LOCK(sc); 1781251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 1782251538Srpaulo 1783251538Srpaulo if (ostate == IEEE80211_S_RUN) { 1784251538Srpaulo /* Turn link LED off. */ 1785251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1786251538Srpaulo 1787251538Srpaulo /* Set media status to 'No Link'. */ 1788289811Savos urtwn_set_mode(sc, R92C_MSR_NOLINK); 1789251538Srpaulo 1790251538Srpaulo /* Stop Rx of data frames. */ 1791251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1792251538Srpaulo 1793251538Srpaulo /* Disable TSF synchronization. */ 1794251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1795290631Savos (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 1796251538Srpaulo R92C_BCN_CTRL_DIS_TSF_UDT0); 1797251538Srpaulo 1798290631Savos /* Disable beaconing. */ 1799290631Savos urtwn_write_1(sc, R92C_MBID_NUM, 1800290631Savos urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 1801290631Savos 1802290631Savos /* Reset TSF. */ 1803290631Savos urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 1804290631Savos 1805251538Srpaulo /* Reset EDCA parameters. */ 1806251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1807251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1808251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1809251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1810251538Srpaulo } 1811251538Srpaulo 1812251538Srpaulo switch (nstate) { 1813251538Srpaulo case IEEE80211_S_INIT: 1814251538Srpaulo /* Turn link LED off. */ 1815251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1816251538Srpaulo break; 1817251538Srpaulo case IEEE80211_S_SCAN: 1818251538Srpaulo /* Pause AC Tx queues. */ 1819251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 1820251538Srpaulo urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1821251538Srpaulo break; 1822251538Srpaulo case IEEE80211_S_AUTH: 1823251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 1824251538Srpaulo break; 1825251538Srpaulo case IEEE80211_S_RUN: 1826251538Srpaulo if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1827251538Srpaulo /* Turn link LED on. */ 1828251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1829251538Srpaulo break; 1830251538Srpaulo } 1831251538Srpaulo 1832251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1833290631Savos 1834290631Savos if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 1835290631Savos ni->ni_chan == IEEE80211_CHAN_ANYC) { 1836290631Savos device_printf(sc->sc_dev, 1837290631Savos "%s: could not move to RUN state\n", __func__); 1838290631Savos error = EINVAL; 1839290631Savos goto end_run; 1840290631Savos } 1841290631Savos 1842290631Savos switch (vap->iv_opmode) { 1843290631Savos case IEEE80211_M_STA: 1844290631Savos mode = R92C_MSR_INFRA; 1845290631Savos break; 1846290651Savos case IEEE80211_M_IBSS: 1847290651Savos mode = R92C_MSR_ADHOC; 1848290651Savos break; 1849290631Savos case IEEE80211_M_HOSTAP: 1850290631Savos mode = R92C_MSR_AP; 1851290631Savos break; 1852290631Savos default: 1853290631Savos device_printf(sc->sc_dev, "undefined opmode %d\n", 1854290631Savos vap->iv_opmode); 1855290631Savos error = EINVAL; 1856290631Savos goto end_run; 1857290631Savos } 1858290631Savos 1859251538Srpaulo /* Set media status to 'Associated'. */ 1860290631Savos urtwn_set_mode(sc, mode); 1861251538Srpaulo 1862251538Srpaulo /* Set BSSID. */ 1863251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1864251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1865251538Srpaulo 1866251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1867251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1868251538Srpaulo else /* 802.11b/g */ 1869251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1870251538Srpaulo 1871251538Srpaulo /* Enable Rx of data frames. */ 1872251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1873251538Srpaulo 1874251538Srpaulo /* Flush all AC queues. */ 1875251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0); 1876251538Srpaulo 1877251538Srpaulo /* Set beacon interval. */ 1878251538Srpaulo urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1879251538Srpaulo 1880251538Srpaulo /* Allow Rx from our BSSID only. */ 1881290564Savos if (ic->ic_promisc == 0) { 1882290631Savos reg = urtwn_read_4(sc, R92C_RCR); 1883290631Savos 1884290631Savos if (vap->iv_opmode != IEEE80211_M_HOSTAP) 1885290631Savos reg |= R92C_RCR_CBSSID_DATA; 1886290651Savos if (vap->iv_opmode != IEEE80211_M_IBSS) 1887290651Savos reg |= R92C_RCR_CBSSID_BCN; 1888290631Savos 1889290631Savos urtwn_write_4(sc, R92C_RCR, reg); 1890290564Savos } 1891251538Srpaulo 1892290651Savos if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1893290651Savos vap->iv_opmode == IEEE80211_M_IBSS) { 1894290631Savos error = urtwn_setup_beacon(sc, ni); 1895290631Savos if (error != 0) { 1896290631Savos device_printf(sc->sc_dev, 1897290631Savos "unable to push beacon into the chip, " 1898290631Savos "error %d\n", error); 1899290631Savos goto end_run; 1900290631Savos } 1901290631Savos } 1902290631Savos 1903251538Srpaulo /* Enable TSF synchronization. */ 1904290631Savos urtwn_tsf_sync_enable(sc, vap); 1905251538Srpaulo 1906251538Srpaulo urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1907251538Srpaulo urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1908251538Srpaulo urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1909251538Srpaulo urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1910251538Srpaulo urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1911251538Srpaulo urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1912251538Srpaulo 1913251538Srpaulo /* Intialize rate adaptation. */ 1914264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1915264912Skevlo ni->ni_txrate = 1916264912Skevlo ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1917281069Srpaulo else 1918264912Skevlo urtwn_ra_init(sc); 1919251538Srpaulo /* Turn link LED on. */ 1920251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1921251538Srpaulo 1922251538Srpaulo sc->avg_pwdb = -1; /* Reset average RSSI. */ 1923251538Srpaulo /* Reset temperature calibration state machine. */ 1924251538Srpaulo sc->thcal_state = 0; 1925251538Srpaulo sc->thcal_lctemp = 0; 1926290631Savos 1927290631Savosend_run: 1928251538Srpaulo ieee80211_free_node(ni); 1929251538Srpaulo break; 1930251538Srpaulo default: 1931251538Srpaulo break; 1932251538Srpaulo } 1933290631Savos 1934251538Srpaulo URTWN_UNLOCK(sc); 1935251538Srpaulo IEEE80211_LOCK(ic); 1936290631Savos return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 1937251538Srpaulo} 1938251538Srpaulo 1939251538Srpaulostatic void 1940251538Srpaulourtwn_watchdog(void *arg) 1941251538Srpaulo{ 1942251538Srpaulo struct urtwn_softc *sc = arg; 1943251538Srpaulo 1944251538Srpaulo if (sc->sc_txtimer > 0) { 1945251538Srpaulo if (--sc->sc_txtimer == 0) { 1946251538Srpaulo device_printf(sc->sc_dev, "device timeout\n"); 1947287197Sglebius counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1948251538Srpaulo return; 1949251538Srpaulo } 1950251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1951251538Srpaulo } 1952251538Srpaulo} 1953251538Srpaulo 1954251538Srpaulostatic void 1955251538Srpaulourtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1956251538Srpaulo{ 1957251538Srpaulo int pwdb; 1958251538Srpaulo 1959251538Srpaulo /* Convert antenna signal to percentage. */ 1960251538Srpaulo if (rssi <= -100 || rssi >= 20) 1961251538Srpaulo pwdb = 0; 1962251538Srpaulo else if (rssi >= 0) 1963251538Srpaulo pwdb = 100; 1964251538Srpaulo else 1965251538Srpaulo pwdb = 100 + rssi; 1966264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1967289758Savos if (rate <= URTWN_RIDX_CCK11) { 1968264912Skevlo /* CCK gain is smaller than OFDM/MCS gain. */ 1969264912Skevlo pwdb += 6; 1970264912Skevlo if (pwdb > 100) 1971264912Skevlo pwdb = 100; 1972264912Skevlo if (pwdb <= 14) 1973264912Skevlo pwdb -= 4; 1974264912Skevlo else if (pwdb <= 26) 1975264912Skevlo pwdb -= 8; 1976264912Skevlo else if (pwdb <= 34) 1977264912Skevlo pwdb -= 6; 1978264912Skevlo else if (pwdb <= 42) 1979264912Skevlo pwdb -= 2; 1980264912Skevlo } 1981251538Srpaulo } 1982251538Srpaulo if (sc->avg_pwdb == -1) /* Init. */ 1983251538Srpaulo sc->avg_pwdb = pwdb; 1984251538Srpaulo else if (sc->avg_pwdb < pwdb) 1985251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1986251538Srpaulo else 1987251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1988251538Srpaulo DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1989251538Srpaulo} 1990251538Srpaulo 1991251538Srpaulostatic int8_t 1992251538Srpaulourtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1993251538Srpaulo{ 1994251538Srpaulo static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1995251538Srpaulo struct r92c_rx_phystat *phy; 1996251538Srpaulo struct r92c_rx_cck *cck; 1997251538Srpaulo uint8_t rpt; 1998251538Srpaulo int8_t rssi; 1999251538Srpaulo 2000289758Savos if (rate <= URTWN_RIDX_CCK11) { 2001251538Srpaulo cck = (struct r92c_rx_cck *)physt; 2002251538Srpaulo if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 2003251538Srpaulo rpt = (cck->agc_rpt >> 5) & 0x3; 2004251538Srpaulo rssi = (cck->agc_rpt & 0x1f) << 1; 2005251538Srpaulo } else { 2006251538Srpaulo rpt = (cck->agc_rpt >> 6) & 0x3; 2007251538Srpaulo rssi = cck->agc_rpt & 0x3e; 2008251538Srpaulo } 2009251538Srpaulo rssi = cckoff[rpt] - rssi; 2010251538Srpaulo } else { /* OFDM/HT. */ 2011251538Srpaulo phy = (struct r92c_rx_phystat *)physt; 2012251538Srpaulo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2013251538Srpaulo } 2014251538Srpaulo return (rssi); 2015251538Srpaulo} 2016251538Srpaulo 2017264912Skevlostatic int8_t 2018264912Skevlourtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2019264912Skevlo{ 2020264912Skevlo struct r92c_rx_phystat *phy; 2021264912Skevlo struct r88e_rx_cck *cck; 2022264912Skevlo uint8_t cck_agc_rpt, lna_idx, vga_idx; 2023264912Skevlo int8_t rssi; 2024264912Skevlo 2025264972Skevlo rssi = 0; 2026289758Savos if (rate <= URTWN_RIDX_CCK11) { 2027264912Skevlo cck = (struct r88e_rx_cck *)physt; 2028264912Skevlo cck_agc_rpt = cck->agc_rpt; 2029264912Skevlo lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2030281069Srpaulo vga_idx = cck_agc_rpt & 0x1f; 2031264912Skevlo switch (lna_idx) { 2032264912Skevlo case 7: 2033264912Skevlo if (vga_idx <= 27) 2034264912Skevlo rssi = -100 + 2* (27 - vga_idx); 2035264912Skevlo else 2036264912Skevlo rssi = -100; 2037264912Skevlo break; 2038264912Skevlo case 6: 2039264912Skevlo rssi = -48 + 2 * (2 - vga_idx); 2040264912Skevlo break; 2041264912Skevlo case 5: 2042264912Skevlo rssi = -42 + 2 * (7 - vga_idx); 2043264912Skevlo break; 2044264912Skevlo case 4: 2045264912Skevlo rssi = -36 + 2 * (7 - vga_idx); 2046264912Skevlo break; 2047264912Skevlo case 3: 2048264912Skevlo rssi = -24 + 2 * (7 - vga_idx); 2049264912Skevlo break; 2050264912Skevlo case 2: 2051264912Skevlo rssi = -12 + 2 * (5 - vga_idx); 2052264912Skevlo break; 2053264912Skevlo case 1: 2054264912Skevlo rssi = 8 - (2 * vga_idx); 2055264912Skevlo break; 2056264912Skevlo case 0: 2057264912Skevlo rssi = 14 - (2 * vga_idx); 2058264912Skevlo break; 2059264912Skevlo } 2060264912Skevlo rssi += 6; 2061264912Skevlo } else { /* OFDM/HT. */ 2062264912Skevlo phy = (struct r92c_rx_phystat *)physt; 2063264912Skevlo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2064264912Skevlo } 2065264912Skevlo return (rssi); 2066264912Skevlo} 2067264912Skevlo 2068251538Srpaulostatic int 2069290630Savosurtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 2070290630Savos struct mbuf *m, struct urtwn_data *data) 2071251538Srpaulo{ 2072251538Srpaulo struct ieee80211_frame *wh; 2073290630Savos struct ieee80211_key *k = NULL; 2074287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 2075251538Srpaulo struct ieee80211vap *vap = ni->ni_vap; 2076251538Srpaulo struct r92c_tx_desc *txd; 2077290630Savos uint8_t macid, raid, ridx, subtype, type, qsel; 2078290630Savos int ismcast; 2079251538Srpaulo 2080251538Srpaulo URTWN_ASSERT_LOCKED(sc); 2081251538Srpaulo 2082251538Srpaulo /* 2083251538Srpaulo * Software crypto. 2084251538Srpaulo */ 2085290630Savos wh = mtod(m, struct ieee80211_frame *); 2086264912Skevlo type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2087290630Savos subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2088290630Savos ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2089264912Skevlo 2090260444Skevlo if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2091290630Savos k = ieee80211_crypto_encap(ni, m); 2092251538Srpaulo if (k == NULL) { 2093251538Srpaulo device_printf(sc->sc_dev, 2094251538Srpaulo "ieee80211_crypto_encap returns NULL.\n"); 2095251538Srpaulo return (ENOBUFS); 2096251538Srpaulo } 2097251538Srpaulo 2098251538Srpaulo /* in case packet header moved, reset pointer */ 2099290630Savos wh = mtod(m, struct ieee80211_frame *); 2100251538Srpaulo } 2101281069Srpaulo 2102251538Srpaulo /* Fill Tx descriptor. */ 2103251538Srpaulo txd = (struct r92c_tx_desc *)data->buf; 2104251538Srpaulo memset(txd, 0, sizeof(*txd)); 2105251538Srpaulo 2106251538Srpaulo txd->txdw0 |= htole32( 2107251538Srpaulo SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2108251538Srpaulo R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2109290630Savos if (ismcast) 2110251538Srpaulo txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2111290630Savos 2112290630Savos raid = R92C_RAID_11B; /* by default */ 2113290630Savos ridx = URTWN_RIDX_CCK1; 2114290630Savos if (!ismcast) { 2115290630Savos macid = URTWN_MACID_BSS; 2116290630Savos 2117290630Savos if (type == IEEE80211_FC0_TYPE_DATA) { 2118290630Savos qsel = R92C_TXDW1_QSEL_BE; 2119290630Savos 2120290630Savos if (!(m->m_flags & M_EAPOL)) { 2121290630Savos if (ic->ic_curmode != IEEE80211_MODE_11B) { 2122290630Savos raid = R92C_RAID_11BG; 2123290630Savos ridx = URTWN_RIDX_OFDM54; 2124290630Savos } else 2125290630Savos ridx = URTWN_RIDX_CCK11; 2126251538Srpaulo } 2127290630Savos 2128290630Savos if (sc->chip & URTWN_CHIP_88E) 2129290630Savos txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2130290630Savos else 2131290630Savos txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2132290630Savos 2133290630Savos if (ic->ic_flags & IEEE80211_F_USEPROT) { 2134290630Savos switch (ic->ic_protmode) { 2135290630Savos case IEEE80211_PROT_CTSONLY: 2136290630Savos txd->txdw4 |= htole32( 2137290630Savos R92C_TXDW4_CTS2SELF | 2138290630Savos R92C_TXDW4_HWRTSEN); 2139290630Savos break; 2140290630Savos case IEEE80211_PROT_RTSCTS: 2141290630Savos txd->txdw4 |= htole32( 2142290630Savos R92C_TXDW4_RTSEN | 2143290630Savos R92C_TXDW4_HWRTSEN); 2144290630Savos break; 2145290630Savos default: 2146290630Savos break; 2147290630Savos } 2148290630Savos } 2149290630Savos txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2150290630Savos URTWN_RIDX_OFDM24)); 2151290630Savos txd->txdw5 |= htole32(0x0001ff00); 2152290630Savos } else /* IEEE80211_FC0_TYPE_MGT */ 2153290630Savos qsel = R92C_TXDW1_QSEL_MGNT; 2154251538Srpaulo } else { 2155290630Savos macid = URTWN_MACID_BC; 2156290630Savos qsel = R92C_TXDW1_QSEL_MGNT; 2157290630Savos } 2158251538Srpaulo 2159290630Savos txd->txdw1 |= htole32( 2160290630Savos SM(R92C_TXDW1_QSEL, qsel) | 2161290630Savos SM(R92C_TXDW1_RAID, raid)); 2162290630Savos 2163290630Savos if (sc->chip & URTWN_CHIP_88E) 2164290630Savos txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 2165290630Savos else 2166290630Savos txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 2167290630Savos 2168290630Savos txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2169290630Savos /* not sure here */ 2170290630Savos if (ridx <= URTWN_RIDX_CCK11) 2171251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2172251538Srpaulo 2173288534Sadrian if (!IEEE80211_QOS_HAS_SEQ(wh)) { 2174251538Srpaulo /* Use HW sequence numbering for non-QoS frames. */ 2175290630Savos txd->txdseq = htole16(R92C_TXDSEQ_HWSEQ_EN); 2176290630Savos } else { 2177290630Savos /* Set sequence number. */ 2178290630Savos txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2179290630Savos } 2180251538Srpaulo 2181251538Srpaulo if (ieee80211_radiotap_active_vap(vap)) { 2182251538Srpaulo struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2183251538Srpaulo 2184251538Srpaulo tap->wt_flags = 0; 2185251538Srpaulo tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2186251538Srpaulo tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2187290630Savos if (k != NULL) 2188290630Savos tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2189290630Savos ieee80211_radiotap_tx(vap, m); 2190251538Srpaulo } 2191251538Srpaulo 2192290630Savos data->ni = ni; 2193251538Srpaulo 2194290630Savos urtwn_tx_start(sc, m, type, data); 2195290630Savos 2196290630Savos return (0); 2197290630Savos} 2198290630Savos 2199290630Savosstatic void 2200290630Savosurtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 2201290630Savos struct urtwn_data *data) 2202290630Savos{ 2203290630Savos struct usb_xfer *xfer; 2204290630Savos struct r92c_tx_desc *txd; 2205290630Savos uint16_t ac, sum; 2206290630Savos int i, xferlen; 2207290630Savos struct usb_xfer *urtwn_pipes[WME_NUM_AC] = { 2208290630Savos sc->sc_xfer[URTWN_BULK_TX_BE], 2209290630Savos sc->sc_xfer[URTWN_BULK_TX_BK], 2210290630Savos sc->sc_xfer[URTWN_BULK_TX_VI], 2211290630Savos sc->sc_xfer[URTWN_BULK_TX_VO] 2212290630Savos }; 2213290630Savos 2214290630Savos URTWN_ASSERT_LOCKED(sc); 2215290630Savos 2216290630Savos ac = M_WME_GETAC(m); 2217290630Savos 2218290630Savos switch (type) { 2219290630Savos case IEEE80211_FC0_TYPE_CTL: 2220290630Savos case IEEE80211_FC0_TYPE_MGT: 2221290630Savos xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 2222290630Savos break; 2223290630Savos default: 2224290630Savos xfer = urtwn_pipes[ac]; 2225290630Savos break; 2226290630Savos } 2227290630Savos 2228290630Savos txd = (struct r92c_tx_desc *)data->buf; 2229290630Savos txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 2230290630Savos 2231290630Savos /* Compute Tx descriptor checksum. */ 2232290630Savos sum = 0; 2233290630Savos for (i = 0; i < sizeof(*txd) / 2; i++) 2234290630Savos sum ^= ((uint16_t *)txd)[i]; 2235290630Savos txd->txdsum = sum; /* NB: already little endian. */ 2236290630Savos 2237290630Savos xferlen = sizeof(*txd) + m->m_pkthdr.len; 2238290630Savos m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 2239290630Savos 2240251538Srpaulo data->buflen = xferlen; 2241290630Savos data->m = m; 2242251538Srpaulo 2243251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 2244251538Srpaulo usbd_transfer_start(xfer); 2245251538Srpaulo} 2246251538Srpaulo 2247287197Sglebiusstatic int 2248287197Sglebiusurtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 2249251538Srpaulo{ 2250287197Sglebius struct urtwn_softc *sc = ic->ic_softc; 2251287197Sglebius int error; 2252261863Srpaulo 2253261863Srpaulo URTWN_LOCK(sc); 2254287197Sglebius if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2255287197Sglebius URTWN_UNLOCK(sc); 2256287197Sglebius return (ENXIO); 2257287197Sglebius } 2258287197Sglebius error = mbufq_enqueue(&sc->sc_snd, m); 2259287197Sglebius if (error) { 2260287197Sglebius URTWN_UNLOCK(sc); 2261287197Sglebius return (error); 2262287197Sglebius } 2263287197Sglebius urtwn_start(sc); 2264261863Srpaulo URTWN_UNLOCK(sc); 2265287197Sglebius 2266287197Sglebius return (0); 2267261863Srpaulo} 2268261863Srpaulo 2269261863Srpaulostatic void 2270287197Sglebiusurtwn_start(struct urtwn_softc *sc) 2271261863Srpaulo{ 2272251538Srpaulo struct ieee80211_node *ni; 2273251538Srpaulo struct mbuf *m; 2274251538Srpaulo struct urtwn_data *bf; 2275251538Srpaulo 2276261863Srpaulo URTWN_ASSERT_LOCKED(sc); 2277287197Sglebius while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2278251538Srpaulo bf = urtwn_getbuf(sc); 2279251538Srpaulo if (bf == NULL) { 2280287197Sglebius mbufq_prepend(&sc->sc_snd, m); 2281251538Srpaulo break; 2282251538Srpaulo } 2283251538Srpaulo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2284251538Srpaulo m->m_pkthdr.rcvif = NULL; 2285290630Savos if (urtwn_tx_data(sc, ni, m, bf) != 0) { 2286287197Sglebius if_inc_counter(ni->ni_vap->iv_ifp, 2287287197Sglebius IFCOUNTER_OERRORS, 1); 2288251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2289288353Sadrian m_freem(m); 2290251538Srpaulo ieee80211_free_node(ni); 2291251538Srpaulo break; 2292251538Srpaulo } 2293251538Srpaulo sc->sc_txtimer = 5; 2294251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2295251538Srpaulo } 2296251538Srpaulo} 2297251538Srpaulo 2298287197Sglebiusstatic void 2299287197Sglebiusurtwn_parent(struct ieee80211com *ic) 2300251538Srpaulo{ 2301286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 2302287197Sglebius int startall = 0; 2303251538Srpaulo 2304263153Skevlo URTWN_LOCK(sc); 2305287197Sglebius if (sc->sc_flags & URTWN_DETACHED) { 2306287197Sglebius URTWN_UNLOCK(sc); 2307287197Sglebius return; 2308287197Sglebius } 2309287197Sglebius if (ic->ic_nrunning > 0) { 2310287197Sglebius if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2311287197Sglebius urtwn_init(sc); 2312287197Sglebius startall = 1; 2313287197Sglebius } 2314287197Sglebius } else if (sc->sc_flags & URTWN_RUNNING) 2315287197Sglebius urtwn_stop(sc); 2316263153Skevlo URTWN_UNLOCK(sc); 2317263153Skevlo 2318287197Sglebius if (startall) 2319287197Sglebius ieee80211_start_all(ic); 2320251538Srpaulo} 2321251538Srpaulo 2322264912Skevlostatic __inline int 2323251538Srpaulourtwn_power_on(struct urtwn_softc *sc) 2324251538Srpaulo{ 2325264912Skevlo 2326264912Skevlo return sc->sc_power_on(sc); 2327264912Skevlo} 2328264912Skevlo 2329264912Skevlostatic int 2330264912Skevlourtwn_r92c_power_on(struct urtwn_softc *sc) 2331264912Skevlo{ 2332251538Srpaulo uint32_t reg; 2333251538Srpaulo int ntries; 2334251538Srpaulo 2335251538Srpaulo /* Wait for autoload done bit. */ 2336251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2337251538Srpaulo if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2338251538Srpaulo break; 2339266472Shselasky urtwn_ms_delay(sc); 2340251538Srpaulo } 2341251538Srpaulo if (ntries == 1000) { 2342251538Srpaulo device_printf(sc->sc_dev, 2343251538Srpaulo "timeout waiting for chip autoload\n"); 2344251538Srpaulo return (ETIMEDOUT); 2345251538Srpaulo } 2346251538Srpaulo 2347251538Srpaulo /* Unlock ISO/CLK/Power control register. */ 2348251538Srpaulo urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2349251538Srpaulo /* Move SPS into PWM mode. */ 2350251538Srpaulo urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2351266472Shselasky urtwn_ms_delay(sc); 2352251538Srpaulo 2353251538Srpaulo reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2354251538Srpaulo if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2355251538Srpaulo urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2356251538Srpaulo reg | R92C_LDOV12D_CTRL_LDV12_EN); 2357266472Shselasky urtwn_ms_delay(sc); 2358251538Srpaulo urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2359251538Srpaulo urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2360251538Srpaulo ~R92C_SYS_ISO_CTRL_MD2PP); 2361251538Srpaulo } 2362251538Srpaulo 2363251538Srpaulo /* Auto enable WLAN. */ 2364251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2365251538Srpaulo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2366251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2367262822Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2368262822Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2369251538Srpaulo break; 2370266472Shselasky urtwn_ms_delay(sc); 2371251538Srpaulo } 2372251538Srpaulo if (ntries == 1000) { 2373251538Srpaulo device_printf(sc->sc_dev, 2374251538Srpaulo "timeout waiting for MAC auto ON\n"); 2375251538Srpaulo return (ETIMEDOUT); 2376251538Srpaulo } 2377251538Srpaulo 2378251538Srpaulo /* Enable radio, GPIO and LED functions. */ 2379251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2380251538Srpaulo R92C_APS_FSMCO_AFSM_HSUS | 2381251538Srpaulo R92C_APS_FSMCO_PDN_EN | 2382251538Srpaulo R92C_APS_FSMCO_PFM_ALDN); 2383251538Srpaulo /* Release RF digital isolation. */ 2384251538Srpaulo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2385251538Srpaulo urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2386251538Srpaulo 2387251538Srpaulo /* Initialize MAC. */ 2388251538Srpaulo urtwn_write_1(sc, R92C_APSD_CTRL, 2389251538Srpaulo urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2390251538Srpaulo for (ntries = 0; ntries < 200; ntries++) { 2391251538Srpaulo if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2392251538Srpaulo R92C_APSD_CTRL_OFF_STATUS)) 2393251538Srpaulo break; 2394266472Shselasky urtwn_ms_delay(sc); 2395251538Srpaulo } 2396251538Srpaulo if (ntries == 200) { 2397251538Srpaulo device_printf(sc->sc_dev, 2398251538Srpaulo "timeout waiting for MAC initialization\n"); 2399251538Srpaulo return (ETIMEDOUT); 2400251538Srpaulo } 2401251538Srpaulo 2402251538Srpaulo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2403251538Srpaulo reg = urtwn_read_2(sc, R92C_CR); 2404251538Srpaulo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2405251538Srpaulo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2406251538Srpaulo R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2407251538Srpaulo R92C_CR_ENSEC; 2408251538Srpaulo urtwn_write_2(sc, R92C_CR, reg); 2409251538Srpaulo 2410251538Srpaulo urtwn_write_1(sc, 0xfe10, 0x19); 2411251538Srpaulo return (0); 2412251538Srpaulo} 2413251538Srpaulo 2414251538Srpaulostatic int 2415264912Skevlourtwn_r88e_power_on(struct urtwn_softc *sc) 2416264912Skevlo{ 2417264912Skevlo uint32_t reg; 2418264912Skevlo int ntries; 2419264912Skevlo 2420264912Skevlo /* Wait for power ready bit. */ 2421264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2422281918Skevlo if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2423264912Skevlo break; 2424266472Shselasky urtwn_ms_delay(sc); 2425264912Skevlo } 2426264912Skevlo if (ntries == 5000) { 2427264912Skevlo device_printf(sc->sc_dev, 2428264912Skevlo "timeout waiting for chip power up\n"); 2429264912Skevlo return (ETIMEDOUT); 2430264912Skevlo } 2431264912Skevlo 2432264912Skevlo /* Reset BB. */ 2433264912Skevlo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2434264912Skevlo urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2435264912Skevlo R92C_SYS_FUNC_EN_BB_GLB_RST)); 2436264912Skevlo 2437281918Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2438281918Skevlo urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2439264912Skevlo 2440264912Skevlo /* Disable HWPDN. */ 2441281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2442281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2443264912Skevlo 2444264912Skevlo /* Disable WL suspend. */ 2445281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2446281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & 2447281918Skevlo ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2448264912Skevlo 2449281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2450281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2451264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2452281918Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2453281918Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2454264912Skevlo break; 2455266472Shselasky urtwn_ms_delay(sc); 2456264912Skevlo } 2457264912Skevlo if (ntries == 5000) 2458264912Skevlo return (ETIMEDOUT); 2459264912Skevlo 2460264912Skevlo /* Enable LDO normal mode. */ 2461281918Skevlo urtwn_write_1(sc, R92C_LPLDO_CTRL, 2462281918Skevlo urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2463264912Skevlo 2464264912Skevlo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2465264912Skevlo urtwn_write_2(sc, R92C_CR, 0); 2466264912Skevlo reg = urtwn_read_2(sc, R92C_CR); 2467264912Skevlo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2468264912Skevlo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2469264912Skevlo R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2470264912Skevlo urtwn_write_2(sc, R92C_CR, reg); 2471264912Skevlo 2472264912Skevlo return (0); 2473264912Skevlo} 2474264912Skevlo 2475264912Skevlostatic int 2476251538Srpaulourtwn_llt_init(struct urtwn_softc *sc) 2477251538Srpaulo{ 2478264912Skevlo int i, error, page_count, pktbuf_count; 2479251538Srpaulo 2480264912Skevlo page_count = (sc->chip & URTWN_CHIP_88E) ? 2481264912Skevlo R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2482264912Skevlo pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2483264912Skevlo R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2484264912Skevlo 2485264912Skevlo /* Reserve pages [0; page_count]. */ 2486264912Skevlo for (i = 0; i < page_count; i++) { 2487251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2488251538Srpaulo return (error); 2489251538Srpaulo } 2490251538Srpaulo /* NB: 0xff indicates end-of-list. */ 2491251538Srpaulo if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2492251538Srpaulo return (error); 2493251538Srpaulo /* 2494264912Skevlo * Use pages [page_count + 1; pktbuf_count - 1] 2495251538Srpaulo * as ring buffer. 2496251538Srpaulo */ 2497264912Skevlo for (++i; i < pktbuf_count - 1; i++) { 2498251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2499251538Srpaulo return (error); 2500251538Srpaulo } 2501251538Srpaulo /* Make the last page point to the beginning of the ring buffer. */ 2502264912Skevlo error = urtwn_llt_write(sc, i, page_count + 1); 2503251538Srpaulo return (error); 2504251538Srpaulo} 2505251538Srpaulo 2506251538Srpaulostatic void 2507251538Srpaulourtwn_fw_reset(struct urtwn_softc *sc) 2508251538Srpaulo{ 2509251538Srpaulo uint16_t reg; 2510251538Srpaulo int ntries; 2511251538Srpaulo 2512251538Srpaulo /* Tell 8051 to reset itself. */ 2513251538Srpaulo urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2514251538Srpaulo 2515251538Srpaulo /* Wait until 8051 resets by itself. */ 2516251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 2517251538Srpaulo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2518251538Srpaulo if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2519251538Srpaulo return; 2520266472Shselasky urtwn_ms_delay(sc); 2521251538Srpaulo } 2522251538Srpaulo /* Force 8051 reset. */ 2523251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2524251538Srpaulo} 2525251538Srpaulo 2526264912Skevlostatic void 2527264912Skevlourtwn_r88e_fw_reset(struct urtwn_softc *sc) 2528264912Skevlo{ 2529264912Skevlo uint16_t reg; 2530264912Skevlo 2531264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2532264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2533264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2534264912Skevlo} 2535264912Skevlo 2536251538Srpaulostatic int 2537251538Srpaulourtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2538251538Srpaulo{ 2539251538Srpaulo uint32_t reg; 2540251538Srpaulo int off, mlen, error = 0; 2541251538Srpaulo 2542251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2543251538Srpaulo reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2544251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2545251538Srpaulo 2546251538Srpaulo off = R92C_FW_START_ADDR; 2547251538Srpaulo while (len > 0) { 2548251538Srpaulo if (len > 196) 2549251538Srpaulo mlen = 196; 2550251538Srpaulo else if (len > 4) 2551251538Srpaulo mlen = 4; 2552251538Srpaulo else 2553251538Srpaulo mlen = 1; 2554251538Srpaulo /* XXX fix this deconst */ 2555281069Srpaulo error = urtwn_write_region_1(sc, off, 2556251538Srpaulo __DECONST(uint8_t *, buf), mlen); 2557251538Srpaulo if (error != 0) 2558251538Srpaulo break; 2559251538Srpaulo off += mlen; 2560251538Srpaulo buf += mlen; 2561251538Srpaulo len -= mlen; 2562251538Srpaulo } 2563251538Srpaulo return (error); 2564251538Srpaulo} 2565251538Srpaulo 2566251538Srpaulostatic int 2567251538Srpaulourtwn_load_firmware(struct urtwn_softc *sc) 2568251538Srpaulo{ 2569251538Srpaulo const struct firmware *fw; 2570251538Srpaulo const struct r92c_fw_hdr *hdr; 2571251538Srpaulo const char *imagename; 2572251538Srpaulo const u_char *ptr; 2573251538Srpaulo size_t len; 2574251538Srpaulo uint32_t reg; 2575251538Srpaulo int mlen, ntries, page, error; 2576251538Srpaulo 2577264864Skevlo URTWN_UNLOCK(sc); 2578251538Srpaulo /* Read firmware image from the filesystem. */ 2579264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2580264912Skevlo imagename = "urtwn-rtl8188eufw"; 2581264912Skevlo else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2582264912Skevlo URTWN_CHIP_UMC_A_CUT) 2583251538Srpaulo imagename = "urtwn-rtl8192cfwU"; 2584251538Srpaulo else 2585251538Srpaulo imagename = "urtwn-rtl8192cfwT"; 2586251538Srpaulo 2587251538Srpaulo fw = firmware_get(imagename); 2588264864Skevlo URTWN_LOCK(sc); 2589251538Srpaulo if (fw == NULL) { 2590251538Srpaulo device_printf(sc->sc_dev, 2591251538Srpaulo "failed loadfirmware of file %s\n", imagename); 2592251538Srpaulo return (ENOENT); 2593251538Srpaulo } 2594251538Srpaulo 2595251538Srpaulo len = fw->datasize; 2596251538Srpaulo 2597251538Srpaulo if (len < sizeof(*hdr)) { 2598251538Srpaulo device_printf(sc->sc_dev, "firmware too short\n"); 2599251538Srpaulo error = EINVAL; 2600251538Srpaulo goto fail; 2601251538Srpaulo } 2602251538Srpaulo ptr = fw->data; 2603251538Srpaulo hdr = (const struct r92c_fw_hdr *)ptr; 2604251538Srpaulo /* Check if there is a valid FW header and skip it. */ 2605251538Srpaulo if ((le16toh(hdr->signature) >> 4) == 0x88c || 2606264912Skevlo (le16toh(hdr->signature) >> 4) == 0x88e || 2607251538Srpaulo (le16toh(hdr->signature) >> 4) == 0x92c) { 2608251538Srpaulo DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2609251538Srpaulo le16toh(hdr->version), le16toh(hdr->subversion), 2610251538Srpaulo hdr->month, hdr->date, hdr->hour, hdr->minute); 2611251538Srpaulo ptr += sizeof(*hdr); 2612251538Srpaulo len -= sizeof(*hdr); 2613251538Srpaulo } 2614251538Srpaulo 2615264912Skevlo if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2616264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2617264912Skevlo urtwn_r88e_fw_reset(sc); 2618264912Skevlo else 2619264912Skevlo urtwn_fw_reset(sc); 2620251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 0); 2621251538Srpaulo } 2622264912Skevlo 2623268487Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2624268487Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2625268487Skevlo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2626268487Skevlo R92C_SYS_FUNC_EN_CPUEN); 2627268487Skevlo } 2628251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2629251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2630251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 2, 2631251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2632251538Srpaulo 2633263154Skevlo /* Reset the FWDL checksum. */ 2634263154Skevlo urtwn_write_1(sc, R92C_MCUFWDL, 2635263154Skevlo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2636263154Skevlo 2637251538Srpaulo for (page = 0; len > 0; page++) { 2638251538Srpaulo mlen = min(len, R92C_FW_PAGE_SIZE); 2639251538Srpaulo error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2640251538Srpaulo if (error != 0) { 2641251538Srpaulo device_printf(sc->sc_dev, 2642251538Srpaulo "could not load firmware page\n"); 2643251538Srpaulo goto fail; 2644251538Srpaulo } 2645251538Srpaulo ptr += mlen; 2646251538Srpaulo len -= mlen; 2647251538Srpaulo } 2648251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2649251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2650251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2651251538Srpaulo 2652251538Srpaulo /* Wait for checksum report. */ 2653251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2654251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2655251538Srpaulo break; 2656266472Shselasky urtwn_ms_delay(sc); 2657251538Srpaulo } 2658251538Srpaulo if (ntries == 1000) { 2659251538Srpaulo device_printf(sc->sc_dev, 2660251538Srpaulo "timeout waiting for checksum report\n"); 2661251538Srpaulo error = ETIMEDOUT; 2662251538Srpaulo goto fail; 2663251538Srpaulo } 2664251538Srpaulo 2665251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2666251538Srpaulo reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2667251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2668264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2669264912Skevlo urtwn_r88e_fw_reset(sc); 2670251538Srpaulo /* Wait for firmware readiness. */ 2671251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2672251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2673251538Srpaulo break; 2674266472Shselasky urtwn_ms_delay(sc); 2675251538Srpaulo } 2676251538Srpaulo if (ntries == 1000) { 2677251538Srpaulo device_printf(sc->sc_dev, 2678251538Srpaulo "timeout waiting for firmware readiness\n"); 2679251538Srpaulo error = ETIMEDOUT; 2680251538Srpaulo goto fail; 2681251538Srpaulo } 2682251538Srpaulofail: 2683251538Srpaulo firmware_put(fw, FIRMWARE_UNLOAD); 2684251538Srpaulo return (error); 2685251538Srpaulo} 2686251538Srpaulo 2687264912Skevlostatic __inline int 2688251538Srpaulourtwn_dma_init(struct urtwn_softc *sc) 2689251538Srpaulo{ 2690281069Srpaulo 2691264912Skevlo return sc->sc_dma_init(sc); 2692264912Skevlo} 2693264912Skevlo 2694264912Skevlostatic int 2695264912Skevlourtwn_r92c_dma_init(struct urtwn_softc *sc) 2696264912Skevlo{ 2697251538Srpaulo int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2698251538Srpaulo uint32_t reg; 2699251538Srpaulo int error; 2700251538Srpaulo 2701251538Srpaulo /* Initialize LLT table. */ 2702251538Srpaulo error = urtwn_llt_init(sc); 2703251538Srpaulo if (error != 0) 2704251538Srpaulo return (error); 2705251538Srpaulo 2706251538Srpaulo /* Get Tx queues to USB endpoints mapping. */ 2707251538Srpaulo hashq = hasnq = haslq = 0; 2708251538Srpaulo reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2709251538Srpaulo DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2710251538Srpaulo if (MS(reg, R92C_USB_EP_HQ) != 0) 2711251538Srpaulo hashq = 1; 2712251538Srpaulo if (MS(reg, R92C_USB_EP_NQ) != 0) 2713251538Srpaulo hasnq = 1; 2714251538Srpaulo if (MS(reg, R92C_USB_EP_LQ) != 0) 2715251538Srpaulo haslq = 1; 2716251538Srpaulo nqueues = hashq + hasnq + haslq; 2717251538Srpaulo if (nqueues == 0) 2718251538Srpaulo return (EIO); 2719251538Srpaulo /* Get the number of pages for each queue. */ 2720251538Srpaulo nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2721251538Srpaulo /* The remaining pages are assigned to the high priority queue. */ 2722251538Srpaulo nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2723251538Srpaulo 2724251538Srpaulo /* Set number of pages for normal priority queue. */ 2725251538Srpaulo urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2726251538Srpaulo urtwn_write_4(sc, R92C_RQPN, 2727251538Srpaulo /* Set number of pages for public queue. */ 2728251538Srpaulo SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2729251538Srpaulo /* Set number of pages for high priority queue. */ 2730251538Srpaulo SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2731251538Srpaulo /* Set number of pages for low priority queue. */ 2732251538Srpaulo SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2733251538Srpaulo /* Load values. */ 2734251538Srpaulo R92C_RQPN_LD); 2735251538Srpaulo 2736251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2737251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2738251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2739251538Srpaulo urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2740251538Srpaulo urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2741251538Srpaulo 2742251538Srpaulo /* Set queue to USB pipe mapping. */ 2743251538Srpaulo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2744251538Srpaulo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2745251538Srpaulo if (nqueues == 1) { 2746251538Srpaulo if (hashq) 2747251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2748251538Srpaulo else if (hasnq) 2749251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2750251538Srpaulo else 2751251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2752251538Srpaulo } else if (nqueues == 2) { 2753251538Srpaulo /* All 2-endpoints configs have a high priority queue. */ 2754251538Srpaulo if (!hashq) 2755251538Srpaulo return (EIO); 2756251538Srpaulo if (hasnq) 2757251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2758251538Srpaulo else 2759251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2760251538Srpaulo } else 2761251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2762251538Srpaulo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2763251538Srpaulo 2764251538Srpaulo /* Set Tx/Rx transfer page boundary. */ 2765251538Srpaulo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2766251538Srpaulo 2767251538Srpaulo /* Set Tx/Rx transfer page size. */ 2768251538Srpaulo urtwn_write_1(sc, R92C_PBP, 2769251538Srpaulo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2770251538Srpaulo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2771251538Srpaulo return (0); 2772251538Srpaulo} 2773251538Srpaulo 2774264912Skevlostatic int 2775264912Skevlourtwn_r88e_dma_init(struct urtwn_softc *sc) 2776264912Skevlo{ 2777264912Skevlo struct usb_interface *iface; 2778264912Skevlo uint32_t reg; 2779264912Skevlo int nqueues; 2780264912Skevlo int error; 2781264912Skevlo 2782264912Skevlo /* Initialize LLT table. */ 2783264912Skevlo error = urtwn_llt_init(sc); 2784264912Skevlo if (error != 0) 2785264912Skevlo return (error); 2786264912Skevlo 2787264912Skevlo /* Get Tx queues to USB endpoints mapping. */ 2788264912Skevlo iface = usbd_get_iface(sc->sc_udev, 0); 2789264912Skevlo nqueues = iface->idesc->bNumEndpoints - 1; 2790264912Skevlo if (nqueues == 0) 2791264912Skevlo return (EIO); 2792264912Skevlo 2793264912Skevlo /* Set number of pages for normal priority queue. */ 2794264912Skevlo urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2795264912Skevlo urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2796264912Skevlo 2797264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2798264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2799264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2800264912Skevlo urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2801264912Skevlo urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2802264912Skevlo 2803264912Skevlo /* Set queue to USB pipe mapping. */ 2804264912Skevlo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2805264912Skevlo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2806264912Skevlo if (nqueues == 1) 2807264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2808264912Skevlo else if (nqueues == 2) 2809264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2810264912Skevlo else 2811264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2812264912Skevlo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2813264912Skevlo 2814264912Skevlo /* Set Tx/Rx transfer page boundary. */ 2815264912Skevlo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2816264912Skevlo 2817264912Skevlo /* Set Tx/Rx transfer page size. */ 2818264912Skevlo urtwn_write_1(sc, R92C_PBP, 2819264912Skevlo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2820264912Skevlo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2821264912Skevlo 2822264912Skevlo return (0); 2823264912Skevlo} 2824264912Skevlo 2825251538Srpaulostatic void 2826251538Srpaulourtwn_mac_init(struct urtwn_softc *sc) 2827251538Srpaulo{ 2828251538Srpaulo int i; 2829251538Srpaulo 2830251538Srpaulo /* Write MAC initialization values. */ 2831264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2832264912Skevlo for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2833264912Skevlo urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2834264912Skevlo rtl8188eu_mac[i].val); 2835264912Skevlo } 2836264912Skevlo urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2837264912Skevlo } else { 2838264912Skevlo for (i = 0; i < nitems(rtl8192cu_mac); i++) 2839264912Skevlo urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2840264912Skevlo rtl8192cu_mac[i].val); 2841264912Skevlo } 2842251538Srpaulo} 2843251538Srpaulo 2844251538Srpaulostatic void 2845251538Srpaulourtwn_bb_init(struct urtwn_softc *sc) 2846251538Srpaulo{ 2847251538Srpaulo const struct urtwn_bb_prog *prog; 2848251538Srpaulo uint32_t reg; 2849264912Skevlo uint8_t crystalcap; 2850251538Srpaulo int i; 2851251538Srpaulo 2852251538Srpaulo /* Enable BB and RF. */ 2853251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2854251538Srpaulo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2855251538Srpaulo R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2856251538Srpaulo R92C_SYS_FUNC_EN_DIO_RF); 2857251538Srpaulo 2858264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 2859264912Skevlo urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2860251538Srpaulo 2861251538Srpaulo urtwn_write_1(sc, R92C_RF_CTRL, 2862251538Srpaulo R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2863251538Srpaulo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2864251538Srpaulo R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2865251538Srpaulo R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2866251538Srpaulo 2867264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2868264912Skevlo urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2869264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 2870264912Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2871264912Skevlo } 2872251538Srpaulo 2873251538Srpaulo /* Select BB programming based on board type. */ 2874264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2875264912Skevlo prog = &rtl8188eu_bb_prog; 2876264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2877251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2878251538Srpaulo prog = &rtl8188ce_bb_prog; 2879251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2880251538Srpaulo prog = &rtl8188ru_bb_prog; 2881251538Srpaulo else 2882251538Srpaulo prog = &rtl8188cu_bb_prog; 2883251538Srpaulo } else { 2884251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2885251538Srpaulo prog = &rtl8192ce_bb_prog; 2886251538Srpaulo else 2887251538Srpaulo prog = &rtl8192cu_bb_prog; 2888251538Srpaulo } 2889251538Srpaulo /* Write BB initialization values. */ 2890251538Srpaulo for (i = 0; i < prog->count; i++) { 2891251538Srpaulo urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2892266472Shselasky urtwn_ms_delay(sc); 2893251538Srpaulo } 2894251538Srpaulo 2895251538Srpaulo if (sc->chip & URTWN_CHIP_92C_1T2R) { 2896251538Srpaulo /* 8192C 1T only configuration. */ 2897251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2898251538Srpaulo reg = (reg & ~0x00000003) | 0x2; 2899251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2900251538Srpaulo 2901251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2902251538Srpaulo reg = (reg & ~0x00300033) | 0x00200022; 2903251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2904251538Srpaulo 2905251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2906251538Srpaulo reg = (reg & ~0xff000000) | 0x45 << 24; 2907251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2908251538Srpaulo 2909251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2910251538Srpaulo reg = (reg & ~0x000000ff) | 0x23; 2911251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2912251538Srpaulo 2913251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2914251538Srpaulo reg = (reg & ~0x00000030) | 1 << 4; 2915251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2916251538Srpaulo 2917251538Srpaulo reg = urtwn_bb_read(sc, 0xe74); 2918251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2919251538Srpaulo urtwn_bb_write(sc, 0xe74, reg); 2920251538Srpaulo reg = urtwn_bb_read(sc, 0xe78); 2921251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2922251538Srpaulo urtwn_bb_write(sc, 0xe78, reg); 2923251538Srpaulo reg = urtwn_bb_read(sc, 0xe7c); 2924251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2925251538Srpaulo urtwn_bb_write(sc, 0xe7c, reg); 2926251538Srpaulo reg = urtwn_bb_read(sc, 0xe80); 2927251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2928251538Srpaulo urtwn_bb_write(sc, 0xe80, reg); 2929251538Srpaulo reg = urtwn_bb_read(sc, 0xe88); 2930251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2931251538Srpaulo urtwn_bb_write(sc, 0xe88, reg); 2932251538Srpaulo } 2933251538Srpaulo 2934251538Srpaulo /* Write AGC values. */ 2935251538Srpaulo for (i = 0; i < prog->agccount; i++) { 2936251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2937251538Srpaulo prog->agcvals[i]); 2938266472Shselasky urtwn_ms_delay(sc); 2939251538Srpaulo } 2940251538Srpaulo 2941264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2942264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2943266472Shselasky urtwn_ms_delay(sc); 2944264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2945266472Shselasky urtwn_ms_delay(sc); 2946264912Skevlo 2947264912Skevlo crystalcap = sc->r88e_rom[0xb9]; 2948264912Skevlo if (crystalcap == 0xff) 2949264912Skevlo crystalcap = 0x20; 2950264912Skevlo crystalcap &= 0x3f; 2951264912Skevlo reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2952264912Skevlo urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2953264912Skevlo RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2954264912Skevlo crystalcap | crystalcap << 6)); 2955264912Skevlo } else { 2956264912Skevlo if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2957264912Skevlo R92C_HSSI_PARAM2_CCK_HIPWR) 2958264912Skevlo sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2959264912Skevlo } 2960251538Srpaulo} 2961251538Srpaulo 2962289066Skevlostatic void 2963251538Srpaulourtwn_rf_init(struct urtwn_softc *sc) 2964251538Srpaulo{ 2965251538Srpaulo const struct urtwn_rf_prog *prog; 2966251538Srpaulo uint32_t reg, type; 2967251538Srpaulo int i, j, idx, off; 2968251538Srpaulo 2969251538Srpaulo /* Select RF programming based on board type. */ 2970264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2971264912Skevlo prog = rtl8188eu_rf_prog; 2972264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2973251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2974251538Srpaulo prog = rtl8188ce_rf_prog; 2975251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2976251538Srpaulo prog = rtl8188ru_rf_prog; 2977251538Srpaulo else 2978251538Srpaulo prog = rtl8188cu_rf_prog; 2979251538Srpaulo } else 2980251538Srpaulo prog = rtl8192ce_rf_prog; 2981251538Srpaulo 2982251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2983251538Srpaulo /* Save RF_ENV control type. */ 2984251538Srpaulo idx = i / 2; 2985251538Srpaulo off = (i % 2) * 16; 2986251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2987251538Srpaulo type = (reg >> off) & 0x10; 2988251538Srpaulo 2989251538Srpaulo /* Set RF_ENV enable. */ 2990251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2991251538Srpaulo reg |= 0x100000; 2992251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2993266472Shselasky urtwn_ms_delay(sc); 2994251538Srpaulo /* Set RF_ENV output high. */ 2995251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2996251538Srpaulo reg |= 0x10; 2997251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2998266472Shselasky urtwn_ms_delay(sc); 2999251538Srpaulo /* Set address and data lengths of RF registers. */ 3000251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3001251538Srpaulo reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 3002251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3003266472Shselasky urtwn_ms_delay(sc); 3004251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 3005251538Srpaulo reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 3006251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 3007266472Shselasky urtwn_ms_delay(sc); 3008251538Srpaulo 3009251538Srpaulo /* Write RF initialization values for this chain. */ 3010251538Srpaulo for (j = 0; j < prog[i].count; j++) { 3011251538Srpaulo if (prog[i].regs[j] >= 0xf9 && 3012251538Srpaulo prog[i].regs[j] <= 0xfe) { 3013251538Srpaulo /* 3014251538Srpaulo * These are fake RF registers offsets that 3015251538Srpaulo * indicate a delay is required. 3016251538Srpaulo */ 3017266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 3018251538Srpaulo continue; 3019251538Srpaulo } 3020251538Srpaulo urtwn_rf_write(sc, i, prog[i].regs[j], 3021251538Srpaulo prog[i].vals[j]); 3022266472Shselasky urtwn_ms_delay(sc); 3023251538Srpaulo } 3024251538Srpaulo 3025251538Srpaulo /* Restore RF_ENV control type. */ 3026251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 3027251538Srpaulo reg &= ~(0x10 << off) | (type << off); 3028251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 3029251538Srpaulo 3030251538Srpaulo /* Cache RF register CHNLBW. */ 3031251538Srpaulo sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 3032251538Srpaulo } 3033251538Srpaulo 3034251538Srpaulo if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3035251538Srpaulo URTWN_CHIP_UMC_A_CUT) { 3036251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 3037251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 3038251538Srpaulo } 3039251538Srpaulo} 3040251538Srpaulo 3041251538Srpaulostatic void 3042251538Srpaulourtwn_cam_init(struct urtwn_softc *sc) 3043251538Srpaulo{ 3044251538Srpaulo /* Invalidate all CAM entries. */ 3045251538Srpaulo urtwn_write_4(sc, R92C_CAMCMD, 3046251538Srpaulo R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 3047251538Srpaulo} 3048251538Srpaulo 3049251538Srpaulostatic void 3050251538Srpaulourtwn_pa_bias_init(struct urtwn_softc *sc) 3051251538Srpaulo{ 3052251538Srpaulo uint8_t reg; 3053251538Srpaulo int i; 3054251538Srpaulo 3055251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3056251538Srpaulo if (sc->pa_setting & (1 << i)) 3057251538Srpaulo continue; 3058251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 3059251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 3060251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 3061251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 3062251538Srpaulo } 3063251538Srpaulo if (!(sc->pa_setting & 0x10)) { 3064251538Srpaulo reg = urtwn_read_1(sc, 0x16); 3065251538Srpaulo reg = (reg & ~0xf0) | 0x90; 3066251538Srpaulo urtwn_write_1(sc, 0x16, reg); 3067251538Srpaulo } 3068251538Srpaulo} 3069251538Srpaulo 3070251538Srpaulostatic void 3071251538Srpaulourtwn_rxfilter_init(struct urtwn_softc *sc) 3072251538Srpaulo{ 3073290564Savos struct ieee80211com *ic = &sc->sc_ic; 3074290564Savos struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3075290564Savos uint32_t rcr; 3076290564Savos uint16_t filter; 3077290564Savos 3078290564Savos URTWN_ASSERT_LOCKED(sc); 3079290564Savos 3080251538Srpaulo /* Accept all multicast frames. */ 3081251538Srpaulo urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 3082251538Srpaulo urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 3083290564Savos 3084290564Savos /* Filter for management frames. */ 3085290564Savos filter = 0x7f3f; 3086290631Savos switch (vap->iv_opmode) { 3087290631Savos case IEEE80211_M_STA: 3088290564Savos filter &= ~( 3089290564Savos R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 3090290564Savos R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 3091290564Savos R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 3092290631Savos break; 3093290631Savos case IEEE80211_M_HOSTAP: 3094290631Savos filter &= ~( 3095290631Savos R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 3096290631Savos R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP) | 3097290631Savos R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_BEACON)); 3098290631Savos break; 3099290631Savos case IEEE80211_M_MONITOR: 3100290651Savos case IEEE80211_M_IBSS: 3101290631Savos break; 3102290631Savos default: 3103290631Savos device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3104290631Savos __func__, vap->iv_opmode); 3105290631Savos break; 3106290564Savos } 3107290564Savos urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 3108290564Savos 3109251538Srpaulo /* Reject all control frames. */ 3110251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3111290564Savos 3112290564Savos /* Reject all data frames. */ 3113290564Savos urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 3114290564Savos 3115290564Savos rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 3116290564Savos R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 3117290564Savos R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 3118290564Savos 3119290564Savos if (vap->iv_opmode == IEEE80211_M_MONITOR) { 3120290564Savos /* Accept all frames. */ 3121290564Savos rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 3122290564Savos R92C_RCR_AAP; 3123290564Savos } 3124290564Savos 3125290564Savos /* Set Rx filter. */ 3126290564Savos urtwn_write_4(sc, R92C_RCR, rcr); 3127290564Savos 3128290564Savos if (ic->ic_promisc != 0) { 3129290564Savos /* Update Rx filter. */ 3130290564Savos urtwn_set_promisc(sc); 3131290564Savos } 3132251538Srpaulo} 3133251538Srpaulo 3134251538Srpaulostatic void 3135251538Srpaulourtwn_edca_init(struct urtwn_softc *sc) 3136251538Srpaulo{ 3137251538Srpaulo urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3138251538Srpaulo urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3139251538Srpaulo urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3140251538Srpaulo urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3141251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3142251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3143251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3144251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3145251538Srpaulo} 3146251538Srpaulo 3147289066Skevlostatic void 3148251538Srpaulourtwn_write_txpower(struct urtwn_softc *sc, int chain, 3149251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 3150251538Srpaulo{ 3151251538Srpaulo uint32_t reg; 3152251538Srpaulo 3153251538Srpaulo /* Write per-CCK rate Tx power. */ 3154251538Srpaulo if (chain == 0) { 3155251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3156251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3157251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3158251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3159251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3160251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3161251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3162251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3163251538Srpaulo } else { 3164251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3165251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3166251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3167251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3168251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3169251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3170251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3171251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3172251538Srpaulo } 3173251538Srpaulo /* Write per-OFDM rate Tx power. */ 3174251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3175251538Srpaulo SM(R92C_TXAGC_RATE06, power[ 4]) | 3176251538Srpaulo SM(R92C_TXAGC_RATE09, power[ 5]) | 3177251538Srpaulo SM(R92C_TXAGC_RATE12, power[ 6]) | 3178251538Srpaulo SM(R92C_TXAGC_RATE18, power[ 7])); 3179251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3180251538Srpaulo SM(R92C_TXAGC_RATE24, power[ 8]) | 3181251538Srpaulo SM(R92C_TXAGC_RATE36, power[ 9]) | 3182251538Srpaulo SM(R92C_TXAGC_RATE48, power[10]) | 3183251538Srpaulo SM(R92C_TXAGC_RATE54, power[11])); 3184251538Srpaulo /* Write per-MCS Tx power. */ 3185251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3186251538Srpaulo SM(R92C_TXAGC_MCS00, power[12]) | 3187251538Srpaulo SM(R92C_TXAGC_MCS01, power[13]) | 3188251538Srpaulo SM(R92C_TXAGC_MCS02, power[14]) | 3189251538Srpaulo SM(R92C_TXAGC_MCS03, power[15])); 3190251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3191251538Srpaulo SM(R92C_TXAGC_MCS04, power[16]) | 3192251538Srpaulo SM(R92C_TXAGC_MCS05, power[17]) | 3193251538Srpaulo SM(R92C_TXAGC_MCS06, power[18]) | 3194251538Srpaulo SM(R92C_TXAGC_MCS07, power[19])); 3195251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3196251538Srpaulo SM(R92C_TXAGC_MCS08, power[20]) | 3197261506Skevlo SM(R92C_TXAGC_MCS09, power[21]) | 3198251538Srpaulo SM(R92C_TXAGC_MCS10, power[22]) | 3199251538Srpaulo SM(R92C_TXAGC_MCS11, power[23])); 3200251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3201251538Srpaulo SM(R92C_TXAGC_MCS12, power[24]) | 3202251538Srpaulo SM(R92C_TXAGC_MCS13, power[25]) | 3203251538Srpaulo SM(R92C_TXAGC_MCS14, power[26]) | 3204251538Srpaulo SM(R92C_TXAGC_MCS15, power[27])); 3205251538Srpaulo} 3206251538Srpaulo 3207289066Skevlostatic void 3208251538Srpaulourtwn_get_txpower(struct urtwn_softc *sc, int chain, 3209251538Srpaulo struct ieee80211_channel *c, struct ieee80211_channel *extc, 3210251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 3211251538Srpaulo{ 3212287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3213251538Srpaulo struct r92c_rom *rom = &sc->rom; 3214251538Srpaulo uint16_t cckpow, ofdmpow, htpow, diff, max; 3215251538Srpaulo const struct urtwn_txpwr *base; 3216251538Srpaulo int ridx, chan, group; 3217251538Srpaulo 3218251538Srpaulo /* Determine channel group. */ 3219251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3220251538Srpaulo if (chan <= 3) 3221251538Srpaulo group = 0; 3222251538Srpaulo else if (chan <= 9) 3223251538Srpaulo group = 1; 3224251538Srpaulo else 3225251538Srpaulo group = 2; 3226251538Srpaulo 3227251538Srpaulo /* Get original Tx power based on board type and RF chain. */ 3228251538Srpaulo if (!(sc->chip & URTWN_CHIP_92C)) { 3229251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3230251538Srpaulo base = &rtl8188ru_txagc[chain]; 3231251538Srpaulo else 3232251538Srpaulo base = &rtl8192cu_txagc[chain]; 3233251538Srpaulo } else 3234251538Srpaulo base = &rtl8192cu_txagc[chain]; 3235251538Srpaulo 3236251538Srpaulo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3237251538Srpaulo if (sc->regulatory == 0) { 3238289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3239251538Srpaulo power[ridx] = base->pwr[0][ridx]; 3240251538Srpaulo } 3241289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3242251538Srpaulo if (sc->regulatory == 3) { 3243251538Srpaulo power[ridx] = base->pwr[0][ridx]; 3244251538Srpaulo /* Apply vendor limits. */ 3245251538Srpaulo if (extc != NULL) 3246251538Srpaulo max = rom->ht40_max_pwr[group]; 3247251538Srpaulo else 3248251538Srpaulo max = rom->ht20_max_pwr[group]; 3249251538Srpaulo max = (max >> (chain * 4)) & 0xf; 3250251538Srpaulo if (power[ridx] > max) 3251251538Srpaulo power[ridx] = max; 3252251538Srpaulo } else if (sc->regulatory == 1) { 3253251538Srpaulo if (extc == NULL) 3254251538Srpaulo power[ridx] = base->pwr[group][ridx]; 3255251538Srpaulo } else if (sc->regulatory != 2) 3256251538Srpaulo power[ridx] = base->pwr[0][ridx]; 3257251538Srpaulo } 3258251538Srpaulo 3259251538Srpaulo /* Compute per-CCK rate Tx power. */ 3260251538Srpaulo cckpow = rom->cck_tx_pwr[chain][group]; 3261289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3262251538Srpaulo power[ridx] += cckpow; 3263251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 3264251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 3265251538Srpaulo } 3266251538Srpaulo 3267251538Srpaulo htpow = rom->ht40_1s_tx_pwr[chain][group]; 3268251538Srpaulo if (sc->ntxchains > 1) { 3269251538Srpaulo /* Apply reduction for 2 spatial streams. */ 3270251538Srpaulo diff = rom->ht40_2s_tx_pwr_diff[group]; 3271251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 3272251538Srpaulo htpow = (htpow > diff) ? htpow - diff : 0; 3273251538Srpaulo } 3274251538Srpaulo 3275251538Srpaulo /* Compute per-OFDM rate Tx power. */ 3276251538Srpaulo diff = rom->ofdm_tx_pwr_diff[group]; 3277251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 3278251538Srpaulo ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3279289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3280251538Srpaulo power[ridx] += ofdmpow; 3281251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 3282251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 3283251538Srpaulo } 3284251538Srpaulo 3285251538Srpaulo /* Compute per-MCS Tx power. */ 3286251538Srpaulo if (extc == NULL) { 3287251538Srpaulo diff = rom->ht20_tx_pwr_diff[group]; 3288251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 3289251538Srpaulo htpow += diff; /* HT40->HT20 correction. */ 3290251538Srpaulo } 3291251538Srpaulo for (ridx = 12; ridx <= 27; ridx++) { 3292251538Srpaulo power[ridx] += htpow; 3293251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 3294251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 3295251538Srpaulo } 3296251538Srpaulo#ifdef URTWN_DEBUG 3297251538Srpaulo if (urtwn_debug >= 4) { 3298251538Srpaulo /* Dump per-rate Tx power values. */ 3299251538Srpaulo printf("Tx power for chain %d:\n", chain); 3300289758Savos for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 3301251538Srpaulo printf("Rate %d = %u\n", ridx, power[ridx]); 3302251538Srpaulo } 3303251538Srpaulo#endif 3304251538Srpaulo} 3305251538Srpaulo 3306289066Skevlostatic void 3307264912Skevlourtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3308264912Skevlo struct ieee80211_channel *c, struct ieee80211_channel *extc, 3309264912Skevlo uint16_t power[URTWN_RIDX_COUNT]) 3310264912Skevlo{ 3311287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3312264912Skevlo uint16_t cckpow, ofdmpow, bw20pow, htpow; 3313264912Skevlo const struct urtwn_r88e_txpwr *base; 3314264912Skevlo int ridx, chan, group; 3315264912Skevlo 3316264912Skevlo /* Determine channel group. */ 3317264912Skevlo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3318264912Skevlo if (chan <= 2) 3319264912Skevlo group = 0; 3320264912Skevlo else if (chan <= 5) 3321264912Skevlo group = 1; 3322264912Skevlo else if (chan <= 8) 3323264912Skevlo group = 2; 3324264912Skevlo else if (chan <= 11) 3325264912Skevlo group = 3; 3326264912Skevlo else if (chan <= 13) 3327264912Skevlo group = 4; 3328264912Skevlo else 3329264912Skevlo group = 5; 3330264912Skevlo 3331264912Skevlo /* Get original Tx power based on board type and RF chain. */ 3332264912Skevlo base = &rtl8188eu_txagc[chain]; 3333264912Skevlo 3334264912Skevlo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3335264912Skevlo if (sc->regulatory == 0) { 3336289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3337264912Skevlo power[ridx] = base->pwr[0][ridx]; 3338264912Skevlo } 3339289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3340264912Skevlo if (sc->regulatory == 3) 3341264912Skevlo power[ridx] = base->pwr[0][ridx]; 3342264912Skevlo else if (sc->regulatory == 1) { 3343264912Skevlo if (extc == NULL) 3344264912Skevlo power[ridx] = base->pwr[group][ridx]; 3345264912Skevlo } else if (sc->regulatory != 2) 3346264912Skevlo power[ridx] = base->pwr[0][ridx]; 3347264912Skevlo } 3348264912Skevlo 3349264912Skevlo /* Compute per-CCK rate Tx power. */ 3350264912Skevlo cckpow = sc->cck_tx_pwr[group]; 3351289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3352264912Skevlo power[ridx] += cckpow; 3353264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3354264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3355264912Skevlo } 3356264912Skevlo 3357264912Skevlo htpow = sc->ht40_tx_pwr[group]; 3358264912Skevlo 3359264912Skevlo /* Compute per-OFDM rate Tx power. */ 3360264912Skevlo ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3361289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3362264912Skevlo power[ridx] += ofdmpow; 3363264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3364264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3365264912Skevlo } 3366264912Skevlo 3367264912Skevlo bw20pow = htpow + sc->bw20_tx_pwr_diff; 3368264912Skevlo for (ridx = 12; ridx <= 27; ridx++) { 3369264912Skevlo power[ridx] += bw20pow; 3370264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3371264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3372264912Skevlo } 3373264912Skevlo} 3374264912Skevlo 3375289066Skevlostatic void 3376251538Srpaulourtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3377251538Srpaulo struct ieee80211_channel *extc) 3378251538Srpaulo{ 3379251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]; 3380251538Srpaulo int i; 3381251538Srpaulo 3382251538Srpaulo for (i = 0; i < sc->ntxchains; i++) { 3383251538Srpaulo /* Compute per-rate Tx power values. */ 3384264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3385264912Skevlo urtwn_r88e_get_txpower(sc, i, c, extc, power); 3386264912Skevlo else 3387264912Skevlo urtwn_get_txpower(sc, i, c, extc, power); 3388251538Srpaulo /* Write per-rate Tx power values to hardware. */ 3389251538Srpaulo urtwn_write_txpower(sc, i, power); 3390251538Srpaulo } 3391251538Srpaulo} 3392251538Srpaulo 3393251538Srpaulostatic void 3394290048Savosurtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 3395290048Savos{ 3396290048Savos uint32_t reg; 3397290048Savos 3398290048Savos reg = urtwn_read_4(sc, R92C_RCR); 3399290048Savos if (enable) 3400290048Savos reg &= ~R92C_RCR_CBSSID_BCN; 3401290048Savos else 3402290048Savos reg |= R92C_RCR_CBSSID_BCN; 3403290048Savos urtwn_write_4(sc, R92C_RCR, reg); 3404290048Savos} 3405290048Savos 3406290048Savosstatic void 3407290048Savosurtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 3408290048Savos{ 3409290048Savos uint32_t reg; 3410290048Savos 3411290048Savos reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3412290048Savos reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3413290048Savos urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3414290048Savos 3415290048Savos if (!(sc->chip & URTWN_CHIP_88E)) { 3416290048Savos reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3417290048Savos reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3418290048Savos urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3419290048Savos } 3420290048Savos} 3421290048Savos 3422290048Savosstatic void 3423251538Srpaulourtwn_scan_start(struct ieee80211com *ic) 3424251538Srpaulo{ 3425290048Savos struct urtwn_softc *sc = ic->ic_softc; 3426290048Savos 3427290048Savos URTWN_LOCK(sc); 3428290048Savos /* Receive beacons / probe responses from any BSSID. */ 3429290651Savos if (ic->ic_opmode != IEEE80211_M_IBSS) 3430290651Savos urtwn_set_rx_bssid_all(sc, 1); 3431290651Savos 3432290048Savos /* Set gain for scanning. */ 3433290048Savos urtwn_set_gain(sc, 0x20); 3434290048Savos URTWN_UNLOCK(sc); 3435251538Srpaulo} 3436251538Srpaulo 3437251538Srpaulostatic void 3438251538Srpaulourtwn_scan_end(struct ieee80211com *ic) 3439251538Srpaulo{ 3440290048Savos struct urtwn_softc *sc = ic->ic_softc; 3441290048Savos 3442290048Savos URTWN_LOCK(sc); 3443290048Savos /* Restore limitations. */ 3444290651Savos if (ic->ic_promisc == 0 && ic->ic_opmode != IEEE80211_M_IBSS) 3445290564Savos urtwn_set_rx_bssid_all(sc, 0); 3446290651Savos 3447290048Savos /* Set gain under link. */ 3448290048Savos urtwn_set_gain(sc, 0x32); 3449290048Savos URTWN_UNLOCK(sc); 3450251538Srpaulo} 3451251538Srpaulo 3452251538Srpaulostatic void 3453251538Srpaulourtwn_set_channel(struct ieee80211com *ic) 3454251538Srpaulo{ 3455286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 3456281070Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3457251538Srpaulo 3458251538Srpaulo URTWN_LOCK(sc); 3459281070Srpaulo if (vap->iv_state == IEEE80211_S_SCAN) { 3460281070Srpaulo /* Make link LED blink during scan. */ 3461281070Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3462281070Srpaulo } 3463251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 3464251538Srpaulo URTWN_UNLOCK(sc); 3465251538Srpaulo} 3466251538Srpaulo 3467251538Srpaulostatic void 3468290564Savosurtwn_set_promisc(struct urtwn_softc *sc) 3469290564Savos{ 3470290564Savos struct ieee80211com *ic = &sc->sc_ic; 3471290564Savos struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3472290564Savos uint32_t rcr, mask1, mask2; 3473290564Savos 3474290564Savos URTWN_ASSERT_LOCKED(sc); 3475290564Savos 3476290564Savos if (vap->iv_opmode == IEEE80211_M_MONITOR) 3477290564Savos return; 3478290564Savos 3479290564Savos mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 3480290564Savos mask2 = R92C_RCR_APM; 3481290564Savos 3482290564Savos if (vap->iv_state == IEEE80211_S_RUN) { 3483290564Savos switch (vap->iv_opmode) { 3484290564Savos case IEEE80211_M_STA: 3485290631Savos mask2 |= R92C_RCR_CBSSID_DATA; 3486290631Savos /* FALLTHROUGH */ 3487290631Savos case IEEE80211_M_HOSTAP: 3488290631Savos mask2 |= R92C_RCR_CBSSID_BCN; 3489290564Savos break; 3490290651Savos case IEEE80211_M_IBSS: 3491290651Savos mask2 |= R92C_RCR_CBSSID_DATA; 3492290651Savos break; 3493290564Savos default: 3494290564Savos device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3495290564Savos __func__, vap->iv_opmode); 3496290564Savos return; 3497290564Savos } 3498290564Savos } 3499290564Savos 3500290564Savos rcr = urtwn_read_4(sc, R92C_RCR); 3501290564Savos if (ic->ic_promisc == 0) 3502290564Savos rcr = (rcr & ~mask1) | mask2; 3503290564Savos else 3504290564Savos rcr = (rcr & ~mask2) | mask1; 3505290564Savos urtwn_write_4(sc, R92C_RCR, rcr); 3506290564Savos} 3507290564Savos 3508290564Savosstatic void 3509290564Savosurtwn_update_promisc(struct ieee80211com *ic) 3510290564Savos{ 3511290564Savos struct urtwn_softc *sc = ic->ic_softc; 3512290564Savos 3513290564Savos URTWN_LOCK(sc); 3514290564Savos if (sc->sc_flags & URTWN_RUNNING) 3515290564Savos urtwn_set_promisc(sc); 3516290564Savos URTWN_UNLOCK(sc); 3517290564Savos} 3518290564Savos 3519290564Savosstatic void 3520283540Sglebiusurtwn_update_mcast(struct ieee80211com *ic) 3521251538Srpaulo{ 3522251538Srpaulo /* XXX do nothing? */ 3523251538Srpaulo} 3524251538Srpaulo 3525251538Srpaulostatic void 3526251538Srpaulourtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3527251538Srpaulo struct ieee80211_channel *extc) 3528251538Srpaulo{ 3529287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3530251538Srpaulo uint32_t reg; 3531251538Srpaulo u_int chan; 3532251538Srpaulo int i; 3533251538Srpaulo 3534251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3535251538Srpaulo if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3536251538Srpaulo device_printf(sc->sc_dev, 3537251538Srpaulo "%s: invalid channel %x\n", __func__, chan); 3538251538Srpaulo return; 3539251538Srpaulo } 3540251538Srpaulo 3541251538Srpaulo /* Set Tx power for this new channel. */ 3542251538Srpaulo urtwn_set_txpower(sc, c, extc); 3543251538Srpaulo 3544251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3545251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3546251538Srpaulo RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3547251538Srpaulo } 3548251538Srpaulo#ifndef IEEE80211_NO_HT 3549251538Srpaulo if (extc != NULL) { 3550251538Srpaulo /* Is secondary channel below or above primary? */ 3551251538Srpaulo int prichlo = c->ic_freq < extc->ic_freq; 3552251538Srpaulo 3553251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3554251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3555251538Srpaulo 3556251538Srpaulo reg = urtwn_read_1(sc, R92C_RRSR + 2); 3557251538Srpaulo reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3558251538Srpaulo urtwn_write_1(sc, R92C_RRSR + 2, reg); 3559251538Srpaulo 3560251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3561251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3562251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3563251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3564251538Srpaulo 3565251538Srpaulo /* Set CCK side band. */ 3566251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3567251538Srpaulo reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3568251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3569251538Srpaulo 3570251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3571251538Srpaulo reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3572251538Srpaulo urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3573251538Srpaulo 3574251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3575251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3576251538Srpaulo ~R92C_FPGA0_ANAPARAM2_CBW20); 3577251538Srpaulo 3578251538Srpaulo reg = urtwn_bb_read(sc, 0x818); 3579251538Srpaulo reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3580251538Srpaulo urtwn_bb_write(sc, 0x818, reg); 3581251538Srpaulo 3582251538Srpaulo /* Select 40MHz bandwidth. */ 3583251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3584251538Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan); 3585251538Srpaulo } else 3586251538Srpaulo#endif 3587251538Srpaulo { 3588251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3589251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3590251538Srpaulo 3591251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3592251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3593251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3594251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3595251538Srpaulo 3596264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3597264912Skevlo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3598264912Skevlo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3599264912Skevlo R92C_FPGA0_ANAPARAM2_CBW20); 3600264912Skevlo } 3601281069Srpaulo 3602251538Srpaulo /* Select 20MHz bandwidth. */ 3603251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3604281069Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan | 3605264912Skevlo ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3606264912Skevlo R92C_RF_CHNLBW_BW20)); 3607251538Srpaulo } 3608251538Srpaulo} 3609251538Srpaulo 3610251538Srpaulostatic void 3611251538Srpaulourtwn_iq_calib(struct urtwn_softc *sc) 3612251538Srpaulo{ 3613251538Srpaulo /* TODO */ 3614251538Srpaulo} 3615251538Srpaulo 3616251538Srpaulostatic void 3617251538Srpaulourtwn_lc_calib(struct urtwn_softc *sc) 3618251538Srpaulo{ 3619251538Srpaulo uint32_t rf_ac[2]; 3620251538Srpaulo uint8_t txmode; 3621251538Srpaulo int i; 3622251538Srpaulo 3623251538Srpaulo txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3624251538Srpaulo if ((txmode & 0x70) != 0) { 3625251538Srpaulo /* Disable all continuous Tx. */ 3626251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3627251538Srpaulo 3628251538Srpaulo /* Set RF mode to standby mode. */ 3629251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3630251538Srpaulo rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3631251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, 3632251538Srpaulo RW(rf_ac[i], R92C_RF_AC_MODE, 3633251538Srpaulo R92C_RF_AC_MODE_STANDBY)); 3634251538Srpaulo } 3635251538Srpaulo } else { 3636251538Srpaulo /* Block all Tx queues. */ 3637251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3638251538Srpaulo } 3639251538Srpaulo /* Start calibration. */ 3640251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3641251538Srpaulo urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3642251538Srpaulo 3643251538Srpaulo /* Give calibration the time to complete. */ 3644266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3645251538Srpaulo 3646251538Srpaulo /* Restore configuration. */ 3647251538Srpaulo if ((txmode & 0x70) != 0) { 3648251538Srpaulo /* Restore Tx mode. */ 3649251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3650251538Srpaulo /* Restore RF mode. */ 3651251538Srpaulo for (i = 0; i < sc->nrxchains; i++) 3652251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3653251538Srpaulo } else { 3654251538Srpaulo /* Unblock all Tx queues. */ 3655251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3656251538Srpaulo } 3657251538Srpaulo} 3658251538Srpaulo 3659251538Srpaulostatic void 3660287197Sglebiusurtwn_init(struct urtwn_softc *sc) 3661251538Srpaulo{ 3662287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3663287197Sglebius struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3664287197Sglebius uint8_t macaddr[IEEE80211_ADDR_LEN]; 3665251538Srpaulo uint32_t reg; 3666251538Srpaulo int error; 3667251538Srpaulo 3668264864Skevlo URTWN_ASSERT_LOCKED(sc); 3669264864Skevlo 3670287197Sglebius if (sc->sc_flags & URTWN_RUNNING) 3671287197Sglebius urtwn_stop(sc); 3672251538Srpaulo 3673251538Srpaulo /* Init firmware commands ring. */ 3674251538Srpaulo sc->fwcur = 0; 3675251538Srpaulo 3676251538Srpaulo /* Allocate Tx/Rx buffers. */ 3677251538Srpaulo error = urtwn_alloc_rx_list(sc); 3678251538Srpaulo if (error != 0) 3679251538Srpaulo goto fail; 3680281069Srpaulo 3681251538Srpaulo error = urtwn_alloc_tx_list(sc); 3682251538Srpaulo if (error != 0) 3683251538Srpaulo goto fail; 3684251538Srpaulo 3685251538Srpaulo /* Power on adapter. */ 3686251538Srpaulo error = urtwn_power_on(sc); 3687251538Srpaulo if (error != 0) 3688251538Srpaulo goto fail; 3689251538Srpaulo 3690251538Srpaulo /* Initialize DMA. */ 3691251538Srpaulo error = urtwn_dma_init(sc); 3692251538Srpaulo if (error != 0) 3693251538Srpaulo goto fail; 3694251538Srpaulo 3695251538Srpaulo /* Set info size in Rx descriptors (in 64-bit words). */ 3696251538Srpaulo urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3697251538Srpaulo 3698251538Srpaulo /* Init interrupts. */ 3699264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3700264912Skevlo urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3701264912Skevlo urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3702264912Skevlo R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3703264912Skevlo urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3704264912Skevlo R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3705264912Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3706264912Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3707264912Skevlo R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3708264912Skevlo } else { 3709264912Skevlo urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3710264912Skevlo urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3711264912Skevlo } 3712251538Srpaulo 3713251538Srpaulo /* Set MAC address. */ 3714287197Sglebius IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3715287197Sglebius urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3716251538Srpaulo 3717251538Srpaulo /* Set initial network type. */ 3718289811Savos urtwn_set_mode(sc, R92C_MSR_INFRA); 3719251538Srpaulo 3720290564Savos /* Initialize Rx filter. */ 3721251538Srpaulo urtwn_rxfilter_init(sc); 3722251538Srpaulo 3723282623Skevlo /* Set response rate. */ 3724251538Srpaulo reg = urtwn_read_4(sc, R92C_RRSR); 3725251538Srpaulo reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3726251538Srpaulo urtwn_write_4(sc, R92C_RRSR, reg); 3727251538Srpaulo 3728251538Srpaulo /* Set short/long retry limits. */ 3729251538Srpaulo urtwn_write_2(sc, R92C_RL, 3730251538Srpaulo SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3731251538Srpaulo 3732251538Srpaulo /* Initialize EDCA parameters. */ 3733251538Srpaulo urtwn_edca_init(sc); 3734251538Srpaulo 3735251538Srpaulo /* Setup rate fallback. */ 3736264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3737264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3738264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3739264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3740264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3741264912Skevlo } 3742251538Srpaulo 3743251538Srpaulo urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3744251538Srpaulo urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3745251538Srpaulo R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3746251538Srpaulo /* Set ACK timeout. */ 3747251538Srpaulo urtwn_write_1(sc, R92C_ACKTO, 0x40); 3748251538Srpaulo 3749251538Srpaulo /* Setup USB aggregation. */ 3750251538Srpaulo reg = urtwn_read_4(sc, R92C_TDECTRL); 3751251538Srpaulo reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3752251538Srpaulo urtwn_write_4(sc, R92C_TDECTRL, reg); 3753251538Srpaulo urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3754251538Srpaulo urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3755251538Srpaulo R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3756251538Srpaulo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3757264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3758264912Skevlo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3759282266Skevlo else { 3760264912Skevlo urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3761282266Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3762282266Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3763282266Skevlo R92C_USB_SPECIAL_OPTION_AGG_EN); 3764282266Skevlo urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3765282266Skevlo urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3766282266Skevlo } 3767251538Srpaulo 3768251538Srpaulo /* Initialize beacon parameters. */ 3769264912Skevlo urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3770251538Srpaulo urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3771251538Srpaulo urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3772251538Srpaulo urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3773251538Srpaulo urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3774251538Srpaulo 3775264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3776264912Skevlo /* Setup AMPDU aggregation. */ 3777264912Skevlo urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3778264912Skevlo urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3779264912Skevlo urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3780251538Srpaulo 3781264912Skevlo urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3782264912Skevlo } 3783251538Srpaulo 3784251538Srpaulo /* Load 8051 microcode. */ 3785251538Srpaulo error = urtwn_load_firmware(sc); 3786251538Srpaulo if (error != 0) 3787251538Srpaulo goto fail; 3788251538Srpaulo 3789251538Srpaulo /* Initialize MAC/BB/RF blocks. */ 3790251538Srpaulo urtwn_mac_init(sc); 3791251538Srpaulo urtwn_bb_init(sc); 3792251538Srpaulo urtwn_rf_init(sc); 3793251538Srpaulo 3794290564Savos /* Reinitialize Rx filter (D3845 is not committed yet). */ 3795290564Savos urtwn_rxfilter_init(sc); 3796290564Savos 3797264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3798264912Skevlo urtwn_write_2(sc, R92C_CR, 3799264912Skevlo urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3800264912Skevlo R92C_CR_MACRXEN); 3801264912Skevlo } 3802264912Skevlo 3803251538Srpaulo /* Turn CCK and OFDM blocks on. */ 3804251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3805251538Srpaulo reg |= R92C_RFMOD_CCK_EN; 3806251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3807251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3808251538Srpaulo reg |= R92C_RFMOD_OFDM_EN; 3809251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3810251538Srpaulo 3811251538Srpaulo /* Clear per-station keys table. */ 3812251538Srpaulo urtwn_cam_init(sc); 3813251538Srpaulo 3814251538Srpaulo /* Enable hardware sequence numbering. */ 3815251538Srpaulo urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3816251538Srpaulo 3817251538Srpaulo /* Perform LO and IQ calibrations. */ 3818251538Srpaulo urtwn_iq_calib(sc); 3819251538Srpaulo /* Perform LC calibration. */ 3820251538Srpaulo urtwn_lc_calib(sc); 3821251538Srpaulo 3822251538Srpaulo /* Fix USB interference issue. */ 3823264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3824264912Skevlo urtwn_write_1(sc, 0xfe40, 0xe0); 3825264912Skevlo urtwn_write_1(sc, 0xfe41, 0x8d); 3826264912Skevlo urtwn_write_1(sc, 0xfe42, 0x80); 3827251538Srpaulo 3828264912Skevlo urtwn_pa_bias_init(sc); 3829264912Skevlo } 3830251538Srpaulo 3831251538Srpaulo /* Initialize GPIO setting. */ 3832251538Srpaulo urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3833251538Srpaulo urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3834251538Srpaulo 3835251538Srpaulo /* Fix for lower temperature. */ 3836264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 3837264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 3838251538Srpaulo 3839251538Srpaulo usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3840251538Srpaulo 3841287197Sglebius sc->sc_flags |= URTWN_RUNNING; 3842251538Srpaulo 3843251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3844251538Srpaulofail: 3845251538Srpaulo return; 3846251538Srpaulo} 3847251538Srpaulo 3848251538Srpaulostatic void 3849287197Sglebiusurtwn_stop(struct urtwn_softc *sc) 3850251538Srpaulo{ 3851251538Srpaulo 3852264864Skevlo URTWN_ASSERT_LOCKED(sc); 3853287197Sglebius sc->sc_flags &= ~URTWN_RUNNING; 3854251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 3855251538Srpaulo urtwn_abort_xfers(sc); 3856288353Sadrian 3857288353Sadrian urtwn_drain_mbufq(sc); 3858251538Srpaulo} 3859251538Srpaulo 3860251538Srpaulostatic void 3861251538Srpaulourtwn_abort_xfers(struct urtwn_softc *sc) 3862251538Srpaulo{ 3863251538Srpaulo int i; 3864251538Srpaulo 3865251538Srpaulo URTWN_ASSERT_LOCKED(sc); 3866251538Srpaulo 3867251538Srpaulo /* abort any pending transfers */ 3868251538Srpaulo for (i = 0; i < URTWN_N_TRANSFER; i++) 3869251538Srpaulo usbd_transfer_stop(sc->sc_xfer[i]); 3870251538Srpaulo} 3871251538Srpaulo 3872251538Srpaulostatic int 3873251538Srpaulourtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3874251538Srpaulo const struct ieee80211_bpf_params *params) 3875251538Srpaulo{ 3876251538Srpaulo struct ieee80211com *ic = ni->ni_ic; 3877286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 3878251538Srpaulo struct urtwn_data *bf; 3879290630Savos int error; 3880251538Srpaulo 3881251538Srpaulo /* prevent management frames from being sent if we're not ready */ 3882290630Savos URTWN_LOCK(sc); 3883287197Sglebius if (!(sc->sc_flags & URTWN_RUNNING)) { 3884290630Savos error = ENETDOWN; 3885290630Savos goto end; 3886251538Srpaulo } 3887290630Savos 3888251538Srpaulo bf = urtwn_getbuf(sc); 3889251538Srpaulo if (bf == NULL) { 3890290630Savos error = ENOBUFS; 3891290630Savos goto end; 3892251538Srpaulo } 3893251538Srpaulo 3894290630Savos if ((error = urtwn_tx_data(sc, ni, m, bf)) != 0) { 3895251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3896290630Savos goto end; 3897251538Srpaulo } 3898290630Savos 3899288353Sadrian sc->sc_txtimer = 5; 3900290630Savos callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3901290630Savos 3902290630Savosend: 3903290630Savos if (error != 0) 3904290630Savos m_freem(m); 3905290630Savos 3906251538Srpaulo URTWN_UNLOCK(sc); 3907251538Srpaulo 3908290630Savos return (error); 3909251538Srpaulo} 3910251538Srpaulo 3911266472Shselaskystatic void 3912266472Shselaskyurtwn_ms_delay(struct urtwn_softc *sc) 3913266472Shselasky{ 3914266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3915266472Shselasky} 3916266472Shselasky 3917251538Srpaulostatic device_method_t urtwn_methods[] = { 3918251538Srpaulo /* Device interface */ 3919251538Srpaulo DEVMETHOD(device_probe, urtwn_match), 3920251538Srpaulo DEVMETHOD(device_attach, urtwn_attach), 3921251538Srpaulo DEVMETHOD(device_detach, urtwn_detach), 3922251538Srpaulo 3923264912Skevlo DEVMETHOD_END 3924251538Srpaulo}; 3925251538Srpaulo 3926251538Srpaulostatic driver_t urtwn_driver = { 3927251538Srpaulo "urtwn", 3928251538Srpaulo urtwn_methods, 3929251538Srpaulo sizeof(struct urtwn_softc) 3930251538Srpaulo}; 3931251538Srpaulo 3932251538Srpaulostatic devclass_t urtwn_devclass; 3933251538Srpaulo 3934251538SrpauloDRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3935251538SrpauloMODULE_DEPEND(urtwn, usb, 1, 1, 1); 3936251538SrpauloMODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3937251538SrpauloMODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3938251538SrpauloMODULE_VERSION(urtwn, 1); 3939