if_urtwn.c revision 290631
1251538Srpaulo/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2251538Srpaulo 3251538Srpaulo/*- 4251538Srpaulo * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5264912Skevlo * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6251538Srpaulo * 7251538Srpaulo * Permission to use, copy, modify, and distribute this software for any 8251538Srpaulo * purpose with or without fee is hereby granted, provided that the above 9251538Srpaulo * copyright notice and this permission notice appear in all copies. 10251538Srpaulo * 11251538Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12251538Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13251538Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14251538Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15251538Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16251538Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17251538Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18251538Srpaulo */ 19251538Srpaulo 20251538Srpaulo#include <sys/cdefs.h> 21251538Srpaulo__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 290631 2015-11-10 00:12:00Z avos $"); 22251538Srpaulo 23251538Srpaulo/* 24264912Skevlo * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25251538Srpaulo */ 26251538Srpaulo 27288353Sadrian#include "opt_wlan.h" 28288353Sadrian 29251538Srpaulo#include <sys/param.h> 30251538Srpaulo#include <sys/sockio.h> 31251538Srpaulo#include <sys/sysctl.h> 32251538Srpaulo#include <sys/lock.h> 33251538Srpaulo#include <sys/mutex.h> 34251538Srpaulo#include <sys/mbuf.h> 35251538Srpaulo#include <sys/kernel.h> 36251538Srpaulo#include <sys/socket.h> 37251538Srpaulo#include <sys/systm.h> 38251538Srpaulo#include <sys/malloc.h> 39251538Srpaulo#include <sys/module.h> 40251538Srpaulo#include <sys/bus.h> 41251538Srpaulo#include <sys/endian.h> 42251538Srpaulo#include <sys/linker.h> 43251538Srpaulo#include <sys/firmware.h> 44251538Srpaulo#include <sys/kdb.h> 45251538Srpaulo 46251538Srpaulo#include <machine/bus.h> 47251538Srpaulo#include <machine/resource.h> 48251538Srpaulo#include <sys/rman.h> 49251538Srpaulo 50251538Srpaulo#include <net/bpf.h> 51251538Srpaulo#include <net/if.h> 52257176Sglebius#include <net/if_var.h> 53251538Srpaulo#include <net/if_arp.h> 54251538Srpaulo#include <net/ethernet.h> 55251538Srpaulo#include <net/if_dl.h> 56251538Srpaulo#include <net/if_media.h> 57251538Srpaulo#include <net/if_types.h> 58251538Srpaulo 59251538Srpaulo#include <netinet/in.h> 60251538Srpaulo#include <netinet/in_systm.h> 61251538Srpaulo#include <netinet/in_var.h> 62251538Srpaulo#include <netinet/if_ether.h> 63251538Srpaulo#include <netinet/ip.h> 64251538Srpaulo 65251538Srpaulo#include <net80211/ieee80211_var.h> 66288088Sadrian#include <net80211/ieee80211_input.h> 67251538Srpaulo#include <net80211/ieee80211_regdomain.h> 68251538Srpaulo#include <net80211/ieee80211_radiotap.h> 69251538Srpaulo#include <net80211/ieee80211_ratectl.h> 70251538Srpaulo 71251538Srpaulo#include <dev/usb/usb.h> 72251538Srpaulo#include <dev/usb/usbdi.h> 73251538Srpaulo#include "usbdevs.h" 74251538Srpaulo 75251538Srpaulo#define USB_DEBUG_VAR urtwn_debug 76251538Srpaulo#include <dev/usb/usb_debug.h> 77251538Srpaulo 78251538Srpaulo#include <dev/usb/wlan/if_urtwnreg.h> 79289167Sadrian#include <dev/usb/wlan/if_urtwnvar.h> 80251538Srpaulo 81251538Srpaulo#ifdef USB_DEBUG 82251538Srpaulostatic int urtwn_debug = 0; 83251538Srpaulo 84251538SrpauloSYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 85276701ShselaskySYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 86251538Srpaulo "Debug level"); 87251538Srpaulo#endif 88251538Srpaulo 89288088Sadrian#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 90251538Srpaulo 91251538Srpaulo/* various supported device vendors/products */ 92251596Srpaulostatic const STRUCT_USB_HOST_ID urtwn_devs[] = { 93251538Srpaulo#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 94264912Skevlo#define URTWN_RTL8188E_DEV(v,p) \ 95264912Skevlo { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 96264912Skevlo#define URTWN_RTL8188E 1 97251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_1), 98251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_2), 99251538Srpaulo URTWN_DEV(ABOCOM, RTL8192CU), 100251538Srpaulo URTWN_DEV(ASUS, RTL8192CU), 101266721Skevlo URTWN_DEV(ASUS, USBN10NANO), 102251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_1), 103251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_2), 104251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CU), 105251538Srpaulo URTWN_DEV(BELKIN, F7D2102), 106251538Srpaulo URTWN_DEV(BELKIN, RTL8188CU), 107251538Srpaulo URTWN_DEV(BELKIN, RTL8192CU), 108251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_1), 109251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_2), 110251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_3), 111251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_4), 112251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_5), 113251538Srpaulo URTWN_DEV(COREGA, RTL8192CU), 114251538Srpaulo URTWN_DEV(DLINK, RTL8188CU), 115251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_1), 116251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_2), 117251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_3), 118252196Skevlo URTWN_DEV(DLINK, DWA131B), 119251538Srpaulo URTWN_DEV(EDIMAX, EW7811UN), 120251538Srpaulo URTWN_DEV(EDIMAX, RTL8192CU), 121251538Srpaulo URTWN_DEV(FEIXUN, RTL8188CU), 122251538Srpaulo URTWN_DEV(FEIXUN, RTL8192CU), 123251538Srpaulo URTWN_DEV(GUILLEMOT, HWNUP150), 124251538Srpaulo URTWN_DEV(HAWKING, RTL8192CU), 125251538Srpaulo URTWN_DEV(HP3, RTL8188CU), 126251538Srpaulo URTWN_DEV(NETGEAR, WNA1000M), 127251538Srpaulo URTWN_DEV(NETGEAR, RTL8192CU), 128251538Srpaulo URTWN_DEV(NETGEAR4, RTL8188CU), 129251538Srpaulo URTWN_DEV(NOVATECH, RTL8188CU), 130251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_1), 131251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_2), 132251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_3), 133251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_4), 134251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CUS), 135251538Srpaulo URTWN_DEV(PLANEX2, RTL8192CU), 136251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_0), 137251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_1), 138251538Srpaulo URTWN_DEV(REALTEK, RTL8188CTV), 139251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_0), 140251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_1), 141251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_2), 142282119Skevlo URTWN_DEV(REALTEK, RTL8188CU_3), 143251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_COMBO), 144251538Srpaulo URTWN_DEV(REALTEK, RTL8188CUS), 145251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_1), 146251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_2), 147272410Shselasky URTWN_DEV(REALTEK, RTL8188RU_3), 148251538Srpaulo URTWN_DEV(REALTEK, RTL8191CU), 149251538Srpaulo URTWN_DEV(REALTEK, RTL8192CE), 150251538Srpaulo URTWN_DEV(REALTEK, RTL8192CU), 151251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_1), 152251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_2), 153251538Srpaulo URTWN_DEV(SITECOMEU, RTL8192CU), 154251538Srpaulo URTWN_DEV(TRENDNET, RTL8188CU), 155251538Srpaulo URTWN_DEV(TRENDNET, RTL8192CU), 156251538Srpaulo URTWN_DEV(ZYXEL, RTL8192CU), 157264912Skevlo /* URTWN_RTL8188E */ 158273589Skevlo URTWN_RTL8188E_DEV(DLINK, DWA123D1), 159270191Skevlo URTWN_RTL8188E_DEV(DLINK, DWA125D1), 160273589Skevlo URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 161264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 162264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 163264912Skevlo#undef URTWN_RTL8188E_DEV 164251538Srpaulo#undef URTWN_DEV 165251538Srpaulo}; 166251538Srpaulo 167251538Srpaulostatic device_probe_t urtwn_match; 168251538Srpaulostatic device_attach_t urtwn_attach; 169251538Srpaulostatic device_detach_t urtwn_detach; 170251538Srpaulo 171251538Srpaulostatic usb_callback_t urtwn_bulk_tx_callback; 172251538Srpaulostatic usb_callback_t urtwn_bulk_rx_callback; 173251538Srpaulo 174288353Sadrianstatic void urtwn_drain_mbufq(struct urtwn_softc *sc); 175287197Sglebiusstatic usb_error_t urtwn_do_request(struct urtwn_softc *, 176287197Sglebius struct usb_device_request *, void *); 177251538Srpaulostatic struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 178251538Srpaulo const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 179251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN], 180251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN]); 181251538Srpaulostatic void urtwn_vap_delete(struct ieee80211vap *); 182281069Srpaulostatic struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 183251538Srpaulo int *); 184281069Srpaulostatic struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 185251538Srpaulo int *, int8_t *); 186289891Savosstatic void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 187289891Savos int); 188281069Srpaulostatic int urtwn_alloc_list(struct urtwn_softc *, 189251538Srpaulo struct urtwn_data[], int, int); 190251538Srpaulostatic int urtwn_alloc_rx_list(struct urtwn_softc *); 191251538Srpaulostatic int urtwn_alloc_tx_list(struct urtwn_softc *); 192251538Srpaulostatic void urtwn_free_list(struct urtwn_softc *, 193251538Srpaulo struct urtwn_data data[], int); 194289066Skevlostatic void urtwn_free_rx_list(struct urtwn_softc *); 195289066Skevlostatic void urtwn_free_tx_list(struct urtwn_softc *); 196251538Srpaulostatic struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 197251538Srpaulostatic struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 198281069Srpaulostatic int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 199251538Srpaulo uint8_t *, int); 200251538Srpaulostatic void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 201251538Srpaulostatic void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 202251538Srpaulostatic void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 203281069Srpaulostatic int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 204251538Srpaulo uint8_t *, int); 205251538Srpaulostatic uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 206251538Srpaulostatic uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 207251538Srpaulostatic uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 208281069Srpaulostatic int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 209251538Srpaulo const void *, int); 210264912Skevlostatic void urtwn_r92c_rf_write(struct urtwn_softc *, int, 211264912Skevlo uint8_t, uint32_t); 212281069Srpaulostatic void urtwn_r88e_rf_write(struct urtwn_softc *, int, 213264912Skevlo uint8_t, uint32_t); 214251538Srpaulostatic uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 215281069Srpaulostatic int urtwn_llt_write(struct urtwn_softc *, uint32_t, 216251538Srpaulo uint32_t); 217251538Srpaulostatic uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 218251538Srpaulostatic void urtwn_efuse_read(struct urtwn_softc *); 219264912Skevlostatic void urtwn_efuse_switch_power(struct urtwn_softc *); 220251538Srpaulostatic int urtwn_read_chipid(struct urtwn_softc *); 221251538Srpaulostatic void urtwn_read_rom(struct urtwn_softc *); 222264912Skevlostatic void urtwn_r88e_read_rom(struct urtwn_softc *); 223251538Srpaulostatic int urtwn_ra_init(struct urtwn_softc *); 224290631Savosstatic void urtwn_init_beacon(struct urtwn_softc *, 225290631Savos struct urtwn_vap *); 226290631Savosstatic int urtwn_setup_beacon(struct urtwn_softc *, 227290631Savos struct ieee80211_node *); 228290631Savosstatic void urtwn_update_beacon(struct ieee80211vap *, int); 229290631Savosstatic int urtwn_tx_beacon(struct urtwn_softc *sc, 230290631Savos struct urtwn_vap *); 231290631Savosstatic void urtwn_tsf_sync_enable(struct urtwn_softc *, 232290631Savos struct ieee80211vap *); 233251538Srpaulostatic void urtwn_set_led(struct urtwn_softc *, int, int); 234289811Savosstatic void urtwn_set_mode(struct urtwn_softc *, uint8_t); 235281069Srpaulostatic int urtwn_newstate(struct ieee80211vap *, 236251538Srpaulo enum ieee80211_state, int); 237251538Srpaulostatic void urtwn_watchdog(void *); 238251538Srpaulostatic void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 239251538Srpaulostatic int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 240264912Skevlostatic int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 241290630Savosstatic int urtwn_tx_data(struct urtwn_softc *, 242251538Srpaulo struct ieee80211_node *, struct mbuf *, 243251538Srpaulo struct urtwn_data *); 244290630Savosstatic void urtwn_tx_start(struct urtwn_softc *, struct mbuf *, 245290630Savos uint8_t, struct urtwn_data *); 246287197Sglebiusstatic int urtwn_transmit(struct ieee80211com *, struct mbuf *); 247287197Sglebiusstatic void urtwn_start(struct urtwn_softc *); 248287197Sglebiusstatic void urtwn_parent(struct ieee80211com *); 249264912Skevlostatic int urtwn_r92c_power_on(struct urtwn_softc *); 250264912Skevlostatic int urtwn_r88e_power_on(struct urtwn_softc *); 251251538Srpaulostatic int urtwn_llt_init(struct urtwn_softc *); 252251538Srpaulostatic void urtwn_fw_reset(struct urtwn_softc *); 253264912Skevlostatic void urtwn_r88e_fw_reset(struct urtwn_softc *); 254281069Srpaulostatic int urtwn_fw_loadpage(struct urtwn_softc *, int, 255251538Srpaulo const uint8_t *, int); 256251538Srpaulostatic int urtwn_load_firmware(struct urtwn_softc *); 257264912Skevlostatic int urtwn_r92c_dma_init(struct urtwn_softc *); 258264912Skevlostatic int urtwn_r88e_dma_init(struct urtwn_softc *); 259251538Srpaulostatic void urtwn_mac_init(struct urtwn_softc *); 260251538Srpaulostatic void urtwn_bb_init(struct urtwn_softc *); 261251538Srpaulostatic void urtwn_rf_init(struct urtwn_softc *); 262251538Srpaulostatic void urtwn_cam_init(struct urtwn_softc *); 263251538Srpaulostatic void urtwn_pa_bias_init(struct urtwn_softc *); 264251538Srpaulostatic void urtwn_rxfilter_init(struct urtwn_softc *); 265251538Srpaulostatic void urtwn_edca_init(struct urtwn_softc *); 266281069Srpaulostatic void urtwn_write_txpower(struct urtwn_softc *, int, 267251538Srpaulo uint16_t[]); 268251538Srpaulostatic void urtwn_get_txpower(struct urtwn_softc *, int, 269281069Srpaulo struct ieee80211_channel *, 270251538Srpaulo struct ieee80211_channel *, uint16_t[]); 271264912Skevlostatic void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 272281069Srpaulo struct ieee80211_channel *, 273264912Skevlo struct ieee80211_channel *, uint16_t[]); 274251538Srpaulostatic void urtwn_set_txpower(struct urtwn_softc *, 275281069Srpaulo struct ieee80211_channel *, 276251538Srpaulo struct ieee80211_channel *); 277290048Savosstatic void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 278290048Savosstatic void urtwn_set_gain(struct urtwn_softc *, uint8_t); 279251538Srpaulostatic void urtwn_scan_start(struct ieee80211com *); 280251538Srpaulostatic void urtwn_scan_end(struct ieee80211com *); 281251538Srpaulostatic void urtwn_set_channel(struct ieee80211com *); 282290564Savosstatic void urtwn_set_promisc(struct urtwn_softc *); 283290564Savosstatic void urtwn_update_promisc(struct ieee80211com *); 284289066Skevlostatic void urtwn_update_mcast(struct ieee80211com *); 285251538Srpaulostatic void urtwn_set_chan(struct urtwn_softc *, 286281069Srpaulo struct ieee80211_channel *, 287251538Srpaulo struct ieee80211_channel *); 288251538Srpaulostatic void urtwn_iq_calib(struct urtwn_softc *); 289251538Srpaulostatic void urtwn_lc_calib(struct urtwn_softc *); 290287197Sglebiusstatic void urtwn_init(struct urtwn_softc *); 291287197Sglebiusstatic void urtwn_stop(struct urtwn_softc *); 292251538Srpaulostatic void urtwn_abort_xfers(struct urtwn_softc *); 293251538Srpaulostatic int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 294251538Srpaulo const struct ieee80211_bpf_params *); 295266472Shselaskystatic void urtwn_ms_delay(struct urtwn_softc *); 296251538Srpaulo 297251538Srpaulo/* Aliases. */ 298251538Srpaulo#define urtwn_bb_write urtwn_write_4 299251538Srpaulo#define urtwn_bb_read urtwn_read_4 300251538Srpaulo 301251538Srpaulostatic const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 302251538Srpaulo [URTWN_BULK_RX] = { 303251538Srpaulo .type = UE_BULK, 304251538Srpaulo .endpoint = UE_ADDR_ANY, 305251538Srpaulo .direction = UE_DIR_IN, 306251538Srpaulo .bufsize = URTWN_RXBUFSZ, 307251538Srpaulo .flags = { 308251538Srpaulo .pipe_bof = 1, 309251538Srpaulo .short_xfer_ok = 1 310251538Srpaulo }, 311251538Srpaulo .callback = urtwn_bulk_rx_callback, 312251538Srpaulo }, 313251538Srpaulo [URTWN_BULK_TX_BE] = { 314251538Srpaulo .type = UE_BULK, 315251538Srpaulo .endpoint = 0x03, 316251538Srpaulo .direction = UE_DIR_OUT, 317251538Srpaulo .bufsize = URTWN_TXBUFSZ, 318251538Srpaulo .flags = { 319251538Srpaulo .ext_buffer = 1, 320251538Srpaulo .pipe_bof = 1, 321251538Srpaulo .force_short_xfer = 1 322251538Srpaulo }, 323251538Srpaulo .callback = urtwn_bulk_tx_callback, 324251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 325251538Srpaulo }, 326251538Srpaulo [URTWN_BULK_TX_BK] = { 327251538Srpaulo .type = UE_BULK, 328251538Srpaulo .endpoint = 0x03, 329251538Srpaulo .direction = UE_DIR_OUT, 330251538Srpaulo .bufsize = URTWN_TXBUFSZ, 331251538Srpaulo .flags = { 332251538Srpaulo .ext_buffer = 1, 333251538Srpaulo .pipe_bof = 1, 334251538Srpaulo .force_short_xfer = 1, 335251538Srpaulo }, 336251538Srpaulo .callback = urtwn_bulk_tx_callback, 337251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 338251538Srpaulo }, 339251538Srpaulo [URTWN_BULK_TX_VI] = { 340251538Srpaulo .type = UE_BULK, 341251538Srpaulo .endpoint = 0x02, 342251538Srpaulo .direction = UE_DIR_OUT, 343251538Srpaulo .bufsize = URTWN_TXBUFSZ, 344251538Srpaulo .flags = { 345251538Srpaulo .ext_buffer = 1, 346251538Srpaulo .pipe_bof = 1, 347251538Srpaulo .force_short_xfer = 1 348251538Srpaulo }, 349251538Srpaulo .callback = urtwn_bulk_tx_callback, 350251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 351251538Srpaulo }, 352251538Srpaulo [URTWN_BULK_TX_VO] = { 353251538Srpaulo .type = UE_BULK, 354251538Srpaulo .endpoint = 0x02, 355251538Srpaulo .direction = UE_DIR_OUT, 356251538Srpaulo .bufsize = URTWN_TXBUFSZ, 357251538Srpaulo .flags = { 358251538Srpaulo .ext_buffer = 1, 359251538Srpaulo .pipe_bof = 1, 360251538Srpaulo .force_short_xfer = 1 361251538Srpaulo }, 362251538Srpaulo .callback = urtwn_bulk_tx_callback, 363251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 364251538Srpaulo }, 365251538Srpaulo}; 366251538Srpaulo 367251538Srpaulostatic int 368251538Srpaulourtwn_match(device_t self) 369251538Srpaulo{ 370251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 371251538Srpaulo 372251538Srpaulo if (uaa->usb_mode != USB_MODE_HOST) 373251538Srpaulo return (ENXIO); 374251538Srpaulo if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 375251538Srpaulo return (ENXIO); 376251538Srpaulo if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 377251538Srpaulo return (ENXIO); 378251538Srpaulo 379251538Srpaulo return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 380251538Srpaulo} 381251538Srpaulo 382251538Srpaulostatic int 383251538Srpaulourtwn_attach(device_t self) 384251538Srpaulo{ 385251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 386251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 387287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 388251538Srpaulo uint8_t iface_index, bands; 389251538Srpaulo int error; 390251538Srpaulo 391251538Srpaulo device_set_usb_desc(self); 392251538Srpaulo sc->sc_udev = uaa->device; 393251538Srpaulo sc->sc_dev = self; 394264912Skevlo if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 395264912Skevlo sc->chip |= URTWN_CHIP_88E; 396251538Srpaulo 397251538Srpaulo mtx_init(&sc->sc_mtx, device_get_nameunit(self), 398251538Srpaulo MTX_NETWORK_LOCK, MTX_DEF); 399251538Srpaulo callout_init(&sc->sc_watchdog_ch, 0); 400287197Sglebius mbufq_init(&sc->sc_snd, ifqmaxlen); 401251538Srpaulo 402251538Srpaulo iface_index = URTWN_IFACE_INDEX; 403251538Srpaulo error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 404251538Srpaulo urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 405251538Srpaulo if (error) { 406251538Srpaulo device_printf(self, "could not allocate USB transfers, " 407251538Srpaulo "err=%s\n", usbd_errstr(error)); 408251538Srpaulo goto detach; 409251538Srpaulo } 410251538Srpaulo 411251538Srpaulo URTWN_LOCK(sc); 412251538Srpaulo 413251538Srpaulo error = urtwn_read_chipid(sc); 414251538Srpaulo if (error) { 415251538Srpaulo device_printf(sc->sc_dev, "unsupported test chip\n"); 416251538Srpaulo URTWN_UNLOCK(sc); 417251538Srpaulo goto detach; 418251538Srpaulo } 419251538Srpaulo 420251538Srpaulo /* Determine number of Tx/Rx chains. */ 421251538Srpaulo if (sc->chip & URTWN_CHIP_92C) { 422251538Srpaulo sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 423251538Srpaulo sc->nrxchains = 2; 424251538Srpaulo } else { 425251538Srpaulo sc->ntxchains = 1; 426251538Srpaulo sc->nrxchains = 1; 427251538Srpaulo } 428251538Srpaulo 429264912Skevlo if (sc->chip & URTWN_CHIP_88E) 430264912Skevlo urtwn_r88e_read_rom(sc); 431264912Skevlo else 432264912Skevlo urtwn_read_rom(sc); 433264912Skevlo 434251538Srpaulo device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 435251538Srpaulo (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 436264912Skevlo (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 437251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 438251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 439251538Srpaulo "8188CUS", sc->ntxchains, sc->nrxchains); 440251538Srpaulo 441251538Srpaulo URTWN_UNLOCK(sc); 442251538Srpaulo 443283537Sglebius ic->ic_softc = sc; 444283527Sglebius ic->ic_name = device_get_nameunit(self); 445251538Srpaulo ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 446251538Srpaulo ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 447251538Srpaulo 448251538Srpaulo /* set device capabilities */ 449251538Srpaulo ic->ic_caps = 450251538Srpaulo IEEE80211_C_STA /* station mode */ 451251538Srpaulo | IEEE80211_C_MONITOR /* monitor mode */ 452290631Savos | IEEE80211_C_HOSTAP /* hostap mode */ 453251538Srpaulo | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 454251538Srpaulo | IEEE80211_C_SHSLOT /* short slot time supported */ 455251538Srpaulo | IEEE80211_C_BGSCAN /* capable of bg scanning */ 456251538Srpaulo | IEEE80211_C_WPA /* 802.11i */ 457251538Srpaulo ; 458251538Srpaulo 459251538Srpaulo bands = 0; 460251538Srpaulo setbit(&bands, IEEE80211_MODE_11B); 461251538Srpaulo setbit(&bands, IEEE80211_MODE_11G); 462251538Srpaulo ieee80211_init_channels(ic, NULL, &bands); 463251538Srpaulo 464287197Sglebius ieee80211_ifattach(ic); 465251538Srpaulo ic->ic_raw_xmit = urtwn_raw_xmit; 466251538Srpaulo ic->ic_scan_start = urtwn_scan_start; 467251538Srpaulo ic->ic_scan_end = urtwn_scan_end; 468251538Srpaulo ic->ic_set_channel = urtwn_set_channel; 469287197Sglebius ic->ic_transmit = urtwn_transmit; 470287197Sglebius ic->ic_parent = urtwn_parent; 471251538Srpaulo ic->ic_vap_create = urtwn_vap_create; 472251538Srpaulo ic->ic_vap_delete = urtwn_vap_delete; 473290564Savos ic->ic_update_promisc = urtwn_update_promisc; 474251538Srpaulo ic->ic_update_mcast = urtwn_update_mcast; 475251538Srpaulo 476281069Srpaulo ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 477251538Srpaulo sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 478251538Srpaulo &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 479251538Srpaulo URTWN_RX_RADIOTAP_PRESENT); 480251538Srpaulo 481251538Srpaulo if (bootverbose) 482251538Srpaulo ieee80211_announce(ic); 483251538Srpaulo 484251538Srpaulo return (0); 485251538Srpaulo 486251538Srpaulodetach: 487251538Srpaulo urtwn_detach(self); 488251538Srpaulo return (ENXIO); /* failure */ 489251538Srpaulo} 490251538Srpaulo 491251538Srpaulostatic int 492251538Srpaulourtwn_detach(device_t self) 493251538Srpaulo{ 494251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 495287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 496263153Skevlo unsigned int x; 497281069Srpaulo 498263153Skevlo /* Prevent further ioctls. */ 499263153Skevlo URTWN_LOCK(sc); 500263153Skevlo sc->sc_flags |= URTWN_DETACHED; 501287197Sglebius urtwn_stop(sc); 502263153Skevlo URTWN_UNLOCK(sc); 503251538Srpaulo 504251538Srpaulo callout_drain(&sc->sc_watchdog_ch); 505251538Srpaulo 506288353Sadrian /* stop all USB transfers */ 507288353Sadrian usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 508288353Sadrian 509263153Skevlo /* Prevent further allocations from RX/TX data lists. */ 510263153Skevlo URTWN_LOCK(sc); 511263153Skevlo STAILQ_INIT(&sc->sc_tx_active); 512263153Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 513263153Skevlo STAILQ_INIT(&sc->sc_tx_pending); 514263153Skevlo 515263153Skevlo STAILQ_INIT(&sc->sc_rx_active); 516263153Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 517263153Skevlo URTWN_UNLOCK(sc); 518263153Skevlo 519263153Skevlo /* drain USB transfers */ 520263153Skevlo for (x = 0; x != URTWN_N_TRANSFER; x++) 521263153Skevlo usbd_transfer_drain(sc->sc_xfer[x]); 522263153Skevlo 523263153Skevlo /* Free data buffers. */ 524263153Skevlo URTWN_LOCK(sc); 525263153Skevlo urtwn_free_tx_list(sc); 526263153Skevlo urtwn_free_rx_list(sc); 527263153Skevlo URTWN_UNLOCK(sc); 528263153Skevlo 529251538Srpaulo ieee80211_ifdetach(ic); 530251538Srpaulo mtx_destroy(&sc->sc_mtx); 531251538Srpaulo 532251538Srpaulo return (0); 533251538Srpaulo} 534251538Srpaulo 535251538Srpaulostatic void 536289066Skevlourtwn_drain_mbufq(struct urtwn_softc *sc) 537251538Srpaulo{ 538289066Skevlo struct mbuf *m; 539289066Skevlo struct ieee80211_node *ni; 540289066Skevlo URTWN_ASSERT_LOCKED(sc); 541289066Skevlo while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 542289066Skevlo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 543289066Skevlo m->m_pkthdr.rcvif = NULL; 544289066Skevlo ieee80211_free_node(ni); 545289066Skevlo m_freem(m); 546251538Srpaulo } 547251538Srpaulo} 548251538Srpaulo 549251538Srpaulostatic usb_error_t 550251538Srpaulourtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 551251538Srpaulo void *data) 552251538Srpaulo{ 553251538Srpaulo usb_error_t err; 554251538Srpaulo int ntries = 10; 555251538Srpaulo 556251538Srpaulo URTWN_ASSERT_LOCKED(sc); 557251538Srpaulo 558251538Srpaulo while (ntries--) { 559251538Srpaulo err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 560251538Srpaulo req, data, 0, NULL, 250 /* ms */); 561251538Srpaulo if (err == 0) 562251538Srpaulo break; 563251538Srpaulo 564251538Srpaulo DPRINTFN(1, "Control request failed, %s (retrying)\n", 565251538Srpaulo usbd_errstr(err)); 566251538Srpaulo usb_pause_mtx(&sc->sc_mtx, hz / 100); 567251538Srpaulo } 568251538Srpaulo return (err); 569251538Srpaulo} 570251538Srpaulo 571251538Srpaulostatic struct ieee80211vap * 572251538Srpaulourtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 573251538Srpaulo enum ieee80211_opmode opmode, int flags, 574251538Srpaulo const uint8_t bssid[IEEE80211_ADDR_LEN], 575251538Srpaulo const uint8_t mac[IEEE80211_ADDR_LEN]) 576251538Srpaulo{ 577290631Savos struct urtwn_softc *sc = ic->ic_softc; 578251538Srpaulo struct urtwn_vap *uvp; 579251538Srpaulo struct ieee80211vap *vap; 580251538Srpaulo 581251538Srpaulo if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 582251538Srpaulo return (NULL); 583251538Srpaulo 584287197Sglebius uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 585251538Srpaulo vap = &uvp->vap; 586251538Srpaulo /* enable s/w bmiss handling for sta mode */ 587251538Srpaulo 588281069Srpaulo if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 589287197Sglebius flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 590257743Shselasky /* out of memory */ 591257743Shselasky free(uvp, M_80211_VAP); 592257743Shselasky return (NULL); 593257743Shselasky } 594257743Shselasky 595290631Savos if (opmode == IEEE80211_M_HOSTAP) 596290631Savos urtwn_init_beacon(sc, uvp); 597290631Savos 598251538Srpaulo /* override state transition machine */ 599251538Srpaulo uvp->newstate = vap->iv_newstate; 600251538Srpaulo vap->iv_newstate = urtwn_newstate; 601290631Savos vap->iv_update_beacon = urtwn_update_beacon; 602251538Srpaulo 603251538Srpaulo /* complete setup */ 604251538Srpaulo ieee80211_vap_attach(vap, ieee80211_media_change, 605287197Sglebius ieee80211_media_status, mac); 606251538Srpaulo ic->ic_opmode = opmode; 607251538Srpaulo return (vap); 608251538Srpaulo} 609251538Srpaulo 610251538Srpaulostatic void 611251538Srpaulourtwn_vap_delete(struct ieee80211vap *vap) 612251538Srpaulo{ 613251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 614290631Savos enum ieee80211_opmode opmode = vap->iv_opmode; 615251538Srpaulo 616290631Savos if (opmode == IEEE80211_M_HOSTAP) { 617290631Savos if (uvp->bcn_mbuf != NULL) 618290631Savos m_freem(uvp->bcn_mbuf); 619290631Savos } 620251538Srpaulo ieee80211_vap_detach(vap); 621251538Srpaulo free(uvp, M_80211_VAP); 622251538Srpaulo} 623251538Srpaulo 624251538Srpaulostatic struct mbuf * 625251538Srpaulourtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 626251538Srpaulo{ 627287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 628251538Srpaulo struct ieee80211_frame *wh; 629251538Srpaulo struct mbuf *m; 630251538Srpaulo struct r92c_rx_stat *stat; 631251538Srpaulo uint32_t rxdw0, rxdw3; 632251538Srpaulo uint8_t rate; 633251538Srpaulo int8_t rssi = 0; 634251538Srpaulo int infosz; 635251538Srpaulo 636251538Srpaulo /* 637251538Srpaulo * don't pass packets to the ieee80211 framework if the driver isn't 638251538Srpaulo * RUNNING. 639251538Srpaulo */ 640287197Sglebius if (!(sc->sc_flags & URTWN_RUNNING)) 641251538Srpaulo return (NULL); 642251538Srpaulo 643251538Srpaulo stat = (struct r92c_rx_stat *)buf; 644251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 645251538Srpaulo rxdw3 = le32toh(stat->rxdw3); 646251538Srpaulo 647251538Srpaulo if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 648251538Srpaulo /* 649251538Srpaulo * This should not happen since we setup our Rx filter 650251538Srpaulo * to not receive these frames. 651251538Srpaulo */ 652287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 653251538Srpaulo return (NULL); 654251538Srpaulo } 655290022Savos if (pktlen < sizeof(struct ieee80211_frame_ack) || 656290022Savos pktlen > MCLBYTES) { 657287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 658271303Skevlo return (NULL); 659271303Skevlo } 660251538Srpaulo 661251538Srpaulo rate = MS(rxdw3, R92C_RXDW3_RATE); 662251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 663251538Srpaulo 664251538Srpaulo /* Get RSSI from PHY status descriptor if present. */ 665251538Srpaulo if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 666281069Srpaulo if (sc->chip & URTWN_CHIP_88E) 667264912Skevlo rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 668264912Skevlo else 669264912Skevlo rssi = urtwn_get_rssi(sc, rate, &stat[1]); 670251538Srpaulo /* Update our average RSSI. */ 671251538Srpaulo urtwn_update_avgrssi(sc, rate, rssi); 672251538Srpaulo } 673251538Srpaulo 674260463Skevlo m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 675251538Srpaulo if (m == NULL) { 676251538Srpaulo device_printf(sc->sc_dev, "could not create RX mbuf\n"); 677251538Srpaulo return (NULL); 678251538Srpaulo } 679251538Srpaulo 680251538Srpaulo /* Finalize mbuf. */ 681251538Srpaulo wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 682251538Srpaulo memcpy(mtod(m, uint8_t *), wh, pktlen); 683251538Srpaulo m->m_pkthdr.len = m->m_len = pktlen; 684251538Srpaulo 685251538Srpaulo if (ieee80211_radiotap_active(ic)) { 686251538Srpaulo struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 687251538Srpaulo 688251538Srpaulo tap->wr_flags = 0; 689251538Srpaulo /* Map HW rate index to 802.11 rate. */ 690251538Srpaulo if (!(rxdw3 & R92C_RXDW3_HT)) { 691289758Savos tap->wr_rate = ridx2rate[rate]; 692251538Srpaulo } else if (rate >= 12) { /* MCS0~15. */ 693251538Srpaulo /* Bit 7 set means HT MCS instead of rate. */ 694251538Srpaulo tap->wr_rate = 0x80 | (rate - 12); 695251538Srpaulo } 696251538Srpaulo tap->wr_dbm_antsignal = rssi; 697289816Savos tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 698251538Srpaulo tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 699251538Srpaulo tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 700251538Srpaulo } 701251538Srpaulo 702251538Srpaulo *rssi_p = rssi; 703251538Srpaulo 704251538Srpaulo return (m); 705251538Srpaulo} 706251538Srpaulo 707251538Srpaulostatic struct mbuf * 708251538Srpaulourtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 709251538Srpaulo int8_t *nf) 710251538Srpaulo{ 711251538Srpaulo struct urtwn_softc *sc = data->sc; 712287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 713251538Srpaulo struct r92c_rx_stat *stat; 714251538Srpaulo struct mbuf *m, *m0 = NULL, *prevm = NULL; 715251538Srpaulo uint32_t rxdw0; 716251538Srpaulo uint8_t *buf; 717251538Srpaulo int len, totlen, pktlen, infosz, npkts; 718251538Srpaulo 719251538Srpaulo usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 720251538Srpaulo 721251538Srpaulo if (len < sizeof(*stat)) { 722287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 723251538Srpaulo return (NULL); 724251538Srpaulo } 725251538Srpaulo 726251538Srpaulo buf = data->buf; 727251538Srpaulo /* Get the number of encapsulated frames. */ 728251538Srpaulo stat = (struct r92c_rx_stat *)buf; 729251538Srpaulo npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 730251538Srpaulo DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 731251538Srpaulo 732251538Srpaulo /* Process all of them. */ 733251538Srpaulo while (npkts-- > 0) { 734251538Srpaulo if (len < sizeof(*stat)) 735251538Srpaulo break; 736251538Srpaulo stat = (struct r92c_rx_stat *)buf; 737251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 738251538Srpaulo 739251538Srpaulo pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 740251538Srpaulo if (pktlen == 0) 741251538Srpaulo break; 742251538Srpaulo 743251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 744251538Srpaulo 745251538Srpaulo /* Make sure everything fits in xfer. */ 746251538Srpaulo totlen = sizeof(*stat) + infosz + pktlen; 747251538Srpaulo if (totlen > len) 748251538Srpaulo break; 749251538Srpaulo 750251538Srpaulo m = urtwn_rx_frame(sc, buf, pktlen, rssi); 751251538Srpaulo if (m0 == NULL) 752251538Srpaulo m0 = m; 753251538Srpaulo if (prevm == NULL) 754251538Srpaulo prevm = m; 755251538Srpaulo else { 756251538Srpaulo prevm->m_next = m; 757251538Srpaulo prevm = m; 758251538Srpaulo } 759251538Srpaulo 760251538Srpaulo /* Next chunk is 128-byte aligned. */ 761251538Srpaulo totlen = (totlen + 127) & ~127; 762251538Srpaulo buf += totlen; 763251538Srpaulo len -= totlen; 764251538Srpaulo } 765251538Srpaulo 766251538Srpaulo return (m0); 767251538Srpaulo} 768251538Srpaulo 769251538Srpaulostatic void 770251538Srpaulourtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 771251538Srpaulo{ 772251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 773287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 774290022Savos struct ieee80211_frame_min *wh; 775251538Srpaulo struct ieee80211_node *ni; 776251538Srpaulo struct mbuf *m = NULL, *next; 777251538Srpaulo struct urtwn_data *data; 778251538Srpaulo int8_t nf; 779251538Srpaulo int rssi = 1; 780251538Srpaulo 781251538Srpaulo URTWN_ASSERT_LOCKED(sc); 782251538Srpaulo 783251538Srpaulo switch (USB_GET_STATE(xfer)) { 784251538Srpaulo case USB_ST_TRANSFERRED: 785251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 786251538Srpaulo if (data == NULL) 787251538Srpaulo goto tr_setup; 788251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 789251538Srpaulo m = urtwn_rxeof(xfer, data, &rssi, &nf); 790251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 791251538Srpaulo /* FALLTHROUGH */ 792251538Srpaulo case USB_ST_SETUP: 793251538Srpaulotr_setup: 794251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_inactive); 795251538Srpaulo if (data == NULL) { 796251538Srpaulo KASSERT(m == NULL, ("mbuf isn't NULL")); 797251538Srpaulo return; 798251538Srpaulo } 799251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 800251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 801251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, 802251538Srpaulo usbd_xfer_max_len(xfer)); 803251538Srpaulo usbd_transfer_submit(xfer); 804251538Srpaulo 805251538Srpaulo /* 806251538Srpaulo * To avoid LOR we should unlock our private mutex here to call 807251538Srpaulo * ieee80211_input() because here is at the end of a USB 808251538Srpaulo * callback and safe to unlock. 809251538Srpaulo */ 810251538Srpaulo URTWN_UNLOCK(sc); 811251538Srpaulo while (m != NULL) { 812251538Srpaulo next = m->m_next; 813251538Srpaulo m->m_next = NULL; 814290022Savos wh = mtod(m, struct ieee80211_frame_min *); 815290022Savos if (m->m_len >= sizeof(*wh)) 816290022Savos ni = ieee80211_find_rxnode(ic, wh); 817290022Savos else 818290022Savos ni = NULL; 819251538Srpaulo nf = URTWN_NOISE_FLOOR; 820251538Srpaulo if (ni != NULL) { 821289799Savos (void)ieee80211_input(ni, m, rssi - nf, nf); 822251538Srpaulo ieee80211_free_node(ni); 823289799Savos } else { 824289799Savos (void)ieee80211_input_all(ic, m, rssi - nf, 825289799Savos nf); 826289799Savos } 827251538Srpaulo m = next; 828251538Srpaulo } 829251538Srpaulo URTWN_LOCK(sc); 830251538Srpaulo break; 831251538Srpaulo default: 832251538Srpaulo /* needs it to the inactive queue due to a error. */ 833251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 834251538Srpaulo if (data != NULL) { 835251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 836251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 837251538Srpaulo } 838251538Srpaulo if (error != USB_ERR_CANCELLED) { 839251538Srpaulo usbd_xfer_set_stall(xfer); 840287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 841251538Srpaulo goto tr_setup; 842251538Srpaulo } 843251538Srpaulo break; 844251538Srpaulo } 845251538Srpaulo} 846251538Srpaulo 847251538Srpaulostatic void 848289891Savosurtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 849251538Srpaulo{ 850251538Srpaulo 851251538Srpaulo URTWN_ASSERT_LOCKED(sc); 852289891Savos 853290631Savos if (data->ni != NULL) /* not a beacon frame */ 854290631Savos ieee80211_tx_complete(data->ni, data->m, status); 855289891Savos 856287197Sglebius data->ni = NULL; 857287197Sglebius data->m = NULL; 858289891Savos 859251538Srpaulo sc->sc_txtimer = 0; 860289891Savos 861289891Savos STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 862251538Srpaulo} 863251538Srpaulo 864289066Skevlostatic int 865289066Skevlourtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 866289066Skevlo int ndata, int maxsz) 867289066Skevlo{ 868289066Skevlo int i, error; 869289066Skevlo 870289066Skevlo for (i = 0; i < ndata; i++) { 871289066Skevlo struct urtwn_data *dp = &data[i]; 872289066Skevlo dp->sc = sc; 873289066Skevlo dp->m = NULL; 874289066Skevlo dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 875289066Skevlo if (dp->buf == NULL) { 876289066Skevlo device_printf(sc->sc_dev, 877289066Skevlo "could not allocate buffer\n"); 878289066Skevlo error = ENOMEM; 879289066Skevlo goto fail; 880289066Skevlo } 881289066Skevlo dp->ni = NULL; 882289066Skevlo } 883289066Skevlo 884289066Skevlo return (0); 885289066Skevlofail: 886289066Skevlo urtwn_free_list(sc, data, ndata); 887289066Skevlo return (error); 888289066Skevlo} 889289066Skevlo 890289066Skevlostatic int 891289066Skevlourtwn_alloc_rx_list(struct urtwn_softc *sc) 892289066Skevlo{ 893289066Skevlo int error, i; 894289066Skevlo 895289066Skevlo error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 896289066Skevlo URTWN_RXBUFSZ); 897289066Skevlo if (error != 0) 898289066Skevlo return (error); 899289066Skevlo 900289066Skevlo STAILQ_INIT(&sc->sc_rx_active); 901289066Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 902289066Skevlo 903289066Skevlo for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 904289066Skevlo STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 905289066Skevlo 906289066Skevlo return (0); 907289066Skevlo} 908289066Skevlo 909289066Skevlostatic int 910289066Skevlourtwn_alloc_tx_list(struct urtwn_softc *sc) 911289066Skevlo{ 912289066Skevlo int error, i; 913289066Skevlo 914289066Skevlo error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 915289066Skevlo URTWN_TXBUFSZ); 916289066Skevlo if (error != 0) 917289066Skevlo return (error); 918289066Skevlo 919289066Skevlo STAILQ_INIT(&sc->sc_tx_active); 920289066Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 921289066Skevlo STAILQ_INIT(&sc->sc_tx_pending); 922289066Skevlo 923289066Skevlo for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 924289066Skevlo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 925289066Skevlo 926289066Skevlo return (0); 927289066Skevlo} 928289066Skevlo 929251538Srpaulostatic void 930289066Skevlourtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 931289066Skevlo{ 932289066Skevlo int i; 933289066Skevlo 934289066Skevlo for (i = 0; i < ndata; i++) { 935289066Skevlo struct urtwn_data *dp = &data[i]; 936289066Skevlo 937289066Skevlo if (dp->buf != NULL) { 938289066Skevlo free(dp->buf, M_USBDEV); 939289066Skevlo dp->buf = NULL; 940289066Skevlo } 941289066Skevlo if (dp->ni != NULL) { 942289066Skevlo ieee80211_free_node(dp->ni); 943289066Skevlo dp->ni = NULL; 944289066Skevlo } 945289066Skevlo } 946289066Skevlo} 947289066Skevlo 948289066Skevlostatic void 949289066Skevlourtwn_free_rx_list(struct urtwn_softc *sc) 950289066Skevlo{ 951289066Skevlo urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 952289066Skevlo} 953289066Skevlo 954289066Skevlostatic void 955289066Skevlourtwn_free_tx_list(struct urtwn_softc *sc) 956289066Skevlo{ 957289066Skevlo urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 958289066Skevlo} 959289066Skevlo 960289066Skevlostatic void 961251538Srpaulourtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 962251538Srpaulo{ 963251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 964251538Srpaulo struct urtwn_data *data; 965251538Srpaulo 966251538Srpaulo URTWN_ASSERT_LOCKED(sc); 967251538Srpaulo 968251538Srpaulo switch (USB_GET_STATE(xfer)){ 969251538Srpaulo case USB_ST_TRANSFERRED: 970251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 971251538Srpaulo if (data == NULL) 972251538Srpaulo goto tr_setup; 973251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 974289891Savos urtwn_txeof(sc, data, 0); 975251538Srpaulo /* FALLTHROUGH */ 976251538Srpaulo case USB_ST_SETUP: 977251538Srpaulotr_setup: 978251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_pending); 979251538Srpaulo if (data == NULL) { 980251538Srpaulo DPRINTF("%s: empty pending queue\n", __func__); 981288353Sadrian goto finish; 982251538Srpaulo } 983251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 984251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 985251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 986251538Srpaulo usbd_transfer_submit(xfer); 987251538Srpaulo break; 988251538Srpaulo default: 989251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 990251538Srpaulo if (data == NULL) 991251538Srpaulo goto tr_setup; 992289891Savos STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 993289891Savos urtwn_txeof(sc, data, 1); 994251538Srpaulo if (error != USB_ERR_CANCELLED) { 995251538Srpaulo usbd_xfer_set_stall(xfer); 996251538Srpaulo goto tr_setup; 997251538Srpaulo } 998251538Srpaulo break; 999251538Srpaulo } 1000288353Sadrianfinish: 1001288353Sadrian /* Kick-start more transmit */ 1002288353Sadrian urtwn_start(sc); 1003251538Srpaulo} 1004251538Srpaulo 1005251538Srpaulostatic struct urtwn_data * 1006251538Srpaulo_urtwn_getbuf(struct urtwn_softc *sc) 1007251538Srpaulo{ 1008251538Srpaulo struct urtwn_data *bf; 1009251538Srpaulo 1010251538Srpaulo bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1011251538Srpaulo if (bf != NULL) 1012251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1013251538Srpaulo else 1014251538Srpaulo DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 1015251538Srpaulo return (bf); 1016251538Srpaulo} 1017251538Srpaulo 1018251538Srpaulostatic struct urtwn_data * 1019251538Srpaulourtwn_getbuf(struct urtwn_softc *sc) 1020251538Srpaulo{ 1021251538Srpaulo struct urtwn_data *bf; 1022251538Srpaulo 1023251538Srpaulo URTWN_ASSERT_LOCKED(sc); 1024251538Srpaulo 1025251538Srpaulo bf = _urtwn_getbuf(sc); 1026287197Sglebius if (bf == NULL) 1027251538Srpaulo DPRINTF("%s: stop queue\n", __func__); 1028251538Srpaulo return (bf); 1029251538Srpaulo} 1030251538Srpaulo 1031251538Srpaulostatic int 1032251538Srpaulourtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1033251538Srpaulo int len) 1034251538Srpaulo{ 1035251538Srpaulo usb_device_request_t req; 1036251538Srpaulo 1037251538Srpaulo req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1038251538Srpaulo req.bRequest = R92C_REQ_REGS; 1039251538Srpaulo USETW(req.wValue, addr); 1040251538Srpaulo USETW(req.wIndex, 0); 1041251538Srpaulo USETW(req.wLength, len); 1042251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 1043251538Srpaulo} 1044251538Srpaulo 1045251538Srpaulostatic void 1046251538Srpaulourtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1047251538Srpaulo{ 1048251538Srpaulo urtwn_write_region_1(sc, addr, &val, 1); 1049251538Srpaulo} 1050251538Srpaulo 1051251538Srpaulo 1052251538Srpaulostatic void 1053251538Srpaulourtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1054251538Srpaulo{ 1055251538Srpaulo val = htole16(val); 1056251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1057251538Srpaulo} 1058251538Srpaulo 1059251538Srpaulostatic void 1060251538Srpaulourtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1061251538Srpaulo{ 1062251538Srpaulo val = htole32(val); 1063251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1064251538Srpaulo} 1065251538Srpaulo 1066251538Srpaulostatic int 1067251538Srpaulourtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1068251538Srpaulo int len) 1069251538Srpaulo{ 1070251538Srpaulo usb_device_request_t req; 1071251538Srpaulo 1072251538Srpaulo req.bmRequestType = UT_READ_VENDOR_DEVICE; 1073251538Srpaulo req.bRequest = R92C_REQ_REGS; 1074251538Srpaulo USETW(req.wValue, addr); 1075251538Srpaulo USETW(req.wIndex, 0); 1076251538Srpaulo USETW(req.wLength, len); 1077251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 1078251538Srpaulo} 1079251538Srpaulo 1080251538Srpaulostatic uint8_t 1081251538Srpaulourtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1082251538Srpaulo{ 1083251538Srpaulo uint8_t val; 1084251538Srpaulo 1085251538Srpaulo if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1086251538Srpaulo return (0xff); 1087251538Srpaulo return (val); 1088251538Srpaulo} 1089251538Srpaulo 1090251538Srpaulostatic uint16_t 1091251538Srpaulourtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1092251538Srpaulo{ 1093251538Srpaulo uint16_t val; 1094251538Srpaulo 1095251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1096251538Srpaulo return (0xffff); 1097251538Srpaulo return (le16toh(val)); 1098251538Srpaulo} 1099251538Srpaulo 1100251538Srpaulostatic uint32_t 1101251538Srpaulourtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1102251538Srpaulo{ 1103251538Srpaulo uint32_t val; 1104251538Srpaulo 1105251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1106251538Srpaulo return (0xffffffff); 1107251538Srpaulo return (le32toh(val)); 1108251538Srpaulo} 1109251538Srpaulo 1110251538Srpaulostatic int 1111251538Srpaulourtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1112251538Srpaulo{ 1113251538Srpaulo struct r92c_fw_cmd cmd; 1114251538Srpaulo int ntries; 1115251538Srpaulo 1116251538Srpaulo /* Wait for current FW box to be empty. */ 1117251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1118251538Srpaulo if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1119251538Srpaulo break; 1120266472Shselasky urtwn_ms_delay(sc); 1121251538Srpaulo } 1122251538Srpaulo if (ntries == 100) { 1123251538Srpaulo device_printf(sc->sc_dev, 1124251538Srpaulo "could not send firmware command\n"); 1125251538Srpaulo return (ETIMEDOUT); 1126251538Srpaulo } 1127251538Srpaulo memset(&cmd, 0, sizeof(cmd)); 1128251538Srpaulo cmd.id = id; 1129251538Srpaulo if (len > 3) 1130251538Srpaulo cmd.id |= R92C_CMD_FLAG_EXT; 1131251538Srpaulo KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1132251538Srpaulo memcpy(cmd.msg, buf, len); 1133251538Srpaulo 1134251538Srpaulo /* Write the first word last since that will trigger the FW. */ 1135251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1136251538Srpaulo (uint8_t *)&cmd + 4, 2); 1137251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1138251538Srpaulo (uint8_t *)&cmd + 0, 4); 1139251538Srpaulo 1140251538Srpaulo sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1141251538Srpaulo return (0); 1142251538Srpaulo} 1143251538Srpaulo 1144264912Skevlostatic __inline void 1145251538Srpaulourtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1146251538Srpaulo{ 1147264912Skevlo 1148264912Skevlo sc->sc_rf_write(sc, chain, addr, val); 1149264912Skevlo} 1150264912Skevlo 1151264912Skevlostatic void 1152264912Skevlourtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1153264912Skevlo uint32_t val) 1154264912Skevlo{ 1155251538Srpaulo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1156251538Srpaulo SM(R92C_LSSI_PARAM_ADDR, addr) | 1157251538Srpaulo SM(R92C_LSSI_PARAM_DATA, val)); 1158251538Srpaulo} 1159251538Srpaulo 1160264912Skevlostatic void 1161264912Skevlourtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1162264912Skevlouint32_t val) 1163264912Skevlo{ 1164264912Skevlo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1165264912Skevlo SM(R88E_LSSI_PARAM_ADDR, addr) | 1166264912Skevlo SM(R92C_LSSI_PARAM_DATA, val)); 1167264912Skevlo} 1168264912Skevlo 1169251538Srpaulostatic uint32_t 1170251538Srpaulourtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1171251538Srpaulo{ 1172251538Srpaulo uint32_t reg[R92C_MAX_CHAINS], val; 1173251538Srpaulo 1174251538Srpaulo reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1175251538Srpaulo if (chain != 0) 1176251538Srpaulo reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1177251538Srpaulo 1178251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1179251538Srpaulo reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1180266472Shselasky urtwn_ms_delay(sc); 1181251538Srpaulo 1182251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1183251538Srpaulo RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1184251538Srpaulo R92C_HSSI_PARAM2_READ_EDGE); 1185266472Shselasky urtwn_ms_delay(sc); 1186251538Srpaulo 1187251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1188251538Srpaulo reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1189266472Shselasky urtwn_ms_delay(sc); 1190251538Srpaulo 1191251538Srpaulo if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1192251538Srpaulo val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1193251538Srpaulo else 1194251538Srpaulo val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1195251538Srpaulo return (MS(val, R92C_LSSI_READBACK_DATA)); 1196251538Srpaulo} 1197251538Srpaulo 1198251538Srpaulostatic int 1199251538Srpaulourtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1200251538Srpaulo{ 1201251538Srpaulo int ntries; 1202251538Srpaulo 1203251538Srpaulo urtwn_write_4(sc, R92C_LLT_INIT, 1204251538Srpaulo SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1205251538Srpaulo SM(R92C_LLT_INIT_ADDR, addr) | 1206251538Srpaulo SM(R92C_LLT_INIT_DATA, data)); 1207251538Srpaulo /* Wait for write operation to complete. */ 1208251538Srpaulo for (ntries = 0; ntries < 20; ntries++) { 1209251538Srpaulo if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1210251538Srpaulo R92C_LLT_INIT_OP_NO_ACTIVE) 1211251538Srpaulo return (0); 1212266472Shselasky urtwn_ms_delay(sc); 1213251538Srpaulo } 1214251538Srpaulo return (ETIMEDOUT); 1215251538Srpaulo} 1216251538Srpaulo 1217251538Srpaulostatic uint8_t 1218251538Srpaulourtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1219251538Srpaulo{ 1220251538Srpaulo uint32_t reg; 1221251538Srpaulo int ntries; 1222251538Srpaulo 1223251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1224251538Srpaulo reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1225251538Srpaulo reg &= ~R92C_EFUSE_CTRL_VALID; 1226251538Srpaulo urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1227251538Srpaulo /* Wait for read operation to complete. */ 1228251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1229251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1230251538Srpaulo if (reg & R92C_EFUSE_CTRL_VALID) 1231251538Srpaulo return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1232266472Shselasky urtwn_ms_delay(sc); 1233251538Srpaulo } 1234281069Srpaulo device_printf(sc->sc_dev, 1235251538Srpaulo "could not read efuse byte at address 0x%x\n", addr); 1236251538Srpaulo return (0xff); 1237251538Srpaulo} 1238251538Srpaulo 1239251538Srpaulostatic void 1240251538Srpaulourtwn_efuse_read(struct urtwn_softc *sc) 1241251538Srpaulo{ 1242251538Srpaulo uint8_t *rom = (uint8_t *)&sc->rom; 1243251538Srpaulo uint16_t addr = 0; 1244251538Srpaulo uint32_t reg; 1245282623Skevlo uint8_t off, msk; 1246251538Srpaulo int i; 1247251538Srpaulo 1248264912Skevlo urtwn_efuse_switch_power(sc); 1249264912Skevlo 1250251538Srpaulo memset(&sc->rom, 0xff, sizeof(sc->rom)); 1251251538Srpaulo while (addr < 512) { 1252251538Srpaulo reg = urtwn_efuse_read_1(sc, addr); 1253251538Srpaulo if (reg == 0xff) 1254251538Srpaulo break; 1255251538Srpaulo addr++; 1256251538Srpaulo off = reg >> 4; 1257251538Srpaulo msk = reg & 0xf; 1258251538Srpaulo for (i = 0; i < 4; i++) { 1259251538Srpaulo if (msk & (1 << i)) 1260251538Srpaulo continue; 1261251538Srpaulo rom[off * 8 + i * 2 + 0] = 1262251538Srpaulo urtwn_efuse_read_1(sc, addr); 1263251538Srpaulo addr++; 1264251538Srpaulo rom[off * 8 + i * 2 + 1] = 1265251538Srpaulo urtwn_efuse_read_1(sc, addr); 1266251538Srpaulo addr++; 1267251538Srpaulo } 1268251538Srpaulo } 1269251538Srpaulo#ifdef URTWN_DEBUG 1270251538Srpaulo if (urtwn_debug >= 2) { 1271251538Srpaulo /* Dump ROM content. */ 1272251538Srpaulo printf("\n"); 1273251538Srpaulo for (i = 0; i < sizeof(sc->rom); i++) 1274251538Srpaulo printf("%02x:", rom[i]); 1275251538Srpaulo printf("\n"); 1276251538Srpaulo } 1277251538Srpaulo#endif 1278282623Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1279282623Skevlo} 1280281592Skevlo 1281264912Skevlostatic void 1282264912Skevlourtwn_efuse_switch_power(struct urtwn_softc *sc) 1283264912Skevlo{ 1284264912Skevlo uint32_t reg; 1285251538Srpaulo 1286282623Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1287281918Skevlo 1288264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1289264912Skevlo if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1290264912Skevlo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1291264912Skevlo reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1292264912Skevlo } 1293264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1294264912Skevlo if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1295264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1296264912Skevlo reg | R92C_SYS_FUNC_EN_ELDR); 1297264912Skevlo } 1298264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1299264912Skevlo if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1300264912Skevlo (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1301264912Skevlo urtwn_write_2(sc, R92C_SYS_CLKR, 1302264912Skevlo reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1303264912Skevlo } 1304264912Skevlo} 1305264912Skevlo 1306251538Srpaulostatic int 1307251538Srpaulourtwn_read_chipid(struct urtwn_softc *sc) 1308251538Srpaulo{ 1309251538Srpaulo uint32_t reg; 1310251538Srpaulo 1311264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1312264912Skevlo return (0); 1313264912Skevlo 1314251538Srpaulo reg = urtwn_read_4(sc, R92C_SYS_CFG); 1315251538Srpaulo if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1316251538Srpaulo return (EIO); 1317251538Srpaulo 1318251538Srpaulo if (reg & R92C_SYS_CFG_TYPE_92C) { 1319251538Srpaulo sc->chip |= URTWN_CHIP_92C; 1320251538Srpaulo /* Check if it is a castrated 8192C. */ 1321251538Srpaulo if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1322251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID) == 1323251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1324251538Srpaulo sc->chip |= URTWN_CHIP_92C_1T2R; 1325251538Srpaulo } 1326251538Srpaulo if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1327251538Srpaulo sc->chip |= URTWN_CHIP_UMC; 1328251538Srpaulo if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1329251538Srpaulo sc->chip |= URTWN_CHIP_UMC_A_CUT; 1330251538Srpaulo } 1331251538Srpaulo return (0); 1332251538Srpaulo} 1333251538Srpaulo 1334251538Srpaulostatic void 1335251538Srpaulourtwn_read_rom(struct urtwn_softc *sc) 1336251538Srpaulo{ 1337251538Srpaulo struct r92c_rom *rom = &sc->rom; 1338251538Srpaulo 1339251538Srpaulo /* Read full ROM image. */ 1340251538Srpaulo urtwn_efuse_read(sc); 1341251538Srpaulo 1342251538Srpaulo /* XXX Weird but this is what the vendor driver does. */ 1343251538Srpaulo sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1344251538Srpaulo DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1345251538Srpaulo 1346251538Srpaulo sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1347251538Srpaulo 1348251538Srpaulo sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1349251538Srpaulo DPRINTF("regulatory type=%d\n", sc->regulatory); 1350287197Sglebius IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1351251538Srpaulo 1352264912Skevlo sc->sc_rf_write = urtwn_r92c_rf_write; 1353264912Skevlo sc->sc_power_on = urtwn_r92c_power_on; 1354264912Skevlo sc->sc_dma_init = urtwn_r92c_dma_init; 1355251538Srpaulo} 1356251538Srpaulo 1357264912Skevlostatic void 1358264912Skevlourtwn_r88e_read_rom(struct urtwn_softc *sc) 1359264912Skevlo{ 1360264912Skevlo uint8_t *rom = sc->r88e_rom; 1361264912Skevlo uint16_t addr = 0; 1362264912Skevlo uint32_t reg; 1363264912Skevlo uint8_t off, msk, tmp; 1364264912Skevlo int i; 1365264912Skevlo 1366264982Sandreast off = 0; 1367264912Skevlo urtwn_efuse_switch_power(sc); 1368264912Skevlo 1369264912Skevlo /* Read full ROM image. */ 1370264912Skevlo memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1371281918Skevlo while (addr < 512) { 1372264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1373264912Skevlo if (reg == 0xff) 1374264912Skevlo break; 1375264912Skevlo addr++; 1376264912Skevlo if ((reg & 0x1f) == 0x0f) { 1377264912Skevlo tmp = (reg & 0xe0) >> 5; 1378264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1379264912Skevlo if ((reg & 0x0f) != 0x0f) 1380264912Skevlo off = ((reg & 0xf0) >> 1) | tmp; 1381264912Skevlo addr++; 1382264912Skevlo } else 1383264912Skevlo off = reg >> 4; 1384264912Skevlo msk = reg & 0xf; 1385264912Skevlo for (i = 0; i < 4; i++) { 1386264912Skevlo if (msk & (1 << i)) 1387264912Skevlo continue; 1388264912Skevlo rom[off * 8 + i * 2 + 0] = 1389264912Skevlo urtwn_efuse_read_1(sc, addr); 1390264912Skevlo addr++; 1391264912Skevlo rom[off * 8 + i * 2 + 1] = 1392264912Skevlo urtwn_efuse_read_1(sc, addr); 1393264912Skevlo addr++; 1394264912Skevlo } 1395264912Skevlo } 1396264912Skevlo 1397281918Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1398281918Skevlo 1399264912Skevlo addr = 0x10; 1400264912Skevlo for (i = 0; i < 6; i++) 1401264912Skevlo sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1402264912Skevlo for (i = 0; i < 5; i++) 1403264912Skevlo sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1404264912Skevlo sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1405264912Skevlo if (sc->bw20_tx_pwr_diff & 0x08) 1406264912Skevlo sc->bw20_tx_pwr_diff |= 0xf0; 1407264912Skevlo sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1408264912Skevlo if (sc->ofdm_tx_pwr_diff & 0x08) 1409264912Skevlo sc->ofdm_tx_pwr_diff |= 0xf0; 1410264912Skevlo sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1411287197Sglebius IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &sc->r88e_rom[0xd7]); 1412264912Skevlo 1413264912Skevlo sc->sc_rf_write = urtwn_r88e_rf_write; 1414264912Skevlo sc->sc_power_on = urtwn_r88e_power_on; 1415264912Skevlo sc->sc_dma_init = urtwn_r88e_dma_init; 1416264912Skevlo} 1417264912Skevlo 1418251538Srpaulo/* 1419251538Srpaulo * Initialize rate adaptation in firmware. 1420251538Srpaulo */ 1421251538Srpaulostatic int 1422251538Srpaulourtwn_ra_init(struct urtwn_softc *sc) 1423251538Srpaulo{ 1424287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1425251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1426251538Srpaulo struct ieee80211_node *ni; 1427251538Srpaulo struct ieee80211_rateset *rs; 1428251538Srpaulo struct r92c_fw_cmd_macid_cfg cmd; 1429251538Srpaulo uint32_t rates, basicrates; 1430251538Srpaulo uint8_t mode; 1431251538Srpaulo int maxrate, maxbasicrate, error, i, j; 1432251538Srpaulo 1433251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1434251538Srpaulo rs = &ni->ni_rates; 1435251538Srpaulo 1436251538Srpaulo /* Get normal and basic rates mask. */ 1437251538Srpaulo rates = basicrates = 0; 1438251538Srpaulo maxrate = maxbasicrate = 0; 1439251538Srpaulo for (i = 0; i < rs->rs_nrates; i++) { 1440251538Srpaulo /* Convert 802.11 rate to HW rate index. */ 1441289758Savos for (j = 0; j < nitems(ridx2rate); j++) 1442289758Savos if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1443289758Savos ridx2rate[j]) 1444251538Srpaulo break; 1445289758Savos if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1446251538Srpaulo continue; 1447251538Srpaulo rates |= 1 << j; 1448251538Srpaulo if (j > maxrate) 1449251538Srpaulo maxrate = j; 1450251538Srpaulo if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1451251538Srpaulo basicrates |= 1 << j; 1452251538Srpaulo if (j > maxbasicrate) 1453251538Srpaulo maxbasicrate = j; 1454251538Srpaulo } 1455251538Srpaulo } 1456251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1457251538Srpaulo mode = R92C_RAID_11B; 1458251538Srpaulo else 1459251538Srpaulo mode = R92C_RAID_11BG; 1460251538Srpaulo DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1461251538Srpaulo mode, rates, basicrates); 1462251538Srpaulo 1463251538Srpaulo /* Set rates mask for group addressed frames. */ 1464251538Srpaulo cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1465251538Srpaulo cmd.mask = htole32(mode << 28 | basicrates); 1466251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1467251538Srpaulo if (error != 0) { 1468252401Srpaulo ieee80211_free_node(ni); 1469251538Srpaulo device_printf(sc->sc_dev, 1470251538Srpaulo "could not add broadcast station\n"); 1471251538Srpaulo return (error); 1472251538Srpaulo } 1473251538Srpaulo /* Set initial MRR rate. */ 1474251538Srpaulo DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1475251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1476251538Srpaulo maxbasicrate); 1477251538Srpaulo 1478251538Srpaulo /* Set rates mask for unicast frames. */ 1479251538Srpaulo cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1480251538Srpaulo cmd.mask = htole32(mode << 28 | rates); 1481251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1482251538Srpaulo if (error != 0) { 1483252401Srpaulo ieee80211_free_node(ni); 1484251538Srpaulo device_printf(sc->sc_dev, "could not add BSS station\n"); 1485251538Srpaulo return (error); 1486251538Srpaulo } 1487251538Srpaulo /* Set initial MRR rate. */ 1488251538Srpaulo DPRINTF("maxrate=%d\n", maxrate); 1489251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1490251538Srpaulo maxrate); 1491251538Srpaulo 1492251538Srpaulo /* Indicate highest supported rate. */ 1493252403Srpaulo ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1494252401Srpaulo ieee80211_free_node(ni); 1495252401Srpaulo 1496251538Srpaulo return (0); 1497251538Srpaulo} 1498251538Srpaulo 1499290439Savosstatic void 1500290631Savosurtwn_init_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1501251538Srpaulo{ 1502290631Savos struct r92c_tx_desc *txd = &uvp->bcn_desc; 1503290631Savos 1504290631Savos txd->txdw0 = htole32( 1505290631Savos SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | R92C_TXDW0_BMCAST | 1506290631Savos R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1507290631Savos txd->txdw1 = htole32( 1508290631Savos SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BEACON) | 1509290631Savos SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1510290631Savos 1511290631Savos if (sc->chip & URTWN_CHIP_88E) 1512290631Savos txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, URTWN_MACID_BC)); 1513290631Savos else 1514290631Savos txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, URTWN_MACID_BC)); 1515290631Savos 1516290631Savos txd->txdw4 = htole32(R92C_TXDW4_DRVRATE); 1517290631Savos txd->txdw5 = htole32(SM(R92C_TXDW5_DATARATE, URTWN_RIDX_CCK1)); 1518290631Savos txd->txdseq = htole16(R92C_TXDSEQ_HWSEQ_EN); 1519251538Srpaulo} 1520251538Srpaulo 1521290631Savosstatic int 1522290631Savosurtwn_setup_beacon(struct urtwn_softc *sc, struct ieee80211_node *ni) 1523290631Savos{ 1524290631Savos struct ieee80211vap *vap = ni->ni_vap; 1525290631Savos struct urtwn_vap *uvp = URTWN_VAP(vap); 1526290631Savos struct mbuf *m; 1527290631Savos int error; 1528290631Savos 1529290631Savos URTWN_ASSERT_LOCKED(sc); 1530290631Savos 1531290631Savos if (ni->ni_chan == IEEE80211_CHAN_ANYC) 1532290631Savos return (EINVAL); 1533290631Savos 1534290631Savos m = ieee80211_beacon_alloc(ni); 1535290631Savos if (m == NULL) { 1536290631Savos device_printf(sc->sc_dev, 1537290631Savos "%s: could not allocate beacon frame\n", __func__); 1538290631Savos return (ENOMEM); 1539290631Savos } 1540290631Savos 1541290631Savos if (uvp->bcn_mbuf != NULL) 1542290631Savos m_freem(uvp->bcn_mbuf); 1543290631Savos 1544290631Savos uvp->bcn_mbuf = m; 1545290631Savos 1546290631Savos if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1547290631Savos return (error); 1548290631Savos 1549290631Savos /* XXX bcnq stuck workaround */ 1550290631Savos if ((error = urtwn_tx_beacon(sc, uvp)) != 0) 1551290631Savos return (error); 1552290631Savos 1553290631Savos return (0); 1554290631Savos} 1555290631Savos 1556251538Srpaulostatic void 1557290631Savosurtwn_update_beacon(struct ieee80211vap *vap, int item) 1558290631Savos{ 1559290631Savos struct urtwn_softc *sc = vap->iv_ic->ic_softc; 1560290631Savos struct urtwn_vap *uvp = URTWN_VAP(vap); 1561290631Savos struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 1562290631Savos struct ieee80211_node *ni = vap->iv_bss; 1563290631Savos int mcast = 0; 1564290631Savos 1565290631Savos URTWN_LOCK(sc); 1566290631Savos if (uvp->bcn_mbuf == NULL) { 1567290631Savos uvp->bcn_mbuf = ieee80211_beacon_alloc(ni); 1568290631Savos if (uvp->bcn_mbuf == NULL) { 1569290631Savos device_printf(sc->sc_dev, 1570290631Savos "%s: could not allocate beacon frame\n", __func__); 1571290631Savos URTWN_UNLOCK(sc); 1572290631Savos return; 1573290631Savos } 1574290631Savos } 1575290631Savos URTWN_UNLOCK(sc); 1576290631Savos 1577290631Savos if (item == IEEE80211_BEACON_TIM) 1578290631Savos mcast = 1; /* XXX */ 1579290631Savos 1580290631Savos setbit(bo->bo_flags, item); 1581290631Savos ieee80211_beacon_update(ni, uvp->bcn_mbuf, mcast); 1582290631Savos 1583290631Savos URTWN_LOCK(sc); 1584290631Savos urtwn_tx_beacon(sc, uvp); 1585290631Savos URTWN_UNLOCK(sc); 1586290631Savos} 1587290631Savos 1588290631Savos/* 1589290631Savos * Push a beacon frame into the chip. Beacon will 1590290631Savos * be repeated by the chip every R92C_BCN_INTERVAL. 1591290631Savos */ 1592290631Savosstatic int 1593290631Savosurtwn_tx_beacon(struct urtwn_softc *sc, struct urtwn_vap *uvp) 1594290631Savos{ 1595290631Savos struct r92c_tx_desc *desc = &uvp->bcn_desc; 1596290631Savos struct urtwn_data *bf; 1597290631Savos 1598290631Savos URTWN_ASSERT_LOCKED(sc); 1599290631Savos 1600290631Savos bf = urtwn_getbuf(sc); 1601290631Savos if (bf == NULL) 1602290631Savos return (ENOMEM); 1603290631Savos 1604290631Savos memcpy(bf->buf, desc, sizeof(*desc)); 1605290631Savos urtwn_tx_start(sc, uvp->bcn_mbuf, IEEE80211_FC0_TYPE_MGT, bf); 1606290631Savos 1607290631Savos sc->sc_txtimer = 5; 1608290631Savos callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1609290631Savos 1610290631Savos return (0); 1611290631Savos} 1612290631Savos 1613290631Savosstatic void 1614290631Savosurtwn_tsf_sync_enable(struct urtwn_softc *sc, struct ieee80211vap *vap) 1615290631Savos{ 1616290631Savos /* Reset TSF. */ 1617290631Savos urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 1618290631Savos 1619290631Savos switch (vap->iv_opmode) { 1620290631Savos case IEEE80211_M_STA: 1621290631Savos /* Enable TSF synchronization. */ 1622290631Savos urtwn_write_1(sc, R92C_BCN_CTRL, 1623290631Savos urtwn_read_1(sc, R92C_BCN_CTRL) & 1624290631Savos ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1625290631Savos break; 1626290631Savos case IEEE80211_M_HOSTAP: 1627290631Savos /* Enable beaconing. */ 1628290631Savos urtwn_write_1(sc, R92C_MBID_NUM, 1629290631Savos urtwn_read_1(sc, R92C_MBID_NUM) | R92C_MBID_TXBCN_RPT0); 1630290631Savos urtwn_write_1(sc, R92C_BCN_CTRL, 1631290631Savos urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1632290631Savos break; 1633290631Savos default: 1634290631Savos device_printf(sc->sc_dev, "undefined opmode %d\n", 1635290631Savos vap->iv_opmode); 1636290631Savos return; 1637290631Savos } 1638290631Savos} 1639290631Savos 1640290631Savosstatic void 1641251538Srpaulourtwn_set_led(struct urtwn_softc *sc, int led, int on) 1642251538Srpaulo{ 1643251538Srpaulo uint8_t reg; 1644281069Srpaulo 1645251538Srpaulo if (led == URTWN_LED_LINK) { 1646264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 1647264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1648264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1649264912Skevlo if (!on) { 1650264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1651264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, 1652264912Skevlo reg | R92C_LEDCFG0_DIS); 1653264912Skevlo urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1654264912Skevlo urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1655264912Skevlo 0xfe); 1656264912Skevlo } 1657264912Skevlo } else { 1658264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1659264912Skevlo if (!on) 1660264912Skevlo reg |= R92C_LEDCFG0_DIS; 1661264912Skevlo urtwn_write_1(sc, R92C_LEDCFG0, reg); 1662264912Skevlo } 1663264912Skevlo sc->ledlink = on; /* Save LED state. */ 1664251538Srpaulo } 1665251538Srpaulo} 1666251538Srpaulo 1667289811Savosstatic void 1668289811Savosurtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 1669289811Savos{ 1670289811Savos uint8_t reg; 1671289811Savos 1672289811Savos reg = urtwn_read_1(sc, R92C_MSR); 1673289811Savos reg = (reg & ~R92C_MSR_MASK) | mode; 1674289811Savos urtwn_write_1(sc, R92C_MSR, reg); 1675289811Savos} 1676289811Savos 1677251538Srpaulostatic int 1678251538Srpaulourtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1679251538Srpaulo{ 1680251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 1681251538Srpaulo struct ieee80211com *ic = vap->iv_ic; 1682286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 1683251538Srpaulo struct ieee80211_node *ni; 1684251538Srpaulo enum ieee80211_state ostate; 1685290631Savos uint32_t reg; 1686290631Savos uint8_t mode; 1687290631Savos int error = 0; 1688251538Srpaulo 1689251538Srpaulo ostate = vap->iv_state; 1690251538Srpaulo DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1691251538Srpaulo ieee80211_state_name[nstate]); 1692251538Srpaulo 1693251538Srpaulo IEEE80211_UNLOCK(ic); 1694251538Srpaulo URTWN_LOCK(sc); 1695251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 1696251538Srpaulo 1697251538Srpaulo if (ostate == IEEE80211_S_RUN) { 1698251538Srpaulo /* Turn link LED off. */ 1699251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1700251538Srpaulo 1701251538Srpaulo /* Set media status to 'No Link'. */ 1702289811Savos urtwn_set_mode(sc, R92C_MSR_NOLINK); 1703251538Srpaulo 1704251538Srpaulo /* Stop Rx of data frames. */ 1705251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1706251538Srpaulo 1707251538Srpaulo /* Disable TSF synchronization. */ 1708251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1709290631Savos (urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN) | 1710251538Srpaulo R92C_BCN_CTRL_DIS_TSF_UDT0); 1711251538Srpaulo 1712290631Savos /* Disable beaconing. */ 1713290631Savos urtwn_write_1(sc, R92C_MBID_NUM, 1714290631Savos urtwn_read_1(sc, R92C_MBID_NUM) & ~R92C_MBID_TXBCN_RPT0); 1715290631Savos 1716290631Savos /* Reset TSF. */ 1717290631Savos urtwn_write_1(sc, R92C_DUAL_TSF_RST, R92C_DUAL_TSF_RST0); 1718290631Savos 1719251538Srpaulo /* Reset EDCA parameters. */ 1720251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1721251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1722251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1723251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1724251538Srpaulo } 1725251538Srpaulo 1726251538Srpaulo switch (nstate) { 1727251538Srpaulo case IEEE80211_S_INIT: 1728251538Srpaulo /* Turn link LED off. */ 1729251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1730251538Srpaulo break; 1731251538Srpaulo case IEEE80211_S_SCAN: 1732251538Srpaulo /* Pause AC Tx queues. */ 1733251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 1734251538Srpaulo urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1735251538Srpaulo break; 1736251538Srpaulo case IEEE80211_S_AUTH: 1737251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 1738251538Srpaulo break; 1739251538Srpaulo case IEEE80211_S_RUN: 1740251538Srpaulo if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1741251538Srpaulo /* Turn link LED on. */ 1742251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1743251538Srpaulo break; 1744251538Srpaulo } 1745251538Srpaulo 1746251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1747290631Savos 1748290631Savos if (ic->ic_bsschan == IEEE80211_CHAN_ANYC || 1749290631Savos ni->ni_chan == IEEE80211_CHAN_ANYC) { 1750290631Savos device_printf(sc->sc_dev, 1751290631Savos "%s: could not move to RUN state\n", __func__); 1752290631Savos error = EINVAL; 1753290631Savos goto end_run; 1754290631Savos } 1755290631Savos 1756290631Savos switch (vap->iv_opmode) { 1757290631Savos case IEEE80211_M_STA: 1758290631Savos mode = R92C_MSR_INFRA; 1759290631Savos break; 1760290631Savos case IEEE80211_M_HOSTAP: 1761290631Savos mode = R92C_MSR_AP; 1762290631Savos break; 1763290631Savos default: 1764290631Savos device_printf(sc->sc_dev, "undefined opmode %d\n", 1765290631Savos vap->iv_opmode); 1766290631Savos error = EINVAL; 1767290631Savos goto end_run; 1768290631Savos } 1769290631Savos 1770251538Srpaulo /* Set media status to 'Associated'. */ 1771290631Savos urtwn_set_mode(sc, mode); 1772251538Srpaulo 1773251538Srpaulo /* Set BSSID. */ 1774251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1775251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1776251538Srpaulo 1777251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1778251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1779251538Srpaulo else /* 802.11b/g */ 1780251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1781251538Srpaulo 1782251538Srpaulo /* Enable Rx of data frames. */ 1783251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1784251538Srpaulo 1785251538Srpaulo /* Flush all AC queues. */ 1786251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0); 1787251538Srpaulo 1788251538Srpaulo /* Set beacon interval. */ 1789251538Srpaulo urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1790251538Srpaulo 1791251538Srpaulo /* Allow Rx from our BSSID only. */ 1792290564Savos if (ic->ic_promisc == 0) { 1793290631Savos reg = urtwn_read_4(sc, R92C_RCR); 1794290631Savos 1795290631Savos if (vap->iv_opmode != IEEE80211_M_HOSTAP) 1796290631Savos reg |= R92C_RCR_CBSSID_DATA; 1797290631Savos 1798290631Savos reg |= R92C_RCR_CBSSID_BCN; 1799290631Savos 1800290631Savos urtwn_write_4(sc, R92C_RCR, reg); 1801290564Savos } 1802251538Srpaulo 1803290631Savos if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 1804290631Savos error = urtwn_setup_beacon(sc, ni); 1805290631Savos if (error != 0) { 1806290631Savos device_printf(sc->sc_dev, 1807290631Savos "unable to push beacon into the chip, " 1808290631Savos "error %d\n", error); 1809290631Savos goto end_run; 1810290631Savos } 1811290631Savos } 1812290631Savos 1813251538Srpaulo /* Enable TSF synchronization. */ 1814290631Savos urtwn_tsf_sync_enable(sc, vap); 1815251538Srpaulo 1816251538Srpaulo urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1817251538Srpaulo urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1818251538Srpaulo urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1819251538Srpaulo urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1820251538Srpaulo urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1821251538Srpaulo urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1822251538Srpaulo 1823251538Srpaulo /* Intialize rate adaptation. */ 1824264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1825264912Skevlo ni->ni_txrate = 1826264912Skevlo ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1827281069Srpaulo else 1828264912Skevlo urtwn_ra_init(sc); 1829251538Srpaulo /* Turn link LED on. */ 1830251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1831251538Srpaulo 1832251538Srpaulo sc->avg_pwdb = -1; /* Reset average RSSI. */ 1833251538Srpaulo /* Reset temperature calibration state machine. */ 1834251538Srpaulo sc->thcal_state = 0; 1835251538Srpaulo sc->thcal_lctemp = 0; 1836290631Savos 1837290631Savosend_run: 1838251538Srpaulo ieee80211_free_node(ni); 1839251538Srpaulo break; 1840251538Srpaulo default: 1841251538Srpaulo break; 1842251538Srpaulo } 1843290631Savos 1844251538Srpaulo URTWN_UNLOCK(sc); 1845251538Srpaulo IEEE80211_LOCK(ic); 1846290631Savos return (error != 0 ? error : uvp->newstate(vap, nstate, arg)); 1847251538Srpaulo} 1848251538Srpaulo 1849251538Srpaulostatic void 1850251538Srpaulourtwn_watchdog(void *arg) 1851251538Srpaulo{ 1852251538Srpaulo struct urtwn_softc *sc = arg; 1853251538Srpaulo 1854251538Srpaulo if (sc->sc_txtimer > 0) { 1855251538Srpaulo if (--sc->sc_txtimer == 0) { 1856251538Srpaulo device_printf(sc->sc_dev, "device timeout\n"); 1857287197Sglebius counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1858251538Srpaulo return; 1859251538Srpaulo } 1860251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1861251538Srpaulo } 1862251538Srpaulo} 1863251538Srpaulo 1864251538Srpaulostatic void 1865251538Srpaulourtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1866251538Srpaulo{ 1867251538Srpaulo int pwdb; 1868251538Srpaulo 1869251538Srpaulo /* Convert antenna signal to percentage. */ 1870251538Srpaulo if (rssi <= -100 || rssi >= 20) 1871251538Srpaulo pwdb = 0; 1872251538Srpaulo else if (rssi >= 0) 1873251538Srpaulo pwdb = 100; 1874251538Srpaulo else 1875251538Srpaulo pwdb = 100 + rssi; 1876264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1877289758Savos if (rate <= URTWN_RIDX_CCK11) { 1878264912Skevlo /* CCK gain is smaller than OFDM/MCS gain. */ 1879264912Skevlo pwdb += 6; 1880264912Skevlo if (pwdb > 100) 1881264912Skevlo pwdb = 100; 1882264912Skevlo if (pwdb <= 14) 1883264912Skevlo pwdb -= 4; 1884264912Skevlo else if (pwdb <= 26) 1885264912Skevlo pwdb -= 8; 1886264912Skevlo else if (pwdb <= 34) 1887264912Skevlo pwdb -= 6; 1888264912Skevlo else if (pwdb <= 42) 1889264912Skevlo pwdb -= 2; 1890264912Skevlo } 1891251538Srpaulo } 1892251538Srpaulo if (sc->avg_pwdb == -1) /* Init. */ 1893251538Srpaulo sc->avg_pwdb = pwdb; 1894251538Srpaulo else if (sc->avg_pwdb < pwdb) 1895251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1896251538Srpaulo else 1897251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1898251538Srpaulo DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1899251538Srpaulo} 1900251538Srpaulo 1901251538Srpaulostatic int8_t 1902251538Srpaulourtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1903251538Srpaulo{ 1904251538Srpaulo static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1905251538Srpaulo struct r92c_rx_phystat *phy; 1906251538Srpaulo struct r92c_rx_cck *cck; 1907251538Srpaulo uint8_t rpt; 1908251538Srpaulo int8_t rssi; 1909251538Srpaulo 1910289758Savos if (rate <= URTWN_RIDX_CCK11) { 1911251538Srpaulo cck = (struct r92c_rx_cck *)physt; 1912251538Srpaulo if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1913251538Srpaulo rpt = (cck->agc_rpt >> 5) & 0x3; 1914251538Srpaulo rssi = (cck->agc_rpt & 0x1f) << 1; 1915251538Srpaulo } else { 1916251538Srpaulo rpt = (cck->agc_rpt >> 6) & 0x3; 1917251538Srpaulo rssi = cck->agc_rpt & 0x3e; 1918251538Srpaulo } 1919251538Srpaulo rssi = cckoff[rpt] - rssi; 1920251538Srpaulo } else { /* OFDM/HT. */ 1921251538Srpaulo phy = (struct r92c_rx_phystat *)physt; 1922251538Srpaulo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1923251538Srpaulo } 1924251538Srpaulo return (rssi); 1925251538Srpaulo} 1926251538Srpaulo 1927264912Skevlostatic int8_t 1928264912Skevlourtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1929264912Skevlo{ 1930264912Skevlo struct r92c_rx_phystat *phy; 1931264912Skevlo struct r88e_rx_cck *cck; 1932264912Skevlo uint8_t cck_agc_rpt, lna_idx, vga_idx; 1933264912Skevlo int8_t rssi; 1934264912Skevlo 1935264972Skevlo rssi = 0; 1936289758Savos if (rate <= URTWN_RIDX_CCK11) { 1937264912Skevlo cck = (struct r88e_rx_cck *)physt; 1938264912Skevlo cck_agc_rpt = cck->agc_rpt; 1939264912Skevlo lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1940281069Srpaulo vga_idx = cck_agc_rpt & 0x1f; 1941264912Skevlo switch (lna_idx) { 1942264912Skevlo case 7: 1943264912Skevlo if (vga_idx <= 27) 1944264912Skevlo rssi = -100 + 2* (27 - vga_idx); 1945264912Skevlo else 1946264912Skevlo rssi = -100; 1947264912Skevlo break; 1948264912Skevlo case 6: 1949264912Skevlo rssi = -48 + 2 * (2 - vga_idx); 1950264912Skevlo break; 1951264912Skevlo case 5: 1952264912Skevlo rssi = -42 + 2 * (7 - vga_idx); 1953264912Skevlo break; 1954264912Skevlo case 4: 1955264912Skevlo rssi = -36 + 2 * (7 - vga_idx); 1956264912Skevlo break; 1957264912Skevlo case 3: 1958264912Skevlo rssi = -24 + 2 * (7 - vga_idx); 1959264912Skevlo break; 1960264912Skevlo case 2: 1961264912Skevlo rssi = -12 + 2 * (5 - vga_idx); 1962264912Skevlo break; 1963264912Skevlo case 1: 1964264912Skevlo rssi = 8 - (2 * vga_idx); 1965264912Skevlo break; 1966264912Skevlo case 0: 1967264912Skevlo rssi = 14 - (2 * vga_idx); 1968264912Skevlo break; 1969264912Skevlo } 1970264912Skevlo rssi += 6; 1971264912Skevlo } else { /* OFDM/HT. */ 1972264912Skevlo phy = (struct r92c_rx_phystat *)physt; 1973264912Skevlo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1974264912Skevlo } 1975264912Skevlo return (rssi); 1976264912Skevlo} 1977264912Skevlo 1978251538Srpaulostatic int 1979290630Savosurtwn_tx_data(struct urtwn_softc *sc, struct ieee80211_node *ni, 1980290630Savos struct mbuf *m, struct urtwn_data *data) 1981251538Srpaulo{ 1982251538Srpaulo struct ieee80211_frame *wh; 1983290630Savos struct ieee80211_key *k = NULL; 1984287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1985251538Srpaulo struct ieee80211vap *vap = ni->ni_vap; 1986251538Srpaulo struct r92c_tx_desc *txd; 1987290630Savos uint8_t macid, raid, ridx, subtype, type, qsel; 1988290630Savos int ismcast; 1989251538Srpaulo 1990251538Srpaulo URTWN_ASSERT_LOCKED(sc); 1991251538Srpaulo 1992251538Srpaulo /* 1993251538Srpaulo * Software crypto. 1994251538Srpaulo */ 1995290630Savos wh = mtod(m, struct ieee80211_frame *); 1996264912Skevlo type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1997290630Savos subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1998290630Savos ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1999264912Skevlo 2000260444Skevlo if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2001290630Savos k = ieee80211_crypto_encap(ni, m); 2002251538Srpaulo if (k == NULL) { 2003251538Srpaulo device_printf(sc->sc_dev, 2004251538Srpaulo "ieee80211_crypto_encap returns NULL.\n"); 2005251538Srpaulo return (ENOBUFS); 2006251538Srpaulo } 2007251538Srpaulo 2008251538Srpaulo /* in case packet header moved, reset pointer */ 2009290630Savos wh = mtod(m, struct ieee80211_frame *); 2010251538Srpaulo } 2011281069Srpaulo 2012251538Srpaulo /* Fill Tx descriptor. */ 2013251538Srpaulo txd = (struct r92c_tx_desc *)data->buf; 2014251538Srpaulo memset(txd, 0, sizeof(*txd)); 2015251538Srpaulo 2016251538Srpaulo txd->txdw0 |= htole32( 2017251538Srpaulo SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 2018251538Srpaulo R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2019290630Savos if (ismcast) 2020251538Srpaulo txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2021290630Savos 2022290630Savos raid = R92C_RAID_11B; /* by default */ 2023290630Savos ridx = URTWN_RIDX_CCK1; 2024290630Savos if (!ismcast) { 2025290630Savos macid = URTWN_MACID_BSS; 2026290630Savos 2027290630Savos if (type == IEEE80211_FC0_TYPE_DATA) { 2028290630Savos qsel = R92C_TXDW1_QSEL_BE; 2029290630Savos 2030290630Savos if (!(m->m_flags & M_EAPOL)) { 2031290630Savos if (ic->ic_curmode != IEEE80211_MODE_11B) { 2032290630Savos raid = R92C_RAID_11BG; 2033290630Savos ridx = URTWN_RIDX_OFDM54; 2034290630Savos } else 2035290630Savos ridx = URTWN_RIDX_CCK11; 2036251538Srpaulo } 2037290630Savos 2038290630Savos if (sc->chip & URTWN_CHIP_88E) 2039290630Savos txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2040290630Savos else 2041290630Savos txd->txdw1 |= htole32(R92C_TXDW1_AGGBK); 2042290630Savos 2043290630Savos if (ic->ic_flags & IEEE80211_F_USEPROT) { 2044290630Savos switch (ic->ic_protmode) { 2045290630Savos case IEEE80211_PROT_CTSONLY: 2046290630Savos txd->txdw4 |= htole32( 2047290630Savos R92C_TXDW4_CTS2SELF | 2048290630Savos R92C_TXDW4_HWRTSEN); 2049290630Savos break; 2050290630Savos case IEEE80211_PROT_RTSCTS: 2051290630Savos txd->txdw4 |= htole32( 2052290630Savos R92C_TXDW4_RTSEN | 2053290630Savos R92C_TXDW4_HWRTSEN); 2054290630Savos break; 2055290630Savos default: 2056290630Savos break; 2057290630Savos } 2058290630Savos } 2059290630Savos txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 2060290630Savos URTWN_RIDX_OFDM24)); 2061290630Savos txd->txdw5 |= htole32(0x0001ff00); 2062290630Savos } else /* IEEE80211_FC0_TYPE_MGT */ 2063290630Savos qsel = R92C_TXDW1_QSEL_MGNT; 2064251538Srpaulo } else { 2065290630Savos macid = URTWN_MACID_BC; 2066290630Savos qsel = R92C_TXDW1_QSEL_MGNT; 2067290630Savos } 2068251538Srpaulo 2069290630Savos txd->txdw1 |= htole32( 2070290630Savos SM(R92C_TXDW1_QSEL, qsel) | 2071290630Savos SM(R92C_TXDW1_RAID, raid)); 2072290630Savos 2073290630Savos if (sc->chip & URTWN_CHIP_88E) 2074290630Savos txd->txdw1 |= htole32(SM(R88E_TXDW1_MACID, macid)); 2075290630Savos else 2076290630Savos txd->txdw1 |= htole32(SM(R92C_TXDW1_MACID, macid)); 2077290630Savos 2078290630Savos txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, ridx)); 2079290630Savos /* not sure here */ 2080290630Savos if (ridx <= URTWN_RIDX_CCK11) 2081251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2082251538Srpaulo 2083288534Sadrian if (!IEEE80211_QOS_HAS_SEQ(wh)) { 2084251538Srpaulo /* Use HW sequence numbering for non-QoS frames. */ 2085290630Savos txd->txdseq = htole16(R92C_TXDSEQ_HWSEQ_EN); 2086290630Savos } else { 2087290630Savos /* Set sequence number. */ 2088290630Savos txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 2089290630Savos } 2090251538Srpaulo 2091251538Srpaulo if (ieee80211_radiotap_active_vap(vap)) { 2092251538Srpaulo struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2093251538Srpaulo 2094251538Srpaulo tap->wt_flags = 0; 2095251538Srpaulo tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2096251538Srpaulo tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2097290630Savos if (k != NULL) 2098290630Savos tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2099290630Savos ieee80211_radiotap_tx(vap, m); 2100251538Srpaulo } 2101251538Srpaulo 2102290630Savos data->ni = ni; 2103251538Srpaulo 2104290630Savos urtwn_tx_start(sc, m, type, data); 2105290630Savos 2106290630Savos return (0); 2107290630Savos} 2108290630Savos 2109290630Savosstatic void 2110290630Savosurtwn_tx_start(struct urtwn_softc *sc, struct mbuf *m, uint8_t type, 2111290630Savos struct urtwn_data *data) 2112290630Savos{ 2113290630Savos struct usb_xfer *xfer; 2114290630Savos struct r92c_tx_desc *txd; 2115290630Savos uint16_t ac, sum; 2116290630Savos int i, xferlen; 2117290630Savos struct usb_xfer *urtwn_pipes[WME_NUM_AC] = { 2118290630Savos sc->sc_xfer[URTWN_BULK_TX_BE], 2119290630Savos sc->sc_xfer[URTWN_BULK_TX_BK], 2120290630Savos sc->sc_xfer[URTWN_BULK_TX_VI], 2121290630Savos sc->sc_xfer[URTWN_BULK_TX_VO] 2122290630Savos }; 2123290630Savos 2124290630Savos URTWN_ASSERT_LOCKED(sc); 2125290630Savos 2126290630Savos ac = M_WME_GETAC(m); 2127290630Savos 2128290630Savos switch (type) { 2129290630Savos case IEEE80211_FC0_TYPE_CTL: 2130290630Savos case IEEE80211_FC0_TYPE_MGT: 2131290630Savos xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 2132290630Savos break; 2133290630Savos default: 2134290630Savos xfer = urtwn_pipes[ac]; 2135290630Savos break; 2136290630Savos } 2137290630Savos 2138290630Savos txd = (struct r92c_tx_desc *)data->buf; 2139290630Savos txd->txdw0 |= htole32(SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len)); 2140290630Savos 2141290630Savos /* Compute Tx descriptor checksum. */ 2142290630Savos sum = 0; 2143290630Savos for (i = 0; i < sizeof(*txd) / 2; i++) 2144290630Savos sum ^= ((uint16_t *)txd)[i]; 2145290630Savos txd->txdsum = sum; /* NB: already little endian. */ 2146290630Savos 2147290630Savos xferlen = sizeof(*txd) + m->m_pkthdr.len; 2148290630Savos m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 2149290630Savos 2150251538Srpaulo data->buflen = xferlen; 2151290630Savos data->m = m; 2152251538Srpaulo 2153251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 2154251538Srpaulo usbd_transfer_start(xfer); 2155251538Srpaulo} 2156251538Srpaulo 2157287197Sglebiusstatic int 2158287197Sglebiusurtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 2159251538Srpaulo{ 2160287197Sglebius struct urtwn_softc *sc = ic->ic_softc; 2161287197Sglebius int error; 2162261863Srpaulo 2163261863Srpaulo URTWN_LOCK(sc); 2164287197Sglebius if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2165287197Sglebius URTWN_UNLOCK(sc); 2166287197Sglebius return (ENXIO); 2167287197Sglebius } 2168287197Sglebius error = mbufq_enqueue(&sc->sc_snd, m); 2169287197Sglebius if (error) { 2170287197Sglebius URTWN_UNLOCK(sc); 2171287197Sglebius return (error); 2172287197Sglebius } 2173287197Sglebius urtwn_start(sc); 2174261863Srpaulo URTWN_UNLOCK(sc); 2175287197Sglebius 2176287197Sglebius return (0); 2177261863Srpaulo} 2178261863Srpaulo 2179261863Srpaulostatic void 2180287197Sglebiusurtwn_start(struct urtwn_softc *sc) 2181261863Srpaulo{ 2182251538Srpaulo struct ieee80211_node *ni; 2183251538Srpaulo struct mbuf *m; 2184251538Srpaulo struct urtwn_data *bf; 2185251538Srpaulo 2186261863Srpaulo URTWN_ASSERT_LOCKED(sc); 2187287197Sglebius while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2188251538Srpaulo bf = urtwn_getbuf(sc); 2189251538Srpaulo if (bf == NULL) { 2190287197Sglebius mbufq_prepend(&sc->sc_snd, m); 2191251538Srpaulo break; 2192251538Srpaulo } 2193251538Srpaulo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2194251538Srpaulo m->m_pkthdr.rcvif = NULL; 2195290630Savos if (urtwn_tx_data(sc, ni, m, bf) != 0) { 2196287197Sglebius if_inc_counter(ni->ni_vap->iv_ifp, 2197287197Sglebius IFCOUNTER_OERRORS, 1); 2198251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2199288353Sadrian m_freem(m); 2200251538Srpaulo ieee80211_free_node(ni); 2201251538Srpaulo break; 2202251538Srpaulo } 2203251538Srpaulo sc->sc_txtimer = 5; 2204251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2205251538Srpaulo } 2206251538Srpaulo} 2207251538Srpaulo 2208287197Sglebiusstatic void 2209287197Sglebiusurtwn_parent(struct ieee80211com *ic) 2210251538Srpaulo{ 2211286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 2212287197Sglebius int startall = 0; 2213251538Srpaulo 2214263153Skevlo URTWN_LOCK(sc); 2215287197Sglebius if (sc->sc_flags & URTWN_DETACHED) { 2216287197Sglebius URTWN_UNLOCK(sc); 2217287197Sglebius return; 2218287197Sglebius } 2219287197Sglebius if (ic->ic_nrunning > 0) { 2220287197Sglebius if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2221287197Sglebius urtwn_init(sc); 2222287197Sglebius startall = 1; 2223287197Sglebius } 2224287197Sglebius } else if (sc->sc_flags & URTWN_RUNNING) 2225287197Sglebius urtwn_stop(sc); 2226263153Skevlo URTWN_UNLOCK(sc); 2227263153Skevlo 2228287197Sglebius if (startall) 2229287197Sglebius ieee80211_start_all(ic); 2230251538Srpaulo} 2231251538Srpaulo 2232264912Skevlostatic __inline int 2233251538Srpaulourtwn_power_on(struct urtwn_softc *sc) 2234251538Srpaulo{ 2235264912Skevlo 2236264912Skevlo return sc->sc_power_on(sc); 2237264912Skevlo} 2238264912Skevlo 2239264912Skevlostatic int 2240264912Skevlourtwn_r92c_power_on(struct urtwn_softc *sc) 2241264912Skevlo{ 2242251538Srpaulo uint32_t reg; 2243251538Srpaulo int ntries; 2244251538Srpaulo 2245251538Srpaulo /* Wait for autoload done bit. */ 2246251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2247251538Srpaulo if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2248251538Srpaulo break; 2249266472Shselasky urtwn_ms_delay(sc); 2250251538Srpaulo } 2251251538Srpaulo if (ntries == 1000) { 2252251538Srpaulo device_printf(sc->sc_dev, 2253251538Srpaulo "timeout waiting for chip autoload\n"); 2254251538Srpaulo return (ETIMEDOUT); 2255251538Srpaulo } 2256251538Srpaulo 2257251538Srpaulo /* Unlock ISO/CLK/Power control register. */ 2258251538Srpaulo urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2259251538Srpaulo /* Move SPS into PWM mode. */ 2260251538Srpaulo urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2261266472Shselasky urtwn_ms_delay(sc); 2262251538Srpaulo 2263251538Srpaulo reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2264251538Srpaulo if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2265251538Srpaulo urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2266251538Srpaulo reg | R92C_LDOV12D_CTRL_LDV12_EN); 2267266472Shselasky urtwn_ms_delay(sc); 2268251538Srpaulo urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2269251538Srpaulo urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2270251538Srpaulo ~R92C_SYS_ISO_CTRL_MD2PP); 2271251538Srpaulo } 2272251538Srpaulo 2273251538Srpaulo /* Auto enable WLAN. */ 2274251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2275251538Srpaulo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2276251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2277262822Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2278262822Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2279251538Srpaulo break; 2280266472Shselasky urtwn_ms_delay(sc); 2281251538Srpaulo } 2282251538Srpaulo if (ntries == 1000) { 2283251538Srpaulo device_printf(sc->sc_dev, 2284251538Srpaulo "timeout waiting for MAC auto ON\n"); 2285251538Srpaulo return (ETIMEDOUT); 2286251538Srpaulo } 2287251538Srpaulo 2288251538Srpaulo /* Enable radio, GPIO and LED functions. */ 2289251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2290251538Srpaulo R92C_APS_FSMCO_AFSM_HSUS | 2291251538Srpaulo R92C_APS_FSMCO_PDN_EN | 2292251538Srpaulo R92C_APS_FSMCO_PFM_ALDN); 2293251538Srpaulo /* Release RF digital isolation. */ 2294251538Srpaulo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2295251538Srpaulo urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2296251538Srpaulo 2297251538Srpaulo /* Initialize MAC. */ 2298251538Srpaulo urtwn_write_1(sc, R92C_APSD_CTRL, 2299251538Srpaulo urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2300251538Srpaulo for (ntries = 0; ntries < 200; ntries++) { 2301251538Srpaulo if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2302251538Srpaulo R92C_APSD_CTRL_OFF_STATUS)) 2303251538Srpaulo break; 2304266472Shselasky urtwn_ms_delay(sc); 2305251538Srpaulo } 2306251538Srpaulo if (ntries == 200) { 2307251538Srpaulo device_printf(sc->sc_dev, 2308251538Srpaulo "timeout waiting for MAC initialization\n"); 2309251538Srpaulo return (ETIMEDOUT); 2310251538Srpaulo } 2311251538Srpaulo 2312251538Srpaulo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2313251538Srpaulo reg = urtwn_read_2(sc, R92C_CR); 2314251538Srpaulo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2315251538Srpaulo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2316251538Srpaulo R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2317251538Srpaulo R92C_CR_ENSEC; 2318251538Srpaulo urtwn_write_2(sc, R92C_CR, reg); 2319251538Srpaulo 2320251538Srpaulo urtwn_write_1(sc, 0xfe10, 0x19); 2321251538Srpaulo return (0); 2322251538Srpaulo} 2323251538Srpaulo 2324251538Srpaulostatic int 2325264912Skevlourtwn_r88e_power_on(struct urtwn_softc *sc) 2326264912Skevlo{ 2327264912Skevlo uint32_t reg; 2328264912Skevlo int ntries; 2329264912Skevlo 2330264912Skevlo /* Wait for power ready bit. */ 2331264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2332281918Skevlo if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2333264912Skevlo break; 2334266472Shselasky urtwn_ms_delay(sc); 2335264912Skevlo } 2336264912Skevlo if (ntries == 5000) { 2337264912Skevlo device_printf(sc->sc_dev, 2338264912Skevlo "timeout waiting for chip power up\n"); 2339264912Skevlo return (ETIMEDOUT); 2340264912Skevlo } 2341264912Skevlo 2342264912Skevlo /* Reset BB. */ 2343264912Skevlo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2344264912Skevlo urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2345264912Skevlo R92C_SYS_FUNC_EN_BB_GLB_RST)); 2346264912Skevlo 2347281918Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2348281918Skevlo urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2349264912Skevlo 2350264912Skevlo /* Disable HWPDN. */ 2351281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2352281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2353264912Skevlo 2354264912Skevlo /* Disable WL suspend. */ 2355281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2356281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & 2357281918Skevlo ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2358264912Skevlo 2359281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2360281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2361264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2362281918Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2363281918Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2364264912Skevlo break; 2365266472Shselasky urtwn_ms_delay(sc); 2366264912Skevlo } 2367264912Skevlo if (ntries == 5000) 2368264912Skevlo return (ETIMEDOUT); 2369264912Skevlo 2370264912Skevlo /* Enable LDO normal mode. */ 2371281918Skevlo urtwn_write_1(sc, R92C_LPLDO_CTRL, 2372281918Skevlo urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2373264912Skevlo 2374264912Skevlo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2375264912Skevlo urtwn_write_2(sc, R92C_CR, 0); 2376264912Skevlo reg = urtwn_read_2(sc, R92C_CR); 2377264912Skevlo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2378264912Skevlo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2379264912Skevlo R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2380264912Skevlo urtwn_write_2(sc, R92C_CR, reg); 2381264912Skevlo 2382264912Skevlo return (0); 2383264912Skevlo} 2384264912Skevlo 2385264912Skevlostatic int 2386251538Srpaulourtwn_llt_init(struct urtwn_softc *sc) 2387251538Srpaulo{ 2388264912Skevlo int i, error, page_count, pktbuf_count; 2389251538Srpaulo 2390264912Skevlo page_count = (sc->chip & URTWN_CHIP_88E) ? 2391264912Skevlo R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2392264912Skevlo pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2393264912Skevlo R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2394264912Skevlo 2395264912Skevlo /* Reserve pages [0; page_count]. */ 2396264912Skevlo for (i = 0; i < page_count; i++) { 2397251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2398251538Srpaulo return (error); 2399251538Srpaulo } 2400251538Srpaulo /* NB: 0xff indicates end-of-list. */ 2401251538Srpaulo if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2402251538Srpaulo return (error); 2403251538Srpaulo /* 2404264912Skevlo * Use pages [page_count + 1; pktbuf_count - 1] 2405251538Srpaulo * as ring buffer. 2406251538Srpaulo */ 2407264912Skevlo for (++i; i < pktbuf_count - 1; i++) { 2408251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2409251538Srpaulo return (error); 2410251538Srpaulo } 2411251538Srpaulo /* Make the last page point to the beginning of the ring buffer. */ 2412264912Skevlo error = urtwn_llt_write(sc, i, page_count + 1); 2413251538Srpaulo return (error); 2414251538Srpaulo} 2415251538Srpaulo 2416251538Srpaulostatic void 2417251538Srpaulourtwn_fw_reset(struct urtwn_softc *sc) 2418251538Srpaulo{ 2419251538Srpaulo uint16_t reg; 2420251538Srpaulo int ntries; 2421251538Srpaulo 2422251538Srpaulo /* Tell 8051 to reset itself. */ 2423251538Srpaulo urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2424251538Srpaulo 2425251538Srpaulo /* Wait until 8051 resets by itself. */ 2426251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 2427251538Srpaulo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2428251538Srpaulo if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2429251538Srpaulo return; 2430266472Shselasky urtwn_ms_delay(sc); 2431251538Srpaulo } 2432251538Srpaulo /* Force 8051 reset. */ 2433251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2434251538Srpaulo} 2435251538Srpaulo 2436264912Skevlostatic void 2437264912Skevlourtwn_r88e_fw_reset(struct urtwn_softc *sc) 2438264912Skevlo{ 2439264912Skevlo uint16_t reg; 2440264912Skevlo 2441264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2442264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2443264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2444264912Skevlo} 2445264912Skevlo 2446251538Srpaulostatic int 2447251538Srpaulourtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2448251538Srpaulo{ 2449251538Srpaulo uint32_t reg; 2450251538Srpaulo int off, mlen, error = 0; 2451251538Srpaulo 2452251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2453251538Srpaulo reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2454251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2455251538Srpaulo 2456251538Srpaulo off = R92C_FW_START_ADDR; 2457251538Srpaulo while (len > 0) { 2458251538Srpaulo if (len > 196) 2459251538Srpaulo mlen = 196; 2460251538Srpaulo else if (len > 4) 2461251538Srpaulo mlen = 4; 2462251538Srpaulo else 2463251538Srpaulo mlen = 1; 2464251538Srpaulo /* XXX fix this deconst */ 2465281069Srpaulo error = urtwn_write_region_1(sc, off, 2466251538Srpaulo __DECONST(uint8_t *, buf), mlen); 2467251538Srpaulo if (error != 0) 2468251538Srpaulo break; 2469251538Srpaulo off += mlen; 2470251538Srpaulo buf += mlen; 2471251538Srpaulo len -= mlen; 2472251538Srpaulo } 2473251538Srpaulo return (error); 2474251538Srpaulo} 2475251538Srpaulo 2476251538Srpaulostatic int 2477251538Srpaulourtwn_load_firmware(struct urtwn_softc *sc) 2478251538Srpaulo{ 2479251538Srpaulo const struct firmware *fw; 2480251538Srpaulo const struct r92c_fw_hdr *hdr; 2481251538Srpaulo const char *imagename; 2482251538Srpaulo const u_char *ptr; 2483251538Srpaulo size_t len; 2484251538Srpaulo uint32_t reg; 2485251538Srpaulo int mlen, ntries, page, error; 2486251538Srpaulo 2487264864Skevlo URTWN_UNLOCK(sc); 2488251538Srpaulo /* Read firmware image from the filesystem. */ 2489264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2490264912Skevlo imagename = "urtwn-rtl8188eufw"; 2491264912Skevlo else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2492264912Skevlo URTWN_CHIP_UMC_A_CUT) 2493251538Srpaulo imagename = "urtwn-rtl8192cfwU"; 2494251538Srpaulo else 2495251538Srpaulo imagename = "urtwn-rtl8192cfwT"; 2496251538Srpaulo 2497251538Srpaulo fw = firmware_get(imagename); 2498264864Skevlo URTWN_LOCK(sc); 2499251538Srpaulo if (fw == NULL) { 2500251538Srpaulo device_printf(sc->sc_dev, 2501251538Srpaulo "failed loadfirmware of file %s\n", imagename); 2502251538Srpaulo return (ENOENT); 2503251538Srpaulo } 2504251538Srpaulo 2505251538Srpaulo len = fw->datasize; 2506251538Srpaulo 2507251538Srpaulo if (len < sizeof(*hdr)) { 2508251538Srpaulo device_printf(sc->sc_dev, "firmware too short\n"); 2509251538Srpaulo error = EINVAL; 2510251538Srpaulo goto fail; 2511251538Srpaulo } 2512251538Srpaulo ptr = fw->data; 2513251538Srpaulo hdr = (const struct r92c_fw_hdr *)ptr; 2514251538Srpaulo /* Check if there is a valid FW header and skip it. */ 2515251538Srpaulo if ((le16toh(hdr->signature) >> 4) == 0x88c || 2516264912Skevlo (le16toh(hdr->signature) >> 4) == 0x88e || 2517251538Srpaulo (le16toh(hdr->signature) >> 4) == 0x92c) { 2518251538Srpaulo DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2519251538Srpaulo le16toh(hdr->version), le16toh(hdr->subversion), 2520251538Srpaulo hdr->month, hdr->date, hdr->hour, hdr->minute); 2521251538Srpaulo ptr += sizeof(*hdr); 2522251538Srpaulo len -= sizeof(*hdr); 2523251538Srpaulo } 2524251538Srpaulo 2525264912Skevlo if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2526264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2527264912Skevlo urtwn_r88e_fw_reset(sc); 2528264912Skevlo else 2529264912Skevlo urtwn_fw_reset(sc); 2530251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 0); 2531251538Srpaulo } 2532264912Skevlo 2533268487Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2534268487Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2535268487Skevlo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2536268487Skevlo R92C_SYS_FUNC_EN_CPUEN); 2537268487Skevlo } 2538251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2539251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2540251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 2, 2541251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2542251538Srpaulo 2543263154Skevlo /* Reset the FWDL checksum. */ 2544263154Skevlo urtwn_write_1(sc, R92C_MCUFWDL, 2545263154Skevlo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2546263154Skevlo 2547251538Srpaulo for (page = 0; len > 0; page++) { 2548251538Srpaulo mlen = min(len, R92C_FW_PAGE_SIZE); 2549251538Srpaulo error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2550251538Srpaulo if (error != 0) { 2551251538Srpaulo device_printf(sc->sc_dev, 2552251538Srpaulo "could not load firmware page\n"); 2553251538Srpaulo goto fail; 2554251538Srpaulo } 2555251538Srpaulo ptr += mlen; 2556251538Srpaulo len -= mlen; 2557251538Srpaulo } 2558251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2559251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2560251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2561251538Srpaulo 2562251538Srpaulo /* Wait for checksum report. */ 2563251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2564251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2565251538Srpaulo break; 2566266472Shselasky urtwn_ms_delay(sc); 2567251538Srpaulo } 2568251538Srpaulo if (ntries == 1000) { 2569251538Srpaulo device_printf(sc->sc_dev, 2570251538Srpaulo "timeout waiting for checksum report\n"); 2571251538Srpaulo error = ETIMEDOUT; 2572251538Srpaulo goto fail; 2573251538Srpaulo } 2574251538Srpaulo 2575251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2576251538Srpaulo reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2577251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2578264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2579264912Skevlo urtwn_r88e_fw_reset(sc); 2580251538Srpaulo /* Wait for firmware readiness. */ 2581251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2582251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2583251538Srpaulo break; 2584266472Shselasky urtwn_ms_delay(sc); 2585251538Srpaulo } 2586251538Srpaulo if (ntries == 1000) { 2587251538Srpaulo device_printf(sc->sc_dev, 2588251538Srpaulo "timeout waiting for firmware readiness\n"); 2589251538Srpaulo error = ETIMEDOUT; 2590251538Srpaulo goto fail; 2591251538Srpaulo } 2592251538Srpaulofail: 2593251538Srpaulo firmware_put(fw, FIRMWARE_UNLOAD); 2594251538Srpaulo return (error); 2595251538Srpaulo} 2596251538Srpaulo 2597264912Skevlostatic __inline int 2598251538Srpaulourtwn_dma_init(struct urtwn_softc *sc) 2599251538Srpaulo{ 2600281069Srpaulo 2601264912Skevlo return sc->sc_dma_init(sc); 2602264912Skevlo} 2603264912Skevlo 2604264912Skevlostatic int 2605264912Skevlourtwn_r92c_dma_init(struct urtwn_softc *sc) 2606264912Skevlo{ 2607251538Srpaulo int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2608251538Srpaulo uint32_t reg; 2609251538Srpaulo int error; 2610251538Srpaulo 2611251538Srpaulo /* Initialize LLT table. */ 2612251538Srpaulo error = urtwn_llt_init(sc); 2613251538Srpaulo if (error != 0) 2614251538Srpaulo return (error); 2615251538Srpaulo 2616251538Srpaulo /* Get Tx queues to USB endpoints mapping. */ 2617251538Srpaulo hashq = hasnq = haslq = 0; 2618251538Srpaulo reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2619251538Srpaulo DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2620251538Srpaulo if (MS(reg, R92C_USB_EP_HQ) != 0) 2621251538Srpaulo hashq = 1; 2622251538Srpaulo if (MS(reg, R92C_USB_EP_NQ) != 0) 2623251538Srpaulo hasnq = 1; 2624251538Srpaulo if (MS(reg, R92C_USB_EP_LQ) != 0) 2625251538Srpaulo haslq = 1; 2626251538Srpaulo nqueues = hashq + hasnq + haslq; 2627251538Srpaulo if (nqueues == 0) 2628251538Srpaulo return (EIO); 2629251538Srpaulo /* Get the number of pages for each queue. */ 2630251538Srpaulo nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2631251538Srpaulo /* The remaining pages are assigned to the high priority queue. */ 2632251538Srpaulo nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2633251538Srpaulo 2634251538Srpaulo /* Set number of pages for normal priority queue. */ 2635251538Srpaulo urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2636251538Srpaulo urtwn_write_4(sc, R92C_RQPN, 2637251538Srpaulo /* Set number of pages for public queue. */ 2638251538Srpaulo SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2639251538Srpaulo /* Set number of pages for high priority queue. */ 2640251538Srpaulo SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2641251538Srpaulo /* Set number of pages for low priority queue. */ 2642251538Srpaulo SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2643251538Srpaulo /* Load values. */ 2644251538Srpaulo R92C_RQPN_LD); 2645251538Srpaulo 2646251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2647251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2648251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2649251538Srpaulo urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2650251538Srpaulo urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2651251538Srpaulo 2652251538Srpaulo /* Set queue to USB pipe mapping. */ 2653251538Srpaulo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2654251538Srpaulo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2655251538Srpaulo if (nqueues == 1) { 2656251538Srpaulo if (hashq) 2657251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2658251538Srpaulo else if (hasnq) 2659251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2660251538Srpaulo else 2661251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2662251538Srpaulo } else if (nqueues == 2) { 2663251538Srpaulo /* All 2-endpoints configs have a high priority queue. */ 2664251538Srpaulo if (!hashq) 2665251538Srpaulo return (EIO); 2666251538Srpaulo if (hasnq) 2667251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2668251538Srpaulo else 2669251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2670251538Srpaulo } else 2671251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2672251538Srpaulo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2673251538Srpaulo 2674251538Srpaulo /* Set Tx/Rx transfer page boundary. */ 2675251538Srpaulo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2676251538Srpaulo 2677251538Srpaulo /* Set Tx/Rx transfer page size. */ 2678251538Srpaulo urtwn_write_1(sc, R92C_PBP, 2679251538Srpaulo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2680251538Srpaulo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2681251538Srpaulo return (0); 2682251538Srpaulo} 2683251538Srpaulo 2684264912Skevlostatic int 2685264912Skevlourtwn_r88e_dma_init(struct urtwn_softc *sc) 2686264912Skevlo{ 2687264912Skevlo struct usb_interface *iface; 2688264912Skevlo uint32_t reg; 2689264912Skevlo int nqueues; 2690264912Skevlo int error; 2691264912Skevlo 2692264912Skevlo /* Initialize LLT table. */ 2693264912Skevlo error = urtwn_llt_init(sc); 2694264912Skevlo if (error != 0) 2695264912Skevlo return (error); 2696264912Skevlo 2697264912Skevlo /* Get Tx queues to USB endpoints mapping. */ 2698264912Skevlo iface = usbd_get_iface(sc->sc_udev, 0); 2699264912Skevlo nqueues = iface->idesc->bNumEndpoints - 1; 2700264912Skevlo if (nqueues == 0) 2701264912Skevlo return (EIO); 2702264912Skevlo 2703264912Skevlo /* Set number of pages for normal priority queue. */ 2704264912Skevlo urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2705264912Skevlo urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2706264912Skevlo 2707264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2708264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2709264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2710264912Skevlo urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2711264912Skevlo urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2712264912Skevlo 2713264912Skevlo /* Set queue to USB pipe mapping. */ 2714264912Skevlo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2715264912Skevlo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2716264912Skevlo if (nqueues == 1) 2717264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2718264912Skevlo else if (nqueues == 2) 2719264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2720264912Skevlo else 2721264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2722264912Skevlo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2723264912Skevlo 2724264912Skevlo /* Set Tx/Rx transfer page boundary. */ 2725264912Skevlo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2726264912Skevlo 2727264912Skevlo /* Set Tx/Rx transfer page size. */ 2728264912Skevlo urtwn_write_1(sc, R92C_PBP, 2729264912Skevlo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2730264912Skevlo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2731264912Skevlo 2732264912Skevlo return (0); 2733264912Skevlo} 2734264912Skevlo 2735251538Srpaulostatic void 2736251538Srpaulourtwn_mac_init(struct urtwn_softc *sc) 2737251538Srpaulo{ 2738251538Srpaulo int i; 2739251538Srpaulo 2740251538Srpaulo /* Write MAC initialization values. */ 2741264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2742264912Skevlo for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2743264912Skevlo urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2744264912Skevlo rtl8188eu_mac[i].val); 2745264912Skevlo } 2746264912Skevlo urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2747264912Skevlo } else { 2748264912Skevlo for (i = 0; i < nitems(rtl8192cu_mac); i++) 2749264912Skevlo urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2750264912Skevlo rtl8192cu_mac[i].val); 2751264912Skevlo } 2752251538Srpaulo} 2753251538Srpaulo 2754251538Srpaulostatic void 2755251538Srpaulourtwn_bb_init(struct urtwn_softc *sc) 2756251538Srpaulo{ 2757251538Srpaulo const struct urtwn_bb_prog *prog; 2758251538Srpaulo uint32_t reg; 2759264912Skevlo uint8_t crystalcap; 2760251538Srpaulo int i; 2761251538Srpaulo 2762251538Srpaulo /* Enable BB and RF. */ 2763251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2764251538Srpaulo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2765251538Srpaulo R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2766251538Srpaulo R92C_SYS_FUNC_EN_DIO_RF); 2767251538Srpaulo 2768264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 2769264912Skevlo urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2770251538Srpaulo 2771251538Srpaulo urtwn_write_1(sc, R92C_RF_CTRL, 2772251538Srpaulo R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2773251538Srpaulo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2774251538Srpaulo R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2775251538Srpaulo R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2776251538Srpaulo 2777264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2778264912Skevlo urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2779264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 2780264912Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2781264912Skevlo } 2782251538Srpaulo 2783251538Srpaulo /* Select BB programming based on board type. */ 2784264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2785264912Skevlo prog = &rtl8188eu_bb_prog; 2786264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2787251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2788251538Srpaulo prog = &rtl8188ce_bb_prog; 2789251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2790251538Srpaulo prog = &rtl8188ru_bb_prog; 2791251538Srpaulo else 2792251538Srpaulo prog = &rtl8188cu_bb_prog; 2793251538Srpaulo } else { 2794251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2795251538Srpaulo prog = &rtl8192ce_bb_prog; 2796251538Srpaulo else 2797251538Srpaulo prog = &rtl8192cu_bb_prog; 2798251538Srpaulo } 2799251538Srpaulo /* Write BB initialization values. */ 2800251538Srpaulo for (i = 0; i < prog->count; i++) { 2801251538Srpaulo urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2802266472Shselasky urtwn_ms_delay(sc); 2803251538Srpaulo } 2804251538Srpaulo 2805251538Srpaulo if (sc->chip & URTWN_CHIP_92C_1T2R) { 2806251538Srpaulo /* 8192C 1T only configuration. */ 2807251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2808251538Srpaulo reg = (reg & ~0x00000003) | 0x2; 2809251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2810251538Srpaulo 2811251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2812251538Srpaulo reg = (reg & ~0x00300033) | 0x00200022; 2813251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2814251538Srpaulo 2815251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2816251538Srpaulo reg = (reg & ~0xff000000) | 0x45 << 24; 2817251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2818251538Srpaulo 2819251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2820251538Srpaulo reg = (reg & ~0x000000ff) | 0x23; 2821251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2822251538Srpaulo 2823251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2824251538Srpaulo reg = (reg & ~0x00000030) | 1 << 4; 2825251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2826251538Srpaulo 2827251538Srpaulo reg = urtwn_bb_read(sc, 0xe74); 2828251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2829251538Srpaulo urtwn_bb_write(sc, 0xe74, reg); 2830251538Srpaulo reg = urtwn_bb_read(sc, 0xe78); 2831251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2832251538Srpaulo urtwn_bb_write(sc, 0xe78, reg); 2833251538Srpaulo reg = urtwn_bb_read(sc, 0xe7c); 2834251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2835251538Srpaulo urtwn_bb_write(sc, 0xe7c, reg); 2836251538Srpaulo reg = urtwn_bb_read(sc, 0xe80); 2837251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2838251538Srpaulo urtwn_bb_write(sc, 0xe80, reg); 2839251538Srpaulo reg = urtwn_bb_read(sc, 0xe88); 2840251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2841251538Srpaulo urtwn_bb_write(sc, 0xe88, reg); 2842251538Srpaulo } 2843251538Srpaulo 2844251538Srpaulo /* Write AGC values. */ 2845251538Srpaulo for (i = 0; i < prog->agccount; i++) { 2846251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2847251538Srpaulo prog->agcvals[i]); 2848266472Shselasky urtwn_ms_delay(sc); 2849251538Srpaulo } 2850251538Srpaulo 2851264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2852264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2853266472Shselasky urtwn_ms_delay(sc); 2854264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2855266472Shselasky urtwn_ms_delay(sc); 2856264912Skevlo 2857264912Skevlo crystalcap = sc->r88e_rom[0xb9]; 2858264912Skevlo if (crystalcap == 0xff) 2859264912Skevlo crystalcap = 0x20; 2860264912Skevlo crystalcap &= 0x3f; 2861264912Skevlo reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2862264912Skevlo urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2863264912Skevlo RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2864264912Skevlo crystalcap | crystalcap << 6)); 2865264912Skevlo } else { 2866264912Skevlo if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2867264912Skevlo R92C_HSSI_PARAM2_CCK_HIPWR) 2868264912Skevlo sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2869264912Skevlo } 2870251538Srpaulo} 2871251538Srpaulo 2872289066Skevlostatic void 2873251538Srpaulourtwn_rf_init(struct urtwn_softc *sc) 2874251538Srpaulo{ 2875251538Srpaulo const struct urtwn_rf_prog *prog; 2876251538Srpaulo uint32_t reg, type; 2877251538Srpaulo int i, j, idx, off; 2878251538Srpaulo 2879251538Srpaulo /* Select RF programming based on board type. */ 2880264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2881264912Skevlo prog = rtl8188eu_rf_prog; 2882264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2883251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2884251538Srpaulo prog = rtl8188ce_rf_prog; 2885251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2886251538Srpaulo prog = rtl8188ru_rf_prog; 2887251538Srpaulo else 2888251538Srpaulo prog = rtl8188cu_rf_prog; 2889251538Srpaulo } else 2890251538Srpaulo prog = rtl8192ce_rf_prog; 2891251538Srpaulo 2892251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2893251538Srpaulo /* Save RF_ENV control type. */ 2894251538Srpaulo idx = i / 2; 2895251538Srpaulo off = (i % 2) * 16; 2896251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2897251538Srpaulo type = (reg >> off) & 0x10; 2898251538Srpaulo 2899251538Srpaulo /* Set RF_ENV enable. */ 2900251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2901251538Srpaulo reg |= 0x100000; 2902251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2903266472Shselasky urtwn_ms_delay(sc); 2904251538Srpaulo /* Set RF_ENV output high. */ 2905251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2906251538Srpaulo reg |= 0x10; 2907251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2908266472Shselasky urtwn_ms_delay(sc); 2909251538Srpaulo /* Set address and data lengths of RF registers. */ 2910251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2911251538Srpaulo reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2912251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2913266472Shselasky urtwn_ms_delay(sc); 2914251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2915251538Srpaulo reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2916251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2917266472Shselasky urtwn_ms_delay(sc); 2918251538Srpaulo 2919251538Srpaulo /* Write RF initialization values for this chain. */ 2920251538Srpaulo for (j = 0; j < prog[i].count; j++) { 2921251538Srpaulo if (prog[i].regs[j] >= 0xf9 && 2922251538Srpaulo prog[i].regs[j] <= 0xfe) { 2923251538Srpaulo /* 2924251538Srpaulo * These are fake RF registers offsets that 2925251538Srpaulo * indicate a delay is required. 2926251538Srpaulo */ 2927266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2928251538Srpaulo continue; 2929251538Srpaulo } 2930251538Srpaulo urtwn_rf_write(sc, i, prog[i].regs[j], 2931251538Srpaulo prog[i].vals[j]); 2932266472Shselasky urtwn_ms_delay(sc); 2933251538Srpaulo } 2934251538Srpaulo 2935251538Srpaulo /* Restore RF_ENV control type. */ 2936251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2937251538Srpaulo reg &= ~(0x10 << off) | (type << off); 2938251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2939251538Srpaulo 2940251538Srpaulo /* Cache RF register CHNLBW. */ 2941251538Srpaulo sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2942251538Srpaulo } 2943251538Srpaulo 2944251538Srpaulo if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2945251538Srpaulo URTWN_CHIP_UMC_A_CUT) { 2946251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2947251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2948251538Srpaulo } 2949251538Srpaulo} 2950251538Srpaulo 2951251538Srpaulostatic void 2952251538Srpaulourtwn_cam_init(struct urtwn_softc *sc) 2953251538Srpaulo{ 2954251538Srpaulo /* Invalidate all CAM entries. */ 2955251538Srpaulo urtwn_write_4(sc, R92C_CAMCMD, 2956251538Srpaulo R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2957251538Srpaulo} 2958251538Srpaulo 2959251538Srpaulostatic void 2960251538Srpaulourtwn_pa_bias_init(struct urtwn_softc *sc) 2961251538Srpaulo{ 2962251538Srpaulo uint8_t reg; 2963251538Srpaulo int i; 2964251538Srpaulo 2965251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2966251538Srpaulo if (sc->pa_setting & (1 << i)) 2967251538Srpaulo continue; 2968251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2969251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2970251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2971251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2972251538Srpaulo } 2973251538Srpaulo if (!(sc->pa_setting & 0x10)) { 2974251538Srpaulo reg = urtwn_read_1(sc, 0x16); 2975251538Srpaulo reg = (reg & ~0xf0) | 0x90; 2976251538Srpaulo urtwn_write_1(sc, 0x16, reg); 2977251538Srpaulo } 2978251538Srpaulo} 2979251538Srpaulo 2980251538Srpaulostatic void 2981251538Srpaulourtwn_rxfilter_init(struct urtwn_softc *sc) 2982251538Srpaulo{ 2983290564Savos struct ieee80211com *ic = &sc->sc_ic; 2984290564Savos struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2985290564Savos uint32_t rcr; 2986290564Savos uint16_t filter; 2987290564Savos 2988290564Savos URTWN_ASSERT_LOCKED(sc); 2989290564Savos 2990251538Srpaulo /* Accept all multicast frames. */ 2991251538Srpaulo urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2992251538Srpaulo urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2993290564Savos 2994290564Savos /* Filter for management frames. */ 2995290564Savos filter = 0x7f3f; 2996290631Savos switch (vap->iv_opmode) { 2997290631Savos case IEEE80211_M_STA: 2998290564Savos filter &= ~( 2999290564Savos R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 3000290564Savos R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 3001290564Savos R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 3002290631Savos break; 3003290631Savos case IEEE80211_M_HOSTAP: 3004290631Savos filter &= ~( 3005290631Savos R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_RESP) | 3006290631Savos R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_RESP) | 3007290631Savos R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_BEACON)); 3008290631Savos break; 3009290631Savos case IEEE80211_M_MONITOR: 3010290631Savos break; 3011290631Savos default: 3012290631Savos device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3013290631Savos __func__, vap->iv_opmode); 3014290631Savos break; 3015290564Savos } 3016290564Savos urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 3017290564Savos 3018251538Srpaulo /* Reject all control frames. */ 3019251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 3020290564Savos 3021290564Savos /* Reject all data frames. */ 3022290564Savos urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 3023290564Savos 3024290564Savos rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 3025290564Savos R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 3026290564Savos R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 3027290564Savos 3028290564Savos if (vap->iv_opmode == IEEE80211_M_MONITOR) { 3029290564Savos /* Accept all frames. */ 3030290564Savos rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 3031290564Savos R92C_RCR_AAP; 3032290564Savos } 3033290564Savos 3034290564Savos /* Set Rx filter. */ 3035290564Savos urtwn_write_4(sc, R92C_RCR, rcr); 3036290564Savos 3037290564Savos if (ic->ic_promisc != 0) { 3038290564Savos /* Update Rx filter. */ 3039290564Savos urtwn_set_promisc(sc); 3040290564Savos } 3041251538Srpaulo} 3042251538Srpaulo 3043251538Srpaulostatic void 3044251538Srpaulourtwn_edca_init(struct urtwn_softc *sc) 3045251538Srpaulo{ 3046251538Srpaulo urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 3047251538Srpaulo urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 3048251538Srpaulo urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 3049251538Srpaulo urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 3050251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 3051251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 3052251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 3053251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 3054251538Srpaulo} 3055251538Srpaulo 3056289066Skevlostatic void 3057251538Srpaulourtwn_write_txpower(struct urtwn_softc *sc, int chain, 3058251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 3059251538Srpaulo{ 3060251538Srpaulo uint32_t reg; 3061251538Srpaulo 3062251538Srpaulo /* Write per-CCK rate Tx power. */ 3063251538Srpaulo if (chain == 0) { 3064251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 3065251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 3066251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 3067251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3068251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 3069251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 3070251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 3071251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3072251538Srpaulo } else { 3073251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 3074251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 3075251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 3076251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 3077251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 3078251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 3079251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 3080251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 3081251538Srpaulo } 3082251538Srpaulo /* Write per-OFDM rate Tx power. */ 3083251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 3084251538Srpaulo SM(R92C_TXAGC_RATE06, power[ 4]) | 3085251538Srpaulo SM(R92C_TXAGC_RATE09, power[ 5]) | 3086251538Srpaulo SM(R92C_TXAGC_RATE12, power[ 6]) | 3087251538Srpaulo SM(R92C_TXAGC_RATE18, power[ 7])); 3088251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 3089251538Srpaulo SM(R92C_TXAGC_RATE24, power[ 8]) | 3090251538Srpaulo SM(R92C_TXAGC_RATE36, power[ 9]) | 3091251538Srpaulo SM(R92C_TXAGC_RATE48, power[10]) | 3092251538Srpaulo SM(R92C_TXAGC_RATE54, power[11])); 3093251538Srpaulo /* Write per-MCS Tx power. */ 3094251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 3095251538Srpaulo SM(R92C_TXAGC_MCS00, power[12]) | 3096251538Srpaulo SM(R92C_TXAGC_MCS01, power[13]) | 3097251538Srpaulo SM(R92C_TXAGC_MCS02, power[14]) | 3098251538Srpaulo SM(R92C_TXAGC_MCS03, power[15])); 3099251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 3100251538Srpaulo SM(R92C_TXAGC_MCS04, power[16]) | 3101251538Srpaulo SM(R92C_TXAGC_MCS05, power[17]) | 3102251538Srpaulo SM(R92C_TXAGC_MCS06, power[18]) | 3103251538Srpaulo SM(R92C_TXAGC_MCS07, power[19])); 3104251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 3105251538Srpaulo SM(R92C_TXAGC_MCS08, power[20]) | 3106261506Skevlo SM(R92C_TXAGC_MCS09, power[21]) | 3107251538Srpaulo SM(R92C_TXAGC_MCS10, power[22]) | 3108251538Srpaulo SM(R92C_TXAGC_MCS11, power[23])); 3109251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 3110251538Srpaulo SM(R92C_TXAGC_MCS12, power[24]) | 3111251538Srpaulo SM(R92C_TXAGC_MCS13, power[25]) | 3112251538Srpaulo SM(R92C_TXAGC_MCS14, power[26]) | 3113251538Srpaulo SM(R92C_TXAGC_MCS15, power[27])); 3114251538Srpaulo} 3115251538Srpaulo 3116289066Skevlostatic void 3117251538Srpaulourtwn_get_txpower(struct urtwn_softc *sc, int chain, 3118251538Srpaulo struct ieee80211_channel *c, struct ieee80211_channel *extc, 3119251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 3120251538Srpaulo{ 3121287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3122251538Srpaulo struct r92c_rom *rom = &sc->rom; 3123251538Srpaulo uint16_t cckpow, ofdmpow, htpow, diff, max; 3124251538Srpaulo const struct urtwn_txpwr *base; 3125251538Srpaulo int ridx, chan, group; 3126251538Srpaulo 3127251538Srpaulo /* Determine channel group. */ 3128251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3129251538Srpaulo if (chan <= 3) 3130251538Srpaulo group = 0; 3131251538Srpaulo else if (chan <= 9) 3132251538Srpaulo group = 1; 3133251538Srpaulo else 3134251538Srpaulo group = 2; 3135251538Srpaulo 3136251538Srpaulo /* Get original Tx power based on board type and RF chain. */ 3137251538Srpaulo if (!(sc->chip & URTWN_CHIP_92C)) { 3138251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3139251538Srpaulo base = &rtl8188ru_txagc[chain]; 3140251538Srpaulo else 3141251538Srpaulo base = &rtl8192cu_txagc[chain]; 3142251538Srpaulo } else 3143251538Srpaulo base = &rtl8192cu_txagc[chain]; 3144251538Srpaulo 3145251538Srpaulo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3146251538Srpaulo if (sc->regulatory == 0) { 3147289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3148251538Srpaulo power[ridx] = base->pwr[0][ridx]; 3149251538Srpaulo } 3150289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3151251538Srpaulo if (sc->regulatory == 3) { 3152251538Srpaulo power[ridx] = base->pwr[0][ridx]; 3153251538Srpaulo /* Apply vendor limits. */ 3154251538Srpaulo if (extc != NULL) 3155251538Srpaulo max = rom->ht40_max_pwr[group]; 3156251538Srpaulo else 3157251538Srpaulo max = rom->ht20_max_pwr[group]; 3158251538Srpaulo max = (max >> (chain * 4)) & 0xf; 3159251538Srpaulo if (power[ridx] > max) 3160251538Srpaulo power[ridx] = max; 3161251538Srpaulo } else if (sc->regulatory == 1) { 3162251538Srpaulo if (extc == NULL) 3163251538Srpaulo power[ridx] = base->pwr[group][ridx]; 3164251538Srpaulo } else if (sc->regulatory != 2) 3165251538Srpaulo power[ridx] = base->pwr[0][ridx]; 3166251538Srpaulo } 3167251538Srpaulo 3168251538Srpaulo /* Compute per-CCK rate Tx power. */ 3169251538Srpaulo cckpow = rom->cck_tx_pwr[chain][group]; 3170289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3171251538Srpaulo power[ridx] += cckpow; 3172251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 3173251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 3174251538Srpaulo } 3175251538Srpaulo 3176251538Srpaulo htpow = rom->ht40_1s_tx_pwr[chain][group]; 3177251538Srpaulo if (sc->ntxchains > 1) { 3178251538Srpaulo /* Apply reduction for 2 spatial streams. */ 3179251538Srpaulo diff = rom->ht40_2s_tx_pwr_diff[group]; 3180251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 3181251538Srpaulo htpow = (htpow > diff) ? htpow - diff : 0; 3182251538Srpaulo } 3183251538Srpaulo 3184251538Srpaulo /* Compute per-OFDM rate Tx power. */ 3185251538Srpaulo diff = rom->ofdm_tx_pwr_diff[group]; 3186251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 3187251538Srpaulo ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3188289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3189251538Srpaulo power[ridx] += ofdmpow; 3190251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 3191251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 3192251538Srpaulo } 3193251538Srpaulo 3194251538Srpaulo /* Compute per-MCS Tx power. */ 3195251538Srpaulo if (extc == NULL) { 3196251538Srpaulo diff = rom->ht20_tx_pwr_diff[group]; 3197251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 3198251538Srpaulo htpow += diff; /* HT40->HT20 correction. */ 3199251538Srpaulo } 3200251538Srpaulo for (ridx = 12; ridx <= 27; ridx++) { 3201251538Srpaulo power[ridx] += htpow; 3202251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 3203251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 3204251538Srpaulo } 3205251538Srpaulo#ifdef URTWN_DEBUG 3206251538Srpaulo if (urtwn_debug >= 4) { 3207251538Srpaulo /* Dump per-rate Tx power values. */ 3208251538Srpaulo printf("Tx power for chain %d:\n", chain); 3209289758Savos for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 3210251538Srpaulo printf("Rate %d = %u\n", ridx, power[ridx]); 3211251538Srpaulo } 3212251538Srpaulo#endif 3213251538Srpaulo} 3214251538Srpaulo 3215289066Skevlostatic void 3216264912Skevlourtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3217264912Skevlo struct ieee80211_channel *c, struct ieee80211_channel *extc, 3218264912Skevlo uint16_t power[URTWN_RIDX_COUNT]) 3219264912Skevlo{ 3220287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3221264912Skevlo uint16_t cckpow, ofdmpow, bw20pow, htpow; 3222264912Skevlo const struct urtwn_r88e_txpwr *base; 3223264912Skevlo int ridx, chan, group; 3224264912Skevlo 3225264912Skevlo /* Determine channel group. */ 3226264912Skevlo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3227264912Skevlo if (chan <= 2) 3228264912Skevlo group = 0; 3229264912Skevlo else if (chan <= 5) 3230264912Skevlo group = 1; 3231264912Skevlo else if (chan <= 8) 3232264912Skevlo group = 2; 3233264912Skevlo else if (chan <= 11) 3234264912Skevlo group = 3; 3235264912Skevlo else if (chan <= 13) 3236264912Skevlo group = 4; 3237264912Skevlo else 3238264912Skevlo group = 5; 3239264912Skevlo 3240264912Skevlo /* Get original Tx power based on board type and RF chain. */ 3241264912Skevlo base = &rtl8188eu_txagc[chain]; 3242264912Skevlo 3243264912Skevlo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3244264912Skevlo if (sc->regulatory == 0) { 3245289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3246264912Skevlo power[ridx] = base->pwr[0][ridx]; 3247264912Skevlo } 3248289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3249264912Skevlo if (sc->regulatory == 3) 3250264912Skevlo power[ridx] = base->pwr[0][ridx]; 3251264912Skevlo else if (sc->regulatory == 1) { 3252264912Skevlo if (extc == NULL) 3253264912Skevlo power[ridx] = base->pwr[group][ridx]; 3254264912Skevlo } else if (sc->regulatory != 2) 3255264912Skevlo power[ridx] = base->pwr[0][ridx]; 3256264912Skevlo } 3257264912Skevlo 3258264912Skevlo /* Compute per-CCK rate Tx power. */ 3259264912Skevlo cckpow = sc->cck_tx_pwr[group]; 3260289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3261264912Skevlo power[ridx] += cckpow; 3262264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3263264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3264264912Skevlo } 3265264912Skevlo 3266264912Skevlo htpow = sc->ht40_tx_pwr[group]; 3267264912Skevlo 3268264912Skevlo /* Compute per-OFDM rate Tx power. */ 3269264912Skevlo ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3270289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3271264912Skevlo power[ridx] += ofdmpow; 3272264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3273264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3274264912Skevlo } 3275264912Skevlo 3276264912Skevlo bw20pow = htpow + sc->bw20_tx_pwr_diff; 3277264912Skevlo for (ridx = 12; ridx <= 27; ridx++) { 3278264912Skevlo power[ridx] += bw20pow; 3279264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3280264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3281264912Skevlo } 3282264912Skevlo} 3283264912Skevlo 3284289066Skevlostatic void 3285251538Srpaulourtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3286251538Srpaulo struct ieee80211_channel *extc) 3287251538Srpaulo{ 3288251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]; 3289251538Srpaulo int i; 3290251538Srpaulo 3291251538Srpaulo for (i = 0; i < sc->ntxchains; i++) { 3292251538Srpaulo /* Compute per-rate Tx power values. */ 3293264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3294264912Skevlo urtwn_r88e_get_txpower(sc, i, c, extc, power); 3295264912Skevlo else 3296264912Skevlo urtwn_get_txpower(sc, i, c, extc, power); 3297251538Srpaulo /* Write per-rate Tx power values to hardware. */ 3298251538Srpaulo urtwn_write_txpower(sc, i, power); 3299251538Srpaulo } 3300251538Srpaulo} 3301251538Srpaulo 3302251538Srpaulostatic void 3303290048Savosurtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 3304290048Savos{ 3305290048Savos uint32_t reg; 3306290048Savos 3307290048Savos reg = urtwn_read_4(sc, R92C_RCR); 3308290048Savos if (enable) 3309290048Savos reg &= ~R92C_RCR_CBSSID_BCN; 3310290048Savos else 3311290048Savos reg |= R92C_RCR_CBSSID_BCN; 3312290048Savos urtwn_write_4(sc, R92C_RCR, reg); 3313290048Savos} 3314290048Savos 3315290048Savosstatic void 3316290048Savosurtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 3317290048Savos{ 3318290048Savos uint32_t reg; 3319290048Savos 3320290048Savos reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3321290048Savos reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3322290048Savos urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3323290048Savos 3324290048Savos if (!(sc->chip & URTWN_CHIP_88E)) { 3325290048Savos reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3326290048Savos reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3327290048Savos urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3328290048Savos } 3329290048Savos} 3330290048Savos 3331290048Savosstatic void 3332251538Srpaulourtwn_scan_start(struct ieee80211com *ic) 3333251538Srpaulo{ 3334290048Savos struct urtwn_softc *sc = ic->ic_softc; 3335290048Savos 3336290048Savos URTWN_LOCK(sc); 3337290048Savos /* Receive beacons / probe responses from any BSSID. */ 3338290048Savos urtwn_set_rx_bssid_all(sc, 1); 3339290048Savos /* Set gain for scanning. */ 3340290048Savos urtwn_set_gain(sc, 0x20); 3341290048Savos URTWN_UNLOCK(sc); 3342251538Srpaulo} 3343251538Srpaulo 3344251538Srpaulostatic void 3345251538Srpaulourtwn_scan_end(struct ieee80211com *ic) 3346251538Srpaulo{ 3347290048Savos struct urtwn_softc *sc = ic->ic_softc; 3348290048Savos 3349290048Savos URTWN_LOCK(sc); 3350290048Savos /* Restore limitations. */ 3351290564Savos if (ic->ic_promisc == 0) 3352290564Savos urtwn_set_rx_bssid_all(sc, 0); 3353290048Savos /* Set gain under link. */ 3354290048Savos urtwn_set_gain(sc, 0x32); 3355290048Savos URTWN_UNLOCK(sc); 3356251538Srpaulo} 3357251538Srpaulo 3358251538Srpaulostatic void 3359251538Srpaulourtwn_set_channel(struct ieee80211com *ic) 3360251538Srpaulo{ 3361286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 3362281070Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3363251538Srpaulo 3364251538Srpaulo URTWN_LOCK(sc); 3365281070Srpaulo if (vap->iv_state == IEEE80211_S_SCAN) { 3366281070Srpaulo /* Make link LED blink during scan. */ 3367281070Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3368281070Srpaulo } 3369251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 3370251538Srpaulo URTWN_UNLOCK(sc); 3371251538Srpaulo} 3372251538Srpaulo 3373251538Srpaulostatic void 3374290564Savosurtwn_set_promisc(struct urtwn_softc *sc) 3375290564Savos{ 3376290564Savos struct ieee80211com *ic = &sc->sc_ic; 3377290564Savos struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3378290564Savos uint32_t rcr, mask1, mask2; 3379290564Savos 3380290564Savos URTWN_ASSERT_LOCKED(sc); 3381290564Savos 3382290564Savos if (vap->iv_opmode == IEEE80211_M_MONITOR) 3383290564Savos return; 3384290564Savos 3385290564Savos mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 3386290564Savos mask2 = R92C_RCR_APM; 3387290564Savos 3388290564Savos if (vap->iv_state == IEEE80211_S_RUN) { 3389290564Savos switch (vap->iv_opmode) { 3390290564Savos case IEEE80211_M_STA: 3391290631Savos mask2 |= R92C_RCR_CBSSID_DATA; 3392290631Savos /* FALLTHROUGH */ 3393290631Savos case IEEE80211_M_HOSTAP: 3394290631Savos mask2 |= R92C_RCR_CBSSID_BCN; 3395290564Savos break; 3396290564Savos default: 3397290564Savos device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3398290564Savos __func__, vap->iv_opmode); 3399290564Savos return; 3400290564Savos } 3401290564Savos } 3402290564Savos 3403290564Savos rcr = urtwn_read_4(sc, R92C_RCR); 3404290564Savos if (ic->ic_promisc == 0) 3405290564Savos rcr = (rcr & ~mask1) | mask2; 3406290564Savos else 3407290564Savos rcr = (rcr & ~mask2) | mask1; 3408290564Savos urtwn_write_4(sc, R92C_RCR, rcr); 3409290564Savos} 3410290564Savos 3411290564Savosstatic void 3412290564Savosurtwn_update_promisc(struct ieee80211com *ic) 3413290564Savos{ 3414290564Savos struct urtwn_softc *sc = ic->ic_softc; 3415290564Savos 3416290564Savos URTWN_LOCK(sc); 3417290564Savos if (sc->sc_flags & URTWN_RUNNING) 3418290564Savos urtwn_set_promisc(sc); 3419290564Savos URTWN_UNLOCK(sc); 3420290564Savos} 3421290564Savos 3422290564Savosstatic void 3423283540Sglebiusurtwn_update_mcast(struct ieee80211com *ic) 3424251538Srpaulo{ 3425251538Srpaulo /* XXX do nothing? */ 3426251538Srpaulo} 3427251538Srpaulo 3428251538Srpaulostatic void 3429251538Srpaulourtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3430251538Srpaulo struct ieee80211_channel *extc) 3431251538Srpaulo{ 3432287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3433251538Srpaulo uint32_t reg; 3434251538Srpaulo u_int chan; 3435251538Srpaulo int i; 3436251538Srpaulo 3437251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3438251538Srpaulo if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3439251538Srpaulo device_printf(sc->sc_dev, 3440251538Srpaulo "%s: invalid channel %x\n", __func__, chan); 3441251538Srpaulo return; 3442251538Srpaulo } 3443251538Srpaulo 3444251538Srpaulo /* Set Tx power for this new channel. */ 3445251538Srpaulo urtwn_set_txpower(sc, c, extc); 3446251538Srpaulo 3447251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3448251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3449251538Srpaulo RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3450251538Srpaulo } 3451251538Srpaulo#ifndef IEEE80211_NO_HT 3452251538Srpaulo if (extc != NULL) { 3453251538Srpaulo /* Is secondary channel below or above primary? */ 3454251538Srpaulo int prichlo = c->ic_freq < extc->ic_freq; 3455251538Srpaulo 3456251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3457251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3458251538Srpaulo 3459251538Srpaulo reg = urtwn_read_1(sc, R92C_RRSR + 2); 3460251538Srpaulo reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3461251538Srpaulo urtwn_write_1(sc, R92C_RRSR + 2, reg); 3462251538Srpaulo 3463251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3464251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3465251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3466251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3467251538Srpaulo 3468251538Srpaulo /* Set CCK side band. */ 3469251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3470251538Srpaulo reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3471251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3472251538Srpaulo 3473251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3474251538Srpaulo reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3475251538Srpaulo urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3476251538Srpaulo 3477251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3478251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3479251538Srpaulo ~R92C_FPGA0_ANAPARAM2_CBW20); 3480251538Srpaulo 3481251538Srpaulo reg = urtwn_bb_read(sc, 0x818); 3482251538Srpaulo reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3483251538Srpaulo urtwn_bb_write(sc, 0x818, reg); 3484251538Srpaulo 3485251538Srpaulo /* Select 40MHz bandwidth. */ 3486251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3487251538Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan); 3488251538Srpaulo } else 3489251538Srpaulo#endif 3490251538Srpaulo { 3491251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3492251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3493251538Srpaulo 3494251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3495251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3496251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3497251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3498251538Srpaulo 3499264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3500264912Skevlo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3501264912Skevlo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3502264912Skevlo R92C_FPGA0_ANAPARAM2_CBW20); 3503264912Skevlo } 3504281069Srpaulo 3505251538Srpaulo /* Select 20MHz bandwidth. */ 3506251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3507281069Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan | 3508264912Skevlo ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3509264912Skevlo R92C_RF_CHNLBW_BW20)); 3510251538Srpaulo } 3511251538Srpaulo} 3512251538Srpaulo 3513251538Srpaulostatic void 3514251538Srpaulourtwn_iq_calib(struct urtwn_softc *sc) 3515251538Srpaulo{ 3516251538Srpaulo /* TODO */ 3517251538Srpaulo} 3518251538Srpaulo 3519251538Srpaulostatic void 3520251538Srpaulourtwn_lc_calib(struct urtwn_softc *sc) 3521251538Srpaulo{ 3522251538Srpaulo uint32_t rf_ac[2]; 3523251538Srpaulo uint8_t txmode; 3524251538Srpaulo int i; 3525251538Srpaulo 3526251538Srpaulo txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3527251538Srpaulo if ((txmode & 0x70) != 0) { 3528251538Srpaulo /* Disable all continuous Tx. */ 3529251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3530251538Srpaulo 3531251538Srpaulo /* Set RF mode to standby mode. */ 3532251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3533251538Srpaulo rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3534251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, 3535251538Srpaulo RW(rf_ac[i], R92C_RF_AC_MODE, 3536251538Srpaulo R92C_RF_AC_MODE_STANDBY)); 3537251538Srpaulo } 3538251538Srpaulo } else { 3539251538Srpaulo /* Block all Tx queues. */ 3540251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3541251538Srpaulo } 3542251538Srpaulo /* Start calibration. */ 3543251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3544251538Srpaulo urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3545251538Srpaulo 3546251538Srpaulo /* Give calibration the time to complete. */ 3547266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3548251538Srpaulo 3549251538Srpaulo /* Restore configuration. */ 3550251538Srpaulo if ((txmode & 0x70) != 0) { 3551251538Srpaulo /* Restore Tx mode. */ 3552251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3553251538Srpaulo /* Restore RF mode. */ 3554251538Srpaulo for (i = 0; i < sc->nrxchains; i++) 3555251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3556251538Srpaulo } else { 3557251538Srpaulo /* Unblock all Tx queues. */ 3558251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3559251538Srpaulo } 3560251538Srpaulo} 3561251538Srpaulo 3562251538Srpaulostatic void 3563287197Sglebiusurtwn_init(struct urtwn_softc *sc) 3564251538Srpaulo{ 3565287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3566287197Sglebius struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3567287197Sglebius uint8_t macaddr[IEEE80211_ADDR_LEN]; 3568251538Srpaulo uint32_t reg; 3569251538Srpaulo int error; 3570251538Srpaulo 3571264864Skevlo URTWN_ASSERT_LOCKED(sc); 3572264864Skevlo 3573287197Sglebius if (sc->sc_flags & URTWN_RUNNING) 3574287197Sglebius urtwn_stop(sc); 3575251538Srpaulo 3576251538Srpaulo /* Init firmware commands ring. */ 3577251538Srpaulo sc->fwcur = 0; 3578251538Srpaulo 3579251538Srpaulo /* Allocate Tx/Rx buffers. */ 3580251538Srpaulo error = urtwn_alloc_rx_list(sc); 3581251538Srpaulo if (error != 0) 3582251538Srpaulo goto fail; 3583281069Srpaulo 3584251538Srpaulo error = urtwn_alloc_tx_list(sc); 3585251538Srpaulo if (error != 0) 3586251538Srpaulo goto fail; 3587251538Srpaulo 3588251538Srpaulo /* Power on adapter. */ 3589251538Srpaulo error = urtwn_power_on(sc); 3590251538Srpaulo if (error != 0) 3591251538Srpaulo goto fail; 3592251538Srpaulo 3593251538Srpaulo /* Initialize DMA. */ 3594251538Srpaulo error = urtwn_dma_init(sc); 3595251538Srpaulo if (error != 0) 3596251538Srpaulo goto fail; 3597251538Srpaulo 3598251538Srpaulo /* Set info size in Rx descriptors (in 64-bit words). */ 3599251538Srpaulo urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3600251538Srpaulo 3601251538Srpaulo /* Init interrupts. */ 3602264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3603264912Skevlo urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3604264912Skevlo urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3605264912Skevlo R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3606264912Skevlo urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3607264912Skevlo R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3608264912Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3609264912Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3610264912Skevlo R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3611264912Skevlo } else { 3612264912Skevlo urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3613264912Skevlo urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3614264912Skevlo } 3615251538Srpaulo 3616251538Srpaulo /* Set MAC address. */ 3617287197Sglebius IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3618287197Sglebius urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3619251538Srpaulo 3620251538Srpaulo /* Set initial network type. */ 3621289811Savos urtwn_set_mode(sc, R92C_MSR_INFRA); 3622251538Srpaulo 3623290564Savos /* Initialize Rx filter. */ 3624251538Srpaulo urtwn_rxfilter_init(sc); 3625251538Srpaulo 3626282623Skevlo /* Set response rate. */ 3627251538Srpaulo reg = urtwn_read_4(sc, R92C_RRSR); 3628251538Srpaulo reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3629251538Srpaulo urtwn_write_4(sc, R92C_RRSR, reg); 3630251538Srpaulo 3631251538Srpaulo /* Set short/long retry limits. */ 3632251538Srpaulo urtwn_write_2(sc, R92C_RL, 3633251538Srpaulo SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3634251538Srpaulo 3635251538Srpaulo /* Initialize EDCA parameters. */ 3636251538Srpaulo urtwn_edca_init(sc); 3637251538Srpaulo 3638251538Srpaulo /* Setup rate fallback. */ 3639264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3640264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3641264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3642264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3643264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3644264912Skevlo } 3645251538Srpaulo 3646251538Srpaulo urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3647251538Srpaulo urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3648251538Srpaulo R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3649251538Srpaulo /* Set ACK timeout. */ 3650251538Srpaulo urtwn_write_1(sc, R92C_ACKTO, 0x40); 3651251538Srpaulo 3652251538Srpaulo /* Setup USB aggregation. */ 3653251538Srpaulo reg = urtwn_read_4(sc, R92C_TDECTRL); 3654251538Srpaulo reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3655251538Srpaulo urtwn_write_4(sc, R92C_TDECTRL, reg); 3656251538Srpaulo urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3657251538Srpaulo urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3658251538Srpaulo R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3659251538Srpaulo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3660264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3661264912Skevlo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3662282266Skevlo else { 3663264912Skevlo urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3664282266Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3665282266Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3666282266Skevlo R92C_USB_SPECIAL_OPTION_AGG_EN); 3667282266Skevlo urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3668282266Skevlo urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3669282266Skevlo } 3670251538Srpaulo 3671251538Srpaulo /* Initialize beacon parameters. */ 3672264912Skevlo urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3673251538Srpaulo urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3674251538Srpaulo urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3675251538Srpaulo urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3676251538Srpaulo urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3677251538Srpaulo 3678264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3679264912Skevlo /* Setup AMPDU aggregation. */ 3680264912Skevlo urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3681264912Skevlo urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3682264912Skevlo urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3683251538Srpaulo 3684264912Skevlo urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3685264912Skevlo } 3686251538Srpaulo 3687251538Srpaulo /* Load 8051 microcode. */ 3688251538Srpaulo error = urtwn_load_firmware(sc); 3689251538Srpaulo if (error != 0) 3690251538Srpaulo goto fail; 3691251538Srpaulo 3692251538Srpaulo /* Initialize MAC/BB/RF blocks. */ 3693251538Srpaulo urtwn_mac_init(sc); 3694251538Srpaulo urtwn_bb_init(sc); 3695251538Srpaulo urtwn_rf_init(sc); 3696251538Srpaulo 3697290564Savos /* Reinitialize Rx filter (D3845 is not committed yet). */ 3698290564Savos urtwn_rxfilter_init(sc); 3699290564Savos 3700264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3701264912Skevlo urtwn_write_2(sc, R92C_CR, 3702264912Skevlo urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3703264912Skevlo R92C_CR_MACRXEN); 3704264912Skevlo } 3705264912Skevlo 3706251538Srpaulo /* Turn CCK and OFDM blocks on. */ 3707251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3708251538Srpaulo reg |= R92C_RFMOD_CCK_EN; 3709251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3710251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3711251538Srpaulo reg |= R92C_RFMOD_OFDM_EN; 3712251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3713251538Srpaulo 3714251538Srpaulo /* Clear per-station keys table. */ 3715251538Srpaulo urtwn_cam_init(sc); 3716251538Srpaulo 3717251538Srpaulo /* Enable hardware sequence numbering. */ 3718251538Srpaulo urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3719251538Srpaulo 3720251538Srpaulo /* Perform LO and IQ calibrations. */ 3721251538Srpaulo urtwn_iq_calib(sc); 3722251538Srpaulo /* Perform LC calibration. */ 3723251538Srpaulo urtwn_lc_calib(sc); 3724251538Srpaulo 3725251538Srpaulo /* Fix USB interference issue. */ 3726264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3727264912Skevlo urtwn_write_1(sc, 0xfe40, 0xe0); 3728264912Skevlo urtwn_write_1(sc, 0xfe41, 0x8d); 3729264912Skevlo urtwn_write_1(sc, 0xfe42, 0x80); 3730251538Srpaulo 3731264912Skevlo urtwn_pa_bias_init(sc); 3732264912Skevlo } 3733251538Srpaulo 3734251538Srpaulo /* Initialize GPIO setting. */ 3735251538Srpaulo urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3736251538Srpaulo urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3737251538Srpaulo 3738251538Srpaulo /* Fix for lower temperature. */ 3739264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 3740264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 3741251538Srpaulo 3742251538Srpaulo usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3743251538Srpaulo 3744287197Sglebius sc->sc_flags |= URTWN_RUNNING; 3745251538Srpaulo 3746251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3747251538Srpaulofail: 3748251538Srpaulo return; 3749251538Srpaulo} 3750251538Srpaulo 3751251538Srpaulostatic void 3752287197Sglebiusurtwn_stop(struct urtwn_softc *sc) 3753251538Srpaulo{ 3754251538Srpaulo 3755264864Skevlo URTWN_ASSERT_LOCKED(sc); 3756287197Sglebius sc->sc_flags &= ~URTWN_RUNNING; 3757251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 3758251538Srpaulo urtwn_abort_xfers(sc); 3759288353Sadrian 3760288353Sadrian urtwn_drain_mbufq(sc); 3761251538Srpaulo} 3762251538Srpaulo 3763251538Srpaulostatic void 3764251538Srpaulourtwn_abort_xfers(struct urtwn_softc *sc) 3765251538Srpaulo{ 3766251538Srpaulo int i; 3767251538Srpaulo 3768251538Srpaulo URTWN_ASSERT_LOCKED(sc); 3769251538Srpaulo 3770251538Srpaulo /* abort any pending transfers */ 3771251538Srpaulo for (i = 0; i < URTWN_N_TRANSFER; i++) 3772251538Srpaulo usbd_transfer_stop(sc->sc_xfer[i]); 3773251538Srpaulo} 3774251538Srpaulo 3775251538Srpaulostatic int 3776251538Srpaulourtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3777251538Srpaulo const struct ieee80211_bpf_params *params) 3778251538Srpaulo{ 3779251538Srpaulo struct ieee80211com *ic = ni->ni_ic; 3780286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 3781251538Srpaulo struct urtwn_data *bf; 3782290630Savos int error; 3783251538Srpaulo 3784251538Srpaulo /* prevent management frames from being sent if we're not ready */ 3785290630Savos URTWN_LOCK(sc); 3786287197Sglebius if (!(sc->sc_flags & URTWN_RUNNING)) { 3787290630Savos error = ENETDOWN; 3788290630Savos goto end; 3789251538Srpaulo } 3790290630Savos 3791251538Srpaulo bf = urtwn_getbuf(sc); 3792251538Srpaulo if (bf == NULL) { 3793290630Savos error = ENOBUFS; 3794290630Savos goto end; 3795251538Srpaulo } 3796251538Srpaulo 3797290630Savos if ((error = urtwn_tx_data(sc, ni, m, bf)) != 0) { 3798251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3799290630Savos goto end; 3800251538Srpaulo } 3801290630Savos 3802288353Sadrian sc->sc_txtimer = 5; 3803290630Savos callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3804290630Savos 3805290630Savosend: 3806290630Savos if (error != 0) 3807290630Savos m_freem(m); 3808290630Savos 3809251538Srpaulo URTWN_UNLOCK(sc); 3810251538Srpaulo 3811290630Savos return (error); 3812251538Srpaulo} 3813251538Srpaulo 3814266472Shselaskystatic void 3815266472Shselaskyurtwn_ms_delay(struct urtwn_softc *sc) 3816266472Shselasky{ 3817266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3818266472Shselasky} 3819266472Shselasky 3820251538Srpaulostatic device_method_t urtwn_methods[] = { 3821251538Srpaulo /* Device interface */ 3822251538Srpaulo DEVMETHOD(device_probe, urtwn_match), 3823251538Srpaulo DEVMETHOD(device_attach, urtwn_attach), 3824251538Srpaulo DEVMETHOD(device_detach, urtwn_detach), 3825251538Srpaulo 3826264912Skevlo DEVMETHOD_END 3827251538Srpaulo}; 3828251538Srpaulo 3829251538Srpaulostatic driver_t urtwn_driver = { 3830251538Srpaulo "urtwn", 3831251538Srpaulo urtwn_methods, 3832251538Srpaulo sizeof(struct urtwn_softc) 3833251538Srpaulo}; 3834251538Srpaulo 3835251538Srpaulostatic devclass_t urtwn_devclass; 3836251538Srpaulo 3837251538SrpauloDRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3838251538SrpauloMODULE_DEPEND(urtwn, usb, 1, 1, 1); 3839251538SrpauloMODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3840251538SrpauloMODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3841251538SrpauloMODULE_VERSION(urtwn, 1); 3842