if_urtwn.c revision 290564
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 290564 2015-11-08 23:21:54Z avos $"); 22 23/* 24 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25 */ 26 27#include "opt_wlan.h" 28 29#include <sys/param.h> 30#include <sys/sockio.h> 31#include <sys/sysctl.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/mbuf.h> 35#include <sys/kernel.h> 36#include <sys/socket.h> 37#include <sys/systm.h> 38#include <sys/malloc.h> 39#include <sys/module.h> 40#include <sys/bus.h> 41#include <sys/endian.h> 42#include <sys/linker.h> 43#include <sys/firmware.h> 44#include <sys/kdb.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48#include <sys/rman.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_var.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/in_var.h> 62#include <netinet/if_ether.h> 63#include <netinet/ip.h> 64 65#include <net80211/ieee80211_var.h> 66#include <net80211/ieee80211_input.h> 67#include <net80211/ieee80211_regdomain.h> 68#include <net80211/ieee80211_radiotap.h> 69#include <net80211/ieee80211_ratectl.h> 70 71#include <dev/usb/usb.h> 72#include <dev/usb/usbdi.h> 73#include "usbdevs.h" 74 75#define USB_DEBUG_VAR urtwn_debug 76#include <dev/usb/usb_debug.h> 77 78#include <dev/usb/wlan/if_urtwnreg.h> 79#include <dev/usb/wlan/if_urtwnvar.h> 80 81#ifdef USB_DEBUG 82static int urtwn_debug = 0; 83 84SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 85SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 86 "Debug level"); 87#endif 88 89#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 90 91/* various supported device vendors/products */ 92static const STRUCT_USB_HOST_ID urtwn_devs[] = { 93#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 94#define URTWN_RTL8188E_DEV(v,p) \ 95 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 96#define URTWN_RTL8188E 1 97 URTWN_DEV(ABOCOM, RTL8188CU_1), 98 URTWN_DEV(ABOCOM, RTL8188CU_2), 99 URTWN_DEV(ABOCOM, RTL8192CU), 100 URTWN_DEV(ASUS, RTL8192CU), 101 URTWN_DEV(ASUS, USBN10NANO), 102 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 103 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 104 URTWN_DEV(AZUREWAVE, RTL8188CU), 105 URTWN_DEV(BELKIN, F7D2102), 106 URTWN_DEV(BELKIN, RTL8188CU), 107 URTWN_DEV(BELKIN, RTL8192CU), 108 URTWN_DEV(CHICONY, RTL8188CUS_1), 109 URTWN_DEV(CHICONY, RTL8188CUS_2), 110 URTWN_DEV(CHICONY, RTL8188CUS_3), 111 URTWN_DEV(CHICONY, RTL8188CUS_4), 112 URTWN_DEV(CHICONY, RTL8188CUS_5), 113 URTWN_DEV(COREGA, RTL8192CU), 114 URTWN_DEV(DLINK, RTL8188CU), 115 URTWN_DEV(DLINK, RTL8192CU_1), 116 URTWN_DEV(DLINK, RTL8192CU_2), 117 URTWN_DEV(DLINK, RTL8192CU_3), 118 URTWN_DEV(DLINK, DWA131B), 119 URTWN_DEV(EDIMAX, EW7811UN), 120 URTWN_DEV(EDIMAX, RTL8192CU), 121 URTWN_DEV(FEIXUN, RTL8188CU), 122 URTWN_DEV(FEIXUN, RTL8192CU), 123 URTWN_DEV(GUILLEMOT, HWNUP150), 124 URTWN_DEV(HAWKING, RTL8192CU), 125 URTWN_DEV(HP3, RTL8188CU), 126 URTWN_DEV(NETGEAR, WNA1000M), 127 URTWN_DEV(NETGEAR, RTL8192CU), 128 URTWN_DEV(NETGEAR4, RTL8188CU), 129 URTWN_DEV(NOVATECH, RTL8188CU), 130 URTWN_DEV(PLANEX2, RTL8188CU_1), 131 URTWN_DEV(PLANEX2, RTL8188CU_2), 132 URTWN_DEV(PLANEX2, RTL8188CU_3), 133 URTWN_DEV(PLANEX2, RTL8188CU_4), 134 URTWN_DEV(PLANEX2, RTL8188CUS), 135 URTWN_DEV(PLANEX2, RTL8192CU), 136 URTWN_DEV(REALTEK, RTL8188CE_0), 137 URTWN_DEV(REALTEK, RTL8188CE_1), 138 URTWN_DEV(REALTEK, RTL8188CTV), 139 URTWN_DEV(REALTEK, RTL8188CU_0), 140 URTWN_DEV(REALTEK, RTL8188CU_1), 141 URTWN_DEV(REALTEK, RTL8188CU_2), 142 URTWN_DEV(REALTEK, RTL8188CU_3), 143 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 144 URTWN_DEV(REALTEK, RTL8188CUS), 145 URTWN_DEV(REALTEK, RTL8188RU_1), 146 URTWN_DEV(REALTEK, RTL8188RU_2), 147 URTWN_DEV(REALTEK, RTL8188RU_3), 148 URTWN_DEV(REALTEK, RTL8191CU), 149 URTWN_DEV(REALTEK, RTL8192CE), 150 URTWN_DEV(REALTEK, RTL8192CU), 151 URTWN_DEV(SITECOMEU, RTL8188CU_1), 152 URTWN_DEV(SITECOMEU, RTL8188CU_2), 153 URTWN_DEV(SITECOMEU, RTL8192CU), 154 URTWN_DEV(TRENDNET, RTL8188CU), 155 URTWN_DEV(TRENDNET, RTL8192CU), 156 URTWN_DEV(ZYXEL, RTL8192CU), 157 /* URTWN_RTL8188E */ 158 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 159 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 160 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 161 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 162 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 163#undef URTWN_RTL8188E_DEV 164#undef URTWN_DEV 165}; 166 167static device_probe_t urtwn_match; 168static device_attach_t urtwn_attach; 169static device_detach_t urtwn_detach; 170 171static usb_callback_t urtwn_bulk_tx_callback; 172static usb_callback_t urtwn_bulk_rx_callback; 173 174static void urtwn_drain_mbufq(struct urtwn_softc *sc); 175static usb_error_t urtwn_do_request(struct urtwn_softc *, 176 struct usb_device_request *, void *); 177static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 178 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 179 const uint8_t [IEEE80211_ADDR_LEN], 180 const uint8_t [IEEE80211_ADDR_LEN]); 181static void urtwn_vap_delete(struct ieee80211vap *); 182static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 183 int *); 184static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 185 int *, int8_t *); 186static void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 187 int); 188static int urtwn_alloc_list(struct urtwn_softc *, 189 struct urtwn_data[], int, int); 190static int urtwn_alloc_rx_list(struct urtwn_softc *); 191static int urtwn_alloc_tx_list(struct urtwn_softc *); 192static void urtwn_free_list(struct urtwn_softc *, 193 struct urtwn_data data[], int); 194static void urtwn_free_rx_list(struct urtwn_softc *); 195static void urtwn_free_tx_list(struct urtwn_softc *); 196static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 197static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 198static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 199 uint8_t *, int); 200static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 201static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 202static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 203static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 204 uint8_t *, int); 205static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 206static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 207static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 208static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 209 const void *, int); 210static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 211 uint8_t, uint32_t); 212static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 213 uint8_t, uint32_t); 214static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 215static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 216 uint32_t); 217static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 218static void urtwn_efuse_read(struct urtwn_softc *); 219static void urtwn_efuse_switch_power(struct urtwn_softc *); 220static int urtwn_read_chipid(struct urtwn_softc *); 221static void urtwn_read_rom(struct urtwn_softc *); 222static void urtwn_r88e_read_rom(struct urtwn_softc *); 223static int urtwn_ra_init(struct urtwn_softc *); 224static void urtwn_tsf_sync_enable(struct urtwn_softc *); 225static void urtwn_set_led(struct urtwn_softc *, int, int); 226static void urtwn_set_mode(struct urtwn_softc *, uint8_t); 227static int urtwn_newstate(struct ieee80211vap *, 228 enum ieee80211_state, int); 229static void urtwn_watchdog(void *); 230static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 231static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 232static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 233static int urtwn_tx_start(struct urtwn_softc *, 234 struct ieee80211_node *, struct mbuf *, 235 struct urtwn_data *); 236static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 237static void urtwn_start(struct urtwn_softc *); 238static void urtwn_parent(struct ieee80211com *); 239static int urtwn_r92c_power_on(struct urtwn_softc *); 240static int urtwn_r88e_power_on(struct urtwn_softc *); 241static int urtwn_llt_init(struct urtwn_softc *); 242static void urtwn_fw_reset(struct urtwn_softc *); 243static void urtwn_r88e_fw_reset(struct urtwn_softc *); 244static int urtwn_fw_loadpage(struct urtwn_softc *, int, 245 const uint8_t *, int); 246static int urtwn_load_firmware(struct urtwn_softc *); 247static int urtwn_r92c_dma_init(struct urtwn_softc *); 248static int urtwn_r88e_dma_init(struct urtwn_softc *); 249static void urtwn_mac_init(struct urtwn_softc *); 250static void urtwn_bb_init(struct urtwn_softc *); 251static void urtwn_rf_init(struct urtwn_softc *); 252static void urtwn_cam_init(struct urtwn_softc *); 253static void urtwn_pa_bias_init(struct urtwn_softc *); 254static void urtwn_rxfilter_init(struct urtwn_softc *); 255static void urtwn_edca_init(struct urtwn_softc *); 256static void urtwn_write_txpower(struct urtwn_softc *, int, 257 uint16_t[]); 258static void urtwn_get_txpower(struct urtwn_softc *, int, 259 struct ieee80211_channel *, 260 struct ieee80211_channel *, uint16_t[]); 261static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 262 struct ieee80211_channel *, 263 struct ieee80211_channel *, uint16_t[]); 264static void urtwn_set_txpower(struct urtwn_softc *, 265 struct ieee80211_channel *, 266 struct ieee80211_channel *); 267static void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 268static void urtwn_set_gain(struct urtwn_softc *, uint8_t); 269static void urtwn_scan_start(struct ieee80211com *); 270static void urtwn_scan_end(struct ieee80211com *); 271static void urtwn_set_channel(struct ieee80211com *); 272static void urtwn_set_promisc(struct urtwn_softc *); 273static void urtwn_update_promisc(struct ieee80211com *); 274static void urtwn_update_mcast(struct ieee80211com *); 275static void urtwn_set_chan(struct urtwn_softc *, 276 struct ieee80211_channel *, 277 struct ieee80211_channel *); 278static void urtwn_iq_calib(struct urtwn_softc *); 279static void urtwn_lc_calib(struct urtwn_softc *); 280static void urtwn_init(struct urtwn_softc *); 281static void urtwn_stop(struct urtwn_softc *); 282static void urtwn_abort_xfers(struct urtwn_softc *); 283static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 284 const struct ieee80211_bpf_params *); 285static void urtwn_ms_delay(struct urtwn_softc *); 286 287/* Aliases. */ 288#define urtwn_bb_write urtwn_write_4 289#define urtwn_bb_read urtwn_read_4 290 291static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 292 [URTWN_BULK_RX] = { 293 .type = UE_BULK, 294 .endpoint = UE_ADDR_ANY, 295 .direction = UE_DIR_IN, 296 .bufsize = URTWN_RXBUFSZ, 297 .flags = { 298 .pipe_bof = 1, 299 .short_xfer_ok = 1 300 }, 301 .callback = urtwn_bulk_rx_callback, 302 }, 303 [URTWN_BULK_TX_BE] = { 304 .type = UE_BULK, 305 .endpoint = 0x03, 306 .direction = UE_DIR_OUT, 307 .bufsize = URTWN_TXBUFSZ, 308 .flags = { 309 .ext_buffer = 1, 310 .pipe_bof = 1, 311 .force_short_xfer = 1 312 }, 313 .callback = urtwn_bulk_tx_callback, 314 .timeout = URTWN_TX_TIMEOUT, /* ms */ 315 }, 316 [URTWN_BULK_TX_BK] = { 317 .type = UE_BULK, 318 .endpoint = 0x03, 319 .direction = UE_DIR_OUT, 320 .bufsize = URTWN_TXBUFSZ, 321 .flags = { 322 .ext_buffer = 1, 323 .pipe_bof = 1, 324 .force_short_xfer = 1, 325 }, 326 .callback = urtwn_bulk_tx_callback, 327 .timeout = URTWN_TX_TIMEOUT, /* ms */ 328 }, 329 [URTWN_BULK_TX_VI] = { 330 .type = UE_BULK, 331 .endpoint = 0x02, 332 .direction = UE_DIR_OUT, 333 .bufsize = URTWN_TXBUFSZ, 334 .flags = { 335 .ext_buffer = 1, 336 .pipe_bof = 1, 337 .force_short_xfer = 1 338 }, 339 .callback = urtwn_bulk_tx_callback, 340 .timeout = URTWN_TX_TIMEOUT, /* ms */ 341 }, 342 [URTWN_BULK_TX_VO] = { 343 .type = UE_BULK, 344 .endpoint = 0x02, 345 .direction = UE_DIR_OUT, 346 .bufsize = URTWN_TXBUFSZ, 347 .flags = { 348 .ext_buffer = 1, 349 .pipe_bof = 1, 350 .force_short_xfer = 1 351 }, 352 .callback = urtwn_bulk_tx_callback, 353 .timeout = URTWN_TX_TIMEOUT, /* ms */ 354 }, 355}; 356 357static int 358urtwn_match(device_t self) 359{ 360 struct usb_attach_arg *uaa = device_get_ivars(self); 361 362 if (uaa->usb_mode != USB_MODE_HOST) 363 return (ENXIO); 364 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 365 return (ENXIO); 366 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 367 return (ENXIO); 368 369 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 370} 371 372static int 373urtwn_attach(device_t self) 374{ 375 struct usb_attach_arg *uaa = device_get_ivars(self); 376 struct urtwn_softc *sc = device_get_softc(self); 377 struct ieee80211com *ic = &sc->sc_ic; 378 uint8_t iface_index, bands; 379 int error; 380 381 device_set_usb_desc(self); 382 sc->sc_udev = uaa->device; 383 sc->sc_dev = self; 384 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 385 sc->chip |= URTWN_CHIP_88E; 386 387 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 388 MTX_NETWORK_LOCK, MTX_DEF); 389 callout_init(&sc->sc_watchdog_ch, 0); 390 mbufq_init(&sc->sc_snd, ifqmaxlen); 391 392 iface_index = URTWN_IFACE_INDEX; 393 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 394 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 395 if (error) { 396 device_printf(self, "could not allocate USB transfers, " 397 "err=%s\n", usbd_errstr(error)); 398 goto detach; 399 } 400 401 URTWN_LOCK(sc); 402 403 error = urtwn_read_chipid(sc); 404 if (error) { 405 device_printf(sc->sc_dev, "unsupported test chip\n"); 406 URTWN_UNLOCK(sc); 407 goto detach; 408 } 409 410 /* Determine number of Tx/Rx chains. */ 411 if (sc->chip & URTWN_CHIP_92C) { 412 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 413 sc->nrxchains = 2; 414 } else { 415 sc->ntxchains = 1; 416 sc->nrxchains = 1; 417 } 418 419 if (sc->chip & URTWN_CHIP_88E) 420 urtwn_r88e_read_rom(sc); 421 else 422 urtwn_read_rom(sc); 423 424 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 425 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 426 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 427 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 428 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 429 "8188CUS", sc->ntxchains, sc->nrxchains); 430 431 URTWN_UNLOCK(sc); 432 433 ic->ic_softc = sc; 434 ic->ic_name = device_get_nameunit(self); 435 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 436 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 437 438 /* set device capabilities */ 439 ic->ic_caps = 440 IEEE80211_C_STA /* station mode */ 441 | IEEE80211_C_MONITOR /* monitor mode */ 442 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 443 | IEEE80211_C_SHSLOT /* short slot time supported */ 444 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 445 | IEEE80211_C_WPA /* 802.11i */ 446 ; 447 448 bands = 0; 449 setbit(&bands, IEEE80211_MODE_11B); 450 setbit(&bands, IEEE80211_MODE_11G); 451 ieee80211_init_channels(ic, NULL, &bands); 452 453 ieee80211_ifattach(ic); 454 ic->ic_raw_xmit = urtwn_raw_xmit; 455 ic->ic_scan_start = urtwn_scan_start; 456 ic->ic_scan_end = urtwn_scan_end; 457 ic->ic_set_channel = urtwn_set_channel; 458 ic->ic_transmit = urtwn_transmit; 459 ic->ic_parent = urtwn_parent; 460 ic->ic_vap_create = urtwn_vap_create; 461 ic->ic_vap_delete = urtwn_vap_delete; 462 ic->ic_update_promisc = urtwn_update_promisc; 463 ic->ic_update_mcast = urtwn_update_mcast; 464 465 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 466 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 467 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 468 URTWN_RX_RADIOTAP_PRESENT); 469 470 if (bootverbose) 471 ieee80211_announce(ic); 472 473 return (0); 474 475detach: 476 urtwn_detach(self); 477 return (ENXIO); /* failure */ 478} 479 480static int 481urtwn_detach(device_t self) 482{ 483 struct urtwn_softc *sc = device_get_softc(self); 484 struct ieee80211com *ic = &sc->sc_ic; 485 unsigned int x; 486 487 /* Prevent further ioctls. */ 488 URTWN_LOCK(sc); 489 sc->sc_flags |= URTWN_DETACHED; 490 urtwn_stop(sc); 491 URTWN_UNLOCK(sc); 492 493 callout_drain(&sc->sc_watchdog_ch); 494 495 /* stop all USB transfers */ 496 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 497 498 /* Prevent further allocations from RX/TX data lists. */ 499 URTWN_LOCK(sc); 500 STAILQ_INIT(&sc->sc_tx_active); 501 STAILQ_INIT(&sc->sc_tx_inactive); 502 STAILQ_INIT(&sc->sc_tx_pending); 503 504 STAILQ_INIT(&sc->sc_rx_active); 505 STAILQ_INIT(&sc->sc_rx_inactive); 506 URTWN_UNLOCK(sc); 507 508 /* drain USB transfers */ 509 for (x = 0; x != URTWN_N_TRANSFER; x++) 510 usbd_transfer_drain(sc->sc_xfer[x]); 511 512 /* Free data buffers. */ 513 URTWN_LOCK(sc); 514 urtwn_free_tx_list(sc); 515 urtwn_free_rx_list(sc); 516 URTWN_UNLOCK(sc); 517 518 ieee80211_ifdetach(ic); 519 mtx_destroy(&sc->sc_mtx); 520 521 return (0); 522} 523 524static void 525urtwn_drain_mbufq(struct urtwn_softc *sc) 526{ 527 struct mbuf *m; 528 struct ieee80211_node *ni; 529 URTWN_ASSERT_LOCKED(sc); 530 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 531 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 532 m->m_pkthdr.rcvif = NULL; 533 ieee80211_free_node(ni); 534 m_freem(m); 535 } 536} 537 538static usb_error_t 539urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 540 void *data) 541{ 542 usb_error_t err; 543 int ntries = 10; 544 545 URTWN_ASSERT_LOCKED(sc); 546 547 while (ntries--) { 548 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 549 req, data, 0, NULL, 250 /* ms */); 550 if (err == 0) 551 break; 552 553 DPRINTFN(1, "Control request failed, %s (retrying)\n", 554 usbd_errstr(err)); 555 usb_pause_mtx(&sc->sc_mtx, hz / 100); 556 } 557 return (err); 558} 559 560static struct ieee80211vap * 561urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 562 enum ieee80211_opmode opmode, int flags, 563 const uint8_t bssid[IEEE80211_ADDR_LEN], 564 const uint8_t mac[IEEE80211_ADDR_LEN]) 565{ 566 struct urtwn_vap *uvp; 567 struct ieee80211vap *vap; 568 569 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 570 return (NULL); 571 572 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 573 vap = &uvp->vap; 574 /* enable s/w bmiss handling for sta mode */ 575 576 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 577 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 578 /* out of memory */ 579 free(uvp, M_80211_VAP); 580 return (NULL); 581 } 582 583 /* override state transition machine */ 584 uvp->newstate = vap->iv_newstate; 585 vap->iv_newstate = urtwn_newstate; 586 587 /* complete setup */ 588 ieee80211_vap_attach(vap, ieee80211_media_change, 589 ieee80211_media_status, mac); 590 ic->ic_opmode = opmode; 591 return (vap); 592} 593 594static void 595urtwn_vap_delete(struct ieee80211vap *vap) 596{ 597 struct urtwn_vap *uvp = URTWN_VAP(vap); 598 599 ieee80211_vap_detach(vap); 600 free(uvp, M_80211_VAP); 601} 602 603static struct mbuf * 604urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 605{ 606 struct ieee80211com *ic = &sc->sc_ic; 607 struct ieee80211_frame *wh; 608 struct mbuf *m; 609 struct r92c_rx_stat *stat; 610 uint32_t rxdw0, rxdw3; 611 uint8_t rate; 612 int8_t rssi = 0; 613 int infosz; 614 615 /* 616 * don't pass packets to the ieee80211 framework if the driver isn't 617 * RUNNING. 618 */ 619 if (!(sc->sc_flags & URTWN_RUNNING)) 620 return (NULL); 621 622 stat = (struct r92c_rx_stat *)buf; 623 rxdw0 = le32toh(stat->rxdw0); 624 rxdw3 = le32toh(stat->rxdw3); 625 626 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 627 /* 628 * This should not happen since we setup our Rx filter 629 * to not receive these frames. 630 */ 631 counter_u64_add(ic->ic_ierrors, 1); 632 return (NULL); 633 } 634 if (pktlen < sizeof(struct ieee80211_frame_ack) || 635 pktlen > MCLBYTES) { 636 counter_u64_add(ic->ic_ierrors, 1); 637 return (NULL); 638 } 639 640 rate = MS(rxdw3, R92C_RXDW3_RATE); 641 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 642 643 /* Get RSSI from PHY status descriptor if present. */ 644 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 645 if (sc->chip & URTWN_CHIP_88E) 646 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 647 else 648 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 649 /* Update our average RSSI. */ 650 urtwn_update_avgrssi(sc, rate, rssi); 651 } 652 653 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 654 if (m == NULL) { 655 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 656 return (NULL); 657 } 658 659 /* Finalize mbuf. */ 660 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 661 memcpy(mtod(m, uint8_t *), wh, pktlen); 662 m->m_pkthdr.len = m->m_len = pktlen; 663 664 if (ieee80211_radiotap_active(ic)) { 665 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 666 667 tap->wr_flags = 0; 668 /* Map HW rate index to 802.11 rate. */ 669 if (!(rxdw3 & R92C_RXDW3_HT)) { 670 tap->wr_rate = ridx2rate[rate]; 671 } else if (rate >= 12) { /* MCS0~15. */ 672 /* Bit 7 set means HT MCS instead of rate. */ 673 tap->wr_rate = 0x80 | (rate - 12); 674 } 675 tap->wr_dbm_antsignal = rssi; 676 tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 677 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 678 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 679 } 680 681 *rssi_p = rssi; 682 683 return (m); 684} 685 686static struct mbuf * 687urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 688 int8_t *nf) 689{ 690 struct urtwn_softc *sc = data->sc; 691 struct ieee80211com *ic = &sc->sc_ic; 692 struct r92c_rx_stat *stat; 693 struct mbuf *m, *m0 = NULL, *prevm = NULL; 694 uint32_t rxdw0; 695 uint8_t *buf; 696 int len, totlen, pktlen, infosz, npkts; 697 698 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 699 700 if (len < sizeof(*stat)) { 701 counter_u64_add(ic->ic_ierrors, 1); 702 return (NULL); 703 } 704 705 buf = data->buf; 706 /* Get the number of encapsulated frames. */ 707 stat = (struct r92c_rx_stat *)buf; 708 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 709 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 710 711 /* Process all of them. */ 712 while (npkts-- > 0) { 713 if (len < sizeof(*stat)) 714 break; 715 stat = (struct r92c_rx_stat *)buf; 716 rxdw0 = le32toh(stat->rxdw0); 717 718 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 719 if (pktlen == 0) 720 break; 721 722 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 723 724 /* Make sure everything fits in xfer. */ 725 totlen = sizeof(*stat) + infosz + pktlen; 726 if (totlen > len) 727 break; 728 729 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 730 if (m0 == NULL) 731 m0 = m; 732 if (prevm == NULL) 733 prevm = m; 734 else { 735 prevm->m_next = m; 736 prevm = m; 737 } 738 739 /* Next chunk is 128-byte aligned. */ 740 totlen = (totlen + 127) & ~127; 741 buf += totlen; 742 len -= totlen; 743 } 744 745 return (m0); 746} 747 748static void 749urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 750{ 751 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 752 struct ieee80211com *ic = &sc->sc_ic; 753 struct ieee80211_frame_min *wh; 754 struct ieee80211_node *ni; 755 struct mbuf *m = NULL, *next; 756 struct urtwn_data *data; 757 int8_t nf; 758 int rssi = 1; 759 760 URTWN_ASSERT_LOCKED(sc); 761 762 switch (USB_GET_STATE(xfer)) { 763 case USB_ST_TRANSFERRED: 764 data = STAILQ_FIRST(&sc->sc_rx_active); 765 if (data == NULL) 766 goto tr_setup; 767 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 768 m = urtwn_rxeof(xfer, data, &rssi, &nf); 769 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 770 /* FALLTHROUGH */ 771 case USB_ST_SETUP: 772tr_setup: 773 data = STAILQ_FIRST(&sc->sc_rx_inactive); 774 if (data == NULL) { 775 KASSERT(m == NULL, ("mbuf isn't NULL")); 776 return; 777 } 778 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 779 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 780 usbd_xfer_set_frame_data(xfer, 0, data->buf, 781 usbd_xfer_max_len(xfer)); 782 usbd_transfer_submit(xfer); 783 784 /* 785 * To avoid LOR we should unlock our private mutex here to call 786 * ieee80211_input() because here is at the end of a USB 787 * callback and safe to unlock. 788 */ 789 URTWN_UNLOCK(sc); 790 while (m != NULL) { 791 next = m->m_next; 792 m->m_next = NULL; 793 wh = mtod(m, struct ieee80211_frame_min *); 794 if (m->m_len >= sizeof(*wh)) 795 ni = ieee80211_find_rxnode(ic, wh); 796 else 797 ni = NULL; 798 nf = URTWN_NOISE_FLOOR; 799 if (ni != NULL) { 800 (void)ieee80211_input(ni, m, rssi - nf, nf); 801 ieee80211_free_node(ni); 802 } else { 803 (void)ieee80211_input_all(ic, m, rssi - nf, 804 nf); 805 } 806 m = next; 807 } 808 URTWN_LOCK(sc); 809 break; 810 default: 811 /* needs it to the inactive queue due to a error. */ 812 data = STAILQ_FIRST(&sc->sc_rx_active); 813 if (data != NULL) { 814 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 815 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 816 } 817 if (error != USB_ERR_CANCELLED) { 818 usbd_xfer_set_stall(xfer); 819 counter_u64_add(ic->ic_ierrors, 1); 820 goto tr_setup; 821 } 822 break; 823 } 824} 825 826static void 827urtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 828{ 829 830 URTWN_ASSERT_LOCKED(sc); 831 832 ieee80211_tx_complete(data->ni, data->m, status); 833 834 data->ni = NULL; 835 data->m = NULL; 836 837 sc->sc_txtimer = 0; 838 839 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 840} 841 842static int 843urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 844 int ndata, int maxsz) 845{ 846 int i, error; 847 848 for (i = 0; i < ndata; i++) { 849 struct urtwn_data *dp = &data[i]; 850 dp->sc = sc; 851 dp->m = NULL; 852 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 853 if (dp->buf == NULL) { 854 device_printf(sc->sc_dev, 855 "could not allocate buffer\n"); 856 error = ENOMEM; 857 goto fail; 858 } 859 dp->ni = NULL; 860 } 861 862 return (0); 863fail: 864 urtwn_free_list(sc, data, ndata); 865 return (error); 866} 867 868static int 869urtwn_alloc_rx_list(struct urtwn_softc *sc) 870{ 871 int error, i; 872 873 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 874 URTWN_RXBUFSZ); 875 if (error != 0) 876 return (error); 877 878 STAILQ_INIT(&sc->sc_rx_active); 879 STAILQ_INIT(&sc->sc_rx_inactive); 880 881 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 882 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 883 884 return (0); 885} 886 887static int 888urtwn_alloc_tx_list(struct urtwn_softc *sc) 889{ 890 int error, i; 891 892 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 893 URTWN_TXBUFSZ); 894 if (error != 0) 895 return (error); 896 897 STAILQ_INIT(&sc->sc_tx_active); 898 STAILQ_INIT(&sc->sc_tx_inactive); 899 STAILQ_INIT(&sc->sc_tx_pending); 900 901 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 902 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 903 904 return (0); 905} 906 907static void 908urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 909{ 910 int i; 911 912 for (i = 0; i < ndata; i++) { 913 struct urtwn_data *dp = &data[i]; 914 915 if (dp->buf != NULL) { 916 free(dp->buf, M_USBDEV); 917 dp->buf = NULL; 918 } 919 if (dp->ni != NULL) { 920 ieee80211_free_node(dp->ni); 921 dp->ni = NULL; 922 } 923 } 924} 925 926static void 927urtwn_free_rx_list(struct urtwn_softc *sc) 928{ 929 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 930} 931 932static void 933urtwn_free_tx_list(struct urtwn_softc *sc) 934{ 935 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 936} 937 938static void 939urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 940{ 941 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 942 struct urtwn_data *data; 943 944 URTWN_ASSERT_LOCKED(sc); 945 946 switch (USB_GET_STATE(xfer)){ 947 case USB_ST_TRANSFERRED: 948 data = STAILQ_FIRST(&sc->sc_tx_active); 949 if (data == NULL) 950 goto tr_setup; 951 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 952 urtwn_txeof(sc, data, 0); 953 /* FALLTHROUGH */ 954 case USB_ST_SETUP: 955tr_setup: 956 data = STAILQ_FIRST(&sc->sc_tx_pending); 957 if (data == NULL) { 958 DPRINTF("%s: empty pending queue\n", __func__); 959 goto finish; 960 } 961 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 962 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 963 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 964 usbd_transfer_submit(xfer); 965 break; 966 default: 967 data = STAILQ_FIRST(&sc->sc_tx_active); 968 if (data == NULL) 969 goto tr_setup; 970 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 971 urtwn_txeof(sc, data, 1); 972 if (error != USB_ERR_CANCELLED) { 973 usbd_xfer_set_stall(xfer); 974 goto tr_setup; 975 } 976 break; 977 } 978finish: 979 /* Kick-start more transmit */ 980 urtwn_start(sc); 981} 982 983static struct urtwn_data * 984_urtwn_getbuf(struct urtwn_softc *sc) 985{ 986 struct urtwn_data *bf; 987 988 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 989 if (bf != NULL) 990 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 991 else 992 bf = NULL; 993 if (bf == NULL) 994 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 995 return (bf); 996} 997 998static struct urtwn_data * 999urtwn_getbuf(struct urtwn_softc *sc) 1000{ 1001 struct urtwn_data *bf; 1002 1003 URTWN_ASSERT_LOCKED(sc); 1004 1005 bf = _urtwn_getbuf(sc); 1006 if (bf == NULL) 1007 DPRINTF("%s: stop queue\n", __func__); 1008 return (bf); 1009} 1010 1011static int 1012urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1013 int len) 1014{ 1015 usb_device_request_t req; 1016 1017 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1018 req.bRequest = R92C_REQ_REGS; 1019 USETW(req.wValue, addr); 1020 USETW(req.wIndex, 0); 1021 USETW(req.wLength, len); 1022 return (urtwn_do_request(sc, &req, buf)); 1023} 1024 1025static void 1026urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1027{ 1028 urtwn_write_region_1(sc, addr, &val, 1); 1029} 1030 1031 1032static void 1033urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1034{ 1035 val = htole16(val); 1036 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1037} 1038 1039static void 1040urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1041{ 1042 val = htole32(val); 1043 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1044} 1045 1046static int 1047urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1048 int len) 1049{ 1050 usb_device_request_t req; 1051 1052 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1053 req.bRequest = R92C_REQ_REGS; 1054 USETW(req.wValue, addr); 1055 USETW(req.wIndex, 0); 1056 USETW(req.wLength, len); 1057 return (urtwn_do_request(sc, &req, buf)); 1058} 1059 1060static uint8_t 1061urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1062{ 1063 uint8_t val; 1064 1065 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1066 return (0xff); 1067 return (val); 1068} 1069 1070static uint16_t 1071urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1072{ 1073 uint16_t val; 1074 1075 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1076 return (0xffff); 1077 return (le16toh(val)); 1078} 1079 1080static uint32_t 1081urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1082{ 1083 uint32_t val; 1084 1085 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1086 return (0xffffffff); 1087 return (le32toh(val)); 1088} 1089 1090static int 1091urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1092{ 1093 struct r92c_fw_cmd cmd; 1094 int ntries; 1095 1096 /* Wait for current FW box to be empty. */ 1097 for (ntries = 0; ntries < 100; ntries++) { 1098 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1099 break; 1100 urtwn_ms_delay(sc); 1101 } 1102 if (ntries == 100) { 1103 device_printf(sc->sc_dev, 1104 "could not send firmware command\n"); 1105 return (ETIMEDOUT); 1106 } 1107 memset(&cmd, 0, sizeof(cmd)); 1108 cmd.id = id; 1109 if (len > 3) 1110 cmd.id |= R92C_CMD_FLAG_EXT; 1111 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1112 memcpy(cmd.msg, buf, len); 1113 1114 /* Write the first word last since that will trigger the FW. */ 1115 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1116 (uint8_t *)&cmd + 4, 2); 1117 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1118 (uint8_t *)&cmd + 0, 4); 1119 1120 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1121 return (0); 1122} 1123 1124static __inline void 1125urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1126{ 1127 1128 sc->sc_rf_write(sc, chain, addr, val); 1129} 1130 1131static void 1132urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1133 uint32_t val) 1134{ 1135 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1136 SM(R92C_LSSI_PARAM_ADDR, addr) | 1137 SM(R92C_LSSI_PARAM_DATA, val)); 1138} 1139 1140static void 1141urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1142uint32_t val) 1143{ 1144 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1145 SM(R88E_LSSI_PARAM_ADDR, addr) | 1146 SM(R92C_LSSI_PARAM_DATA, val)); 1147} 1148 1149static uint32_t 1150urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1151{ 1152 uint32_t reg[R92C_MAX_CHAINS], val; 1153 1154 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1155 if (chain != 0) 1156 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1157 1158 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1159 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1160 urtwn_ms_delay(sc); 1161 1162 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1163 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1164 R92C_HSSI_PARAM2_READ_EDGE); 1165 urtwn_ms_delay(sc); 1166 1167 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1168 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1169 urtwn_ms_delay(sc); 1170 1171 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1172 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1173 else 1174 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1175 return (MS(val, R92C_LSSI_READBACK_DATA)); 1176} 1177 1178static int 1179urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1180{ 1181 int ntries; 1182 1183 urtwn_write_4(sc, R92C_LLT_INIT, 1184 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1185 SM(R92C_LLT_INIT_ADDR, addr) | 1186 SM(R92C_LLT_INIT_DATA, data)); 1187 /* Wait for write operation to complete. */ 1188 for (ntries = 0; ntries < 20; ntries++) { 1189 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1190 R92C_LLT_INIT_OP_NO_ACTIVE) 1191 return (0); 1192 urtwn_ms_delay(sc); 1193 } 1194 return (ETIMEDOUT); 1195} 1196 1197static uint8_t 1198urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1199{ 1200 uint32_t reg; 1201 int ntries; 1202 1203 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1204 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1205 reg &= ~R92C_EFUSE_CTRL_VALID; 1206 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1207 /* Wait for read operation to complete. */ 1208 for (ntries = 0; ntries < 100; ntries++) { 1209 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1210 if (reg & R92C_EFUSE_CTRL_VALID) 1211 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1212 urtwn_ms_delay(sc); 1213 } 1214 device_printf(sc->sc_dev, 1215 "could not read efuse byte at address 0x%x\n", addr); 1216 return (0xff); 1217} 1218 1219static void 1220urtwn_efuse_read(struct urtwn_softc *sc) 1221{ 1222 uint8_t *rom = (uint8_t *)&sc->rom; 1223 uint16_t addr = 0; 1224 uint32_t reg; 1225 uint8_t off, msk; 1226 int i; 1227 1228 urtwn_efuse_switch_power(sc); 1229 1230 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1231 while (addr < 512) { 1232 reg = urtwn_efuse_read_1(sc, addr); 1233 if (reg == 0xff) 1234 break; 1235 addr++; 1236 off = reg >> 4; 1237 msk = reg & 0xf; 1238 for (i = 0; i < 4; i++) { 1239 if (msk & (1 << i)) 1240 continue; 1241 rom[off * 8 + i * 2 + 0] = 1242 urtwn_efuse_read_1(sc, addr); 1243 addr++; 1244 rom[off * 8 + i * 2 + 1] = 1245 urtwn_efuse_read_1(sc, addr); 1246 addr++; 1247 } 1248 } 1249#ifdef URTWN_DEBUG 1250 if (urtwn_debug >= 2) { 1251 /* Dump ROM content. */ 1252 printf("\n"); 1253 for (i = 0; i < sizeof(sc->rom); i++) 1254 printf("%02x:", rom[i]); 1255 printf("\n"); 1256 } 1257#endif 1258 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1259} 1260 1261static void 1262urtwn_efuse_switch_power(struct urtwn_softc *sc) 1263{ 1264 uint32_t reg; 1265 1266 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1267 1268 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1269 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1270 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1271 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1272 } 1273 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1274 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1275 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1276 reg | R92C_SYS_FUNC_EN_ELDR); 1277 } 1278 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1279 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1280 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1281 urtwn_write_2(sc, R92C_SYS_CLKR, 1282 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1283 } 1284} 1285 1286static int 1287urtwn_read_chipid(struct urtwn_softc *sc) 1288{ 1289 uint32_t reg; 1290 1291 if (sc->chip & URTWN_CHIP_88E) 1292 return (0); 1293 1294 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1295 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1296 return (EIO); 1297 1298 if (reg & R92C_SYS_CFG_TYPE_92C) { 1299 sc->chip |= URTWN_CHIP_92C; 1300 /* Check if it is a castrated 8192C. */ 1301 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1302 R92C_HPON_FSM_CHIP_BONDING_ID) == 1303 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1304 sc->chip |= URTWN_CHIP_92C_1T2R; 1305 } 1306 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1307 sc->chip |= URTWN_CHIP_UMC; 1308 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1309 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1310 } 1311 return (0); 1312} 1313 1314static void 1315urtwn_read_rom(struct urtwn_softc *sc) 1316{ 1317 struct r92c_rom *rom = &sc->rom; 1318 1319 /* Read full ROM image. */ 1320 urtwn_efuse_read(sc); 1321 1322 /* XXX Weird but this is what the vendor driver does. */ 1323 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1324 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1325 1326 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1327 1328 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1329 DPRINTF("regulatory type=%d\n", sc->regulatory); 1330 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1331 1332 sc->sc_rf_write = urtwn_r92c_rf_write; 1333 sc->sc_power_on = urtwn_r92c_power_on; 1334 sc->sc_dma_init = urtwn_r92c_dma_init; 1335} 1336 1337static void 1338urtwn_r88e_read_rom(struct urtwn_softc *sc) 1339{ 1340 uint8_t *rom = sc->r88e_rom; 1341 uint16_t addr = 0; 1342 uint32_t reg; 1343 uint8_t off, msk, tmp; 1344 int i; 1345 1346 off = 0; 1347 urtwn_efuse_switch_power(sc); 1348 1349 /* Read full ROM image. */ 1350 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1351 while (addr < 512) { 1352 reg = urtwn_efuse_read_1(sc, addr); 1353 if (reg == 0xff) 1354 break; 1355 addr++; 1356 if ((reg & 0x1f) == 0x0f) { 1357 tmp = (reg & 0xe0) >> 5; 1358 reg = urtwn_efuse_read_1(sc, addr); 1359 if ((reg & 0x0f) != 0x0f) 1360 off = ((reg & 0xf0) >> 1) | tmp; 1361 addr++; 1362 } else 1363 off = reg >> 4; 1364 msk = reg & 0xf; 1365 for (i = 0; i < 4; i++) { 1366 if (msk & (1 << i)) 1367 continue; 1368 rom[off * 8 + i * 2 + 0] = 1369 urtwn_efuse_read_1(sc, addr); 1370 addr++; 1371 rom[off * 8 + i * 2 + 1] = 1372 urtwn_efuse_read_1(sc, addr); 1373 addr++; 1374 } 1375 } 1376 1377 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1378 1379 addr = 0x10; 1380 for (i = 0; i < 6; i++) 1381 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1382 for (i = 0; i < 5; i++) 1383 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1384 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1385 if (sc->bw20_tx_pwr_diff & 0x08) 1386 sc->bw20_tx_pwr_diff |= 0xf0; 1387 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1388 if (sc->ofdm_tx_pwr_diff & 0x08) 1389 sc->ofdm_tx_pwr_diff |= 0xf0; 1390 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1391 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &sc->r88e_rom[0xd7]); 1392 1393 sc->sc_rf_write = urtwn_r88e_rf_write; 1394 sc->sc_power_on = urtwn_r88e_power_on; 1395 sc->sc_dma_init = urtwn_r88e_dma_init; 1396} 1397 1398/* 1399 * Initialize rate adaptation in firmware. 1400 */ 1401static int 1402urtwn_ra_init(struct urtwn_softc *sc) 1403{ 1404 struct ieee80211com *ic = &sc->sc_ic; 1405 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1406 struct ieee80211_node *ni; 1407 struct ieee80211_rateset *rs; 1408 struct r92c_fw_cmd_macid_cfg cmd; 1409 uint32_t rates, basicrates; 1410 uint8_t mode; 1411 int maxrate, maxbasicrate, error, i, j; 1412 1413 ni = ieee80211_ref_node(vap->iv_bss); 1414 rs = &ni->ni_rates; 1415 1416 /* Get normal and basic rates mask. */ 1417 rates = basicrates = 0; 1418 maxrate = maxbasicrate = 0; 1419 for (i = 0; i < rs->rs_nrates; i++) { 1420 /* Convert 802.11 rate to HW rate index. */ 1421 for (j = 0; j < nitems(ridx2rate); j++) 1422 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1423 ridx2rate[j]) 1424 break; 1425 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1426 continue; 1427 rates |= 1 << j; 1428 if (j > maxrate) 1429 maxrate = j; 1430 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1431 basicrates |= 1 << j; 1432 if (j > maxbasicrate) 1433 maxbasicrate = j; 1434 } 1435 } 1436 if (ic->ic_curmode == IEEE80211_MODE_11B) 1437 mode = R92C_RAID_11B; 1438 else 1439 mode = R92C_RAID_11BG; 1440 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1441 mode, rates, basicrates); 1442 1443 /* Set rates mask for group addressed frames. */ 1444 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1445 cmd.mask = htole32(mode << 28 | basicrates); 1446 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1447 if (error != 0) { 1448 ieee80211_free_node(ni); 1449 device_printf(sc->sc_dev, 1450 "could not add broadcast station\n"); 1451 return (error); 1452 } 1453 /* Set initial MRR rate. */ 1454 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1455 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1456 maxbasicrate); 1457 1458 /* Set rates mask for unicast frames. */ 1459 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1460 cmd.mask = htole32(mode << 28 | rates); 1461 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1462 if (error != 0) { 1463 ieee80211_free_node(ni); 1464 device_printf(sc->sc_dev, "could not add BSS station\n"); 1465 return (error); 1466 } 1467 /* Set initial MRR rate. */ 1468 DPRINTF("maxrate=%d\n", maxrate); 1469 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1470 maxrate); 1471 1472 /* Indicate highest supported rate. */ 1473 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1474 ieee80211_free_node(ni); 1475 1476 return (0); 1477} 1478 1479static void 1480urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1481{ 1482 urtwn_write_1(sc, R92C_BCN_CTRL, 1483 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1484} 1485 1486static void 1487urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1488{ 1489 uint8_t reg; 1490 1491 if (led == URTWN_LED_LINK) { 1492 if (sc->chip & URTWN_CHIP_88E) { 1493 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1494 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1495 if (!on) { 1496 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1497 urtwn_write_1(sc, R92C_LEDCFG2, 1498 reg | R92C_LEDCFG0_DIS); 1499 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1500 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1501 0xfe); 1502 } 1503 } else { 1504 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1505 if (!on) 1506 reg |= R92C_LEDCFG0_DIS; 1507 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1508 } 1509 sc->ledlink = on; /* Save LED state. */ 1510 } 1511} 1512 1513static void 1514urtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 1515{ 1516 uint8_t reg; 1517 1518 reg = urtwn_read_1(sc, R92C_MSR); 1519 reg = (reg & ~R92C_MSR_MASK) | mode; 1520 urtwn_write_1(sc, R92C_MSR, reg); 1521} 1522 1523static int 1524urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1525{ 1526 struct urtwn_vap *uvp = URTWN_VAP(vap); 1527 struct ieee80211com *ic = vap->iv_ic; 1528 struct urtwn_softc *sc = ic->ic_softc; 1529 struct ieee80211_node *ni; 1530 enum ieee80211_state ostate; 1531 1532 ostate = vap->iv_state; 1533 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1534 ieee80211_state_name[nstate]); 1535 1536 IEEE80211_UNLOCK(ic); 1537 URTWN_LOCK(sc); 1538 callout_stop(&sc->sc_watchdog_ch); 1539 1540 if (ostate == IEEE80211_S_RUN) { 1541 /* Turn link LED off. */ 1542 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1543 1544 /* Set media status to 'No Link'. */ 1545 urtwn_set_mode(sc, R92C_MSR_NOLINK); 1546 1547 /* Stop Rx of data frames. */ 1548 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1549 1550 /* Rest TSF. */ 1551 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1552 1553 /* Disable TSF synchronization. */ 1554 urtwn_write_1(sc, R92C_BCN_CTRL, 1555 urtwn_read_1(sc, R92C_BCN_CTRL) | 1556 R92C_BCN_CTRL_DIS_TSF_UDT0); 1557 1558 /* Reset EDCA parameters. */ 1559 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1560 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1561 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1562 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1563 } 1564 1565 switch (nstate) { 1566 case IEEE80211_S_INIT: 1567 /* Turn link LED off. */ 1568 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1569 break; 1570 case IEEE80211_S_SCAN: 1571 /* Pause AC Tx queues. */ 1572 urtwn_write_1(sc, R92C_TXPAUSE, 1573 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1574 break; 1575 case IEEE80211_S_AUTH: 1576 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1577 break; 1578 case IEEE80211_S_RUN: 1579 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1580 /* Turn link LED on. */ 1581 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1582 break; 1583 } 1584 1585 ni = ieee80211_ref_node(vap->iv_bss); 1586 /* Set media status to 'Associated'. */ 1587 urtwn_set_mode(sc, R92C_MSR_INFRA); 1588 1589 /* Set BSSID. */ 1590 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1591 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1592 1593 if (ic->ic_curmode == IEEE80211_MODE_11B) 1594 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1595 else /* 802.11b/g */ 1596 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1597 1598 /* Enable Rx of data frames. */ 1599 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1600 1601 /* Flush all AC queues. */ 1602 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1603 1604 /* Set beacon interval. */ 1605 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1606 1607 /* Allow Rx from our BSSID only. */ 1608 if (ic->ic_promisc == 0) { 1609 urtwn_write_4(sc, R92C_RCR, 1610 urtwn_read_4(sc, R92C_RCR) | 1611 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1612 } 1613 1614 /* Enable TSF synchronization. */ 1615 urtwn_tsf_sync_enable(sc); 1616 1617 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1618 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1619 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1620 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1621 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1622 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1623 1624 /* Intialize rate adaptation. */ 1625 if (sc->chip & URTWN_CHIP_88E) 1626 ni->ni_txrate = 1627 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1628 else 1629 urtwn_ra_init(sc); 1630 /* Turn link LED on. */ 1631 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1632 1633 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1634 /* Reset temperature calibration state machine. */ 1635 sc->thcal_state = 0; 1636 sc->thcal_lctemp = 0; 1637 ieee80211_free_node(ni); 1638 break; 1639 default: 1640 break; 1641 } 1642 URTWN_UNLOCK(sc); 1643 IEEE80211_LOCK(ic); 1644 return(uvp->newstate(vap, nstate, arg)); 1645} 1646 1647static void 1648urtwn_watchdog(void *arg) 1649{ 1650 struct urtwn_softc *sc = arg; 1651 1652 if (sc->sc_txtimer > 0) { 1653 if (--sc->sc_txtimer == 0) { 1654 device_printf(sc->sc_dev, "device timeout\n"); 1655 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1656 return; 1657 } 1658 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1659 } 1660} 1661 1662static void 1663urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1664{ 1665 int pwdb; 1666 1667 /* Convert antenna signal to percentage. */ 1668 if (rssi <= -100 || rssi >= 20) 1669 pwdb = 0; 1670 else if (rssi >= 0) 1671 pwdb = 100; 1672 else 1673 pwdb = 100 + rssi; 1674 if (!(sc->chip & URTWN_CHIP_88E)) { 1675 if (rate <= URTWN_RIDX_CCK11) { 1676 /* CCK gain is smaller than OFDM/MCS gain. */ 1677 pwdb += 6; 1678 if (pwdb > 100) 1679 pwdb = 100; 1680 if (pwdb <= 14) 1681 pwdb -= 4; 1682 else if (pwdb <= 26) 1683 pwdb -= 8; 1684 else if (pwdb <= 34) 1685 pwdb -= 6; 1686 else if (pwdb <= 42) 1687 pwdb -= 2; 1688 } 1689 } 1690 if (sc->avg_pwdb == -1) /* Init. */ 1691 sc->avg_pwdb = pwdb; 1692 else if (sc->avg_pwdb < pwdb) 1693 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1694 else 1695 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1696 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1697} 1698 1699static int8_t 1700urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1701{ 1702 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1703 struct r92c_rx_phystat *phy; 1704 struct r92c_rx_cck *cck; 1705 uint8_t rpt; 1706 int8_t rssi; 1707 1708 if (rate <= URTWN_RIDX_CCK11) { 1709 cck = (struct r92c_rx_cck *)physt; 1710 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1711 rpt = (cck->agc_rpt >> 5) & 0x3; 1712 rssi = (cck->agc_rpt & 0x1f) << 1; 1713 } else { 1714 rpt = (cck->agc_rpt >> 6) & 0x3; 1715 rssi = cck->agc_rpt & 0x3e; 1716 } 1717 rssi = cckoff[rpt] - rssi; 1718 } else { /* OFDM/HT. */ 1719 phy = (struct r92c_rx_phystat *)physt; 1720 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1721 } 1722 return (rssi); 1723} 1724 1725static int8_t 1726urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1727{ 1728 struct r92c_rx_phystat *phy; 1729 struct r88e_rx_cck *cck; 1730 uint8_t cck_agc_rpt, lna_idx, vga_idx; 1731 int8_t rssi; 1732 1733 rssi = 0; 1734 if (rate <= URTWN_RIDX_CCK11) { 1735 cck = (struct r88e_rx_cck *)physt; 1736 cck_agc_rpt = cck->agc_rpt; 1737 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1738 vga_idx = cck_agc_rpt & 0x1f; 1739 switch (lna_idx) { 1740 case 7: 1741 if (vga_idx <= 27) 1742 rssi = -100 + 2* (27 - vga_idx); 1743 else 1744 rssi = -100; 1745 break; 1746 case 6: 1747 rssi = -48 + 2 * (2 - vga_idx); 1748 break; 1749 case 5: 1750 rssi = -42 + 2 * (7 - vga_idx); 1751 break; 1752 case 4: 1753 rssi = -36 + 2 * (7 - vga_idx); 1754 break; 1755 case 3: 1756 rssi = -24 + 2 * (7 - vga_idx); 1757 break; 1758 case 2: 1759 rssi = -12 + 2 * (5 - vga_idx); 1760 break; 1761 case 1: 1762 rssi = 8 - (2 * vga_idx); 1763 break; 1764 case 0: 1765 rssi = 14 - (2 * vga_idx); 1766 break; 1767 } 1768 rssi += 6; 1769 } else { /* OFDM/HT. */ 1770 phy = (struct r92c_rx_phystat *)physt; 1771 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1772 } 1773 return (rssi); 1774} 1775 1776static int 1777urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1778 struct mbuf *m0, struct urtwn_data *data) 1779{ 1780 struct ieee80211_frame *wh; 1781 struct ieee80211_key *k; 1782 struct ieee80211com *ic = &sc->sc_ic; 1783 struct ieee80211vap *vap = ni->ni_vap; 1784 struct usb_xfer *xfer; 1785 struct r92c_tx_desc *txd; 1786 uint8_t raid, type; 1787 uint16_t sum; 1788 int i, xferlen; 1789 struct usb_xfer *urtwn_pipes[4] = { 1790 sc->sc_xfer[URTWN_BULK_TX_BE], 1791 sc->sc_xfer[URTWN_BULK_TX_BK], 1792 sc->sc_xfer[URTWN_BULK_TX_VI], 1793 sc->sc_xfer[URTWN_BULK_TX_VO] 1794 }; 1795 1796 URTWN_ASSERT_LOCKED(sc); 1797 1798 /* 1799 * Software crypto. 1800 */ 1801 wh = mtod(m0, struct ieee80211_frame *); 1802 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1803 1804 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1805 k = ieee80211_crypto_encap(ni, m0); 1806 if (k == NULL) { 1807 device_printf(sc->sc_dev, 1808 "ieee80211_crypto_encap returns NULL.\n"); 1809 /* XXX we don't expect the fragmented frames */ 1810 return (ENOBUFS); 1811 } 1812 1813 /* in case packet header moved, reset pointer */ 1814 wh = mtod(m0, struct ieee80211_frame *); 1815 } 1816 1817 switch (type) { 1818 case IEEE80211_FC0_TYPE_CTL: 1819 case IEEE80211_FC0_TYPE_MGT: 1820 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1821 break; 1822 default: 1823 KASSERT(M_WME_GETAC(m0) < 4, 1824 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1825 xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1826 break; 1827 } 1828 1829 /* Fill Tx descriptor. */ 1830 txd = (struct r92c_tx_desc *)data->buf; 1831 memset(txd, 0, sizeof(*txd)); 1832 1833 txd->txdw0 |= htole32( 1834 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1835 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1836 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1837 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1838 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1839 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1840 type == IEEE80211_FC0_TYPE_DATA) { 1841 if (ic->ic_curmode == IEEE80211_MODE_11B) 1842 raid = R92C_RAID_11B; 1843 else 1844 raid = R92C_RAID_11BG; 1845 if (sc->chip & URTWN_CHIP_88E) { 1846 txd->txdw1 |= htole32( 1847 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1848 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1849 SM(R92C_TXDW1_RAID, raid)); 1850 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1851 } else { 1852 txd->txdw1 |= htole32( 1853 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1854 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1855 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1856 } 1857 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1858 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1859 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1860 R92C_TXDW4_HWRTSEN); 1861 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1862 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1863 R92C_TXDW4_HWRTSEN); 1864 } 1865 } 1866 /* Send RTS at OFDM24. */ 1867 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1868 URTWN_RIDX_OFDM24)); 1869 txd->txdw5 |= htole32(0x0001ff00); 1870 /* Send data at OFDM54. */ 1871 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1872 URTWN_RIDX_OFDM54)); 1873 } else { 1874 txd->txdw1 |= htole32( 1875 SM(R92C_TXDW1_MACID, 0) | 1876 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1877 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1878 1879 /* Force CCK1. */ 1880 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1881 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1882 URTWN_RIDX_CCK1)); 1883 } 1884 /* Set sequence number (already little endian). */ 1885 txd->txdseq |= *(uint16_t *)wh->i_seq; 1886 1887 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 1888 /* Use HW sequence numbering for non-QoS frames. */ 1889 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1890 txd->txdseq |= htole16(0x8000); 1891 } else 1892 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1893 1894 /* Compute Tx descriptor checksum. */ 1895 sum = 0; 1896 for (i = 0; i < sizeof(*txd) / 2; i++) 1897 sum ^= ((uint16_t *)txd)[i]; 1898 txd->txdsum = sum; /* NB: already little endian. */ 1899 1900 if (ieee80211_radiotap_active_vap(vap)) { 1901 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1902 1903 tap->wt_flags = 0; 1904 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1905 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1906 ieee80211_radiotap_tx(vap, m0); 1907 } 1908 1909 xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1910 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1911 1912 data->buflen = xferlen; 1913 data->ni = ni; 1914 data->m = m0; 1915 1916 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1917 usbd_transfer_start(xfer); 1918 return (0); 1919} 1920 1921static int 1922urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1923{ 1924 struct urtwn_softc *sc = ic->ic_softc; 1925 int error; 1926 1927 URTWN_LOCK(sc); 1928 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1929 URTWN_UNLOCK(sc); 1930 return (ENXIO); 1931 } 1932 error = mbufq_enqueue(&sc->sc_snd, m); 1933 if (error) { 1934 URTWN_UNLOCK(sc); 1935 return (error); 1936 } 1937 urtwn_start(sc); 1938 URTWN_UNLOCK(sc); 1939 1940 return (0); 1941} 1942 1943static void 1944urtwn_start(struct urtwn_softc *sc) 1945{ 1946 struct ieee80211_node *ni; 1947 struct mbuf *m; 1948 struct urtwn_data *bf; 1949 1950 URTWN_ASSERT_LOCKED(sc); 1951 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1952 bf = urtwn_getbuf(sc); 1953 if (bf == NULL) { 1954 mbufq_prepend(&sc->sc_snd, m); 1955 break; 1956 } 1957 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1958 m->m_pkthdr.rcvif = NULL; 1959 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 1960 if_inc_counter(ni->ni_vap->iv_ifp, 1961 IFCOUNTER_OERRORS, 1); 1962 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1963 m_freem(m); 1964 ieee80211_free_node(ni); 1965 break; 1966 } 1967 sc->sc_txtimer = 5; 1968 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1969 } 1970} 1971 1972static void 1973urtwn_parent(struct ieee80211com *ic) 1974{ 1975 struct urtwn_softc *sc = ic->ic_softc; 1976 int startall = 0; 1977 1978 URTWN_LOCK(sc); 1979 if (sc->sc_flags & URTWN_DETACHED) { 1980 URTWN_UNLOCK(sc); 1981 return; 1982 } 1983 if (ic->ic_nrunning > 0) { 1984 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1985 urtwn_init(sc); 1986 startall = 1; 1987 } 1988 } else if (sc->sc_flags & URTWN_RUNNING) 1989 urtwn_stop(sc); 1990 URTWN_UNLOCK(sc); 1991 1992 if (startall) 1993 ieee80211_start_all(ic); 1994} 1995 1996static __inline int 1997urtwn_power_on(struct urtwn_softc *sc) 1998{ 1999 2000 return sc->sc_power_on(sc); 2001} 2002 2003static int 2004urtwn_r92c_power_on(struct urtwn_softc *sc) 2005{ 2006 uint32_t reg; 2007 int ntries; 2008 2009 /* Wait for autoload done bit. */ 2010 for (ntries = 0; ntries < 1000; ntries++) { 2011 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2012 break; 2013 urtwn_ms_delay(sc); 2014 } 2015 if (ntries == 1000) { 2016 device_printf(sc->sc_dev, 2017 "timeout waiting for chip autoload\n"); 2018 return (ETIMEDOUT); 2019 } 2020 2021 /* Unlock ISO/CLK/Power control register. */ 2022 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2023 /* Move SPS into PWM mode. */ 2024 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2025 urtwn_ms_delay(sc); 2026 2027 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2028 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2029 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2030 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2031 urtwn_ms_delay(sc); 2032 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2033 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2034 ~R92C_SYS_ISO_CTRL_MD2PP); 2035 } 2036 2037 /* Auto enable WLAN. */ 2038 urtwn_write_2(sc, R92C_APS_FSMCO, 2039 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2040 for (ntries = 0; ntries < 1000; ntries++) { 2041 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2042 R92C_APS_FSMCO_APFM_ONMAC)) 2043 break; 2044 urtwn_ms_delay(sc); 2045 } 2046 if (ntries == 1000) { 2047 device_printf(sc->sc_dev, 2048 "timeout waiting for MAC auto ON\n"); 2049 return (ETIMEDOUT); 2050 } 2051 2052 /* Enable radio, GPIO and LED functions. */ 2053 urtwn_write_2(sc, R92C_APS_FSMCO, 2054 R92C_APS_FSMCO_AFSM_HSUS | 2055 R92C_APS_FSMCO_PDN_EN | 2056 R92C_APS_FSMCO_PFM_ALDN); 2057 /* Release RF digital isolation. */ 2058 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2059 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2060 2061 /* Initialize MAC. */ 2062 urtwn_write_1(sc, R92C_APSD_CTRL, 2063 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2064 for (ntries = 0; ntries < 200; ntries++) { 2065 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2066 R92C_APSD_CTRL_OFF_STATUS)) 2067 break; 2068 urtwn_ms_delay(sc); 2069 } 2070 if (ntries == 200) { 2071 device_printf(sc->sc_dev, 2072 "timeout waiting for MAC initialization\n"); 2073 return (ETIMEDOUT); 2074 } 2075 2076 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2077 reg = urtwn_read_2(sc, R92C_CR); 2078 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2079 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2080 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2081 R92C_CR_ENSEC; 2082 urtwn_write_2(sc, R92C_CR, reg); 2083 2084 urtwn_write_1(sc, 0xfe10, 0x19); 2085 return (0); 2086} 2087 2088static int 2089urtwn_r88e_power_on(struct urtwn_softc *sc) 2090{ 2091 uint32_t reg; 2092 int ntries; 2093 2094 /* Wait for power ready bit. */ 2095 for (ntries = 0; ntries < 5000; ntries++) { 2096 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2097 break; 2098 urtwn_ms_delay(sc); 2099 } 2100 if (ntries == 5000) { 2101 device_printf(sc->sc_dev, 2102 "timeout waiting for chip power up\n"); 2103 return (ETIMEDOUT); 2104 } 2105 2106 /* Reset BB. */ 2107 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2108 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2109 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2110 2111 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2112 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2113 2114 /* Disable HWPDN. */ 2115 urtwn_write_2(sc, R92C_APS_FSMCO, 2116 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2117 2118 /* Disable WL suspend. */ 2119 urtwn_write_2(sc, R92C_APS_FSMCO, 2120 urtwn_read_2(sc, R92C_APS_FSMCO) & 2121 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2122 2123 urtwn_write_2(sc, R92C_APS_FSMCO, 2124 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2125 for (ntries = 0; ntries < 5000; ntries++) { 2126 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2127 R92C_APS_FSMCO_APFM_ONMAC)) 2128 break; 2129 urtwn_ms_delay(sc); 2130 } 2131 if (ntries == 5000) 2132 return (ETIMEDOUT); 2133 2134 /* Enable LDO normal mode. */ 2135 urtwn_write_1(sc, R92C_LPLDO_CTRL, 2136 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2137 2138 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2139 urtwn_write_2(sc, R92C_CR, 0); 2140 reg = urtwn_read_2(sc, R92C_CR); 2141 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2142 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2143 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2144 urtwn_write_2(sc, R92C_CR, reg); 2145 2146 return (0); 2147} 2148 2149static int 2150urtwn_llt_init(struct urtwn_softc *sc) 2151{ 2152 int i, error, page_count, pktbuf_count; 2153 2154 page_count = (sc->chip & URTWN_CHIP_88E) ? 2155 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2156 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2157 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2158 2159 /* Reserve pages [0; page_count]. */ 2160 for (i = 0; i < page_count; i++) { 2161 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2162 return (error); 2163 } 2164 /* NB: 0xff indicates end-of-list. */ 2165 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2166 return (error); 2167 /* 2168 * Use pages [page_count + 1; pktbuf_count - 1] 2169 * as ring buffer. 2170 */ 2171 for (++i; i < pktbuf_count - 1; i++) { 2172 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2173 return (error); 2174 } 2175 /* Make the last page point to the beginning of the ring buffer. */ 2176 error = urtwn_llt_write(sc, i, page_count + 1); 2177 return (error); 2178} 2179 2180static void 2181urtwn_fw_reset(struct urtwn_softc *sc) 2182{ 2183 uint16_t reg; 2184 int ntries; 2185 2186 /* Tell 8051 to reset itself. */ 2187 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2188 2189 /* Wait until 8051 resets by itself. */ 2190 for (ntries = 0; ntries < 100; ntries++) { 2191 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2192 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2193 return; 2194 urtwn_ms_delay(sc); 2195 } 2196 /* Force 8051 reset. */ 2197 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2198} 2199 2200static void 2201urtwn_r88e_fw_reset(struct urtwn_softc *sc) 2202{ 2203 uint16_t reg; 2204 2205 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2206 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2207 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2208} 2209 2210static int 2211urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2212{ 2213 uint32_t reg; 2214 int off, mlen, error = 0; 2215 2216 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2217 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2218 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2219 2220 off = R92C_FW_START_ADDR; 2221 while (len > 0) { 2222 if (len > 196) 2223 mlen = 196; 2224 else if (len > 4) 2225 mlen = 4; 2226 else 2227 mlen = 1; 2228 /* XXX fix this deconst */ 2229 error = urtwn_write_region_1(sc, off, 2230 __DECONST(uint8_t *, buf), mlen); 2231 if (error != 0) 2232 break; 2233 off += mlen; 2234 buf += mlen; 2235 len -= mlen; 2236 } 2237 return (error); 2238} 2239 2240static int 2241urtwn_load_firmware(struct urtwn_softc *sc) 2242{ 2243 const struct firmware *fw; 2244 const struct r92c_fw_hdr *hdr; 2245 const char *imagename; 2246 const u_char *ptr; 2247 size_t len; 2248 uint32_t reg; 2249 int mlen, ntries, page, error; 2250 2251 URTWN_UNLOCK(sc); 2252 /* Read firmware image from the filesystem. */ 2253 if (sc->chip & URTWN_CHIP_88E) 2254 imagename = "urtwn-rtl8188eufw"; 2255 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2256 URTWN_CHIP_UMC_A_CUT) 2257 imagename = "urtwn-rtl8192cfwU"; 2258 else 2259 imagename = "urtwn-rtl8192cfwT"; 2260 2261 fw = firmware_get(imagename); 2262 URTWN_LOCK(sc); 2263 if (fw == NULL) { 2264 device_printf(sc->sc_dev, 2265 "failed loadfirmware of file %s\n", imagename); 2266 return (ENOENT); 2267 } 2268 2269 len = fw->datasize; 2270 2271 if (len < sizeof(*hdr)) { 2272 device_printf(sc->sc_dev, "firmware too short\n"); 2273 error = EINVAL; 2274 goto fail; 2275 } 2276 ptr = fw->data; 2277 hdr = (const struct r92c_fw_hdr *)ptr; 2278 /* Check if there is a valid FW header and skip it. */ 2279 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2280 (le16toh(hdr->signature) >> 4) == 0x88e || 2281 (le16toh(hdr->signature) >> 4) == 0x92c) { 2282 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2283 le16toh(hdr->version), le16toh(hdr->subversion), 2284 hdr->month, hdr->date, hdr->hour, hdr->minute); 2285 ptr += sizeof(*hdr); 2286 len -= sizeof(*hdr); 2287 } 2288 2289 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2290 if (sc->chip & URTWN_CHIP_88E) 2291 urtwn_r88e_fw_reset(sc); 2292 else 2293 urtwn_fw_reset(sc); 2294 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2295 } 2296 2297 if (!(sc->chip & URTWN_CHIP_88E)) { 2298 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2299 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2300 R92C_SYS_FUNC_EN_CPUEN); 2301 } 2302 urtwn_write_1(sc, R92C_MCUFWDL, 2303 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2304 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2305 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2306 2307 /* Reset the FWDL checksum. */ 2308 urtwn_write_1(sc, R92C_MCUFWDL, 2309 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2310 2311 for (page = 0; len > 0; page++) { 2312 mlen = min(len, R92C_FW_PAGE_SIZE); 2313 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2314 if (error != 0) { 2315 device_printf(sc->sc_dev, 2316 "could not load firmware page\n"); 2317 goto fail; 2318 } 2319 ptr += mlen; 2320 len -= mlen; 2321 } 2322 urtwn_write_1(sc, R92C_MCUFWDL, 2323 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2324 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2325 2326 /* Wait for checksum report. */ 2327 for (ntries = 0; ntries < 1000; ntries++) { 2328 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2329 break; 2330 urtwn_ms_delay(sc); 2331 } 2332 if (ntries == 1000) { 2333 device_printf(sc->sc_dev, 2334 "timeout waiting for checksum report\n"); 2335 error = ETIMEDOUT; 2336 goto fail; 2337 } 2338 2339 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2340 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2341 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2342 if (sc->chip & URTWN_CHIP_88E) 2343 urtwn_r88e_fw_reset(sc); 2344 /* Wait for firmware readiness. */ 2345 for (ntries = 0; ntries < 1000; ntries++) { 2346 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2347 break; 2348 urtwn_ms_delay(sc); 2349 } 2350 if (ntries == 1000) { 2351 device_printf(sc->sc_dev, 2352 "timeout waiting for firmware readiness\n"); 2353 error = ETIMEDOUT; 2354 goto fail; 2355 } 2356fail: 2357 firmware_put(fw, FIRMWARE_UNLOAD); 2358 return (error); 2359} 2360 2361static __inline int 2362urtwn_dma_init(struct urtwn_softc *sc) 2363{ 2364 2365 return sc->sc_dma_init(sc); 2366} 2367 2368static int 2369urtwn_r92c_dma_init(struct urtwn_softc *sc) 2370{ 2371 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2372 uint32_t reg; 2373 int error; 2374 2375 /* Initialize LLT table. */ 2376 error = urtwn_llt_init(sc); 2377 if (error != 0) 2378 return (error); 2379 2380 /* Get Tx queues to USB endpoints mapping. */ 2381 hashq = hasnq = haslq = 0; 2382 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2383 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2384 if (MS(reg, R92C_USB_EP_HQ) != 0) 2385 hashq = 1; 2386 if (MS(reg, R92C_USB_EP_NQ) != 0) 2387 hasnq = 1; 2388 if (MS(reg, R92C_USB_EP_LQ) != 0) 2389 haslq = 1; 2390 nqueues = hashq + hasnq + haslq; 2391 if (nqueues == 0) 2392 return (EIO); 2393 /* Get the number of pages for each queue. */ 2394 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2395 /* The remaining pages are assigned to the high priority queue. */ 2396 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2397 2398 /* Set number of pages for normal priority queue. */ 2399 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2400 urtwn_write_4(sc, R92C_RQPN, 2401 /* Set number of pages for public queue. */ 2402 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2403 /* Set number of pages for high priority queue. */ 2404 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2405 /* Set number of pages for low priority queue. */ 2406 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2407 /* Load values. */ 2408 R92C_RQPN_LD); 2409 2410 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2411 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2412 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2413 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2414 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2415 2416 /* Set queue to USB pipe mapping. */ 2417 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2418 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2419 if (nqueues == 1) { 2420 if (hashq) 2421 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2422 else if (hasnq) 2423 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2424 else 2425 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2426 } else if (nqueues == 2) { 2427 /* All 2-endpoints configs have a high priority queue. */ 2428 if (!hashq) 2429 return (EIO); 2430 if (hasnq) 2431 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2432 else 2433 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2434 } else 2435 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2436 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2437 2438 /* Set Tx/Rx transfer page boundary. */ 2439 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2440 2441 /* Set Tx/Rx transfer page size. */ 2442 urtwn_write_1(sc, R92C_PBP, 2443 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2444 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2445 return (0); 2446} 2447 2448static int 2449urtwn_r88e_dma_init(struct urtwn_softc *sc) 2450{ 2451 struct usb_interface *iface; 2452 uint32_t reg; 2453 int nqueues; 2454 int error; 2455 2456 /* Initialize LLT table. */ 2457 error = urtwn_llt_init(sc); 2458 if (error != 0) 2459 return (error); 2460 2461 /* Get Tx queues to USB endpoints mapping. */ 2462 iface = usbd_get_iface(sc->sc_udev, 0); 2463 nqueues = iface->idesc->bNumEndpoints - 1; 2464 if (nqueues == 0) 2465 return (EIO); 2466 2467 /* Set number of pages for normal priority queue. */ 2468 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2469 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2470 2471 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2472 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2473 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2474 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2475 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2476 2477 /* Set queue to USB pipe mapping. */ 2478 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2479 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2480 if (nqueues == 1) 2481 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2482 else if (nqueues == 2) 2483 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2484 else 2485 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2486 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2487 2488 /* Set Tx/Rx transfer page boundary. */ 2489 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2490 2491 /* Set Tx/Rx transfer page size. */ 2492 urtwn_write_1(sc, R92C_PBP, 2493 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2494 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2495 2496 return (0); 2497} 2498 2499static void 2500urtwn_mac_init(struct urtwn_softc *sc) 2501{ 2502 int i; 2503 2504 /* Write MAC initialization values. */ 2505 if (sc->chip & URTWN_CHIP_88E) { 2506 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2507 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2508 rtl8188eu_mac[i].val); 2509 } 2510 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2511 } else { 2512 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2513 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2514 rtl8192cu_mac[i].val); 2515 } 2516} 2517 2518static void 2519urtwn_bb_init(struct urtwn_softc *sc) 2520{ 2521 const struct urtwn_bb_prog *prog; 2522 uint32_t reg; 2523 uint8_t crystalcap; 2524 int i; 2525 2526 /* Enable BB and RF. */ 2527 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2528 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2529 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2530 R92C_SYS_FUNC_EN_DIO_RF); 2531 2532 if (!(sc->chip & URTWN_CHIP_88E)) 2533 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2534 2535 urtwn_write_1(sc, R92C_RF_CTRL, 2536 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2537 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2538 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2539 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2540 2541 if (!(sc->chip & URTWN_CHIP_88E)) { 2542 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2543 urtwn_write_1(sc, 0x15, 0xe9); 2544 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2545 } 2546 2547 /* Select BB programming based on board type. */ 2548 if (sc->chip & URTWN_CHIP_88E) 2549 prog = &rtl8188eu_bb_prog; 2550 else if (!(sc->chip & URTWN_CHIP_92C)) { 2551 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2552 prog = &rtl8188ce_bb_prog; 2553 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2554 prog = &rtl8188ru_bb_prog; 2555 else 2556 prog = &rtl8188cu_bb_prog; 2557 } else { 2558 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2559 prog = &rtl8192ce_bb_prog; 2560 else 2561 prog = &rtl8192cu_bb_prog; 2562 } 2563 /* Write BB initialization values. */ 2564 for (i = 0; i < prog->count; i++) { 2565 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2566 urtwn_ms_delay(sc); 2567 } 2568 2569 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2570 /* 8192C 1T only configuration. */ 2571 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2572 reg = (reg & ~0x00000003) | 0x2; 2573 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2574 2575 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2576 reg = (reg & ~0x00300033) | 0x00200022; 2577 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2578 2579 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2580 reg = (reg & ~0xff000000) | 0x45 << 24; 2581 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2582 2583 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2584 reg = (reg & ~0x000000ff) | 0x23; 2585 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2586 2587 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2588 reg = (reg & ~0x00000030) | 1 << 4; 2589 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2590 2591 reg = urtwn_bb_read(sc, 0xe74); 2592 reg = (reg & ~0x0c000000) | 2 << 26; 2593 urtwn_bb_write(sc, 0xe74, reg); 2594 reg = urtwn_bb_read(sc, 0xe78); 2595 reg = (reg & ~0x0c000000) | 2 << 26; 2596 urtwn_bb_write(sc, 0xe78, reg); 2597 reg = urtwn_bb_read(sc, 0xe7c); 2598 reg = (reg & ~0x0c000000) | 2 << 26; 2599 urtwn_bb_write(sc, 0xe7c, reg); 2600 reg = urtwn_bb_read(sc, 0xe80); 2601 reg = (reg & ~0x0c000000) | 2 << 26; 2602 urtwn_bb_write(sc, 0xe80, reg); 2603 reg = urtwn_bb_read(sc, 0xe88); 2604 reg = (reg & ~0x0c000000) | 2 << 26; 2605 urtwn_bb_write(sc, 0xe88, reg); 2606 } 2607 2608 /* Write AGC values. */ 2609 for (i = 0; i < prog->agccount; i++) { 2610 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2611 prog->agcvals[i]); 2612 urtwn_ms_delay(sc); 2613 } 2614 2615 if (sc->chip & URTWN_CHIP_88E) { 2616 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2617 urtwn_ms_delay(sc); 2618 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2619 urtwn_ms_delay(sc); 2620 2621 crystalcap = sc->r88e_rom[0xb9]; 2622 if (crystalcap == 0xff) 2623 crystalcap = 0x20; 2624 crystalcap &= 0x3f; 2625 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2626 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2627 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2628 crystalcap | crystalcap << 6)); 2629 } else { 2630 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2631 R92C_HSSI_PARAM2_CCK_HIPWR) 2632 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2633 } 2634} 2635 2636static void 2637urtwn_rf_init(struct urtwn_softc *sc) 2638{ 2639 const struct urtwn_rf_prog *prog; 2640 uint32_t reg, type; 2641 int i, j, idx, off; 2642 2643 /* Select RF programming based on board type. */ 2644 if (sc->chip & URTWN_CHIP_88E) 2645 prog = rtl8188eu_rf_prog; 2646 else if (!(sc->chip & URTWN_CHIP_92C)) { 2647 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2648 prog = rtl8188ce_rf_prog; 2649 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2650 prog = rtl8188ru_rf_prog; 2651 else 2652 prog = rtl8188cu_rf_prog; 2653 } else 2654 prog = rtl8192ce_rf_prog; 2655 2656 for (i = 0; i < sc->nrxchains; i++) { 2657 /* Save RF_ENV control type. */ 2658 idx = i / 2; 2659 off = (i % 2) * 16; 2660 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2661 type = (reg >> off) & 0x10; 2662 2663 /* Set RF_ENV enable. */ 2664 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2665 reg |= 0x100000; 2666 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2667 urtwn_ms_delay(sc); 2668 /* Set RF_ENV output high. */ 2669 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2670 reg |= 0x10; 2671 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2672 urtwn_ms_delay(sc); 2673 /* Set address and data lengths of RF registers. */ 2674 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2675 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2676 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2677 urtwn_ms_delay(sc); 2678 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2679 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2680 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2681 urtwn_ms_delay(sc); 2682 2683 /* Write RF initialization values for this chain. */ 2684 for (j = 0; j < prog[i].count; j++) { 2685 if (prog[i].regs[j] >= 0xf9 && 2686 prog[i].regs[j] <= 0xfe) { 2687 /* 2688 * These are fake RF registers offsets that 2689 * indicate a delay is required. 2690 */ 2691 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2692 continue; 2693 } 2694 urtwn_rf_write(sc, i, prog[i].regs[j], 2695 prog[i].vals[j]); 2696 urtwn_ms_delay(sc); 2697 } 2698 2699 /* Restore RF_ENV control type. */ 2700 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2701 reg &= ~(0x10 << off) | (type << off); 2702 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2703 2704 /* Cache RF register CHNLBW. */ 2705 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2706 } 2707 2708 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2709 URTWN_CHIP_UMC_A_CUT) { 2710 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2711 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2712 } 2713} 2714 2715static void 2716urtwn_cam_init(struct urtwn_softc *sc) 2717{ 2718 /* Invalidate all CAM entries. */ 2719 urtwn_write_4(sc, R92C_CAMCMD, 2720 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2721} 2722 2723static void 2724urtwn_pa_bias_init(struct urtwn_softc *sc) 2725{ 2726 uint8_t reg; 2727 int i; 2728 2729 for (i = 0; i < sc->nrxchains; i++) { 2730 if (sc->pa_setting & (1 << i)) 2731 continue; 2732 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2733 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2734 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2735 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2736 } 2737 if (!(sc->pa_setting & 0x10)) { 2738 reg = urtwn_read_1(sc, 0x16); 2739 reg = (reg & ~0xf0) | 0x90; 2740 urtwn_write_1(sc, 0x16, reg); 2741 } 2742} 2743 2744static void 2745urtwn_rxfilter_init(struct urtwn_softc *sc) 2746{ 2747 struct ieee80211com *ic = &sc->sc_ic; 2748 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2749 uint32_t rcr; 2750 uint16_t filter; 2751 2752 URTWN_ASSERT_LOCKED(sc); 2753 2754 /* Accept all multicast frames. */ 2755 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2756 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2757 2758 /* Filter for management frames. */ 2759 filter = 0x7f3f; 2760 if (vap->iv_opmode == IEEE80211_M_STA) { 2761 filter &= ~( 2762 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_ASSOC_REQ) | 2763 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_REASSOC_REQ) | 2764 R92C_RXFLTMAP_SUBTYPE(IEEE80211_FC0_SUBTYPE_PROBE_REQ)); 2765 } 2766 urtwn_write_2(sc, R92C_RXFLTMAP0, filter); 2767 2768 /* Reject all control frames. */ 2769 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2770 2771 /* Reject all data frames. */ 2772 urtwn_write_2(sc, R92C_RXFLTMAP2, 0x0000); 2773 2774 rcr = R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_APM | 2775 R92C_RCR_HTC_LOC_CTRL | R92C_RCR_APP_PHYSTS | 2776 R92C_RCR_APP_ICV | R92C_RCR_APP_MIC; 2777 2778 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 2779 /* Accept all frames. */ 2780 rcr |= R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | 2781 R92C_RCR_AAP; 2782 } 2783 2784 /* Set Rx filter. */ 2785 urtwn_write_4(sc, R92C_RCR, rcr); 2786 2787 if (ic->ic_promisc != 0) { 2788 /* Update Rx filter. */ 2789 urtwn_set_promisc(sc); 2790 } 2791} 2792 2793static void 2794urtwn_edca_init(struct urtwn_softc *sc) 2795{ 2796 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2797 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2798 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2799 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2800 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2801 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2802 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2803 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2804} 2805 2806static void 2807urtwn_write_txpower(struct urtwn_softc *sc, int chain, 2808 uint16_t power[URTWN_RIDX_COUNT]) 2809{ 2810 uint32_t reg; 2811 2812 /* Write per-CCK rate Tx power. */ 2813 if (chain == 0) { 2814 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2815 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2816 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2817 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2818 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2819 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2820 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2821 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2822 } else { 2823 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2824 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2825 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2826 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2827 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2828 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2829 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2830 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2831 } 2832 /* Write per-OFDM rate Tx power. */ 2833 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2834 SM(R92C_TXAGC_RATE06, power[ 4]) | 2835 SM(R92C_TXAGC_RATE09, power[ 5]) | 2836 SM(R92C_TXAGC_RATE12, power[ 6]) | 2837 SM(R92C_TXAGC_RATE18, power[ 7])); 2838 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2839 SM(R92C_TXAGC_RATE24, power[ 8]) | 2840 SM(R92C_TXAGC_RATE36, power[ 9]) | 2841 SM(R92C_TXAGC_RATE48, power[10]) | 2842 SM(R92C_TXAGC_RATE54, power[11])); 2843 /* Write per-MCS Tx power. */ 2844 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2845 SM(R92C_TXAGC_MCS00, power[12]) | 2846 SM(R92C_TXAGC_MCS01, power[13]) | 2847 SM(R92C_TXAGC_MCS02, power[14]) | 2848 SM(R92C_TXAGC_MCS03, power[15])); 2849 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2850 SM(R92C_TXAGC_MCS04, power[16]) | 2851 SM(R92C_TXAGC_MCS05, power[17]) | 2852 SM(R92C_TXAGC_MCS06, power[18]) | 2853 SM(R92C_TXAGC_MCS07, power[19])); 2854 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2855 SM(R92C_TXAGC_MCS08, power[20]) | 2856 SM(R92C_TXAGC_MCS09, power[21]) | 2857 SM(R92C_TXAGC_MCS10, power[22]) | 2858 SM(R92C_TXAGC_MCS11, power[23])); 2859 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2860 SM(R92C_TXAGC_MCS12, power[24]) | 2861 SM(R92C_TXAGC_MCS13, power[25]) | 2862 SM(R92C_TXAGC_MCS14, power[26]) | 2863 SM(R92C_TXAGC_MCS15, power[27])); 2864} 2865 2866static void 2867urtwn_get_txpower(struct urtwn_softc *sc, int chain, 2868 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2869 uint16_t power[URTWN_RIDX_COUNT]) 2870{ 2871 struct ieee80211com *ic = &sc->sc_ic; 2872 struct r92c_rom *rom = &sc->rom; 2873 uint16_t cckpow, ofdmpow, htpow, diff, max; 2874 const struct urtwn_txpwr *base; 2875 int ridx, chan, group; 2876 2877 /* Determine channel group. */ 2878 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2879 if (chan <= 3) 2880 group = 0; 2881 else if (chan <= 9) 2882 group = 1; 2883 else 2884 group = 2; 2885 2886 /* Get original Tx power based on board type and RF chain. */ 2887 if (!(sc->chip & URTWN_CHIP_92C)) { 2888 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2889 base = &rtl8188ru_txagc[chain]; 2890 else 2891 base = &rtl8192cu_txagc[chain]; 2892 } else 2893 base = &rtl8192cu_txagc[chain]; 2894 2895 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2896 if (sc->regulatory == 0) { 2897 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 2898 power[ridx] = base->pwr[0][ridx]; 2899 } 2900 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 2901 if (sc->regulatory == 3) { 2902 power[ridx] = base->pwr[0][ridx]; 2903 /* Apply vendor limits. */ 2904 if (extc != NULL) 2905 max = rom->ht40_max_pwr[group]; 2906 else 2907 max = rom->ht20_max_pwr[group]; 2908 max = (max >> (chain * 4)) & 0xf; 2909 if (power[ridx] > max) 2910 power[ridx] = max; 2911 } else if (sc->regulatory == 1) { 2912 if (extc == NULL) 2913 power[ridx] = base->pwr[group][ridx]; 2914 } else if (sc->regulatory != 2) 2915 power[ridx] = base->pwr[0][ridx]; 2916 } 2917 2918 /* Compute per-CCK rate Tx power. */ 2919 cckpow = rom->cck_tx_pwr[chain][group]; 2920 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 2921 power[ridx] += cckpow; 2922 if (power[ridx] > R92C_MAX_TX_PWR) 2923 power[ridx] = R92C_MAX_TX_PWR; 2924 } 2925 2926 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2927 if (sc->ntxchains > 1) { 2928 /* Apply reduction for 2 spatial streams. */ 2929 diff = rom->ht40_2s_tx_pwr_diff[group]; 2930 diff = (diff >> (chain * 4)) & 0xf; 2931 htpow = (htpow > diff) ? htpow - diff : 0; 2932 } 2933 2934 /* Compute per-OFDM rate Tx power. */ 2935 diff = rom->ofdm_tx_pwr_diff[group]; 2936 diff = (diff >> (chain * 4)) & 0xf; 2937 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2938 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 2939 power[ridx] += ofdmpow; 2940 if (power[ridx] > R92C_MAX_TX_PWR) 2941 power[ridx] = R92C_MAX_TX_PWR; 2942 } 2943 2944 /* Compute per-MCS Tx power. */ 2945 if (extc == NULL) { 2946 diff = rom->ht20_tx_pwr_diff[group]; 2947 diff = (diff >> (chain * 4)) & 0xf; 2948 htpow += diff; /* HT40->HT20 correction. */ 2949 } 2950 for (ridx = 12; ridx <= 27; ridx++) { 2951 power[ridx] += htpow; 2952 if (power[ridx] > R92C_MAX_TX_PWR) 2953 power[ridx] = R92C_MAX_TX_PWR; 2954 } 2955#ifdef URTWN_DEBUG 2956 if (urtwn_debug >= 4) { 2957 /* Dump per-rate Tx power values. */ 2958 printf("Tx power for chain %d:\n", chain); 2959 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 2960 printf("Rate %d = %u\n", ridx, power[ridx]); 2961 } 2962#endif 2963} 2964 2965static void 2966urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 2967 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2968 uint16_t power[URTWN_RIDX_COUNT]) 2969{ 2970 struct ieee80211com *ic = &sc->sc_ic; 2971 uint16_t cckpow, ofdmpow, bw20pow, htpow; 2972 const struct urtwn_r88e_txpwr *base; 2973 int ridx, chan, group; 2974 2975 /* Determine channel group. */ 2976 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2977 if (chan <= 2) 2978 group = 0; 2979 else if (chan <= 5) 2980 group = 1; 2981 else if (chan <= 8) 2982 group = 2; 2983 else if (chan <= 11) 2984 group = 3; 2985 else if (chan <= 13) 2986 group = 4; 2987 else 2988 group = 5; 2989 2990 /* Get original Tx power based on board type and RF chain. */ 2991 base = &rtl8188eu_txagc[chain]; 2992 2993 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2994 if (sc->regulatory == 0) { 2995 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 2996 power[ridx] = base->pwr[0][ridx]; 2997 } 2998 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 2999 if (sc->regulatory == 3) 3000 power[ridx] = base->pwr[0][ridx]; 3001 else if (sc->regulatory == 1) { 3002 if (extc == NULL) 3003 power[ridx] = base->pwr[group][ridx]; 3004 } else if (sc->regulatory != 2) 3005 power[ridx] = base->pwr[0][ridx]; 3006 } 3007 3008 /* Compute per-CCK rate Tx power. */ 3009 cckpow = sc->cck_tx_pwr[group]; 3010 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3011 power[ridx] += cckpow; 3012 if (power[ridx] > R92C_MAX_TX_PWR) 3013 power[ridx] = R92C_MAX_TX_PWR; 3014 } 3015 3016 htpow = sc->ht40_tx_pwr[group]; 3017 3018 /* Compute per-OFDM rate Tx power. */ 3019 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3020 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3021 power[ridx] += ofdmpow; 3022 if (power[ridx] > R92C_MAX_TX_PWR) 3023 power[ridx] = R92C_MAX_TX_PWR; 3024 } 3025 3026 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3027 for (ridx = 12; ridx <= 27; ridx++) { 3028 power[ridx] += bw20pow; 3029 if (power[ridx] > R92C_MAX_TX_PWR) 3030 power[ridx] = R92C_MAX_TX_PWR; 3031 } 3032} 3033 3034static void 3035urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3036 struct ieee80211_channel *extc) 3037{ 3038 uint16_t power[URTWN_RIDX_COUNT]; 3039 int i; 3040 3041 for (i = 0; i < sc->ntxchains; i++) { 3042 /* Compute per-rate Tx power values. */ 3043 if (sc->chip & URTWN_CHIP_88E) 3044 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3045 else 3046 urtwn_get_txpower(sc, i, c, extc, power); 3047 /* Write per-rate Tx power values to hardware. */ 3048 urtwn_write_txpower(sc, i, power); 3049 } 3050} 3051 3052static void 3053urtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 3054{ 3055 uint32_t reg; 3056 3057 reg = urtwn_read_4(sc, R92C_RCR); 3058 if (enable) 3059 reg &= ~R92C_RCR_CBSSID_BCN; 3060 else 3061 reg |= R92C_RCR_CBSSID_BCN; 3062 urtwn_write_4(sc, R92C_RCR, reg); 3063} 3064 3065static void 3066urtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 3067{ 3068 uint32_t reg; 3069 3070 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3071 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3072 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3073 3074 if (!(sc->chip & URTWN_CHIP_88E)) { 3075 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3076 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3077 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3078 } 3079} 3080 3081static void 3082urtwn_scan_start(struct ieee80211com *ic) 3083{ 3084 struct urtwn_softc *sc = ic->ic_softc; 3085 3086 URTWN_LOCK(sc); 3087 /* Receive beacons / probe responses from any BSSID. */ 3088 urtwn_set_rx_bssid_all(sc, 1); 3089 /* Set gain for scanning. */ 3090 urtwn_set_gain(sc, 0x20); 3091 URTWN_UNLOCK(sc); 3092} 3093 3094static void 3095urtwn_scan_end(struct ieee80211com *ic) 3096{ 3097 struct urtwn_softc *sc = ic->ic_softc; 3098 3099 URTWN_LOCK(sc); 3100 /* Restore limitations. */ 3101 if (ic->ic_promisc == 0) 3102 urtwn_set_rx_bssid_all(sc, 0); 3103 /* Set gain under link. */ 3104 urtwn_set_gain(sc, 0x32); 3105 URTWN_UNLOCK(sc); 3106} 3107 3108static void 3109urtwn_set_channel(struct ieee80211com *ic) 3110{ 3111 struct urtwn_softc *sc = ic->ic_softc; 3112 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3113 3114 URTWN_LOCK(sc); 3115 if (vap->iv_state == IEEE80211_S_SCAN) { 3116 /* Make link LED blink during scan. */ 3117 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3118 } 3119 urtwn_set_chan(sc, ic->ic_curchan, NULL); 3120 URTWN_UNLOCK(sc); 3121} 3122 3123static void 3124urtwn_set_promisc(struct urtwn_softc *sc) 3125{ 3126 struct ieee80211com *ic = &sc->sc_ic; 3127 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3128 uint32_t rcr, mask1, mask2; 3129 3130 URTWN_ASSERT_LOCKED(sc); 3131 3132 if (vap->iv_opmode == IEEE80211_M_MONITOR) 3133 return; 3134 3135 mask1 = R92C_RCR_ACF | R92C_RCR_ADF | R92C_RCR_AMF | R92C_RCR_AAP; 3136 mask2 = R92C_RCR_APM; 3137 3138 if (vap->iv_state == IEEE80211_S_RUN) { 3139 switch (vap->iv_opmode) { 3140 case IEEE80211_M_STA: 3141 mask2 |= R92C_RCR_CBSSID_BCN | R92C_RCR_CBSSID_DATA; 3142 break; 3143 default: 3144 device_printf(sc->sc_dev, "%s: undefined opmode %d\n", 3145 __func__, vap->iv_opmode); 3146 return; 3147 } 3148 } 3149 3150 rcr = urtwn_read_4(sc, R92C_RCR); 3151 if (ic->ic_promisc == 0) 3152 rcr = (rcr & ~mask1) | mask2; 3153 else 3154 rcr = (rcr & ~mask2) | mask1; 3155 urtwn_write_4(sc, R92C_RCR, rcr); 3156} 3157 3158static void 3159urtwn_update_promisc(struct ieee80211com *ic) 3160{ 3161 struct urtwn_softc *sc = ic->ic_softc; 3162 3163 URTWN_LOCK(sc); 3164 if (sc->sc_flags & URTWN_RUNNING) 3165 urtwn_set_promisc(sc); 3166 URTWN_UNLOCK(sc); 3167} 3168 3169static void 3170urtwn_update_mcast(struct ieee80211com *ic) 3171{ 3172 /* XXX do nothing? */ 3173} 3174 3175static void 3176urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3177 struct ieee80211_channel *extc) 3178{ 3179 struct ieee80211com *ic = &sc->sc_ic; 3180 uint32_t reg; 3181 u_int chan; 3182 int i; 3183 3184 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3185 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3186 device_printf(sc->sc_dev, 3187 "%s: invalid channel %x\n", __func__, chan); 3188 return; 3189 } 3190 3191 /* Set Tx power for this new channel. */ 3192 urtwn_set_txpower(sc, c, extc); 3193 3194 for (i = 0; i < sc->nrxchains; i++) { 3195 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3196 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3197 } 3198#ifndef IEEE80211_NO_HT 3199 if (extc != NULL) { 3200 /* Is secondary channel below or above primary? */ 3201 int prichlo = c->ic_freq < extc->ic_freq; 3202 3203 urtwn_write_1(sc, R92C_BWOPMODE, 3204 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3205 3206 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3207 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3208 urtwn_write_1(sc, R92C_RRSR + 2, reg); 3209 3210 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3211 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3212 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3213 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3214 3215 /* Set CCK side band. */ 3216 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3217 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3218 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3219 3220 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3221 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3222 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3223 3224 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3225 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3226 ~R92C_FPGA0_ANAPARAM2_CBW20); 3227 3228 reg = urtwn_bb_read(sc, 0x818); 3229 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3230 urtwn_bb_write(sc, 0x818, reg); 3231 3232 /* Select 40MHz bandwidth. */ 3233 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3234 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3235 } else 3236#endif 3237 { 3238 urtwn_write_1(sc, R92C_BWOPMODE, 3239 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3240 3241 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3242 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3243 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3244 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3245 3246 if (!(sc->chip & URTWN_CHIP_88E)) { 3247 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3248 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3249 R92C_FPGA0_ANAPARAM2_CBW20); 3250 } 3251 3252 /* Select 20MHz bandwidth. */ 3253 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3254 (sc->rf_chnlbw[0] & ~0xfff) | chan | 3255 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3256 R92C_RF_CHNLBW_BW20)); 3257 } 3258} 3259 3260static void 3261urtwn_iq_calib(struct urtwn_softc *sc) 3262{ 3263 /* TODO */ 3264} 3265 3266static void 3267urtwn_lc_calib(struct urtwn_softc *sc) 3268{ 3269 uint32_t rf_ac[2]; 3270 uint8_t txmode; 3271 int i; 3272 3273 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3274 if ((txmode & 0x70) != 0) { 3275 /* Disable all continuous Tx. */ 3276 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3277 3278 /* Set RF mode to standby mode. */ 3279 for (i = 0; i < sc->nrxchains; i++) { 3280 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3281 urtwn_rf_write(sc, i, R92C_RF_AC, 3282 RW(rf_ac[i], R92C_RF_AC_MODE, 3283 R92C_RF_AC_MODE_STANDBY)); 3284 } 3285 } else { 3286 /* Block all Tx queues. */ 3287 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3288 } 3289 /* Start calibration. */ 3290 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3291 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3292 3293 /* Give calibration the time to complete. */ 3294 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3295 3296 /* Restore configuration. */ 3297 if ((txmode & 0x70) != 0) { 3298 /* Restore Tx mode. */ 3299 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3300 /* Restore RF mode. */ 3301 for (i = 0; i < sc->nrxchains; i++) 3302 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3303 } else { 3304 /* Unblock all Tx queues. */ 3305 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3306 } 3307} 3308 3309static void 3310urtwn_init(struct urtwn_softc *sc) 3311{ 3312 struct ieee80211com *ic = &sc->sc_ic; 3313 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3314 uint8_t macaddr[IEEE80211_ADDR_LEN]; 3315 uint32_t reg; 3316 int error; 3317 3318 URTWN_ASSERT_LOCKED(sc); 3319 3320 if (sc->sc_flags & URTWN_RUNNING) 3321 urtwn_stop(sc); 3322 3323 /* Init firmware commands ring. */ 3324 sc->fwcur = 0; 3325 3326 /* Allocate Tx/Rx buffers. */ 3327 error = urtwn_alloc_rx_list(sc); 3328 if (error != 0) 3329 goto fail; 3330 3331 error = urtwn_alloc_tx_list(sc); 3332 if (error != 0) 3333 goto fail; 3334 3335 /* Power on adapter. */ 3336 error = urtwn_power_on(sc); 3337 if (error != 0) 3338 goto fail; 3339 3340 /* Initialize DMA. */ 3341 error = urtwn_dma_init(sc); 3342 if (error != 0) 3343 goto fail; 3344 3345 /* Set info size in Rx descriptors (in 64-bit words). */ 3346 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3347 3348 /* Init interrupts. */ 3349 if (sc->chip & URTWN_CHIP_88E) { 3350 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3351 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3352 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3353 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3354 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3355 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3356 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3357 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3358 } else { 3359 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3360 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3361 } 3362 3363 /* Set MAC address. */ 3364 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3365 urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3366 3367 /* Set initial network type. */ 3368 urtwn_set_mode(sc, R92C_MSR_INFRA); 3369 3370 /* Initialize Rx filter. */ 3371 urtwn_rxfilter_init(sc); 3372 3373 /* Set response rate. */ 3374 reg = urtwn_read_4(sc, R92C_RRSR); 3375 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3376 urtwn_write_4(sc, R92C_RRSR, reg); 3377 3378 /* Set short/long retry limits. */ 3379 urtwn_write_2(sc, R92C_RL, 3380 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3381 3382 /* Initialize EDCA parameters. */ 3383 urtwn_edca_init(sc); 3384 3385 /* Setup rate fallback. */ 3386 if (!(sc->chip & URTWN_CHIP_88E)) { 3387 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3388 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3389 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3390 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3391 } 3392 3393 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3394 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3395 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3396 /* Set ACK timeout. */ 3397 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3398 3399 /* Setup USB aggregation. */ 3400 reg = urtwn_read_4(sc, R92C_TDECTRL); 3401 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3402 urtwn_write_4(sc, R92C_TDECTRL, reg); 3403 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3404 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3405 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3406 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3407 if (sc->chip & URTWN_CHIP_88E) 3408 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3409 else { 3410 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3411 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3412 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3413 R92C_USB_SPECIAL_OPTION_AGG_EN); 3414 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3415 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3416 } 3417 3418 /* Initialize beacon parameters. */ 3419 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3420 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3421 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3422 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3423 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3424 3425 if (!(sc->chip & URTWN_CHIP_88E)) { 3426 /* Setup AMPDU aggregation. */ 3427 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3428 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3429 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3430 3431 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3432 } 3433 3434 /* Load 8051 microcode. */ 3435 error = urtwn_load_firmware(sc); 3436 if (error != 0) 3437 goto fail; 3438 3439 /* Initialize MAC/BB/RF blocks. */ 3440 urtwn_mac_init(sc); 3441 urtwn_bb_init(sc); 3442 urtwn_rf_init(sc); 3443 3444 /* Reinitialize Rx filter (D3845 is not committed yet). */ 3445 urtwn_rxfilter_init(sc); 3446 3447 if (sc->chip & URTWN_CHIP_88E) { 3448 urtwn_write_2(sc, R92C_CR, 3449 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3450 R92C_CR_MACRXEN); 3451 } 3452 3453 /* Turn CCK and OFDM blocks on. */ 3454 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3455 reg |= R92C_RFMOD_CCK_EN; 3456 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3457 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3458 reg |= R92C_RFMOD_OFDM_EN; 3459 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3460 3461 /* Clear per-station keys table. */ 3462 urtwn_cam_init(sc); 3463 3464 /* Enable hardware sequence numbering. */ 3465 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3466 3467 /* Perform LO and IQ calibrations. */ 3468 urtwn_iq_calib(sc); 3469 /* Perform LC calibration. */ 3470 urtwn_lc_calib(sc); 3471 3472 /* Fix USB interference issue. */ 3473 if (!(sc->chip & URTWN_CHIP_88E)) { 3474 urtwn_write_1(sc, 0xfe40, 0xe0); 3475 urtwn_write_1(sc, 0xfe41, 0x8d); 3476 urtwn_write_1(sc, 0xfe42, 0x80); 3477 3478 urtwn_pa_bias_init(sc); 3479 } 3480 3481 /* Initialize GPIO setting. */ 3482 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3483 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3484 3485 /* Fix for lower temperature. */ 3486 if (!(sc->chip & URTWN_CHIP_88E)) 3487 urtwn_write_1(sc, 0x15, 0xe9); 3488 3489 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3490 3491 sc->sc_flags |= URTWN_RUNNING; 3492 3493 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3494fail: 3495 return; 3496} 3497 3498static void 3499urtwn_stop(struct urtwn_softc *sc) 3500{ 3501 3502 URTWN_ASSERT_LOCKED(sc); 3503 sc->sc_flags &= ~URTWN_RUNNING; 3504 callout_stop(&sc->sc_watchdog_ch); 3505 urtwn_abort_xfers(sc); 3506 3507 urtwn_drain_mbufq(sc); 3508} 3509 3510static void 3511urtwn_abort_xfers(struct urtwn_softc *sc) 3512{ 3513 int i; 3514 3515 URTWN_ASSERT_LOCKED(sc); 3516 3517 /* abort any pending transfers */ 3518 for (i = 0; i < URTWN_N_TRANSFER; i++) 3519 usbd_transfer_stop(sc->sc_xfer[i]); 3520} 3521 3522static int 3523urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3524 const struct ieee80211_bpf_params *params) 3525{ 3526 struct ieee80211com *ic = ni->ni_ic; 3527 struct urtwn_softc *sc = ic->ic_softc; 3528 struct urtwn_data *bf; 3529 3530 /* prevent management frames from being sent if we're not ready */ 3531 if (!(sc->sc_flags & URTWN_RUNNING)) { 3532 m_freem(m); 3533 return (ENETDOWN); 3534 } 3535 URTWN_LOCK(sc); 3536 bf = urtwn_getbuf(sc); 3537 if (bf == NULL) { 3538 m_freem(m); 3539 URTWN_UNLOCK(sc); 3540 return (ENOBUFS); 3541 } 3542 3543 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3544 m_freem(m); 3545 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3546 URTWN_UNLOCK(sc); 3547 return (EIO); 3548 } 3549 sc->sc_txtimer = 5; 3550 URTWN_UNLOCK(sc); 3551 3552 return (0); 3553} 3554 3555static void 3556urtwn_ms_delay(struct urtwn_softc *sc) 3557{ 3558 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3559} 3560 3561static device_method_t urtwn_methods[] = { 3562 /* Device interface */ 3563 DEVMETHOD(device_probe, urtwn_match), 3564 DEVMETHOD(device_attach, urtwn_attach), 3565 DEVMETHOD(device_detach, urtwn_detach), 3566 3567 DEVMETHOD_END 3568}; 3569 3570static driver_t urtwn_driver = { 3571 "urtwn", 3572 urtwn_methods, 3573 sizeof(struct urtwn_softc) 3574}; 3575 3576static devclass_t urtwn_devclass; 3577 3578DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3579MODULE_DEPEND(urtwn, usb, 1, 1, 1); 3580MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3581MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3582MODULE_VERSION(urtwn, 1); 3583