if_urtwn.c revision 290048
1251538Srpaulo/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2251538Srpaulo 3251538Srpaulo/*- 4251538Srpaulo * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5264912Skevlo * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6251538Srpaulo * 7251538Srpaulo * Permission to use, copy, modify, and distribute this software for any 8251538Srpaulo * purpose with or without fee is hereby granted, provided that the above 9251538Srpaulo * copyright notice and this permission notice appear in all copies. 10251538Srpaulo * 11251538Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12251538Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13251538Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14251538Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15251538Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16251538Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17251538Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18251538Srpaulo */ 19251538Srpaulo 20251538Srpaulo#include <sys/cdefs.h> 21251538Srpaulo__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 290048 2015-10-27 14:21:24Z avos $"); 22251538Srpaulo 23251538Srpaulo/* 24264912Skevlo * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25251538Srpaulo */ 26251538Srpaulo 27288353Sadrian#include "opt_wlan.h" 28288353Sadrian 29251538Srpaulo#include <sys/param.h> 30251538Srpaulo#include <sys/sockio.h> 31251538Srpaulo#include <sys/sysctl.h> 32251538Srpaulo#include <sys/lock.h> 33251538Srpaulo#include <sys/mutex.h> 34251538Srpaulo#include <sys/mbuf.h> 35251538Srpaulo#include <sys/kernel.h> 36251538Srpaulo#include <sys/socket.h> 37251538Srpaulo#include <sys/systm.h> 38251538Srpaulo#include <sys/malloc.h> 39251538Srpaulo#include <sys/module.h> 40251538Srpaulo#include <sys/bus.h> 41251538Srpaulo#include <sys/endian.h> 42251538Srpaulo#include <sys/linker.h> 43251538Srpaulo#include <sys/firmware.h> 44251538Srpaulo#include <sys/kdb.h> 45251538Srpaulo 46251538Srpaulo#include <machine/bus.h> 47251538Srpaulo#include <machine/resource.h> 48251538Srpaulo#include <sys/rman.h> 49251538Srpaulo 50251538Srpaulo#include <net/bpf.h> 51251538Srpaulo#include <net/if.h> 52257176Sglebius#include <net/if_var.h> 53251538Srpaulo#include <net/if_arp.h> 54251538Srpaulo#include <net/ethernet.h> 55251538Srpaulo#include <net/if_dl.h> 56251538Srpaulo#include <net/if_media.h> 57251538Srpaulo#include <net/if_types.h> 58251538Srpaulo 59251538Srpaulo#include <netinet/in.h> 60251538Srpaulo#include <netinet/in_systm.h> 61251538Srpaulo#include <netinet/in_var.h> 62251538Srpaulo#include <netinet/if_ether.h> 63251538Srpaulo#include <netinet/ip.h> 64251538Srpaulo 65251538Srpaulo#include <net80211/ieee80211_var.h> 66288088Sadrian#include <net80211/ieee80211_input.h> 67251538Srpaulo#include <net80211/ieee80211_regdomain.h> 68251538Srpaulo#include <net80211/ieee80211_radiotap.h> 69251538Srpaulo#include <net80211/ieee80211_ratectl.h> 70251538Srpaulo 71251538Srpaulo#include <dev/usb/usb.h> 72251538Srpaulo#include <dev/usb/usbdi.h> 73251538Srpaulo#include "usbdevs.h" 74251538Srpaulo 75251538Srpaulo#define USB_DEBUG_VAR urtwn_debug 76251538Srpaulo#include <dev/usb/usb_debug.h> 77251538Srpaulo 78251538Srpaulo#include <dev/usb/wlan/if_urtwnreg.h> 79289167Sadrian#include <dev/usb/wlan/if_urtwnvar.h> 80251538Srpaulo 81251538Srpaulo#ifdef USB_DEBUG 82251538Srpaulostatic int urtwn_debug = 0; 83251538Srpaulo 84251538SrpauloSYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 85276701ShselaskySYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 86251538Srpaulo "Debug level"); 87251538Srpaulo#endif 88251538Srpaulo 89288088Sadrian#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 90251538Srpaulo 91251538Srpaulo/* various supported device vendors/products */ 92251596Srpaulostatic const STRUCT_USB_HOST_ID urtwn_devs[] = { 93251538Srpaulo#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 94264912Skevlo#define URTWN_RTL8188E_DEV(v,p) \ 95264912Skevlo { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 96264912Skevlo#define URTWN_RTL8188E 1 97251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_1), 98251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_2), 99251538Srpaulo URTWN_DEV(ABOCOM, RTL8192CU), 100251538Srpaulo URTWN_DEV(ASUS, RTL8192CU), 101266721Skevlo URTWN_DEV(ASUS, USBN10NANO), 102251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_1), 103251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_2), 104251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CU), 105251538Srpaulo URTWN_DEV(BELKIN, F7D2102), 106251538Srpaulo URTWN_DEV(BELKIN, RTL8188CU), 107251538Srpaulo URTWN_DEV(BELKIN, RTL8192CU), 108251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_1), 109251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_2), 110251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_3), 111251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_4), 112251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_5), 113251538Srpaulo URTWN_DEV(COREGA, RTL8192CU), 114251538Srpaulo URTWN_DEV(DLINK, RTL8188CU), 115251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_1), 116251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_2), 117251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_3), 118252196Skevlo URTWN_DEV(DLINK, DWA131B), 119251538Srpaulo URTWN_DEV(EDIMAX, EW7811UN), 120251538Srpaulo URTWN_DEV(EDIMAX, RTL8192CU), 121251538Srpaulo URTWN_DEV(FEIXUN, RTL8188CU), 122251538Srpaulo URTWN_DEV(FEIXUN, RTL8192CU), 123251538Srpaulo URTWN_DEV(GUILLEMOT, HWNUP150), 124251538Srpaulo URTWN_DEV(HAWKING, RTL8192CU), 125251538Srpaulo URTWN_DEV(HP3, RTL8188CU), 126251538Srpaulo URTWN_DEV(NETGEAR, WNA1000M), 127251538Srpaulo URTWN_DEV(NETGEAR, RTL8192CU), 128251538Srpaulo URTWN_DEV(NETGEAR4, RTL8188CU), 129251538Srpaulo URTWN_DEV(NOVATECH, RTL8188CU), 130251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_1), 131251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_2), 132251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_3), 133251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_4), 134251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CUS), 135251538Srpaulo URTWN_DEV(PLANEX2, RTL8192CU), 136251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_0), 137251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_1), 138251538Srpaulo URTWN_DEV(REALTEK, RTL8188CTV), 139251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_0), 140251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_1), 141251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_2), 142282119Skevlo URTWN_DEV(REALTEK, RTL8188CU_3), 143251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_COMBO), 144251538Srpaulo URTWN_DEV(REALTEK, RTL8188CUS), 145251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_1), 146251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_2), 147272410Shselasky URTWN_DEV(REALTEK, RTL8188RU_3), 148251538Srpaulo URTWN_DEV(REALTEK, RTL8191CU), 149251538Srpaulo URTWN_DEV(REALTEK, RTL8192CE), 150251538Srpaulo URTWN_DEV(REALTEK, RTL8192CU), 151251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_1), 152251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_2), 153251538Srpaulo URTWN_DEV(SITECOMEU, RTL8192CU), 154251538Srpaulo URTWN_DEV(TRENDNET, RTL8188CU), 155251538Srpaulo URTWN_DEV(TRENDNET, RTL8192CU), 156251538Srpaulo URTWN_DEV(ZYXEL, RTL8192CU), 157264912Skevlo /* URTWN_RTL8188E */ 158273589Skevlo URTWN_RTL8188E_DEV(DLINK, DWA123D1), 159270191Skevlo URTWN_RTL8188E_DEV(DLINK, DWA125D1), 160273589Skevlo URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 161264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 162264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 163264912Skevlo#undef URTWN_RTL8188E_DEV 164251538Srpaulo#undef URTWN_DEV 165251538Srpaulo}; 166251538Srpaulo 167251538Srpaulostatic device_probe_t urtwn_match; 168251538Srpaulostatic device_attach_t urtwn_attach; 169251538Srpaulostatic device_detach_t urtwn_detach; 170251538Srpaulo 171251538Srpaulostatic usb_callback_t urtwn_bulk_tx_callback; 172251538Srpaulostatic usb_callback_t urtwn_bulk_rx_callback; 173251538Srpaulo 174288353Sadrianstatic void urtwn_drain_mbufq(struct urtwn_softc *sc); 175287197Sglebiusstatic usb_error_t urtwn_do_request(struct urtwn_softc *, 176287197Sglebius struct usb_device_request *, void *); 177251538Srpaulostatic struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 178251538Srpaulo const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 179251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN], 180251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN]); 181251538Srpaulostatic void urtwn_vap_delete(struct ieee80211vap *); 182281069Srpaulostatic struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 183251538Srpaulo int *); 184281069Srpaulostatic struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 185251538Srpaulo int *, int8_t *); 186289891Savosstatic void urtwn_txeof(struct urtwn_softc *, struct urtwn_data *, 187289891Savos int); 188281069Srpaulostatic int urtwn_alloc_list(struct urtwn_softc *, 189251538Srpaulo struct urtwn_data[], int, int); 190251538Srpaulostatic int urtwn_alloc_rx_list(struct urtwn_softc *); 191251538Srpaulostatic int urtwn_alloc_tx_list(struct urtwn_softc *); 192251538Srpaulostatic void urtwn_free_list(struct urtwn_softc *, 193251538Srpaulo struct urtwn_data data[], int); 194289066Skevlostatic void urtwn_free_rx_list(struct urtwn_softc *); 195289066Skevlostatic void urtwn_free_tx_list(struct urtwn_softc *); 196251538Srpaulostatic struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 197251538Srpaulostatic struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 198281069Srpaulostatic int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 199251538Srpaulo uint8_t *, int); 200251538Srpaulostatic void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 201251538Srpaulostatic void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 202251538Srpaulostatic void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 203281069Srpaulostatic int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 204251538Srpaulo uint8_t *, int); 205251538Srpaulostatic uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 206251538Srpaulostatic uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 207251538Srpaulostatic uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 208281069Srpaulostatic int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 209251538Srpaulo const void *, int); 210264912Skevlostatic void urtwn_r92c_rf_write(struct urtwn_softc *, int, 211264912Skevlo uint8_t, uint32_t); 212281069Srpaulostatic void urtwn_r88e_rf_write(struct urtwn_softc *, int, 213264912Skevlo uint8_t, uint32_t); 214251538Srpaulostatic uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 215281069Srpaulostatic int urtwn_llt_write(struct urtwn_softc *, uint32_t, 216251538Srpaulo uint32_t); 217251538Srpaulostatic uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 218251538Srpaulostatic void urtwn_efuse_read(struct urtwn_softc *); 219264912Skevlostatic void urtwn_efuse_switch_power(struct urtwn_softc *); 220251538Srpaulostatic int urtwn_read_chipid(struct urtwn_softc *); 221251538Srpaulostatic void urtwn_read_rom(struct urtwn_softc *); 222264912Skevlostatic void urtwn_r88e_read_rom(struct urtwn_softc *); 223251538Srpaulostatic int urtwn_ra_init(struct urtwn_softc *); 224251538Srpaulostatic void urtwn_tsf_sync_enable(struct urtwn_softc *); 225251538Srpaulostatic void urtwn_set_led(struct urtwn_softc *, int, int); 226289811Savosstatic void urtwn_set_mode(struct urtwn_softc *, uint8_t); 227281069Srpaulostatic int urtwn_newstate(struct ieee80211vap *, 228251538Srpaulo enum ieee80211_state, int); 229251538Srpaulostatic void urtwn_watchdog(void *); 230251538Srpaulostatic void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 231251538Srpaulostatic int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 232264912Skevlostatic int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 233251538Srpaulostatic int urtwn_tx_start(struct urtwn_softc *, 234251538Srpaulo struct ieee80211_node *, struct mbuf *, 235251538Srpaulo struct urtwn_data *); 236287197Sglebiusstatic int urtwn_transmit(struct ieee80211com *, struct mbuf *); 237287197Sglebiusstatic void urtwn_start(struct urtwn_softc *); 238287197Sglebiusstatic void urtwn_parent(struct ieee80211com *); 239264912Skevlostatic int urtwn_r92c_power_on(struct urtwn_softc *); 240264912Skevlostatic int urtwn_r88e_power_on(struct urtwn_softc *); 241251538Srpaulostatic int urtwn_llt_init(struct urtwn_softc *); 242251538Srpaulostatic void urtwn_fw_reset(struct urtwn_softc *); 243264912Skevlostatic void urtwn_r88e_fw_reset(struct urtwn_softc *); 244281069Srpaulostatic int urtwn_fw_loadpage(struct urtwn_softc *, int, 245251538Srpaulo const uint8_t *, int); 246251538Srpaulostatic int urtwn_load_firmware(struct urtwn_softc *); 247264912Skevlostatic int urtwn_r92c_dma_init(struct urtwn_softc *); 248264912Skevlostatic int urtwn_r88e_dma_init(struct urtwn_softc *); 249251538Srpaulostatic void urtwn_mac_init(struct urtwn_softc *); 250251538Srpaulostatic void urtwn_bb_init(struct urtwn_softc *); 251251538Srpaulostatic void urtwn_rf_init(struct urtwn_softc *); 252251538Srpaulostatic void urtwn_cam_init(struct urtwn_softc *); 253251538Srpaulostatic void urtwn_pa_bias_init(struct urtwn_softc *); 254251538Srpaulostatic void urtwn_rxfilter_init(struct urtwn_softc *); 255251538Srpaulostatic void urtwn_edca_init(struct urtwn_softc *); 256281069Srpaulostatic void urtwn_write_txpower(struct urtwn_softc *, int, 257251538Srpaulo uint16_t[]); 258251538Srpaulostatic void urtwn_get_txpower(struct urtwn_softc *, int, 259281069Srpaulo struct ieee80211_channel *, 260251538Srpaulo struct ieee80211_channel *, uint16_t[]); 261264912Skevlostatic void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 262281069Srpaulo struct ieee80211_channel *, 263264912Skevlo struct ieee80211_channel *, uint16_t[]); 264251538Srpaulostatic void urtwn_set_txpower(struct urtwn_softc *, 265281069Srpaulo struct ieee80211_channel *, 266251538Srpaulo struct ieee80211_channel *); 267290048Savosstatic void urtwn_set_rx_bssid_all(struct urtwn_softc *, int); 268290048Savosstatic void urtwn_set_gain(struct urtwn_softc *, uint8_t); 269251538Srpaulostatic void urtwn_scan_start(struct ieee80211com *); 270251538Srpaulostatic void urtwn_scan_end(struct ieee80211com *); 271251538Srpaulostatic void urtwn_set_channel(struct ieee80211com *); 272289066Skevlostatic void urtwn_update_mcast(struct ieee80211com *); 273251538Srpaulostatic void urtwn_set_chan(struct urtwn_softc *, 274281069Srpaulo struct ieee80211_channel *, 275251538Srpaulo struct ieee80211_channel *); 276251538Srpaulostatic void urtwn_iq_calib(struct urtwn_softc *); 277251538Srpaulostatic void urtwn_lc_calib(struct urtwn_softc *); 278287197Sglebiusstatic void urtwn_init(struct urtwn_softc *); 279287197Sglebiusstatic void urtwn_stop(struct urtwn_softc *); 280251538Srpaulostatic void urtwn_abort_xfers(struct urtwn_softc *); 281251538Srpaulostatic int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 282251538Srpaulo const struct ieee80211_bpf_params *); 283266472Shselaskystatic void urtwn_ms_delay(struct urtwn_softc *); 284251538Srpaulo 285251538Srpaulo/* Aliases. */ 286251538Srpaulo#define urtwn_bb_write urtwn_write_4 287251538Srpaulo#define urtwn_bb_read urtwn_read_4 288251538Srpaulo 289251538Srpaulostatic const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 290251538Srpaulo [URTWN_BULK_RX] = { 291251538Srpaulo .type = UE_BULK, 292251538Srpaulo .endpoint = UE_ADDR_ANY, 293251538Srpaulo .direction = UE_DIR_IN, 294251538Srpaulo .bufsize = URTWN_RXBUFSZ, 295251538Srpaulo .flags = { 296251538Srpaulo .pipe_bof = 1, 297251538Srpaulo .short_xfer_ok = 1 298251538Srpaulo }, 299251538Srpaulo .callback = urtwn_bulk_rx_callback, 300251538Srpaulo }, 301251538Srpaulo [URTWN_BULK_TX_BE] = { 302251538Srpaulo .type = UE_BULK, 303251538Srpaulo .endpoint = 0x03, 304251538Srpaulo .direction = UE_DIR_OUT, 305251538Srpaulo .bufsize = URTWN_TXBUFSZ, 306251538Srpaulo .flags = { 307251538Srpaulo .ext_buffer = 1, 308251538Srpaulo .pipe_bof = 1, 309251538Srpaulo .force_short_xfer = 1 310251538Srpaulo }, 311251538Srpaulo .callback = urtwn_bulk_tx_callback, 312251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 313251538Srpaulo }, 314251538Srpaulo [URTWN_BULK_TX_BK] = { 315251538Srpaulo .type = UE_BULK, 316251538Srpaulo .endpoint = 0x03, 317251538Srpaulo .direction = UE_DIR_OUT, 318251538Srpaulo .bufsize = URTWN_TXBUFSZ, 319251538Srpaulo .flags = { 320251538Srpaulo .ext_buffer = 1, 321251538Srpaulo .pipe_bof = 1, 322251538Srpaulo .force_short_xfer = 1, 323251538Srpaulo }, 324251538Srpaulo .callback = urtwn_bulk_tx_callback, 325251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 326251538Srpaulo }, 327251538Srpaulo [URTWN_BULK_TX_VI] = { 328251538Srpaulo .type = UE_BULK, 329251538Srpaulo .endpoint = 0x02, 330251538Srpaulo .direction = UE_DIR_OUT, 331251538Srpaulo .bufsize = URTWN_TXBUFSZ, 332251538Srpaulo .flags = { 333251538Srpaulo .ext_buffer = 1, 334251538Srpaulo .pipe_bof = 1, 335251538Srpaulo .force_short_xfer = 1 336251538Srpaulo }, 337251538Srpaulo .callback = urtwn_bulk_tx_callback, 338251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 339251538Srpaulo }, 340251538Srpaulo [URTWN_BULK_TX_VO] = { 341251538Srpaulo .type = UE_BULK, 342251538Srpaulo .endpoint = 0x02, 343251538Srpaulo .direction = UE_DIR_OUT, 344251538Srpaulo .bufsize = URTWN_TXBUFSZ, 345251538Srpaulo .flags = { 346251538Srpaulo .ext_buffer = 1, 347251538Srpaulo .pipe_bof = 1, 348251538Srpaulo .force_short_xfer = 1 349251538Srpaulo }, 350251538Srpaulo .callback = urtwn_bulk_tx_callback, 351251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 352251538Srpaulo }, 353251538Srpaulo}; 354251538Srpaulo 355251538Srpaulostatic int 356251538Srpaulourtwn_match(device_t self) 357251538Srpaulo{ 358251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 359251538Srpaulo 360251538Srpaulo if (uaa->usb_mode != USB_MODE_HOST) 361251538Srpaulo return (ENXIO); 362251538Srpaulo if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 363251538Srpaulo return (ENXIO); 364251538Srpaulo if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 365251538Srpaulo return (ENXIO); 366251538Srpaulo 367251538Srpaulo return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 368251538Srpaulo} 369251538Srpaulo 370251538Srpaulostatic int 371251538Srpaulourtwn_attach(device_t self) 372251538Srpaulo{ 373251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 374251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 375287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 376251538Srpaulo uint8_t iface_index, bands; 377251538Srpaulo int error; 378251538Srpaulo 379251538Srpaulo device_set_usb_desc(self); 380251538Srpaulo sc->sc_udev = uaa->device; 381251538Srpaulo sc->sc_dev = self; 382264912Skevlo if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 383264912Skevlo sc->chip |= URTWN_CHIP_88E; 384251538Srpaulo 385251538Srpaulo mtx_init(&sc->sc_mtx, device_get_nameunit(self), 386251538Srpaulo MTX_NETWORK_LOCK, MTX_DEF); 387251538Srpaulo callout_init(&sc->sc_watchdog_ch, 0); 388287197Sglebius mbufq_init(&sc->sc_snd, ifqmaxlen); 389251538Srpaulo 390251538Srpaulo iface_index = URTWN_IFACE_INDEX; 391251538Srpaulo error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 392251538Srpaulo urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 393251538Srpaulo if (error) { 394251538Srpaulo device_printf(self, "could not allocate USB transfers, " 395251538Srpaulo "err=%s\n", usbd_errstr(error)); 396251538Srpaulo goto detach; 397251538Srpaulo } 398251538Srpaulo 399251538Srpaulo URTWN_LOCK(sc); 400251538Srpaulo 401251538Srpaulo error = urtwn_read_chipid(sc); 402251538Srpaulo if (error) { 403251538Srpaulo device_printf(sc->sc_dev, "unsupported test chip\n"); 404251538Srpaulo URTWN_UNLOCK(sc); 405251538Srpaulo goto detach; 406251538Srpaulo } 407251538Srpaulo 408251538Srpaulo /* Determine number of Tx/Rx chains. */ 409251538Srpaulo if (sc->chip & URTWN_CHIP_92C) { 410251538Srpaulo sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 411251538Srpaulo sc->nrxchains = 2; 412251538Srpaulo } else { 413251538Srpaulo sc->ntxchains = 1; 414251538Srpaulo sc->nrxchains = 1; 415251538Srpaulo } 416251538Srpaulo 417264912Skevlo if (sc->chip & URTWN_CHIP_88E) 418264912Skevlo urtwn_r88e_read_rom(sc); 419264912Skevlo else 420264912Skevlo urtwn_read_rom(sc); 421264912Skevlo 422251538Srpaulo device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 423251538Srpaulo (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 424264912Skevlo (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 425251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 426251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 427251538Srpaulo "8188CUS", sc->ntxchains, sc->nrxchains); 428251538Srpaulo 429251538Srpaulo URTWN_UNLOCK(sc); 430251538Srpaulo 431283537Sglebius ic->ic_softc = sc; 432283527Sglebius ic->ic_name = device_get_nameunit(self); 433251538Srpaulo ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 434251538Srpaulo ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 435251538Srpaulo 436251538Srpaulo /* set device capabilities */ 437251538Srpaulo ic->ic_caps = 438251538Srpaulo IEEE80211_C_STA /* station mode */ 439251538Srpaulo | IEEE80211_C_MONITOR /* monitor mode */ 440251538Srpaulo | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 441251538Srpaulo | IEEE80211_C_SHSLOT /* short slot time supported */ 442251538Srpaulo | IEEE80211_C_BGSCAN /* capable of bg scanning */ 443251538Srpaulo | IEEE80211_C_WPA /* 802.11i */ 444251538Srpaulo ; 445251538Srpaulo 446251538Srpaulo bands = 0; 447251538Srpaulo setbit(&bands, IEEE80211_MODE_11B); 448251538Srpaulo setbit(&bands, IEEE80211_MODE_11G); 449251538Srpaulo ieee80211_init_channels(ic, NULL, &bands); 450251538Srpaulo 451287197Sglebius ieee80211_ifattach(ic); 452251538Srpaulo ic->ic_raw_xmit = urtwn_raw_xmit; 453251538Srpaulo ic->ic_scan_start = urtwn_scan_start; 454251538Srpaulo ic->ic_scan_end = urtwn_scan_end; 455251538Srpaulo ic->ic_set_channel = urtwn_set_channel; 456287197Sglebius ic->ic_transmit = urtwn_transmit; 457287197Sglebius ic->ic_parent = urtwn_parent; 458251538Srpaulo ic->ic_vap_create = urtwn_vap_create; 459251538Srpaulo ic->ic_vap_delete = urtwn_vap_delete; 460251538Srpaulo ic->ic_update_mcast = urtwn_update_mcast; 461251538Srpaulo 462281069Srpaulo ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 463251538Srpaulo sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 464251538Srpaulo &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 465251538Srpaulo URTWN_RX_RADIOTAP_PRESENT); 466251538Srpaulo 467251538Srpaulo if (bootverbose) 468251538Srpaulo ieee80211_announce(ic); 469251538Srpaulo 470251538Srpaulo return (0); 471251538Srpaulo 472251538Srpaulodetach: 473251538Srpaulo urtwn_detach(self); 474251538Srpaulo return (ENXIO); /* failure */ 475251538Srpaulo} 476251538Srpaulo 477251538Srpaulostatic int 478251538Srpaulourtwn_detach(device_t self) 479251538Srpaulo{ 480251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 481287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 482263153Skevlo unsigned int x; 483281069Srpaulo 484263153Skevlo /* Prevent further ioctls. */ 485263153Skevlo URTWN_LOCK(sc); 486263153Skevlo sc->sc_flags |= URTWN_DETACHED; 487287197Sglebius urtwn_stop(sc); 488263153Skevlo URTWN_UNLOCK(sc); 489251538Srpaulo 490251538Srpaulo callout_drain(&sc->sc_watchdog_ch); 491251538Srpaulo 492288353Sadrian /* stop all USB transfers */ 493288353Sadrian usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 494288353Sadrian 495263153Skevlo /* Prevent further allocations from RX/TX data lists. */ 496263153Skevlo URTWN_LOCK(sc); 497263153Skevlo STAILQ_INIT(&sc->sc_tx_active); 498263153Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 499263153Skevlo STAILQ_INIT(&sc->sc_tx_pending); 500263153Skevlo 501263153Skevlo STAILQ_INIT(&sc->sc_rx_active); 502263153Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 503263153Skevlo URTWN_UNLOCK(sc); 504263153Skevlo 505263153Skevlo /* drain USB transfers */ 506263153Skevlo for (x = 0; x != URTWN_N_TRANSFER; x++) 507263153Skevlo usbd_transfer_drain(sc->sc_xfer[x]); 508263153Skevlo 509263153Skevlo /* Free data buffers. */ 510263153Skevlo URTWN_LOCK(sc); 511263153Skevlo urtwn_free_tx_list(sc); 512263153Skevlo urtwn_free_rx_list(sc); 513263153Skevlo URTWN_UNLOCK(sc); 514263153Skevlo 515251538Srpaulo ieee80211_ifdetach(ic); 516251538Srpaulo mtx_destroy(&sc->sc_mtx); 517251538Srpaulo 518251538Srpaulo return (0); 519251538Srpaulo} 520251538Srpaulo 521251538Srpaulostatic void 522289066Skevlourtwn_drain_mbufq(struct urtwn_softc *sc) 523251538Srpaulo{ 524289066Skevlo struct mbuf *m; 525289066Skevlo struct ieee80211_node *ni; 526289066Skevlo URTWN_ASSERT_LOCKED(sc); 527289066Skevlo while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 528289066Skevlo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 529289066Skevlo m->m_pkthdr.rcvif = NULL; 530289066Skevlo ieee80211_free_node(ni); 531289066Skevlo m_freem(m); 532251538Srpaulo } 533251538Srpaulo} 534251538Srpaulo 535251538Srpaulostatic usb_error_t 536251538Srpaulourtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 537251538Srpaulo void *data) 538251538Srpaulo{ 539251538Srpaulo usb_error_t err; 540251538Srpaulo int ntries = 10; 541251538Srpaulo 542251538Srpaulo URTWN_ASSERT_LOCKED(sc); 543251538Srpaulo 544251538Srpaulo while (ntries--) { 545251538Srpaulo err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 546251538Srpaulo req, data, 0, NULL, 250 /* ms */); 547251538Srpaulo if (err == 0) 548251538Srpaulo break; 549251538Srpaulo 550251538Srpaulo DPRINTFN(1, "Control request failed, %s (retrying)\n", 551251538Srpaulo usbd_errstr(err)); 552251538Srpaulo usb_pause_mtx(&sc->sc_mtx, hz / 100); 553251538Srpaulo } 554251538Srpaulo return (err); 555251538Srpaulo} 556251538Srpaulo 557251538Srpaulostatic struct ieee80211vap * 558251538Srpaulourtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 559251538Srpaulo enum ieee80211_opmode opmode, int flags, 560251538Srpaulo const uint8_t bssid[IEEE80211_ADDR_LEN], 561251538Srpaulo const uint8_t mac[IEEE80211_ADDR_LEN]) 562251538Srpaulo{ 563251538Srpaulo struct urtwn_vap *uvp; 564251538Srpaulo struct ieee80211vap *vap; 565251538Srpaulo 566251538Srpaulo if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 567251538Srpaulo return (NULL); 568251538Srpaulo 569287197Sglebius uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 570251538Srpaulo vap = &uvp->vap; 571251538Srpaulo /* enable s/w bmiss handling for sta mode */ 572251538Srpaulo 573281069Srpaulo if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 574287197Sglebius flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 575257743Shselasky /* out of memory */ 576257743Shselasky free(uvp, M_80211_VAP); 577257743Shselasky return (NULL); 578257743Shselasky } 579257743Shselasky 580251538Srpaulo /* override state transition machine */ 581251538Srpaulo uvp->newstate = vap->iv_newstate; 582251538Srpaulo vap->iv_newstate = urtwn_newstate; 583251538Srpaulo 584251538Srpaulo /* complete setup */ 585251538Srpaulo ieee80211_vap_attach(vap, ieee80211_media_change, 586287197Sglebius ieee80211_media_status, mac); 587251538Srpaulo ic->ic_opmode = opmode; 588251538Srpaulo return (vap); 589251538Srpaulo} 590251538Srpaulo 591251538Srpaulostatic void 592251538Srpaulourtwn_vap_delete(struct ieee80211vap *vap) 593251538Srpaulo{ 594251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 595251538Srpaulo 596251538Srpaulo ieee80211_vap_detach(vap); 597251538Srpaulo free(uvp, M_80211_VAP); 598251538Srpaulo} 599251538Srpaulo 600251538Srpaulostatic struct mbuf * 601251538Srpaulourtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 602251538Srpaulo{ 603287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 604251538Srpaulo struct ieee80211_frame *wh; 605251538Srpaulo struct mbuf *m; 606251538Srpaulo struct r92c_rx_stat *stat; 607251538Srpaulo uint32_t rxdw0, rxdw3; 608251538Srpaulo uint8_t rate; 609251538Srpaulo int8_t rssi = 0; 610251538Srpaulo int infosz; 611251538Srpaulo 612251538Srpaulo /* 613251538Srpaulo * don't pass packets to the ieee80211 framework if the driver isn't 614251538Srpaulo * RUNNING. 615251538Srpaulo */ 616287197Sglebius if (!(sc->sc_flags & URTWN_RUNNING)) 617251538Srpaulo return (NULL); 618251538Srpaulo 619251538Srpaulo stat = (struct r92c_rx_stat *)buf; 620251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 621251538Srpaulo rxdw3 = le32toh(stat->rxdw3); 622251538Srpaulo 623251538Srpaulo if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 624251538Srpaulo /* 625251538Srpaulo * This should not happen since we setup our Rx filter 626251538Srpaulo * to not receive these frames. 627251538Srpaulo */ 628287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 629251538Srpaulo return (NULL); 630251538Srpaulo } 631290022Savos if (pktlen < sizeof(struct ieee80211_frame_ack) || 632290022Savos pktlen > MCLBYTES) { 633287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 634271303Skevlo return (NULL); 635271303Skevlo } 636251538Srpaulo 637251538Srpaulo rate = MS(rxdw3, R92C_RXDW3_RATE); 638251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 639251538Srpaulo 640251538Srpaulo /* Get RSSI from PHY status descriptor if present. */ 641251538Srpaulo if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 642281069Srpaulo if (sc->chip & URTWN_CHIP_88E) 643264912Skevlo rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 644264912Skevlo else 645264912Skevlo rssi = urtwn_get_rssi(sc, rate, &stat[1]); 646251538Srpaulo /* Update our average RSSI. */ 647251538Srpaulo urtwn_update_avgrssi(sc, rate, rssi); 648251538Srpaulo } 649251538Srpaulo 650260463Skevlo m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 651251538Srpaulo if (m == NULL) { 652251538Srpaulo device_printf(sc->sc_dev, "could not create RX mbuf\n"); 653251538Srpaulo return (NULL); 654251538Srpaulo } 655251538Srpaulo 656251538Srpaulo /* Finalize mbuf. */ 657251538Srpaulo wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 658251538Srpaulo memcpy(mtod(m, uint8_t *), wh, pktlen); 659251538Srpaulo m->m_pkthdr.len = m->m_len = pktlen; 660251538Srpaulo 661251538Srpaulo if (ieee80211_radiotap_active(ic)) { 662251538Srpaulo struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 663251538Srpaulo 664251538Srpaulo tap->wr_flags = 0; 665251538Srpaulo /* Map HW rate index to 802.11 rate. */ 666251538Srpaulo if (!(rxdw3 & R92C_RXDW3_HT)) { 667289758Savos tap->wr_rate = ridx2rate[rate]; 668251538Srpaulo } else if (rate >= 12) { /* MCS0~15. */ 669251538Srpaulo /* Bit 7 set means HT MCS instead of rate. */ 670251538Srpaulo tap->wr_rate = 0x80 | (rate - 12); 671251538Srpaulo } 672251538Srpaulo tap->wr_dbm_antsignal = rssi; 673289816Savos tap->wr_dbm_antnoise = URTWN_NOISE_FLOOR; 674251538Srpaulo tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 675251538Srpaulo tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 676251538Srpaulo } 677251538Srpaulo 678251538Srpaulo *rssi_p = rssi; 679251538Srpaulo 680251538Srpaulo return (m); 681251538Srpaulo} 682251538Srpaulo 683251538Srpaulostatic struct mbuf * 684251538Srpaulourtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 685251538Srpaulo int8_t *nf) 686251538Srpaulo{ 687251538Srpaulo struct urtwn_softc *sc = data->sc; 688287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 689251538Srpaulo struct r92c_rx_stat *stat; 690251538Srpaulo struct mbuf *m, *m0 = NULL, *prevm = NULL; 691251538Srpaulo uint32_t rxdw0; 692251538Srpaulo uint8_t *buf; 693251538Srpaulo int len, totlen, pktlen, infosz, npkts; 694251538Srpaulo 695251538Srpaulo usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 696251538Srpaulo 697251538Srpaulo if (len < sizeof(*stat)) { 698287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 699251538Srpaulo return (NULL); 700251538Srpaulo } 701251538Srpaulo 702251538Srpaulo buf = data->buf; 703251538Srpaulo /* Get the number of encapsulated frames. */ 704251538Srpaulo stat = (struct r92c_rx_stat *)buf; 705251538Srpaulo npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 706251538Srpaulo DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 707251538Srpaulo 708251538Srpaulo /* Process all of them. */ 709251538Srpaulo while (npkts-- > 0) { 710251538Srpaulo if (len < sizeof(*stat)) 711251538Srpaulo break; 712251538Srpaulo stat = (struct r92c_rx_stat *)buf; 713251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 714251538Srpaulo 715251538Srpaulo pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 716251538Srpaulo if (pktlen == 0) 717251538Srpaulo break; 718251538Srpaulo 719251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 720251538Srpaulo 721251538Srpaulo /* Make sure everything fits in xfer. */ 722251538Srpaulo totlen = sizeof(*stat) + infosz + pktlen; 723251538Srpaulo if (totlen > len) 724251538Srpaulo break; 725251538Srpaulo 726251538Srpaulo m = urtwn_rx_frame(sc, buf, pktlen, rssi); 727251538Srpaulo if (m0 == NULL) 728251538Srpaulo m0 = m; 729251538Srpaulo if (prevm == NULL) 730251538Srpaulo prevm = m; 731251538Srpaulo else { 732251538Srpaulo prevm->m_next = m; 733251538Srpaulo prevm = m; 734251538Srpaulo } 735251538Srpaulo 736251538Srpaulo /* Next chunk is 128-byte aligned. */ 737251538Srpaulo totlen = (totlen + 127) & ~127; 738251538Srpaulo buf += totlen; 739251538Srpaulo len -= totlen; 740251538Srpaulo } 741251538Srpaulo 742251538Srpaulo return (m0); 743251538Srpaulo} 744251538Srpaulo 745251538Srpaulostatic void 746251538Srpaulourtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 747251538Srpaulo{ 748251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 749287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 750290022Savos struct ieee80211_frame_min *wh; 751251538Srpaulo struct ieee80211_node *ni; 752251538Srpaulo struct mbuf *m = NULL, *next; 753251538Srpaulo struct urtwn_data *data; 754251538Srpaulo int8_t nf; 755251538Srpaulo int rssi = 1; 756251538Srpaulo 757251538Srpaulo URTWN_ASSERT_LOCKED(sc); 758251538Srpaulo 759251538Srpaulo switch (USB_GET_STATE(xfer)) { 760251538Srpaulo case USB_ST_TRANSFERRED: 761251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 762251538Srpaulo if (data == NULL) 763251538Srpaulo goto tr_setup; 764251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 765251538Srpaulo m = urtwn_rxeof(xfer, data, &rssi, &nf); 766251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 767251538Srpaulo /* FALLTHROUGH */ 768251538Srpaulo case USB_ST_SETUP: 769251538Srpaulotr_setup: 770251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_inactive); 771251538Srpaulo if (data == NULL) { 772251538Srpaulo KASSERT(m == NULL, ("mbuf isn't NULL")); 773251538Srpaulo return; 774251538Srpaulo } 775251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 776251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 777251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, 778251538Srpaulo usbd_xfer_max_len(xfer)); 779251538Srpaulo usbd_transfer_submit(xfer); 780251538Srpaulo 781251538Srpaulo /* 782251538Srpaulo * To avoid LOR we should unlock our private mutex here to call 783251538Srpaulo * ieee80211_input() because here is at the end of a USB 784251538Srpaulo * callback and safe to unlock. 785251538Srpaulo */ 786251538Srpaulo URTWN_UNLOCK(sc); 787251538Srpaulo while (m != NULL) { 788251538Srpaulo next = m->m_next; 789251538Srpaulo m->m_next = NULL; 790290022Savos wh = mtod(m, struct ieee80211_frame_min *); 791290022Savos if (m->m_len >= sizeof(*wh)) 792290022Savos ni = ieee80211_find_rxnode(ic, wh); 793290022Savos else 794290022Savos ni = NULL; 795251538Srpaulo nf = URTWN_NOISE_FLOOR; 796251538Srpaulo if (ni != NULL) { 797289799Savos (void)ieee80211_input(ni, m, rssi - nf, nf); 798251538Srpaulo ieee80211_free_node(ni); 799289799Savos } else { 800289799Savos (void)ieee80211_input_all(ic, m, rssi - nf, 801289799Savos nf); 802289799Savos } 803251538Srpaulo m = next; 804251538Srpaulo } 805251538Srpaulo URTWN_LOCK(sc); 806251538Srpaulo break; 807251538Srpaulo default: 808251538Srpaulo /* needs it to the inactive queue due to a error. */ 809251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 810251538Srpaulo if (data != NULL) { 811251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 812251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 813251538Srpaulo } 814251538Srpaulo if (error != USB_ERR_CANCELLED) { 815251538Srpaulo usbd_xfer_set_stall(xfer); 816287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 817251538Srpaulo goto tr_setup; 818251538Srpaulo } 819251538Srpaulo break; 820251538Srpaulo } 821251538Srpaulo} 822251538Srpaulo 823251538Srpaulostatic void 824289891Savosurtwn_txeof(struct urtwn_softc *sc, struct urtwn_data *data, int status) 825251538Srpaulo{ 826251538Srpaulo 827251538Srpaulo URTWN_ASSERT_LOCKED(sc); 828289891Savos 829289891Savos ieee80211_tx_complete(data->ni, data->m, status); 830289891Savos 831287197Sglebius data->ni = NULL; 832287197Sglebius data->m = NULL; 833289891Savos 834251538Srpaulo sc->sc_txtimer = 0; 835289891Savos 836289891Savos STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 837251538Srpaulo} 838251538Srpaulo 839289066Skevlostatic int 840289066Skevlourtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 841289066Skevlo int ndata, int maxsz) 842289066Skevlo{ 843289066Skevlo int i, error; 844289066Skevlo 845289066Skevlo for (i = 0; i < ndata; i++) { 846289066Skevlo struct urtwn_data *dp = &data[i]; 847289066Skevlo dp->sc = sc; 848289066Skevlo dp->m = NULL; 849289066Skevlo dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 850289066Skevlo if (dp->buf == NULL) { 851289066Skevlo device_printf(sc->sc_dev, 852289066Skevlo "could not allocate buffer\n"); 853289066Skevlo error = ENOMEM; 854289066Skevlo goto fail; 855289066Skevlo } 856289066Skevlo dp->ni = NULL; 857289066Skevlo } 858289066Skevlo 859289066Skevlo return (0); 860289066Skevlofail: 861289066Skevlo urtwn_free_list(sc, data, ndata); 862289066Skevlo return (error); 863289066Skevlo} 864289066Skevlo 865289066Skevlostatic int 866289066Skevlourtwn_alloc_rx_list(struct urtwn_softc *sc) 867289066Skevlo{ 868289066Skevlo int error, i; 869289066Skevlo 870289066Skevlo error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 871289066Skevlo URTWN_RXBUFSZ); 872289066Skevlo if (error != 0) 873289066Skevlo return (error); 874289066Skevlo 875289066Skevlo STAILQ_INIT(&sc->sc_rx_active); 876289066Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 877289066Skevlo 878289066Skevlo for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 879289066Skevlo STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 880289066Skevlo 881289066Skevlo return (0); 882289066Skevlo} 883289066Skevlo 884289066Skevlostatic int 885289066Skevlourtwn_alloc_tx_list(struct urtwn_softc *sc) 886289066Skevlo{ 887289066Skevlo int error, i; 888289066Skevlo 889289066Skevlo error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 890289066Skevlo URTWN_TXBUFSZ); 891289066Skevlo if (error != 0) 892289066Skevlo return (error); 893289066Skevlo 894289066Skevlo STAILQ_INIT(&sc->sc_tx_active); 895289066Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 896289066Skevlo STAILQ_INIT(&sc->sc_tx_pending); 897289066Skevlo 898289066Skevlo for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 899289066Skevlo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 900289066Skevlo 901289066Skevlo return (0); 902289066Skevlo} 903289066Skevlo 904251538Srpaulostatic void 905289066Skevlourtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 906289066Skevlo{ 907289066Skevlo int i; 908289066Skevlo 909289066Skevlo for (i = 0; i < ndata; i++) { 910289066Skevlo struct urtwn_data *dp = &data[i]; 911289066Skevlo 912289066Skevlo if (dp->buf != NULL) { 913289066Skevlo free(dp->buf, M_USBDEV); 914289066Skevlo dp->buf = NULL; 915289066Skevlo } 916289066Skevlo if (dp->ni != NULL) { 917289066Skevlo ieee80211_free_node(dp->ni); 918289066Skevlo dp->ni = NULL; 919289066Skevlo } 920289066Skevlo } 921289066Skevlo} 922289066Skevlo 923289066Skevlostatic void 924289066Skevlourtwn_free_rx_list(struct urtwn_softc *sc) 925289066Skevlo{ 926289066Skevlo urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 927289066Skevlo} 928289066Skevlo 929289066Skevlostatic void 930289066Skevlourtwn_free_tx_list(struct urtwn_softc *sc) 931289066Skevlo{ 932289066Skevlo urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 933289066Skevlo} 934289066Skevlo 935289066Skevlostatic void 936251538Srpaulourtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 937251538Srpaulo{ 938251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 939251538Srpaulo struct urtwn_data *data; 940251538Srpaulo 941251538Srpaulo URTWN_ASSERT_LOCKED(sc); 942251538Srpaulo 943251538Srpaulo switch (USB_GET_STATE(xfer)){ 944251538Srpaulo case USB_ST_TRANSFERRED: 945251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 946251538Srpaulo if (data == NULL) 947251538Srpaulo goto tr_setup; 948251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 949289891Savos urtwn_txeof(sc, data, 0); 950251538Srpaulo /* FALLTHROUGH */ 951251538Srpaulo case USB_ST_SETUP: 952251538Srpaulotr_setup: 953251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_pending); 954251538Srpaulo if (data == NULL) { 955251538Srpaulo DPRINTF("%s: empty pending queue\n", __func__); 956288353Sadrian goto finish; 957251538Srpaulo } 958251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 959251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 960251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 961251538Srpaulo usbd_transfer_submit(xfer); 962251538Srpaulo break; 963251538Srpaulo default: 964251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 965251538Srpaulo if (data == NULL) 966251538Srpaulo goto tr_setup; 967289891Savos STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 968289891Savos urtwn_txeof(sc, data, 1); 969251538Srpaulo if (error != USB_ERR_CANCELLED) { 970251538Srpaulo usbd_xfer_set_stall(xfer); 971251538Srpaulo goto tr_setup; 972251538Srpaulo } 973251538Srpaulo break; 974251538Srpaulo } 975288353Sadrianfinish: 976288353Sadrian /* Kick-start more transmit */ 977288353Sadrian urtwn_start(sc); 978251538Srpaulo} 979251538Srpaulo 980251538Srpaulostatic struct urtwn_data * 981251538Srpaulo_urtwn_getbuf(struct urtwn_softc *sc) 982251538Srpaulo{ 983251538Srpaulo struct urtwn_data *bf; 984251538Srpaulo 985251538Srpaulo bf = STAILQ_FIRST(&sc->sc_tx_inactive); 986251538Srpaulo if (bf != NULL) 987251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 988251538Srpaulo else 989251538Srpaulo bf = NULL; 990251538Srpaulo if (bf == NULL) 991251538Srpaulo DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 992251538Srpaulo return (bf); 993251538Srpaulo} 994251538Srpaulo 995251538Srpaulostatic struct urtwn_data * 996251538Srpaulourtwn_getbuf(struct urtwn_softc *sc) 997251538Srpaulo{ 998251538Srpaulo struct urtwn_data *bf; 999251538Srpaulo 1000251538Srpaulo URTWN_ASSERT_LOCKED(sc); 1001251538Srpaulo 1002251538Srpaulo bf = _urtwn_getbuf(sc); 1003287197Sglebius if (bf == NULL) 1004251538Srpaulo DPRINTF("%s: stop queue\n", __func__); 1005251538Srpaulo return (bf); 1006251538Srpaulo} 1007251538Srpaulo 1008251538Srpaulostatic int 1009251538Srpaulourtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1010251538Srpaulo int len) 1011251538Srpaulo{ 1012251538Srpaulo usb_device_request_t req; 1013251538Srpaulo 1014251538Srpaulo req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1015251538Srpaulo req.bRequest = R92C_REQ_REGS; 1016251538Srpaulo USETW(req.wValue, addr); 1017251538Srpaulo USETW(req.wIndex, 0); 1018251538Srpaulo USETW(req.wLength, len); 1019251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 1020251538Srpaulo} 1021251538Srpaulo 1022251538Srpaulostatic void 1023251538Srpaulourtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1024251538Srpaulo{ 1025251538Srpaulo urtwn_write_region_1(sc, addr, &val, 1); 1026251538Srpaulo} 1027251538Srpaulo 1028251538Srpaulo 1029251538Srpaulostatic void 1030251538Srpaulourtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1031251538Srpaulo{ 1032251538Srpaulo val = htole16(val); 1033251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1034251538Srpaulo} 1035251538Srpaulo 1036251538Srpaulostatic void 1037251538Srpaulourtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1038251538Srpaulo{ 1039251538Srpaulo val = htole32(val); 1040251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1041251538Srpaulo} 1042251538Srpaulo 1043251538Srpaulostatic int 1044251538Srpaulourtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1045251538Srpaulo int len) 1046251538Srpaulo{ 1047251538Srpaulo usb_device_request_t req; 1048251538Srpaulo 1049251538Srpaulo req.bmRequestType = UT_READ_VENDOR_DEVICE; 1050251538Srpaulo req.bRequest = R92C_REQ_REGS; 1051251538Srpaulo USETW(req.wValue, addr); 1052251538Srpaulo USETW(req.wIndex, 0); 1053251538Srpaulo USETW(req.wLength, len); 1054251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 1055251538Srpaulo} 1056251538Srpaulo 1057251538Srpaulostatic uint8_t 1058251538Srpaulourtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1059251538Srpaulo{ 1060251538Srpaulo uint8_t val; 1061251538Srpaulo 1062251538Srpaulo if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1063251538Srpaulo return (0xff); 1064251538Srpaulo return (val); 1065251538Srpaulo} 1066251538Srpaulo 1067251538Srpaulostatic uint16_t 1068251538Srpaulourtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1069251538Srpaulo{ 1070251538Srpaulo uint16_t val; 1071251538Srpaulo 1072251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1073251538Srpaulo return (0xffff); 1074251538Srpaulo return (le16toh(val)); 1075251538Srpaulo} 1076251538Srpaulo 1077251538Srpaulostatic uint32_t 1078251538Srpaulourtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1079251538Srpaulo{ 1080251538Srpaulo uint32_t val; 1081251538Srpaulo 1082251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1083251538Srpaulo return (0xffffffff); 1084251538Srpaulo return (le32toh(val)); 1085251538Srpaulo} 1086251538Srpaulo 1087251538Srpaulostatic int 1088251538Srpaulourtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1089251538Srpaulo{ 1090251538Srpaulo struct r92c_fw_cmd cmd; 1091251538Srpaulo int ntries; 1092251538Srpaulo 1093251538Srpaulo /* Wait for current FW box to be empty. */ 1094251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1095251538Srpaulo if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1096251538Srpaulo break; 1097266472Shselasky urtwn_ms_delay(sc); 1098251538Srpaulo } 1099251538Srpaulo if (ntries == 100) { 1100251538Srpaulo device_printf(sc->sc_dev, 1101251538Srpaulo "could not send firmware command\n"); 1102251538Srpaulo return (ETIMEDOUT); 1103251538Srpaulo } 1104251538Srpaulo memset(&cmd, 0, sizeof(cmd)); 1105251538Srpaulo cmd.id = id; 1106251538Srpaulo if (len > 3) 1107251538Srpaulo cmd.id |= R92C_CMD_FLAG_EXT; 1108251538Srpaulo KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1109251538Srpaulo memcpy(cmd.msg, buf, len); 1110251538Srpaulo 1111251538Srpaulo /* Write the first word last since that will trigger the FW. */ 1112251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1113251538Srpaulo (uint8_t *)&cmd + 4, 2); 1114251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1115251538Srpaulo (uint8_t *)&cmd + 0, 4); 1116251538Srpaulo 1117251538Srpaulo sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1118251538Srpaulo return (0); 1119251538Srpaulo} 1120251538Srpaulo 1121264912Skevlostatic __inline void 1122251538Srpaulourtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1123251538Srpaulo{ 1124264912Skevlo 1125264912Skevlo sc->sc_rf_write(sc, chain, addr, val); 1126264912Skevlo} 1127264912Skevlo 1128264912Skevlostatic void 1129264912Skevlourtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1130264912Skevlo uint32_t val) 1131264912Skevlo{ 1132251538Srpaulo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1133251538Srpaulo SM(R92C_LSSI_PARAM_ADDR, addr) | 1134251538Srpaulo SM(R92C_LSSI_PARAM_DATA, val)); 1135251538Srpaulo} 1136251538Srpaulo 1137264912Skevlostatic void 1138264912Skevlourtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1139264912Skevlouint32_t val) 1140264912Skevlo{ 1141264912Skevlo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1142264912Skevlo SM(R88E_LSSI_PARAM_ADDR, addr) | 1143264912Skevlo SM(R92C_LSSI_PARAM_DATA, val)); 1144264912Skevlo} 1145264912Skevlo 1146251538Srpaulostatic uint32_t 1147251538Srpaulourtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1148251538Srpaulo{ 1149251538Srpaulo uint32_t reg[R92C_MAX_CHAINS], val; 1150251538Srpaulo 1151251538Srpaulo reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1152251538Srpaulo if (chain != 0) 1153251538Srpaulo reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1154251538Srpaulo 1155251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1156251538Srpaulo reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1157266472Shselasky urtwn_ms_delay(sc); 1158251538Srpaulo 1159251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1160251538Srpaulo RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1161251538Srpaulo R92C_HSSI_PARAM2_READ_EDGE); 1162266472Shselasky urtwn_ms_delay(sc); 1163251538Srpaulo 1164251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1165251538Srpaulo reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1166266472Shselasky urtwn_ms_delay(sc); 1167251538Srpaulo 1168251538Srpaulo if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1169251538Srpaulo val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1170251538Srpaulo else 1171251538Srpaulo val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1172251538Srpaulo return (MS(val, R92C_LSSI_READBACK_DATA)); 1173251538Srpaulo} 1174251538Srpaulo 1175251538Srpaulostatic int 1176251538Srpaulourtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1177251538Srpaulo{ 1178251538Srpaulo int ntries; 1179251538Srpaulo 1180251538Srpaulo urtwn_write_4(sc, R92C_LLT_INIT, 1181251538Srpaulo SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1182251538Srpaulo SM(R92C_LLT_INIT_ADDR, addr) | 1183251538Srpaulo SM(R92C_LLT_INIT_DATA, data)); 1184251538Srpaulo /* Wait for write operation to complete. */ 1185251538Srpaulo for (ntries = 0; ntries < 20; ntries++) { 1186251538Srpaulo if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1187251538Srpaulo R92C_LLT_INIT_OP_NO_ACTIVE) 1188251538Srpaulo return (0); 1189266472Shselasky urtwn_ms_delay(sc); 1190251538Srpaulo } 1191251538Srpaulo return (ETIMEDOUT); 1192251538Srpaulo} 1193251538Srpaulo 1194251538Srpaulostatic uint8_t 1195251538Srpaulourtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1196251538Srpaulo{ 1197251538Srpaulo uint32_t reg; 1198251538Srpaulo int ntries; 1199251538Srpaulo 1200251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1201251538Srpaulo reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1202251538Srpaulo reg &= ~R92C_EFUSE_CTRL_VALID; 1203251538Srpaulo urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1204251538Srpaulo /* Wait for read operation to complete. */ 1205251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1206251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1207251538Srpaulo if (reg & R92C_EFUSE_CTRL_VALID) 1208251538Srpaulo return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1209266472Shselasky urtwn_ms_delay(sc); 1210251538Srpaulo } 1211281069Srpaulo device_printf(sc->sc_dev, 1212251538Srpaulo "could not read efuse byte at address 0x%x\n", addr); 1213251538Srpaulo return (0xff); 1214251538Srpaulo} 1215251538Srpaulo 1216251538Srpaulostatic void 1217251538Srpaulourtwn_efuse_read(struct urtwn_softc *sc) 1218251538Srpaulo{ 1219251538Srpaulo uint8_t *rom = (uint8_t *)&sc->rom; 1220251538Srpaulo uint16_t addr = 0; 1221251538Srpaulo uint32_t reg; 1222282623Skevlo uint8_t off, msk; 1223251538Srpaulo int i; 1224251538Srpaulo 1225264912Skevlo urtwn_efuse_switch_power(sc); 1226264912Skevlo 1227251538Srpaulo memset(&sc->rom, 0xff, sizeof(sc->rom)); 1228251538Srpaulo while (addr < 512) { 1229251538Srpaulo reg = urtwn_efuse_read_1(sc, addr); 1230251538Srpaulo if (reg == 0xff) 1231251538Srpaulo break; 1232251538Srpaulo addr++; 1233251538Srpaulo off = reg >> 4; 1234251538Srpaulo msk = reg & 0xf; 1235251538Srpaulo for (i = 0; i < 4; i++) { 1236251538Srpaulo if (msk & (1 << i)) 1237251538Srpaulo continue; 1238251538Srpaulo rom[off * 8 + i * 2 + 0] = 1239251538Srpaulo urtwn_efuse_read_1(sc, addr); 1240251538Srpaulo addr++; 1241251538Srpaulo rom[off * 8 + i * 2 + 1] = 1242251538Srpaulo urtwn_efuse_read_1(sc, addr); 1243251538Srpaulo addr++; 1244251538Srpaulo } 1245251538Srpaulo } 1246251538Srpaulo#ifdef URTWN_DEBUG 1247251538Srpaulo if (urtwn_debug >= 2) { 1248251538Srpaulo /* Dump ROM content. */ 1249251538Srpaulo printf("\n"); 1250251538Srpaulo for (i = 0; i < sizeof(sc->rom); i++) 1251251538Srpaulo printf("%02x:", rom[i]); 1252251538Srpaulo printf("\n"); 1253251538Srpaulo } 1254251538Srpaulo#endif 1255282623Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1256282623Skevlo} 1257281592Skevlo 1258264912Skevlostatic void 1259264912Skevlourtwn_efuse_switch_power(struct urtwn_softc *sc) 1260264912Skevlo{ 1261264912Skevlo uint32_t reg; 1262251538Srpaulo 1263282623Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1264281918Skevlo 1265264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1266264912Skevlo if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1267264912Skevlo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1268264912Skevlo reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1269264912Skevlo } 1270264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1271264912Skevlo if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1272264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1273264912Skevlo reg | R92C_SYS_FUNC_EN_ELDR); 1274264912Skevlo } 1275264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1276264912Skevlo if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1277264912Skevlo (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1278264912Skevlo urtwn_write_2(sc, R92C_SYS_CLKR, 1279264912Skevlo reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1280264912Skevlo } 1281264912Skevlo} 1282264912Skevlo 1283251538Srpaulostatic int 1284251538Srpaulourtwn_read_chipid(struct urtwn_softc *sc) 1285251538Srpaulo{ 1286251538Srpaulo uint32_t reg; 1287251538Srpaulo 1288264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1289264912Skevlo return (0); 1290264912Skevlo 1291251538Srpaulo reg = urtwn_read_4(sc, R92C_SYS_CFG); 1292251538Srpaulo if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1293251538Srpaulo return (EIO); 1294251538Srpaulo 1295251538Srpaulo if (reg & R92C_SYS_CFG_TYPE_92C) { 1296251538Srpaulo sc->chip |= URTWN_CHIP_92C; 1297251538Srpaulo /* Check if it is a castrated 8192C. */ 1298251538Srpaulo if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1299251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID) == 1300251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1301251538Srpaulo sc->chip |= URTWN_CHIP_92C_1T2R; 1302251538Srpaulo } 1303251538Srpaulo if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1304251538Srpaulo sc->chip |= URTWN_CHIP_UMC; 1305251538Srpaulo if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1306251538Srpaulo sc->chip |= URTWN_CHIP_UMC_A_CUT; 1307251538Srpaulo } 1308251538Srpaulo return (0); 1309251538Srpaulo} 1310251538Srpaulo 1311251538Srpaulostatic void 1312251538Srpaulourtwn_read_rom(struct urtwn_softc *sc) 1313251538Srpaulo{ 1314251538Srpaulo struct r92c_rom *rom = &sc->rom; 1315251538Srpaulo 1316251538Srpaulo /* Read full ROM image. */ 1317251538Srpaulo urtwn_efuse_read(sc); 1318251538Srpaulo 1319251538Srpaulo /* XXX Weird but this is what the vendor driver does. */ 1320251538Srpaulo sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1321251538Srpaulo DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1322251538Srpaulo 1323251538Srpaulo sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1324251538Srpaulo 1325251538Srpaulo sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1326251538Srpaulo DPRINTF("regulatory type=%d\n", sc->regulatory); 1327287197Sglebius IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1328251538Srpaulo 1329264912Skevlo sc->sc_rf_write = urtwn_r92c_rf_write; 1330264912Skevlo sc->sc_power_on = urtwn_r92c_power_on; 1331264912Skevlo sc->sc_dma_init = urtwn_r92c_dma_init; 1332251538Srpaulo} 1333251538Srpaulo 1334264912Skevlostatic void 1335264912Skevlourtwn_r88e_read_rom(struct urtwn_softc *sc) 1336264912Skevlo{ 1337264912Skevlo uint8_t *rom = sc->r88e_rom; 1338264912Skevlo uint16_t addr = 0; 1339264912Skevlo uint32_t reg; 1340264912Skevlo uint8_t off, msk, tmp; 1341264912Skevlo int i; 1342264912Skevlo 1343264982Sandreast off = 0; 1344264912Skevlo urtwn_efuse_switch_power(sc); 1345264912Skevlo 1346264912Skevlo /* Read full ROM image. */ 1347264912Skevlo memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1348281918Skevlo while (addr < 512) { 1349264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1350264912Skevlo if (reg == 0xff) 1351264912Skevlo break; 1352264912Skevlo addr++; 1353264912Skevlo if ((reg & 0x1f) == 0x0f) { 1354264912Skevlo tmp = (reg & 0xe0) >> 5; 1355264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1356264912Skevlo if ((reg & 0x0f) != 0x0f) 1357264912Skevlo off = ((reg & 0xf0) >> 1) | tmp; 1358264912Skevlo addr++; 1359264912Skevlo } else 1360264912Skevlo off = reg >> 4; 1361264912Skevlo msk = reg & 0xf; 1362264912Skevlo for (i = 0; i < 4; i++) { 1363264912Skevlo if (msk & (1 << i)) 1364264912Skevlo continue; 1365264912Skevlo rom[off * 8 + i * 2 + 0] = 1366264912Skevlo urtwn_efuse_read_1(sc, addr); 1367264912Skevlo addr++; 1368264912Skevlo rom[off * 8 + i * 2 + 1] = 1369264912Skevlo urtwn_efuse_read_1(sc, addr); 1370264912Skevlo addr++; 1371264912Skevlo } 1372264912Skevlo } 1373264912Skevlo 1374281918Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1375281918Skevlo 1376264912Skevlo addr = 0x10; 1377264912Skevlo for (i = 0; i < 6; i++) 1378264912Skevlo sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1379264912Skevlo for (i = 0; i < 5; i++) 1380264912Skevlo sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1381264912Skevlo sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1382264912Skevlo if (sc->bw20_tx_pwr_diff & 0x08) 1383264912Skevlo sc->bw20_tx_pwr_diff |= 0xf0; 1384264912Skevlo sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1385264912Skevlo if (sc->ofdm_tx_pwr_diff & 0x08) 1386264912Skevlo sc->ofdm_tx_pwr_diff |= 0xf0; 1387264912Skevlo sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1388287197Sglebius IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &sc->r88e_rom[0xd7]); 1389264912Skevlo 1390264912Skevlo sc->sc_rf_write = urtwn_r88e_rf_write; 1391264912Skevlo sc->sc_power_on = urtwn_r88e_power_on; 1392264912Skevlo sc->sc_dma_init = urtwn_r88e_dma_init; 1393264912Skevlo} 1394264912Skevlo 1395251538Srpaulo/* 1396251538Srpaulo * Initialize rate adaptation in firmware. 1397251538Srpaulo */ 1398251538Srpaulostatic int 1399251538Srpaulourtwn_ra_init(struct urtwn_softc *sc) 1400251538Srpaulo{ 1401287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1402251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1403251538Srpaulo struct ieee80211_node *ni; 1404251538Srpaulo struct ieee80211_rateset *rs; 1405251538Srpaulo struct r92c_fw_cmd_macid_cfg cmd; 1406251538Srpaulo uint32_t rates, basicrates; 1407251538Srpaulo uint8_t mode; 1408251538Srpaulo int maxrate, maxbasicrate, error, i, j; 1409251538Srpaulo 1410251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1411251538Srpaulo rs = &ni->ni_rates; 1412251538Srpaulo 1413251538Srpaulo /* Get normal and basic rates mask. */ 1414251538Srpaulo rates = basicrates = 0; 1415251538Srpaulo maxrate = maxbasicrate = 0; 1416251538Srpaulo for (i = 0; i < rs->rs_nrates; i++) { 1417251538Srpaulo /* Convert 802.11 rate to HW rate index. */ 1418289758Savos for (j = 0; j < nitems(ridx2rate); j++) 1419289758Savos if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1420289758Savos ridx2rate[j]) 1421251538Srpaulo break; 1422289758Savos if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1423251538Srpaulo continue; 1424251538Srpaulo rates |= 1 << j; 1425251538Srpaulo if (j > maxrate) 1426251538Srpaulo maxrate = j; 1427251538Srpaulo if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1428251538Srpaulo basicrates |= 1 << j; 1429251538Srpaulo if (j > maxbasicrate) 1430251538Srpaulo maxbasicrate = j; 1431251538Srpaulo } 1432251538Srpaulo } 1433251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1434251538Srpaulo mode = R92C_RAID_11B; 1435251538Srpaulo else 1436251538Srpaulo mode = R92C_RAID_11BG; 1437251538Srpaulo DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1438251538Srpaulo mode, rates, basicrates); 1439251538Srpaulo 1440251538Srpaulo /* Set rates mask for group addressed frames. */ 1441251538Srpaulo cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1442251538Srpaulo cmd.mask = htole32(mode << 28 | basicrates); 1443251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1444251538Srpaulo if (error != 0) { 1445252401Srpaulo ieee80211_free_node(ni); 1446251538Srpaulo device_printf(sc->sc_dev, 1447251538Srpaulo "could not add broadcast station\n"); 1448251538Srpaulo return (error); 1449251538Srpaulo } 1450251538Srpaulo /* Set initial MRR rate. */ 1451251538Srpaulo DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1452251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1453251538Srpaulo maxbasicrate); 1454251538Srpaulo 1455251538Srpaulo /* Set rates mask for unicast frames. */ 1456251538Srpaulo cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1457251538Srpaulo cmd.mask = htole32(mode << 28 | rates); 1458251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1459251538Srpaulo if (error != 0) { 1460252401Srpaulo ieee80211_free_node(ni); 1461251538Srpaulo device_printf(sc->sc_dev, "could not add BSS station\n"); 1462251538Srpaulo return (error); 1463251538Srpaulo } 1464251538Srpaulo /* Set initial MRR rate. */ 1465251538Srpaulo DPRINTF("maxrate=%d\n", maxrate); 1466251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1467251538Srpaulo maxrate); 1468251538Srpaulo 1469251538Srpaulo /* Indicate highest supported rate. */ 1470252403Srpaulo ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1471252401Srpaulo ieee80211_free_node(ni); 1472252401Srpaulo 1473251538Srpaulo return (0); 1474251538Srpaulo} 1475251538Srpaulo 1476251538Srpaulovoid 1477251538Srpaulourtwn_tsf_sync_enable(struct urtwn_softc *sc) 1478251538Srpaulo{ 1479287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1480251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1481251538Srpaulo struct ieee80211_node *ni = vap->iv_bss; 1482251538Srpaulo 1483251538Srpaulo uint64_t tsf; 1484251538Srpaulo 1485251538Srpaulo /* Enable TSF synchronization. */ 1486251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1487251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1488251538Srpaulo 1489251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1490251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1491251538Srpaulo 1492251538Srpaulo /* Set initial TSF. */ 1493251538Srpaulo memcpy(&tsf, ni->ni_tstamp.data, 8); 1494251538Srpaulo tsf = le64toh(tsf); 1495251538Srpaulo tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1496251538Srpaulo tsf -= IEEE80211_DUR_TU; 1497251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1498251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1499251538Srpaulo 1500251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1501251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1502251538Srpaulo} 1503251538Srpaulo 1504251538Srpaulostatic void 1505251538Srpaulourtwn_set_led(struct urtwn_softc *sc, int led, int on) 1506251538Srpaulo{ 1507251538Srpaulo uint8_t reg; 1508281069Srpaulo 1509251538Srpaulo if (led == URTWN_LED_LINK) { 1510264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 1511264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1512264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1513264912Skevlo if (!on) { 1514264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1515264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, 1516264912Skevlo reg | R92C_LEDCFG0_DIS); 1517264912Skevlo urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1518264912Skevlo urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1519264912Skevlo 0xfe); 1520264912Skevlo } 1521264912Skevlo } else { 1522264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1523264912Skevlo if (!on) 1524264912Skevlo reg |= R92C_LEDCFG0_DIS; 1525264912Skevlo urtwn_write_1(sc, R92C_LEDCFG0, reg); 1526264912Skevlo } 1527264912Skevlo sc->ledlink = on; /* Save LED state. */ 1528251538Srpaulo } 1529251538Srpaulo} 1530251538Srpaulo 1531289811Savosstatic void 1532289811Savosurtwn_set_mode(struct urtwn_softc *sc, uint8_t mode) 1533289811Savos{ 1534289811Savos uint8_t reg; 1535289811Savos 1536289811Savos reg = urtwn_read_1(sc, R92C_MSR); 1537289811Savos reg = (reg & ~R92C_MSR_MASK) | mode; 1538289811Savos urtwn_write_1(sc, R92C_MSR, reg); 1539289811Savos} 1540289811Savos 1541251538Srpaulostatic int 1542251538Srpaulourtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1543251538Srpaulo{ 1544251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 1545251538Srpaulo struct ieee80211com *ic = vap->iv_ic; 1546286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 1547251538Srpaulo struct ieee80211_node *ni; 1548251538Srpaulo enum ieee80211_state ostate; 1549251538Srpaulo 1550251538Srpaulo ostate = vap->iv_state; 1551251538Srpaulo DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1552251538Srpaulo ieee80211_state_name[nstate]); 1553251538Srpaulo 1554251538Srpaulo IEEE80211_UNLOCK(ic); 1555251538Srpaulo URTWN_LOCK(sc); 1556251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 1557251538Srpaulo 1558251538Srpaulo if (ostate == IEEE80211_S_RUN) { 1559251538Srpaulo /* Turn link LED off. */ 1560251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1561251538Srpaulo 1562251538Srpaulo /* Set media status to 'No Link'. */ 1563289811Savos urtwn_set_mode(sc, R92C_MSR_NOLINK); 1564251538Srpaulo 1565251538Srpaulo /* Stop Rx of data frames. */ 1566251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1567251538Srpaulo 1568251538Srpaulo /* Rest TSF. */ 1569251538Srpaulo urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1570251538Srpaulo 1571251538Srpaulo /* Disable TSF synchronization. */ 1572251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1573251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | 1574251538Srpaulo R92C_BCN_CTRL_DIS_TSF_UDT0); 1575251538Srpaulo 1576251538Srpaulo /* Reset EDCA parameters. */ 1577251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1578251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1579251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1580251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1581251538Srpaulo } 1582251538Srpaulo 1583251538Srpaulo switch (nstate) { 1584251538Srpaulo case IEEE80211_S_INIT: 1585251538Srpaulo /* Turn link LED off. */ 1586251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1587251538Srpaulo break; 1588251538Srpaulo case IEEE80211_S_SCAN: 1589251538Srpaulo /* Pause AC Tx queues. */ 1590251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 1591251538Srpaulo urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1592251538Srpaulo break; 1593251538Srpaulo case IEEE80211_S_AUTH: 1594251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 1595251538Srpaulo break; 1596251538Srpaulo case IEEE80211_S_RUN: 1597251538Srpaulo if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1598251538Srpaulo /* Enable Rx of data frames. */ 1599251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1600251538Srpaulo 1601289173Skevlo /* Enable Rx of ctrl frames. */ 1602289173Skevlo urtwn_write_2(sc, R92C_RXFLTMAP1, 0xffff); 1603289173Skevlo 1604289173Skevlo /* 1605289173Skevlo * Accept data/control/management frames 1606289173Skevlo * from any BSSID. 1607289173Skevlo */ 1608289173Skevlo urtwn_write_4(sc, R92C_RCR, 1609289173Skevlo (urtwn_read_4(sc, R92C_RCR) & ~(R92C_RCR_APM | 1610289173Skevlo R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)) | 1611289173Skevlo R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF | 1612289173Skevlo R92C_RCR_AAP); 1613289173Skevlo 1614251538Srpaulo /* Turn link LED on. */ 1615251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1616251538Srpaulo break; 1617251538Srpaulo } 1618251538Srpaulo 1619251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1620251538Srpaulo /* Set media status to 'Associated'. */ 1621289811Savos urtwn_set_mode(sc, R92C_MSR_INFRA); 1622251538Srpaulo 1623251538Srpaulo /* Set BSSID. */ 1624251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1625251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1626251538Srpaulo 1627251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1628251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1629251538Srpaulo else /* 802.11b/g */ 1630251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1631251538Srpaulo 1632251538Srpaulo /* Enable Rx of data frames. */ 1633251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1634251538Srpaulo 1635251538Srpaulo /* Flush all AC queues. */ 1636251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0); 1637251538Srpaulo 1638251538Srpaulo /* Set beacon interval. */ 1639251538Srpaulo urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1640251538Srpaulo 1641251538Srpaulo /* Allow Rx from our BSSID only. */ 1642251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1643251538Srpaulo urtwn_read_4(sc, R92C_RCR) | 1644251538Srpaulo R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1645251538Srpaulo 1646251538Srpaulo /* Enable TSF synchronization. */ 1647251538Srpaulo urtwn_tsf_sync_enable(sc); 1648251538Srpaulo 1649251538Srpaulo urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1650251538Srpaulo urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1651251538Srpaulo urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1652251538Srpaulo urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1653251538Srpaulo urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1654251538Srpaulo urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1655251538Srpaulo 1656251538Srpaulo /* Intialize rate adaptation. */ 1657264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1658264912Skevlo ni->ni_txrate = 1659264912Skevlo ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1660281069Srpaulo else 1661264912Skevlo urtwn_ra_init(sc); 1662251538Srpaulo /* Turn link LED on. */ 1663251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1664251538Srpaulo 1665251538Srpaulo sc->avg_pwdb = -1; /* Reset average RSSI. */ 1666251538Srpaulo /* Reset temperature calibration state machine. */ 1667251538Srpaulo sc->thcal_state = 0; 1668251538Srpaulo sc->thcal_lctemp = 0; 1669251538Srpaulo ieee80211_free_node(ni); 1670251538Srpaulo break; 1671251538Srpaulo default: 1672251538Srpaulo break; 1673251538Srpaulo } 1674251538Srpaulo URTWN_UNLOCK(sc); 1675251538Srpaulo IEEE80211_LOCK(ic); 1676251538Srpaulo return(uvp->newstate(vap, nstate, arg)); 1677251538Srpaulo} 1678251538Srpaulo 1679251538Srpaulostatic void 1680251538Srpaulourtwn_watchdog(void *arg) 1681251538Srpaulo{ 1682251538Srpaulo struct urtwn_softc *sc = arg; 1683251538Srpaulo 1684251538Srpaulo if (sc->sc_txtimer > 0) { 1685251538Srpaulo if (--sc->sc_txtimer == 0) { 1686251538Srpaulo device_printf(sc->sc_dev, "device timeout\n"); 1687287197Sglebius counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1688251538Srpaulo return; 1689251538Srpaulo } 1690251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1691251538Srpaulo } 1692251538Srpaulo} 1693251538Srpaulo 1694251538Srpaulostatic void 1695251538Srpaulourtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1696251538Srpaulo{ 1697251538Srpaulo int pwdb; 1698251538Srpaulo 1699251538Srpaulo /* Convert antenna signal to percentage. */ 1700251538Srpaulo if (rssi <= -100 || rssi >= 20) 1701251538Srpaulo pwdb = 0; 1702251538Srpaulo else if (rssi >= 0) 1703251538Srpaulo pwdb = 100; 1704251538Srpaulo else 1705251538Srpaulo pwdb = 100 + rssi; 1706264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1707289758Savos if (rate <= URTWN_RIDX_CCK11) { 1708264912Skevlo /* CCK gain is smaller than OFDM/MCS gain. */ 1709264912Skevlo pwdb += 6; 1710264912Skevlo if (pwdb > 100) 1711264912Skevlo pwdb = 100; 1712264912Skevlo if (pwdb <= 14) 1713264912Skevlo pwdb -= 4; 1714264912Skevlo else if (pwdb <= 26) 1715264912Skevlo pwdb -= 8; 1716264912Skevlo else if (pwdb <= 34) 1717264912Skevlo pwdb -= 6; 1718264912Skevlo else if (pwdb <= 42) 1719264912Skevlo pwdb -= 2; 1720264912Skevlo } 1721251538Srpaulo } 1722251538Srpaulo if (sc->avg_pwdb == -1) /* Init. */ 1723251538Srpaulo sc->avg_pwdb = pwdb; 1724251538Srpaulo else if (sc->avg_pwdb < pwdb) 1725251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1726251538Srpaulo else 1727251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1728251538Srpaulo DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1729251538Srpaulo} 1730251538Srpaulo 1731251538Srpaulostatic int8_t 1732251538Srpaulourtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1733251538Srpaulo{ 1734251538Srpaulo static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1735251538Srpaulo struct r92c_rx_phystat *phy; 1736251538Srpaulo struct r92c_rx_cck *cck; 1737251538Srpaulo uint8_t rpt; 1738251538Srpaulo int8_t rssi; 1739251538Srpaulo 1740289758Savos if (rate <= URTWN_RIDX_CCK11) { 1741251538Srpaulo cck = (struct r92c_rx_cck *)physt; 1742251538Srpaulo if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1743251538Srpaulo rpt = (cck->agc_rpt >> 5) & 0x3; 1744251538Srpaulo rssi = (cck->agc_rpt & 0x1f) << 1; 1745251538Srpaulo } else { 1746251538Srpaulo rpt = (cck->agc_rpt >> 6) & 0x3; 1747251538Srpaulo rssi = cck->agc_rpt & 0x3e; 1748251538Srpaulo } 1749251538Srpaulo rssi = cckoff[rpt] - rssi; 1750251538Srpaulo } else { /* OFDM/HT. */ 1751251538Srpaulo phy = (struct r92c_rx_phystat *)physt; 1752251538Srpaulo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1753251538Srpaulo } 1754251538Srpaulo return (rssi); 1755251538Srpaulo} 1756251538Srpaulo 1757264912Skevlostatic int8_t 1758264912Skevlourtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1759264912Skevlo{ 1760264912Skevlo struct r92c_rx_phystat *phy; 1761264912Skevlo struct r88e_rx_cck *cck; 1762264912Skevlo uint8_t cck_agc_rpt, lna_idx, vga_idx; 1763264912Skevlo int8_t rssi; 1764264912Skevlo 1765264972Skevlo rssi = 0; 1766289758Savos if (rate <= URTWN_RIDX_CCK11) { 1767264912Skevlo cck = (struct r88e_rx_cck *)physt; 1768264912Skevlo cck_agc_rpt = cck->agc_rpt; 1769264912Skevlo lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1770281069Srpaulo vga_idx = cck_agc_rpt & 0x1f; 1771264912Skevlo switch (lna_idx) { 1772264912Skevlo case 7: 1773264912Skevlo if (vga_idx <= 27) 1774264912Skevlo rssi = -100 + 2* (27 - vga_idx); 1775264912Skevlo else 1776264912Skevlo rssi = -100; 1777264912Skevlo break; 1778264912Skevlo case 6: 1779264912Skevlo rssi = -48 + 2 * (2 - vga_idx); 1780264912Skevlo break; 1781264912Skevlo case 5: 1782264912Skevlo rssi = -42 + 2 * (7 - vga_idx); 1783264912Skevlo break; 1784264912Skevlo case 4: 1785264912Skevlo rssi = -36 + 2 * (7 - vga_idx); 1786264912Skevlo break; 1787264912Skevlo case 3: 1788264912Skevlo rssi = -24 + 2 * (7 - vga_idx); 1789264912Skevlo break; 1790264912Skevlo case 2: 1791264912Skevlo rssi = -12 + 2 * (5 - vga_idx); 1792264912Skevlo break; 1793264912Skevlo case 1: 1794264912Skevlo rssi = 8 - (2 * vga_idx); 1795264912Skevlo break; 1796264912Skevlo case 0: 1797264912Skevlo rssi = 14 - (2 * vga_idx); 1798264912Skevlo break; 1799264912Skevlo } 1800264912Skevlo rssi += 6; 1801264912Skevlo } else { /* OFDM/HT. */ 1802264912Skevlo phy = (struct r92c_rx_phystat *)physt; 1803264912Skevlo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1804264912Skevlo } 1805264912Skevlo return (rssi); 1806264912Skevlo} 1807264912Skevlo 1808251538Srpaulostatic int 1809281069Srpaulourtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1810251538Srpaulo struct mbuf *m0, struct urtwn_data *data) 1811251538Srpaulo{ 1812251538Srpaulo struct ieee80211_frame *wh; 1813251538Srpaulo struct ieee80211_key *k; 1814287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1815251538Srpaulo struct ieee80211vap *vap = ni->ni_vap; 1816251538Srpaulo struct usb_xfer *xfer; 1817251538Srpaulo struct r92c_tx_desc *txd; 1818251538Srpaulo uint8_t raid, type; 1819251538Srpaulo uint16_t sum; 1820288534Sadrian int i, xferlen; 1821251538Srpaulo struct usb_xfer *urtwn_pipes[4] = { 1822251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BE], 1823251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BK], 1824251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VI], 1825251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VO] 1826251538Srpaulo }; 1827251538Srpaulo 1828251538Srpaulo URTWN_ASSERT_LOCKED(sc); 1829251538Srpaulo 1830251538Srpaulo /* 1831251538Srpaulo * Software crypto. 1832251538Srpaulo */ 1833251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1834264912Skevlo type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1835264912Skevlo 1836260444Skevlo if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1837251538Srpaulo k = ieee80211_crypto_encap(ni, m0); 1838251538Srpaulo if (k == NULL) { 1839251538Srpaulo device_printf(sc->sc_dev, 1840251538Srpaulo "ieee80211_crypto_encap returns NULL.\n"); 1841251538Srpaulo /* XXX we don't expect the fragmented frames */ 1842251538Srpaulo return (ENOBUFS); 1843251538Srpaulo } 1844251538Srpaulo 1845251538Srpaulo /* in case packet header moved, reset pointer */ 1846251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1847251538Srpaulo } 1848281069Srpaulo 1849264912Skevlo switch (type) { 1850251538Srpaulo case IEEE80211_FC0_TYPE_CTL: 1851251538Srpaulo case IEEE80211_FC0_TYPE_MGT: 1852251538Srpaulo xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1853251538Srpaulo break; 1854251538Srpaulo default: 1855251538Srpaulo KASSERT(M_WME_GETAC(m0) < 4, 1856251538Srpaulo ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1857251538Srpaulo xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1858251538Srpaulo break; 1859251538Srpaulo } 1860281069Srpaulo 1861251538Srpaulo /* Fill Tx descriptor. */ 1862251538Srpaulo txd = (struct r92c_tx_desc *)data->buf; 1863251538Srpaulo memset(txd, 0, sizeof(*txd)); 1864251538Srpaulo 1865251538Srpaulo txd->txdw0 |= htole32( 1866251538Srpaulo SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1867251538Srpaulo SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1868251538Srpaulo R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1869251538Srpaulo if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1870251538Srpaulo txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1871251538Srpaulo if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1872251538Srpaulo type == IEEE80211_FC0_TYPE_DATA) { 1873251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1874251538Srpaulo raid = R92C_RAID_11B; 1875251538Srpaulo else 1876251538Srpaulo raid = R92C_RAID_11BG; 1877264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 1878264912Skevlo txd->txdw1 |= htole32( 1879264912Skevlo SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1880264912Skevlo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1881264912Skevlo SM(R92C_TXDW1_RAID, raid)); 1882264912Skevlo txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1883264912Skevlo } else { 1884264912Skevlo txd->txdw1 |= htole32( 1885264912Skevlo SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1886264912Skevlo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1887264912Skevlo SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1888264912Skevlo } 1889251538Srpaulo if (ic->ic_flags & IEEE80211_F_USEPROT) { 1890251538Srpaulo if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1891251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1892251538Srpaulo R92C_TXDW4_HWRTSEN); 1893251538Srpaulo } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1894251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1895251538Srpaulo R92C_TXDW4_HWRTSEN); 1896251538Srpaulo } 1897251538Srpaulo } 1898251538Srpaulo /* Send RTS at OFDM24. */ 1899289758Savos txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1900289758Savos URTWN_RIDX_OFDM24)); 1901251538Srpaulo txd->txdw5 |= htole32(0x0001ff00); 1902251538Srpaulo /* Send data at OFDM54. */ 1903289758Savos txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1904289758Savos URTWN_RIDX_OFDM54)); 1905251538Srpaulo } else { 1906251538Srpaulo txd->txdw1 |= htole32( 1907251538Srpaulo SM(R92C_TXDW1_MACID, 0) | 1908251538Srpaulo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1909251538Srpaulo SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1910251538Srpaulo 1911251538Srpaulo /* Force CCK1. */ 1912251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1913289758Savos txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1914289758Savos URTWN_RIDX_CCK1)); 1915251538Srpaulo } 1916251538Srpaulo /* Set sequence number (already little endian). */ 1917251538Srpaulo txd->txdseq |= *(uint16_t *)wh->i_seq; 1918251538Srpaulo 1919288534Sadrian if (!IEEE80211_QOS_HAS_SEQ(wh)) { 1920251538Srpaulo /* Use HW sequence numbering for non-QoS frames. */ 1921251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1922251538Srpaulo txd->txdseq |= htole16(0x8000); 1923251538Srpaulo } else 1924251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1925251538Srpaulo 1926251538Srpaulo /* Compute Tx descriptor checksum. */ 1927251538Srpaulo sum = 0; 1928251538Srpaulo for (i = 0; i < sizeof(*txd) / 2; i++) 1929251538Srpaulo sum ^= ((uint16_t *)txd)[i]; 1930251538Srpaulo txd->txdsum = sum; /* NB: already little endian. */ 1931251538Srpaulo 1932251538Srpaulo if (ieee80211_radiotap_active_vap(vap)) { 1933251538Srpaulo struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1934251538Srpaulo 1935251538Srpaulo tap->wt_flags = 0; 1936251538Srpaulo tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1937251538Srpaulo tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1938251538Srpaulo ieee80211_radiotap_tx(vap, m0); 1939251538Srpaulo } 1940251538Srpaulo 1941251538Srpaulo xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1942251538Srpaulo m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1943251538Srpaulo 1944251538Srpaulo data->buflen = xferlen; 1945251538Srpaulo data->ni = ni; 1946251538Srpaulo data->m = m0; 1947251538Srpaulo 1948251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1949251538Srpaulo usbd_transfer_start(xfer); 1950251538Srpaulo return (0); 1951251538Srpaulo} 1952251538Srpaulo 1953287197Sglebiusstatic int 1954287197Sglebiusurtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1955251538Srpaulo{ 1956287197Sglebius struct urtwn_softc *sc = ic->ic_softc; 1957287197Sglebius int error; 1958261863Srpaulo 1959261863Srpaulo URTWN_LOCK(sc); 1960287197Sglebius if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1961287197Sglebius URTWN_UNLOCK(sc); 1962287197Sglebius return (ENXIO); 1963287197Sglebius } 1964287197Sglebius error = mbufq_enqueue(&sc->sc_snd, m); 1965287197Sglebius if (error) { 1966287197Sglebius URTWN_UNLOCK(sc); 1967287197Sglebius return (error); 1968287197Sglebius } 1969287197Sglebius urtwn_start(sc); 1970261863Srpaulo URTWN_UNLOCK(sc); 1971287197Sglebius 1972287197Sglebius return (0); 1973261863Srpaulo} 1974261863Srpaulo 1975261863Srpaulostatic void 1976287197Sglebiusurtwn_start(struct urtwn_softc *sc) 1977261863Srpaulo{ 1978251538Srpaulo struct ieee80211_node *ni; 1979251538Srpaulo struct mbuf *m; 1980251538Srpaulo struct urtwn_data *bf; 1981251538Srpaulo 1982261863Srpaulo URTWN_ASSERT_LOCKED(sc); 1983287197Sglebius while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1984251538Srpaulo bf = urtwn_getbuf(sc); 1985251538Srpaulo if (bf == NULL) { 1986287197Sglebius mbufq_prepend(&sc->sc_snd, m); 1987251538Srpaulo break; 1988251538Srpaulo } 1989251538Srpaulo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1990251538Srpaulo m->m_pkthdr.rcvif = NULL; 1991251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 1992287197Sglebius if_inc_counter(ni->ni_vap->iv_ifp, 1993287197Sglebius IFCOUNTER_OERRORS, 1); 1994251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1995288353Sadrian m_freem(m); 1996251538Srpaulo ieee80211_free_node(ni); 1997251538Srpaulo break; 1998251538Srpaulo } 1999251538Srpaulo sc->sc_txtimer = 5; 2000251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2001251538Srpaulo } 2002251538Srpaulo} 2003251538Srpaulo 2004287197Sglebiusstatic void 2005287197Sglebiusurtwn_parent(struct ieee80211com *ic) 2006251538Srpaulo{ 2007286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 2008287197Sglebius int startall = 0; 2009251538Srpaulo 2010263153Skevlo URTWN_LOCK(sc); 2011287197Sglebius if (sc->sc_flags & URTWN_DETACHED) { 2012287197Sglebius URTWN_UNLOCK(sc); 2013287197Sglebius return; 2014287197Sglebius } 2015287197Sglebius if (ic->ic_nrunning > 0) { 2016287197Sglebius if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2017287197Sglebius urtwn_init(sc); 2018287197Sglebius startall = 1; 2019287197Sglebius } 2020287197Sglebius } else if (sc->sc_flags & URTWN_RUNNING) 2021287197Sglebius urtwn_stop(sc); 2022263153Skevlo URTWN_UNLOCK(sc); 2023263153Skevlo 2024287197Sglebius if (startall) 2025287197Sglebius ieee80211_start_all(ic); 2026251538Srpaulo} 2027251538Srpaulo 2028264912Skevlostatic __inline int 2029251538Srpaulourtwn_power_on(struct urtwn_softc *sc) 2030251538Srpaulo{ 2031264912Skevlo 2032264912Skevlo return sc->sc_power_on(sc); 2033264912Skevlo} 2034264912Skevlo 2035264912Skevlostatic int 2036264912Skevlourtwn_r92c_power_on(struct urtwn_softc *sc) 2037264912Skevlo{ 2038251538Srpaulo uint32_t reg; 2039251538Srpaulo int ntries; 2040251538Srpaulo 2041251538Srpaulo /* Wait for autoload done bit. */ 2042251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2043251538Srpaulo if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2044251538Srpaulo break; 2045266472Shselasky urtwn_ms_delay(sc); 2046251538Srpaulo } 2047251538Srpaulo if (ntries == 1000) { 2048251538Srpaulo device_printf(sc->sc_dev, 2049251538Srpaulo "timeout waiting for chip autoload\n"); 2050251538Srpaulo return (ETIMEDOUT); 2051251538Srpaulo } 2052251538Srpaulo 2053251538Srpaulo /* Unlock ISO/CLK/Power control register. */ 2054251538Srpaulo urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2055251538Srpaulo /* Move SPS into PWM mode. */ 2056251538Srpaulo urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2057266472Shselasky urtwn_ms_delay(sc); 2058251538Srpaulo 2059251538Srpaulo reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2060251538Srpaulo if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2061251538Srpaulo urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2062251538Srpaulo reg | R92C_LDOV12D_CTRL_LDV12_EN); 2063266472Shselasky urtwn_ms_delay(sc); 2064251538Srpaulo urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2065251538Srpaulo urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2066251538Srpaulo ~R92C_SYS_ISO_CTRL_MD2PP); 2067251538Srpaulo } 2068251538Srpaulo 2069251538Srpaulo /* Auto enable WLAN. */ 2070251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2071251538Srpaulo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2072251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2073262822Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2074262822Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2075251538Srpaulo break; 2076266472Shselasky urtwn_ms_delay(sc); 2077251538Srpaulo } 2078251538Srpaulo if (ntries == 1000) { 2079251538Srpaulo device_printf(sc->sc_dev, 2080251538Srpaulo "timeout waiting for MAC auto ON\n"); 2081251538Srpaulo return (ETIMEDOUT); 2082251538Srpaulo } 2083251538Srpaulo 2084251538Srpaulo /* Enable radio, GPIO and LED functions. */ 2085251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2086251538Srpaulo R92C_APS_FSMCO_AFSM_HSUS | 2087251538Srpaulo R92C_APS_FSMCO_PDN_EN | 2088251538Srpaulo R92C_APS_FSMCO_PFM_ALDN); 2089251538Srpaulo /* Release RF digital isolation. */ 2090251538Srpaulo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2091251538Srpaulo urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2092251538Srpaulo 2093251538Srpaulo /* Initialize MAC. */ 2094251538Srpaulo urtwn_write_1(sc, R92C_APSD_CTRL, 2095251538Srpaulo urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2096251538Srpaulo for (ntries = 0; ntries < 200; ntries++) { 2097251538Srpaulo if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2098251538Srpaulo R92C_APSD_CTRL_OFF_STATUS)) 2099251538Srpaulo break; 2100266472Shselasky urtwn_ms_delay(sc); 2101251538Srpaulo } 2102251538Srpaulo if (ntries == 200) { 2103251538Srpaulo device_printf(sc->sc_dev, 2104251538Srpaulo "timeout waiting for MAC initialization\n"); 2105251538Srpaulo return (ETIMEDOUT); 2106251538Srpaulo } 2107251538Srpaulo 2108251538Srpaulo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2109251538Srpaulo reg = urtwn_read_2(sc, R92C_CR); 2110251538Srpaulo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2111251538Srpaulo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2112251538Srpaulo R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2113251538Srpaulo R92C_CR_ENSEC; 2114251538Srpaulo urtwn_write_2(sc, R92C_CR, reg); 2115251538Srpaulo 2116251538Srpaulo urtwn_write_1(sc, 0xfe10, 0x19); 2117251538Srpaulo return (0); 2118251538Srpaulo} 2119251538Srpaulo 2120251538Srpaulostatic int 2121264912Skevlourtwn_r88e_power_on(struct urtwn_softc *sc) 2122264912Skevlo{ 2123264912Skevlo uint32_t reg; 2124264912Skevlo int ntries; 2125264912Skevlo 2126264912Skevlo /* Wait for power ready bit. */ 2127264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2128281918Skevlo if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2129264912Skevlo break; 2130266472Shselasky urtwn_ms_delay(sc); 2131264912Skevlo } 2132264912Skevlo if (ntries == 5000) { 2133264912Skevlo device_printf(sc->sc_dev, 2134264912Skevlo "timeout waiting for chip power up\n"); 2135264912Skevlo return (ETIMEDOUT); 2136264912Skevlo } 2137264912Skevlo 2138264912Skevlo /* Reset BB. */ 2139264912Skevlo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2140264912Skevlo urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2141264912Skevlo R92C_SYS_FUNC_EN_BB_GLB_RST)); 2142264912Skevlo 2143281918Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2144281918Skevlo urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2145264912Skevlo 2146264912Skevlo /* Disable HWPDN. */ 2147281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2148281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2149264912Skevlo 2150264912Skevlo /* Disable WL suspend. */ 2151281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2152281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & 2153281918Skevlo ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2154264912Skevlo 2155281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2156281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2157264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2158281918Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2159281918Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2160264912Skevlo break; 2161266472Shselasky urtwn_ms_delay(sc); 2162264912Skevlo } 2163264912Skevlo if (ntries == 5000) 2164264912Skevlo return (ETIMEDOUT); 2165264912Skevlo 2166264912Skevlo /* Enable LDO normal mode. */ 2167281918Skevlo urtwn_write_1(sc, R92C_LPLDO_CTRL, 2168281918Skevlo urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2169264912Skevlo 2170264912Skevlo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2171264912Skevlo urtwn_write_2(sc, R92C_CR, 0); 2172264912Skevlo reg = urtwn_read_2(sc, R92C_CR); 2173264912Skevlo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2174264912Skevlo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2175264912Skevlo R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2176264912Skevlo urtwn_write_2(sc, R92C_CR, reg); 2177264912Skevlo 2178264912Skevlo return (0); 2179264912Skevlo} 2180264912Skevlo 2181264912Skevlostatic int 2182251538Srpaulourtwn_llt_init(struct urtwn_softc *sc) 2183251538Srpaulo{ 2184264912Skevlo int i, error, page_count, pktbuf_count; 2185251538Srpaulo 2186264912Skevlo page_count = (sc->chip & URTWN_CHIP_88E) ? 2187264912Skevlo R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2188264912Skevlo pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2189264912Skevlo R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2190264912Skevlo 2191264912Skevlo /* Reserve pages [0; page_count]. */ 2192264912Skevlo for (i = 0; i < page_count; i++) { 2193251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2194251538Srpaulo return (error); 2195251538Srpaulo } 2196251538Srpaulo /* NB: 0xff indicates end-of-list. */ 2197251538Srpaulo if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2198251538Srpaulo return (error); 2199251538Srpaulo /* 2200264912Skevlo * Use pages [page_count + 1; pktbuf_count - 1] 2201251538Srpaulo * as ring buffer. 2202251538Srpaulo */ 2203264912Skevlo for (++i; i < pktbuf_count - 1; i++) { 2204251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2205251538Srpaulo return (error); 2206251538Srpaulo } 2207251538Srpaulo /* Make the last page point to the beginning of the ring buffer. */ 2208264912Skevlo error = urtwn_llt_write(sc, i, page_count + 1); 2209251538Srpaulo return (error); 2210251538Srpaulo} 2211251538Srpaulo 2212251538Srpaulostatic void 2213251538Srpaulourtwn_fw_reset(struct urtwn_softc *sc) 2214251538Srpaulo{ 2215251538Srpaulo uint16_t reg; 2216251538Srpaulo int ntries; 2217251538Srpaulo 2218251538Srpaulo /* Tell 8051 to reset itself. */ 2219251538Srpaulo urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2220251538Srpaulo 2221251538Srpaulo /* Wait until 8051 resets by itself. */ 2222251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 2223251538Srpaulo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2224251538Srpaulo if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2225251538Srpaulo return; 2226266472Shselasky urtwn_ms_delay(sc); 2227251538Srpaulo } 2228251538Srpaulo /* Force 8051 reset. */ 2229251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2230251538Srpaulo} 2231251538Srpaulo 2232264912Skevlostatic void 2233264912Skevlourtwn_r88e_fw_reset(struct urtwn_softc *sc) 2234264912Skevlo{ 2235264912Skevlo uint16_t reg; 2236264912Skevlo 2237264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2238264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2239264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2240264912Skevlo} 2241264912Skevlo 2242251538Srpaulostatic int 2243251538Srpaulourtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2244251538Srpaulo{ 2245251538Srpaulo uint32_t reg; 2246251538Srpaulo int off, mlen, error = 0; 2247251538Srpaulo 2248251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2249251538Srpaulo reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2250251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2251251538Srpaulo 2252251538Srpaulo off = R92C_FW_START_ADDR; 2253251538Srpaulo while (len > 0) { 2254251538Srpaulo if (len > 196) 2255251538Srpaulo mlen = 196; 2256251538Srpaulo else if (len > 4) 2257251538Srpaulo mlen = 4; 2258251538Srpaulo else 2259251538Srpaulo mlen = 1; 2260251538Srpaulo /* XXX fix this deconst */ 2261281069Srpaulo error = urtwn_write_region_1(sc, off, 2262251538Srpaulo __DECONST(uint8_t *, buf), mlen); 2263251538Srpaulo if (error != 0) 2264251538Srpaulo break; 2265251538Srpaulo off += mlen; 2266251538Srpaulo buf += mlen; 2267251538Srpaulo len -= mlen; 2268251538Srpaulo } 2269251538Srpaulo return (error); 2270251538Srpaulo} 2271251538Srpaulo 2272251538Srpaulostatic int 2273251538Srpaulourtwn_load_firmware(struct urtwn_softc *sc) 2274251538Srpaulo{ 2275251538Srpaulo const struct firmware *fw; 2276251538Srpaulo const struct r92c_fw_hdr *hdr; 2277251538Srpaulo const char *imagename; 2278251538Srpaulo const u_char *ptr; 2279251538Srpaulo size_t len; 2280251538Srpaulo uint32_t reg; 2281251538Srpaulo int mlen, ntries, page, error; 2282251538Srpaulo 2283264864Skevlo URTWN_UNLOCK(sc); 2284251538Srpaulo /* Read firmware image from the filesystem. */ 2285264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2286264912Skevlo imagename = "urtwn-rtl8188eufw"; 2287264912Skevlo else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2288264912Skevlo URTWN_CHIP_UMC_A_CUT) 2289251538Srpaulo imagename = "urtwn-rtl8192cfwU"; 2290251538Srpaulo else 2291251538Srpaulo imagename = "urtwn-rtl8192cfwT"; 2292251538Srpaulo 2293251538Srpaulo fw = firmware_get(imagename); 2294264864Skevlo URTWN_LOCK(sc); 2295251538Srpaulo if (fw == NULL) { 2296251538Srpaulo device_printf(sc->sc_dev, 2297251538Srpaulo "failed loadfirmware of file %s\n", imagename); 2298251538Srpaulo return (ENOENT); 2299251538Srpaulo } 2300251538Srpaulo 2301251538Srpaulo len = fw->datasize; 2302251538Srpaulo 2303251538Srpaulo if (len < sizeof(*hdr)) { 2304251538Srpaulo device_printf(sc->sc_dev, "firmware too short\n"); 2305251538Srpaulo error = EINVAL; 2306251538Srpaulo goto fail; 2307251538Srpaulo } 2308251538Srpaulo ptr = fw->data; 2309251538Srpaulo hdr = (const struct r92c_fw_hdr *)ptr; 2310251538Srpaulo /* Check if there is a valid FW header and skip it. */ 2311251538Srpaulo if ((le16toh(hdr->signature) >> 4) == 0x88c || 2312264912Skevlo (le16toh(hdr->signature) >> 4) == 0x88e || 2313251538Srpaulo (le16toh(hdr->signature) >> 4) == 0x92c) { 2314251538Srpaulo DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2315251538Srpaulo le16toh(hdr->version), le16toh(hdr->subversion), 2316251538Srpaulo hdr->month, hdr->date, hdr->hour, hdr->minute); 2317251538Srpaulo ptr += sizeof(*hdr); 2318251538Srpaulo len -= sizeof(*hdr); 2319251538Srpaulo } 2320251538Srpaulo 2321264912Skevlo if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2322264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2323264912Skevlo urtwn_r88e_fw_reset(sc); 2324264912Skevlo else 2325264912Skevlo urtwn_fw_reset(sc); 2326251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 0); 2327251538Srpaulo } 2328264912Skevlo 2329268487Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2330268487Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2331268487Skevlo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2332268487Skevlo R92C_SYS_FUNC_EN_CPUEN); 2333268487Skevlo } 2334251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2335251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2336251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 2, 2337251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2338251538Srpaulo 2339263154Skevlo /* Reset the FWDL checksum. */ 2340263154Skevlo urtwn_write_1(sc, R92C_MCUFWDL, 2341263154Skevlo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2342263154Skevlo 2343251538Srpaulo for (page = 0; len > 0; page++) { 2344251538Srpaulo mlen = min(len, R92C_FW_PAGE_SIZE); 2345251538Srpaulo error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2346251538Srpaulo if (error != 0) { 2347251538Srpaulo device_printf(sc->sc_dev, 2348251538Srpaulo "could not load firmware page\n"); 2349251538Srpaulo goto fail; 2350251538Srpaulo } 2351251538Srpaulo ptr += mlen; 2352251538Srpaulo len -= mlen; 2353251538Srpaulo } 2354251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2355251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2356251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2357251538Srpaulo 2358251538Srpaulo /* Wait for checksum report. */ 2359251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2360251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2361251538Srpaulo break; 2362266472Shselasky urtwn_ms_delay(sc); 2363251538Srpaulo } 2364251538Srpaulo if (ntries == 1000) { 2365251538Srpaulo device_printf(sc->sc_dev, 2366251538Srpaulo "timeout waiting for checksum report\n"); 2367251538Srpaulo error = ETIMEDOUT; 2368251538Srpaulo goto fail; 2369251538Srpaulo } 2370251538Srpaulo 2371251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2372251538Srpaulo reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2373251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2374264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2375264912Skevlo urtwn_r88e_fw_reset(sc); 2376251538Srpaulo /* Wait for firmware readiness. */ 2377251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2378251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2379251538Srpaulo break; 2380266472Shselasky urtwn_ms_delay(sc); 2381251538Srpaulo } 2382251538Srpaulo if (ntries == 1000) { 2383251538Srpaulo device_printf(sc->sc_dev, 2384251538Srpaulo "timeout waiting for firmware readiness\n"); 2385251538Srpaulo error = ETIMEDOUT; 2386251538Srpaulo goto fail; 2387251538Srpaulo } 2388251538Srpaulofail: 2389251538Srpaulo firmware_put(fw, FIRMWARE_UNLOAD); 2390251538Srpaulo return (error); 2391251538Srpaulo} 2392251538Srpaulo 2393264912Skevlostatic __inline int 2394251538Srpaulourtwn_dma_init(struct urtwn_softc *sc) 2395251538Srpaulo{ 2396281069Srpaulo 2397264912Skevlo return sc->sc_dma_init(sc); 2398264912Skevlo} 2399264912Skevlo 2400264912Skevlostatic int 2401264912Skevlourtwn_r92c_dma_init(struct urtwn_softc *sc) 2402264912Skevlo{ 2403251538Srpaulo int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2404251538Srpaulo uint32_t reg; 2405251538Srpaulo int error; 2406251538Srpaulo 2407251538Srpaulo /* Initialize LLT table. */ 2408251538Srpaulo error = urtwn_llt_init(sc); 2409251538Srpaulo if (error != 0) 2410251538Srpaulo return (error); 2411251538Srpaulo 2412251538Srpaulo /* Get Tx queues to USB endpoints mapping. */ 2413251538Srpaulo hashq = hasnq = haslq = 0; 2414251538Srpaulo reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2415251538Srpaulo DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2416251538Srpaulo if (MS(reg, R92C_USB_EP_HQ) != 0) 2417251538Srpaulo hashq = 1; 2418251538Srpaulo if (MS(reg, R92C_USB_EP_NQ) != 0) 2419251538Srpaulo hasnq = 1; 2420251538Srpaulo if (MS(reg, R92C_USB_EP_LQ) != 0) 2421251538Srpaulo haslq = 1; 2422251538Srpaulo nqueues = hashq + hasnq + haslq; 2423251538Srpaulo if (nqueues == 0) 2424251538Srpaulo return (EIO); 2425251538Srpaulo /* Get the number of pages for each queue. */ 2426251538Srpaulo nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2427251538Srpaulo /* The remaining pages are assigned to the high priority queue. */ 2428251538Srpaulo nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2429251538Srpaulo 2430251538Srpaulo /* Set number of pages for normal priority queue. */ 2431251538Srpaulo urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2432251538Srpaulo urtwn_write_4(sc, R92C_RQPN, 2433251538Srpaulo /* Set number of pages for public queue. */ 2434251538Srpaulo SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2435251538Srpaulo /* Set number of pages for high priority queue. */ 2436251538Srpaulo SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2437251538Srpaulo /* Set number of pages for low priority queue. */ 2438251538Srpaulo SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2439251538Srpaulo /* Load values. */ 2440251538Srpaulo R92C_RQPN_LD); 2441251538Srpaulo 2442251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2443251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2444251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2445251538Srpaulo urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2446251538Srpaulo urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2447251538Srpaulo 2448251538Srpaulo /* Set queue to USB pipe mapping. */ 2449251538Srpaulo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2450251538Srpaulo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2451251538Srpaulo if (nqueues == 1) { 2452251538Srpaulo if (hashq) 2453251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2454251538Srpaulo else if (hasnq) 2455251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2456251538Srpaulo else 2457251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2458251538Srpaulo } else if (nqueues == 2) { 2459251538Srpaulo /* All 2-endpoints configs have a high priority queue. */ 2460251538Srpaulo if (!hashq) 2461251538Srpaulo return (EIO); 2462251538Srpaulo if (hasnq) 2463251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2464251538Srpaulo else 2465251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2466251538Srpaulo } else 2467251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2468251538Srpaulo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2469251538Srpaulo 2470251538Srpaulo /* Set Tx/Rx transfer page boundary. */ 2471251538Srpaulo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2472251538Srpaulo 2473251538Srpaulo /* Set Tx/Rx transfer page size. */ 2474251538Srpaulo urtwn_write_1(sc, R92C_PBP, 2475251538Srpaulo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2476251538Srpaulo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2477251538Srpaulo return (0); 2478251538Srpaulo} 2479251538Srpaulo 2480264912Skevlostatic int 2481264912Skevlourtwn_r88e_dma_init(struct urtwn_softc *sc) 2482264912Skevlo{ 2483264912Skevlo struct usb_interface *iface; 2484264912Skevlo uint32_t reg; 2485264912Skevlo int nqueues; 2486264912Skevlo int error; 2487264912Skevlo 2488264912Skevlo /* Initialize LLT table. */ 2489264912Skevlo error = urtwn_llt_init(sc); 2490264912Skevlo if (error != 0) 2491264912Skevlo return (error); 2492264912Skevlo 2493264912Skevlo /* Get Tx queues to USB endpoints mapping. */ 2494264912Skevlo iface = usbd_get_iface(sc->sc_udev, 0); 2495264912Skevlo nqueues = iface->idesc->bNumEndpoints - 1; 2496264912Skevlo if (nqueues == 0) 2497264912Skevlo return (EIO); 2498264912Skevlo 2499264912Skevlo /* Set number of pages for normal priority queue. */ 2500264912Skevlo urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2501264912Skevlo urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2502264912Skevlo 2503264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2504264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2505264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2506264912Skevlo urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2507264912Skevlo urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2508264912Skevlo 2509264912Skevlo /* Set queue to USB pipe mapping. */ 2510264912Skevlo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2511264912Skevlo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2512264912Skevlo if (nqueues == 1) 2513264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2514264912Skevlo else if (nqueues == 2) 2515264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2516264912Skevlo else 2517264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2518264912Skevlo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2519264912Skevlo 2520264912Skevlo /* Set Tx/Rx transfer page boundary. */ 2521264912Skevlo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2522264912Skevlo 2523264912Skevlo /* Set Tx/Rx transfer page size. */ 2524264912Skevlo urtwn_write_1(sc, R92C_PBP, 2525264912Skevlo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2526264912Skevlo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2527264912Skevlo 2528264912Skevlo return (0); 2529264912Skevlo} 2530264912Skevlo 2531251538Srpaulostatic void 2532251538Srpaulourtwn_mac_init(struct urtwn_softc *sc) 2533251538Srpaulo{ 2534251538Srpaulo int i; 2535251538Srpaulo 2536251538Srpaulo /* Write MAC initialization values. */ 2537264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2538264912Skevlo for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2539264912Skevlo urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2540264912Skevlo rtl8188eu_mac[i].val); 2541264912Skevlo } 2542264912Skevlo urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2543264912Skevlo } else { 2544264912Skevlo for (i = 0; i < nitems(rtl8192cu_mac); i++) 2545264912Skevlo urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2546264912Skevlo rtl8192cu_mac[i].val); 2547264912Skevlo } 2548251538Srpaulo} 2549251538Srpaulo 2550251538Srpaulostatic void 2551251538Srpaulourtwn_bb_init(struct urtwn_softc *sc) 2552251538Srpaulo{ 2553251538Srpaulo const struct urtwn_bb_prog *prog; 2554251538Srpaulo uint32_t reg; 2555264912Skevlo uint8_t crystalcap; 2556251538Srpaulo int i; 2557251538Srpaulo 2558251538Srpaulo /* Enable BB and RF. */ 2559251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2560251538Srpaulo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2561251538Srpaulo R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2562251538Srpaulo R92C_SYS_FUNC_EN_DIO_RF); 2563251538Srpaulo 2564264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 2565264912Skevlo urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2566251538Srpaulo 2567251538Srpaulo urtwn_write_1(sc, R92C_RF_CTRL, 2568251538Srpaulo R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2569251538Srpaulo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2570251538Srpaulo R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2571251538Srpaulo R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2572251538Srpaulo 2573264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2574264912Skevlo urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2575264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 2576264912Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2577264912Skevlo } 2578251538Srpaulo 2579251538Srpaulo /* Select BB programming based on board type. */ 2580264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2581264912Skevlo prog = &rtl8188eu_bb_prog; 2582264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2583251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2584251538Srpaulo prog = &rtl8188ce_bb_prog; 2585251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2586251538Srpaulo prog = &rtl8188ru_bb_prog; 2587251538Srpaulo else 2588251538Srpaulo prog = &rtl8188cu_bb_prog; 2589251538Srpaulo } else { 2590251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2591251538Srpaulo prog = &rtl8192ce_bb_prog; 2592251538Srpaulo else 2593251538Srpaulo prog = &rtl8192cu_bb_prog; 2594251538Srpaulo } 2595251538Srpaulo /* Write BB initialization values. */ 2596251538Srpaulo for (i = 0; i < prog->count; i++) { 2597251538Srpaulo urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2598266472Shselasky urtwn_ms_delay(sc); 2599251538Srpaulo } 2600251538Srpaulo 2601251538Srpaulo if (sc->chip & URTWN_CHIP_92C_1T2R) { 2602251538Srpaulo /* 8192C 1T only configuration. */ 2603251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2604251538Srpaulo reg = (reg & ~0x00000003) | 0x2; 2605251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2606251538Srpaulo 2607251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2608251538Srpaulo reg = (reg & ~0x00300033) | 0x00200022; 2609251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2610251538Srpaulo 2611251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2612251538Srpaulo reg = (reg & ~0xff000000) | 0x45 << 24; 2613251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2614251538Srpaulo 2615251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2616251538Srpaulo reg = (reg & ~0x000000ff) | 0x23; 2617251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2618251538Srpaulo 2619251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2620251538Srpaulo reg = (reg & ~0x00000030) | 1 << 4; 2621251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2622251538Srpaulo 2623251538Srpaulo reg = urtwn_bb_read(sc, 0xe74); 2624251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2625251538Srpaulo urtwn_bb_write(sc, 0xe74, reg); 2626251538Srpaulo reg = urtwn_bb_read(sc, 0xe78); 2627251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2628251538Srpaulo urtwn_bb_write(sc, 0xe78, reg); 2629251538Srpaulo reg = urtwn_bb_read(sc, 0xe7c); 2630251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2631251538Srpaulo urtwn_bb_write(sc, 0xe7c, reg); 2632251538Srpaulo reg = urtwn_bb_read(sc, 0xe80); 2633251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2634251538Srpaulo urtwn_bb_write(sc, 0xe80, reg); 2635251538Srpaulo reg = urtwn_bb_read(sc, 0xe88); 2636251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2637251538Srpaulo urtwn_bb_write(sc, 0xe88, reg); 2638251538Srpaulo } 2639251538Srpaulo 2640251538Srpaulo /* Write AGC values. */ 2641251538Srpaulo for (i = 0; i < prog->agccount; i++) { 2642251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2643251538Srpaulo prog->agcvals[i]); 2644266472Shselasky urtwn_ms_delay(sc); 2645251538Srpaulo } 2646251538Srpaulo 2647264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2648264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2649266472Shselasky urtwn_ms_delay(sc); 2650264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2651266472Shselasky urtwn_ms_delay(sc); 2652264912Skevlo 2653264912Skevlo crystalcap = sc->r88e_rom[0xb9]; 2654264912Skevlo if (crystalcap == 0xff) 2655264912Skevlo crystalcap = 0x20; 2656264912Skevlo crystalcap &= 0x3f; 2657264912Skevlo reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2658264912Skevlo urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2659264912Skevlo RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2660264912Skevlo crystalcap | crystalcap << 6)); 2661264912Skevlo } else { 2662264912Skevlo if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2663264912Skevlo R92C_HSSI_PARAM2_CCK_HIPWR) 2664264912Skevlo sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2665264912Skevlo } 2666251538Srpaulo} 2667251538Srpaulo 2668289066Skevlostatic void 2669251538Srpaulourtwn_rf_init(struct urtwn_softc *sc) 2670251538Srpaulo{ 2671251538Srpaulo const struct urtwn_rf_prog *prog; 2672251538Srpaulo uint32_t reg, type; 2673251538Srpaulo int i, j, idx, off; 2674251538Srpaulo 2675251538Srpaulo /* Select RF programming based on board type. */ 2676264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2677264912Skevlo prog = rtl8188eu_rf_prog; 2678264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2679251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2680251538Srpaulo prog = rtl8188ce_rf_prog; 2681251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2682251538Srpaulo prog = rtl8188ru_rf_prog; 2683251538Srpaulo else 2684251538Srpaulo prog = rtl8188cu_rf_prog; 2685251538Srpaulo } else 2686251538Srpaulo prog = rtl8192ce_rf_prog; 2687251538Srpaulo 2688251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2689251538Srpaulo /* Save RF_ENV control type. */ 2690251538Srpaulo idx = i / 2; 2691251538Srpaulo off = (i % 2) * 16; 2692251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2693251538Srpaulo type = (reg >> off) & 0x10; 2694251538Srpaulo 2695251538Srpaulo /* Set RF_ENV enable. */ 2696251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2697251538Srpaulo reg |= 0x100000; 2698251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2699266472Shselasky urtwn_ms_delay(sc); 2700251538Srpaulo /* Set RF_ENV output high. */ 2701251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2702251538Srpaulo reg |= 0x10; 2703251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2704266472Shselasky urtwn_ms_delay(sc); 2705251538Srpaulo /* Set address and data lengths of RF registers. */ 2706251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2707251538Srpaulo reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2708251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2709266472Shselasky urtwn_ms_delay(sc); 2710251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2711251538Srpaulo reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2712251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2713266472Shselasky urtwn_ms_delay(sc); 2714251538Srpaulo 2715251538Srpaulo /* Write RF initialization values for this chain. */ 2716251538Srpaulo for (j = 0; j < prog[i].count; j++) { 2717251538Srpaulo if (prog[i].regs[j] >= 0xf9 && 2718251538Srpaulo prog[i].regs[j] <= 0xfe) { 2719251538Srpaulo /* 2720251538Srpaulo * These are fake RF registers offsets that 2721251538Srpaulo * indicate a delay is required. 2722251538Srpaulo */ 2723266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2724251538Srpaulo continue; 2725251538Srpaulo } 2726251538Srpaulo urtwn_rf_write(sc, i, prog[i].regs[j], 2727251538Srpaulo prog[i].vals[j]); 2728266472Shselasky urtwn_ms_delay(sc); 2729251538Srpaulo } 2730251538Srpaulo 2731251538Srpaulo /* Restore RF_ENV control type. */ 2732251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2733251538Srpaulo reg &= ~(0x10 << off) | (type << off); 2734251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2735251538Srpaulo 2736251538Srpaulo /* Cache RF register CHNLBW. */ 2737251538Srpaulo sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2738251538Srpaulo } 2739251538Srpaulo 2740251538Srpaulo if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2741251538Srpaulo URTWN_CHIP_UMC_A_CUT) { 2742251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2743251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2744251538Srpaulo } 2745251538Srpaulo} 2746251538Srpaulo 2747251538Srpaulostatic void 2748251538Srpaulourtwn_cam_init(struct urtwn_softc *sc) 2749251538Srpaulo{ 2750251538Srpaulo /* Invalidate all CAM entries. */ 2751251538Srpaulo urtwn_write_4(sc, R92C_CAMCMD, 2752251538Srpaulo R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2753251538Srpaulo} 2754251538Srpaulo 2755251538Srpaulostatic void 2756251538Srpaulourtwn_pa_bias_init(struct urtwn_softc *sc) 2757251538Srpaulo{ 2758251538Srpaulo uint8_t reg; 2759251538Srpaulo int i; 2760251538Srpaulo 2761251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2762251538Srpaulo if (sc->pa_setting & (1 << i)) 2763251538Srpaulo continue; 2764251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2765251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2766251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2767251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2768251538Srpaulo } 2769251538Srpaulo if (!(sc->pa_setting & 0x10)) { 2770251538Srpaulo reg = urtwn_read_1(sc, 0x16); 2771251538Srpaulo reg = (reg & ~0xf0) | 0x90; 2772251538Srpaulo urtwn_write_1(sc, 0x16, reg); 2773251538Srpaulo } 2774251538Srpaulo} 2775251538Srpaulo 2776251538Srpaulostatic void 2777251538Srpaulourtwn_rxfilter_init(struct urtwn_softc *sc) 2778251538Srpaulo{ 2779251538Srpaulo /* Initialize Rx filter. */ 2780251538Srpaulo /* TODO: use better filter for monitor mode. */ 2781251538Srpaulo urtwn_write_4(sc, R92C_RCR, 2782251538Srpaulo R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2783251538Srpaulo R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2784251538Srpaulo R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2785251538Srpaulo /* Accept all multicast frames. */ 2786251538Srpaulo urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2787251538Srpaulo urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2788251538Srpaulo /* Accept all management frames. */ 2789251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2790251538Srpaulo /* Reject all control frames. */ 2791251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2792251538Srpaulo /* Accept all data frames. */ 2793251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2794251538Srpaulo} 2795251538Srpaulo 2796251538Srpaulostatic void 2797251538Srpaulourtwn_edca_init(struct urtwn_softc *sc) 2798251538Srpaulo{ 2799251538Srpaulo urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2800251538Srpaulo urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2801251538Srpaulo urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2802251538Srpaulo urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2803251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2804251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2805251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2806251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2807251538Srpaulo} 2808251538Srpaulo 2809289066Skevlostatic void 2810251538Srpaulourtwn_write_txpower(struct urtwn_softc *sc, int chain, 2811251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2812251538Srpaulo{ 2813251538Srpaulo uint32_t reg; 2814251538Srpaulo 2815251538Srpaulo /* Write per-CCK rate Tx power. */ 2816251538Srpaulo if (chain == 0) { 2817251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2818251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2819251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2820251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2821251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2822251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2823251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2824251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2825251538Srpaulo } else { 2826251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2827251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2828251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2829251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2830251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2831251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2832251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2833251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2834251538Srpaulo } 2835251538Srpaulo /* Write per-OFDM rate Tx power. */ 2836251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2837251538Srpaulo SM(R92C_TXAGC_RATE06, power[ 4]) | 2838251538Srpaulo SM(R92C_TXAGC_RATE09, power[ 5]) | 2839251538Srpaulo SM(R92C_TXAGC_RATE12, power[ 6]) | 2840251538Srpaulo SM(R92C_TXAGC_RATE18, power[ 7])); 2841251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2842251538Srpaulo SM(R92C_TXAGC_RATE24, power[ 8]) | 2843251538Srpaulo SM(R92C_TXAGC_RATE36, power[ 9]) | 2844251538Srpaulo SM(R92C_TXAGC_RATE48, power[10]) | 2845251538Srpaulo SM(R92C_TXAGC_RATE54, power[11])); 2846251538Srpaulo /* Write per-MCS Tx power. */ 2847251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2848251538Srpaulo SM(R92C_TXAGC_MCS00, power[12]) | 2849251538Srpaulo SM(R92C_TXAGC_MCS01, power[13]) | 2850251538Srpaulo SM(R92C_TXAGC_MCS02, power[14]) | 2851251538Srpaulo SM(R92C_TXAGC_MCS03, power[15])); 2852251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2853251538Srpaulo SM(R92C_TXAGC_MCS04, power[16]) | 2854251538Srpaulo SM(R92C_TXAGC_MCS05, power[17]) | 2855251538Srpaulo SM(R92C_TXAGC_MCS06, power[18]) | 2856251538Srpaulo SM(R92C_TXAGC_MCS07, power[19])); 2857251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2858251538Srpaulo SM(R92C_TXAGC_MCS08, power[20]) | 2859261506Skevlo SM(R92C_TXAGC_MCS09, power[21]) | 2860251538Srpaulo SM(R92C_TXAGC_MCS10, power[22]) | 2861251538Srpaulo SM(R92C_TXAGC_MCS11, power[23])); 2862251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2863251538Srpaulo SM(R92C_TXAGC_MCS12, power[24]) | 2864251538Srpaulo SM(R92C_TXAGC_MCS13, power[25]) | 2865251538Srpaulo SM(R92C_TXAGC_MCS14, power[26]) | 2866251538Srpaulo SM(R92C_TXAGC_MCS15, power[27])); 2867251538Srpaulo} 2868251538Srpaulo 2869289066Skevlostatic void 2870251538Srpaulourtwn_get_txpower(struct urtwn_softc *sc, int chain, 2871251538Srpaulo struct ieee80211_channel *c, struct ieee80211_channel *extc, 2872251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2873251538Srpaulo{ 2874287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 2875251538Srpaulo struct r92c_rom *rom = &sc->rom; 2876251538Srpaulo uint16_t cckpow, ofdmpow, htpow, diff, max; 2877251538Srpaulo const struct urtwn_txpwr *base; 2878251538Srpaulo int ridx, chan, group; 2879251538Srpaulo 2880251538Srpaulo /* Determine channel group. */ 2881251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2882251538Srpaulo if (chan <= 3) 2883251538Srpaulo group = 0; 2884251538Srpaulo else if (chan <= 9) 2885251538Srpaulo group = 1; 2886251538Srpaulo else 2887251538Srpaulo group = 2; 2888251538Srpaulo 2889251538Srpaulo /* Get original Tx power based on board type and RF chain. */ 2890251538Srpaulo if (!(sc->chip & URTWN_CHIP_92C)) { 2891251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2892251538Srpaulo base = &rtl8188ru_txagc[chain]; 2893251538Srpaulo else 2894251538Srpaulo base = &rtl8192cu_txagc[chain]; 2895251538Srpaulo } else 2896251538Srpaulo base = &rtl8192cu_txagc[chain]; 2897251538Srpaulo 2898251538Srpaulo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2899251538Srpaulo if (sc->regulatory == 0) { 2900289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 2901251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2902251538Srpaulo } 2903289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 2904251538Srpaulo if (sc->regulatory == 3) { 2905251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2906251538Srpaulo /* Apply vendor limits. */ 2907251538Srpaulo if (extc != NULL) 2908251538Srpaulo max = rom->ht40_max_pwr[group]; 2909251538Srpaulo else 2910251538Srpaulo max = rom->ht20_max_pwr[group]; 2911251538Srpaulo max = (max >> (chain * 4)) & 0xf; 2912251538Srpaulo if (power[ridx] > max) 2913251538Srpaulo power[ridx] = max; 2914251538Srpaulo } else if (sc->regulatory == 1) { 2915251538Srpaulo if (extc == NULL) 2916251538Srpaulo power[ridx] = base->pwr[group][ridx]; 2917251538Srpaulo } else if (sc->regulatory != 2) 2918251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2919251538Srpaulo } 2920251538Srpaulo 2921251538Srpaulo /* Compute per-CCK rate Tx power. */ 2922251538Srpaulo cckpow = rom->cck_tx_pwr[chain][group]; 2923289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 2924251538Srpaulo power[ridx] += cckpow; 2925251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2926251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2927251538Srpaulo } 2928251538Srpaulo 2929251538Srpaulo htpow = rom->ht40_1s_tx_pwr[chain][group]; 2930251538Srpaulo if (sc->ntxchains > 1) { 2931251538Srpaulo /* Apply reduction for 2 spatial streams. */ 2932251538Srpaulo diff = rom->ht40_2s_tx_pwr_diff[group]; 2933251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2934251538Srpaulo htpow = (htpow > diff) ? htpow - diff : 0; 2935251538Srpaulo } 2936251538Srpaulo 2937251538Srpaulo /* Compute per-OFDM rate Tx power. */ 2938251538Srpaulo diff = rom->ofdm_tx_pwr_diff[group]; 2939251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2940251538Srpaulo ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2941289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 2942251538Srpaulo power[ridx] += ofdmpow; 2943251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2944251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2945251538Srpaulo } 2946251538Srpaulo 2947251538Srpaulo /* Compute per-MCS Tx power. */ 2948251538Srpaulo if (extc == NULL) { 2949251538Srpaulo diff = rom->ht20_tx_pwr_diff[group]; 2950251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2951251538Srpaulo htpow += diff; /* HT40->HT20 correction. */ 2952251538Srpaulo } 2953251538Srpaulo for (ridx = 12; ridx <= 27; ridx++) { 2954251538Srpaulo power[ridx] += htpow; 2955251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2956251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2957251538Srpaulo } 2958251538Srpaulo#ifdef URTWN_DEBUG 2959251538Srpaulo if (urtwn_debug >= 4) { 2960251538Srpaulo /* Dump per-rate Tx power values. */ 2961251538Srpaulo printf("Tx power for chain %d:\n", chain); 2962289758Savos for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 2963251538Srpaulo printf("Rate %d = %u\n", ridx, power[ridx]); 2964251538Srpaulo } 2965251538Srpaulo#endif 2966251538Srpaulo} 2967251538Srpaulo 2968289066Skevlostatic void 2969264912Skevlourtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 2970264912Skevlo struct ieee80211_channel *c, struct ieee80211_channel *extc, 2971264912Skevlo uint16_t power[URTWN_RIDX_COUNT]) 2972264912Skevlo{ 2973287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 2974264912Skevlo uint16_t cckpow, ofdmpow, bw20pow, htpow; 2975264912Skevlo const struct urtwn_r88e_txpwr *base; 2976264912Skevlo int ridx, chan, group; 2977264912Skevlo 2978264912Skevlo /* Determine channel group. */ 2979264912Skevlo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2980264912Skevlo if (chan <= 2) 2981264912Skevlo group = 0; 2982264912Skevlo else if (chan <= 5) 2983264912Skevlo group = 1; 2984264912Skevlo else if (chan <= 8) 2985264912Skevlo group = 2; 2986264912Skevlo else if (chan <= 11) 2987264912Skevlo group = 3; 2988264912Skevlo else if (chan <= 13) 2989264912Skevlo group = 4; 2990264912Skevlo else 2991264912Skevlo group = 5; 2992264912Skevlo 2993264912Skevlo /* Get original Tx power based on board type and RF chain. */ 2994264912Skevlo base = &rtl8188eu_txagc[chain]; 2995264912Skevlo 2996264912Skevlo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2997264912Skevlo if (sc->regulatory == 0) { 2998289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 2999264912Skevlo power[ridx] = base->pwr[0][ridx]; 3000264912Skevlo } 3001289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3002264912Skevlo if (sc->regulatory == 3) 3003264912Skevlo power[ridx] = base->pwr[0][ridx]; 3004264912Skevlo else if (sc->regulatory == 1) { 3005264912Skevlo if (extc == NULL) 3006264912Skevlo power[ridx] = base->pwr[group][ridx]; 3007264912Skevlo } else if (sc->regulatory != 2) 3008264912Skevlo power[ridx] = base->pwr[0][ridx]; 3009264912Skevlo } 3010264912Skevlo 3011264912Skevlo /* Compute per-CCK rate Tx power. */ 3012264912Skevlo cckpow = sc->cck_tx_pwr[group]; 3013289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3014264912Skevlo power[ridx] += cckpow; 3015264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3016264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3017264912Skevlo } 3018264912Skevlo 3019264912Skevlo htpow = sc->ht40_tx_pwr[group]; 3020264912Skevlo 3021264912Skevlo /* Compute per-OFDM rate Tx power. */ 3022264912Skevlo ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3023289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3024264912Skevlo power[ridx] += ofdmpow; 3025264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3026264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3027264912Skevlo } 3028264912Skevlo 3029264912Skevlo bw20pow = htpow + sc->bw20_tx_pwr_diff; 3030264912Skevlo for (ridx = 12; ridx <= 27; ridx++) { 3031264912Skevlo power[ridx] += bw20pow; 3032264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3033264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3034264912Skevlo } 3035264912Skevlo} 3036264912Skevlo 3037289066Skevlostatic void 3038251538Srpaulourtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3039251538Srpaulo struct ieee80211_channel *extc) 3040251538Srpaulo{ 3041251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]; 3042251538Srpaulo int i; 3043251538Srpaulo 3044251538Srpaulo for (i = 0; i < sc->ntxchains; i++) { 3045251538Srpaulo /* Compute per-rate Tx power values. */ 3046264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3047264912Skevlo urtwn_r88e_get_txpower(sc, i, c, extc, power); 3048264912Skevlo else 3049264912Skevlo urtwn_get_txpower(sc, i, c, extc, power); 3050251538Srpaulo /* Write per-rate Tx power values to hardware. */ 3051251538Srpaulo urtwn_write_txpower(sc, i, power); 3052251538Srpaulo } 3053251538Srpaulo} 3054251538Srpaulo 3055251538Srpaulostatic void 3056290048Savosurtwn_set_rx_bssid_all(struct urtwn_softc *sc, int enable) 3057290048Savos{ 3058290048Savos uint32_t reg; 3059290048Savos 3060290048Savos reg = urtwn_read_4(sc, R92C_RCR); 3061290048Savos if (enable) 3062290048Savos reg &= ~R92C_RCR_CBSSID_BCN; 3063290048Savos else 3064290048Savos reg |= R92C_RCR_CBSSID_BCN; 3065290048Savos urtwn_write_4(sc, R92C_RCR, reg); 3066290048Savos} 3067290048Savos 3068290048Savosstatic void 3069290048Savosurtwn_set_gain(struct urtwn_softc *sc, uint8_t gain) 3070290048Savos{ 3071290048Savos uint32_t reg; 3072290048Savos 3073290048Savos reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 3074290048Savos reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3075290048Savos urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 3076290048Savos 3077290048Savos if (!(sc->chip & URTWN_CHIP_88E)) { 3078290048Savos reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 3079290048Savos reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain); 3080290048Savos urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 3081290048Savos } 3082290048Savos} 3083290048Savos 3084290048Savosstatic void 3085251538Srpaulourtwn_scan_start(struct ieee80211com *ic) 3086251538Srpaulo{ 3087290048Savos struct urtwn_softc *sc = ic->ic_softc; 3088290048Savos 3089290048Savos URTWN_LOCK(sc); 3090290048Savos /* Receive beacons / probe responses from any BSSID. */ 3091290048Savos urtwn_set_rx_bssid_all(sc, 1); 3092290048Savos /* Set gain for scanning. */ 3093290048Savos urtwn_set_gain(sc, 0x20); 3094290048Savos URTWN_UNLOCK(sc); 3095251538Srpaulo} 3096251538Srpaulo 3097251538Srpaulostatic void 3098251538Srpaulourtwn_scan_end(struct ieee80211com *ic) 3099251538Srpaulo{ 3100290048Savos struct urtwn_softc *sc = ic->ic_softc; 3101290048Savos 3102290048Savos URTWN_LOCK(sc); 3103290048Savos /* Restore limitations. */ 3104290048Savos urtwn_set_rx_bssid_all(sc, 0); 3105290048Savos /* Set gain under link. */ 3106290048Savos urtwn_set_gain(sc, 0x32); 3107290048Savos URTWN_UNLOCK(sc); 3108251538Srpaulo} 3109251538Srpaulo 3110251538Srpaulostatic void 3111251538Srpaulourtwn_set_channel(struct ieee80211com *ic) 3112251538Srpaulo{ 3113286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 3114281070Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3115251538Srpaulo 3116251538Srpaulo URTWN_LOCK(sc); 3117281070Srpaulo if (vap->iv_state == IEEE80211_S_SCAN) { 3118281070Srpaulo /* Make link LED blink during scan. */ 3119281070Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3120281070Srpaulo } 3121251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 3122251538Srpaulo URTWN_UNLOCK(sc); 3123251538Srpaulo} 3124251538Srpaulo 3125251538Srpaulostatic void 3126283540Sglebiusurtwn_update_mcast(struct ieee80211com *ic) 3127251538Srpaulo{ 3128251538Srpaulo /* XXX do nothing? */ 3129251538Srpaulo} 3130251538Srpaulo 3131251538Srpaulostatic void 3132251538Srpaulourtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3133251538Srpaulo struct ieee80211_channel *extc) 3134251538Srpaulo{ 3135287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3136251538Srpaulo uint32_t reg; 3137251538Srpaulo u_int chan; 3138251538Srpaulo int i; 3139251538Srpaulo 3140251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3141251538Srpaulo if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3142251538Srpaulo device_printf(sc->sc_dev, 3143251538Srpaulo "%s: invalid channel %x\n", __func__, chan); 3144251538Srpaulo return; 3145251538Srpaulo } 3146251538Srpaulo 3147251538Srpaulo /* Set Tx power for this new channel. */ 3148251538Srpaulo urtwn_set_txpower(sc, c, extc); 3149251538Srpaulo 3150251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3151251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3152251538Srpaulo RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3153251538Srpaulo } 3154251538Srpaulo#ifndef IEEE80211_NO_HT 3155251538Srpaulo if (extc != NULL) { 3156251538Srpaulo /* Is secondary channel below or above primary? */ 3157251538Srpaulo int prichlo = c->ic_freq < extc->ic_freq; 3158251538Srpaulo 3159251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3160251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3161251538Srpaulo 3162251538Srpaulo reg = urtwn_read_1(sc, R92C_RRSR + 2); 3163251538Srpaulo reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3164251538Srpaulo urtwn_write_1(sc, R92C_RRSR + 2, reg); 3165251538Srpaulo 3166251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3167251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3168251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3169251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3170251538Srpaulo 3171251538Srpaulo /* Set CCK side band. */ 3172251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3173251538Srpaulo reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3174251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3175251538Srpaulo 3176251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3177251538Srpaulo reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3178251538Srpaulo urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3179251538Srpaulo 3180251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3181251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3182251538Srpaulo ~R92C_FPGA0_ANAPARAM2_CBW20); 3183251538Srpaulo 3184251538Srpaulo reg = urtwn_bb_read(sc, 0x818); 3185251538Srpaulo reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3186251538Srpaulo urtwn_bb_write(sc, 0x818, reg); 3187251538Srpaulo 3188251538Srpaulo /* Select 40MHz bandwidth. */ 3189251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3190251538Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan); 3191251538Srpaulo } else 3192251538Srpaulo#endif 3193251538Srpaulo { 3194251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3195251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3196251538Srpaulo 3197251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3198251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3199251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3200251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3201251538Srpaulo 3202264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3203264912Skevlo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3204264912Skevlo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3205264912Skevlo R92C_FPGA0_ANAPARAM2_CBW20); 3206264912Skevlo } 3207281069Srpaulo 3208251538Srpaulo /* Select 20MHz bandwidth. */ 3209251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3210281069Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan | 3211264912Skevlo ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3212264912Skevlo R92C_RF_CHNLBW_BW20)); 3213251538Srpaulo } 3214251538Srpaulo} 3215251538Srpaulo 3216251538Srpaulostatic void 3217251538Srpaulourtwn_iq_calib(struct urtwn_softc *sc) 3218251538Srpaulo{ 3219251538Srpaulo /* TODO */ 3220251538Srpaulo} 3221251538Srpaulo 3222251538Srpaulostatic void 3223251538Srpaulourtwn_lc_calib(struct urtwn_softc *sc) 3224251538Srpaulo{ 3225251538Srpaulo uint32_t rf_ac[2]; 3226251538Srpaulo uint8_t txmode; 3227251538Srpaulo int i; 3228251538Srpaulo 3229251538Srpaulo txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3230251538Srpaulo if ((txmode & 0x70) != 0) { 3231251538Srpaulo /* Disable all continuous Tx. */ 3232251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3233251538Srpaulo 3234251538Srpaulo /* Set RF mode to standby mode. */ 3235251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3236251538Srpaulo rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3237251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, 3238251538Srpaulo RW(rf_ac[i], R92C_RF_AC_MODE, 3239251538Srpaulo R92C_RF_AC_MODE_STANDBY)); 3240251538Srpaulo } 3241251538Srpaulo } else { 3242251538Srpaulo /* Block all Tx queues. */ 3243251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3244251538Srpaulo } 3245251538Srpaulo /* Start calibration. */ 3246251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3247251538Srpaulo urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3248251538Srpaulo 3249251538Srpaulo /* Give calibration the time to complete. */ 3250266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3251251538Srpaulo 3252251538Srpaulo /* Restore configuration. */ 3253251538Srpaulo if ((txmode & 0x70) != 0) { 3254251538Srpaulo /* Restore Tx mode. */ 3255251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3256251538Srpaulo /* Restore RF mode. */ 3257251538Srpaulo for (i = 0; i < sc->nrxchains; i++) 3258251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3259251538Srpaulo } else { 3260251538Srpaulo /* Unblock all Tx queues. */ 3261251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3262251538Srpaulo } 3263251538Srpaulo} 3264251538Srpaulo 3265251538Srpaulostatic void 3266287197Sglebiusurtwn_init(struct urtwn_softc *sc) 3267251538Srpaulo{ 3268287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3269287197Sglebius struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3270287197Sglebius uint8_t macaddr[IEEE80211_ADDR_LEN]; 3271251538Srpaulo uint32_t reg; 3272251538Srpaulo int error; 3273251538Srpaulo 3274264864Skevlo URTWN_ASSERT_LOCKED(sc); 3275264864Skevlo 3276287197Sglebius if (sc->sc_flags & URTWN_RUNNING) 3277287197Sglebius urtwn_stop(sc); 3278251538Srpaulo 3279251538Srpaulo /* Init firmware commands ring. */ 3280251538Srpaulo sc->fwcur = 0; 3281251538Srpaulo 3282251538Srpaulo /* Allocate Tx/Rx buffers. */ 3283251538Srpaulo error = urtwn_alloc_rx_list(sc); 3284251538Srpaulo if (error != 0) 3285251538Srpaulo goto fail; 3286281069Srpaulo 3287251538Srpaulo error = urtwn_alloc_tx_list(sc); 3288251538Srpaulo if (error != 0) 3289251538Srpaulo goto fail; 3290251538Srpaulo 3291251538Srpaulo /* Power on adapter. */ 3292251538Srpaulo error = urtwn_power_on(sc); 3293251538Srpaulo if (error != 0) 3294251538Srpaulo goto fail; 3295251538Srpaulo 3296251538Srpaulo /* Initialize DMA. */ 3297251538Srpaulo error = urtwn_dma_init(sc); 3298251538Srpaulo if (error != 0) 3299251538Srpaulo goto fail; 3300251538Srpaulo 3301251538Srpaulo /* Set info size in Rx descriptors (in 64-bit words). */ 3302251538Srpaulo urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3303251538Srpaulo 3304251538Srpaulo /* Init interrupts. */ 3305264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3306264912Skevlo urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3307264912Skevlo urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3308264912Skevlo R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3309264912Skevlo urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3310264912Skevlo R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3311264912Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3312264912Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3313264912Skevlo R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3314264912Skevlo } else { 3315264912Skevlo urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3316264912Skevlo urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3317264912Skevlo } 3318251538Srpaulo 3319251538Srpaulo /* Set MAC address. */ 3320287197Sglebius IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3321287197Sglebius urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3322251538Srpaulo 3323251538Srpaulo /* Set initial network type. */ 3324289811Savos urtwn_set_mode(sc, R92C_MSR_INFRA); 3325251538Srpaulo 3326251538Srpaulo urtwn_rxfilter_init(sc); 3327251538Srpaulo 3328282623Skevlo /* Set response rate. */ 3329251538Srpaulo reg = urtwn_read_4(sc, R92C_RRSR); 3330251538Srpaulo reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3331251538Srpaulo urtwn_write_4(sc, R92C_RRSR, reg); 3332251538Srpaulo 3333251538Srpaulo /* Set short/long retry limits. */ 3334251538Srpaulo urtwn_write_2(sc, R92C_RL, 3335251538Srpaulo SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3336251538Srpaulo 3337251538Srpaulo /* Initialize EDCA parameters. */ 3338251538Srpaulo urtwn_edca_init(sc); 3339251538Srpaulo 3340251538Srpaulo /* Setup rate fallback. */ 3341264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3342264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3343264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3344264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3345264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3346264912Skevlo } 3347251538Srpaulo 3348251538Srpaulo urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3349251538Srpaulo urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3350251538Srpaulo R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3351251538Srpaulo /* Set ACK timeout. */ 3352251538Srpaulo urtwn_write_1(sc, R92C_ACKTO, 0x40); 3353251538Srpaulo 3354251538Srpaulo /* Setup USB aggregation. */ 3355251538Srpaulo reg = urtwn_read_4(sc, R92C_TDECTRL); 3356251538Srpaulo reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3357251538Srpaulo urtwn_write_4(sc, R92C_TDECTRL, reg); 3358251538Srpaulo urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3359251538Srpaulo urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3360251538Srpaulo R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3361251538Srpaulo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3362264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3363264912Skevlo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3364282266Skevlo else { 3365264912Skevlo urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3366282266Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3367282266Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3368282266Skevlo R92C_USB_SPECIAL_OPTION_AGG_EN); 3369282266Skevlo urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3370282266Skevlo urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3371282266Skevlo } 3372251538Srpaulo 3373251538Srpaulo /* Initialize beacon parameters. */ 3374264912Skevlo urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3375251538Srpaulo urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3376251538Srpaulo urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3377251538Srpaulo urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3378251538Srpaulo urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3379251538Srpaulo 3380264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3381264912Skevlo /* Setup AMPDU aggregation. */ 3382264912Skevlo urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3383264912Skevlo urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3384264912Skevlo urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3385251538Srpaulo 3386264912Skevlo urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3387264912Skevlo } 3388251538Srpaulo 3389251538Srpaulo /* Load 8051 microcode. */ 3390251538Srpaulo error = urtwn_load_firmware(sc); 3391251538Srpaulo if (error != 0) 3392251538Srpaulo goto fail; 3393251538Srpaulo 3394251538Srpaulo /* Initialize MAC/BB/RF blocks. */ 3395251538Srpaulo urtwn_mac_init(sc); 3396251538Srpaulo urtwn_bb_init(sc); 3397251538Srpaulo urtwn_rf_init(sc); 3398251538Srpaulo 3399264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3400264912Skevlo urtwn_write_2(sc, R92C_CR, 3401264912Skevlo urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3402264912Skevlo R92C_CR_MACRXEN); 3403264912Skevlo } 3404264912Skevlo 3405251538Srpaulo /* Turn CCK and OFDM blocks on. */ 3406251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3407251538Srpaulo reg |= R92C_RFMOD_CCK_EN; 3408251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3409251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3410251538Srpaulo reg |= R92C_RFMOD_OFDM_EN; 3411251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3412251538Srpaulo 3413251538Srpaulo /* Clear per-station keys table. */ 3414251538Srpaulo urtwn_cam_init(sc); 3415251538Srpaulo 3416251538Srpaulo /* Enable hardware sequence numbering. */ 3417251538Srpaulo urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3418251538Srpaulo 3419251538Srpaulo /* Perform LO and IQ calibrations. */ 3420251538Srpaulo urtwn_iq_calib(sc); 3421251538Srpaulo /* Perform LC calibration. */ 3422251538Srpaulo urtwn_lc_calib(sc); 3423251538Srpaulo 3424251538Srpaulo /* Fix USB interference issue. */ 3425264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3426264912Skevlo urtwn_write_1(sc, 0xfe40, 0xe0); 3427264912Skevlo urtwn_write_1(sc, 0xfe41, 0x8d); 3428264912Skevlo urtwn_write_1(sc, 0xfe42, 0x80); 3429251538Srpaulo 3430264912Skevlo urtwn_pa_bias_init(sc); 3431264912Skevlo } 3432251538Srpaulo 3433251538Srpaulo /* Initialize GPIO setting. */ 3434251538Srpaulo urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3435251538Srpaulo urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3436251538Srpaulo 3437251538Srpaulo /* Fix for lower temperature. */ 3438264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 3439264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 3440251538Srpaulo 3441251538Srpaulo usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3442251538Srpaulo 3443287197Sglebius sc->sc_flags |= URTWN_RUNNING; 3444251538Srpaulo 3445251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3446251538Srpaulofail: 3447251538Srpaulo return; 3448251538Srpaulo} 3449251538Srpaulo 3450251538Srpaulostatic void 3451287197Sglebiusurtwn_stop(struct urtwn_softc *sc) 3452251538Srpaulo{ 3453251538Srpaulo 3454264864Skevlo URTWN_ASSERT_LOCKED(sc); 3455287197Sglebius sc->sc_flags &= ~URTWN_RUNNING; 3456251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 3457251538Srpaulo urtwn_abort_xfers(sc); 3458288353Sadrian 3459288353Sadrian urtwn_drain_mbufq(sc); 3460251538Srpaulo} 3461251538Srpaulo 3462251538Srpaulostatic void 3463251538Srpaulourtwn_abort_xfers(struct urtwn_softc *sc) 3464251538Srpaulo{ 3465251538Srpaulo int i; 3466251538Srpaulo 3467251538Srpaulo URTWN_ASSERT_LOCKED(sc); 3468251538Srpaulo 3469251538Srpaulo /* abort any pending transfers */ 3470251538Srpaulo for (i = 0; i < URTWN_N_TRANSFER; i++) 3471251538Srpaulo usbd_transfer_stop(sc->sc_xfer[i]); 3472251538Srpaulo} 3473251538Srpaulo 3474251538Srpaulostatic int 3475251538Srpaulourtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3476251538Srpaulo const struct ieee80211_bpf_params *params) 3477251538Srpaulo{ 3478251538Srpaulo struct ieee80211com *ic = ni->ni_ic; 3479286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 3480251538Srpaulo struct urtwn_data *bf; 3481251538Srpaulo 3482251538Srpaulo /* prevent management frames from being sent if we're not ready */ 3483287197Sglebius if (!(sc->sc_flags & URTWN_RUNNING)) { 3484251538Srpaulo m_freem(m); 3485251538Srpaulo return (ENETDOWN); 3486251538Srpaulo } 3487251538Srpaulo URTWN_LOCK(sc); 3488251538Srpaulo bf = urtwn_getbuf(sc); 3489251538Srpaulo if (bf == NULL) { 3490251538Srpaulo m_freem(m); 3491251538Srpaulo URTWN_UNLOCK(sc); 3492251538Srpaulo return (ENOBUFS); 3493251538Srpaulo } 3494251538Srpaulo 3495251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3496288353Sadrian m_freem(m); 3497251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3498251538Srpaulo URTWN_UNLOCK(sc); 3499251538Srpaulo return (EIO); 3500251538Srpaulo } 3501288353Sadrian sc->sc_txtimer = 5; 3502251538Srpaulo URTWN_UNLOCK(sc); 3503251538Srpaulo 3504251538Srpaulo return (0); 3505251538Srpaulo} 3506251538Srpaulo 3507266472Shselaskystatic void 3508266472Shselaskyurtwn_ms_delay(struct urtwn_softc *sc) 3509266472Shselasky{ 3510266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3511266472Shselasky} 3512266472Shselasky 3513251538Srpaulostatic device_method_t urtwn_methods[] = { 3514251538Srpaulo /* Device interface */ 3515251538Srpaulo DEVMETHOD(device_probe, urtwn_match), 3516251538Srpaulo DEVMETHOD(device_attach, urtwn_attach), 3517251538Srpaulo DEVMETHOD(device_detach, urtwn_detach), 3518251538Srpaulo 3519264912Skevlo DEVMETHOD_END 3520251538Srpaulo}; 3521251538Srpaulo 3522251538Srpaulostatic driver_t urtwn_driver = { 3523251538Srpaulo "urtwn", 3524251538Srpaulo urtwn_methods, 3525251538Srpaulo sizeof(struct urtwn_softc) 3526251538Srpaulo}; 3527251538Srpaulo 3528251538Srpaulostatic devclass_t urtwn_devclass; 3529251538Srpaulo 3530251538SrpauloDRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3531251538SrpauloMODULE_DEPEND(urtwn, usb, 1, 1, 1); 3532251538SrpauloMODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3533251538SrpauloMODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3534251538SrpauloMODULE_VERSION(urtwn, 1); 3535