if_urtwn.c revision 289799
1251538Srpaulo/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2251538Srpaulo 3251538Srpaulo/*- 4251538Srpaulo * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5264912Skevlo * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6251538Srpaulo * 7251538Srpaulo * Permission to use, copy, modify, and distribute this software for any 8251538Srpaulo * purpose with or without fee is hereby granted, provided that the above 9251538Srpaulo * copyright notice and this permission notice appear in all copies. 10251538Srpaulo * 11251538Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12251538Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13251538Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14251538Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15251538Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16251538Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17251538Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18251538Srpaulo */ 19251538Srpaulo 20251538Srpaulo#include <sys/cdefs.h> 21251538Srpaulo__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 289799 2015-10-23 07:42:56Z avos $"); 22251538Srpaulo 23251538Srpaulo/* 24264912Skevlo * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25251538Srpaulo */ 26251538Srpaulo 27288353Sadrian#include "opt_wlan.h" 28288353Sadrian 29251538Srpaulo#include <sys/param.h> 30251538Srpaulo#include <sys/sockio.h> 31251538Srpaulo#include <sys/sysctl.h> 32251538Srpaulo#include <sys/lock.h> 33251538Srpaulo#include <sys/mutex.h> 34251538Srpaulo#include <sys/mbuf.h> 35251538Srpaulo#include <sys/kernel.h> 36251538Srpaulo#include <sys/socket.h> 37251538Srpaulo#include <sys/systm.h> 38251538Srpaulo#include <sys/malloc.h> 39251538Srpaulo#include <sys/module.h> 40251538Srpaulo#include <sys/bus.h> 41251538Srpaulo#include <sys/endian.h> 42251538Srpaulo#include <sys/linker.h> 43251538Srpaulo#include <sys/firmware.h> 44251538Srpaulo#include <sys/kdb.h> 45251538Srpaulo 46251538Srpaulo#include <machine/bus.h> 47251538Srpaulo#include <machine/resource.h> 48251538Srpaulo#include <sys/rman.h> 49251538Srpaulo 50251538Srpaulo#include <net/bpf.h> 51251538Srpaulo#include <net/if.h> 52257176Sglebius#include <net/if_var.h> 53251538Srpaulo#include <net/if_arp.h> 54251538Srpaulo#include <net/ethernet.h> 55251538Srpaulo#include <net/if_dl.h> 56251538Srpaulo#include <net/if_media.h> 57251538Srpaulo#include <net/if_types.h> 58251538Srpaulo 59251538Srpaulo#include <netinet/in.h> 60251538Srpaulo#include <netinet/in_systm.h> 61251538Srpaulo#include <netinet/in_var.h> 62251538Srpaulo#include <netinet/if_ether.h> 63251538Srpaulo#include <netinet/ip.h> 64251538Srpaulo 65251538Srpaulo#include <net80211/ieee80211_var.h> 66288088Sadrian#include <net80211/ieee80211_input.h> 67251538Srpaulo#include <net80211/ieee80211_regdomain.h> 68251538Srpaulo#include <net80211/ieee80211_radiotap.h> 69251538Srpaulo#include <net80211/ieee80211_ratectl.h> 70251538Srpaulo 71251538Srpaulo#include <dev/usb/usb.h> 72251538Srpaulo#include <dev/usb/usbdi.h> 73251538Srpaulo#include "usbdevs.h" 74251538Srpaulo 75251538Srpaulo#define USB_DEBUG_VAR urtwn_debug 76251538Srpaulo#include <dev/usb/usb_debug.h> 77251538Srpaulo 78251538Srpaulo#include <dev/usb/wlan/if_urtwnreg.h> 79289167Sadrian#include <dev/usb/wlan/if_urtwnvar.h> 80251538Srpaulo 81251538Srpaulo#ifdef USB_DEBUG 82251538Srpaulostatic int urtwn_debug = 0; 83251538Srpaulo 84251538SrpauloSYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 85276701ShselaskySYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 86251538Srpaulo "Debug level"); 87251538Srpaulo#endif 88251538Srpaulo 89288088Sadrian#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 90251538Srpaulo 91251538Srpaulo/* various supported device vendors/products */ 92251596Srpaulostatic const STRUCT_USB_HOST_ID urtwn_devs[] = { 93251538Srpaulo#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 94264912Skevlo#define URTWN_RTL8188E_DEV(v,p) \ 95264912Skevlo { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 96264912Skevlo#define URTWN_RTL8188E 1 97251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_1), 98251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_2), 99251538Srpaulo URTWN_DEV(ABOCOM, RTL8192CU), 100251538Srpaulo URTWN_DEV(ASUS, RTL8192CU), 101266721Skevlo URTWN_DEV(ASUS, USBN10NANO), 102251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_1), 103251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_2), 104251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CU), 105251538Srpaulo URTWN_DEV(BELKIN, F7D2102), 106251538Srpaulo URTWN_DEV(BELKIN, RTL8188CU), 107251538Srpaulo URTWN_DEV(BELKIN, RTL8192CU), 108251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_1), 109251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_2), 110251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_3), 111251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_4), 112251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_5), 113251538Srpaulo URTWN_DEV(COREGA, RTL8192CU), 114251538Srpaulo URTWN_DEV(DLINK, RTL8188CU), 115251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_1), 116251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_2), 117251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_3), 118252196Skevlo URTWN_DEV(DLINK, DWA131B), 119251538Srpaulo URTWN_DEV(EDIMAX, EW7811UN), 120251538Srpaulo URTWN_DEV(EDIMAX, RTL8192CU), 121251538Srpaulo URTWN_DEV(FEIXUN, RTL8188CU), 122251538Srpaulo URTWN_DEV(FEIXUN, RTL8192CU), 123251538Srpaulo URTWN_DEV(GUILLEMOT, HWNUP150), 124251538Srpaulo URTWN_DEV(HAWKING, RTL8192CU), 125251538Srpaulo URTWN_DEV(HP3, RTL8188CU), 126251538Srpaulo URTWN_DEV(NETGEAR, WNA1000M), 127251538Srpaulo URTWN_DEV(NETGEAR, RTL8192CU), 128251538Srpaulo URTWN_DEV(NETGEAR4, RTL8188CU), 129251538Srpaulo URTWN_DEV(NOVATECH, RTL8188CU), 130251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_1), 131251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_2), 132251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_3), 133251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_4), 134251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CUS), 135251538Srpaulo URTWN_DEV(PLANEX2, RTL8192CU), 136251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_0), 137251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_1), 138251538Srpaulo URTWN_DEV(REALTEK, RTL8188CTV), 139251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_0), 140251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_1), 141251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_2), 142282119Skevlo URTWN_DEV(REALTEK, RTL8188CU_3), 143251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_COMBO), 144251538Srpaulo URTWN_DEV(REALTEK, RTL8188CUS), 145251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_1), 146251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_2), 147272410Shselasky URTWN_DEV(REALTEK, RTL8188RU_3), 148251538Srpaulo URTWN_DEV(REALTEK, RTL8191CU), 149251538Srpaulo URTWN_DEV(REALTEK, RTL8192CE), 150251538Srpaulo URTWN_DEV(REALTEK, RTL8192CU), 151251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_1), 152251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_2), 153251538Srpaulo URTWN_DEV(SITECOMEU, RTL8192CU), 154251538Srpaulo URTWN_DEV(TRENDNET, RTL8188CU), 155251538Srpaulo URTWN_DEV(TRENDNET, RTL8192CU), 156251538Srpaulo URTWN_DEV(ZYXEL, RTL8192CU), 157264912Skevlo /* URTWN_RTL8188E */ 158273589Skevlo URTWN_RTL8188E_DEV(DLINK, DWA123D1), 159270191Skevlo URTWN_RTL8188E_DEV(DLINK, DWA125D1), 160273589Skevlo URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 161264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 162264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 163264912Skevlo#undef URTWN_RTL8188E_DEV 164251538Srpaulo#undef URTWN_DEV 165251538Srpaulo}; 166251538Srpaulo 167251538Srpaulostatic device_probe_t urtwn_match; 168251538Srpaulostatic device_attach_t urtwn_attach; 169251538Srpaulostatic device_detach_t urtwn_detach; 170251538Srpaulo 171251538Srpaulostatic usb_callback_t urtwn_bulk_tx_callback; 172251538Srpaulostatic usb_callback_t urtwn_bulk_rx_callback; 173251538Srpaulo 174288353Sadrianstatic void urtwn_drain_mbufq(struct urtwn_softc *sc); 175287197Sglebiusstatic usb_error_t urtwn_do_request(struct urtwn_softc *, 176287197Sglebius struct usb_device_request *, void *); 177251538Srpaulostatic struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 178251538Srpaulo const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 179251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN], 180251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN]); 181251538Srpaulostatic void urtwn_vap_delete(struct ieee80211vap *); 182281069Srpaulostatic struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 183251538Srpaulo int *); 184281069Srpaulostatic struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 185251538Srpaulo int *, int8_t *); 186251538Srpaulostatic void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 187281069Srpaulostatic int urtwn_alloc_list(struct urtwn_softc *, 188251538Srpaulo struct urtwn_data[], int, int); 189251538Srpaulostatic int urtwn_alloc_rx_list(struct urtwn_softc *); 190251538Srpaulostatic int urtwn_alloc_tx_list(struct urtwn_softc *); 191251538Srpaulostatic void urtwn_free_list(struct urtwn_softc *, 192251538Srpaulo struct urtwn_data data[], int); 193289066Skevlostatic void urtwn_free_rx_list(struct urtwn_softc *); 194289066Skevlostatic void urtwn_free_tx_list(struct urtwn_softc *); 195251538Srpaulostatic struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 196251538Srpaulostatic struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 197281069Srpaulostatic int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 198251538Srpaulo uint8_t *, int); 199251538Srpaulostatic void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 200251538Srpaulostatic void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 201251538Srpaulostatic void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 202281069Srpaulostatic int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 203251538Srpaulo uint8_t *, int); 204251538Srpaulostatic uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 205251538Srpaulostatic uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 206251538Srpaulostatic uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 207281069Srpaulostatic int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 208251538Srpaulo const void *, int); 209264912Skevlostatic void urtwn_r92c_rf_write(struct urtwn_softc *, int, 210264912Skevlo uint8_t, uint32_t); 211281069Srpaulostatic void urtwn_r88e_rf_write(struct urtwn_softc *, int, 212264912Skevlo uint8_t, uint32_t); 213251538Srpaulostatic uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 214281069Srpaulostatic int urtwn_llt_write(struct urtwn_softc *, uint32_t, 215251538Srpaulo uint32_t); 216251538Srpaulostatic uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 217251538Srpaulostatic void urtwn_efuse_read(struct urtwn_softc *); 218264912Skevlostatic void urtwn_efuse_switch_power(struct urtwn_softc *); 219251538Srpaulostatic int urtwn_read_chipid(struct urtwn_softc *); 220251538Srpaulostatic void urtwn_read_rom(struct urtwn_softc *); 221264912Skevlostatic void urtwn_r88e_read_rom(struct urtwn_softc *); 222251538Srpaulostatic int urtwn_ra_init(struct urtwn_softc *); 223251538Srpaulostatic void urtwn_tsf_sync_enable(struct urtwn_softc *); 224251538Srpaulostatic void urtwn_set_led(struct urtwn_softc *, int, int); 225281069Srpaulostatic int urtwn_newstate(struct ieee80211vap *, 226251538Srpaulo enum ieee80211_state, int); 227251538Srpaulostatic void urtwn_watchdog(void *); 228251538Srpaulostatic void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 229251538Srpaulostatic int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 230264912Skevlostatic int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 231251538Srpaulostatic int urtwn_tx_start(struct urtwn_softc *, 232251538Srpaulo struct ieee80211_node *, struct mbuf *, 233251538Srpaulo struct urtwn_data *); 234287197Sglebiusstatic int urtwn_transmit(struct ieee80211com *, struct mbuf *); 235287197Sglebiusstatic void urtwn_start(struct urtwn_softc *); 236287197Sglebiusstatic void urtwn_parent(struct ieee80211com *); 237264912Skevlostatic int urtwn_r92c_power_on(struct urtwn_softc *); 238264912Skevlostatic int urtwn_r88e_power_on(struct urtwn_softc *); 239251538Srpaulostatic int urtwn_llt_init(struct urtwn_softc *); 240251538Srpaulostatic void urtwn_fw_reset(struct urtwn_softc *); 241264912Skevlostatic void urtwn_r88e_fw_reset(struct urtwn_softc *); 242281069Srpaulostatic int urtwn_fw_loadpage(struct urtwn_softc *, int, 243251538Srpaulo const uint8_t *, int); 244251538Srpaulostatic int urtwn_load_firmware(struct urtwn_softc *); 245264912Skevlostatic int urtwn_r92c_dma_init(struct urtwn_softc *); 246264912Skevlostatic int urtwn_r88e_dma_init(struct urtwn_softc *); 247251538Srpaulostatic void urtwn_mac_init(struct urtwn_softc *); 248251538Srpaulostatic void urtwn_bb_init(struct urtwn_softc *); 249251538Srpaulostatic void urtwn_rf_init(struct urtwn_softc *); 250251538Srpaulostatic void urtwn_cam_init(struct urtwn_softc *); 251251538Srpaulostatic void urtwn_pa_bias_init(struct urtwn_softc *); 252251538Srpaulostatic void urtwn_rxfilter_init(struct urtwn_softc *); 253251538Srpaulostatic void urtwn_edca_init(struct urtwn_softc *); 254281069Srpaulostatic void urtwn_write_txpower(struct urtwn_softc *, int, 255251538Srpaulo uint16_t[]); 256251538Srpaulostatic void urtwn_get_txpower(struct urtwn_softc *, int, 257281069Srpaulo struct ieee80211_channel *, 258251538Srpaulo struct ieee80211_channel *, uint16_t[]); 259264912Skevlostatic void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 260281069Srpaulo struct ieee80211_channel *, 261264912Skevlo struct ieee80211_channel *, uint16_t[]); 262251538Srpaulostatic void urtwn_set_txpower(struct urtwn_softc *, 263281069Srpaulo struct ieee80211_channel *, 264251538Srpaulo struct ieee80211_channel *); 265251538Srpaulostatic void urtwn_scan_start(struct ieee80211com *); 266251538Srpaulostatic void urtwn_scan_end(struct ieee80211com *); 267251538Srpaulostatic void urtwn_set_channel(struct ieee80211com *); 268289066Skevlostatic void urtwn_update_mcast(struct ieee80211com *); 269251538Srpaulostatic void urtwn_set_chan(struct urtwn_softc *, 270281069Srpaulo struct ieee80211_channel *, 271251538Srpaulo struct ieee80211_channel *); 272251538Srpaulostatic void urtwn_iq_calib(struct urtwn_softc *); 273251538Srpaulostatic void urtwn_lc_calib(struct urtwn_softc *); 274287197Sglebiusstatic void urtwn_init(struct urtwn_softc *); 275287197Sglebiusstatic void urtwn_stop(struct urtwn_softc *); 276251538Srpaulostatic void urtwn_abort_xfers(struct urtwn_softc *); 277251538Srpaulostatic int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 278251538Srpaulo const struct ieee80211_bpf_params *); 279266472Shselaskystatic void urtwn_ms_delay(struct urtwn_softc *); 280251538Srpaulo 281251538Srpaulo/* Aliases. */ 282251538Srpaulo#define urtwn_bb_write urtwn_write_4 283251538Srpaulo#define urtwn_bb_read urtwn_read_4 284251538Srpaulo 285251538Srpaulostatic const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 286251538Srpaulo [URTWN_BULK_RX] = { 287251538Srpaulo .type = UE_BULK, 288251538Srpaulo .endpoint = UE_ADDR_ANY, 289251538Srpaulo .direction = UE_DIR_IN, 290251538Srpaulo .bufsize = URTWN_RXBUFSZ, 291251538Srpaulo .flags = { 292251538Srpaulo .pipe_bof = 1, 293251538Srpaulo .short_xfer_ok = 1 294251538Srpaulo }, 295251538Srpaulo .callback = urtwn_bulk_rx_callback, 296251538Srpaulo }, 297251538Srpaulo [URTWN_BULK_TX_BE] = { 298251538Srpaulo .type = UE_BULK, 299251538Srpaulo .endpoint = 0x03, 300251538Srpaulo .direction = UE_DIR_OUT, 301251538Srpaulo .bufsize = URTWN_TXBUFSZ, 302251538Srpaulo .flags = { 303251538Srpaulo .ext_buffer = 1, 304251538Srpaulo .pipe_bof = 1, 305251538Srpaulo .force_short_xfer = 1 306251538Srpaulo }, 307251538Srpaulo .callback = urtwn_bulk_tx_callback, 308251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 309251538Srpaulo }, 310251538Srpaulo [URTWN_BULK_TX_BK] = { 311251538Srpaulo .type = UE_BULK, 312251538Srpaulo .endpoint = 0x03, 313251538Srpaulo .direction = UE_DIR_OUT, 314251538Srpaulo .bufsize = URTWN_TXBUFSZ, 315251538Srpaulo .flags = { 316251538Srpaulo .ext_buffer = 1, 317251538Srpaulo .pipe_bof = 1, 318251538Srpaulo .force_short_xfer = 1, 319251538Srpaulo }, 320251538Srpaulo .callback = urtwn_bulk_tx_callback, 321251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 322251538Srpaulo }, 323251538Srpaulo [URTWN_BULK_TX_VI] = { 324251538Srpaulo .type = UE_BULK, 325251538Srpaulo .endpoint = 0x02, 326251538Srpaulo .direction = UE_DIR_OUT, 327251538Srpaulo .bufsize = URTWN_TXBUFSZ, 328251538Srpaulo .flags = { 329251538Srpaulo .ext_buffer = 1, 330251538Srpaulo .pipe_bof = 1, 331251538Srpaulo .force_short_xfer = 1 332251538Srpaulo }, 333251538Srpaulo .callback = urtwn_bulk_tx_callback, 334251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 335251538Srpaulo }, 336251538Srpaulo [URTWN_BULK_TX_VO] = { 337251538Srpaulo .type = UE_BULK, 338251538Srpaulo .endpoint = 0x02, 339251538Srpaulo .direction = UE_DIR_OUT, 340251538Srpaulo .bufsize = URTWN_TXBUFSZ, 341251538Srpaulo .flags = { 342251538Srpaulo .ext_buffer = 1, 343251538Srpaulo .pipe_bof = 1, 344251538Srpaulo .force_short_xfer = 1 345251538Srpaulo }, 346251538Srpaulo .callback = urtwn_bulk_tx_callback, 347251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 348251538Srpaulo }, 349251538Srpaulo}; 350251538Srpaulo 351251538Srpaulostatic int 352251538Srpaulourtwn_match(device_t self) 353251538Srpaulo{ 354251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 355251538Srpaulo 356251538Srpaulo if (uaa->usb_mode != USB_MODE_HOST) 357251538Srpaulo return (ENXIO); 358251538Srpaulo if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 359251538Srpaulo return (ENXIO); 360251538Srpaulo if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 361251538Srpaulo return (ENXIO); 362251538Srpaulo 363251538Srpaulo return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 364251538Srpaulo} 365251538Srpaulo 366251538Srpaulostatic int 367251538Srpaulourtwn_attach(device_t self) 368251538Srpaulo{ 369251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 370251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 371287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 372251538Srpaulo uint8_t iface_index, bands; 373251538Srpaulo int error; 374251538Srpaulo 375251538Srpaulo device_set_usb_desc(self); 376251538Srpaulo sc->sc_udev = uaa->device; 377251538Srpaulo sc->sc_dev = self; 378264912Skevlo if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 379264912Skevlo sc->chip |= URTWN_CHIP_88E; 380251538Srpaulo 381251538Srpaulo mtx_init(&sc->sc_mtx, device_get_nameunit(self), 382251538Srpaulo MTX_NETWORK_LOCK, MTX_DEF); 383251538Srpaulo callout_init(&sc->sc_watchdog_ch, 0); 384287197Sglebius mbufq_init(&sc->sc_snd, ifqmaxlen); 385251538Srpaulo 386251538Srpaulo iface_index = URTWN_IFACE_INDEX; 387251538Srpaulo error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 388251538Srpaulo urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 389251538Srpaulo if (error) { 390251538Srpaulo device_printf(self, "could not allocate USB transfers, " 391251538Srpaulo "err=%s\n", usbd_errstr(error)); 392251538Srpaulo goto detach; 393251538Srpaulo } 394251538Srpaulo 395251538Srpaulo URTWN_LOCK(sc); 396251538Srpaulo 397251538Srpaulo error = urtwn_read_chipid(sc); 398251538Srpaulo if (error) { 399251538Srpaulo device_printf(sc->sc_dev, "unsupported test chip\n"); 400251538Srpaulo URTWN_UNLOCK(sc); 401251538Srpaulo goto detach; 402251538Srpaulo } 403251538Srpaulo 404251538Srpaulo /* Determine number of Tx/Rx chains. */ 405251538Srpaulo if (sc->chip & URTWN_CHIP_92C) { 406251538Srpaulo sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 407251538Srpaulo sc->nrxchains = 2; 408251538Srpaulo } else { 409251538Srpaulo sc->ntxchains = 1; 410251538Srpaulo sc->nrxchains = 1; 411251538Srpaulo } 412251538Srpaulo 413264912Skevlo if (sc->chip & URTWN_CHIP_88E) 414264912Skevlo urtwn_r88e_read_rom(sc); 415264912Skevlo else 416264912Skevlo urtwn_read_rom(sc); 417264912Skevlo 418251538Srpaulo device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 419251538Srpaulo (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 420264912Skevlo (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 421251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 422251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 423251538Srpaulo "8188CUS", sc->ntxchains, sc->nrxchains); 424251538Srpaulo 425251538Srpaulo URTWN_UNLOCK(sc); 426251538Srpaulo 427283537Sglebius ic->ic_softc = sc; 428283527Sglebius ic->ic_name = device_get_nameunit(self); 429251538Srpaulo ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 430251538Srpaulo ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 431251538Srpaulo 432251538Srpaulo /* set device capabilities */ 433251538Srpaulo ic->ic_caps = 434251538Srpaulo IEEE80211_C_STA /* station mode */ 435251538Srpaulo | IEEE80211_C_MONITOR /* monitor mode */ 436251538Srpaulo | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 437251538Srpaulo | IEEE80211_C_SHSLOT /* short slot time supported */ 438251538Srpaulo | IEEE80211_C_BGSCAN /* capable of bg scanning */ 439251538Srpaulo | IEEE80211_C_WPA /* 802.11i */ 440251538Srpaulo ; 441251538Srpaulo 442251538Srpaulo bands = 0; 443251538Srpaulo setbit(&bands, IEEE80211_MODE_11B); 444251538Srpaulo setbit(&bands, IEEE80211_MODE_11G); 445251538Srpaulo ieee80211_init_channels(ic, NULL, &bands); 446251538Srpaulo 447287197Sglebius ieee80211_ifattach(ic); 448251538Srpaulo ic->ic_raw_xmit = urtwn_raw_xmit; 449251538Srpaulo ic->ic_scan_start = urtwn_scan_start; 450251538Srpaulo ic->ic_scan_end = urtwn_scan_end; 451251538Srpaulo ic->ic_set_channel = urtwn_set_channel; 452287197Sglebius ic->ic_transmit = urtwn_transmit; 453287197Sglebius ic->ic_parent = urtwn_parent; 454251538Srpaulo ic->ic_vap_create = urtwn_vap_create; 455251538Srpaulo ic->ic_vap_delete = urtwn_vap_delete; 456251538Srpaulo ic->ic_update_mcast = urtwn_update_mcast; 457251538Srpaulo 458281069Srpaulo ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 459251538Srpaulo sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 460251538Srpaulo &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 461251538Srpaulo URTWN_RX_RADIOTAP_PRESENT); 462251538Srpaulo 463251538Srpaulo if (bootverbose) 464251538Srpaulo ieee80211_announce(ic); 465251538Srpaulo 466251538Srpaulo return (0); 467251538Srpaulo 468251538Srpaulodetach: 469251538Srpaulo urtwn_detach(self); 470251538Srpaulo return (ENXIO); /* failure */ 471251538Srpaulo} 472251538Srpaulo 473251538Srpaulostatic int 474251538Srpaulourtwn_detach(device_t self) 475251538Srpaulo{ 476251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 477287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 478263153Skevlo unsigned int x; 479281069Srpaulo 480263153Skevlo /* Prevent further ioctls. */ 481263153Skevlo URTWN_LOCK(sc); 482263153Skevlo sc->sc_flags |= URTWN_DETACHED; 483287197Sglebius urtwn_stop(sc); 484263153Skevlo URTWN_UNLOCK(sc); 485251538Srpaulo 486251538Srpaulo callout_drain(&sc->sc_watchdog_ch); 487251538Srpaulo 488288353Sadrian /* stop all USB transfers */ 489288353Sadrian usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 490288353Sadrian 491263153Skevlo /* Prevent further allocations from RX/TX data lists. */ 492263153Skevlo URTWN_LOCK(sc); 493263153Skevlo STAILQ_INIT(&sc->sc_tx_active); 494263153Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 495263153Skevlo STAILQ_INIT(&sc->sc_tx_pending); 496263153Skevlo 497263153Skevlo STAILQ_INIT(&sc->sc_rx_active); 498263153Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 499263153Skevlo URTWN_UNLOCK(sc); 500263153Skevlo 501263153Skevlo /* drain USB transfers */ 502263153Skevlo for (x = 0; x != URTWN_N_TRANSFER; x++) 503263153Skevlo usbd_transfer_drain(sc->sc_xfer[x]); 504263153Skevlo 505263153Skevlo /* Free data buffers. */ 506263153Skevlo URTWN_LOCK(sc); 507263153Skevlo urtwn_free_tx_list(sc); 508263153Skevlo urtwn_free_rx_list(sc); 509263153Skevlo URTWN_UNLOCK(sc); 510263153Skevlo 511251538Srpaulo ieee80211_ifdetach(ic); 512251538Srpaulo mtx_destroy(&sc->sc_mtx); 513251538Srpaulo 514251538Srpaulo return (0); 515251538Srpaulo} 516251538Srpaulo 517251538Srpaulostatic void 518289066Skevlourtwn_drain_mbufq(struct urtwn_softc *sc) 519251538Srpaulo{ 520289066Skevlo struct mbuf *m; 521289066Skevlo struct ieee80211_node *ni; 522289066Skevlo URTWN_ASSERT_LOCKED(sc); 523289066Skevlo while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 524289066Skevlo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 525289066Skevlo m->m_pkthdr.rcvif = NULL; 526289066Skevlo ieee80211_free_node(ni); 527289066Skevlo m_freem(m); 528251538Srpaulo } 529251538Srpaulo} 530251538Srpaulo 531251538Srpaulostatic usb_error_t 532251538Srpaulourtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 533251538Srpaulo void *data) 534251538Srpaulo{ 535251538Srpaulo usb_error_t err; 536251538Srpaulo int ntries = 10; 537251538Srpaulo 538251538Srpaulo URTWN_ASSERT_LOCKED(sc); 539251538Srpaulo 540251538Srpaulo while (ntries--) { 541251538Srpaulo err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 542251538Srpaulo req, data, 0, NULL, 250 /* ms */); 543251538Srpaulo if (err == 0) 544251538Srpaulo break; 545251538Srpaulo 546251538Srpaulo DPRINTFN(1, "Control request failed, %s (retrying)\n", 547251538Srpaulo usbd_errstr(err)); 548251538Srpaulo usb_pause_mtx(&sc->sc_mtx, hz / 100); 549251538Srpaulo } 550251538Srpaulo return (err); 551251538Srpaulo} 552251538Srpaulo 553251538Srpaulostatic struct ieee80211vap * 554251538Srpaulourtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 555251538Srpaulo enum ieee80211_opmode opmode, int flags, 556251538Srpaulo const uint8_t bssid[IEEE80211_ADDR_LEN], 557251538Srpaulo const uint8_t mac[IEEE80211_ADDR_LEN]) 558251538Srpaulo{ 559251538Srpaulo struct urtwn_vap *uvp; 560251538Srpaulo struct ieee80211vap *vap; 561251538Srpaulo 562251538Srpaulo if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 563251538Srpaulo return (NULL); 564251538Srpaulo 565287197Sglebius uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 566251538Srpaulo vap = &uvp->vap; 567251538Srpaulo /* enable s/w bmiss handling for sta mode */ 568251538Srpaulo 569281069Srpaulo if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 570287197Sglebius flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 571257743Shselasky /* out of memory */ 572257743Shselasky free(uvp, M_80211_VAP); 573257743Shselasky return (NULL); 574257743Shselasky } 575257743Shselasky 576251538Srpaulo /* override state transition machine */ 577251538Srpaulo uvp->newstate = vap->iv_newstate; 578251538Srpaulo vap->iv_newstate = urtwn_newstate; 579251538Srpaulo 580251538Srpaulo /* complete setup */ 581251538Srpaulo ieee80211_vap_attach(vap, ieee80211_media_change, 582287197Sglebius ieee80211_media_status, mac); 583251538Srpaulo ic->ic_opmode = opmode; 584251538Srpaulo return (vap); 585251538Srpaulo} 586251538Srpaulo 587251538Srpaulostatic void 588251538Srpaulourtwn_vap_delete(struct ieee80211vap *vap) 589251538Srpaulo{ 590251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 591251538Srpaulo 592251538Srpaulo ieee80211_vap_detach(vap); 593251538Srpaulo free(uvp, M_80211_VAP); 594251538Srpaulo} 595251538Srpaulo 596251538Srpaulostatic struct mbuf * 597251538Srpaulourtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 598251538Srpaulo{ 599287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 600251538Srpaulo struct ieee80211_frame *wh; 601251538Srpaulo struct mbuf *m; 602251538Srpaulo struct r92c_rx_stat *stat; 603251538Srpaulo uint32_t rxdw0, rxdw3; 604251538Srpaulo uint8_t rate; 605251538Srpaulo int8_t rssi = 0; 606251538Srpaulo int infosz; 607251538Srpaulo 608251538Srpaulo /* 609251538Srpaulo * don't pass packets to the ieee80211 framework if the driver isn't 610251538Srpaulo * RUNNING. 611251538Srpaulo */ 612287197Sglebius if (!(sc->sc_flags & URTWN_RUNNING)) 613251538Srpaulo return (NULL); 614251538Srpaulo 615251538Srpaulo stat = (struct r92c_rx_stat *)buf; 616251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 617251538Srpaulo rxdw3 = le32toh(stat->rxdw3); 618251538Srpaulo 619251538Srpaulo if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 620251538Srpaulo /* 621251538Srpaulo * This should not happen since we setup our Rx filter 622251538Srpaulo * to not receive these frames. 623251538Srpaulo */ 624287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 625251538Srpaulo return (NULL); 626251538Srpaulo } 627271303Skevlo if (pktlen < sizeof(*wh) || pktlen > MCLBYTES) { 628287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 629271303Skevlo return (NULL); 630271303Skevlo } 631251538Srpaulo 632251538Srpaulo rate = MS(rxdw3, R92C_RXDW3_RATE); 633251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 634251538Srpaulo 635251538Srpaulo /* Get RSSI from PHY status descriptor if present. */ 636251538Srpaulo if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 637281069Srpaulo if (sc->chip & URTWN_CHIP_88E) 638264912Skevlo rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 639264912Skevlo else 640264912Skevlo rssi = urtwn_get_rssi(sc, rate, &stat[1]); 641251538Srpaulo /* Update our average RSSI. */ 642251538Srpaulo urtwn_update_avgrssi(sc, rate, rssi); 643251538Srpaulo } 644251538Srpaulo 645260463Skevlo m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 646251538Srpaulo if (m == NULL) { 647251538Srpaulo device_printf(sc->sc_dev, "could not create RX mbuf\n"); 648251538Srpaulo return (NULL); 649251538Srpaulo } 650251538Srpaulo 651251538Srpaulo /* Finalize mbuf. */ 652251538Srpaulo wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 653251538Srpaulo memcpy(mtod(m, uint8_t *), wh, pktlen); 654251538Srpaulo m->m_pkthdr.len = m->m_len = pktlen; 655251538Srpaulo 656251538Srpaulo if (ieee80211_radiotap_active(ic)) { 657251538Srpaulo struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 658251538Srpaulo 659251538Srpaulo tap->wr_flags = 0; 660251538Srpaulo /* Map HW rate index to 802.11 rate. */ 661251538Srpaulo if (!(rxdw3 & R92C_RXDW3_HT)) { 662289758Savos tap->wr_rate = ridx2rate[rate]; 663251538Srpaulo } else if (rate >= 12) { /* MCS0~15. */ 664251538Srpaulo /* Bit 7 set means HT MCS instead of rate. */ 665251538Srpaulo tap->wr_rate = 0x80 | (rate - 12); 666251538Srpaulo } 667251538Srpaulo tap->wr_dbm_antsignal = rssi; 668251538Srpaulo tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 669251538Srpaulo tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 670251538Srpaulo } 671251538Srpaulo 672251538Srpaulo *rssi_p = rssi; 673251538Srpaulo 674251538Srpaulo return (m); 675251538Srpaulo} 676251538Srpaulo 677251538Srpaulostatic struct mbuf * 678251538Srpaulourtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 679251538Srpaulo int8_t *nf) 680251538Srpaulo{ 681251538Srpaulo struct urtwn_softc *sc = data->sc; 682287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 683251538Srpaulo struct r92c_rx_stat *stat; 684251538Srpaulo struct mbuf *m, *m0 = NULL, *prevm = NULL; 685251538Srpaulo uint32_t rxdw0; 686251538Srpaulo uint8_t *buf; 687251538Srpaulo int len, totlen, pktlen, infosz, npkts; 688251538Srpaulo 689251538Srpaulo usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 690251538Srpaulo 691251538Srpaulo if (len < sizeof(*stat)) { 692287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 693251538Srpaulo return (NULL); 694251538Srpaulo } 695251538Srpaulo 696251538Srpaulo buf = data->buf; 697251538Srpaulo /* Get the number of encapsulated frames. */ 698251538Srpaulo stat = (struct r92c_rx_stat *)buf; 699251538Srpaulo npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 700251538Srpaulo DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 701251538Srpaulo 702251538Srpaulo /* Process all of them. */ 703251538Srpaulo while (npkts-- > 0) { 704251538Srpaulo if (len < sizeof(*stat)) 705251538Srpaulo break; 706251538Srpaulo stat = (struct r92c_rx_stat *)buf; 707251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 708251538Srpaulo 709251538Srpaulo pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 710251538Srpaulo if (pktlen == 0) 711251538Srpaulo break; 712251538Srpaulo 713251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 714251538Srpaulo 715251538Srpaulo /* Make sure everything fits in xfer. */ 716251538Srpaulo totlen = sizeof(*stat) + infosz + pktlen; 717251538Srpaulo if (totlen > len) 718251538Srpaulo break; 719251538Srpaulo 720251538Srpaulo m = urtwn_rx_frame(sc, buf, pktlen, rssi); 721251538Srpaulo if (m0 == NULL) 722251538Srpaulo m0 = m; 723251538Srpaulo if (prevm == NULL) 724251538Srpaulo prevm = m; 725251538Srpaulo else { 726251538Srpaulo prevm->m_next = m; 727251538Srpaulo prevm = m; 728251538Srpaulo } 729251538Srpaulo 730251538Srpaulo /* Next chunk is 128-byte aligned. */ 731251538Srpaulo totlen = (totlen + 127) & ~127; 732251538Srpaulo buf += totlen; 733251538Srpaulo len -= totlen; 734251538Srpaulo } 735251538Srpaulo 736251538Srpaulo return (m0); 737251538Srpaulo} 738251538Srpaulo 739251538Srpaulostatic void 740251538Srpaulourtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 741251538Srpaulo{ 742251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 743287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 744251538Srpaulo struct ieee80211_frame *wh; 745251538Srpaulo struct ieee80211_node *ni; 746251538Srpaulo struct mbuf *m = NULL, *next; 747251538Srpaulo struct urtwn_data *data; 748251538Srpaulo int8_t nf; 749251538Srpaulo int rssi = 1; 750251538Srpaulo 751251538Srpaulo URTWN_ASSERT_LOCKED(sc); 752251538Srpaulo 753251538Srpaulo switch (USB_GET_STATE(xfer)) { 754251538Srpaulo case USB_ST_TRANSFERRED: 755251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 756251538Srpaulo if (data == NULL) 757251538Srpaulo goto tr_setup; 758251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 759251538Srpaulo m = urtwn_rxeof(xfer, data, &rssi, &nf); 760251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 761251538Srpaulo /* FALLTHROUGH */ 762251538Srpaulo case USB_ST_SETUP: 763251538Srpaulotr_setup: 764251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_inactive); 765251538Srpaulo if (data == NULL) { 766251538Srpaulo KASSERT(m == NULL, ("mbuf isn't NULL")); 767251538Srpaulo return; 768251538Srpaulo } 769251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 770251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 771251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, 772251538Srpaulo usbd_xfer_max_len(xfer)); 773251538Srpaulo usbd_transfer_submit(xfer); 774251538Srpaulo 775251538Srpaulo /* 776251538Srpaulo * To avoid LOR we should unlock our private mutex here to call 777251538Srpaulo * ieee80211_input() because here is at the end of a USB 778251538Srpaulo * callback and safe to unlock. 779251538Srpaulo */ 780251538Srpaulo URTWN_UNLOCK(sc); 781251538Srpaulo while (m != NULL) { 782251538Srpaulo next = m->m_next; 783251538Srpaulo m->m_next = NULL; 784251538Srpaulo wh = mtod(m, struct ieee80211_frame *); 785251538Srpaulo ni = ieee80211_find_rxnode(ic, 786251538Srpaulo (struct ieee80211_frame_min *)wh); 787251538Srpaulo nf = URTWN_NOISE_FLOOR; 788251538Srpaulo if (ni != NULL) { 789289799Savos (void)ieee80211_input(ni, m, rssi - nf, nf); 790251538Srpaulo ieee80211_free_node(ni); 791289799Savos } else { 792289799Savos (void)ieee80211_input_all(ic, m, rssi - nf, 793289799Savos nf); 794289799Savos } 795251538Srpaulo m = next; 796251538Srpaulo } 797251538Srpaulo URTWN_LOCK(sc); 798251538Srpaulo break; 799251538Srpaulo default: 800251538Srpaulo /* needs it to the inactive queue due to a error. */ 801251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 802251538Srpaulo if (data != NULL) { 803251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 804251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 805251538Srpaulo } 806251538Srpaulo if (error != USB_ERR_CANCELLED) { 807251538Srpaulo usbd_xfer_set_stall(xfer); 808287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 809251538Srpaulo goto tr_setup; 810251538Srpaulo } 811251538Srpaulo break; 812251538Srpaulo } 813251538Srpaulo} 814251538Srpaulo 815251538Srpaulostatic void 816251538Srpaulourtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 817251538Srpaulo{ 818251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 819251538Srpaulo 820251538Srpaulo URTWN_ASSERT_LOCKED(sc); 821287197Sglebius /* XXX status? */ 822287197Sglebius ieee80211_tx_complete(data->ni, data->m, 0); 823287197Sglebius data->ni = NULL; 824287197Sglebius data->m = NULL; 825251538Srpaulo sc->sc_txtimer = 0; 826251538Srpaulo} 827251538Srpaulo 828289066Skevlostatic int 829289066Skevlourtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 830289066Skevlo int ndata, int maxsz) 831289066Skevlo{ 832289066Skevlo int i, error; 833289066Skevlo 834289066Skevlo for (i = 0; i < ndata; i++) { 835289066Skevlo struct urtwn_data *dp = &data[i]; 836289066Skevlo dp->sc = sc; 837289066Skevlo dp->m = NULL; 838289066Skevlo dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 839289066Skevlo if (dp->buf == NULL) { 840289066Skevlo device_printf(sc->sc_dev, 841289066Skevlo "could not allocate buffer\n"); 842289066Skevlo error = ENOMEM; 843289066Skevlo goto fail; 844289066Skevlo } 845289066Skevlo dp->ni = NULL; 846289066Skevlo } 847289066Skevlo 848289066Skevlo return (0); 849289066Skevlofail: 850289066Skevlo urtwn_free_list(sc, data, ndata); 851289066Skevlo return (error); 852289066Skevlo} 853289066Skevlo 854289066Skevlostatic int 855289066Skevlourtwn_alloc_rx_list(struct urtwn_softc *sc) 856289066Skevlo{ 857289066Skevlo int error, i; 858289066Skevlo 859289066Skevlo error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 860289066Skevlo URTWN_RXBUFSZ); 861289066Skevlo if (error != 0) 862289066Skevlo return (error); 863289066Skevlo 864289066Skevlo STAILQ_INIT(&sc->sc_rx_active); 865289066Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 866289066Skevlo 867289066Skevlo for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 868289066Skevlo STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 869289066Skevlo 870289066Skevlo return (0); 871289066Skevlo} 872289066Skevlo 873289066Skevlostatic int 874289066Skevlourtwn_alloc_tx_list(struct urtwn_softc *sc) 875289066Skevlo{ 876289066Skevlo int error, i; 877289066Skevlo 878289066Skevlo error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 879289066Skevlo URTWN_TXBUFSZ); 880289066Skevlo if (error != 0) 881289066Skevlo return (error); 882289066Skevlo 883289066Skevlo STAILQ_INIT(&sc->sc_tx_active); 884289066Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 885289066Skevlo STAILQ_INIT(&sc->sc_tx_pending); 886289066Skevlo 887289066Skevlo for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 888289066Skevlo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 889289066Skevlo 890289066Skevlo return (0); 891289066Skevlo} 892289066Skevlo 893251538Srpaulostatic void 894289066Skevlourtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 895289066Skevlo{ 896289066Skevlo int i; 897289066Skevlo 898289066Skevlo for (i = 0; i < ndata; i++) { 899289066Skevlo struct urtwn_data *dp = &data[i]; 900289066Skevlo 901289066Skevlo if (dp->buf != NULL) { 902289066Skevlo free(dp->buf, M_USBDEV); 903289066Skevlo dp->buf = NULL; 904289066Skevlo } 905289066Skevlo if (dp->ni != NULL) { 906289066Skevlo ieee80211_free_node(dp->ni); 907289066Skevlo dp->ni = NULL; 908289066Skevlo } 909289066Skevlo } 910289066Skevlo} 911289066Skevlo 912289066Skevlostatic void 913289066Skevlourtwn_free_rx_list(struct urtwn_softc *sc) 914289066Skevlo{ 915289066Skevlo urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 916289066Skevlo} 917289066Skevlo 918289066Skevlostatic void 919289066Skevlourtwn_free_tx_list(struct urtwn_softc *sc) 920289066Skevlo{ 921289066Skevlo urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 922289066Skevlo} 923289066Skevlo 924289066Skevlostatic void 925251538Srpaulourtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 926251538Srpaulo{ 927251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 928251538Srpaulo struct urtwn_data *data; 929251538Srpaulo 930251538Srpaulo URTWN_ASSERT_LOCKED(sc); 931251538Srpaulo 932251538Srpaulo switch (USB_GET_STATE(xfer)){ 933251538Srpaulo case USB_ST_TRANSFERRED: 934251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 935251538Srpaulo if (data == NULL) 936251538Srpaulo goto tr_setup; 937251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 938251538Srpaulo urtwn_txeof(xfer, data); 939251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 940251538Srpaulo /* FALLTHROUGH */ 941251538Srpaulo case USB_ST_SETUP: 942251538Srpaulotr_setup: 943251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_pending); 944251538Srpaulo if (data == NULL) { 945251538Srpaulo DPRINTF("%s: empty pending queue\n", __func__); 946288353Sadrian goto finish; 947251538Srpaulo } 948251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 949251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 950251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 951251538Srpaulo usbd_transfer_submit(xfer); 952251538Srpaulo break; 953251538Srpaulo default: 954251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 955251538Srpaulo if (data == NULL) 956251538Srpaulo goto tr_setup; 957251538Srpaulo if (data->ni != NULL) { 958287197Sglebius if_inc_counter(data->ni->ni_vap->iv_ifp, 959287197Sglebius IFCOUNTER_OERRORS, 1); 960251538Srpaulo ieee80211_free_node(data->ni); 961251538Srpaulo data->ni = NULL; 962251538Srpaulo } 963251538Srpaulo if (error != USB_ERR_CANCELLED) { 964251538Srpaulo usbd_xfer_set_stall(xfer); 965251538Srpaulo goto tr_setup; 966251538Srpaulo } 967251538Srpaulo break; 968251538Srpaulo } 969288353Sadrianfinish: 970288353Sadrian /* Kick-start more transmit */ 971288353Sadrian urtwn_start(sc); 972251538Srpaulo} 973251538Srpaulo 974251538Srpaulostatic struct urtwn_data * 975251538Srpaulo_urtwn_getbuf(struct urtwn_softc *sc) 976251538Srpaulo{ 977251538Srpaulo struct urtwn_data *bf; 978251538Srpaulo 979251538Srpaulo bf = STAILQ_FIRST(&sc->sc_tx_inactive); 980251538Srpaulo if (bf != NULL) 981251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 982251538Srpaulo else 983251538Srpaulo bf = NULL; 984251538Srpaulo if (bf == NULL) 985251538Srpaulo DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 986251538Srpaulo return (bf); 987251538Srpaulo} 988251538Srpaulo 989251538Srpaulostatic struct urtwn_data * 990251538Srpaulourtwn_getbuf(struct urtwn_softc *sc) 991251538Srpaulo{ 992251538Srpaulo struct urtwn_data *bf; 993251538Srpaulo 994251538Srpaulo URTWN_ASSERT_LOCKED(sc); 995251538Srpaulo 996251538Srpaulo bf = _urtwn_getbuf(sc); 997287197Sglebius if (bf == NULL) 998251538Srpaulo DPRINTF("%s: stop queue\n", __func__); 999251538Srpaulo return (bf); 1000251538Srpaulo} 1001251538Srpaulo 1002251538Srpaulostatic int 1003251538Srpaulourtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1004251538Srpaulo int len) 1005251538Srpaulo{ 1006251538Srpaulo usb_device_request_t req; 1007251538Srpaulo 1008251538Srpaulo req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1009251538Srpaulo req.bRequest = R92C_REQ_REGS; 1010251538Srpaulo USETW(req.wValue, addr); 1011251538Srpaulo USETW(req.wIndex, 0); 1012251538Srpaulo USETW(req.wLength, len); 1013251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 1014251538Srpaulo} 1015251538Srpaulo 1016251538Srpaulostatic void 1017251538Srpaulourtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1018251538Srpaulo{ 1019251538Srpaulo urtwn_write_region_1(sc, addr, &val, 1); 1020251538Srpaulo} 1021251538Srpaulo 1022251538Srpaulo 1023251538Srpaulostatic void 1024251538Srpaulourtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1025251538Srpaulo{ 1026251538Srpaulo val = htole16(val); 1027251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1028251538Srpaulo} 1029251538Srpaulo 1030251538Srpaulostatic void 1031251538Srpaulourtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1032251538Srpaulo{ 1033251538Srpaulo val = htole32(val); 1034251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1035251538Srpaulo} 1036251538Srpaulo 1037251538Srpaulostatic int 1038251538Srpaulourtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1039251538Srpaulo int len) 1040251538Srpaulo{ 1041251538Srpaulo usb_device_request_t req; 1042251538Srpaulo 1043251538Srpaulo req.bmRequestType = UT_READ_VENDOR_DEVICE; 1044251538Srpaulo req.bRequest = R92C_REQ_REGS; 1045251538Srpaulo USETW(req.wValue, addr); 1046251538Srpaulo USETW(req.wIndex, 0); 1047251538Srpaulo USETW(req.wLength, len); 1048251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 1049251538Srpaulo} 1050251538Srpaulo 1051251538Srpaulostatic uint8_t 1052251538Srpaulourtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1053251538Srpaulo{ 1054251538Srpaulo uint8_t val; 1055251538Srpaulo 1056251538Srpaulo if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1057251538Srpaulo return (0xff); 1058251538Srpaulo return (val); 1059251538Srpaulo} 1060251538Srpaulo 1061251538Srpaulostatic uint16_t 1062251538Srpaulourtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1063251538Srpaulo{ 1064251538Srpaulo uint16_t val; 1065251538Srpaulo 1066251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1067251538Srpaulo return (0xffff); 1068251538Srpaulo return (le16toh(val)); 1069251538Srpaulo} 1070251538Srpaulo 1071251538Srpaulostatic uint32_t 1072251538Srpaulourtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1073251538Srpaulo{ 1074251538Srpaulo uint32_t val; 1075251538Srpaulo 1076251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1077251538Srpaulo return (0xffffffff); 1078251538Srpaulo return (le32toh(val)); 1079251538Srpaulo} 1080251538Srpaulo 1081251538Srpaulostatic int 1082251538Srpaulourtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1083251538Srpaulo{ 1084251538Srpaulo struct r92c_fw_cmd cmd; 1085251538Srpaulo int ntries; 1086251538Srpaulo 1087251538Srpaulo /* Wait for current FW box to be empty. */ 1088251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1089251538Srpaulo if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1090251538Srpaulo break; 1091266472Shselasky urtwn_ms_delay(sc); 1092251538Srpaulo } 1093251538Srpaulo if (ntries == 100) { 1094251538Srpaulo device_printf(sc->sc_dev, 1095251538Srpaulo "could not send firmware command\n"); 1096251538Srpaulo return (ETIMEDOUT); 1097251538Srpaulo } 1098251538Srpaulo memset(&cmd, 0, sizeof(cmd)); 1099251538Srpaulo cmd.id = id; 1100251538Srpaulo if (len > 3) 1101251538Srpaulo cmd.id |= R92C_CMD_FLAG_EXT; 1102251538Srpaulo KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1103251538Srpaulo memcpy(cmd.msg, buf, len); 1104251538Srpaulo 1105251538Srpaulo /* Write the first word last since that will trigger the FW. */ 1106251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1107251538Srpaulo (uint8_t *)&cmd + 4, 2); 1108251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1109251538Srpaulo (uint8_t *)&cmd + 0, 4); 1110251538Srpaulo 1111251538Srpaulo sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1112251538Srpaulo return (0); 1113251538Srpaulo} 1114251538Srpaulo 1115264912Skevlostatic __inline void 1116251538Srpaulourtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1117251538Srpaulo{ 1118264912Skevlo 1119264912Skevlo sc->sc_rf_write(sc, chain, addr, val); 1120264912Skevlo} 1121264912Skevlo 1122264912Skevlostatic void 1123264912Skevlourtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1124264912Skevlo uint32_t val) 1125264912Skevlo{ 1126251538Srpaulo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1127251538Srpaulo SM(R92C_LSSI_PARAM_ADDR, addr) | 1128251538Srpaulo SM(R92C_LSSI_PARAM_DATA, val)); 1129251538Srpaulo} 1130251538Srpaulo 1131264912Skevlostatic void 1132264912Skevlourtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1133264912Skevlouint32_t val) 1134264912Skevlo{ 1135264912Skevlo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1136264912Skevlo SM(R88E_LSSI_PARAM_ADDR, addr) | 1137264912Skevlo SM(R92C_LSSI_PARAM_DATA, val)); 1138264912Skevlo} 1139264912Skevlo 1140251538Srpaulostatic uint32_t 1141251538Srpaulourtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1142251538Srpaulo{ 1143251538Srpaulo uint32_t reg[R92C_MAX_CHAINS], val; 1144251538Srpaulo 1145251538Srpaulo reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1146251538Srpaulo if (chain != 0) 1147251538Srpaulo reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1148251538Srpaulo 1149251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1150251538Srpaulo reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1151266472Shselasky urtwn_ms_delay(sc); 1152251538Srpaulo 1153251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1154251538Srpaulo RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1155251538Srpaulo R92C_HSSI_PARAM2_READ_EDGE); 1156266472Shselasky urtwn_ms_delay(sc); 1157251538Srpaulo 1158251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1159251538Srpaulo reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1160266472Shselasky urtwn_ms_delay(sc); 1161251538Srpaulo 1162251538Srpaulo if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1163251538Srpaulo val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1164251538Srpaulo else 1165251538Srpaulo val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1166251538Srpaulo return (MS(val, R92C_LSSI_READBACK_DATA)); 1167251538Srpaulo} 1168251538Srpaulo 1169251538Srpaulostatic int 1170251538Srpaulourtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1171251538Srpaulo{ 1172251538Srpaulo int ntries; 1173251538Srpaulo 1174251538Srpaulo urtwn_write_4(sc, R92C_LLT_INIT, 1175251538Srpaulo SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1176251538Srpaulo SM(R92C_LLT_INIT_ADDR, addr) | 1177251538Srpaulo SM(R92C_LLT_INIT_DATA, data)); 1178251538Srpaulo /* Wait for write operation to complete. */ 1179251538Srpaulo for (ntries = 0; ntries < 20; ntries++) { 1180251538Srpaulo if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1181251538Srpaulo R92C_LLT_INIT_OP_NO_ACTIVE) 1182251538Srpaulo return (0); 1183266472Shselasky urtwn_ms_delay(sc); 1184251538Srpaulo } 1185251538Srpaulo return (ETIMEDOUT); 1186251538Srpaulo} 1187251538Srpaulo 1188251538Srpaulostatic uint8_t 1189251538Srpaulourtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1190251538Srpaulo{ 1191251538Srpaulo uint32_t reg; 1192251538Srpaulo int ntries; 1193251538Srpaulo 1194251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1195251538Srpaulo reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1196251538Srpaulo reg &= ~R92C_EFUSE_CTRL_VALID; 1197251538Srpaulo urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1198251538Srpaulo /* Wait for read operation to complete. */ 1199251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1200251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1201251538Srpaulo if (reg & R92C_EFUSE_CTRL_VALID) 1202251538Srpaulo return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1203266472Shselasky urtwn_ms_delay(sc); 1204251538Srpaulo } 1205281069Srpaulo device_printf(sc->sc_dev, 1206251538Srpaulo "could not read efuse byte at address 0x%x\n", addr); 1207251538Srpaulo return (0xff); 1208251538Srpaulo} 1209251538Srpaulo 1210251538Srpaulostatic void 1211251538Srpaulourtwn_efuse_read(struct urtwn_softc *sc) 1212251538Srpaulo{ 1213251538Srpaulo uint8_t *rom = (uint8_t *)&sc->rom; 1214251538Srpaulo uint16_t addr = 0; 1215251538Srpaulo uint32_t reg; 1216282623Skevlo uint8_t off, msk; 1217251538Srpaulo int i; 1218251538Srpaulo 1219264912Skevlo urtwn_efuse_switch_power(sc); 1220264912Skevlo 1221251538Srpaulo memset(&sc->rom, 0xff, sizeof(sc->rom)); 1222251538Srpaulo while (addr < 512) { 1223251538Srpaulo reg = urtwn_efuse_read_1(sc, addr); 1224251538Srpaulo if (reg == 0xff) 1225251538Srpaulo break; 1226251538Srpaulo addr++; 1227251538Srpaulo off = reg >> 4; 1228251538Srpaulo msk = reg & 0xf; 1229251538Srpaulo for (i = 0; i < 4; i++) { 1230251538Srpaulo if (msk & (1 << i)) 1231251538Srpaulo continue; 1232251538Srpaulo rom[off * 8 + i * 2 + 0] = 1233251538Srpaulo urtwn_efuse_read_1(sc, addr); 1234251538Srpaulo addr++; 1235251538Srpaulo rom[off * 8 + i * 2 + 1] = 1236251538Srpaulo urtwn_efuse_read_1(sc, addr); 1237251538Srpaulo addr++; 1238251538Srpaulo } 1239251538Srpaulo } 1240251538Srpaulo#ifdef URTWN_DEBUG 1241251538Srpaulo if (urtwn_debug >= 2) { 1242251538Srpaulo /* Dump ROM content. */ 1243251538Srpaulo printf("\n"); 1244251538Srpaulo for (i = 0; i < sizeof(sc->rom); i++) 1245251538Srpaulo printf("%02x:", rom[i]); 1246251538Srpaulo printf("\n"); 1247251538Srpaulo } 1248251538Srpaulo#endif 1249282623Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1250282623Skevlo} 1251281592Skevlo 1252264912Skevlostatic void 1253264912Skevlourtwn_efuse_switch_power(struct urtwn_softc *sc) 1254264912Skevlo{ 1255264912Skevlo uint32_t reg; 1256251538Srpaulo 1257282623Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1258281918Skevlo 1259264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1260264912Skevlo if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1261264912Skevlo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1262264912Skevlo reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1263264912Skevlo } 1264264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1265264912Skevlo if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1266264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1267264912Skevlo reg | R92C_SYS_FUNC_EN_ELDR); 1268264912Skevlo } 1269264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1270264912Skevlo if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1271264912Skevlo (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1272264912Skevlo urtwn_write_2(sc, R92C_SYS_CLKR, 1273264912Skevlo reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1274264912Skevlo } 1275264912Skevlo} 1276264912Skevlo 1277251538Srpaulostatic int 1278251538Srpaulourtwn_read_chipid(struct urtwn_softc *sc) 1279251538Srpaulo{ 1280251538Srpaulo uint32_t reg; 1281251538Srpaulo 1282264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1283264912Skevlo return (0); 1284264912Skevlo 1285251538Srpaulo reg = urtwn_read_4(sc, R92C_SYS_CFG); 1286251538Srpaulo if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1287251538Srpaulo return (EIO); 1288251538Srpaulo 1289251538Srpaulo if (reg & R92C_SYS_CFG_TYPE_92C) { 1290251538Srpaulo sc->chip |= URTWN_CHIP_92C; 1291251538Srpaulo /* Check if it is a castrated 8192C. */ 1292251538Srpaulo if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1293251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID) == 1294251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1295251538Srpaulo sc->chip |= URTWN_CHIP_92C_1T2R; 1296251538Srpaulo } 1297251538Srpaulo if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1298251538Srpaulo sc->chip |= URTWN_CHIP_UMC; 1299251538Srpaulo if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1300251538Srpaulo sc->chip |= URTWN_CHIP_UMC_A_CUT; 1301251538Srpaulo } 1302251538Srpaulo return (0); 1303251538Srpaulo} 1304251538Srpaulo 1305251538Srpaulostatic void 1306251538Srpaulourtwn_read_rom(struct urtwn_softc *sc) 1307251538Srpaulo{ 1308251538Srpaulo struct r92c_rom *rom = &sc->rom; 1309251538Srpaulo 1310251538Srpaulo /* Read full ROM image. */ 1311251538Srpaulo urtwn_efuse_read(sc); 1312251538Srpaulo 1313251538Srpaulo /* XXX Weird but this is what the vendor driver does. */ 1314251538Srpaulo sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1315251538Srpaulo DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1316251538Srpaulo 1317251538Srpaulo sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1318251538Srpaulo 1319251538Srpaulo sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1320251538Srpaulo DPRINTF("regulatory type=%d\n", sc->regulatory); 1321287197Sglebius IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1322251538Srpaulo 1323264912Skevlo sc->sc_rf_write = urtwn_r92c_rf_write; 1324264912Skevlo sc->sc_power_on = urtwn_r92c_power_on; 1325264912Skevlo sc->sc_dma_init = urtwn_r92c_dma_init; 1326251538Srpaulo} 1327251538Srpaulo 1328264912Skevlostatic void 1329264912Skevlourtwn_r88e_read_rom(struct urtwn_softc *sc) 1330264912Skevlo{ 1331264912Skevlo uint8_t *rom = sc->r88e_rom; 1332264912Skevlo uint16_t addr = 0; 1333264912Skevlo uint32_t reg; 1334264912Skevlo uint8_t off, msk, tmp; 1335264912Skevlo int i; 1336264912Skevlo 1337264982Sandreast off = 0; 1338264912Skevlo urtwn_efuse_switch_power(sc); 1339264912Skevlo 1340264912Skevlo /* Read full ROM image. */ 1341264912Skevlo memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1342281918Skevlo while (addr < 512) { 1343264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1344264912Skevlo if (reg == 0xff) 1345264912Skevlo break; 1346264912Skevlo addr++; 1347264912Skevlo if ((reg & 0x1f) == 0x0f) { 1348264912Skevlo tmp = (reg & 0xe0) >> 5; 1349264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1350264912Skevlo if ((reg & 0x0f) != 0x0f) 1351264912Skevlo off = ((reg & 0xf0) >> 1) | tmp; 1352264912Skevlo addr++; 1353264912Skevlo } else 1354264912Skevlo off = reg >> 4; 1355264912Skevlo msk = reg & 0xf; 1356264912Skevlo for (i = 0; i < 4; i++) { 1357264912Skevlo if (msk & (1 << i)) 1358264912Skevlo continue; 1359264912Skevlo rom[off * 8 + i * 2 + 0] = 1360264912Skevlo urtwn_efuse_read_1(sc, addr); 1361264912Skevlo addr++; 1362264912Skevlo rom[off * 8 + i * 2 + 1] = 1363264912Skevlo urtwn_efuse_read_1(sc, addr); 1364264912Skevlo addr++; 1365264912Skevlo } 1366264912Skevlo } 1367264912Skevlo 1368281918Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1369281918Skevlo 1370264912Skevlo addr = 0x10; 1371264912Skevlo for (i = 0; i < 6; i++) 1372264912Skevlo sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1373264912Skevlo for (i = 0; i < 5; i++) 1374264912Skevlo sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1375264912Skevlo sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1376264912Skevlo if (sc->bw20_tx_pwr_diff & 0x08) 1377264912Skevlo sc->bw20_tx_pwr_diff |= 0xf0; 1378264912Skevlo sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1379264912Skevlo if (sc->ofdm_tx_pwr_diff & 0x08) 1380264912Skevlo sc->ofdm_tx_pwr_diff |= 0xf0; 1381264912Skevlo sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1382287197Sglebius IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &sc->r88e_rom[0xd7]); 1383264912Skevlo 1384264912Skevlo sc->sc_rf_write = urtwn_r88e_rf_write; 1385264912Skevlo sc->sc_power_on = urtwn_r88e_power_on; 1386264912Skevlo sc->sc_dma_init = urtwn_r88e_dma_init; 1387264912Skevlo} 1388264912Skevlo 1389251538Srpaulo/* 1390251538Srpaulo * Initialize rate adaptation in firmware. 1391251538Srpaulo */ 1392251538Srpaulostatic int 1393251538Srpaulourtwn_ra_init(struct urtwn_softc *sc) 1394251538Srpaulo{ 1395287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1396251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1397251538Srpaulo struct ieee80211_node *ni; 1398251538Srpaulo struct ieee80211_rateset *rs; 1399251538Srpaulo struct r92c_fw_cmd_macid_cfg cmd; 1400251538Srpaulo uint32_t rates, basicrates; 1401251538Srpaulo uint8_t mode; 1402251538Srpaulo int maxrate, maxbasicrate, error, i, j; 1403251538Srpaulo 1404251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1405251538Srpaulo rs = &ni->ni_rates; 1406251538Srpaulo 1407251538Srpaulo /* Get normal and basic rates mask. */ 1408251538Srpaulo rates = basicrates = 0; 1409251538Srpaulo maxrate = maxbasicrate = 0; 1410251538Srpaulo for (i = 0; i < rs->rs_nrates; i++) { 1411251538Srpaulo /* Convert 802.11 rate to HW rate index. */ 1412289758Savos for (j = 0; j < nitems(ridx2rate); j++) 1413289758Savos if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1414289758Savos ridx2rate[j]) 1415251538Srpaulo break; 1416289758Savos if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1417251538Srpaulo continue; 1418251538Srpaulo rates |= 1 << j; 1419251538Srpaulo if (j > maxrate) 1420251538Srpaulo maxrate = j; 1421251538Srpaulo if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1422251538Srpaulo basicrates |= 1 << j; 1423251538Srpaulo if (j > maxbasicrate) 1424251538Srpaulo maxbasicrate = j; 1425251538Srpaulo } 1426251538Srpaulo } 1427251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1428251538Srpaulo mode = R92C_RAID_11B; 1429251538Srpaulo else 1430251538Srpaulo mode = R92C_RAID_11BG; 1431251538Srpaulo DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1432251538Srpaulo mode, rates, basicrates); 1433251538Srpaulo 1434251538Srpaulo /* Set rates mask for group addressed frames. */ 1435251538Srpaulo cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1436251538Srpaulo cmd.mask = htole32(mode << 28 | basicrates); 1437251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1438251538Srpaulo if (error != 0) { 1439252401Srpaulo ieee80211_free_node(ni); 1440251538Srpaulo device_printf(sc->sc_dev, 1441251538Srpaulo "could not add broadcast station\n"); 1442251538Srpaulo return (error); 1443251538Srpaulo } 1444251538Srpaulo /* Set initial MRR rate. */ 1445251538Srpaulo DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1446251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1447251538Srpaulo maxbasicrate); 1448251538Srpaulo 1449251538Srpaulo /* Set rates mask for unicast frames. */ 1450251538Srpaulo cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1451251538Srpaulo cmd.mask = htole32(mode << 28 | rates); 1452251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1453251538Srpaulo if (error != 0) { 1454252401Srpaulo ieee80211_free_node(ni); 1455251538Srpaulo device_printf(sc->sc_dev, "could not add BSS station\n"); 1456251538Srpaulo return (error); 1457251538Srpaulo } 1458251538Srpaulo /* Set initial MRR rate. */ 1459251538Srpaulo DPRINTF("maxrate=%d\n", maxrate); 1460251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1461251538Srpaulo maxrate); 1462251538Srpaulo 1463251538Srpaulo /* Indicate highest supported rate. */ 1464252403Srpaulo ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1465252401Srpaulo ieee80211_free_node(ni); 1466252401Srpaulo 1467251538Srpaulo return (0); 1468251538Srpaulo} 1469251538Srpaulo 1470251538Srpaulovoid 1471251538Srpaulourtwn_tsf_sync_enable(struct urtwn_softc *sc) 1472251538Srpaulo{ 1473287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1474251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1475251538Srpaulo struct ieee80211_node *ni = vap->iv_bss; 1476251538Srpaulo 1477251538Srpaulo uint64_t tsf; 1478251538Srpaulo 1479251538Srpaulo /* Enable TSF synchronization. */ 1480251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1481251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1482251538Srpaulo 1483251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1484251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1485251538Srpaulo 1486251538Srpaulo /* Set initial TSF. */ 1487251538Srpaulo memcpy(&tsf, ni->ni_tstamp.data, 8); 1488251538Srpaulo tsf = le64toh(tsf); 1489251538Srpaulo tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1490251538Srpaulo tsf -= IEEE80211_DUR_TU; 1491251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1492251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1493251538Srpaulo 1494251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1495251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1496251538Srpaulo} 1497251538Srpaulo 1498251538Srpaulostatic void 1499251538Srpaulourtwn_set_led(struct urtwn_softc *sc, int led, int on) 1500251538Srpaulo{ 1501251538Srpaulo uint8_t reg; 1502281069Srpaulo 1503251538Srpaulo if (led == URTWN_LED_LINK) { 1504264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 1505264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1506264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1507264912Skevlo if (!on) { 1508264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1509264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, 1510264912Skevlo reg | R92C_LEDCFG0_DIS); 1511264912Skevlo urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1512264912Skevlo urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1513264912Skevlo 0xfe); 1514264912Skevlo } 1515264912Skevlo } else { 1516264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1517264912Skevlo if (!on) 1518264912Skevlo reg |= R92C_LEDCFG0_DIS; 1519264912Skevlo urtwn_write_1(sc, R92C_LEDCFG0, reg); 1520264912Skevlo } 1521264912Skevlo sc->ledlink = on; /* Save LED state. */ 1522251538Srpaulo } 1523251538Srpaulo} 1524251538Srpaulo 1525251538Srpaulostatic int 1526251538Srpaulourtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1527251538Srpaulo{ 1528251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 1529251538Srpaulo struct ieee80211com *ic = vap->iv_ic; 1530286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 1531251538Srpaulo struct ieee80211_node *ni; 1532251538Srpaulo enum ieee80211_state ostate; 1533251538Srpaulo uint32_t reg; 1534251538Srpaulo 1535251538Srpaulo ostate = vap->iv_state; 1536251538Srpaulo DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1537251538Srpaulo ieee80211_state_name[nstate]); 1538251538Srpaulo 1539251538Srpaulo IEEE80211_UNLOCK(ic); 1540251538Srpaulo URTWN_LOCK(sc); 1541251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 1542251538Srpaulo 1543251538Srpaulo if (ostate == IEEE80211_S_RUN) { 1544251538Srpaulo /* Turn link LED off. */ 1545251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1546251538Srpaulo 1547251538Srpaulo /* Set media status to 'No Link'. */ 1548251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 1549251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1550251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 1551251538Srpaulo 1552251538Srpaulo /* Stop Rx of data frames. */ 1553251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1554251538Srpaulo 1555251538Srpaulo /* Rest TSF. */ 1556251538Srpaulo urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1557251538Srpaulo 1558251538Srpaulo /* Disable TSF synchronization. */ 1559251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1560251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | 1561251538Srpaulo R92C_BCN_CTRL_DIS_TSF_UDT0); 1562251538Srpaulo 1563251538Srpaulo /* Reset EDCA parameters. */ 1564251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1565251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1566251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1567251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1568251538Srpaulo } 1569251538Srpaulo 1570251538Srpaulo switch (nstate) { 1571251538Srpaulo case IEEE80211_S_INIT: 1572251538Srpaulo /* Turn link LED off. */ 1573251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1574251538Srpaulo break; 1575251538Srpaulo case IEEE80211_S_SCAN: 1576251538Srpaulo if (ostate != IEEE80211_S_SCAN) { 1577251538Srpaulo /* Allow Rx from any BSSID. */ 1578251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1579251538Srpaulo urtwn_read_4(sc, R92C_RCR) & 1580251538Srpaulo ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1581251538Srpaulo 1582251538Srpaulo /* Set gain for scanning. */ 1583251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1584251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1585251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1586251538Srpaulo 1587264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1588264912Skevlo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1589264912Skevlo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1590264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1591264912Skevlo } 1592251538Srpaulo } 1593251538Srpaulo /* Pause AC Tx queues. */ 1594251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 1595251538Srpaulo urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1596251538Srpaulo break; 1597251538Srpaulo case IEEE80211_S_AUTH: 1598251538Srpaulo /* Set initial gain under link. */ 1599251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1600251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1601251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1602251538Srpaulo 1603264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1604264912Skevlo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1605264912Skevlo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1606264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1607264912Skevlo } 1608251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 1609251538Srpaulo break; 1610251538Srpaulo case IEEE80211_S_RUN: 1611251538Srpaulo if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1612251538Srpaulo /* Enable Rx of data frames. */ 1613251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1614251538Srpaulo 1615289173Skevlo /* Enable Rx of ctrl frames. */ 1616289173Skevlo urtwn_write_2(sc, R92C_RXFLTMAP1, 0xffff); 1617289173Skevlo 1618289173Skevlo /* 1619289173Skevlo * Accept data/control/management frames 1620289173Skevlo * from any BSSID. 1621289173Skevlo */ 1622289173Skevlo urtwn_write_4(sc, R92C_RCR, 1623289173Skevlo (urtwn_read_4(sc, R92C_RCR) & ~(R92C_RCR_APM | 1624289173Skevlo R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)) | 1625289173Skevlo R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF | 1626289173Skevlo R92C_RCR_AAP); 1627289173Skevlo 1628251538Srpaulo /* Turn link LED on. */ 1629251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1630251538Srpaulo break; 1631251538Srpaulo } 1632251538Srpaulo 1633251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1634251538Srpaulo /* Set media status to 'Associated'. */ 1635251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 1636251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1637251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 1638251538Srpaulo 1639251538Srpaulo /* Set BSSID. */ 1640251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1641251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1642251538Srpaulo 1643251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1644251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1645251538Srpaulo else /* 802.11b/g */ 1646251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1647251538Srpaulo 1648251538Srpaulo /* Enable Rx of data frames. */ 1649251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1650251538Srpaulo 1651251538Srpaulo /* Flush all AC queues. */ 1652251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0); 1653251538Srpaulo 1654251538Srpaulo /* Set beacon interval. */ 1655251538Srpaulo urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1656251538Srpaulo 1657251538Srpaulo /* Allow Rx from our BSSID only. */ 1658251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1659251538Srpaulo urtwn_read_4(sc, R92C_RCR) | 1660251538Srpaulo R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1661251538Srpaulo 1662251538Srpaulo /* Enable TSF synchronization. */ 1663251538Srpaulo urtwn_tsf_sync_enable(sc); 1664251538Srpaulo 1665251538Srpaulo urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1666251538Srpaulo urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1667251538Srpaulo urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1668251538Srpaulo urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1669251538Srpaulo urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1670251538Srpaulo urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1671251538Srpaulo 1672251538Srpaulo /* Intialize rate adaptation. */ 1673264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1674264912Skevlo ni->ni_txrate = 1675264912Skevlo ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1676281069Srpaulo else 1677264912Skevlo urtwn_ra_init(sc); 1678251538Srpaulo /* Turn link LED on. */ 1679251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1680251538Srpaulo 1681251538Srpaulo sc->avg_pwdb = -1; /* Reset average RSSI. */ 1682251538Srpaulo /* Reset temperature calibration state machine. */ 1683251538Srpaulo sc->thcal_state = 0; 1684251538Srpaulo sc->thcal_lctemp = 0; 1685251538Srpaulo ieee80211_free_node(ni); 1686251538Srpaulo break; 1687251538Srpaulo default: 1688251538Srpaulo break; 1689251538Srpaulo } 1690251538Srpaulo URTWN_UNLOCK(sc); 1691251538Srpaulo IEEE80211_LOCK(ic); 1692251538Srpaulo return(uvp->newstate(vap, nstate, arg)); 1693251538Srpaulo} 1694251538Srpaulo 1695251538Srpaulostatic void 1696251538Srpaulourtwn_watchdog(void *arg) 1697251538Srpaulo{ 1698251538Srpaulo struct urtwn_softc *sc = arg; 1699251538Srpaulo 1700251538Srpaulo if (sc->sc_txtimer > 0) { 1701251538Srpaulo if (--sc->sc_txtimer == 0) { 1702251538Srpaulo device_printf(sc->sc_dev, "device timeout\n"); 1703287197Sglebius counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1704251538Srpaulo return; 1705251538Srpaulo } 1706251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1707251538Srpaulo } 1708251538Srpaulo} 1709251538Srpaulo 1710251538Srpaulostatic void 1711251538Srpaulourtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1712251538Srpaulo{ 1713251538Srpaulo int pwdb; 1714251538Srpaulo 1715251538Srpaulo /* Convert antenna signal to percentage. */ 1716251538Srpaulo if (rssi <= -100 || rssi >= 20) 1717251538Srpaulo pwdb = 0; 1718251538Srpaulo else if (rssi >= 0) 1719251538Srpaulo pwdb = 100; 1720251538Srpaulo else 1721251538Srpaulo pwdb = 100 + rssi; 1722264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1723289758Savos if (rate <= URTWN_RIDX_CCK11) { 1724264912Skevlo /* CCK gain is smaller than OFDM/MCS gain. */ 1725264912Skevlo pwdb += 6; 1726264912Skevlo if (pwdb > 100) 1727264912Skevlo pwdb = 100; 1728264912Skevlo if (pwdb <= 14) 1729264912Skevlo pwdb -= 4; 1730264912Skevlo else if (pwdb <= 26) 1731264912Skevlo pwdb -= 8; 1732264912Skevlo else if (pwdb <= 34) 1733264912Skevlo pwdb -= 6; 1734264912Skevlo else if (pwdb <= 42) 1735264912Skevlo pwdb -= 2; 1736264912Skevlo } 1737251538Srpaulo } 1738251538Srpaulo if (sc->avg_pwdb == -1) /* Init. */ 1739251538Srpaulo sc->avg_pwdb = pwdb; 1740251538Srpaulo else if (sc->avg_pwdb < pwdb) 1741251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1742251538Srpaulo else 1743251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1744251538Srpaulo DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1745251538Srpaulo} 1746251538Srpaulo 1747251538Srpaulostatic int8_t 1748251538Srpaulourtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1749251538Srpaulo{ 1750251538Srpaulo static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1751251538Srpaulo struct r92c_rx_phystat *phy; 1752251538Srpaulo struct r92c_rx_cck *cck; 1753251538Srpaulo uint8_t rpt; 1754251538Srpaulo int8_t rssi; 1755251538Srpaulo 1756289758Savos if (rate <= URTWN_RIDX_CCK11) { 1757251538Srpaulo cck = (struct r92c_rx_cck *)physt; 1758251538Srpaulo if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1759251538Srpaulo rpt = (cck->agc_rpt >> 5) & 0x3; 1760251538Srpaulo rssi = (cck->agc_rpt & 0x1f) << 1; 1761251538Srpaulo } else { 1762251538Srpaulo rpt = (cck->agc_rpt >> 6) & 0x3; 1763251538Srpaulo rssi = cck->agc_rpt & 0x3e; 1764251538Srpaulo } 1765251538Srpaulo rssi = cckoff[rpt] - rssi; 1766251538Srpaulo } else { /* OFDM/HT. */ 1767251538Srpaulo phy = (struct r92c_rx_phystat *)physt; 1768251538Srpaulo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1769251538Srpaulo } 1770251538Srpaulo return (rssi); 1771251538Srpaulo} 1772251538Srpaulo 1773264912Skevlostatic int8_t 1774264912Skevlourtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1775264912Skevlo{ 1776264912Skevlo struct r92c_rx_phystat *phy; 1777264912Skevlo struct r88e_rx_cck *cck; 1778264912Skevlo uint8_t cck_agc_rpt, lna_idx, vga_idx; 1779264912Skevlo int8_t rssi; 1780264912Skevlo 1781264972Skevlo rssi = 0; 1782289758Savos if (rate <= URTWN_RIDX_CCK11) { 1783264912Skevlo cck = (struct r88e_rx_cck *)physt; 1784264912Skevlo cck_agc_rpt = cck->agc_rpt; 1785264912Skevlo lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1786281069Srpaulo vga_idx = cck_agc_rpt & 0x1f; 1787264912Skevlo switch (lna_idx) { 1788264912Skevlo case 7: 1789264912Skevlo if (vga_idx <= 27) 1790264912Skevlo rssi = -100 + 2* (27 - vga_idx); 1791264912Skevlo else 1792264912Skevlo rssi = -100; 1793264912Skevlo break; 1794264912Skevlo case 6: 1795264912Skevlo rssi = -48 + 2 * (2 - vga_idx); 1796264912Skevlo break; 1797264912Skevlo case 5: 1798264912Skevlo rssi = -42 + 2 * (7 - vga_idx); 1799264912Skevlo break; 1800264912Skevlo case 4: 1801264912Skevlo rssi = -36 + 2 * (7 - vga_idx); 1802264912Skevlo break; 1803264912Skevlo case 3: 1804264912Skevlo rssi = -24 + 2 * (7 - vga_idx); 1805264912Skevlo break; 1806264912Skevlo case 2: 1807264912Skevlo rssi = -12 + 2 * (5 - vga_idx); 1808264912Skevlo break; 1809264912Skevlo case 1: 1810264912Skevlo rssi = 8 - (2 * vga_idx); 1811264912Skevlo break; 1812264912Skevlo case 0: 1813264912Skevlo rssi = 14 - (2 * vga_idx); 1814264912Skevlo break; 1815264912Skevlo } 1816264912Skevlo rssi += 6; 1817264912Skevlo } else { /* OFDM/HT. */ 1818264912Skevlo phy = (struct r92c_rx_phystat *)physt; 1819264912Skevlo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1820264912Skevlo } 1821264912Skevlo return (rssi); 1822264912Skevlo} 1823264912Skevlo 1824251538Srpaulostatic int 1825281069Srpaulourtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1826251538Srpaulo struct mbuf *m0, struct urtwn_data *data) 1827251538Srpaulo{ 1828251538Srpaulo struct ieee80211_frame *wh; 1829251538Srpaulo struct ieee80211_key *k; 1830287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1831251538Srpaulo struct ieee80211vap *vap = ni->ni_vap; 1832251538Srpaulo struct usb_xfer *xfer; 1833251538Srpaulo struct r92c_tx_desc *txd; 1834251538Srpaulo uint8_t raid, type; 1835251538Srpaulo uint16_t sum; 1836288534Sadrian int i, xferlen; 1837251538Srpaulo struct usb_xfer *urtwn_pipes[4] = { 1838251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BE], 1839251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BK], 1840251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VI], 1841251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VO] 1842251538Srpaulo }; 1843251538Srpaulo 1844251538Srpaulo URTWN_ASSERT_LOCKED(sc); 1845251538Srpaulo 1846251538Srpaulo /* 1847251538Srpaulo * Software crypto. 1848251538Srpaulo */ 1849251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1850264912Skevlo type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1851264912Skevlo 1852260444Skevlo if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1853251538Srpaulo k = ieee80211_crypto_encap(ni, m0); 1854251538Srpaulo if (k == NULL) { 1855251538Srpaulo device_printf(sc->sc_dev, 1856251538Srpaulo "ieee80211_crypto_encap returns NULL.\n"); 1857251538Srpaulo /* XXX we don't expect the fragmented frames */ 1858251538Srpaulo return (ENOBUFS); 1859251538Srpaulo } 1860251538Srpaulo 1861251538Srpaulo /* in case packet header moved, reset pointer */ 1862251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1863251538Srpaulo } 1864281069Srpaulo 1865264912Skevlo switch (type) { 1866251538Srpaulo case IEEE80211_FC0_TYPE_CTL: 1867251538Srpaulo case IEEE80211_FC0_TYPE_MGT: 1868251538Srpaulo xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1869251538Srpaulo break; 1870251538Srpaulo default: 1871251538Srpaulo KASSERT(M_WME_GETAC(m0) < 4, 1872251538Srpaulo ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1873251538Srpaulo xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1874251538Srpaulo break; 1875251538Srpaulo } 1876281069Srpaulo 1877251538Srpaulo /* Fill Tx descriptor. */ 1878251538Srpaulo txd = (struct r92c_tx_desc *)data->buf; 1879251538Srpaulo memset(txd, 0, sizeof(*txd)); 1880251538Srpaulo 1881251538Srpaulo txd->txdw0 |= htole32( 1882251538Srpaulo SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1883251538Srpaulo SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1884251538Srpaulo R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1885251538Srpaulo if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1886251538Srpaulo txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1887251538Srpaulo if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1888251538Srpaulo type == IEEE80211_FC0_TYPE_DATA) { 1889251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1890251538Srpaulo raid = R92C_RAID_11B; 1891251538Srpaulo else 1892251538Srpaulo raid = R92C_RAID_11BG; 1893264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 1894264912Skevlo txd->txdw1 |= htole32( 1895264912Skevlo SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1896264912Skevlo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1897264912Skevlo SM(R92C_TXDW1_RAID, raid)); 1898264912Skevlo txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1899264912Skevlo } else { 1900264912Skevlo txd->txdw1 |= htole32( 1901264912Skevlo SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1902264912Skevlo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1903264912Skevlo SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1904264912Skevlo } 1905251538Srpaulo if (ic->ic_flags & IEEE80211_F_USEPROT) { 1906251538Srpaulo if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1907251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1908251538Srpaulo R92C_TXDW4_HWRTSEN); 1909251538Srpaulo } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1910251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1911251538Srpaulo R92C_TXDW4_HWRTSEN); 1912251538Srpaulo } 1913251538Srpaulo } 1914251538Srpaulo /* Send RTS at OFDM24. */ 1915289758Savos txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1916289758Savos URTWN_RIDX_OFDM24)); 1917251538Srpaulo txd->txdw5 |= htole32(0x0001ff00); 1918251538Srpaulo /* Send data at OFDM54. */ 1919289758Savos txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1920289758Savos URTWN_RIDX_OFDM54)); 1921251538Srpaulo } else { 1922251538Srpaulo txd->txdw1 |= htole32( 1923251538Srpaulo SM(R92C_TXDW1_MACID, 0) | 1924251538Srpaulo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1925251538Srpaulo SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1926251538Srpaulo 1927251538Srpaulo /* Force CCK1. */ 1928251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1929289758Savos txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1930289758Savos URTWN_RIDX_CCK1)); 1931251538Srpaulo } 1932251538Srpaulo /* Set sequence number (already little endian). */ 1933251538Srpaulo txd->txdseq |= *(uint16_t *)wh->i_seq; 1934251538Srpaulo 1935288534Sadrian if (!IEEE80211_QOS_HAS_SEQ(wh)) { 1936251538Srpaulo /* Use HW sequence numbering for non-QoS frames. */ 1937251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1938251538Srpaulo txd->txdseq |= htole16(0x8000); 1939251538Srpaulo } else 1940251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1941251538Srpaulo 1942251538Srpaulo /* Compute Tx descriptor checksum. */ 1943251538Srpaulo sum = 0; 1944251538Srpaulo for (i = 0; i < sizeof(*txd) / 2; i++) 1945251538Srpaulo sum ^= ((uint16_t *)txd)[i]; 1946251538Srpaulo txd->txdsum = sum; /* NB: already little endian. */ 1947251538Srpaulo 1948251538Srpaulo if (ieee80211_radiotap_active_vap(vap)) { 1949251538Srpaulo struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1950251538Srpaulo 1951251538Srpaulo tap->wt_flags = 0; 1952251538Srpaulo tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1953251538Srpaulo tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1954251538Srpaulo ieee80211_radiotap_tx(vap, m0); 1955251538Srpaulo } 1956251538Srpaulo 1957251538Srpaulo xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1958251538Srpaulo m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1959251538Srpaulo 1960251538Srpaulo data->buflen = xferlen; 1961251538Srpaulo data->ni = ni; 1962251538Srpaulo data->m = m0; 1963251538Srpaulo 1964251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1965251538Srpaulo usbd_transfer_start(xfer); 1966251538Srpaulo return (0); 1967251538Srpaulo} 1968251538Srpaulo 1969287197Sglebiusstatic int 1970287197Sglebiusurtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1971251538Srpaulo{ 1972287197Sglebius struct urtwn_softc *sc = ic->ic_softc; 1973287197Sglebius int error; 1974261863Srpaulo 1975261863Srpaulo URTWN_LOCK(sc); 1976287197Sglebius if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1977287197Sglebius URTWN_UNLOCK(sc); 1978287197Sglebius return (ENXIO); 1979287197Sglebius } 1980287197Sglebius error = mbufq_enqueue(&sc->sc_snd, m); 1981287197Sglebius if (error) { 1982287197Sglebius URTWN_UNLOCK(sc); 1983287197Sglebius return (error); 1984287197Sglebius } 1985287197Sglebius urtwn_start(sc); 1986261863Srpaulo URTWN_UNLOCK(sc); 1987287197Sglebius 1988287197Sglebius return (0); 1989261863Srpaulo} 1990261863Srpaulo 1991261863Srpaulostatic void 1992287197Sglebiusurtwn_start(struct urtwn_softc *sc) 1993261863Srpaulo{ 1994251538Srpaulo struct ieee80211_node *ni; 1995251538Srpaulo struct mbuf *m; 1996251538Srpaulo struct urtwn_data *bf; 1997251538Srpaulo 1998261863Srpaulo URTWN_ASSERT_LOCKED(sc); 1999287197Sglebius while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2000251538Srpaulo bf = urtwn_getbuf(sc); 2001251538Srpaulo if (bf == NULL) { 2002287197Sglebius mbufq_prepend(&sc->sc_snd, m); 2003251538Srpaulo break; 2004251538Srpaulo } 2005251538Srpaulo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2006251538Srpaulo m->m_pkthdr.rcvif = NULL; 2007251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 2008287197Sglebius if_inc_counter(ni->ni_vap->iv_ifp, 2009287197Sglebius IFCOUNTER_OERRORS, 1); 2010251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2011288353Sadrian m_freem(m); 2012251538Srpaulo ieee80211_free_node(ni); 2013251538Srpaulo break; 2014251538Srpaulo } 2015251538Srpaulo sc->sc_txtimer = 5; 2016251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2017251538Srpaulo } 2018251538Srpaulo} 2019251538Srpaulo 2020287197Sglebiusstatic void 2021287197Sglebiusurtwn_parent(struct ieee80211com *ic) 2022251538Srpaulo{ 2023286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 2024287197Sglebius int startall = 0; 2025251538Srpaulo 2026263153Skevlo URTWN_LOCK(sc); 2027287197Sglebius if (sc->sc_flags & URTWN_DETACHED) { 2028287197Sglebius URTWN_UNLOCK(sc); 2029287197Sglebius return; 2030287197Sglebius } 2031287197Sglebius if (ic->ic_nrunning > 0) { 2032287197Sglebius if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2033287197Sglebius urtwn_init(sc); 2034287197Sglebius startall = 1; 2035287197Sglebius } 2036287197Sglebius } else if (sc->sc_flags & URTWN_RUNNING) 2037287197Sglebius urtwn_stop(sc); 2038263153Skevlo URTWN_UNLOCK(sc); 2039263153Skevlo 2040287197Sglebius if (startall) 2041287197Sglebius ieee80211_start_all(ic); 2042251538Srpaulo} 2043251538Srpaulo 2044264912Skevlostatic __inline int 2045251538Srpaulourtwn_power_on(struct urtwn_softc *sc) 2046251538Srpaulo{ 2047264912Skevlo 2048264912Skevlo return sc->sc_power_on(sc); 2049264912Skevlo} 2050264912Skevlo 2051264912Skevlostatic int 2052264912Skevlourtwn_r92c_power_on(struct urtwn_softc *sc) 2053264912Skevlo{ 2054251538Srpaulo uint32_t reg; 2055251538Srpaulo int ntries; 2056251538Srpaulo 2057251538Srpaulo /* Wait for autoload done bit. */ 2058251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2059251538Srpaulo if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2060251538Srpaulo break; 2061266472Shselasky urtwn_ms_delay(sc); 2062251538Srpaulo } 2063251538Srpaulo if (ntries == 1000) { 2064251538Srpaulo device_printf(sc->sc_dev, 2065251538Srpaulo "timeout waiting for chip autoload\n"); 2066251538Srpaulo return (ETIMEDOUT); 2067251538Srpaulo } 2068251538Srpaulo 2069251538Srpaulo /* Unlock ISO/CLK/Power control register. */ 2070251538Srpaulo urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2071251538Srpaulo /* Move SPS into PWM mode. */ 2072251538Srpaulo urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2073266472Shselasky urtwn_ms_delay(sc); 2074251538Srpaulo 2075251538Srpaulo reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2076251538Srpaulo if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2077251538Srpaulo urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2078251538Srpaulo reg | R92C_LDOV12D_CTRL_LDV12_EN); 2079266472Shselasky urtwn_ms_delay(sc); 2080251538Srpaulo urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2081251538Srpaulo urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2082251538Srpaulo ~R92C_SYS_ISO_CTRL_MD2PP); 2083251538Srpaulo } 2084251538Srpaulo 2085251538Srpaulo /* Auto enable WLAN. */ 2086251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2087251538Srpaulo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2088251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2089262822Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2090262822Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2091251538Srpaulo break; 2092266472Shselasky urtwn_ms_delay(sc); 2093251538Srpaulo } 2094251538Srpaulo if (ntries == 1000) { 2095251538Srpaulo device_printf(sc->sc_dev, 2096251538Srpaulo "timeout waiting for MAC auto ON\n"); 2097251538Srpaulo return (ETIMEDOUT); 2098251538Srpaulo } 2099251538Srpaulo 2100251538Srpaulo /* Enable radio, GPIO and LED functions. */ 2101251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2102251538Srpaulo R92C_APS_FSMCO_AFSM_HSUS | 2103251538Srpaulo R92C_APS_FSMCO_PDN_EN | 2104251538Srpaulo R92C_APS_FSMCO_PFM_ALDN); 2105251538Srpaulo /* Release RF digital isolation. */ 2106251538Srpaulo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2107251538Srpaulo urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2108251538Srpaulo 2109251538Srpaulo /* Initialize MAC. */ 2110251538Srpaulo urtwn_write_1(sc, R92C_APSD_CTRL, 2111251538Srpaulo urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2112251538Srpaulo for (ntries = 0; ntries < 200; ntries++) { 2113251538Srpaulo if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2114251538Srpaulo R92C_APSD_CTRL_OFF_STATUS)) 2115251538Srpaulo break; 2116266472Shselasky urtwn_ms_delay(sc); 2117251538Srpaulo } 2118251538Srpaulo if (ntries == 200) { 2119251538Srpaulo device_printf(sc->sc_dev, 2120251538Srpaulo "timeout waiting for MAC initialization\n"); 2121251538Srpaulo return (ETIMEDOUT); 2122251538Srpaulo } 2123251538Srpaulo 2124251538Srpaulo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2125251538Srpaulo reg = urtwn_read_2(sc, R92C_CR); 2126251538Srpaulo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2127251538Srpaulo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2128251538Srpaulo R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2129251538Srpaulo R92C_CR_ENSEC; 2130251538Srpaulo urtwn_write_2(sc, R92C_CR, reg); 2131251538Srpaulo 2132251538Srpaulo urtwn_write_1(sc, 0xfe10, 0x19); 2133251538Srpaulo return (0); 2134251538Srpaulo} 2135251538Srpaulo 2136251538Srpaulostatic int 2137264912Skevlourtwn_r88e_power_on(struct urtwn_softc *sc) 2138264912Skevlo{ 2139264912Skevlo uint32_t reg; 2140264912Skevlo int ntries; 2141264912Skevlo 2142264912Skevlo /* Wait for power ready bit. */ 2143264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2144281918Skevlo if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2145264912Skevlo break; 2146266472Shselasky urtwn_ms_delay(sc); 2147264912Skevlo } 2148264912Skevlo if (ntries == 5000) { 2149264912Skevlo device_printf(sc->sc_dev, 2150264912Skevlo "timeout waiting for chip power up\n"); 2151264912Skevlo return (ETIMEDOUT); 2152264912Skevlo } 2153264912Skevlo 2154264912Skevlo /* Reset BB. */ 2155264912Skevlo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2156264912Skevlo urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2157264912Skevlo R92C_SYS_FUNC_EN_BB_GLB_RST)); 2158264912Skevlo 2159281918Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2160281918Skevlo urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2161264912Skevlo 2162264912Skevlo /* Disable HWPDN. */ 2163281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2164281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2165264912Skevlo 2166264912Skevlo /* Disable WL suspend. */ 2167281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2168281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & 2169281918Skevlo ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2170264912Skevlo 2171281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2172281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2173264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2174281918Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2175281918Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2176264912Skevlo break; 2177266472Shselasky urtwn_ms_delay(sc); 2178264912Skevlo } 2179264912Skevlo if (ntries == 5000) 2180264912Skevlo return (ETIMEDOUT); 2181264912Skevlo 2182264912Skevlo /* Enable LDO normal mode. */ 2183281918Skevlo urtwn_write_1(sc, R92C_LPLDO_CTRL, 2184281918Skevlo urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2185264912Skevlo 2186264912Skevlo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2187264912Skevlo urtwn_write_2(sc, R92C_CR, 0); 2188264912Skevlo reg = urtwn_read_2(sc, R92C_CR); 2189264912Skevlo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2190264912Skevlo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2191264912Skevlo R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2192264912Skevlo urtwn_write_2(sc, R92C_CR, reg); 2193264912Skevlo 2194264912Skevlo return (0); 2195264912Skevlo} 2196264912Skevlo 2197264912Skevlostatic int 2198251538Srpaulourtwn_llt_init(struct urtwn_softc *sc) 2199251538Srpaulo{ 2200264912Skevlo int i, error, page_count, pktbuf_count; 2201251538Srpaulo 2202264912Skevlo page_count = (sc->chip & URTWN_CHIP_88E) ? 2203264912Skevlo R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2204264912Skevlo pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2205264912Skevlo R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2206264912Skevlo 2207264912Skevlo /* Reserve pages [0; page_count]. */ 2208264912Skevlo for (i = 0; i < page_count; i++) { 2209251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2210251538Srpaulo return (error); 2211251538Srpaulo } 2212251538Srpaulo /* NB: 0xff indicates end-of-list. */ 2213251538Srpaulo if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2214251538Srpaulo return (error); 2215251538Srpaulo /* 2216264912Skevlo * Use pages [page_count + 1; pktbuf_count - 1] 2217251538Srpaulo * as ring buffer. 2218251538Srpaulo */ 2219264912Skevlo for (++i; i < pktbuf_count - 1; i++) { 2220251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2221251538Srpaulo return (error); 2222251538Srpaulo } 2223251538Srpaulo /* Make the last page point to the beginning of the ring buffer. */ 2224264912Skevlo error = urtwn_llt_write(sc, i, page_count + 1); 2225251538Srpaulo return (error); 2226251538Srpaulo} 2227251538Srpaulo 2228251538Srpaulostatic void 2229251538Srpaulourtwn_fw_reset(struct urtwn_softc *sc) 2230251538Srpaulo{ 2231251538Srpaulo uint16_t reg; 2232251538Srpaulo int ntries; 2233251538Srpaulo 2234251538Srpaulo /* Tell 8051 to reset itself. */ 2235251538Srpaulo urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2236251538Srpaulo 2237251538Srpaulo /* Wait until 8051 resets by itself. */ 2238251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 2239251538Srpaulo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2240251538Srpaulo if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2241251538Srpaulo return; 2242266472Shselasky urtwn_ms_delay(sc); 2243251538Srpaulo } 2244251538Srpaulo /* Force 8051 reset. */ 2245251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2246251538Srpaulo} 2247251538Srpaulo 2248264912Skevlostatic void 2249264912Skevlourtwn_r88e_fw_reset(struct urtwn_softc *sc) 2250264912Skevlo{ 2251264912Skevlo uint16_t reg; 2252264912Skevlo 2253264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2254264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2255264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2256264912Skevlo} 2257264912Skevlo 2258251538Srpaulostatic int 2259251538Srpaulourtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2260251538Srpaulo{ 2261251538Srpaulo uint32_t reg; 2262251538Srpaulo int off, mlen, error = 0; 2263251538Srpaulo 2264251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2265251538Srpaulo reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2266251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2267251538Srpaulo 2268251538Srpaulo off = R92C_FW_START_ADDR; 2269251538Srpaulo while (len > 0) { 2270251538Srpaulo if (len > 196) 2271251538Srpaulo mlen = 196; 2272251538Srpaulo else if (len > 4) 2273251538Srpaulo mlen = 4; 2274251538Srpaulo else 2275251538Srpaulo mlen = 1; 2276251538Srpaulo /* XXX fix this deconst */ 2277281069Srpaulo error = urtwn_write_region_1(sc, off, 2278251538Srpaulo __DECONST(uint8_t *, buf), mlen); 2279251538Srpaulo if (error != 0) 2280251538Srpaulo break; 2281251538Srpaulo off += mlen; 2282251538Srpaulo buf += mlen; 2283251538Srpaulo len -= mlen; 2284251538Srpaulo } 2285251538Srpaulo return (error); 2286251538Srpaulo} 2287251538Srpaulo 2288251538Srpaulostatic int 2289251538Srpaulourtwn_load_firmware(struct urtwn_softc *sc) 2290251538Srpaulo{ 2291251538Srpaulo const struct firmware *fw; 2292251538Srpaulo const struct r92c_fw_hdr *hdr; 2293251538Srpaulo const char *imagename; 2294251538Srpaulo const u_char *ptr; 2295251538Srpaulo size_t len; 2296251538Srpaulo uint32_t reg; 2297251538Srpaulo int mlen, ntries, page, error; 2298251538Srpaulo 2299264864Skevlo URTWN_UNLOCK(sc); 2300251538Srpaulo /* Read firmware image from the filesystem. */ 2301264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2302264912Skevlo imagename = "urtwn-rtl8188eufw"; 2303264912Skevlo else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2304264912Skevlo URTWN_CHIP_UMC_A_CUT) 2305251538Srpaulo imagename = "urtwn-rtl8192cfwU"; 2306251538Srpaulo else 2307251538Srpaulo imagename = "urtwn-rtl8192cfwT"; 2308251538Srpaulo 2309251538Srpaulo fw = firmware_get(imagename); 2310264864Skevlo URTWN_LOCK(sc); 2311251538Srpaulo if (fw == NULL) { 2312251538Srpaulo device_printf(sc->sc_dev, 2313251538Srpaulo "failed loadfirmware of file %s\n", imagename); 2314251538Srpaulo return (ENOENT); 2315251538Srpaulo } 2316251538Srpaulo 2317251538Srpaulo len = fw->datasize; 2318251538Srpaulo 2319251538Srpaulo if (len < sizeof(*hdr)) { 2320251538Srpaulo device_printf(sc->sc_dev, "firmware too short\n"); 2321251538Srpaulo error = EINVAL; 2322251538Srpaulo goto fail; 2323251538Srpaulo } 2324251538Srpaulo ptr = fw->data; 2325251538Srpaulo hdr = (const struct r92c_fw_hdr *)ptr; 2326251538Srpaulo /* Check if there is a valid FW header and skip it. */ 2327251538Srpaulo if ((le16toh(hdr->signature) >> 4) == 0x88c || 2328264912Skevlo (le16toh(hdr->signature) >> 4) == 0x88e || 2329251538Srpaulo (le16toh(hdr->signature) >> 4) == 0x92c) { 2330251538Srpaulo DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2331251538Srpaulo le16toh(hdr->version), le16toh(hdr->subversion), 2332251538Srpaulo hdr->month, hdr->date, hdr->hour, hdr->minute); 2333251538Srpaulo ptr += sizeof(*hdr); 2334251538Srpaulo len -= sizeof(*hdr); 2335251538Srpaulo } 2336251538Srpaulo 2337264912Skevlo if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2338264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2339264912Skevlo urtwn_r88e_fw_reset(sc); 2340264912Skevlo else 2341264912Skevlo urtwn_fw_reset(sc); 2342251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 0); 2343251538Srpaulo } 2344264912Skevlo 2345268487Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2346268487Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2347268487Skevlo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2348268487Skevlo R92C_SYS_FUNC_EN_CPUEN); 2349268487Skevlo } 2350251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2351251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2352251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 2, 2353251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2354251538Srpaulo 2355263154Skevlo /* Reset the FWDL checksum. */ 2356263154Skevlo urtwn_write_1(sc, R92C_MCUFWDL, 2357263154Skevlo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2358263154Skevlo 2359251538Srpaulo for (page = 0; len > 0; page++) { 2360251538Srpaulo mlen = min(len, R92C_FW_PAGE_SIZE); 2361251538Srpaulo error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2362251538Srpaulo if (error != 0) { 2363251538Srpaulo device_printf(sc->sc_dev, 2364251538Srpaulo "could not load firmware page\n"); 2365251538Srpaulo goto fail; 2366251538Srpaulo } 2367251538Srpaulo ptr += mlen; 2368251538Srpaulo len -= mlen; 2369251538Srpaulo } 2370251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2371251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2372251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2373251538Srpaulo 2374251538Srpaulo /* Wait for checksum report. */ 2375251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2376251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2377251538Srpaulo break; 2378266472Shselasky urtwn_ms_delay(sc); 2379251538Srpaulo } 2380251538Srpaulo if (ntries == 1000) { 2381251538Srpaulo device_printf(sc->sc_dev, 2382251538Srpaulo "timeout waiting for checksum report\n"); 2383251538Srpaulo error = ETIMEDOUT; 2384251538Srpaulo goto fail; 2385251538Srpaulo } 2386251538Srpaulo 2387251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2388251538Srpaulo reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2389251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2390264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2391264912Skevlo urtwn_r88e_fw_reset(sc); 2392251538Srpaulo /* Wait for firmware readiness. */ 2393251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2394251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2395251538Srpaulo break; 2396266472Shselasky urtwn_ms_delay(sc); 2397251538Srpaulo } 2398251538Srpaulo if (ntries == 1000) { 2399251538Srpaulo device_printf(sc->sc_dev, 2400251538Srpaulo "timeout waiting for firmware readiness\n"); 2401251538Srpaulo error = ETIMEDOUT; 2402251538Srpaulo goto fail; 2403251538Srpaulo } 2404251538Srpaulofail: 2405251538Srpaulo firmware_put(fw, FIRMWARE_UNLOAD); 2406251538Srpaulo return (error); 2407251538Srpaulo} 2408251538Srpaulo 2409264912Skevlostatic __inline int 2410251538Srpaulourtwn_dma_init(struct urtwn_softc *sc) 2411251538Srpaulo{ 2412281069Srpaulo 2413264912Skevlo return sc->sc_dma_init(sc); 2414264912Skevlo} 2415264912Skevlo 2416264912Skevlostatic int 2417264912Skevlourtwn_r92c_dma_init(struct urtwn_softc *sc) 2418264912Skevlo{ 2419251538Srpaulo int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2420251538Srpaulo uint32_t reg; 2421251538Srpaulo int error; 2422251538Srpaulo 2423251538Srpaulo /* Initialize LLT table. */ 2424251538Srpaulo error = urtwn_llt_init(sc); 2425251538Srpaulo if (error != 0) 2426251538Srpaulo return (error); 2427251538Srpaulo 2428251538Srpaulo /* Get Tx queues to USB endpoints mapping. */ 2429251538Srpaulo hashq = hasnq = haslq = 0; 2430251538Srpaulo reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2431251538Srpaulo DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2432251538Srpaulo if (MS(reg, R92C_USB_EP_HQ) != 0) 2433251538Srpaulo hashq = 1; 2434251538Srpaulo if (MS(reg, R92C_USB_EP_NQ) != 0) 2435251538Srpaulo hasnq = 1; 2436251538Srpaulo if (MS(reg, R92C_USB_EP_LQ) != 0) 2437251538Srpaulo haslq = 1; 2438251538Srpaulo nqueues = hashq + hasnq + haslq; 2439251538Srpaulo if (nqueues == 0) 2440251538Srpaulo return (EIO); 2441251538Srpaulo /* Get the number of pages for each queue. */ 2442251538Srpaulo nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2443251538Srpaulo /* The remaining pages are assigned to the high priority queue. */ 2444251538Srpaulo nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2445251538Srpaulo 2446251538Srpaulo /* Set number of pages for normal priority queue. */ 2447251538Srpaulo urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2448251538Srpaulo urtwn_write_4(sc, R92C_RQPN, 2449251538Srpaulo /* Set number of pages for public queue. */ 2450251538Srpaulo SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2451251538Srpaulo /* Set number of pages for high priority queue. */ 2452251538Srpaulo SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2453251538Srpaulo /* Set number of pages for low priority queue. */ 2454251538Srpaulo SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2455251538Srpaulo /* Load values. */ 2456251538Srpaulo R92C_RQPN_LD); 2457251538Srpaulo 2458251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2459251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2460251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2461251538Srpaulo urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2462251538Srpaulo urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2463251538Srpaulo 2464251538Srpaulo /* Set queue to USB pipe mapping. */ 2465251538Srpaulo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2466251538Srpaulo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2467251538Srpaulo if (nqueues == 1) { 2468251538Srpaulo if (hashq) 2469251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2470251538Srpaulo else if (hasnq) 2471251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2472251538Srpaulo else 2473251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2474251538Srpaulo } else if (nqueues == 2) { 2475251538Srpaulo /* All 2-endpoints configs have a high priority queue. */ 2476251538Srpaulo if (!hashq) 2477251538Srpaulo return (EIO); 2478251538Srpaulo if (hasnq) 2479251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2480251538Srpaulo else 2481251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2482251538Srpaulo } else 2483251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2484251538Srpaulo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2485251538Srpaulo 2486251538Srpaulo /* Set Tx/Rx transfer page boundary. */ 2487251538Srpaulo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2488251538Srpaulo 2489251538Srpaulo /* Set Tx/Rx transfer page size. */ 2490251538Srpaulo urtwn_write_1(sc, R92C_PBP, 2491251538Srpaulo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2492251538Srpaulo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2493251538Srpaulo return (0); 2494251538Srpaulo} 2495251538Srpaulo 2496264912Skevlostatic int 2497264912Skevlourtwn_r88e_dma_init(struct urtwn_softc *sc) 2498264912Skevlo{ 2499264912Skevlo struct usb_interface *iface; 2500264912Skevlo uint32_t reg; 2501264912Skevlo int nqueues; 2502264912Skevlo int error; 2503264912Skevlo 2504264912Skevlo /* Initialize LLT table. */ 2505264912Skevlo error = urtwn_llt_init(sc); 2506264912Skevlo if (error != 0) 2507264912Skevlo return (error); 2508264912Skevlo 2509264912Skevlo /* Get Tx queues to USB endpoints mapping. */ 2510264912Skevlo iface = usbd_get_iface(sc->sc_udev, 0); 2511264912Skevlo nqueues = iface->idesc->bNumEndpoints - 1; 2512264912Skevlo if (nqueues == 0) 2513264912Skevlo return (EIO); 2514264912Skevlo 2515264912Skevlo /* Set number of pages for normal priority queue. */ 2516264912Skevlo urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2517264912Skevlo urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2518264912Skevlo 2519264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2520264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2521264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2522264912Skevlo urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2523264912Skevlo urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2524264912Skevlo 2525264912Skevlo /* Set queue to USB pipe mapping. */ 2526264912Skevlo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2527264912Skevlo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2528264912Skevlo if (nqueues == 1) 2529264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2530264912Skevlo else if (nqueues == 2) 2531264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2532264912Skevlo else 2533264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2534264912Skevlo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2535264912Skevlo 2536264912Skevlo /* Set Tx/Rx transfer page boundary. */ 2537264912Skevlo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2538264912Skevlo 2539264912Skevlo /* Set Tx/Rx transfer page size. */ 2540264912Skevlo urtwn_write_1(sc, R92C_PBP, 2541264912Skevlo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2542264912Skevlo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2543264912Skevlo 2544264912Skevlo return (0); 2545264912Skevlo} 2546264912Skevlo 2547251538Srpaulostatic void 2548251538Srpaulourtwn_mac_init(struct urtwn_softc *sc) 2549251538Srpaulo{ 2550251538Srpaulo int i; 2551251538Srpaulo 2552251538Srpaulo /* Write MAC initialization values. */ 2553264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2554264912Skevlo for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2555264912Skevlo urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2556264912Skevlo rtl8188eu_mac[i].val); 2557264912Skevlo } 2558264912Skevlo urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2559264912Skevlo } else { 2560264912Skevlo for (i = 0; i < nitems(rtl8192cu_mac); i++) 2561264912Skevlo urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2562264912Skevlo rtl8192cu_mac[i].val); 2563264912Skevlo } 2564251538Srpaulo} 2565251538Srpaulo 2566251538Srpaulostatic void 2567251538Srpaulourtwn_bb_init(struct urtwn_softc *sc) 2568251538Srpaulo{ 2569251538Srpaulo const struct urtwn_bb_prog *prog; 2570251538Srpaulo uint32_t reg; 2571264912Skevlo uint8_t crystalcap; 2572251538Srpaulo int i; 2573251538Srpaulo 2574251538Srpaulo /* Enable BB and RF. */ 2575251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2576251538Srpaulo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2577251538Srpaulo R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2578251538Srpaulo R92C_SYS_FUNC_EN_DIO_RF); 2579251538Srpaulo 2580264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 2581264912Skevlo urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2582251538Srpaulo 2583251538Srpaulo urtwn_write_1(sc, R92C_RF_CTRL, 2584251538Srpaulo R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2585251538Srpaulo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2586251538Srpaulo R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2587251538Srpaulo R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2588251538Srpaulo 2589264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2590264912Skevlo urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2591264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 2592264912Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2593264912Skevlo } 2594251538Srpaulo 2595251538Srpaulo /* Select BB programming based on board type. */ 2596264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2597264912Skevlo prog = &rtl8188eu_bb_prog; 2598264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2599251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2600251538Srpaulo prog = &rtl8188ce_bb_prog; 2601251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2602251538Srpaulo prog = &rtl8188ru_bb_prog; 2603251538Srpaulo else 2604251538Srpaulo prog = &rtl8188cu_bb_prog; 2605251538Srpaulo } else { 2606251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2607251538Srpaulo prog = &rtl8192ce_bb_prog; 2608251538Srpaulo else 2609251538Srpaulo prog = &rtl8192cu_bb_prog; 2610251538Srpaulo } 2611251538Srpaulo /* Write BB initialization values. */ 2612251538Srpaulo for (i = 0; i < prog->count; i++) { 2613251538Srpaulo urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2614266472Shselasky urtwn_ms_delay(sc); 2615251538Srpaulo } 2616251538Srpaulo 2617251538Srpaulo if (sc->chip & URTWN_CHIP_92C_1T2R) { 2618251538Srpaulo /* 8192C 1T only configuration. */ 2619251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2620251538Srpaulo reg = (reg & ~0x00000003) | 0x2; 2621251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2622251538Srpaulo 2623251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2624251538Srpaulo reg = (reg & ~0x00300033) | 0x00200022; 2625251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2626251538Srpaulo 2627251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2628251538Srpaulo reg = (reg & ~0xff000000) | 0x45 << 24; 2629251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2630251538Srpaulo 2631251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2632251538Srpaulo reg = (reg & ~0x000000ff) | 0x23; 2633251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2634251538Srpaulo 2635251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2636251538Srpaulo reg = (reg & ~0x00000030) | 1 << 4; 2637251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2638251538Srpaulo 2639251538Srpaulo reg = urtwn_bb_read(sc, 0xe74); 2640251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2641251538Srpaulo urtwn_bb_write(sc, 0xe74, reg); 2642251538Srpaulo reg = urtwn_bb_read(sc, 0xe78); 2643251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2644251538Srpaulo urtwn_bb_write(sc, 0xe78, reg); 2645251538Srpaulo reg = urtwn_bb_read(sc, 0xe7c); 2646251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2647251538Srpaulo urtwn_bb_write(sc, 0xe7c, reg); 2648251538Srpaulo reg = urtwn_bb_read(sc, 0xe80); 2649251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2650251538Srpaulo urtwn_bb_write(sc, 0xe80, reg); 2651251538Srpaulo reg = urtwn_bb_read(sc, 0xe88); 2652251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2653251538Srpaulo urtwn_bb_write(sc, 0xe88, reg); 2654251538Srpaulo } 2655251538Srpaulo 2656251538Srpaulo /* Write AGC values. */ 2657251538Srpaulo for (i = 0; i < prog->agccount; i++) { 2658251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2659251538Srpaulo prog->agcvals[i]); 2660266472Shselasky urtwn_ms_delay(sc); 2661251538Srpaulo } 2662251538Srpaulo 2663264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2664264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2665266472Shselasky urtwn_ms_delay(sc); 2666264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2667266472Shselasky urtwn_ms_delay(sc); 2668264912Skevlo 2669264912Skevlo crystalcap = sc->r88e_rom[0xb9]; 2670264912Skevlo if (crystalcap == 0xff) 2671264912Skevlo crystalcap = 0x20; 2672264912Skevlo crystalcap &= 0x3f; 2673264912Skevlo reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2674264912Skevlo urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2675264912Skevlo RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2676264912Skevlo crystalcap | crystalcap << 6)); 2677264912Skevlo } else { 2678264912Skevlo if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2679264912Skevlo R92C_HSSI_PARAM2_CCK_HIPWR) 2680264912Skevlo sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2681264912Skevlo } 2682251538Srpaulo} 2683251538Srpaulo 2684289066Skevlostatic void 2685251538Srpaulourtwn_rf_init(struct urtwn_softc *sc) 2686251538Srpaulo{ 2687251538Srpaulo const struct urtwn_rf_prog *prog; 2688251538Srpaulo uint32_t reg, type; 2689251538Srpaulo int i, j, idx, off; 2690251538Srpaulo 2691251538Srpaulo /* Select RF programming based on board type. */ 2692264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2693264912Skevlo prog = rtl8188eu_rf_prog; 2694264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2695251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2696251538Srpaulo prog = rtl8188ce_rf_prog; 2697251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2698251538Srpaulo prog = rtl8188ru_rf_prog; 2699251538Srpaulo else 2700251538Srpaulo prog = rtl8188cu_rf_prog; 2701251538Srpaulo } else 2702251538Srpaulo prog = rtl8192ce_rf_prog; 2703251538Srpaulo 2704251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2705251538Srpaulo /* Save RF_ENV control type. */ 2706251538Srpaulo idx = i / 2; 2707251538Srpaulo off = (i % 2) * 16; 2708251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2709251538Srpaulo type = (reg >> off) & 0x10; 2710251538Srpaulo 2711251538Srpaulo /* Set RF_ENV enable. */ 2712251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2713251538Srpaulo reg |= 0x100000; 2714251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2715266472Shselasky urtwn_ms_delay(sc); 2716251538Srpaulo /* Set RF_ENV output high. */ 2717251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2718251538Srpaulo reg |= 0x10; 2719251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2720266472Shselasky urtwn_ms_delay(sc); 2721251538Srpaulo /* Set address and data lengths of RF registers. */ 2722251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2723251538Srpaulo reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2724251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2725266472Shselasky urtwn_ms_delay(sc); 2726251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2727251538Srpaulo reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2728251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2729266472Shselasky urtwn_ms_delay(sc); 2730251538Srpaulo 2731251538Srpaulo /* Write RF initialization values for this chain. */ 2732251538Srpaulo for (j = 0; j < prog[i].count; j++) { 2733251538Srpaulo if (prog[i].regs[j] >= 0xf9 && 2734251538Srpaulo prog[i].regs[j] <= 0xfe) { 2735251538Srpaulo /* 2736251538Srpaulo * These are fake RF registers offsets that 2737251538Srpaulo * indicate a delay is required. 2738251538Srpaulo */ 2739266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2740251538Srpaulo continue; 2741251538Srpaulo } 2742251538Srpaulo urtwn_rf_write(sc, i, prog[i].regs[j], 2743251538Srpaulo prog[i].vals[j]); 2744266472Shselasky urtwn_ms_delay(sc); 2745251538Srpaulo } 2746251538Srpaulo 2747251538Srpaulo /* Restore RF_ENV control type. */ 2748251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2749251538Srpaulo reg &= ~(0x10 << off) | (type << off); 2750251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2751251538Srpaulo 2752251538Srpaulo /* Cache RF register CHNLBW. */ 2753251538Srpaulo sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2754251538Srpaulo } 2755251538Srpaulo 2756251538Srpaulo if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2757251538Srpaulo URTWN_CHIP_UMC_A_CUT) { 2758251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2759251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2760251538Srpaulo } 2761251538Srpaulo} 2762251538Srpaulo 2763251538Srpaulostatic void 2764251538Srpaulourtwn_cam_init(struct urtwn_softc *sc) 2765251538Srpaulo{ 2766251538Srpaulo /* Invalidate all CAM entries. */ 2767251538Srpaulo urtwn_write_4(sc, R92C_CAMCMD, 2768251538Srpaulo R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2769251538Srpaulo} 2770251538Srpaulo 2771251538Srpaulostatic void 2772251538Srpaulourtwn_pa_bias_init(struct urtwn_softc *sc) 2773251538Srpaulo{ 2774251538Srpaulo uint8_t reg; 2775251538Srpaulo int i; 2776251538Srpaulo 2777251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2778251538Srpaulo if (sc->pa_setting & (1 << i)) 2779251538Srpaulo continue; 2780251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2781251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2782251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2783251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2784251538Srpaulo } 2785251538Srpaulo if (!(sc->pa_setting & 0x10)) { 2786251538Srpaulo reg = urtwn_read_1(sc, 0x16); 2787251538Srpaulo reg = (reg & ~0xf0) | 0x90; 2788251538Srpaulo urtwn_write_1(sc, 0x16, reg); 2789251538Srpaulo } 2790251538Srpaulo} 2791251538Srpaulo 2792251538Srpaulostatic void 2793251538Srpaulourtwn_rxfilter_init(struct urtwn_softc *sc) 2794251538Srpaulo{ 2795251538Srpaulo /* Initialize Rx filter. */ 2796251538Srpaulo /* TODO: use better filter for monitor mode. */ 2797251538Srpaulo urtwn_write_4(sc, R92C_RCR, 2798251538Srpaulo R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2799251538Srpaulo R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2800251538Srpaulo R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2801251538Srpaulo /* Accept all multicast frames. */ 2802251538Srpaulo urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2803251538Srpaulo urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2804251538Srpaulo /* Accept all management frames. */ 2805251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2806251538Srpaulo /* Reject all control frames. */ 2807251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2808251538Srpaulo /* Accept all data frames. */ 2809251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2810251538Srpaulo} 2811251538Srpaulo 2812251538Srpaulostatic void 2813251538Srpaulourtwn_edca_init(struct urtwn_softc *sc) 2814251538Srpaulo{ 2815251538Srpaulo urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2816251538Srpaulo urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2817251538Srpaulo urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2818251538Srpaulo urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2819251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2820251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2821251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2822251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2823251538Srpaulo} 2824251538Srpaulo 2825289066Skevlostatic void 2826251538Srpaulourtwn_write_txpower(struct urtwn_softc *sc, int chain, 2827251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2828251538Srpaulo{ 2829251538Srpaulo uint32_t reg; 2830251538Srpaulo 2831251538Srpaulo /* Write per-CCK rate Tx power. */ 2832251538Srpaulo if (chain == 0) { 2833251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2834251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2835251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2836251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2837251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2838251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2839251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2840251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2841251538Srpaulo } else { 2842251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2843251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2844251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2845251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2846251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2847251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2848251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2849251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2850251538Srpaulo } 2851251538Srpaulo /* Write per-OFDM rate Tx power. */ 2852251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2853251538Srpaulo SM(R92C_TXAGC_RATE06, power[ 4]) | 2854251538Srpaulo SM(R92C_TXAGC_RATE09, power[ 5]) | 2855251538Srpaulo SM(R92C_TXAGC_RATE12, power[ 6]) | 2856251538Srpaulo SM(R92C_TXAGC_RATE18, power[ 7])); 2857251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2858251538Srpaulo SM(R92C_TXAGC_RATE24, power[ 8]) | 2859251538Srpaulo SM(R92C_TXAGC_RATE36, power[ 9]) | 2860251538Srpaulo SM(R92C_TXAGC_RATE48, power[10]) | 2861251538Srpaulo SM(R92C_TXAGC_RATE54, power[11])); 2862251538Srpaulo /* Write per-MCS Tx power. */ 2863251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2864251538Srpaulo SM(R92C_TXAGC_MCS00, power[12]) | 2865251538Srpaulo SM(R92C_TXAGC_MCS01, power[13]) | 2866251538Srpaulo SM(R92C_TXAGC_MCS02, power[14]) | 2867251538Srpaulo SM(R92C_TXAGC_MCS03, power[15])); 2868251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2869251538Srpaulo SM(R92C_TXAGC_MCS04, power[16]) | 2870251538Srpaulo SM(R92C_TXAGC_MCS05, power[17]) | 2871251538Srpaulo SM(R92C_TXAGC_MCS06, power[18]) | 2872251538Srpaulo SM(R92C_TXAGC_MCS07, power[19])); 2873251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2874251538Srpaulo SM(R92C_TXAGC_MCS08, power[20]) | 2875261506Skevlo SM(R92C_TXAGC_MCS09, power[21]) | 2876251538Srpaulo SM(R92C_TXAGC_MCS10, power[22]) | 2877251538Srpaulo SM(R92C_TXAGC_MCS11, power[23])); 2878251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2879251538Srpaulo SM(R92C_TXAGC_MCS12, power[24]) | 2880251538Srpaulo SM(R92C_TXAGC_MCS13, power[25]) | 2881251538Srpaulo SM(R92C_TXAGC_MCS14, power[26]) | 2882251538Srpaulo SM(R92C_TXAGC_MCS15, power[27])); 2883251538Srpaulo} 2884251538Srpaulo 2885289066Skevlostatic void 2886251538Srpaulourtwn_get_txpower(struct urtwn_softc *sc, int chain, 2887251538Srpaulo struct ieee80211_channel *c, struct ieee80211_channel *extc, 2888251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2889251538Srpaulo{ 2890287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 2891251538Srpaulo struct r92c_rom *rom = &sc->rom; 2892251538Srpaulo uint16_t cckpow, ofdmpow, htpow, diff, max; 2893251538Srpaulo const struct urtwn_txpwr *base; 2894251538Srpaulo int ridx, chan, group; 2895251538Srpaulo 2896251538Srpaulo /* Determine channel group. */ 2897251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2898251538Srpaulo if (chan <= 3) 2899251538Srpaulo group = 0; 2900251538Srpaulo else if (chan <= 9) 2901251538Srpaulo group = 1; 2902251538Srpaulo else 2903251538Srpaulo group = 2; 2904251538Srpaulo 2905251538Srpaulo /* Get original Tx power based on board type and RF chain. */ 2906251538Srpaulo if (!(sc->chip & URTWN_CHIP_92C)) { 2907251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2908251538Srpaulo base = &rtl8188ru_txagc[chain]; 2909251538Srpaulo else 2910251538Srpaulo base = &rtl8192cu_txagc[chain]; 2911251538Srpaulo } else 2912251538Srpaulo base = &rtl8192cu_txagc[chain]; 2913251538Srpaulo 2914251538Srpaulo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2915251538Srpaulo if (sc->regulatory == 0) { 2916289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 2917251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2918251538Srpaulo } 2919289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 2920251538Srpaulo if (sc->regulatory == 3) { 2921251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2922251538Srpaulo /* Apply vendor limits. */ 2923251538Srpaulo if (extc != NULL) 2924251538Srpaulo max = rom->ht40_max_pwr[group]; 2925251538Srpaulo else 2926251538Srpaulo max = rom->ht20_max_pwr[group]; 2927251538Srpaulo max = (max >> (chain * 4)) & 0xf; 2928251538Srpaulo if (power[ridx] > max) 2929251538Srpaulo power[ridx] = max; 2930251538Srpaulo } else if (sc->regulatory == 1) { 2931251538Srpaulo if (extc == NULL) 2932251538Srpaulo power[ridx] = base->pwr[group][ridx]; 2933251538Srpaulo } else if (sc->regulatory != 2) 2934251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2935251538Srpaulo } 2936251538Srpaulo 2937251538Srpaulo /* Compute per-CCK rate Tx power. */ 2938251538Srpaulo cckpow = rom->cck_tx_pwr[chain][group]; 2939289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 2940251538Srpaulo power[ridx] += cckpow; 2941251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2942251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2943251538Srpaulo } 2944251538Srpaulo 2945251538Srpaulo htpow = rom->ht40_1s_tx_pwr[chain][group]; 2946251538Srpaulo if (sc->ntxchains > 1) { 2947251538Srpaulo /* Apply reduction for 2 spatial streams. */ 2948251538Srpaulo diff = rom->ht40_2s_tx_pwr_diff[group]; 2949251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2950251538Srpaulo htpow = (htpow > diff) ? htpow - diff : 0; 2951251538Srpaulo } 2952251538Srpaulo 2953251538Srpaulo /* Compute per-OFDM rate Tx power. */ 2954251538Srpaulo diff = rom->ofdm_tx_pwr_diff[group]; 2955251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2956251538Srpaulo ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2957289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 2958251538Srpaulo power[ridx] += ofdmpow; 2959251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2960251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2961251538Srpaulo } 2962251538Srpaulo 2963251538Srpaulo /* Compute per-MCS Tx power. */ 2964251538Srpaulo if (extc == NULL) { 2965251538Srpaulo diff = rom->ht20_tx_pwr_diff[group]; 2966251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2967251538Srpaulo htpow += diff; /* HT40->HT20 correction. */ 2968251538Srpaulo } 2969251538Srpaulo for (ridx = 12; ridx <= 27; ridx++) { 2970251538Srpaulo power[ridx] += htpow; 2971251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2972251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2973251538Srpaulo } 2974251538Srpaulo#ifdef URTWN_DEBUG 2975251538Srpaulo if (urtwn_debug >= 4) { 2976251538Srpaulo /* Dump per-rate Tx power values. */ 2977251538Srpaulo printf("Tx power for chain %d:\n", chain); 2978289758Savos for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 2979251538Srpaulo printf("Rate %d = %u\n", ridx, power[ridx]); 2980251538Srpaulo } 2981251538Srpaulo#endif 2982251538Srpaulo} 2983251538Srpaulo 2984289066Skevlostatic void 2985264912Skevlourtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 2986264912Skevlo struct ieee80211_channel *c, struct ieee80211_channel *extc, 2987264912Skevlo uint16_t power[URTWN_RIDX_COUNT]) 2988264912Skevlo{ 2989287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 2990264912Skevlo uint16_t cckpow, ofdmpow, bw20pow, htpow; 2991264912Skevlo const struct urtwn_r88e_txpwr *base; 2992264912Skevlo int ridx, chan, group; 2993264912Skevlo 2994264912Skevlo /* Determine channel group. */ 2995264912Skevlo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2996264912Skevlo if (chan <= 2) 2997264912Skevlo group = 0; 2998264912Skevlo else if (chan <= 5) 2999264912Skevlo group = 1; 3000264912Skevlo else if (chan <= 8) 3001264912Skevlo group = 2; 3002264912Skevlo else if (chan <= 11) 3003264912Skevlo group = 3; 3004264912Skevlo else if (chan <= 13) 3005264912Skevlo group = 4; 3006264912Skevlo else 3007264912Skevlo group = 5; 3008264912Skevlo 3009264912Skevlo /* Get original Tx power based on board type and RF chain. */ 3010264912Skevlo base = &rtl8188eu_txagc[chain]; 3011264912Skevlo 3012264912Skevlo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3013264912Skevlo if (sc->regulatory == 0) { 3014289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3015264912Skevlo power[ridx] = base->pwr[0][ridx]; 3016264912Skevlo } 3017289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3018264912Skevlo if (sc->regulatory == 3) 3019264912Skevlo power[ridx] = base->pwr[0][ridx]; 3020264912Skevlo else if (sc->regulatory == 1) { 3021264912Skevlo if (extc == NULL) 3022264912Skevlo power[ridx] = base->pwr[group][ridx]; 3023264912Skevlo } else if (sc->regulatory != 2) 3024264912Skevlo power[ridx] = base->pwr[0][ridx]; 3025264912Skevlo } 3026264912Skevlo 3027264912Skevlo /* Compute per-CCK rate Tx power. */ 3028264912Skevlo cckpow = sc->cck_tx_pwr[group]; 3029289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3030264912Skevlo power[ridx] += cckpow; 3031264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3032264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3033264912Skevlo } 3034264912Skevlo 3035264912Skevlo htpow = sc->ht40_tx_pwr[group]; 3036264912Skevlo 3037264912Skevlo /* Compute per-OFDM rate Tx power. */ 3038264912Skevlo ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3039289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3040264912Skevlo power[ridx] += ofdmpow; 3041264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3042264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3043264912Skevlo } 3044264912Skevlo 3045264912Skevlo bw20pow = htpow + sc->bw20_tx_pwr_diff; 3046264912Skevlo for (ridx = 12; ridx <= 27; ridx++) { 3047264912Skevlo power[ridx] += bw20pow; 3048264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3049264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3050264912Skevlo } 3051264912Skevlo} 3052264912Skevlo 3053289066Skevlostatic void 3054251538Srpaulourtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3055251538Srpaulo struct ieee80211_channel *extc) 3056251538Srpaulo{ 3057251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]; 3058251538Srpaulo int i; 3059251538Srpaulo 3060251538Srpaulo for (i = 0; i < sc->ntxchains; i++) { 3061251538Srpaulo /* Compute per-rate Tx power values. */ 3062264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3063264912Skevlo urtwn_r88e_get_txpower(sc, i, c, extc, power); 3064264912Skevlo else 3065264912Skevlo urtwn_get_txpower(sc, i, c, extc, power); 3066251538Srpaulo /* Write per-rate Tx power values to hardware. */ 3067251538Srpaulo urtwn_write_txpower(sc, i, power); 3068251538Srpaulo } 3069251538Srpaulo} 3070251538Srpaulo 3071251538Srpaulostatic void 3072251538Srpaulourtwn_scan_start(struct ieee80211com *ic) 3073251538Srpaulo{ 3074251538Srpaulo /* XXX do nothing? */ 3075251538Srpaulo} 3076251538Srpaulo 3077251538Srpaulostatic void 3078251538Srpaulourtwn_scan_end(struct ieee80211com *ic) 3079251538Srpaulo{ 3080251538Srpaulo /* XXX do nothing? */ 3081251538Srpaulo} 3082251538Srpaulo 3083251538Srpaulostatic void 3084251538Srpaulourtwn_set_channel(struct ieee80211com *ic) 3085251538Srpaulo{ 3086286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 3087281070Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3088251538Srpaulo 3089251538Srpaulo URTWN_LOCK(sc); 3090281070Srpaulo if (vap->iv_state == IEEE80211_S_SCAN) { 3091281070Srpaulo /* Make link LED blink during scan. */ 3092281070Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3093281070Srpaulo } 3094251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 3095251538Srpaulo URTWN_UNLOCK(sc); 3096251538Srpaulo} 3097251538Srpaulo 3098251538Srpaulostatic void 3099283540Sglebiusurtwn_update_mcast(struct ieee80211com *ic) 3100251538Srpaulo{ 3101251538Srpaulo /* XXX do nothing? */ 3102251538Srpaulo} 3103251538Srpaulo 3104251538Srpaulostatic void 3105251538Srpaulourtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3106251538Srpaulo struct ieee80211_channel *extc) 3107251538Srpaulo{ 3108287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3109251538Srpaulo uint32_t reg; 3110251538Srpaulo u_int chan; 3111251538Srpaulo int i; 3112251538Srpaulo 3113251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3114251538Srpaulo if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3115251538Srpaulo device_printf(sc->sc_dev, 3116251538Srpaulo "%s: invalid channel %x\n", __func__, chan); 3117251538Srpaulo return; 3118251538Srpaulo } 3119251538Srpaulo 3120251538Srpaulo /* Set Tx power for this new channel. */ 3121251538Srpaulo urtwn_set_txpower(sc, c, extc); 3122251538Srpaulo 3123251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3124251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3125251538Srpaulo RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3126251538Srpaulo } 3127251538Srpaulo#ifndef IEEE80211_NO_HT 3128251538Srpaulo if (extc != NULL) { 3129251538Srpaulo /* Is secondary channel below or above primary? */ 3130251538Srpaulo int prichlo = c->ic_freq < extc->ic_freq; 3131251538Srpaulo 3132251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3133251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3134251538Srpaulo 3135251538Srpaulo reg = urtwn_read_1(sc, R92C_RRSR + 2); 3136251538Srpaulo reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3137251538Srpaulo urtwn_write_1(sc, R92C_RRSR + 2, reg); 3138251538Srpaulo 3139251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3140251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3141251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3142251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3143251538Srpaulo 3144251538Srpaulo /* Set CCK side band. */ 3145251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3146251538Srpaulo reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3147251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3148251538Srpaulo 3149251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3150251538Srpaulo reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3151251538Srpaulo urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3152251538Srpaulo 3153251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3154251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3155251538Srpaulo ~R92C_FPGA0_ANAPARAM2_CBW20); 3156251538Srpaulo 3157251538Srpaulo reg = urtwn_bb_read(sc, 0x818); 3158251538Srpaulo reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3159251538Srpaulo urtwn_bb_write(sc, 0x818, reg); 3160251538Srpaulo 3161251538Srpaulo /* Select 40MHz bandwidth. */ 3162251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3163251538Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan); 3164251538Srpaulo } else 3165251538Srpaulo#endif 3166251538Srpaulo { 3167251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3168251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3169251538Srpaulo 3170251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3171251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3172251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3173251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3174251538Srpaulo 3175264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3176264912Skevlo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3177264912Skevlo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3178264912Skevlo R92C_FPGA0_ANAPARAM2_CBW20); 3179264912Skevlo } 3180281069Srpaulo 3181251538Srpaulo /* Select 20MHz bandwidth. */ 3182251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3183281069Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan | 3184264912Skevlo ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3185264912Skevlo R92C_RF_CHNLBW_BW20)); 3186251538Srpaulo } 3187251538Srpaulo} 3188251538Srpaulo 3189251538Srpaulostatic void 3190251538Srpaulourtwn_iq_calib(struct urtwn_softc *sc) 3191251538Srpaulo{ 3192251538Srpaulo /* TODO */ 3193251538Srpaulo} 3194251538Srpaulo 3195251538Srpaulostatic void 3196251538Srpaulourtwn_lc_calib(struct urtwn_softc *sc) 3197251538Srpaulo{ 3198251538Srpaulo uint32_t rf_ac[2]; 3199251538Srpaulo uint8_t txmode; 3200251538Srpaulo int i; 3201251538Srpaulo 3202251538Srpaulo txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3203251538Srpaulo if ((txmode & 0x70) != 0) { 3204251538Srpaulo /* Disable all continuous Tx. */ 3205251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3206251538Srpaulo 3207251538Srpaulo /* Set RF mode to standby mode. */ 3208251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3209251538Srpaulo rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3210251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, 3211251538Srpaulo RW(rf_ac[i], R92C_RF_AC_MODE, 3212251538Srpaulo R92C_RF_AC_MODE_STANDBY)); 3213251538Srpaulo } 3214251538Srpaulo } else { 3215251538Srpaulo /* Block all Tx queues. */ 3216251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3217251538Srpaulo } 3218251538Srpaulo /* Start calibration. */ 3219251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3220251538Srpaulo urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3221251538Srpaulo 3222251538Srpaulo /* Give calibration the time to complete. */ 3223266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3224251538Srpaulo 3225251538Srpaulo /* Restore configuration. */ 3226251538Srpaulo if ((txmode & 0x70) != 0) { 3227251538Srpaulo /* Restore Tx mode. */ 3228251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3229251538Srpaulo /* Restore RF mode. */ 3230251538Srpaulo for (i = 0; i < sc->nrxchains; i++) 3231251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3232251538Srpaulo } else { 3233251538Srpaulo /* Unblock all Tx queues. */ 3234251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3235251538Srpaulo } 3236251538Srpaulo} 3237251538Srpaulo 3238251538Srpaulostatic void 3239287197Sglebiusurtwn_init(struct urtwn_softc *sc) 3240251538Srpaulo{ 3241287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3242287197Sglebius struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3243287197Sglebius uint8_t macaddr[IEEE80211_ADDR_LEN]; 3244251538Srpaulo uint32_t reg; 3245251538Srpaulo int error; 3246251538Srpaulo 3247264864Skevlo URTWN_ASSERT_LOCKED(sc); 3248264864Skevlo 3249287197Sglebius if (sc->sc_flags & URTWN_RUNNING) 3250287197Sglebius urtwn_stop(sc); 3251251538Srpaulo 3252251538Srpaulo /* Init firmware commands ring. */ 3253251538Srpaulo sc->fwcur = 0; 3254251538Srpaulo 3255251538Srpaulo /* Allocate Tx/Rx buffers. */ 3256251538Srpaulo error = urtwn_alloc_rx_list(sc); 3257251538Srpaulo if (error != 0) 3258251538Srpaulo goto fail; 3259281069Srpaulo 3260251538Srpaulo error = urtwn_alloc_tx_list(sc); 3261251538Srpaulo if (error != 0) 3262251538Srpaulo goto fail; 3263251538Srpaulo 3264251538Srpaulo /* Power on adapter. */ 3265251538Srpaulo error = urtwn_power_on(sc); 3266251538Srpaulo if (error != 0) 3267251538Srpaulo goto fail; 3268251538Srpaulo 3269251538Srpaulo /* Initialize DMA. */ 3270251538Srpaulo error = urtwn_dma_init(sc); 3271251538Srpaulo if (error != 0) 3272251538Srpaulo goto fail; 3273251538Srpaulo 3274251538Srpaulo /* Set info size in Rx descriptors (in 64-bit words). */ 3275251538Srpaulo urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3276251538Srpaulo 3277251538Srpaulo /* Init interrupts. */ 3278264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3279264912Skevlo urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3280264912Skevlo urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3281264912Skevlo R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3282264912Skevlo urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3283264912Skevlo R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3284264912Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3285264912Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3286264912Skevlo R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3287264912Skevlo } else { 3288264912Skevlo urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3289264912Skevlo urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3290264912Skevlo } 3291251538Srpaulo 3292251538Srpaulo /* Set MAC address. */ 3293287197Sglebius IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3294287197Sglebius urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3295251538Srpaulo 3296251538Srpaulo /* Set initial network type. */ 3297251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 3298251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3299251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 3300251538Srpaulo 3301251538Srpaulo urtwn_rxfilter_init(sc); 3302251538Srpaulo 3303282623Skevlo /* Set response rate. */ 3304251538Srpaulo reg = urtwn_read_4(sc, R92C_RRSR); 3305251538Srpaulo reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3306251538Srpaulo urtwn_write_4(sc, R92C_RRSR, reg); 3307251538Srpaulo 3308251538Srpaulo /* Set short/long retry limits. */ 3309251538Srpaulo urtwn_write_2(sc, R92C_RL, 3310251538Srpaulo SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3311251538Srpaulo 3312251538Srpaulo /* Initialize EDCA parameters. */ 3313251538Srpaulo urtwn_edca_init(sc); 3314251538Srpaulo 3315251538Srpaulo /* Setup rate fallback. */ 3316264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3317264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3318264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3319264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3320264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3321264912Skevlo } 3322251538Srpaulo 3323251538Srpaulo urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3324251538Srpaulo urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3325251538Srpaulo R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3326251538Srpaulo /* Set ACK timeout. */ 3327251538Srpaulo urtwn_write_1(sc, R92C_ACKTO, 0x40); 3328251538Srpaulo 3329251538Srpaulo /* Setup USB aggregation. */ 3330251538Srpaulo reg = urtwn_read_4(sc, R92C_TDECTRL); 3331251538Srpaulo reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3332251538Srpaulo urtwn_write_4(sc, R92C_TDECTRL, reg); 3333251538Srpaulo urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3334251538Srpaulo urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3335251538Srpaulo R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3336251538Srpaulo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3337264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3338264912Skevlo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3339282266Skevlo else { 3340264912Skevlo urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3341282266Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3342282266Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3343282266Skevlo R92C_USB_SPECIAL_OPTION_AGG_EN); 3344282266Skevlo urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3345282266Skevlo urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3346282266Skevlo } 3347251538Srpaulo 3348251538Srpaulo /* Initialize beacon parameters. */ 3349264912Skevlo urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3350251538Srpaulo urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3351251538Srpaulo urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3352251538Srpaulo urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3353251538Srpaulo urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3354251538Srpaulo 3355264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3356264912Skevlo /* Setup AMPDU aggregation. */ 3357264912Skevlo urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3358264912Skevlo urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3359264912Skevlo urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3360251538Srpaulo 3361264912Skevlo urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3362264912Skevlo } 3363251538Srpaulo 3364251538Srpaulo /* Load 8051 microcode. */ 3365251538Srpaulo error = urtwn_load_firmware(sc); 3366251538Srpaulo if (error != 0) 3367251538Srpaulo goto fail; 3368251538Srpaulo 3369251538Srpaulo /* Initialize MAC/BB/RF blocks. */ 3370251538Srpaulo urtwn_mac_init(sc); 3371251538Srpaulo urtwn_bb_init(sc); 3372251538Srpaulo urtwn_rf_init(sc); 3373251538Srpaulo 3374264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3375264912Skevlo urtwn_write_2(sc, R92C_CR, 3376264912Skevlo urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3377264912Skevlo R92C_CR_MACRXEN); 3378264912Skevlo } 3379264912Skevlo 3380251538Srpaulo /* Turn CCK and OFDM blocks on. */ 3381251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3382251538Srpaulo reg |= R92C_RFMOD_CCK_EN; 3383251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3384251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3385251538Srpaulo reg |= R92C_RFMOD_OFDM_EN; 3386251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3387251538Srpaulo 3388251538Srpaulo /* Clear per-station keys table. */ 3389251538Srpaulo urtwn_cam_init(sc); 3390251538Srpaulo 3391251538Srpaulo /* Enable hardware sequence numbering. */ 3392251538Srpaulo urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3393251538Srpaulo 3394251538Srpaulo /* Perform LO and IQ calibrations. */ 3395251538Srpaulo urtwn_iq_calib(sc); 3396251538Srpaulo /* Perform LC calibration. */ 3397251538Srpaulo urtwn_lc_calib(sc); 3398251538Srpaulo 3399251538Srpaulo /* Fix USB interference issue. */ 3400264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3401264912Skevlo urtwn_write_1(sc, 0xfe40, 0xe0); 3402264912Skevlo urtwn_write_1(sc, 0xfe41, 0x8d); 3403264912Skevlo urtwn_write_1(sc, 0xfe42, 0x80); 3404251538Srpaulo 3405264912Skevlo urtwn_pa_bias_init(sc); 3406264912Skevlo } 3407251538Srpaulo 3408251538Srpaulo /* Initialize GPIO setting. */ 3409251538Srpaulo urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3410251538Srpaulo urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3411251538Srpaulo 3412251538Srpaulo /* Fix for lower temperature. */ 3413264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 3414264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 3415251538Srpaulo 3416251538Srpaulo usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3417251538Srpaulo 3418287197Sglebius sc->sc_flags |= URTWN_RUNNING; 3419251538Srpaulo 3420251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3421251538Srpaulofail: 3422251538Srpaulo return; 3423251538Srpaulo} 3424251538Srpaulo 3425251538Srpaulostatic void 3426287197Sglebiusurtwn_stop(struct urtwn_softc *sc) 3427251538Srpaulo{ 3428251538Srpaulo 3429264864Skevlo URTWN_ASSERT_LOCKED(sc); 3430287197Sglebius sc->sc_flags &= ~URTWN_RUNNING; 3431251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 3432251538Srpaulo urtwn_abort_xfers(sc); 3433288353Sadrian 3434288353Sadrian urtwn_drain_mbufq(sc); 3435251538Srpaulo} 3436251538Srpaulo 3437251538Srpaulostatic void 3438251538Srpaulourtwn_abort_xfers(struct urtwn_softc *sc) 3439251538Srpaulo{ 3440251538Srpaulo int i; 3441251538Srpaulo 3442251538Srpaulo URTWN_ASSERT_LOCKED(sc); 3443251538Srpaulo 3444251538Srpaulo /* abort any pending transfers */ 3445251538Srpaulo for (i = 0; i < URTWN_N_TRANSFER; i++) 3446251538Srpaulo usbd_transfer_stop(sc->sc_xfer[i]); 3447251538Srpaulo} 3448251538Srpaulo 3449251538Srpaulostatic int 3450251538Srpaulourtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3451251538Srpaulo const struct ieee80211_bpf_params *params) 3452251538Srpaulo{ 3453251538Srpaulo struct ieee80211com *ic = ni->ni_ic; 3454286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 3455251538Srpaulo struct urtwn_data *bf; 3456251538Srpaulo 3457251538Srpaulo /* prevent management frames from being sent if we're not ready */ 3458287197Sglebius if (!(sc->sc_flags & URTWN_RUNNING)) { 3459251538Srpaulo m_freem(m); 3460251538Srpaulo return (ENETDOWN); 3461251538Srpaulo } 3462251538Srpaulo URTWN_LOCK(sc); 3463251538Srpaulo bf = urtwn_getbuf(sc); 3464251538Srpaulo if (bf == NULL) { 3465251538Srpaulo m_freem(m); 3466251538Srpaulo URTWN_UNLOCK(sc); 3467251538Srpaulo return (ENOBUFS); 3468251538Srpaulo } 3469251538Srpaulo 3470251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3471288353Sadrian m_freem(m); 3472251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3473251538Srpaulo URTWN_UNLOCK(sc); 3474251538Srpaulo return (EIO); 3475251538Srpaulo } 3476288353Sadrian sc->sc_txtimer = 5; 3477251538Srpaulo URTWN_UNLOCK(sc); 3478251538Srpaulo 3479251538Srpaulo return (0); 3480251538Srpaulo} 3481251538Srpaulo 3482266472Shselaskystatic void 3483266472Shselaskyurtwn_ms_delay(struct urtwn_softc *sc) 3484266472Shselasky{ 3485266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3486266472Shselasky} 3487266472Shselasky 3488251538Srpaulostatic device_method_t urtwn_methods[] = { 3489251538Srpaulo /* Device interface */ 3490251538Srpaulo DEVMETHOD(device_probe, urtwn_match), 3491251538Srpaulo DEVMETHOD(device_attach, urtwn_attach), 3492251538Srpaulo DEVMETHOD(device_detach, urtwn_detach), 3493251538Srpaulo 3494264912Skevlo DEVMETHOD_END 3495251538Srpaulo}; 3496251538Srpaulo 3497251538Srpaulostatic driver_t urtwn_driver = { 3498251538Srpaulo "urtwn", 3499251538Srpaulo urtwn_methods, 3500251538Srpaulo sizeof(struct urtwn_softc) 3501251538Srpaulo}; 3502251538Srpaulo 3503251538Srpaulostatic devclass_t urtwn_devclass; 3504251538Srpaulo 3505251538SrpauloDRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3506251538SrpauloMODULE_DEPEND(urtwn, usb, 1, 1, 1); 3507251538SrpauloMODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3508251538SrpauloMODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3509251538SrpauloMODULE_VERSION(urtwn, 1); 3510