if_urtwn.c revision 289173
1251538Srpaulo/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2251538Srpaulo 3251538Srpaulo/*- 4251538Srpaulo * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5264912Skevlo * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6251538Srpaulo * 7251538Srpaulo * Permission to use, copy, modify, and distribute this software for any 8251538Srpaulo * purpose with or without fee is hereby granted, provided that the above 9251538Srpaulo * copyright notice and this permission notice appear in all copies. 10251538Srpaulo * 11251538Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12251538Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13251538Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14251538Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15251538Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16251538Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17251538Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18251538Srpaulo */ 19251538Srpaulo 20251538Srpaulo#include <sys/cdefs.h> 21251538Srpaulo__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 289173 2015-10-12 08:17:21Z kevlo $"); 22251538Srpaulo 23251538Srpaulo/* 24264912Skevlo * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25251538Srpaulo */ 26251538Srpaulo 27288353Sadrian#include "opt_wlan.h" 28288353Sadrian 29251538Srpaulo#include <sys/param.h> 30251538Srpaulo#include <sys/sockio.h> 31251538Srpaulo#include <sys/sysctl.h> 32251538Srpaulo#include <sys/lock.h> 33251538Srpaulo#include <sys/mutex.h> 34251538Srpaulo#include <sys/mbuf.h> 35251538Srpaulo#include <sys/kernel.h> 36251538Srpaulo#include <sys/socket.h> 37251538Srpaulo#include <sys/systm.h> 38251538Srpaulo#include <sys/malloc.h> 39251538Srpaulo#include <sys/module.h> 40251538Srpaulo#include <sys/bus.h> 41251538Srpaulo#include <sys/endian.h> 42251538Srpaulo#include <sys/linker.h> 43251538Srpaulo#include <sys/firmware.h> 44251538Srpaulo#include <sys/kdb.h> 45251538Srpaulo 46251538Srpaulo#include <machine/bus.h> 47251538Srpaulo#include <machine/resource.h> 48251538Srpaulo#include <sys/rman.h> 49251538Srpaulo 50251538Srpaulo#include <net/bpf.h> 51251538Srpaulo#include <net/if.h> 52257176Sglebius#include <net/if_var.h> 53251538Srpaulo#include <net/if_arp.h> 54251538Srpaulo#include <net/ethernet.h> 55251538Srpaulo#include <net/if_dl.h> 56251538Srpaulo#include <net/if_media.h> 57251538Srpaulo#include <net/if_types.h> 58251538Srpaulo 59251538Srpaulo#include <netinet/in.h> 60251538Srpaulo#include <netinet/in_systm.h> 61251538Srpaulo#include <netinet/in_var.h> 62251538Srpaulo#include <netinet/if_ether.h> 63251538Srpaulo#include <netinet/ip.h> 64251538Srpaulo 65251538Srpaulo#include <net80211/ieee80211_var.h> 66288088Sadrian#include <net80211/ieee80211_input.h> 67251538Srpaulo#include <net80211/ieee80211_regdomain.h> 68251538Srpaulo#include <net80211/ieee80211_radiotap.h> 69251538Srpaulo#include <net80211/ieee80211_ratectl.h> 70251538Srpaulo 71251538Srpaulo#include <dev/usb/usb.h> 72251538Srpaulo#include <dev/usb/usbdi.h> 73251538Srpaulo#include "usbdevs.h" 74251538Srpaulo 75251538Srpaulo#define USB_DEBUG_VAR urtwn_debug 76251538Srpaulo#include <dev/usb/usb_debug.h> 77251538Srpaulo 78251538Srpaulo#include <dev/usb/wlan/if_urtwnreg.h> 79289167Sadrian#include <dev/usb/wlan/if_urtwnvar.h> 80251538Srpaulo 81251538Srpaulo#ifdef USB_DEBUG 82251538Srpaulostatic int urtwn_debug = 0; 83251538Srpaulo 84251538SrpauloSYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 85276701ShselaskySYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 86251538Srpaulo "Debug level"); 87251538Srpaulo#endif 88251538Srpaulo 89252406Srpaulo#define URTWN_RSSI(r) (r) - 110 90288088Sadrian#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 91251538Srpaulo 92251538Srpaulo/* various supported device vendors/products */ 93251596Srpaulostatic const STRUCT_USB_HOST_ID urtwn_devs[] = { 94251538Srpaulo#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 95264912Skevlo#define URTWN_RTL8188E_DEV(v,p) \ 96264912Skevlo { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 97264912Skevlo#define URTWN_RTL8188E 1 98251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_1), 99251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_2), 100251538Srpaulo URTWN_DEV(ABOCOM, RTL8192CU), 101251538Srpaulo URTWN_DEV(ASUS, RTL8192CU), 102266721Skevlo URTWN_DEV(ASUS, USBN10NANO), 103251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_1), 104251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_2), 105251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CU), 106251538Srpaulo URTWN_DEV(BELKIN, F7D2102), 107251538Srpaulo URTWN_DEV(BELKIN, RTL8188CU), 108251538Srpaulo URTWN_DEV(BELKIN, RTL8192CU), 109251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_1), 110251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_2), 111251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_3), 112251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_4), 113251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_5), 114251538Srpaulo URTWN_DEV(COREGA, RTL8192CU), 115251538Srpaulo URTWN_DEV(DLINK, RTL8188CU), 116251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_1), 117251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_2), 118251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_3), 119252196Skevlo URTWN_DEV(DLINK, DWA131B), 120251538Srpaulo URTWN_DEV(EDIMAX, EW7811UN), 121251538Srpaulo URTWN_DEV(EDIMAX, RTL8192CU), 122251538Srpaulo URTWN_DEV(FEIXUN, RTL8188CU), 123251538Srpaulo URTWN_DEV(FEIXUN, RTL8192CU), 124251538Srpaulo URTWN_DEV(GUILLEMOT, HWNUP150), 125251538Srpaulo URTWN_DEV(HAWKING, RTL8192CU), 126251538Srpaulo URTWN_DEV(HP3, RTL8188CU), 127251538Srpaulo URTWN_DEV(NETGEAR, WNA1000M), 128251538Srpaulo URTWN_DEV(NETGEAR, RTL8192CU), 129251538Srpaulo URTWN_DEV(NETGEAR4, RTL8188CU), 130251538Srpaulo URTWN_DEV(NOVATECH, RTL8188CU), 131251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_1), 132251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_2), 133251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_3), 134251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_4), 135251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CUS), 136251538Srpaulo URTWN_DEV(PLANEX2, RTL8192CU), 137251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_0), 138251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_1), 139251538Srpaulo URTWN_DEV(REALTEK, RTL8188CTV), 140251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_0), 141251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_1), 142251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_2), 143282119Skevlo URTWN_DEV(REALTEK, RTL8188CU_3), 144251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_COMBO), 145251538Srpaulo URTWN_DEV(REALTEK, RTL8188CUS), 146251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_1), 147251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_2), 148272410Shselasky URTWN_DEV(REALTEK, RTL8188RU_3), 149251538Srpaulo URTWN_DEV(REALTEK, RTL8191CU), 150251538Srpaulo URTWN_DEV(REALTEK, RTL8192CE), 151251538Srpaulo URTWN_DEV(REALTEK, RTL8192CU), 152251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_1), 153251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_2), 154251538Srpaulo URTWN_DEV(SITECOMEU, RTL8192CU), 155251538Srpaulo URTWN_DEV(TRENDNET, RTL8188CU), 156251538Srpaulo URTWN_DEV(TRENDNET, RTL8192CU), 157251538Srpaulo URTWN_DEV(ZYXEL, RTL8192CU), 158264912Skevlo /* URTWN_RTL8188E */ 159273589Skevlo URTWN_RTL8188E_DEV(DLINK, DWA123D1), 160270191Skevlo URTWN_RTL8188E_DEV(DLINK, DWA125D1), 161273589Skevlo URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 162264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 163264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 164264912Skevlo#undef URTWN_RTL8188E_DEV 165251538Srpaulo#undef URTWN_DEV 166251538Srpaulo}; 167251538Srpaulo 168251538Srpaulostatic device_probe_t urtwn_match; 169251538Srpaulostatic device_attach_t urtwn_attach; 170251538Srpaulostatic device_detach_t urtwn_detach; 171251538Srpaulo 172251538Srpaulostatic usb_callback_t urtwn_bulk_tx_callback; 173251538Srpaulostatic usb_callback_t urtwn_bulk_rx_callback; 174251538Srpaulo 175288353Sadrianstatic void urtwn_drain_mbufq(struct urtwn_softc *sc); 176287197Sglebiusstatic usb_error_t urtwn_do_request(struct urtwn_softc *, 177287197Sglebius struct usb_device_request *, void *); 178251538Srpaulostatic struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 179251538Srpaulo const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 180251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN], 181251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN]); 182251538Srpaulostatic void urtwn_vap_delete(struct ieee80211vap *); 183281069Srpaulostatic struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 184251538Srpaulo int *); 185281069Srpaulostatic struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 186251538Srpaulo int *, int8_t *); 187251538Srpaulostatic void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 188281069Srpaulostatic int urtwn_alloc_list(struct urtwn_softc *, 189251538Srpaulo struct urtwn_data[], int, int); 190251538Srpaulostatic int urtwn_alloc_rx_list(struct urtwn_softc *); 191251538Srpaulostatic int urtwn_alloc_tx_list(struct urtwn_softc *); 192251538Srpaulostatic void urtwn_free_list(struct urtwn_softc *, 193251538Srpaulo struct urtwn_data data[], int); 194289066Skevlostatic void urtwn_free_rx_list(struct urtwn_softc *); 195289066Skevlostatic void urtwn_free_tx_list(struct urtwn_softc *); 196251538Srpaulostatic struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 197251538Srpaulostatic struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 198281069Srpaulostatic int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 199251538Srpaulo uint8_t *, int); 200251538Srpaulostatic void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 201251538Srpaulostatic void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 202251538Srpaulostatic void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 203281069Srpaulostatic int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 204251538Srpaulo uint8_t *, int); 205251538Srpaulostatic uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 206251538Srpaulostatic uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 207251538Srpaulostatic uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 208281069Srpaulostatic int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 209251538Srpaulo const void *, int); 210264912Skevlostatic void urtwn_r92c_rf_write(struct urtwn_softc *, int, 211264912Skevlo uint8_t, uint32_t); 212281069Srpaulostatic void urtwn_r88e_rf_write(struct urtwn_softc *, int, 213264912Skevlo uint8_t, uint32_t); 214251538Srpaulostatic uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 215281069Srpaulostatic int urtwn_llt_write(struct urtwn_softc *, uint32_t, 216251538Srpaulo uint32_t); 217251538Srpaulostatic uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 218251538Srpaulostatic void urtwn_efuse_read(struct urtwn_softc *); 219264912Skevlostatic void urtwn_efuse_switch_power(struct urtwn_softc *); 220251538Srpaulostatic int urtwn_read_chipid(struct urtwn_softc *); 221251538Srpaulostatic void urtwn_read_rom(struct urtwn_softc *); 222264912Skevlostatic void urtwn_r88e_read_rom(struct urtwn_softc *); 223251538Srpaulostatic int urtwn_ra_init(struct urtwn_softc *); 224251538Srpaulostatic void urtwn_tsf_sync_enable(struct urtwn_softc *); 225251538Srpaulostatic void urtwn_set_led(struct urtwn_softc *, int, int); 226281069Srpaulostatic int urtwn_newstate(struct ieee80211vap *, 227251538Srpaulo enum ieee80211_state, int); 228251538Srpaulostatic void urtwn_watchdog(void *); 229251538Srpaulostatic void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 230251538Srpaulostatic int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 231264912Skevlostatic int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 232251538Srpaulostatic int urtwn_tx_start(struct urtwn_softc *, 233251538Srpaulo struct ieee80211_node *, struct mbuf *, 234251538Srpaulo struct urtwn_data *); 235287197Sglebiusstatic int urtwn_transmit(struct ieee80211com *, struct mbuf *); 236287197Sglebiusstatic void urtwn_start(struct urtwn_softc *); 237287197Sglebiusstatic void urtwn_parent(struct ieee80211com *); 238264912Skevlostatic int urtwn_r92c_power_on(struct urtwn_softc *); 239264912Skevlostatic int urtwn_r88e_power_on(struct urtwn_softc *); 240251538Srpaulostatic int urtwn_llt_init(struct urtwn_softc *); 241251538Srpaulostatic void urtwn_fw_reset(struct urtwn_softc *); 242264912Skevlostatic void urtwn_r88e_fw_reset(struct urtwn_softc *); 243281069Srpaulostatic int urtwn_fw_loadpage(struct urtwn_softc *, int, 244251538Srpaulo const uint8_t *, int); 245251538Srpaulostatic int urtwn_load_firmware(struct urtwn_softc *); 246264912Skevlostatic int urtwn_r92c_dma_init(struct urtwn_softc *); 247264912Skevlostatic int urtwn_r88e_dma_init(struct urtwn_softc *); 248251538Srpaulostatic void urtwn_mac_init(struct urtwn_softc *); 249251538Srpaulostatic void urtwn_bb_init(struct urtwn_softc *); 250251538Srpaulostatic void urtwn_rf_init(struct urtwn_softc *); 251251538Srpaulostatic void urtwn_cam_init(struct urtwn_softc *); 252251538Srpaulostatic void urtwn_pa_bias_init(struct urtwn_softc *); 253251538Srpaulostatic void urtwn_rxfilter_init(struct urtwn_softc *); 254251538Srpaulostatic void urtwn_edca_init(struct urtwn_softc *); 255281069Srpaulostatic void urtwn_write_txpower(struct urtwn_softc *, int, 256251538Srpaulo uint16_t[]); 257251538Srpaulostatic void urtwn_get_txpower(struct urtwn_softc *, int, 258281069Srpaulo struct ieee80211_channel *, 259251538Srpaulo struct ieee80211_channel *, uint16_t[]); 260264912Skevlostatic void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 261281069Srpaulo struct ieee80211_channel *, 262264912Skevlo struct ieee80211_channel *, uint16_t[]); 263251538Srpaulostatic void urtwn_set_txpower(struct urtwn_softc *, 264281069Srpaulo struct ieee80211_channel *, 265251538Srpaulo struct ieee80211_channel *); 266251538Srpaulostatic void urtwn_scan_start(struct ieee80211com *); 267251538Srpaulostatic void urtwn_scan_end(struct ieee80211com *); 268251538Srpaulostatic void urtwn_set_channel(struct ieee80211com *); 269289066Skevlostatic void urtwn_update_mcast(struct ieee80211com *); 270251538Srpaulostatic void urtwn_set_chan(struct urtwn_softc *, 271281069Srpaulo struct ieee80211_channel *, 272251538Srpaulo struct ieee80211_channel *); 273251538Srpaulostatic void urtwn_iq_calib(struct urtwn_softc *); 274251538Srpaulostatic void urtwn_lc_calib(struct urtwn_softc *); 275287197Sglebiusstatic void urtwn_init(struct urtwn_softc *); 276287197Sglebiusstatic void urtwn_stop(struct urtwn_softc *); 277251538Srpaulostatic void urtwn_abort_xfers(struct urtwn_softc *); 278251538Srpaulostatic int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 279251538Srpaulo const struct ieee80211_bpf_params *); 280266472Shselaskystatic void urtwn_ms_delay(struct urtwn_softc *); 281251538Srpaulo 282251538Srpaulo/* Aliases. */ 283251538Srpaulo#define urtwn_bb_write urtwn_write_4 284251538Srpaulo#define urtwn_bb_read urtwn_read_4 285251538Srpaulo 286251538Srpaulostatic const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 287251538Srpaulo [URTWN_BULK_RX] = { 288251538Srpaulo .type = UE_BULK, 289251538Srpaulo .endpoint = UE_ADDR_ANY, 290251538Srpaulo .direction = UE_DIR_IN, 291251538Srpaulo .bufsize = URTWN_RXBUFSZ, 292251538Srpaulo .flags = { 293251538Srpaulo .pipe_bof = 1, 294251538Srpaulo .short_xfer_ok = 1 295251538Srpaulo }, 296251538Srpaulo .callback = urtwn_bulk_rx_callback, 297251538Srpaulo }, 298251538Srpaulo [URTWN_BULK_TX_BE] = { 299251538Srpaulo .type = UE_BULK, 300251538Srpaulo .endpoint = 0x03, 301251538Srpaulo .direction = UE_DIR_OUT, 302251538Srpaulo .bufsize = URTWN_TXBUFSZ, 303251538Srpaulo .flags = { 304251538Srpaulo .ext_buffer = 1, 305251538Srpaulo .pipe_bof = 1, 306251538Srpaulo .force_short_xfer = 1 307251538Srpaulo }, 308251538Srpaulo .callback = urtwn_bulk_tx_callback, 309251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 310251538Srpaulo }, 311251538Srpaulo [URTWN_BULK_TX_BK] = { 312251538Srpaulo .type = UE_BULK, 313251538Srpaulo .endpoint = 0x03, 314251538Srpaulo .direction = UE_DIR_OUT, 315251538Srpaulo .bufsize = URTWN_TXBUFSZ, 316251538Srpaulo .flags = { 317251538Srpaulo .ext_buffer = 1, 318251538Srpaulo .pipe_bof = 1, 319251538Srpaulo .force_short_xfer = 1, 320251538Srpaulo }, 321251538Srpaulo .callback = urtwn_bulk_tx_callback, 322251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 323251538Srpaulo }, 324251538Srpaulo [URTWN_BULK_TX_VI] = { 325251538Srpaulo .type = UE_BULK, 326251538Srpaulo .endpoint = 0x02, 327251538Srpaulo .direction = UE_DIR_OUT, 328251538Srpaulo .bufsize = URTWN_TXBUFSZ, 329251538Srpaulo .flags = { 330251538Srpaulo .ext_buffer = 1, 331251538Srpaulo .pipe_bof = 1, 332251538Srpaulo .force_short_xfer = 1 333251538Srpaulo }, 334251538Srpaulo .callback = urtwn_bulk_tx_callback, 335251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 336251538Srpaulo }, 337251538Srpaulo [URTWN_BULK_TX_VO] = { 338251538Srpaulo .type = UE_BULK, 339251538Srpaulo .endpoint = 0x02, 340251538Srpaulo .direction = UE_DIR_OUT, 341251538Srpaulo .bufsize = URTWN_TXBUFSZ, 342251538Srpaulo .flags = { 343251538Srpaulo .ext_buffer = 1, 344251538Srpaulo .pipe_bof = 1, 345251538Srpaulo .force_short_xfer = 1 346251538Srpaulo }, 347251538Srpaulo .callback = urtwn_bulk_tx_callback, 348251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 349251538Srpaulo }, 350251538Srpaulo}; 351251538Srpaulo 352251538Srpaulostatic int 353251538Srpaulourtwn_match(device_t self) 354251538Srpaulo{ 355251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 356251538Srpaulo 357251538Srpaulo if (uaa->usb_mode != USB_MODE_HOST) 358251538Srpaulo return (ENXIO); 359251538Srpaulo if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 360251538Srpaulo return (ENXIO); 361251538Srpaulo if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 362251538Srpaulo return (ENXIO); 363251538Srpaulo 364251538Srpaulo return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 365251538Srpaulo} 366251538Srpaulo 367251538Srpaulostatic int 368251538Srpaulourtwn_attach(device_t self) 369251538Srpaulo{ 370251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 371251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 372287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 373251538Srpaulo uint8_t iface_index, bands; 374251538Srpaulo int error; 375251538Srpaulo 376251538Srpaulo device_set_usb_desc(self); 377251538Srpaulo sc->sc_udev = uaa->device; 378251538Srpaulo sc->sc_dev = self; 379264912Skevlo if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 380264912Skevlo sc->chip |= URTWN_CHIP_88E; 381251538Srpaulo 382251538Srpaulo mtx_init(&sc->sc_mtx, device_get_nameunit(self), 383251538Srpaulo MTX_NETWORK_LOCK, MTX_DEF); 384251538Srpaulo callout_init(&sc->sc_watchdog_ch, 0); 385287197Sglebius mbufq_init(&sc->sc_snd, ifqmaxlen); 386251538Srpaulo 387251538Srpaulo iface_index = URTWN_IFACE_INDEX; 388251538Srpaulo error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 389251538Srpaulo urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 390251538Srpaulo if (error) { 391251538Srpaulo device_printf(self, "could not allocate USB transfers, " 392251538Srpaulo "err=%s\n", usbd_errstr(error)); 393251538Srpaulo goto detach; 394251538Srpaulo } 395251538Srpaulo 396251538Srpaulo URTWN_LOCK(sc); 397251538Srpaulo 398251538Srpaulo error = urtwn_read_chipid(sc); 399251538Srpaulo if (error) { 400251538Srpaulo device_printf(sc->sc_dev, "unsupported test chip\n"); 401251538Srpaulo URTWN_UNLOCK(sc); 402251538Srpaulo goto detach; 403251538Srpaulo } 404251538Srpaulo 405251538Srpaulo /* Determine number of Tx/Rx chains. */ 406251538Srpaulo if (sc->chip & URTWN_CHIP_92C) { 407251538Srpaulo sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 408251538Srpaulo sc->nrxchains = 2; 409251538Srpaulo } else { 410251538Srpaulo sc->ntxchains = 1; 411251538Srpaulo sc->nrxchains = 1; 412251538Srpaulo } 413251538Srpaulo 414264912Skevlo if (sc->chip & URTWN_CHIP_88E) 415264912Skevlo urtwn_r88e_read_rom(sc); 416264912Skevlo else 417264912Skevlo urtwn_read_rom(sc); 418264912Skevlo 419251538Srpaulo device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 420251538Srpaulo (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 421264912Skevlo (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 422251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 423251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 424251538Srpaulo "8188CUS", sc->ntxchains, sc->nrxchains); 425251538Srpaulo 426251538Srpaulo URTWN_UNLOCK(sc); 427251538Srpaulo 428283537Sglebius ic->ic_softc = sc; 429283527Sglebius ic->ic_name = device_get_nameunit(self); 430251538Srpaulo ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 431251538Srpaulo ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 432251538Srpaulo 433251538Srpaulo /* set device capabilities */ 434251538Srpaulo ic->ic_caps = 435251538Srpaulo IEEE80211_C_STA /* station mode */ 436251538Srpaulo | IEEE80211_C_MONITOR /* monitor mode */ 437251538Srpaulo | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 438251538Srpaulo | IEEE80211_C_SHSLOT /* short slot time supported */ 439251538Srpaulo | IEEE80211_C_BGSCAN /* capable of bg scanning */ 440251538Srpaulo | IEEE80211_C_WPA /* 802.11i */ 441251538Srpaulo ; 442251538Srpaulo 443251538Srpaulo bands = 0; 444251538Srpaulo setbit(&bands, IEEE80211_MODE_11B); 445251538Srpaulo setbit(&bands, IEEE80211_MODE_11G); 446251538Srpaulo ieee80211_init_channels(ic, NULL, &bands); 447251538Srpaulo 448287197Sglebius ieee80211_ifattach(ic); 449251538Srpaulo ic->ic_raw_xmit = urtwn_raw_xmit; 450251538Srpaulo ic->ic_scan_start = urtwn_scan_start; 451251538Srpaulo ic->ic_scan_end = urtwn_scan_end; 452251538Srpaulo ic->ic_set_channel = urtwn_set_channel; 453287197Sglebius ic->ic_transmit = urtwn_transmit; 454287197Sglebius ic->ic_parent = urtwn_parent; 455251538Srpaulo ic->ic_vap_create = urtwn_vap_create; 456251538Srpaulo ic->ic_vap_delete = urtwn_vap_delete; 457251538Srpaulo ic->ic_update_mcast = urtwn_update_mcast; 458251538Srpaulo 459281069Srpaulo ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 460251538Srpaulo sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 461251538Srpaulo &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 462251538Srpaulo URTWN_RX_RADIOTAP_PRESENT); 463251538Srpaulo 464251538Srpaulo if (bootverbose) 465251538Srpaulo ieee80211_announce(ic); 466251538Srpaulo 467251538Srpaulo return (0); 468251538Srpaulo 469251538Srpaulodetach: 470251538Srpaulo urtwn_detach(self); 471251538Srpaulo return (ENXIO); /* failure */ 472251538Srpaulo} 473251538Srpaulo 474251538Srpaulostatic int 475251538Srpaulourtwn_detach(device_t self) 476251538Srpaulo{ 477251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 478287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 479263153Skevlo unsigned int x; 480281069Srpaulo 481263153Skevlo /* Prevent further ioctls. */ 482263153Skevlo URTWN_LOCK(sc); 483263153Skevlo sc->sc_flags |= URTWN_DETACHED; 484287197Sglebius urtwn_stop(sc); 485263153Skevlo URTWN_UNLOCK(sc); 486251538Srpaulo 487251538Srpaulo callout_drain(&sc->sc_watchdog_ch); 488251538Srpaulo 489288353Sadrian /* stop all USB transfers */ 490288353Sadrian usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 491288353Sadrian 492263153Skevlo /* Prevent further allocations from RX/TX data lists. */ 493263153Skevlo URTWN_LOCK(sc); 494263153Skevlo STAILQ_INIT(&sc->sc_tx_active); 495263153Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 496263153Skevlo STAILQ_INIT(&sc->sc_tx_pending); 497263153Skevlo 498263153Skevlo STAILQ_INIT(&sc->sc_rx_active); 499263153Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 500263153Skevlo URTWN_UNLOCK(sc); 501263153Skevlo 502263153Skevlo /* drain USB transfers */ 503263153Skevlo for (x = 0; x != URTWN_N_TRANSFER; x++) 504263153Skevlo usbd_transfer_drain(sc->sc_xfer[x]); 505263153Skevlo 506263153Skevlo /* Free data buffers. */ 507263153Skevlo URTWN_LOCK(sc); 508263153Skevlo urtwn_free_tx_list(sc); 509263153Skevlo urtwn_free_rx_list(sc); 510263153Skevlo URTWN_UNLOCK(sc); 511263153Skevlo 512251538Srpaulo ieee80211_ifdetach(ic); 513251538Srpaulo mtx_destroy(&sc->sc_mtx); 514251538Srpaulo 515251538Srpaulo return (0); 516251538Srpaulo} 517251538Srpaulo 518251538Srpaulostatic void 519289066Skevlourtwn_drain_mbufq(struct urtwn_softc *sc) 520251538Srpaulo{ 521289066Skevlo struct mbuf *m; 522289066Skevlo struct ieee80211_node *ni; 523289066Skevlo URTWN_ASSERT_LOCKED(sc); 524289066Skevlo while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 525289066Skevlo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 526289066Skevlo m->m_pkthdr.rcvif = NULL; 527289066Skevlo ieee80211_free_node(ni); 528289066Skevlo m_freem(m); 529251538Srpaulo } 530251538Srpaulo} 531251538Srpaulo 532251538Srpaulostatic usb_error_t 533251538Srpaulourtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 534251538Srpaulo void *data) 535251538Srpaulo{ 536251538Srpaulo usb_error_t err; 537251538Srpaulo int ntries = 10; 538251538Srpaulo 539251538Srpaulo URTWN_ASSERT_LOCKED(sc); 540251538Srpaulo 541251538Srpaulo while (ntries--) { 542251538Srpaulo err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 543251538Srpaulo req, data, 0, NULL, 250 /* ms */); 544251538Srpaulo if (err == 0) 545251538Srpaulo break; 546251538Srpaulo 547251538Srpaulo DPRINTFN(1, "Control request failed, %s (retrying)\n", 548251538Srpaulo usbd_errstr(err)); 549251538Srpaulo usb_pause_mtx(&sc->sc_mtx, hz / 100); 550251538Srpaulo } 551251538Srpaulo return (err); 552251538Srpaulo} 553251538Srpaulo 554251538Srpaulostatic struct ieee80211vap * 555251538Srpaulourtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 556251538Srpaulo enum ieee80211_opmode opmode, int flags, 557251538Srpaulo const uint8_t bssid[IEEE80211_ADDR_LEN], 558251538Srpaulo const uint8_t mac[IEEE80211_ADDR_LEN]) 559251538Srpaulo{ 560251538Srpaulo struct urtwn_vap *uvp; 561251538Srpaulo struct ieee80211vap *vap; 562251538Srpaulo 563251538Srpaulo if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 564251538Srpaulo return (NULL); 565251538Srpaulo 566287197Sglebius uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 567251538Srpaulo vap = &uvp->vap; 568251538Srpaulo /* enable s/w bmiss handling for sta mode */ 569251538Srpaulo 570281069Srpaulo if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 571287197Sglebius flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 572257743Shselasky /* out of memory */ 573257743Shselasky free(uvp, M_80211_VAP); 574257743Shselasky return (NULL); 575257743Shselasky } 576257743Shselasky 577251538Srpaulo /* override state transition machine */ 578251538Srpaulo uvp->newstate = vap->iv_newstate; 579251538Srpaulo vap->iv_newstate = urtwn_newstate; 580251538Srpaulo 581251538Srpaulo /* complete setup */ 582251538Srpaulo ieee80211_vap_attach(vap, ieee80211_media_change, 583287197Sglebius ieee80211_media_status, mac); 584251538Srpaulo ic->ic_opmode = opmode; 585251538Srpaulo return (vap); 586251538Srpaulo} 587251538Srpaulo 588251538Srpaulostatic void 589251538Srpaulourtwn_vap_delete(struct ieee80211vap *vap) 590251538Srpaulo{ 591251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 592251538Srpaulo 593251538Srpaulo ieee80211_vap_detach(vap); 594251538Srpaulo free(uvp, M_80211_VAP); 595251538Srpaulo} 596251538Srpaulo 597251538Srpaulostatic struct mbuf * 598251538Srpaulourtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 599251538Srpaulo{ 600287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 601251538Srpaulo struct ieee80211_frame *wh; 602251538Srpaulo struct mbuf *m; 603251538Srpaulo struct r92c_rx_stat *stat; 604251538Srpaulo uint32_t rxdw0, rxdw3; 605251538Srpaulo uint8_t rate; 606251538Srpaulo int8_t rssi = 0; 607251538Srpaulo int infosz; 608251538Srpaulo 609251538Srpaulo /* 610251538Srpaulo * don't pass packets to the ieee80211 framework if the driver isn't 611251538Srpaulo * RUNNING. 612251538Srpaulo */ 613287197Sglebius if (!(sc->sc_flags & URTWN_RUNNING)) 614251538Srpaulo return (NULL); 615251538Srpaulo 616251538Srpaulo stat = (struct r92c_rx_stat *)buf; 617251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 618251538Srpaulo rxdw3 = le32toh(stat->rxdw3); 619251538Srpaulo 620251538Srpaulo if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 621251538Srpaulo /* 622251538Srpaulo * This should not happen since we setup our Rx filter 623251538Srpaulo * to not receive these frames. 624251538Srpaulo */ 625287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 626251538Srpaulo return (NULL); 627251538Srpaulo } 628271303Skevlo if (pktlen < sizeof(*wh) || pktlen > MCLBYTES) { 629287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 630271303Skevlo return (NULL); 631271303Skevlo } 632251538Srpaulo 633251538Srpaulo rate = MS(rxdw3, R92C_RXDW3_RATE); 634251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 635251538Srpaulo 636251538Srpaulo /* Get RSSI from PHY status descriptor if present. */ 637251538Srpaulo if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 638281069Srpaulo if (sc->chip & URTWN_CHIP_88E) 639264912Skevlo rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 640264912Skevlo else 641264912Skevlo rssi = urtwn_get_rssi(sc, rate, &stat[1]); 642251538Srpaulo /* Update our average RSSI. */ 643251538Srpaulo urtwn_update_avgrssi(sc, rate, rssi); 644252405Srpaulo /* 645252405Srpaulo * Convert the RSSI to a range that will be accepted 646252405Srpaulo * by net80211. 647252405Srpaulo */ 648252405Srpaulo rssi = URTWN_RSSI(rssi); 649251538Srpaulo } 650251538Srpaulo 651260463Skevlo m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 652251538Srpaulo if (m == NULL) { 653251538Srpaulo device_printf(sc->sc_dev, "could not create RX mbuf\n"); 654251538Srpaulo return (NULL); 655251538Srpaulo } 656251538Srpaulo 657251538Srpaulo /* Finalize mbuf. */ 658251538Srpaulo wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 659251538Srpaulo memcpy(mtod(m, uint8_t *), wh, pktlen); 660251538Srpaulo m->m_pkthdr.len = m->m_len = pktlen; 661251538Srpaulo 662251538Srpaulo if (ieee80211_radiotap_active(ic)) { 663251538Srpaulo struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 664251538Srpaulo 665251538Srpaulo tap->wr_flags = 0; 666251538Srpaulo /* Map HW rate index to 802.11 rate. */ 667251538Srpaulo if (!(rxdw3 & R92C_RXDW3_HT)) { 668251538Srpaulo switch (rate) { 669251538Srpaulo /* CCK. */ 670251538Srpaulo case 0: tap->wr_rate = 2; break; 671251538Srpaulo case 1: tap->wr_rate = 4; break; 672251538Srpaulo case 2: tap->wr_rate = 11; break; 673251538Srpaulo case 3: tap->wr_rate = 22; break; 674251538Srpaulo /* OFDM. */ 675251538Srpaulo case 4: tap->wr_rate = 12; break; 676251538Srpaulo case 5: tap->wr_rate = 18; break; 677251538Srpaulo case 6: tap->wr_rate = 24; break; 678251538Srpaulo case 7: tap->wr_rate = 36; break; 679251538Srpaulo case 8: tap->wr_rate = 48; break; 680251538Srpaulo case 9: tap->wr_rate = 72; break; 681251538Srpaulo case 10: tap->wr_rate = 96; break; 682251538Srpaulo case 11: tap->wr_rate = 108; break; 683251538Srpaulo } 684251538Srpaulo } else if (rate >= 12) { /* MCS0~15. */ 685251538Srpaulo /* Bit 7 set means HT MCS instead of rate. */ 686251538Srpaulo tap->wr_rate = 0x80 | (rate - 12); 687251538Srpaulo } 688251538Srpaulo tap->wr_dbm_antsignal = rssi; 689251538Srpaulo tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 690251538Srpaulo tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 691251538Srpaulo } 692251538Srpaulo 693251538Srpaulo *rssi_p = rssi; 694251538Srpaulo 695251538Srpaulo return (m); 696251538Srpaulo} 697251538Srpaulo 698251538Srpaulostatic struct mbuf * 699251538Srpaulourtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 700251538Srpaulo int8_t *nf) 701251538Srpaulo{ 702251538Srpaulo struct urtwn_softc *sc = data->sc; 703287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 704251538Srpaulo struct r92c_rx_stat *stat; 705251538Srpaulo struct mbuf *m, *m0 = NULL, *prevm = NULL; 706251538Srpaulo uint32_t rxdw0; 707251538Srpaulo uint8_t *buf; 708251538Srpaulo int len, totlen, pktlen, infosz, npkts; 709251538Srpaulo 710251538Srpaulo usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 711251538Srpaulo 712251538Srpaulo if (len < sizeof(*stat)) { 713287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 714251538Srpaulo return (NULL); 715251538Srpaulo } 716251538Srpaulo 717251538Srpaulo buf = data->buf; 718251538Srpaulo /* Get the number of encapsulated frames. */ 719251538Srpaulo stat = (struct r92c_rx_stat *)buf; 720251538Srpaulo npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 721251538Srpaulo DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 722251538Srpaulo 723251538Srpaulo /* Process all of them. */ 724251538Srpaulo while (npkts-- > 0) { 725251538Srpaulo if (len < sizeof(*stat)) 726251538Srpaulo break; 727251538Srpaulo stat = (struct r92c_rx_stat *)buf; 728251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 729251538Srpaulo 730251538Srpaulo pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 731251538Srpaulo if (pktlen == 0) 732251538Srpaulo break; 733251538Srpaulo 734251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 735251538Srpaulo 736251538Srpaulo /* Make sure everything fits in xfer. */ 737251538Srpaulo totlen = sizeof(*stat) + infosz + pktlen; 738251538Srpaulo if (totlen > len) 739251538Srpaulo break; 740251538Srpaulo 741251538Srpaulo m = urtwn_rx_frame(sc, buf, pktlen, rssi); 742251538Srpaulo if (m0 == NULL) 743251538Srpaulo m0 = m; 744251538Srpaulo if (prevm == NULL) 745251538Srpaulo prevm = m; 746251538Srpaulo else { 747251538Srpaulo prevm->m_next = m; 748251538Srpaulo prevm = m; 749251538Srpaulo } 750251538Srpaulo 751251538Srpaulo /* Next chunk is 128-byte aligned. */ 752251538Srpaulo totlen = (totlen + 127) & ~127; 753251538Srpaulo buf += totlen; 754251538Srpaulo len -= totlen; 755251538Srpaulo } 756251538Srpaulo 757251538Srpaulo return (m0); 758251538Srpaulo} 759251538Srpaulo 760251538Srpaulostatic void 761251538Srpaulourtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 762251538Srpaulo{ 763251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 764287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 765251538Srpaulo struct ieee80211_frame *wh; 766251538Srpaulo struct ieee80211_node *ni; 767251538Srpaulo struct mbuf *m = NULL, *next; 768251538Srpaulo struct urtwn_data *data; 769251538Srpaulo int8_t nf; 770251538Srpaulo int rssi = 1; 771251538Srpaulo 772251538Srpaulo URTWN_ASSERT_LOCKED(sc); 773251538Srpaulo 774251538Srpaulo switch (USB_GET_STATE(xfer)) { 775251538Srpaulo case USB_ST_TRANSFERRED: 776251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 777251538Srpaulo if (data == NULL) 778251538Srpaulo goto tr_setup; 779251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 780251538Srpaulo m = urtwn_rxeof(xfer, data, &rssi, &nf); 781251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 782251538Srpaulo /* FALLTHROUGH */ 783251538Srpaulo case USB_ST_SETUP: 784251538Srpaulotr_setup: 785251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_inactive); 786251538Srpaulo if (data == NULL) { 787251538Srpaulo KASSERT(m == NULL, ("mbuf isn't NULL")); 788251538Srpaulo return; 789251538Srpaulo } 790251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 791251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 792251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, 793251538Srpaulo usbd_xfer_max_len(xfer)); 794251538Srpaulo usbd_transfer_submit(xfer); 795251538Srpaulo 796251538Srpaulo /* 797251538Srpaulo * To avoid LOR we should unlock our private mutex here to call 798251538Srpaulo * ieee80211_input() because here is at the end of a USB 799251538Srpaulo * callback and safe to unlock. 800251538Srpaulo */ 801251538Srpaulo URTWN_UNLOCK(sc); 802251538Srpaulo while (m != NULL) { 803251538Srpaulo next = m->m_next; 804251538Srpaulo m->m_next = NULL; 805251538Srpaulo wh = mtod(m, struct ieee80211_frame *); 806251538Srpaulo ni = ieee80211_find_rxnode(ic, 807251538Srpaulo (struct ieee80211_frame_min *)wh); 808251538Srpaulo nf = URTWN_NOISE_FLOOR; 809251538Srpaulo if (ni != NULL) { 810251538Srpaulo (void)ieee80211_input(ni, m, rssi, nf); 811251538Srpaulo ieee80211_free_node(ni); 812251538Srpaulo } else 813251538Srpaulo (void)ieee80211_input_all(ic, m, rssi, nf); 814251538Srpaulo m = next; 815251538Srpaulo } 816251538Srpaulo URTWN_LOCK(sc); 817251538Srpaulo break; 818251538Srpaulo default: 819251538Srpaulo /* needs it to the inactive queue due to a error. */ 820251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 821251538Srpaulo if (data != NULL) { 822251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 823251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 824251538Srpaulo } 825251538Srpaulo if (error != USB_ERR_CANCELLED) { 826251538Srpaulo usbd_xfer_set_stall(xfer); 827287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 828251538Srpaulo goto tr_setup; 829251538Srpaulo } 830251538Srpaulo break; 831251538Srpaulo } 832251538Srpaulo} 833251538Srpaulo 834251538Srpaulostatic void 835251538Srpaulourtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 836251538Srpaulo{ 837251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 838251538Srpaulo 839251538Srpaulo URTWN_ASSERT_LOCKED(sc); 840287197Sglebius /* XXX status? */ 841287197Sglebius ieee80211_tx_complete(data->ni, data->m, 0); 842287197Sglebius data->ni = NULL; 843287197Sglebius data->m = NULL; 844251538Srpaulo sc->sc_txtimer = 0; 845251538Srpaulo} 846251538Srpaulo 847289066Skevlostatic int 848289066Skevlourtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 849289066Skevlo int ndata, int maxsz) 850289066Skevlo{ 851289066Skevlo int i, error; 852289066Skevlo 853289066Skevlo for (i = 0; i < ndata; i++) { 854289066Skevlo struct urtwn_data *dp = &data[i]; 855289066Skevlo dp->sc = sc; 856289066Skevlo dp->m = NULL; 857289066Skevlo dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 858289066Skevlo if (dp->buf == NULL) { 859289066Skevlo device_printf(sc->sc_dev, 860289066Skevlo "could not allocate buffer\n"); 861289066Skevlo error = ENOMEM; 862289066Skevlo goto fail; 863289066Skevlo } 864289066Skevlo dp->ni = NULL; 865289066Skevlo } 866289066Skevlo 867289066Skevlo return (0); 868289066Skevlofail: 869289066Skevlo urtwn_free_list(sc, data, ndata); 870289066Skevlo return (error); 871289066Skevlo} 872289066Skevlo 873289066Skevlostatic int 874289066Skevlourtwn_alloc_rx_list(struct urtwn_softc *sc) 875289066Skevlo{ 876289066Skevlo int error, i; 877289066Skevlo 878289066Skevlo error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 879289066Skevlo URTWN_RXBUFSZ); 880289066Skevlo if (error != 0) 881289066Skevlo return (error); 882289066Skevlo 883289066Skevlo STAILQ_INIT(&sc->sc_rx_active); 884289066Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 885289066Skevlo 886289066Skevlo for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 887289066Skevlo STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 888289066Skevlo 889289066Skevlo return (0); 890289066Skevlo} 891289066Skevlo 892289066Skevlostatic int 893289066Skevlourtwn_alloc_tx_list(struct urtwn_softc *sc) 894289066Skevlo{ 895289066Skevlo int error, i; 896289066Skevlo 897289066Skevlo error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 898289066Skevlo URTWN_TXBUFSZ); 899289066Skevlo if (error != 0) 900289066Skevlo return (error); 901289066Skevlo 902289066Skevlo STAILQ_INIT(&sc->sc_tx_active); 903289066Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 904289066Skevlo STAILQ_INIT(&sc->sc_tx_pending); 905289066Skevlo 906289066Skevlo for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 907289066Skevlo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 908289066Skevlo 909289066Skevlo return (0); 910289066Skevlo} 911289066Skevlo 912251538Srpaulostatic void 913289066Skevlourtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 914289066Skevlo{ 915289066Skevlo int i; 916289066Skevlo 917289066Skevlo for (i = 0; i < ndata; i++) { 918289066Skevlo struct urtwn_data *dp = &data[i]; 919289066Skevlo 920289066Skevlo if (dp->buf != NULL) { 921289066Skevlo free(dp->buf, M_USBDEV); 922289066Skevlo dp->buf = NULL; 923289066Skevlo } 924289066Skevlo if (dp->ni != NULL) { 925289066Skevlo ieee80211_free_node(dp->ni); 926289066Skevlo dp->ni = NULL; 927289066Skevlo } 928289066Skevlo } 929289066Skevlo} 930289066Skevlo 931289066Skevlostatic void 932289066Skevlourtwn_free_rx_list(struct urtwn_softc *sc) 933289066Skevlo{ 934289066Skevlo urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 935289066Skevlo} 936289066Skevlo 937289066Skevlostatic void 938289066Skevlourtwn_free_tx_list(struct urtwn_softc *sc) 939289066Skevlo{ 940289066Skevlo urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 941289066Skevlo} 942289066Skevlo 943289066Skevlostatic void 944251538Srpaulourtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 945251538Srpaulo{ 946251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 947251538Srpaulo struct urtwn_data *data; 948251538Srpaulo 949251538Srpaulo URTWN_ASSERT_LOCKED(sc); 950251538Srpaulo 951251538Srpaulo switch (USB_GET_STATE(xfer)){ 952251538Srpaulo case USB_ST_TRANSFERRED: 953251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 954251538Srpaulo if (data == NULL) 955251538Srpaulo goto tr_setup; 956251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 957251538Srpaulo urtwn_txeof(xfer, data); 958251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 959251538Srpaulo /* FALLTHROUGH */ 960251538Srpaulo case USB_ST_SETUP: 961251538Srpaulotr_setup: 962251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_pending); 963251538Srpaulo if (data == NULL) { 964251538Srpaulo DPRINTF("%s: empty pending queue\n", __func__); 965288353Sadrian goto finish; 966251538Srpaulo } 967251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 968251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 969251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 970251538Srpaulo usbd_transfer_submit(xfer); 971251538Srpaulo break; 972251538Srpaulo default: 973251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 974251538Srpaulo if (data == NULL) 975251538Srpaulo goto tr_setup; 976251538Srpaulo if (data->ni != NULL) { 977287197Sglebius if_inc_counter(data->ni->ni_vap->iv_ifp, 978287197Sglebius IFCOUNTER_OERRORS, 1); 979251538Srpaulo ieee80211_free_node(data->ni); 980251538Srpaulo data->ni = NULL; 981251538Srpaulo } 982251538Srpaulo if (error != USB_ERR_CANCELLED) { 983251538Srpaulo usbd_xfer_set_stall(xfer); 984251538Srpaulo goto tr_setup; 985251538Srpaulo } 986251538Srpaulo break; 987251538Srpaulo } 988288353Sadrianfinish: 989288353Sadrian /* Kick-start more transmit */ 990288353Sadrian urtwn_start(sc); 991251538Srpaulo} 992251538Srpaulo 993251538Srpaulostatic struct urtwn_data * 994251538Srpaulo_urtwn_getbuf(struct urtwn_softc *sc) 995251538Srpaulo{ 996251538Srpaulo struct urtwn_data *bf; 997251538Srpaulo 998251538Srpaulo bf = STAILQ_FIRST(&sc->sc_tx_inactive); 999251538Srpaulo if (bf != NULL) 1000251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1001251538Srpaulo else 1002251538Srpaulo bf = NULL; 1003251538Srpaulo if (bf == NULL) 1004251538Srpaulo DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 1005251538Srpaulo return (bf); 1006251538Srpaulo} 1007251538Srpaulo 1008251538Srpaulostatic struct urtwn_data * 1009251538Srpaulourtwn_getbuf(struct urtwn_softc *sc) 1010251538Srpaulo{ 1011251538Srpaulo struct urtwn_data *bf; 1012251538Srpaulo 1013251538Srpaulo URTWN_ASSERT_LOCKED(sc); 1014251538Srpaulo 1015251538Srpaulo bf = _urtwn_getbuf(sc); 1016287197Sglebius if (bf == NULL) 1017251538Srpaulo DPRINTF("%s: stop queue\n", __func__); 1018251538Srpaulo return (bf); 1019251538Srpaulo} 1020251538Srpaulo 1021251538Srpaulostatic int 1022251538Srpaulourtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1023251538Srpaulo int len) 1024251538Srpaulo{ 1025251538Srpaulo usb_device_request_t req; 1026251538Srpaulo 1027251538Srpaulo req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1028251538Srpaulo req.bRequest = R92C_REQ_REGS; 1029251538Srpaulo USETW(req.wValue, addr); 1030251538Srpaulo USETW(req.wIndex, 0); 1031251538Srpaulo USETW(req.wLength, len); 1032251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 1033251538Srpaulo} 1034251538Srpaulo 1035251538Srpaulostatic void 1036251538Srpaulourtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1037251538Srpaulo{ 1038251538Srpaulo urtwn_write_region_1(sc, addr, &val, 1); 1039251538Srpaulo} 1040251538Srpaulo 1041251538Srpaulo 1042251538Srpaulostatic void 1043251538Srpaulourtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1044251538Srpaulo{ 1045251538Srpaulo val = htole16(val); 1046251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1047251538Srpaulo} 1048251538Srpaulo 1049251538Srpaulostatic void 1050251538Srpaulourtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1051251538Srpaulo{ 1052251538Srpaulo val = htole32(val); 1053251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1054251538Srpaulo} 1055251538Srpaulo 1056251538Srpaulostatic int 1057251538Srpaulourtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1058251538Srpaulo int len) 1059251538Srpaulo{ 1060251538Srpaulo usb_device_request_t req; 1061251538Srpaulo 1062251538Srpaulo req.bmRequestType = UT_READ_VENDOR_DEVICE; 1063251538Srpaulo req.bRequest = R92C_REQ_REGS; 1064251538Srpaulo USETW(req.wValue, addr); 1065251538Srpaulo USETW(req.wIndex, 0); 1066251538Srpaulo USETW(req.wLength, len); 1067251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 1068251538Srpaulo} 1069251538Srpaulo 1070251538Srpaulostatic uint8_t 1071251538Srpaulourtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1072251538Srpaulo{ 1073251538Srpaulo uint8_t val; 1074251538Srpaulo 1075251538Srpaulo if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1076251538Srpaulo return (0xff); 1077251538Srpaulo return (val); 1078251538Srpaulo} 1079251538Srpaulo 1080251538Srpaulostatic uint16_t 1081251538Srpaulourtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1082251538Srpaulo{ 1083251538Srpaulo uint16_t val; 1084251538Srpaulo 1085251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1086251538Srpaulo return (0xffff); 1087251538Srpaulo return (le16toh(val)); 1088251538Srpaulo} 1089251538Srpaulo 1090251538Srpaulostatic uint32_t 1091251538Srpaulourtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1092251538Srpaulo{ 1093251538Srpaulo uint32_t val; 1094251538Srpaulo 1095251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1096251538Srpaulo return (0xffffffff); 1097251538Srpaulo return (le32toh(val)); 1098251538Srpaulo} 1099251538Srpaulo 1100251538Srpaulostatic int 1101251538Srpaulourtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1102251538Srpaulo{ 1103251538Srpaulo struct r92c_fw_cmd cmd; 1104251538Srpaulo int ntries; 1105251538Srpaulo 1106251538Srpaulo /* Wait for current FW box to be empty. */ 1107251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1108251538Srpaulo if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1109251538Srpaulo break; 1110266472Shselasky urtwn_ms_delay(sc); 1111251538Srpaulo } 1112251538Srpaulo if (ntries == 100) { 1113251538Srpaulo device_printf(sc->sc_dev, 1114251538Srpaulo "could not send firmware command\n"); 1115251538Srpaulo return (ETIMEDOUT); 1116251538Srpaulo } 1117251538Srpaulo memset(&cmd, 0, sizeof(cmd)); 1118251538Srpaulo cmd.id = id; 1119251538Srpaulo if (len > 3) 1120251538Srpaulo cmd.id |= R92C_CMD_FLAG_EXT; 1121251538Srpaulo KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1122251538Srpaulo memcpy(cmd.msg, buf, len); 1123251538Srpaulo 1124251538Srpaulo /* Write the first word last since that will trigger the FW. */ 1125251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1126251538Srpaulo (uint8_t *)&cmd + 4, 2); 1127251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1128251538Srpaulo (uint8_t *)&cmd + 0, 4); 1129251538Srpaulo 1130251538Srpaulo sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1131251538Srpaulo return (0); 1132251538Srpaulo} 1133251538Srpaulo 1134264912Skevlostatic __inline void 1135251538Srpaulourtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1136251538Srpaulo{ 1137264912Skevlo 1138264912Skevlo sc->sc_rf_write(sc, chain, addr, val); 1139264912Skevlo} 1140264912Skevlo 1141264912Skevlostatic void 1142264912Skevlourtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1143264912Skevlo uint32_t val) 1144264912Skevlo{ 1145251538Srpaulo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1146251538Srpaulo SM(R92C_LSSI_PARAM_ADDR, addr) | 1147251538Srpaulo SM(R92C_LSSI_PARAM_DATA, val)); 1148251538Srpaulo} 1149251538Srpaulo 1150264912Skevlostatic void 1151264912Skevlourtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1152264912Skevlouint32_t val) 1153264912Skevlo{ 1154264912Skevlo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1155264912Skevlo SM(R88E_LSSI_PARAM_ADDR, addr) | 1156264912Skevlo SM(R92C_LSSI_PARAM_DATA, val)); 1157264912Skevlo} 1158264912Skevlo 1159251538Srpaulostatic uint32_t 1160251538Srpaulourtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1161251538Srpaulo{ 1162251538Srpaulo uint32_t reg[R92C_MAX_CHAINS], val; 1163251538Srpaulo 1164251538Srpaulo reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1165251538Srpaulo if (chain != 0) 1166251538Srpaulo reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1167251538Srpaulo 1168251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1169251538Srpaulo reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1170266472Shselasky urtwn_ms_delay(sc); 1171251538Srpaulo 1172251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1173251538Srpaulo RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1174251538Srpaulo R92C_HSSI_PARAM2_READ_EDGE); 1175266472Shselasky urtwn_ms_delay(sc); 1176251538Srpaulo 1177251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1178251538Srpaulo reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1179266472Shselasky urtwn_ms_delay(sc); 1180251538Srpaulo 1181251538Srpaulo if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1182251538Srpaulo val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1183251538Srpaulo else 1184251538Srpaulo val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1185251538Srpaulo return (MS(val, R92C_LSSI_READBACK_DATA)); 1186251538Srpaulo} 1187251538Srpaulo 1188251538Srpaulostatic int 1189251538Srpaulourtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1190251538Srpaulo{ 1191251538Srpaulo int ntries; 1192251538Srpaulo 1193251538Srpaulo urtwn_write_4(sc, R92C_LLT_INIT, 1194251538Srpaulo SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1195251538Srpaulo SM(R92C_LLT_INIT_ADDR, addr) | 1196251538Srpaulo SM(R92C_LLT_INIT_DATA, data)); 1197251538Srpaulo /* Wait for write operation to complete. */ 1198251538Srpaulo for (ntries = 0; ntries < 20; ntries++) { 1199251538Srpaulo if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1200251538Srpaulo R92C_LLT_INIT_OP_NO_ACTIVE) 1201251538Srpaulo return (0); 1202266472Shselasky urtwn_ms_delay(sc); 1203251538Srpaulo } 1204251538Srpaulo return (ETIMEDOUT); 1205251538Srpaulo} 1206251538Srpaulo 1207251538Srpaulostatic uint8_t 1208251538Srpaulourtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1209251538Srpaulo{ 1210251538Srpaulo uint32_t reg; 1211251538Srpaulo int ntries; 1212251538Srpaulo 1213251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1214251538Srpaulo reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1215251538Srpaulo reg &= ~R92C_EFUSE_CTRL_VALID; 1216251538Srpaulo urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1217251538Srpaulo /* Wait for read operation to complete. */ 1218251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1219251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1220251538Srpaulo if (reg & R92C_EFUSE_CTRL_VALID) 1221251538Srpaulo return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1222266472Shselasky urtwn_ms_delay(sc); 1223251538Srpaulo } 1224281069Srpaulo device_printf(sc->sc_dev, 1225251538Srpaulo "could not read efuse byte at address 0x%x\n", addr); 1226251538Srpaulo return (0xff); 1227251538Srpaulo} 1228251538Srpaulo 1229251538Srpaulostatic void 1230251538Srpaulourtwn_efuse_read(struct urtwn_softc *sc) 1231251538Srpaulo{ 1232251538Srpaulo uint8_t *rom = (uint8_t *)&sc->rom; 1233251538Srpaulo uint16_t addr = 0; 1234251538Srpaulo uint32_t reg; 1235282623Skevlo uint8_t off, msk; 1236251538Srpaulo int i; 1237251538Srpaulo 1238264912Skevlo urtwn_efuse_switch_power(sc); 1239264912Skevlo 1240251538Srpaulo memset(&sc->rom, 0xff, sizeof(sc->rom)); 1241251538Srpaulo while (addr < 512) { 1242251538Srpaulo reg = urtwn_efuse_read_1(sc, addr); 1243251538Srpaulo if (reg == 0xff) 1244251538Srpaulo break; 1245251538Srpaulo addr++; 1246251538Srpaulo off = reg >> 4; 1247251538Srpaulo msk = reg & 0xf; 1248251538Srpaulo for (i = 0; i < 4; i++) { 1249251538Srpaulo if (msk & (1 << i)) 1250251538Srpaulo continue; 1251251538Srpaulo rom[off * 8 + i * 2 + 0] = 1252251538Srpaulo urtwn_efuse_read_1(sc, addr); 1253251538Srpaulo addr++; 1254251538Srpaulo rom[off * 8 + i * 2 + 1] = 1255251538Srpaulo urtwn_efuse_read_1(sc, addr); 1256251538Srpaulo addr++; 1257251538Srpaulo } 1258251538Srpaulo } 1259251538Srpaulo#ifdef URTWN_DEBUG 1260251538Srpaulo if (urtwn_debug >= 2) { 1261251538Srpaulo /* Dump ROM content. */ 1262251538Srpaulo printf("\n"); 1263251538Srpaulo for (i = 0; i < sizeof(sc->rom); i++) 1264251538Srpaulo printf("%02x:", rom[i]); 1265251538Srpaulo printf("\n"); 1266251538Srpaulo } 1267251538Srpaulo#endif 1268282623Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1269282623Skevlo} 1270281592Skevlo 1271264912Skevlostatic void 1272264912Skevlourtwn_efuse_switch_power(struct urtwn_softc *sc) 1273264912Skevlo{ 1274264912Skevlo uint32_t reg; 1275251538Srpaulo 1276282623Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1277281918Skevlo 1278264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1279264912Skevlo if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1280264912Skevlo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1281264912Skevlo reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1282264912Skevlo } 1283264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1284264912Skevlo if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1285264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1286264912Skevlo reg | R92C_SYS_FUNC_EN_ELDR); 1287264912Skevlo } 1288264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1289264912Skevlo if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1290264912Skevlo (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1291264912Skevlo urtwn_write_2(sc, R92C_SYS_CLKR, 1292264912Skevlo reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1293264912Skevlo } 1294264912Skevlo} 1295264912Skevlo 1296251538Srpaulostatic int 1297251538Srpaulourtwn_read_chipid(struct urtwn_softc *sc) 1298251538Srpaulo{ 1299251538Srpaulo uint32_t reg; 1300251538Srpaulo 1301264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1302264912Skevlo return (0); 1303264912Skevlo 1304251538Srpaulo reg = urtwn_read_4(sc, R92C_SYS_CFG); 1305251538Srpaulo if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1306251538Srpaulo return (EIO); 1307251538Srpaulo 1308251538Srpaulo if (reg & R92C_SYS_CFG_TYPE_92C) { 1309251538Srpaulo sc->chip |= URTWN_CHIP_92C; 1310251538Srpaulo /* Check if it is a castrated 8192C. */ 1311251538Srpaulo if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1312251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID) == 1313251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1314251538Srpaulo sc->chip |= URTWN_CHIP_92C_1T2R; 1315251538Srpaulo } 1316251538Srpaulo if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1317251538Srpaulo sc->chip |= URTWN_CHIP_UMC; 1318251538Srpaulo if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1319251538Srpaulo sc->chip |= URTWN_CHIP_UMC_A_CUT; 1320251538Srpaulo } 1321251538Srpaulo return (0); 1322251538Srpaulo} 1323251538Srpaulo 1324251538Srpaulostatic void 1325251538Srpaulourtwn_read_rom(struct urtwn_softc *sc) 1326251538Srpaulo{ 1327251538Srpaulo struct r92c_rom *rom = &sc->rom; 1328251538Srpaulo 1329251538Srpaulo /* Read full ROM image. */ 1330251538Srpaulo urtwn_efuse_read(sc); 1331251538Srpaulo 1332251538Srpaulo /* XXX Weird but this is what the vendor driver does. */ 1333251538Srpaulo sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1334251538Srpaulo DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1335251538Srpaulo 1336251538Srpaulo sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1337251538Srpaulo 1338251538Srpaulo sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1339251538Srpaulo DPRINTF("regulatory type=%d\n", sc->regulatory); 1340287197Sglebius IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1341251538Srpaulo 1342264912Skevlo sc->sc_rf_write = urtwn_r92c_rf_write; 1343264912Skevlo sc->sc_power_on = urtwn_r92c_power_on; 1344264912Skevlo sc->sc_dma_init = urtwn_r92c_dma_init; 1345251538Srpaulo} 1346251538Srpaulo 1347264912Skevlostatic void 1348264912Skevlourtwn_r88e_read_rom(struct urtwn_softc *sc) 1349264912Skevlo{ 1350264912Skevlo uint8_t *rom = sc->r88e_rom; 1351264912Skevlo uint16_t addr = 0; 1352264912Skevlo uint32_t reg; 1353264912Skevlo uint8_t off, msk, tmp; 1354264912Skevlo int i; 1355264912Skevlo 1356264982Sandreast off = 0; 1357264912Skevlo urtwn_efuse_switch_power(sc); 1358264912Skevlo 1359264912Skevlo /* Read full ROM image. */ 1360264912Skevlo memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1361281918Skevlo while (addr < 512) { 1362264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1363264912Skevlo if (reg == 0xff) 1364264912Skevlo break; 1365264912Skevlo addr++; 1366264912Skevlo if ((reg & 0x1f) == 0x0f) { 1367264912Skevlo tmp = (reg & 0xe0) >> 5; 1368264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1369264912Skevlo if ((reg & 0x0f) != 0x0f) 1370264912Skevlo off = ((reg & 0xf0) >> 1) | tmp; 1371264912Skevlo addr++; 1372264912Skevlo } else 1373264912Skevlo off = reg >> 4; 1374264912Skevlo msk = reg & 0xf; 1375264912Skevlo for (i = 0; i < 4; i++) { 1376264912Skevlo if (msk & (1 << i)) 1377264912Skevlo continue; 1378264912Skevlo rom[off * 8 + i * 2 + 0] = 1379264912Skevlo urtwn_efuse_read_1(sc, addr); 1380264912Skevlo addr++; 1381264912Skevlo rom[off * 8 + i * 2 + 1] = 1382264912Skevlo urtwn_efuse_read_1(sc, addr); 1383264912Skevlo addr++; 1384264912Skevlo } 1385264912Skevlo } 1386264912Skevlo 1387281918Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1388281918Skevlo 1389264912Skevlo addr = 0x10; 1390264912Skevlo for (i = 0; i < 6; i++) 1391264912Skevlo sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1392264912Skevlo for (i = 0; i < 5; i++) 1393264912Skevlo sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1394264912Skevlo sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1395264912Skevlo if (sc->bw20_tx_pwr_diff & 0x08) 1396264912Skevlo sc->bw20_tx_pwr_diff |= 0xf0; 1397264912Skevlo sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1398264912Skevlo if (sc->ofdm_tx_pwr_diff & 0x08) 1399264912Skevlo sc->ofdm_tx_pwr_diff |= 0xf0; 1400264912Skevlo sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1401287197Sglebius IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &sc->r88e_rom[0xd7]); 1402264912Skevlo 1403264912Skevlo sc->sc_rf_write = urtwn_r88e_rf_write; 1404264912Skevlo sc->sc_power_on = urtwn_r88e_power_on; 1405264912Skevlo sc->sc_dma_init = urtwn_r88e_dma_init; 1406264912Skevlo} 1407264912Skevlo 1408251538Srpaulo/* 1409251538Srpaulo * Initialize rate adaptation in firmware. 1410251538Srpaulo */ 1411251538Srpaulostatic int 1412251538Srpaulourtwn_ra_init(struct urtwn_softc *sc) 1413251538Srpaulo{ 1414251538Srpaulo static const uint8_t map[] = 1415251538Srpaulo { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1416287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1417251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1418251538Srpaulo struct ieee80211_node *ni; 1419251538Srpaulo struct ieee80211_rateset *rs; 1420251538Srpaulo struct r92c_fw_cmd_macid_cfg cmd; 1421251538Srpaulo uint32_t rates, basicrates; 1422251538Srpaulo uint8_t mode; 1423251538Srpaulo int maxrate, maxbasicrate, error, i, j; 1424251538Srpaulo 1425251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1426251538Srpaulo rs = &ni->ni_rates; 1427251538Srpaulo 1428251538Srpaulo /* Get normal and basic rates mask. */ 1429251538Srpaulo rates = basicrates = 0; 1430251538Srpaulo maxrate = maxbasicrate = 0; 1431251538Srpaulo for (i = 0; i < rs->rs_nrates; i++) { 1432251538Srpaulo /* Convert 802.11 rate to HW rate index. */ 1433251538Srpaulo for (j = 0; j < nitems(map); j++) 1434251538Srpaulo if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1435251538Srpaulo break; 1436251538Srpaulo if (j == nitems(map)) /* Unknown rate, skip. */ 1437251538Srpaulo continue; 1438251538Srpaulo rates |= 1 << j; 1439251538Srpaulo if (j > maxrate) 1440251538Srpaulo maxrate = j; 1441251538Srpaulo if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1442251538Srpaulo basicrates |= 1 << j; 1443251538Srpaulo if (j > maxbasicrate) 1444251538Srpaulo maxbasicrate = j; 1445251538Srpaulo } 1446251538Srpaulo } 1447251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1448251538Srpaulo mode = R92C_RAID_11B; 1449251538Srpaulo else 1450251538Srpaulo mode = R92C_RAID_11BG; 1451251538Srpaulo DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1452251538Srpaulo mode, rates, basicrates); 1453251538Srpaulo 1454251538Srpaulo /* Set rates mask for group addressed frames. */ 1455251538Srpaulo cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1456251538Srpaulo cmd.mask = htole32(mode << 28 | basicrates); 1457251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1458251538Srpaulo if (error != 0) { 1459252401Srpaulo ieee80211_free_node(ni); 1460251538Srpaulo device_printf(sc->sc_dev, 1461251538Srpaulo "could not add broadcast station\n"); 1462251538Srpaulo return (error); 1463251538Srpaulo } 1464251538Srpaulo /* Set initial MRR rate. */ 1465251538Srpaulo DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1466251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1467251538Srpaulo maxbasicrate); 1468251538Srpaulo 1469251538Srpaulo /* Set rates mask for unicast frames. */ 1470251538Srpaulo cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1471251538Srpaulo cmd.mask = htole32(mode << 28 | rates); 1472251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1473251538Srpaulo if (error != 0) { 1474252401Srpaulo ieee80211_free_node(ni); 1475251538Srpaulo device_printf(sc->sc_dev, "could not add BSS station\n"); 1476251538Srpaulo return (error); 1477251538Srpaulo } 1478251538Srpaulo /* Set initial MRR rate. */ 1479251538Srpaulo DPRINTF("maxrate=%d\n", maxrate); 1480251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1481251538Srpaulo maxrate); 1482251538Srpaulo 1483251538Srpaulo /* Indicate highest supported rate. */ 1484252403Srpaulo ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1485252401Srpaulo ieee80211_free_node(ni); 1486252401Srpaulo 1487251538Srpaulo return (0); 1488251538Srpaulo} 1489251538Srpaulo 1490251538Srpaulovoid 1491251538Srpaulourtwn_tsf_sync_enable(struct urtwn_softc *sc) 1492251538Srpaulo{ 1493287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1494251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1495251538Srpaulo struct ieee80211_node *ni = vap->iv_bss; 1496251538Srpaulo 1497251538Srpaulo uint64_t tsf; 1498251538Srpaulo 1499251538Srpaulo /* Enable TSF synchronization. */ 1500251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1501251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1502251538Srpaulo 1503251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1504251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1505251538Srpaulo 1506251538Srpaulo /* Set initial TSF. */ 1507251538Srpaulo memcpy(&tsf, ni->ni_tstamp.data, 8); 1508251538Srpaulo tsf = le64toh(tsf); 1509251538Srpaulo tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1510251538Srpaulo tsf -= IEEE80211_DUR_TU; 1511251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1512251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1513251538Srpaulo 1514251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1515251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1516251538Srpaulo} 1517251538Srpaulo 1518251538Srpaulostatic void 1519251538Srpaulourtwn_set_led(struct urtwn_softc *sc, int led, int on) 1520251538Srpaulo{ 1521251538Srpaulo uint8_t reg; 1522281069Srpaulo 1523251538Srpaulo if (led == URTWN_LED_LINK) { 1524264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 1525264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1526264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1527264912Skevlo if (!on) { 1528264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1529264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, 1530264912Skevlo reg | R92C_LEDCFG0_DIS); 1531264912Skevlo urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1532264912Skevlo urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1533264912Skevlo 0xfe); 1534264912Skevlo } 1535264912Skevlo } else { 1536264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1537264912Skevlo if (!on) 1538264912Skevlo reg |= R92C_LEDCFG0_DIS; 1539264912Skevlo urtwn_write_1(sc, R92C_LEDCFG0, reg); 1540264912Skevlo } 1541264912Skevlo sc->ledlink = on; /* Save LED state. */ 1542251538Srpaulo } 1543251538Srpaulo} 1544251538Srpaulo 1545251538Srpaulostatic int 1546251538Srpaulourtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1547251538Srpaulo{ 1548251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 1549251538Srpaulo struct ieee80211com *ic = vap->iv_ic; 1550286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 1551251538Srpaulo struct ieee80211_node *ni; 1552251538Srpaulo enum ieee80211_state ostate; 1553251538Srpaulo uint32_t reg; 1554251538Srpaulo 1555251538Srpaulo ostate = vap->iv_state; 1556251538Srpaulo DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1557251538Srpaulo ieee80211_state_name[nstate]); 1558251538Srpaulo 1559251538Srpaulo IEEE80211_UNLOCK(ic); 1560251538Srpaulo URTWN_LOCK(sc); 1561251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 1562251538Srpaulo 1563251538Srpaulo if (ostate == IEEE80211_S_RUN) { 1564251538Srpaulo /* Turn link LED off. */ 1565251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1566251538Srpaulo 1567251538Srpaulo /* Set media status to 'No Link'. */ 1568251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 1569251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1570251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 1571251538Srpaulo 1572251538Srpaulo /* Stop Rx of data frames. */ 1573251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1574251538Srpaulo 1575251538Srpaulo /* Rest TSF. */ 1576251538Srpaulo urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1577251538Srpaulo 1578251538Srpaulo /* Disable TSF synchronization. */ 1579251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1580251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | 1581251538Srpaulo R92C_BCN_CTRL_DIS_TSF_UDT0); 1582251538Srpaulo 1583251538Srpaulo /* Reset EDCA parameters. */ 1584251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1585251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1586251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1587251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1588251538Srpaulo } 1589251538Srpaulo 1590251538Srpaulo switch (nstate) { 1591251538Srpaulo case IEEE80211_S_INIT: 1592251538Srpaulo /* Turn link LED off. */ 1593251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1594251538Srpaulo break; 1595251538Srpaulo case IEEE80211_S_SCAN: 1596251538Srpaulo if (ostate != IEEE80211_S_SCAN) { 1597251538Srpaulo /* Allow Rx from any BSSID. */ 1598251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1599251538Srpaulo urtwn_read_4(sc, R92C_RCR) & 1600251538Srpaulo ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1601251538Srpaulo 1602251538Srpaulo /* Set gain for scanning. */ 1603251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1604251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1605251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1606251538Srpaulo 1607264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1608264912Skevlo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1609264912Skevlo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1610264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1611264912Skevlo } 1612251538Srpaulo } 1613251538Srpaulo /* Pause AC Tx queues. */ 1614251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 1615251538Srpaulo urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1616251538Srpaulo break; 1617251538Srpaulo case IEEE80211_S_AUTH: 1618251538Srpaulo /* Set initial gain under link. */ 1619251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1620251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1621251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1622251538Srpaulo 1623264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1624264912Skevlo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1625264912Skevlo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1626264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1627264912Skevlo } 1628251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 1629251538Srpaulo break; 1630251538Srpaulo case IEEE80211_S_RUN: 1631251538Srpaulo if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1632251538Srpaulo /* Enable Rx of data frames. */ 1633251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1634251538Srpaulo 1635289173Skevlo /* Enable Rx of ctrl frames. */ 1636289173Skevlo urtwn_write_2(sc, R92C_RXFLTMAP1, 0xffff); 1637289173Skevlo 1638289173Skevlo /* 1639289173Skevlo * Accept data/control/management frames 1640289173Skevlo * from any BSSID. 1641289173Skevlo */ 1642289173Skevlo urtwn_write_4(sc, R92C_RCR, 1643289173Skevlo (urtwn_read_4(sc, R92C_RCR) & ~(R92C_RCR_APM | 1644289173Skevlo R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)) | 1645289173Skevlo R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF | 1646289173Skevlo R92C_RCR_AAP); 1647289173Skevlo 1648251538Srpaulo /* Turn link LED on. */ 1649251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1650251538Srpaulo break; 1651251538Srpaulo } 1652251538Srpaulo 1653251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1654251538Srpaulo /* Set media status to 'Associated'. */ 1655251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 1656251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1657251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 1658251538Srpaulo 1659251538Srpaulo /* Set BSSID. */ 1660251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1661251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1662251538Srpaulo 1663251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1664251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1665251538Srpaulo else /* 802.11b/g */ 1666251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1667251538Srpaulo 1668251538Srpaulo /* Enable Rx of data frames. */ 1669251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1670251538Srpaulo 1671251538Srpaulo /* Flush all AC queues. */ 1672251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0); 1673251538Srpaulo 1674251538Srpaulo /* Set beacon interval. */ 1675251538Srpaulo urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1676251538Srpaulo 1677251538Srpaulo /* Allow Rx from our BSSID only. */ 1678251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1679251538Srpaulo urtwn_read_4(sc, R92C_RCR) | 1680251538Srpaulo R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1681251538Srpaulo 1682251538Srpaulo /* Enable TSF synchronization. */ 1683251538Srpaulo urtwn_tsf_sync_enable(sc); 1684251538Srpaulo 1685251538Srpaulo urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1686251538Srpaulo urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1687251538Srpaulo urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1688251538Srpaulo urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1689251538Srpaulo urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1690251538Srpaulo urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1691251538Srpaulo 1692251538Srpaulo /* Intialize rate adaptation. */ 1693264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1694264912Skevlo ni->ni_txrate = 1695264912Skevlo ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1696281069Srpaulo else 1697264912Skevlo urtwn_ra_init(sc); 1698251538Srpaulo /* Turn link LED on. */ 1699251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1700251538Srpaulo 1701251538Srpaulo sc->avg_pwdb = -1; /* Reset average RSSI. */ 1702251538Srpaulo /* Reset temperature calibration state machine. */ 1703251538Srpaulo sc->thcal_state = 0; 1704251538Srpaulo sc->thcal_lctemp = 0; 1705251538Srpaulo ieee80211_free_node(ni); 1706251538Srpaulo break; 1707251538Srpaulo default: 1708251538Srpaulo break; 1709251538Srpaulo } 1710251538Srpaulo URTWN_UNLOCK(sc); 1711251538Srpaulo IEEE80211_LOCK(ic); 1712251538Srpaulo return(uvp->newstate(vap, nstate, arg)); 1713251538Srpaulo} 1714251538Srpaulo 1715251538Srpaulostatic void 1716251538Srpaulourtwn_watchdog(void *arg) 1717251538Srpaulo{ 1718251538Srpaulo struct urtwn_softc *sc = arg; 1719251538Srpaulo 1720251538Srpaulo if (sc->sc_txtimer > 0) { 1721251538Srpaulo if (--sc->sc_txtimer == 0) { 1722251538Srpaulo device_printf(sc->sc_dev, "device timeout\n"); 1723287197Sglebius counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1724251538Srpaulo return; 1725251538Srpaulo } 1726251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1727251538Srpaulo } 1728251538Srpaulo} 1729251538Srpaulo 1730251538Srpaulostatic void 1731251538Srpaulourtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1732251538Srpaulo{ 1733251538Srpaulo int pwdb; 1734251538Srpaulo 1735251538Srpaulo /* Convert antenna signal to percentage. */ 1736251538Srpaulo if (rssi <= -100 || rssi >= 20) 1737251538Srpaulo pwdb = 0; 1738251538Srpaulo else if (rssi >= 0) 1739251538Srpaulo pwdb = 100; 1740251538Srpaulo else 1741251538Srpaulo pwdb = 100 + rssi; 1742264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1743264912Skevlo if (rate <= 3) { 1744264912Skevlo /* CCK gain is smaller than OFDM/MCS gain. */ 1745264912Skevlo pwdb += 6; 1746264912Skevlo if (pwdb > 100) 1747264912Skevlo pwdb = 100; 1748264912Skevlo if (pwdb <= 14) 1749264912Skevlo pwdb -= 4; 1750264912Skevlo else if (pwdb <= 26) 1751264912Skevlo pwdb -= 8; 1752264912Skevlo else if (pwdb <= 34) 1753264912Skevlo pwdb -= 6; 1754264912Skevlo else if (pwdb <= 42) 1755264912Skevlo pwdb -= 2; 1756264912Skevlo } 1757251538Srpaulo } 1758251538Srpaulo if (sc->avg_pwdb == -1) /* Init. */ 1759251538Srpaulo sc->avg_pwdb = pwdb; 1760251538Srpaulo else if (sc->avg_pwdb < pwdb) 1761251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1762251538Srpaulo else 1763251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1764251538Srpaulo DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1765251538Srpaulo} 1766251538Srpaulo 1767251538Srpaulostatic int8_t 1768251538Srpaulourtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1769251538Srpaulo{ 1770251538Srpaulo static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1771251538Srpaulo struct r92c_rx_phystat *phy; 1772251538Srpaulo struct r92c_rx_cck *cck; 1773251538Srpaulo uint8_t rpt; 1774251538Srpaulo int8_t rssi; 1775251538Srpaulo 1776251538Srpaulo if (rate <= 3) { 1777251538Srpaulo cck = (struct r92c_rx_cck *)physt; 1778251538Srpaulo if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1779251538Srpaulo rpt = (cck->agc_rpt >> 5) & 0x3; 1780251538Srpaulo rssi = (cck->agc_rpt & 0x1f) << 1; 1781251538Srpaulo } else { 1782251538Srpaulo rpt = (cck->agc_rpt >> 6) & 0x3; 1783251538Srpaulo rssi = cck->agc_rpt & 0x3e; 1784251538Srpaulo } 1785251538Srpaulo rssi = cckoff[rpt] - rssi; 1786251538Srpaulo } else { /* OFDM/HT. */ 1787251538Srpaulo phy = (struct r92c_rx_phystat *)physt; 1788251538Srpaulo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1789251538Srpaulo } 1790251538Srpaulo return (rssi); 1791251538Srpaulo} 1792251538Srpaulo 1793264912Skevlostatic int8_t 1794264912Skevlourtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1795264912Skevlo{ 1796264912Skevlo struct r92c_rx_phystat *phy; 1797264912Skevlo struct r88e_rx_cck *cck; 1798264912Skevlo uint8_t cck_agc_rpt, lna_idx, vga_idx; 1799264912Skevlo int8_t rssi; 1800264912Skevlo 1801264972Skevlo rssi = 0; 1802264912Skevlo if (rate <= 3) { 1803264912Skevlo cck = (struct r88e_rx_cck *)physt; 1804264912Skevlo cck_agc_rpt = cck->agc_rpt; 1805264912Skevlo lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1806281069Srpaulo vga_idx = cck_agc_rpt & 0x1f; 1807264912Skevlo switch (lna_idx) { 1808264912Skevlo case 7: 1809264912Skevlo if (vga_idx <= 27) 1810264912Skevlo rssi = -100 + 2* (27 - vga_idx); 1811264912Skevlo else 1812264912Skevlo rssi = -100; 1813264912Skevlo break; 1814264912Skevlo case 6: 1815264912Skevlo rssi = -48 + 2 * (2 - vga_idx); 1816264912Skevlo break; 1817264912Skevlo case 5: 1818264912Skevlo rssi = -42 + 2 * (7 - vga_idx); 1819264912Skevlo break; 1820264912Skevlo case 4: 1821264912Skevlo rssi = -36 + 2 * (7 - vga_idx); 1822264912Skevlo break; 1823264912Skevlo case 3: 1824264912Skevlo rssi = -24 + 2 * (7 - vga_idx); 1825264912Skevlo break; 1826264912Skevlo case 2: 1827264912Skevlo rssi = -12 + 2 * (5 - vga_idx); 1828264912Skevlo break; 1829264912Skevlo case 1: 1830264912Skevlo rssi = 8 - (2 * vga_idx); 1831264912Skevlo break; 1832264912Skevlo case 0: 1833264912Skevlo rssi = 14 - (2 * vga_idx); 1834264912Skevlo break; 1835264912Skevlo } 1836264912Skevlo rssi += 6; 1837264912Skevlo } else { /* OFDM/HT. */ 1838264912Skevlo phy = (struct r92c_rx_phystat *)physt; 1839264912Skevlo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1840264912Skevlo } 1841264912Skevlo return (rssi); 1842264912Skevlo} 1843264912Skevlo 1844251538Srpaulostatic int 1845281069Srpaulourtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1846251538Srpaulo struct mbuf *m0, struct urtwn_data *data) 1847251538Srpaulo{ 1848251538Srpaulo struct ieee80211_frame *wh; 1849251538Srpaulo struct ieee80211_key *k; 1850287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1851251538Srpaulo struct ieee80211vap *vap = ni->ni_vap; 1852251538Srpaulo struct usb_xfer *xfer; 1853251538Srpaulo struct r92c_tx_desc *txd; 1854251538Srpaulo uint8_t raid, type; 1855251538Srpaulo uint16_t sum; 1856288534Sadrian int i, xferlen; 1857251538Srpaulo struct usb_xfer *urtwn_pipes[4] = { 1858251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BE], 1859251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BK], 1860251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VI], 1861251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VO] 1862251538Srpaulo }; 1863251538Srpaulo 1864251538Srpaulo URTWN_ASSERT_LOCKED(sc); 1865251538Srpaulo 1866251538Srpaulo /* 1867251538Srpaulo * Software crypto. 1868251538Srpaulo */ 1869251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1870264912Skevlo type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1871264912Skevlo 1872260444Skevlo if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1873251538Srpaulo k = ieee80211_crypto_encap(ni, m0); 1874251538Srpaulo if (k == NULL) { 1875251538Srpaulo device_printf(sc->sc_dev, 1876251538Srpaulo "ieee80211_crypto_encap returns NULL.\n"); 1877251538Srpaulo /* XXX we don't expect the fragmented frames */ 1878251538Srpaulo return (ENOBUFS); 1879251538Srpaulo } 1880251538Srpaulo 1881251538Srpaulo /* in case packet header moved, reset pointer */ 1882251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1883251538Srpaulo } 1884281069Srpaulo 1885264912Skevlo switch (type) { 1886251538Srpaulo case IEEE80211_FC0_TYPE_CTL: 1887251538Srpaulo case IEEE80211_FC0_TYPE_MGT: 1888251538Srpaulo xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1889251538Srpaulo break; 1890251538Srpaulo default: 1891251538Srpaulo KASSERT(M_WME_GETAC(m0) < 4, 1892251538Srpaulo ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1893251538Srpaulo xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1894251538Srpaulo break; 1895251538Srpaulo } 1896281069Srpaulo 1897251538Srpaulo /* Fill Tx descriptor. */ 1898251538Srpaulo txd = (struct r92c_tx_desc *)data->buf; 1899251538Srpaulo memset(txd, 0, sizeof(*txd)); 1900251538Srpaulo 1901251538Srpaulo txd->txdw0 |= htole32( 1902251538Srpaulo SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1903251538Srpaulo SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1904251538Srpaulo R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1905251538Srpaulo if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1906251538Srpaulo txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1907251538Srpaulo if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1908251538Srpaulo type == IEEE80211_FC0_TYPE_DATA) { 1909251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1910251538Srpaulo raid = R92C_RAID_11B; 1911251538Srpaulo else 1912251538Srpaulo raid = R92C_RAID_11BG; 1913264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 1914264912Skevlo txd->txdw1 |= htole32( 1915264912Skevlo SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1916264912Skevlo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1917264912Skevlo SM(R92C_TXDW1_RAID, raid)); 1918264912Skevlo txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1919264912Skevlo } else { 1920264912Skevlo txd->txdw1 |= htole32( 1921264912Skevlo SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1922264912Skevlo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1923264912Skevlo SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1924264912Skevlo } 1925251538Srpaulo if (ic->ic_flags & IEEE80211_F_USEPROT) { 1926251538Srpaulo if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1927251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1928251538Srpaulo R92C_TXDW4_HWRTSEN); 1929251538Srpaulo } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1930251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1931251538Srpaulo R92C_TXDW4_HWRTSEN); 1932251538Srpaulo } 1933251538Srpaulo } 1934251538Srpaulo /* Send RTS at OFDM24. */ 1935251538Srpaulo txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1936251538Srpaulo txd->txdw5 |= htole32(0x0001ff00); 1937251538Srpaulo /* Send data at OFDM54. */ 1938282623Skevlo txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1939251538Srpaulo } else { 1940251538Srpaulo txd->txdw1 |= htole32( 1941251538Srpaulo SM(R92C_TXDW1_MACID, 0) | 1942251538Srpaulo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1943251538Srpaulo SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1944251538Srpaulo 1945251538Srpaulo /* Force CCK1. */ 1946251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1947251538Srpaulo txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1948251538Srpaulo } 1949251538Srpaulo /* Set sequence number (already little endian). */ 1950251538Srpaulo txd->txdseq |= *(uint16_t *)wh->i_seq; 1951251538Srpaulo 1952288534Sadrian if (!IEEE80211_QOS_HAS_SEQ(wh)) { 1953251538Srpaulo /* Use HW sequence numbering for non-QoS frames. */ 1954251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1955251538Srpaulo txd->txdseq |= htole16(0x8000); 1956251538Srpaulo } else 1957251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1958251538Srpaulo 1959251538Srpaulo /* Compute Tx descriptor checksum. */ 1960251538Srpaulo sum = 0; 1961251538Srpaulo for (i = 0; i < sizeof(*txd) / 2; i++) 1962251538Srpaulo sum ^= ((uint16_t *)txd)[i]; 1963251538Srpaulo txd->txdsum = sum; /* NB: already little endian. */ 1964251538Srpaulo 1965251538Srpaulo if (ieee80211_radiotap_active_vap(vap)) { 1966251538Srpaulo struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1967251538Srpaulo 1968251538Srpaulo tap->wt_flags = 0; 1969251538Srpaulo tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1970251538Srpaulo tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1971251538Srpaulo ieee80211_radiotap_tx(vap, m0); 1972251538Srpaulo } 1973251538Srpaulo 1974251538Srpaulo xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1975251538Srpaulo m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1976251538Srpaulo 1977251538Srpaulo data->buflen = xferlen; 1978251538Srpaulo data->ni = ni; 1979251538Srpaulo data->m = m0; 1980251538Srpaulo 1981251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1982251538Srpaulo usbd_transfer_start(xfer); 1983251538Srpaulo return (0); 1984251538Srpaulo} 1985251538Srpaulo 1986287197Sglebiusstatic int 1987287197Sglebiusurtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1988251538Srpaulo{ 1989287197Sglebius struct urtwn_softc *sc = ic->ic_softc; 1990287197Sglebius int error; 1991261863Srpaulo 1992261863Srpaulo URTWN_LOCK(sc); 1993287197Sglebius if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1994287197Sglebius URTWN_UNLOCK(sc); 1995287197Sglebius return (ENXIO); 1996287197Sglebius } 1997287197Sglebius error = mbufq_enqueue(&sc->sc_snd, m); 1998287197Sglebius if (error) { 1999287197Sglebius URTWN_UNLOCK(sc); 2000287197Sglebius return (error); 2001287197Sglebius } 2002287197Sglebius urtwn_start(sc); 2003261863Srpaulo URTWN_UNLOCK(sc); 2004287197Sglebius 2005287197Sglebius return (0); 2006261863Srpaulo} 2007261863Srpaulo 2008261863Srpaulostatic void 2009287197Sglebiusurtwn_start(struct urtwn_softc *sc) 2010261863Srpaulo{ 2011251538Srpaulo struct ieee80211_node *ni; 2012251538Srpaulo struct mbuf *m; 2013251538Srpaulo struct urtwn_data *bf; 2014251538Srpaulo 2015261863Srpaulo URTWN_ASSERT_LOCKED(sc); 2016287197Sglebius while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2017251538Srpaulo bf = urtwn_getbuf(sc); 2018251538Srpaulo if (bf == NULL) { 2019287197Sglebius mbufq_prepend(&sc->sc_snd, m); 2020251538Srpaulo break; 2021251538Srpaulo } 2022251538Srpaulo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2023251538Srpaulo m->m_pkthdr.rcvif = NULL; 2024251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 2025287197Sglebius if_inc_counter(ni->ni_vap->iv_ifp, 2026287197Sglebius IFCOUNTER_OERRORS, 1); 2027251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2028288353Sadrian m_freem(m); 2029251538Srpaulo ieee80211_free_node(ni); 2030251538Srpaulo break; 2031251538Srpaulo } 2032251538Srpaulo sc->sc_txtimer = 5; 2033251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2034251538Srpaulo } 2035251538Srpaulo} 2036251538Srpaulo 2037287197Sglebiusstatic void 2038287197Sglebiusurtwn_parent(struct ieee80211com *ic) 2039251538Srpaulo{ 2040286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 2041287197Sglebius int startall = 0; 2042251538Srpaulo 2043263153Skevlo URTWN_LOCK(sc); 2044287197Sglebius if (sc->sc_flags & URTWN_DETACHED) { 2045287197Sglebius URTWN_UNLOCK(sc); 2046287197Sglebius return; 2047287197Sglebius } 2048287197Sglebius if (ic->ic_nrunning > 0) { 2049287197Sglebius if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2050287197Sglebius urtwn_init(sc); 2051287197Sglebius startall = 1; 2052287197Sglebius } 2053287197Sglebius } else if (sc->sc_flags & URTWN_RUNNING) 2054287197Sglebius urtwn_stop(sc); 2055263153Skevlo URTWN_UNLOCK(sc); 2056263153Skevlo 2057287197Sglebius if (startall) 2058287197Sglebius ieee80211_start_all(ic); 2059251538Srpaulo} 2060251538Srpaulo 2061264912Skevlostatic __inline int 2062251538Srpaulourtwn_power_on(struct urtwn_softc *sc) 2063251538Srpaulo{ 2064264912Skevlo 2065264912Skevlo return sc->sc_power_on(sc); 2066264912Skevlo} 2067264912Skevlo 2068264912Skevlostatic int 2069264912Skevlourtwn_r92c_power_on(struct urtwn_softc *sc) 2070264912Skevlo{ 2071251538Srpaulo uint32_t reg; 2072251538Srpaulo int ntries; 2073251538Srpaulo 2074251538Srpaulo /* Wait for autoload done bit. */ 2075251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2076251538Srpaulo if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2077251538Srpaulo break; 2078266472Shselasky urtwn_ms_delay(sc); 2079251538Srpaulo } 2080251538Srpaulo if (ntries == 1000) { 2081251538Srpaulo device_printf(sc->sc_dev, 2082251538Srpaulo "timeout waiting for chip autoload\n"); 2083251538Srpaulo return (ETIMEDOUT); 2084251538Srpaulo } 2085251538Srpaulo 2086251538Srpaulo /* Unlock ISO/CLK/Power control register. */ 2087251538Srpaulo urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2088251538Srpaulo /* Move SPS into PWM mode. */ 2089251538Srpaulo urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2090266472Shselasky urtwn_ms_delay(sc); 2091251538Srpaulo 2092251538Srpaulo reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2093251538Srpaulo if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2094251538Srpaulo urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2095251538Srpaulo reg | R92C_LDOV12D_CTRL_LDV12_EN); 2096266472Shselasky urtwn_ms_delay(sc); 2097251538Srpaulo urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2098251538Srpaulo urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2099251538Srpaulo ~R92C_SYS_ISO_CTRL_MD2PP); 2100251538Srpaulo } 2101251538Srpaulo 2102251538Srpaulo /* Auto enable WLAN. */ 2103251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2104251538Srpaulo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2105251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2106262822Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2107262822Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2108251538Srpaulo break; 2109266472Shselasky urtwn_ms_delay(sc); 2110251538Srpaulo } 2111251538Srpaulo if (ntries == 1000) { 2112251538Srpaulo device_printf(sc->sc_dev, 2113251538Srpaulo "timeout waiting for MAC auto ON\n"); 2114251538Srpaulo return (ETIMEDOUT); 2115251538Srpaulo } 2116251538Srpaulo 2117251538Srpaulo /* Enable radio, GPIO and LED functions. */ 2118251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2119251538Srpaulo R92C_APS_FSMCO_AFSM_HSUS | 2120251538Srpaulo R92C_APS_FSMCO_PDN_EN | 2121251538Srpaulo R92C_APS_FSMCO_PFM_ALDN); 2122251538Srpaulo /* Release RF digital isolation. */ 2123251538Srpaulo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2124251538Srpaulo urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2125251538Srpaulo 2126251538Srpaulo /* Initialize MAC. */ 2127251538Srpaulo urtwn_write_1(sc, R92C_APSD_CTRL, 2128251538Srpaulo urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2129251538Srpaulo for (ntries = 0; ntries < 200; ntries++) { 2130251538Srpaulo if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2131251538Srpaulo R92C_APSD_CTRL_OFF_STATUS)) 2132251538Srpaulo break; 2133266472Shselasky urtwn_ms_delay(sc); 2134251538Srpaulo } 2135251538Srpaulo if (ntries == 200) { 2136251538Srpaulo device_printf(sc->sc_dev, 2137251538Srpaulo "timeout waiting for MAC initialization\n"); 2138251538Srpaulo return (ETIMEDOUT); 2139251538Srpaulo } 2140251538Srpaulo 2141251538Srpaulo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2142251538Srpaulo reg = urtwn_read_2(sc, R92C_CR); 2143251538Srpaulo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2144251538Srpaulo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2145251538Srpaulo R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2146251538Srpaulo R92C_CR_ENSEC; 2147251538Srpaulo urtwn_write_2(sc, R92C_CR, reg); 2148251538Srpaulo 2149251538Srpaulo urtwn_write_1(sc, 0xfe10, 0x19); 2150251538Srpaulo return (0); 2151251538Srpaulo} 2152251538Srpaulo 2153251538Srpaulostatic int 2154264912Skevlourtwn_r88e_power_on(struct urtwn_softc *sc) 2155264912Skevlo{ 2156264912Skevlo uint32_t reg; 2157264912Skevlo int ntries; 2158264912Skevlo 2159264912Skevlo /* Wait for power ready bit. */ 2160264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2161281918Skevlo if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2162264912Skevlo break; 2163266472Shselasky urtwn_ms_delay(sc); 2164264912Skevlo } 2165264912Skevlo if (ntries == 5000) { 2166264912Skevlo device_printf(sc->sc_dev, 2167264912Skevlo "timeout waiting for chip power up\n"); 2168264912Skevlo return (ETIMEDOUT); 2169264912Skevlo } 2170264912Skevlo 2171264912Skevlo /* Reset BB. */ 2172264912Skevlo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2173264912Skevlo urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2174264912Skevlo R92C_SYS_FUNC_EN_BB_GLB_RST)); 2175264912Skevlo 2176281918Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2177281918Skevlo urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2178264912Skevlo 2179264912Skevlo /* Disable HWPDN. */ 2180281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2181281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2182264912Skevlo 2183264912Skevlo /* Disable WL suspend. */ 2184281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2185281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & 2186281918Skevlo ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2187264912Skevlo 2188281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2189281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2190264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2191281918Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2192281918Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2193264912Skevlo break; 2194266472Shselasky urtwn_ms_delay(sc); 2195264912Skevlo } 2196264912Skevlo if (ntries == 5000) 2197264912Skevlo return (ETIMEDOUT); 2198264912Skevlo 2199264912Skevlo /* Enable LDO normal mode. */ 2200281918Skevlo urtwn_write_1(sc, R92C_LPLDO_CTRL, 2201281918Skevlo urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2202264912Skevlo 2203264912Skevlo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2204264912Skevlo urtwn_write_2(sc, R92C_CR, 0); 2205264912Skevlo reg = urtwn_read_2(sc, R92C_CR); 2206264912Skevlo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2207264912Skevlo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2208264912Skevlo R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2209264912Skevlo urtwn_write_2(sc, R92C_CR, reg); 2210264912Skevlo 2211264912Skevlo return (0); 2212264912Skevlo} 2213264912Skevlo 2214264912Skevlostatic int 2215251538Srpaulourtwn_llt_init(struct urtwn_softc *sc) 2216251538Srpaulo{ 2217264912Skevlo int i, error, page_count, pktbuf_count; 2218251538Srpaulo 2219264912Skevlo page_count = (sc->chip & URTWN_CHIP_88E) ? 2220264912Skevlo R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2221264912Skevlo pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2222264912Skevlo R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2223264912Skevlo 2224264912Skevlo /* Reserve pages [0; page_count]. */ 2225264912Skevlo for (i = 0; i < page_count; i++) { 2226251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2227251538Srpaulo return (error); 2228251538Srpaulo } 2229251538Srpaulo /* NB: 0xff indicates end-of-list. */ 2230251538Srpaulo if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2231251538Srpaulo return (error); 2232251538Srpaulo /* 2233264912Skevlo * Use pages [page_count + 1; pktbuf_count - 1] 2234251538Srpaulo * as ring buffer. 2235251538Srpaulo */ 2236264912Skevlo for (++i; i < pktbuf_count - 1; i++) { 2237251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2238251538Srpaulo return (error); 2239251538Srpaulo } 2240251538Srpaulo /* Make the last page point to the beginning of the ring buffer. */ 2241264912Skevlo error = urtwn_llt_write(sc, i, page_count + 1); 2242251538Srpaulo return (error); 2243251538Srpaulo} 2244251538Srpaulo 2245251538Srpaulostatic void 2246251538Srpaulourtwn_fw_reset(struct urtwn_softc *sc) 2247251538Srpaulo{ 2248251538Srpaulo uint16_t reg; 2249251538Srpaulo int ntries; 2250251538Srpaulo 2251251538Srpaulo /* Tell 8051 to reset itself. */ 2252251538Srpaulo urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2253251538Srpaulo 2254251538Srpaulo /* Wait until 8051 resets by itself. */ 2255251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 2256251538Srpaulo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2257251538Srpaulo if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2258251538Srpaulo return; 2259266472Shselasky urtwn_ms_delay(sc); 2260251538Srpaulo } 2261251538Srpaulo /* Force 8051 reset. */ 2262251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2263251538Srpaulo} 2264251538Srpaulo 2265264912Skevlostatic void 2266264912Skevlourtwn_r88e_fw_reset(struct urtwn_softc *sc) 2267264912Skevlo{ 2268264912Skevlo uint16_t reg; 2269264912Skevlo 2270264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2271264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2272264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2273264912Skevlo} 2274264912Skevlo 2275251538Srpaulostatic int 2276251538Srpaulourtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2277251538Srpaulo{ 2278251538Srpaulo uint32_t reg; 2279251538Srpaulo int off, mlen, error = 0; 2280251538Srpaulo 2281251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2282251538Srpaulo reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2283251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2284251538Srpaulo 2285251538Srpaulo off = R92C_FW_START_ADDR; 2286251538Srpaulo while (len > 0) { 2287251538Srpaulo if (len > 196) 2288251538Srpaulo mlen = 196; 2289251538Srpaulo else if (len > 4) 2290251538Srpaulo mlen = 4; 2291251538Srpaulo else 2292251538Srpaulo mlen = 1; 2293251538Srpaulo /* XXX fix this deconst */ 2294281069Srpaulo error = urtwn_write_region_1(sc, off, 2295251538Srpaulo __DECONST(uint8_t *, buf), mlen); 2296251538Srpaulo if (error != 0) 2297251538Srpaulo break; 2298251538Srpaulo off += mlen; 2299251538Srpaulo buf += mlen; 2300251538Srpaulo len -= mlen; 2301251538Srpaulo } 2302251538Srpaulo return (error); 2303251538Srpaulo} 2304251538Srpaulo 2305251538Srpaulostatic int 2306251538Srpaulourtwn_load_firmware(struct urtwn_softc *sc) 2307251538Srpaulo{ 2308251538Srpaulo const struct firmware *fw; 2309251538Srpaulo const struct r92c_fw_hdr *hdr; 2310251538Srpaulo const char *imagename; 2311251538Srpaulo const u_char *ptr; 2312251538Srpaulo size_t len; 2313251538Srpaulo uint32_t reg; 2314251538Srpaulo int mlen, ntries, page, error; 2315251538Srpaulo 2316264864Skevlo URTWN_UNLOCK(sc); 2317251538Srpaulo /* Read firmware image from the filesystem. */ 2318264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2319264912Skevlo imagename = "urtwn-rtl8188eufw"; 2320264912Skevlo else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2321264912Skevlo URTWN_CHIP_UMC_A_CUT) 2322251538Srpaulo imagename = "urtwn-rtl8192cfwU"; 2323251538Srpaulo else 2324251538Srpaulo imagename = "urtwn-rtl8192cfwT"; 2325251538Srpaulo 2326251538Srpaulo fw = firmware_get(imagename); 2327264864Skevlo URTWN_LOCK(sc); 2328251538Srpaulo if (fw == NULL) { 2329251538Srpaulo device_printf(sc->sc_dev, 2330251538Srpaulo "failed loadfirmware of file %s\n", imagename); 2331251538Srpaulo return (ENOENT); 2332251538Srpaulo } 2333251538Srpaulo 2334251538Srpaulo len = fw->datasize; 2335251538Srpaulo 2336251538Srpaulo if (len < sizeof(*hdr)) { 2337251538Srpaulo device_printf(sc->sc_dev, "firmware too short\n"); 2338251538Srpaulo error = EINVAL; 2339251538Srpaulo goto fail; 2340251538Srpaulo } 2341251538Srpaulo ptr = fw->data; 2342251538Srpaulo hdr = (const struct r92c_fw_hdr *)ptr; 2343251538Srpaulo /* Check if there is a valid FW header and skip it. */ 2344251538Srpaulo if ((le16toh(hdr->signature) >> 4) == 0x88c || 2345264912Skevlo (le16toh(hdr->signature) >> 4) == 0x88e || 2346251538Srpaulo (le16toh(hdr->signature) >> 4) == 0x92c) { 2347251538Srpaulo DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2348251538Srpaulo le16toh(hdr->version), le16toh(hdr->subversion), 2349251538Srpaulo hdr->month, hdr->date, hdr->hour, hdr->minute); 2350251538Srpaulo ptr += sizeof(*hdr); 2351251538Srpaulo len -= sizeof(*hdr); 2352251538Srpaulo } 2353251538Srpaulo 2354264912Skevlo if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2355264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2356264912Skevlo urtwn_r88e_fw_reset(sc); 2357264912Skevlo else 2358264912Skevlo urtwn_fw_reset(sc); 2359251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 0); 2360251538Srpaulo } 2361264912Skevlo 2362268487Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2363268487Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2364268487Skevlo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2365268487Skevlo R92C_SYS_FUNC_EN_CPUEN); 2366268487Skevlo } 2367251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2368251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2369251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 2, 2370251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2371251538Srpaulo 2372263154Skevlo /* Reset the FWDL checksum. */ 2373263154Skevlo urtwn_write_1(sc, R92C_MCUFWDL, 2374263154Skevlo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2375263154Skevlo 2376251538Srpaulo for (page = 0; len > 0; page++) { 2377251538Srpaulo mlen = min(len, R92C_FW_PAGE_SIZE); 2378251538Srpaulo error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2379251538Srpaulo if (error != 0) { 2380251538Srpaulo device_printf(sc->sc_dev, 2381251538Srpaulo "could not load firmware page\n"); 2382251538Srpaulo goto fail; 2383251538Srpaulo } 2384251538Srpaulo ptr += mlen; 2385251538Srpaulo len -= mlen; 2386251538Srpaulo } 2387251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2388251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2389251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2390251538Srpaulo 2391251538Srpaulo /* Wait for checksum report. */ 2392251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2393251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2394251538Srpaulo break; 2395266472Shselasky urtwn_ms_delay(sc); 2396251538Srpaulo } 2397251538Srpaulo if (ntries == 1000) { 2398251538Srpaulo device_printf(sc->sc_dev, 2399251538Srpaulo "timeout waiting for checksum report\n"); 2400251538Srpaulo error = ETIMEDOUT; 2401251538Srpaulo goto fail; 2402251538Srpaulo } 2403251538Srpaulo 2404251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2405251538Srpaulo reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2406251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2407264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2408264912Skevlo urtwn_r88e_fw_reset(sc); 2409251538Srpaulo /* Wait for firmware readiness. */ 2410251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2411251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2412251538Srpaulo break; 2413266472Shselasky urtwn_ms_delay(sc); 2414251538Srpaulo } 2415251538Srpaulo if (ntries == 1000) { 2416251538Srpaulo device_printf(sc->sc_dev, 2417251538Srpaulo "timeout waiting for firmware readiness\n"); 2418251538Srpaulo error = ETIMEDOUT; 2419251538Srpaulo goto fail; 2420251538Srpaulo } 2421251538Srpaulofail: 2422251538Srpaulo firmware_put(fw, FIRMWARE_UNLOAD); 2423251538Srpaulo return (error); 2424251538Srpaulo} 2425251538Srpaulo 2426264912Skevlostatic __inline int 2427251538Srpaulourtwn_dma_init(struct urtwn_softc *sc) 2428251538Srpaulo{ 2429281069Srpaulo 2430264912Skevlo return sc->sc_dma_init(sc); 2431264912Skevlo} 2432264912Skevlo 2433264912Skevlostatic int 2434264912Skevlourtwn_r92c_dma_init(struct urtwn_softc *sc) 2435264912Skevlo{ 2436251538Srpaulo int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2437251538Srpaulo uint32_t reg; 2438251538Srpaulo int error; 2439251538Srpaulo 2440251538Srpaulo /* Initialize LLT table. */ 2441251538Srpaulo error = urtwn_llt_init(sc); 2442251538Srpaulo if (error != 0) 2443251538Srpaulo return (error); 2444251538Srpaulo 2445251538Srpaulo /* Get Tx queues to USB endpoints mapping. */ 2446251538Srpaulo hashq = hasnq = haslq = 0; 2447251538Srpaulo reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2448251538Srpaulo DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2449251538Srpaulo if (MS(reg, R92C_USB_EP_HQ) != 0) 2450251538Srpaulo hashq = 1; 2451251538Srpaulo if (MS(reg, R92C_USB_EP_NQ) != 0) 2452251538Srpaulo hasnq = 1; 2453251538Srpaulo if (MS(reg, R92C_USB_EP_LQ) != 0) 2454251538Srpaulo haslq = 1; 2455251538Srpaulo nqueues = hashq + hasnq + haslq; 2456251538Srpaulo if (nqueues == 0) 2457251538Srpaulo return (EIO); 2458251538Srpaulo /* Get the number of pages for each queue. */ 2459251538Srpaulo nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2460251538Srpaulo /* The remaining pages are assigned to the high priority queue. */ 2461251538Srpaulo nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2462251538Srpaulo 2463251538Srpaulo /* Set number of pages for normal priority queue. */ 2464251538Srpaulo urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2465251538Srpaulo urtwn_write_4(sc, R92C_RQPN, 2466251538Srpaulo /* Set number of pages for public queue. */ 2467251538Srpaulo SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2468251538Srpaulo /* Set number of pages for high priority queue. */ 2469251538Srpaulo SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2470251538Srpaulo /* Set number of pages for low priority queue. */ 2471251538Srpaulo SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2472251538Srpaulo /* Load values. */ 2473251538Srpaulo R92C_RQPN_LD); 2474251538Srpaulo 2475251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2476251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2477251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2478251538Srpaulo urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2479251538Srpaulo urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2480251538Srpaulo 2481251538Srpaulo /* Set queue to USB pipe mapping. */ 2482251538Srpaulo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2483251538Srpaulo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2484251538Srpaulo if (nqueues == 1) { 2485251538Srpaulo if (hashq) 2486251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2487251538Srpaulo else if (hasnq) 2488251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2489251538Srpaulo else 2490251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2491251538Srpaulo } else if (nqueues == 2) { 2492251538Srpaulo /* All 2-endpoints configs have a high priority queue. */ 2493251538Srpaulo if (!hashq) 2494251538Srpaulo return (EIO); 2495251538Srpaulo if (hasnq) 2496251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2497251538Srpaulo else 2498251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2499251538Srpaulo } else 2500251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2501251538Srpaulo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2502251538Srpaulo 2503251538Srpaulo /* Set Tx/Rx transfer page boundary. */ 2504251538Srpaulo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2505251538Srpaulo 2506251538Srpaulo /* Set Tx/Rx transfer page size. */ 2507251538Srpaulo urtwn_write_1(sc, R92C_PBP, 2508251538Srpaulo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2509251538Srpaulo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2510251538Srpaulo return (0); 2511251538Srpaulo} 2512251538Srpaulo 2513264912Skevlostatic int 2514264912Skevlourtwn_r88e_dma_init(struct urtwn_softc *sc) 2515264912Skevlo{ 2516264912Skevlo struct usb_interface *iface; 2517264912Skevlo uint32_t reg; 2518264912Skevlo int nqueues; 2519264912Skevlo int error; 2520264912Skevlo 2521264912Skevlo /* Initialize LLT table. */ 2522264912Skevlo error = urtwn_llt_init(sc); 2523264912Skevlo if (error != 0) 2524264912Skevlo return (error); 2525264912Skevlo 2526264912Skevlo /* Get Tx queues to USB endpoints mapping. */ 2527264912Skevlo iface = usbd_get_iface(sc->sc_udev, 0); 2528264912Skevlo nqueues = iface->idesc->bNumEndpoints - 1; 2529264912Skevlo if (nqueues == 0) 2530264912Skevlo return (EIO); 2531264912Skevlo 2532264912Skevlo /* Set number of pages for normal priority queue. */ 2533264912Skevlo urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2534264912Skevlo urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2535264912Skevlo 2536264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2537264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2538264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2539264912Skevlo urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2540264912Skevlo urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2541264912Skevlo 2542264912Skevlo /* Set queue to USB pipe mapping. */ 2543264912Skevlo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2544264912Skevlo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2545264912Skevlo if (nqueues == 1) 2546264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2547264912Skevlo else if (nqueues == 2) 2548264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2549264912Skevlo else 2550264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2551264912Skevlo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2552264912Skevlo 2553264912Skevlo /* Set Tx/Rx transfer page boundary. */ 2554264912Skevlo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2555264912Skevlo 2556264912Skevlo /* Set Tx/Rx transfer page size. */ 2557264912Skevlo urtwn_write_1(sc, R92C_PBP, 2558264912Skevlo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2559264912Skevlo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2560264912Skevlo 2561264912Skevlo return (0); 2562264912Skevlo} 2563264912Skevlo 2564251538Srpaulostatic void 2565251538Srpaulourtwn_mac_init(struct urtwn_softc *sc) 2566251538Srpaulo{ 2567251538Srpaulo int i; 2568251538Srpaulo 2569251538Srpaulo /* Write MAC initialization values. */ 2570264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2571264912Skevlo for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2572264912Skevlo urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2573264912Skevlo rtl8188eu_mac[i].val); 2574264912Skevlo } 2575264912Skevlo urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2576264912Skevlo } else { 2577264912Skevlo for (i = 0; i < nitems(rtl8192cu_mac); i++) 2578264912Skevlo urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2579264912Skevlo rtl8192cu_mac[i].val); 2580264912Skevlo } 2581251538Srpaulo} 2582251538Srpaulo 2583251538Srpaulostatic void 2584251538Srpaulourtwn_bb_init(struct urtwn_softc *sc) 2585251538Srpaulo{ 2586251538Srpaulo const struct urtwn_bb_prog *prog; 2587251538Srpaulo uint32_t reg; 2588264912Skevlo uint8_t crystalcap; 2589251538Srpaulo int i; 2590251538Srpaulo 2591251538Srpaulo /* Enable BB and RF. */ 2592251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2593251538Srpaulo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2594251538Srpaulo R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2595251538Srpaulo R92C_SYS_FUNC_EN_DIO_RF); 2596251538Srpaulo 2597264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 2598264912Skevlo urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2599251538Srpaulo 2600251538Srpaulo urtwn_write_1(sc, R92C_RF_CTRL, 2601251538Srpaulo R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2602251538Srpaulo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2603251538Srpaulo R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2604251538Srpaulo R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2605251538Srpaulo 2606264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2607264912Skevlo urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2608264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 2609264912Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2610264912Skevlo } 2611251538Srpaulo 2612251538Srpaulo /* Select BB programming based on board type. */ 2613264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2614264912Skevlo prog = &rtl8188eu_bb_prog; 2615264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2616251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2617251538Srpaulo prog = &rtl8188ce_bb_prog; 2618251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2619251538Srpaulo prog = &rtl8188ru_bb_prog; 2620251538Srpaulo else 2621251538Srpaulo prog = &rtl8188cu_bb_prog; 2622251538Srpaulo } else { 2623251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2624251538Srpaulo prog = &rtl8192ce_bb_prog; 2625251538Srpaulo else 2626251538Srpaulo prog = &rtl8192cu_bb_prog; 2627251538Srpaulo } 2628251538Srpaulo /* Write BB initialization values. */ 2629251538Srpaulo for (i = 0; i < prog->count; i++) { 2630251538Srpaulo urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2631266472Shselasky urtwn_ms_delay(sc); 2632251538Srpaulo } 2633251538Srpaulo 2634251538Srpaulo if (sc->chip & URTWN_CHIP_92C_1T2R) { 2635251538Srpaulo /* 8192C 1T only configuration. */ 2636251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2637251538Srpaulo reg = (reg & ~0x00000003) | 0x2; 2638251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2639251538Srpaulo 2640251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2641251538Srpaulo reg = (reg & ~0x00300033) | 0x00200022; 2642251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2643251538Srpaulo 2644251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2645251538Srpaulo reg = (reg & ~0xff000000) | 0x45 << 24; 2646251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2647251538Srpaulo 2648251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2649251538Srpaulo reg = (reg & ~0x000000ff) | 0x23; 2650251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2651251538Srpaulo 2652251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2653251538Srpaulo reg = (reg & ~0x00000030) | 1 << 4; 2654251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2655251538Srpaulo 2656251538Srpaulo reg = urtwn_bb_read(sc, 0xe74); 2657251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2658251538Srpaulo urtwn_bb_write(sc, 0xe74, reg); 2659251538Srpaulo reg = urtwn_bb_read(sc, 0xe78); 2660251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2661251538Srpaulo urtwn_bb_write(sc, 0xe78, reg); 2662251538Srpaulo reg = urtwn_bb_read(sc, 0xe7c); 2663251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2664251538Srpaulo urtwn_bb_write(sc, 0xe7c, reg); 2665251538Srpaulo reg = urtwn_bb_read(sc, 0xe80); 2666251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2667251538Srpaulo urtwn_bb_write(sc, 0xe80, reg); 2668251538Srpaulo reg = urtwn_bb_read(sc, 0xe88); 2669251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2670251538Srpaulo urtwn_bb_write(sc, 0xe88, reg); 2671251538Srpaulo } 2672251538Srpaulo 2673251538Srpaulo /* Write AGC values. */ 2674251538Srpaulo for (i = 0; i < prog->agccount; i++) { 2675251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2676251538Srpaulo prog->agcvals[i]); 2677266472Shselasky urtwn_ms_delay(sc); 2678251538Srpaulo } 2679251538Srpaulo 2680264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2681264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2682266472Shselasky urtwn_ms_delay(sc); 2683264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2684266472Shselasky urtwn_ms_delay(sc); 2685264912Skevlo 2686264912Skevlo crystalcap = sc->r88e_rom[0xb9]; 2687264912Skevlo if (crystalcap == 0xff) 2688264912Skevlo crystalcap = 0x20; 2689264912Skevlo crystalcap &= 0x3f; 2690264912Skevlo reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2691264912Skevlo urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2692264912Skevlo RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2693264912Skevlo crystalcap | crystalcap << 6)); 2694264912Skevlo } else { 2695264912Skevlo if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2696264912Skevlo R92C_HSSI_PARAM2_CCK_HIPWR) 2697264912Skevlo sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2698264912Skevlo } 2699251538Srpaulo} 2700251538Srpaulo 2701289066Skevlostatic void 2702251538Srpaulourtwn_rf_init(struct urtwn_softc *sc) 2703251538Srpaulo{ 2704251538Srpaulo const struct urtwn_rf_prog *prog; 2705251538Srpaulo uint32_t reg, type; 2706251538Srpaulo int i, j, idx, off; 2707251538Srpaulo 2708251538Srpaulo /* Select RF programming based on board type. */ 2709264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2710264912Skevlo prog = rtl8188eu_rf_prog; 2711264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2712251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2713251538Srpaulo prog = rtl8188ce_rf_prog; 2714251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2715251538Srpaulo prog = rtl8188ru_rf_prog; 2716251538Srpaulo else 2717251538Srpaulo prog = rtl8188cu_rf_prog; 2718251538Srpaulo } else 2719251538Srpaulo prog = rtl8192ce_rf_prog; 2720251538Srpaulo 2721251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2722251538Srpaulo /* Save RF_ENV control type. */ 2723251538Srpaulo idx = i / 2; 2724251538Srpaulo off = (i % 2) * 16; 2725251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2726251538Srpaulo type = (reg >> off) & 0x10; 2727251538Srpaulo 2728251538Srpaulo /* Set RF_ENV enable. */ 2729251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2730251538Srpaulo reg |= 0x100000; 2731251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2732266472Shselasky urtwn_ms_delay(sc); 2733251538Srpaulo /* Set RF_ENV output high. */ 2734251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2735251538Srpaulo reg |= 0x10; 2736251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2737266472Shselasky urtwn_ms_delay(sc); 2738251538Srpaulo /* Set address and data lengths of RF registers. */ 2739251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2740251538Srpaulo reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2741251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2742266472Shselasky urtwn_ms_delay(sc); 2743251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2744251538Srpaulo reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2745251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2746266472Shselasky urtwn_ms_delay(sc); 2747251538Srpaulo 2748251538Srpaulo /* Write RF initialization values for this chain. */ 2749251538Srpaulo for (j = 0; j < prog[i].count; j++) { 2750251538Srpaulo if (prog[i].regs[j] >= 0xf9 && 2751251538Srpaulo prog[i].regs[j] <= 0xfe) { 2752251538Srpaulo /* 2753251538Srpaulo * These are fake RF registers offsets that 2754251538Srpaulo * indicate a delay is required. 2755251538Srpaulo */ 2756266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2757251538Srpaulo continue; 2758251538Srpaulo } 2759251538Srpaulo urtwn_rf_write(sc, i, prog[i].regs[j], 2760251538Srpaulo prog[i].vals[j]); 2761266472Shselasky urtwn_ms_delay(sc); 2762251538Srpaulo } 2763251538Srpaulo 2764251538Srpaulo /* Restore RF_ENV control type. */ 2765251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2766251538Srpaulo reg &= ~(0x10 << off) | (type << off); 2767251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2768251538Srpaulo 2769251538Srpaulo /* Cache RF register CHNLBW. */ 2770251538Srpaulo sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2771251538Srpaulo } 2772251538Srpaulo 2773251538Srpaulo if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2774251538Srpaulo URTWN_CHIP_UMC_A_CUT) { 2775251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2776251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2777251538Srpaulo } 2778251538Srpaulo} 2779251538Srpaulo 2780251538Srpaulostatic void 2781251538Srpaulourtwn_cam_init(struct urtwn_softc *sc) 2782251538Srpaulo{ 2783251538Srpaulo /* Invalidate all CAM entries. */ 2784251538Srpaulo urtwn_write_4(sc, R92C_CAMCMD, 2785251538Srpaulo R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2786251538Srpaulo} 2787251538Srpaulo 2788251538Srpaulostatic void 2789251538Srpaulourtwn_pa_bias_init(struct urtwn_softc *sc) 2790251538Srpaulo{ 2791251538Srpaulo uint8_t reg; 2792251538Srpaulo int i; 2793251538Srpaulo 2794251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2795251538Srpaulo if (sc->pa_setting & (1 << i)) 2796251538Srpaulo continue; 2797251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2798251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2799251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2800251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2801251538Srpaulo } 2802251538Srpaulo if (!(sc->pa_setting & 0x10)) { 2803251538Srpaulo reg = urtwn_read_1(sc, 0x16); 2804251538Srpaulo reg = (reg & ~0xf0) | 0x90; 2805251538Srpaulo urtwn_write_1(sc, 0x16, reg); 2806251538Srpaulo } 2807251538Srpaulo} 2808251538Srpaulo 2809251538Srpaulostatic void 2810251538Srpaulourtwn_rxfilter_init(struct urtwn_softc *sc) 2811251538Srpaulo{ 2812251538Srpaulo /* Initialize Rx filter. */ 2813251538Srpaulo /* TODO: use better filter for monitor mode. */ 2814251538Srpaulo urtwn_write_4(sc, R92C_RCR, 2815251538Srpaulo R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2816251538Srpaulo R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2817251538Srpaulo R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2818251538Srpaulo /* Accept all multicast frames. */ 2819251538Srpaulo urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2820251538Srpaulo urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2821251538Srpaulo /* Accept all management frames. */ 2822251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2823251538Srpaulo /* Reject all control frames. */ 2824251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2825251538Srpaulo /* Accept all data frames. */ 2826251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2827251538Srpaulo} 2828251538Srpaulo 2829251538Srpaulostatic void 2830251538Srpaulourtwn_edca_init(struct urtwn_softc *sc) 2831251538Srpaulo{ 2832251538Srpaulo urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2833251538Srpaulo urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2834251538Srpaulo urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2835251538Srpaulo urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2836251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2837251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2838251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2839251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2840251538Srpaulo} 2841251538Srpaulo 2842289066Skevlostatic void 2843251538Srpaulourtwn_write_txpower(struct urtwn_softc *sc, int chain, 2844251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2845251538Srpaulo{ 2846251538Srpaulo uint32_t reg; 2847251538Srpaulo 2848251538Srpaulo /* Write per-CCK rate Tx power. */ 2849251538Srpaulo if (chain == 0) { 2850251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2851251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2852251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2853251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2854251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2855251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2856251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2857251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2858251538Srpaulo } else { 2859251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2860251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2861251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2862251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2863251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2864251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2865251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2866251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2867251538Srpaulo } 2868251538Srpaulo /* Write per-OFDM rate Tx power. */ 2869251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2870251538Srpaulo SM(R92C_TXAGC_RATE06, power[ 4]) | 2871251538Srpaulo SM(R92C_TXAGC_RATE09, power[ 5]) | 2872251538Srpaulo SM(R92C_TXAGC_RATE12, power[ 6]) | 2873251538Srpaulo SM(R92C_TXAGC_RATE18, power[ 7])); 2874251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2875251538Srpaulo SM(R92C_TXAGC_RATE24, power[ 8]) | 2876251538Srpaulo SM(R92C_TXAGC_RATE36, power[ 9]) | 2877251538Srpaulo SM(R92C_TXAGC_RATE48, power[10]) | 2878251538Srpaulo SM(R92C_TXAGC_RATE54, power[11])); 2879251538Srpaulo /* Write per-MCS Tx power. */ 2880251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2881251538Srpaulo SM(R92C_TXAGC_MCS00, power[12]) | 2882251538Srpaulo SM(R92C_TXAGC_MCS01, power[13]) | 2883251538Srpaulo SM(R92C_TXAGC_MCS02, power[14]) | 2884251538Srpaulo SM(R92C_TXAGC_MCS03, power[15])); 2885251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2886251538Srpaulo SM(R92C_TXAGC_MCS04, power[16]) | 2887251538Srpaulo SM(R92C_TXAGC_MCS05, power[17]) | 2888251538Srpaulo SM(R92C_TXAGC_MCS06, power[18]) | 2889251538Srpaulo SM(R92C_TXAGC_MCS07, power[19])); 2890251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2891251538Srpaulo SM(R92C_TXAGC_MCS08, power[20]) | 2892261506Skevlo SM(R92C_TXAGC_MCS09, power[21]) | 2893251538Srpaulo SM(R92C_TXAGC_MCS10, power[22]) | 2894251538Srpaulo SM(R92C_TXAGC_MCS11, power[23])); 2895251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2896251538Srpaulo SM(R92C_TXAGC_MCS12, power[24]) | 2897251538Srpaulo SM(R92C_TXAGC_MCS13, power[25]) | 2898251538Srpaulo SM(R92C_TXAGC_MCS14, power[26]) | 2899251538Srpaulo SM(R92C_TXAGC_MCS15, power[27])); 2900251538Srpaulo} 2901251538Srpaulo 2902289066Skevlostatic void 2903251538Srpaulourtwn_get_txpower(struct urtwn_softc *sc, int chain, 2904251538Srpaulo struct ieee80211_channel *c, struct ieee80211_channel *extc, 2905251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2906251538Srpaulo{ 2907287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 2908251538Srpaulo struct r92c_rom *rom = &sc->rom; 2909251538Srpaulo uint16_t cckpow, ofdmpow, htpow, diff, max; 2910251538Srpaulo const struct urtwn_txpwr *base; 2911251538Srpaulo int ridx, chan, group; 2912251538Srpaulo 2913251538Srpaulo /* Determine channel group. */ 2914251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2915251538Srpaulo if (chan <= 3) 2916251538Srpaulo group = 0; 2917251538Srpaulo else if (chan <= 9) 2918251538Srpaulo group = 1; 2919251538Srpaulo else 2920251538Srpaulo group = 2; 2921251538Srpaulo 2922251538Srpaulo /* Get original Tx power based on board type and RF chain. */ 2923251538Srpaulo if (!(sc->chip & URTWN_CHIP_92C)) { 2924251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2925251538Srpaulo base = &rtl8188ru_txagc[chain]; 2926251538Srpaulo else 2927251538Srpaulo base = &rtl8192cu_txagc[chain]; 2928251538Srpaulo } else 2929251538Srpaulo base = &rtl8192cu_txagc[chain]; 2930251538Srpaulo 2931251538Srpaulo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2932251538Srpaulo if (sc->regulatory == 0) { 2933251538Srpaulo for (ridx = 0; ridx <= 3; ridx++) 2934251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2935251538Srpaulo } 2936251538Srpaulo for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 2937251538Srpaulo if (sc->regulatory == 3) { 2938251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2939251538Srpaulo /* Apply vendor limits. */ 2940251538Srpaulo if (extc != NULL) 2941251538Srpaulo max = rom->ht40_max_pwr[group]; 2942251538Srpaulo else 2943251538Srpaulo max = rom->ht20_max_pwr[group]; 2944251538Srpaulo max = (max >> (chain * 4)) & 0xf; 2945251538Srpaulo if (power[ridx] > max) 2946251538Srpaulo power[ridx] = max; 2947251538Srpaulo } else if (sc->regulatory == 1) { 2948251538Srpaulo if (extc == NULL) 2949251538Srpaulo power[ridx] = base->pwr[group][ridx]; 2950251538Srpaulo } else if (sc->regulatory != 2) 2951251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2952251538Srpaulo } 2953251538Srpaulo 2954251538Srpaulo /* Compute per-CCK rate Tx power. */ 2955251538Srpaulo cckpow = rom->cck_tx_pwr[chain][group]; 2956251538Srpaulo for (ridx = 0; ridx <= 3; ridx++) { 2957251538Srpaulo power[ridx] += cckpow; 2958251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2959251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2960251538Srpaulo } 2961251538Srpaulo 2962251538Srpaulo htpow = rom->ht40_1s_tx_pwr[chain][group]; 2963251538Srpaulo if (sc->ntxchains > 1) { 2964251538Srpaulo /* Apply reduction for 2 spatial streams. */ 2965251538Srpaulo diff = rom->ht40_2s_tx_pwr_diff[group]; 2966251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2967251538Srpaulo htpow = (htpow > diff) ? htpow - diff : 0; 2968251538Srpaulo } 2969251538Srpaulo 2970251538Srpaulo /* Compute per-OFDM rate Tx power. */ 2971251538Srpaulo diff = rom->ofdm_tx_pwr_diff[group]; 2972251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2973251538Srpaulo ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2974251538Srpaulo for (ridx = 4; ridx <= 11; ridx++) { 2975251538Srpaulo power[ridx] += ofdmpow; 2976251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2977251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2978251538Srpaulo } 2979251538Srpaulo 2980251538Srpaulo /* Compute per-MCS Tx power. */ 2981251538Srpaulo if (extc == NULL) { 2982251538Srpaulo diff = rom->ht20_tx_pwr_diff[group]; 2983251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2984251538Srpaulo htpow += diff; /* HT40->HT20 correction. */ 2985251538Srpaulo } 2986251538Srpaulo for (ridx = 12; ridx <= 27; ridx++) { 2987251538Srpaulo power[ridx] += htpow; 2988251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2989251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2990251538Srpaulo } 2991251538Srpaulo#ifdef URTWN_DEBUG 2992251538Srpaulo if (urtwn_debug >= 4) { 2993251538Srpaulo /* Dump per-rate Tx power values. */ 2994251538Srpaulo printf("Tx power for chain %d:\n", chain); 2995251538Srpaulo for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 2996251538Srpaulo printf("Rate %d = %u\n", ridx, power[ridx]); 2997251538Srpaulo } 2998251538Srpaulo#endif 2999251538Srpaulo} 3000251538Srpaulo 3001289066Skevlostatic void 3002264912Skevlourtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3003264912Skevlo struct ieee80211_channel *c, struct ieee80211_channel *extc, 3004264912Skevlo uint16_t power[URTWN_RIDX_COUNT]) 3005264912Skevlo{ 3006287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3007264912Skevlo uint16_t cckpow, ofdmpow, bw20pow, htpow; 3008264912Skevlo const struct urtwn_r88e_txpwr *base; 3009264912Skevlo int ridx, chan, group; 3010264912Skevlo 3011264912Skevlo /* Determine channel group. */ 3012264912Skevlo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3013264912Skevlo if (chan <= 2) 3014264912Skevlo group = 0; 3015264912Skevlo else if (chan <= 5) 3016264912Skevlo group = 1; 3017264912Skevlo else if (chan <= 8) 3018264912Skevlo group = 2; 3019264912Skevlo else if (chan <= 11) 3020264912Skevlo group = 3; 3021264912Skevlo else if (chan <= 13) 3022264912Skevlo group = 4; 3023264912Skevlo else 3024264912Skevlo group = 5; 3025264912Skevlo 3026264912Skevlo /* Get original Tx power based on board type and RF chain. */ 3027264912Skevlo base = &rtl8188eu_txagc[chain]; 3028264912Skevlo 3029264912Skevlo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3030264912Skevlo if (sc->regulatory == 0) { 3031264912Skevlo for (ridx = 0; ridx <= 3; ridx++) 3032264912Skevlo power[ridx] = base->pwr[0][ridx]; 3033264912Skevlo } 3034264912Skevlo for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3035264912Skevlo if (sc->regulatory == 3) 3036264912Skevlo power[ridx] = base->pwr[0][ridx]; 3037264912Skevlo else if (sc->regulatory == 1) { 3038264912Skevlo if (extc == NULL) 3039264912Skevlo power[ridx] = base->pwr[group][ridx]; 3040264912Skevlo } else if (sc->regulatory != 2) 3041264912Skevlo power[ridx] = base->pwr[0][ridx]; 3042264912Skevlo } 3043264912Skevlo 3044264912Skevlo /* Compute per-CCK rate Tx power. */ 3045264912Skevlo cckpow = sc->cck_tx_pwr[group]; 3046264912Skevlo for (ridx = 0; ridx <= 3; ridx++) { 3047264912Skevlo power[ridx] += cckpow; 3048264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3049264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3050264912Skevlo } 3051264912Skevlo 3052264912Skevlo htpow = sc->ht40_tx_pwr[group]; 3053264912Skevlo 3054264912Skevlo /* Compute per-OFDM rate Tx power. */ 3055264912Skevlo ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3056264912Skevlo for (ridx = 4; ridx <= 11; ridx++) { 3057264912Skevlo power[ridx] += ofdmpow; 3058264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3059264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3060264912Skevlo } 3061264912Skevlo 3062264912Skevlo bw20pow = htpow + sc->bw20_tx_pwr_diff; 3063264912Skevlo for (ridx = 12; ridx <= 27; ridx++) { 3064264912Skevlo power[ridx] += bw20pow; 3065264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3066264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3067264912Skevlo } 3068264912Skevlo} 3069264912Skevlo 3070289066Skevlostatic void 3071251538Srpaulourtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3072251538Srpaulo struct ieee80211_channel *extc) 3073251538Srpaulo{ 3074251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]; 3075251538Srpaulo int i; 3076251538Srpaulo 3077251538Srpaulo for (i = 0; i < sc->ntxchains; i++) { 3078251538Srpaulo /* Compute per-rate Tx power values. */ 3079264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3080264912Skevlo urtwn_r88e_get_txpower(sc, i, c, extc, power); 3081264912Skevlo else 3082264912Skevlo urtwn_get_txpower(sc, i, c, extc, power); 3083251538Srpaulo /* Write per-rate Tx power values to hardware. */ 3084251538Srpaulo urtwn_write_txpower(sc, i, power); 3085251538Srpaulo } 3086251538Srpaulo} 3087251538Srpaulo 3088251538Srpaulostatic void 3089251538Srpaulourtwn_scan_start(struct ieee80211com *ic) 3090251538Srpaulo{ 3091251538Srpaulo /* XXX do nothing? */ 3092251538Srpaulo} 3093251538Srpaulo 3094251538Srpaulostatic void 3095251538Srpaulourtwn_scan_end(struct ieee80211com *ic) 3096251538Srpaulo{ 3097251538Srpaulo /* XXX do nothing? */ 3098251538Srpaulo} 3099251538Srpaulo 3100251538Srpaulostatic void 3101251538Srpaulourtwn_set_channel(struct ieee80211com *ic) 3102251538Srpaulo{ 3103286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 3104281070Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3105251538Srpaulo 3106251538Srpaulo URTWN_LOCK(sc); 3107281070Srpaulo if (vap->iv_state == IEEE80211_S_SCAN) { 3108281070Srpaulo /* Make link LED blink during scan. */ 3109281070Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3110281070Srpaulo } 3111251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 3112251538Srpaulo URTWN_UNLOCK(sc); 3113251538Srpaulo} 3114251538Srpaulo 3115251538Srpaulostatic void 3116283540Sglebiusurtwn_update_mcast(struct ieee80211com *ic) 3117251538Srpaulo{ 3118251538Srpaulo /* XXX do nothing? */ 3119251538Srpaulo} 3120251538Srpaulo 3121251538Srpaulostatic void 3122251538Srpaulourtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3123251538Srpaulo struct ieee80211_channel *extc) 3124251538Srpaulo{ 3125287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3126251538Srpaulo uint32_t reg; 3127251538Srpaulo u_int chan; 3128251538Srpaulo int i; 3129251538Srpaulo 3130251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3131251538Srpaulo if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3132251538Srpaulo device_printf(sc->sc_dev, 3133251538Srpaulo "%s: invalid channel %x\n", __func__, chan); 3134251538Srpaulo return; 3135251538Srpaulo } 3136251538Srpaulo 3137251538Srpaulo /* Set Tx power for this new channel. */ 3138251538Srpaulo urtwn_set_txpower(sc, c, extc); 3139251538Srpaulo 3140251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3141251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3142251538Srpaulo RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3143251538Srpaulo } 3144251538Srpaulo#ifndef IEEE80211_NO_HT 3145251538Srpaulo if (extc != NULL) { 3146251538Srpaulo /* Is secondary channel below or above primary? */ 3147251538Srpaulo int prichlo = c->ic_freq < extc->ic_freq; 3148251538Srpaulo 3149251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3150251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3151251538Srpaulo 3152251538Srpaulo reg = urtwn_read_1(sc, R92C_RRSR + 2); 3153251538Srpaulo reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3154251538Srpaulo urtwn_write_1(sc, R92C_RRSR + 2, reg); 3155251538Srpaulo 3156251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3157251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3158251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3159251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3160251538Srpaulo 3161251538Srpaulo /* Set CCK side band. */ 3162251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3163251538Srpaulo reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3164251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3165251538Srpaulo 3166251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3167251538Srpaulo reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3168251538Srpaulo urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3169251538Srpaulo 3170251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3171251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3172251538Srpaulo ~R92C_FPGA0_ANAPARAM2_CBW20); 3173251538Srpaulo 3174251538Srpaulo reg = urtwn_bb_read(sc, 0x818); 3175251538Srpaulo reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3176251538Srpaulo urtwn_bb_write(sc, 0x818, reg); 3177251538Srpaulo 3178251538Srpaulo /* Select 40MHz bandwidth. */ 3179251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3180251538Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan); 3181251538Srpaulo } else 3182251538Srpaulo#endif 3183251538Srpaulo { 3184251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3185251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3186251538Srpaulo 3187251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3188251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3189251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3190251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3191251538Srpaulo 3192264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3193264912Skevlo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3194264912Skevlo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3195264912Skevlo R92C_FPGA0_ANAPARAM2_CBW20); 3196264912Skevlo } 3197281069Srpaulo 3198251538Srpaulo /* Select 20MHz bandwidth. */ 3199251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3200281069Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan | 3201264912Skevlo ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3202264912Skevlo R92C_RF_CHNLBW_BW20)); 3203251538Srpaulo } 3204251538Srpaulo} 3205251538Srpaulo 3206251538Srpaulostatic void 3207251538Srpaulourtwn_iq_calib(struct urtwn_softc *sc) 3208251538Srpaulo{ 3209251538Srpaulo /* TODO */ 3210251538Srpaulo} 3211251538Srpaulo 3212251538Srpaulostatic void 3213251538Srpaulourtwn_lc_calib(struct urtwn_softc *sc) 3214251538Srpaulo{ 3215251538Srpaulo uint32_t rf_ac[2]; 3216251538Srpaulo uint8_t txmode; 3217251538Srpaulo int i; 3218251538Srpaulo 3219251538Srpaulo txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3220251538Srpaulo if ((txmode & 0x70) != 0) { 3221251538Srpaulo /* Disable all continuous Tx. */ 3222251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3223251538Srpaulo 3224251538Srpaulo /* Set RF mode to standby mode. */ 3225251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3226251538Srpaulo rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3227251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, 3228251538Srpaulo RW(rf_ac[i], R92C_RF_AC_MODE, 3229251538Srpaulo R92C_RF_AC_MODE_STANDBY)); 3230251538Srpaulo } 3231251538Srpaulo } else { 3232251538Srpaulo /* Block all Tx queues. */ 3233251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3234251538Srpaulo } 3235251538Srpaulo /* Start calibration. */ 3236251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3237251538Srpaulo urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3238251538Srpaulo 3239251538Srpaulo /* Give calibration the time to complete. */ 3240266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3241251538Srpaulo 3242251538Srpaulo /* Restore configuration. */ 3243251538Srpaulo if ((txmode & 0x70) != 0) { 3244251538Srpaulo /* Restore Tx mode. */ 3245251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3246251538Srpaulo /* Restore RF mode. */ 3247251538Srpaulo for (i = 0; i < sc->nrxchains; i++) 3248251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3249251538Srpaulo } else { 3250251538Srpaulo /* Unblock all Tx queues. */ 3251251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3252251538Srpaulo } 3253251538Srpaulo} 3254251538Srpaulo 3255251538Srpaulostatic void 3256287197Sglebiusurtwn_init(struct urtwn_softc *sc) 3257251538Srpaulo{ 3258287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3259287197Sglebius struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3260287197Sglebius uint8_t macaddr[IEEE80211_ADDR_LEN]; 3261251538Srpaulo uint32_t reg; 3262251538Srpaulo int error; 3263251538Srpaulo 3264264864Skevlo URTWN_ASSERT_LOCKED(sc); 3265264864Skevlo 3266287197Sglebius if (sc->sc_flags & URTWN_RUNNING) 3267287197Sglebius urtwn_stop(sc); 3268251538Srpaulo 3269251538Srpaulo /* Init firmware commands ring. */ 3270251538Srpaulo sc->fwcur = 0; 3271251538Srpaulo 3272251538Srpaulo /* Allocate Tx/Rx buffers. */ 3273251538Srpaulo error = urtwn_alloc_rx_list(sc); 3274251538Srpaulo if (error != 0) 3275251538Srpaulo goto fail; 3276281069Srpaulo 3277251538Srpaulo error = urtwn_alloc_tx_list(sc); 3278251538Srpaulo if (error != 0) 3279251538Srpaulo goto fail; 3280251538Srpaulo 3281251538Srpaulo /* Power on adapter. */ 3282251538Srpaulo error = urtwn_power_on(sc); 3283251538Srpaulo if (error != 0) 3284251538Srpaulo goto fail; 3285251538Srpaulo 3286251538Srpaulo /* Initialize DMA. */ 3287251538Srpaulo error = urtwn_dma_init(sc); 3288251538Srpaulo if (error != 0) 3289251538Srpaulo goto fail; 3290251538Srpaulo 3291251538Srpaulo /* Set info size in Rx descriptors (in 64-bit words). */ 3292251538Srpaulo urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3293251538Srpaulo 3294251538Srpaulo /* Init interrupts. */ 3295264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3296264912Skevlo urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3297264912Skevlo urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3298264912Skevlo R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3299264912Skevlo urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3300264912Skevlo R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3301264912Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3302264912Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3303264912Skevlo R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3304264912Skevlo } else { 3305264912Skevlo urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3306264912Skevlo urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3307264912Skevlo } 3308251538Srpaulo 3309251538Srpaulo /* Set MAC address. */ 3310287197Sglebius IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3311287197Sglebius urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3312251538Srpaulo 3313251538Srpaulo /* Set initial network type. */ 3314251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 3315251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3316251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 3317251538Srpaulo 3318251538Srpaulo urtwn_rxfilter_init(sc); 3319251538Srpaulo 3320282623Skevlo /* Set response rate. */ 3321251538Srpaulo reg = urtwn_read_4(sc, R92C_RRSR); 3322251538Srpaulo reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3323251538Srpaulo urtwn_write_4(sc, R92C_RRSR, reg); 3324251538Srpaulo 3325251538Srpaulo /* Set short/long retry limits. */ 3326251538Srpaulo urtwn_write_2(sc, R92C_RL, 3327251538Srpaulo SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3328251538Srpaulo 3329251538Srpaulo /* Initialize EDCA parameters. */ 3330251538Srpaulo urtwn_edca_init(sc); 3331251538Srpaulo 3332251538Srpaulo /* Setup rate fallback. */ 3333264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3334264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3335264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3336264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3337264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3338264912Skevlo } 3339251538Srpaulo 3340251538Srpaulo urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3341251538Srpaulo urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3342251538Srpaulo R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3343251538Srpaulo /* Set ACK timeout. */ 3344251538Srpaulo urtwn_write_1(sc, R92C_ACKTO, 0x40); 3345251538Srpaulo 3346251538Srpaulo /* Setup USB aggregation. */ 3347251538Srpaulo reg = urtwn_read_4(sc, R92C_TDECTRL); 3348251538Srpaulo reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3349251538Srpaulo urtwn_write_4(sc, R92C_TDECTRL, reg); 3350251538Srpaulo urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3351251538Srpaulo urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3352251538Srpaulo R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3353251538Srpaulo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3354264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3355264912Skevlo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3356282266Skevlo else { 3357264912Skevlo urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3358282266Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3359282266Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3360282266Skevlo R92C_USB_SPECIAL_OPTION_AGG_EN); 3361282266Skevlo urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3362282266Skevlo urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3363282266Skevlo } 3364251538Srpaulo 3365251538Srpaulo /* Initialize beacon parameters. */ 3366264912Skevlo urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3367251538Srpaulo urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3368251538Srpaulo urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3369251538Srpaulo urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3370251538Srpaulo urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3371251538Srpaulo 3372264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3373264912Skevlo /* Setup AMPDU aggregation. */ 3374264912Skevlo urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3375264912Skevlo urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3376264912Skevlo urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3377251538Srpaulo 3378264912Skevlo urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3379264912Skevlo } 3380251538Srpaulo 3381251538Srpaulo /* Load 8051 microcode. */ 3382251538Srpaulo error = urtwn_load_firmware(sc); 3383251538Srpaulo if (error != 0) 3384251538Srpaulo goto fail; 3385251538Srpaulo 3386251538Srpaulo /* Initialize MAC/BB/RF blocks. */ 3387251538Srpaulo urtwn_mac_init(sc); 3388251538Srpaulo urtwn_bb_init(sc); 3389251538Srpaulo urtwn_rf_init(sc); 3390251538Srpaulo 3391264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3392264912Skevlo urtwn_write_2(sc, R92C_CR, 3393264912Skevlo urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3394264912Skevlo R92C_CR_MACRXEN); 3395264912Skevlo } 3396264912Skevlo 3397251538Srpaulo /* Turn CCK and OFDM blocks on. */ 3398251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3399251538Srpaulo reg |= R92C_RFMOD_CCK_EN; 3400251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3401251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3402251538Srpaulo reg |= R92C_RFMOD_OFDM_EN; 3403251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3404251538Srpaulo 3405251538Srpaulo /* Clear per-station keys table. */ 3406251538Srpaulo urtwn_cam_init(sc); 3407251538Srpaulo 3408251538Srpaulo /* Enable hardware sequence numbering. */ 3409251538Srpaulo urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3410251538Srpaulo 3411251538Srpaulo /* Perform LO and IQ calibrations. */ 3412251538Srpaulo urtwn_iq_calib(sc); 3413251538Srpaulo /* Perform LC calibration. */ 3414251538Srpaulo urtwn_lc_calib(sc); 3415251538Srpaulo 3416251538Srpaulo /* Fix USB interference issue. */ 3417264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3418264912Skevlo urtwn_write_1(sc, 0xfe40, 0xe0); 3419264912Skevlo urtwn_write_1(sc, 0xfe41, 0x8d); 3420264912Skevlo urtwn_write_1(sc, 0xfe42, 0x80); 3421251538Srpaulo 3422264912Skevlo urtwn_pa_bias_init(sc); 3423264912Skevlo } 3424251538Srpaulo 3425251538Srpaulo /* Initialize GPIO setting. */ 3426251538Srpaulo urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3427251538Srpaulo urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3428251538Srpaulo 3429251538Srpaulo /* Fix for lower temperature. */ 3430264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 3431264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 3432251538Srpaulo 3433251538Srpaulo usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3434251538Srpaulo 3435287197Sglebius sc->sc_flags |= URTWN_RUNNING; 3436251538Srpaulo 3437251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3438251538Srpaulofail: 3439251538Srpaulo return; 3440251538Srpaulo} 3441251538Srpaulo 3442251538Srpaulostatic void 3443287197Sglebiusurtwn_stop(struct urtwn_softc *sc) 3444251538Srpaulo{ 3445251538Srpaulo 3446264864Skevlo URTWN_ASSERT_LOCKED(sc); 3447287197Sglebius sc->sc_flags &= ~URTWN_RUNNING; 3448251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 3449251538Srpaulo urtwn_abort_xfers(sc); 3450288353Sadrian 3451288353Sadrian urtwn_drain_mbufq(sc); 3452251538Srpaulo} 3453251538Srpaulo 3454251538Srpaulostatic void 3455251538Srpaulourtwn_abort_xfers(struct urtwn_softc *sc) 3456251538Srpaulo{ 3457251538Srpaulo int i; 3458251538Srpaulo 3459251538Srpaulo URTWN_ASSERT_LOCKED(sc); 3460251538Srpaulo 3461251538Srpaulo /* abort any pending transfers */ 3462251538Srpaulo for (i = 0; i < URTWN_N_TRANSFER; i++) 3463251538Srpaulo usbd_transfer_stop(sc->sc_xfer[i]); 3464251538Srpaulo} 3465251538Srpaulo 3466251538Srpaulostatic int 3467251538Srpaulourtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3468251538Srpaulo const struct ieee80211_bpf_params *params) 3469251538Srpaulo{ 3470251538Srpaulo struct ieee80211com *ic = ni->ni_ic; 3471286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 3472251538Srpaulo struct urtwn_data *bf; 3473251538Srpaulo 3474251538Srpaulo /* prevent management frames from being sent if we're not ready */ 3475287197Sglebius if (!(sc->sc_flags & URTWN_RUNNING)) { 3476251538Srpaulo m_freem(m); 3477251538Srpaulo return (ENETDOWN); 3478251538Srpaulo } 3479251538Srpaulo URTWN_LOCK(sc); 3480251538Srpaulo bf = urtwn_getbuf(sc); 3481251538Srpaulo if (bf == NULL) { 3482251538Srpaulo m_freem(m); 3483251538Srpaulo URTWN_UNLOCK(sc); 3484251538Srpaulo return (ENOBUFS); 3485251538Srpaulo } 3486251538Srpaulo 3487251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3488288353Sadrian m_freem(m); 3489251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3490251538Srpaulo URTWN_UNLOCK(sc); 3491251538Srpaulo return (EIO); 3492251538Srpaulo } 3493288353Sadrian sc->sc_txtimer = 5; 3494251538Srpaulo URTWN_UNLOCK(sc); 3495251538Srpaulo 3496251538Srpaulo return (0); 3497251538Srpaulo} 3498251538Srpaulo 3499266472Shselaskystatic void 3500266472Shselaskyurtwn_ms_delay(struct urtwn_softc *sc) 3501266472Shselasky{ 3502266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3503266472Shselasky} 3504266472Shselasky 3505251538Srpaulostatic device_method_t urtwn_methods[] = { 3506251538Srpaulo /* Device interface */ 3507251538Srpaulo DEVMETHOD(device_probe, urtwn_match), 3508251538Srpaulo DEVMETHOD(device_attach, urtwn_attach), 3509251538Srpaulo DEVMETHOD(device_detach, urtwn_detach), 3510251538Srpaulo 3511264912Skevlo DEVMETHOD_END 3512251538Srpaulo}; 3513251538Srpaulo 3514251538Srpaulostatic driver_t urtwn_driver = { 3515251538Srpaulo "urtwn", 3516251538Srpaulo urtwn_methods, 3517251538Srpaulo sizeof(struct urtwn_softc) 3518251538Srpaulo}; 3519251538Srpaulo 3520251538Srpaulostatic devclass_t urtwn_devclass; 3521251538Srpaulo 3522251538SrpauloDRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3523251538SrpauloMODULE_DEPEND(urtwn, usb, 1, 1, 1); 3524251538SrpauloMODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3525251538SrpauloMODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3526251538SrpauloMODULE_VERSION(urtwn, 1); 3527