if_urtwn.c revision 289066
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 289066 2015-10-09 14:31:32Z kevlo $"); 22 23/* 24 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25 */ 26 27#include "opt_wlan.h" 28 29#include <sys/param.h> 30#include <sys/sockio.h> 31#include <sys/sysctl.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/mbuf.h> 35#include <sys/kernel.h> 36#include <sys/socket.h> 37#include <sys/systm.h> 38#include <sys/malloc.h> 39#include <sys/module.h> 40#include <sys/bus.h> 41#include <sys/endian.h> 42#include <sys/linker.h> 43#include <sys/firmware.h> 44#include <sys/kdb.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48#include <sys/rman.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_var.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/in_var.h> 62#include <netinet/if_ether.h> 63#include <netinet/ip.h> 64 65#include <net80211/ieee80211_var.h> 66#include <net80211/ieee80211_input.h> 67#include <net80211/ieee80211_regdomain.h> 68#include <net80211/ieee80211_radiotap.h> 69#include <net80211/ieee80211_ratectl.h> 70 71#include <dev/usb/usb.h> 72#include <dev/usb/usbdi.h> 73#include "usbdevs.h" 74 75#define USB_DEBUG_VAR urtwn_debug 76#include <dev/usb/usb_debug.h> 77 78#include <dev/usb/wlan/if_urtwnreg.h> 79 80#ifdef USB_DEBUG 81static int urtwn_debug = 0; 82 83SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 84SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 85 "Debug level"); 86#endif 87 88#define URTWN_RSSI(r) (r) - 110 89#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 90 91/* various supported device vendors/products */ 92static const STRUCT_USB_HOST_ID urtwn_devs[] = { 93#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 94#define URTWN_RTL8188E_DEV(v,p) \ 95 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 96#define URTWN_RTL8188E 1 97 URTWN_DEV(ABOCOM, RTL8188CU_1), 98 URTWN_DEV(ABOCOM, RTL8188CU_2), 99 URTWN_DEV(ABOCOM, RTL8192CU), 100 URTWN_DEV(ASUS, RTL8192CU), 101 URTWN_DEV(ASUS, USBN10NANO), 102 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 103 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 104 URTWN_DEV(AZUREWAVE, RTL8188CU), 105 URTWN_DEV(BELKIN, F7D2102), 106 URTWN_DEV(BELKIN, RTL8188CU), 107 URTWN_DEV(BELKIN, RTL8192CU), 108 URTWN_DEV(CHICONY, RTL8188CUS_1), 109 URTWN_DEV(CHICONY, RTL8188CUS_2), 110 URTWN_DEV(CHICONY, RTL8188CUS_3), 111 URTWN_DEV(CHICONY, RTL8188CUS_4), 112 URTWN_DEV(CHICONY, RTL8188CUS_5), 113 URTWN_DEV(COREGA, RTL8192CU), 114 URTWN_DEV(DLINK, RTL8188CU), 115 URTWN_DEV(DLINK, RTL8192CU_1), 116 URTWN_DEV(DLINK, RTL8192CU_2), 117 URTWN_DEV(DLINK, RTL8192CU_3), 118 URTWN_DEV(DLINK, DWA131B), 119 URTWN_DEV(EDIMAX, EW7811UN), 120 URTWN_DEV(EDIMAX, RTL8192CU), 121 URTWN_DEV(FEIXUN, RTL8188CU), 122 URTWN_DEV(FEIXUN, RTL8192CU), 123 URTWN_DEV(GUILLEMOT, HWNUP150), 124 URTWN_DEV(HAWKING, RTL8192CU), 125 URTWN_DEV(HP3, RTL8188CU), 126 URTWN_DEV(NETGEAR, WNA1000M), 127 URTWN_DEV(NETGEAR, RTL8192CU), 128 URTWN_DEV(NETGEAR4, RTL8188CU), 129 URTWN_DEV(NOVATECH, RTL8188CU), 130 URTWN_DEV(PLANEX2, RTL8188CU_1), 131 URTWN_DEV(PLANEX2, RTL8188CU_2), 132 URTWN_DEV(PLANEX2, RTL8188CU_3), 133 URTWN_DEV(PLANEX2, RTL8188CU_4), 134 URTWN_DEV(PLANEX2, RTL8188CUS), 135 URTWN_DEV(PLANEX2, RTL8192CU), 136 URTWN_DEV(REALTEK, RTL8188CE_0), 137 URTWN_DEV(REALTEK, RTL8188CE_1), 138 URTWN_DEV(REALTEK, RTL8188CTV), 139 URTWN_DEV(REALTEK, RTL8188CU_0), 140 URTWN_DEV(REALTEK, RTL8188CU_1), 141 URTWN_DEV(REALTEK, RTL8188CU_2), 142 URTWN_DEV(REALTEK, RTL8188CU_3), 143 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 144 URTWN_DEV(REALTEK, RTL8188CUS), 145 URTWN_DEV(REALTEK, RTL8188RU_1), 146 URTWN_DEV(REALTEK, RTL8188RU_2), 147 URTWN_DEV(REALTEK, RTL8188RU_3), 148 URTWN_DEV(REALTEK, RTL8191CU), 149 URTWN_DEV(REALTEK, RTL8192CE), 150 URTWN_DEV(REALTEK, RTL8192CU), 151 URTWN_DEV(SITECOMEU, RTL8188CU_1), 152 URTWN_DEV(SITECOMEU, RTL8188CU_2), 153 URTWN_DEV(SITECOMEU, RTL8192CU), 154 URTWN_DEV(TRENDNET, RTL8188CU), 155 URTWN_DEV(TRENDNET, RTL8192CU), 156 URTWN_DEV(ZYXEL, RTL8192CU), 157 /* URTWN_RTL8188E */ 158 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 159 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 160 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 161 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 162 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 163#undef URTWN_RTL8188E_DEV 164#undef URTWN_DEV 165}; 166 167static device_probe_t urtwn_match; 168static device_attach_t urtwn_attach; 169static device_detach_t urtwn_detach; 170 171static usb_callback_t urtwn_bulk_tx_callback; 172static usb_callback_t urtwn_bulk_rx_callback; 173 174static void urtwn_drain_mbufq(struct urtwn_softc *sc); 175static usb_error_t urtwn_do_request(struct urtwn_softc *, 176 struct usb_device_request *, void *); 177static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 178 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 179 const uint8_t [IEEE80211_ADDR_LEN], 180 const uint8_t [IEEE80211_ADDR_LEN]); 181static void urtwn_vap_delete(struct ieee80211vap *); 182static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 183 int *); 184static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 185 int *, int8_t *); 186static void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 187static int urtwn_alloc_list(struct urtwn_softc *, 188 struct urtwn_data[], int, int); 189static int urtwn_alloc_rx_list(struct urtwn_softc *); 190static int urtwn_alloc_tx_list(struct urtwn_softc *); 191static void urtwn_free_list(struct urtwn_softc *, 192 struct urtwn_data data[], int); 193static void urtwn_free_rx_list(struct urtwn_softc *); 194static void urtwn_free_tx_list(struct urtwn_softc *); 195static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 196static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 197static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 198 uint8_t *, int); 199static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 200static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 201static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 202static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 203 uint8_t *, int); 204static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 205static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 206static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 207static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 208 const void *, int); 209static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 210 uint8_t, uint32_t); 211static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 212 uint8_t, uint32_t); 213static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 214static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 215 uint32_t); 216static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 217static void urtwn_efuse_read(struct urtwn_softc *); 218static void urtwn_efuse_switch_power(struct urtwn_softc *); 219static int urtwn_read_chipid(struct urtwn_softc *); 220static void urtwn_read_rom(struct urtwn_softc *); 221static void urtwn_r88e_read_rom(struct urtwn_softc *); 222static int urtwn_ra_init(struct urtwn_softc *); 223static void urtwn_tsf_sync_enable(struct urtwn_softc *); 224static void urtwn_set_led(struct urtwn_softc *, int, int); 225static int urtwn_newstate(struct ieee80211vap *, 226 enum ieee80211_state, int); 227static void urtwn_watchdog(void *); 228static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 229static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 230static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 231static int urtwn_tx_start(struct urtwn_softc *, 232 struct ieee80211_node *, struct mbuf *, 233 struct urtwn_data *); 234static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 235static void urtwn_start(struct urtwn_softc *); 236static void urtwn_parent(struct ieee80211com *); 237static int urtwn_r92c_power_on(struct urtwn_softc *); 238static int urtwn_r88e_power_on(struct urtwn_softc *); 239static int urtwn_llt_init(struct urtwn_softc *); 240static void urtwn_fw_reset(struct urtwn_softc *); 241static void urtwn_r88e_fw_reset(struct urtwn_softc *); 242static int urtwn_fw_loadpage(struct urtwn_softc *, int, 243 const uint8_t *, int); 244static int urtwn_load_firmware(struct urtwn_softc *); 245static int urtwn_r92c_dma_init(struct urtwn_softc *); 246static int urtwn_r88e_dma_init(struct urtwn_softc *); 247static void urtwn_mac_init(struct urtwn_softc *); 248static void urtwn_bb_init(struct urtwn_softc *); 249static void urtwn_rf_init(struct urtwn_softc *); 250static void urtwn_cam_init(struct urtwn_softc *); 251static void urtwn_pa_bias_init(struct urtwn_softc *); 252static void urtwn_rxfilter_init(struct urtwn_softc *); 253static void urtwn_edca_init(struct urtwn_softc *); 254static void urtwn_write_txpower(struct urtwn_softc *, int, 255 uint16_t[]); 256static void urtwn_get_txpower(struct urtwn_softc *, int, 257 struct ieee80211_channel *, 258 struct ieee80211_channel *, uint16_t[]); 259static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 260 struct ieee80211_channel *, 261 struct ieee80211_channel *, uint16_t[]); 262static void urtwn_set_txpower(struct urtwn_softc *, 263 struct ieee80211_channel *, 264 struct ieee80211_channel *); 265static void urtwn_scan_start(struct ieee80211com *); 266static void urtwn_scan_end(struct ieee80211com *); 267static void urtwn_set_channel(struct ieee80211com *); 268static void urtwn_update_mcast(struct ieee80211com *); 269static void urtwn_set_chan(struct urtwn_softc *, 270 struct ieee80211_channel *, 271 struct ieee80211_channel *); 272static void urtwn_iq_calib(struct urtwn_softc *); 273static void urtwn_lc_calib(struct urtwn_softc *); 274static void urtwn_init(struct urtwn_softc *); 275static void urtwn_stop(struct urtwn_softc *); 276static void urtwn_abort_xfers(struct urtwn_softc *); 277static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 278 const struct ieee80211_bpf_params *); 279static void urtwn_ms_delay(struct urtwn_softc *); 280 281/* Aliases. */ 282#define urtwn_bb_write urtwn_write_4 283#define urtwn_bb_read urtwn_read_4 284 285static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 286 [URTWN_BULK_RX] = { 287 .type = UE_BULK, 288 .endpoint = UE_ADDR_ANY, 289 .direction = UE_DIR_IN, 290 .bufsize = URTWN_RXBUFSZ, 291 .flags = { 292 .pipe_bof = 1, 293 .short_xfer_ok = 1 294 }, 295 .callback = urtwn_bulk_rx_callback, 296 }, 297 [URTWN_BULK_TX_BE] = { 298 .type = UE_BULK, 299 .endpoint = 0x03, 300 .direction = UE_DIR_OUT, 301 .bufsize = URTWN_TXBUFSZ, 302 .flags = { 303 .ext_buffer = 1, 304 .pipe_bof = 1, 305 .force_short_xfer = 1 306 }, 307 .callback = urtwn_bulk_tx_callback, 308 .timeout = URTWN_TX_TIMEOUT, /* ms */ 309 }, 310 [URTWN_BULK_TX_BK] = { 311 .type = UE_BULK, 312 .endpoint = 0x03, 313 .direction = UE_DIR_OUT, 314 .bufsize = URTWN_TXBUFSZ, 315 .flags = { 316 .ext_buffer = 1, 317 .pipe_bof = 1, 318 .force_short_xfer = 1, 319 }, 320 .callback = urtwn_bulk_tx_callback, 321 .timeout = URTWN_TX_TIMEOUT, /* ms */ 322 }, 323 [URTWN_BULK_TX_VI] = { 324 .type = UE_BULK, 325 .endpoint = 0x02, 326 .direction = UE_DIR_OUT, 327 .bufsize = URTWN_TXBUFSZ, 328 .flags = { 329 .ext_buffer = 1, 330 .pipe_bof = 1, 331 .force_short_xfer = 1 332 }, 333 .callback = urtwn_bulk_tx_callback, 334 .timeout = URTWN_TX_TIMEOUT, /* ms */ 335 }, 336 [URTWN_BULK_TX_VO] = { 337 .type = UE_BULK, 338 .endpoint = 0x02, 339 .direction = UE_DIR_OUT, 340 .bufsize = URTWN_TXBUFSZ, 341 .flags = { 342 .ext_buffer = 1, 343 .pipe_bof = 1, 344 .force_short_xfer = 1 345 }, 346 .callback = urtwn_bulk_tx_callback, 347 .timeout = URTWN_TX_TIMEOUT, /* ms */ 348 }, 349}; 350 351static int 352urtwn_match(device_t self) 353{ 354 struct usb_attach_arg *uaa = device_get_ivars(self); 355 356 if (uaa->usb_mode != USB_MODE_HOST) 357 return (ENXIO); 358 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 359 return (ENXIO); 360 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 361 return (ENXIO); 362 363 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 364} 365 366static int 367urtwn_attach(device_t self) 368{ 369 struct usb_attach_arg *uaa = device_get_ivars(self); 370 struct urtwn_softc *sc = device_get_softc(self); 371 struct ieee80211com *ic = &sc->sc_ic; 372 uint8_t iface_index, bands; 373 int error; 374 375 device_set_usb_desc(self); 376 sc->sc_udev = uaa->device; 377 sc->sc_dev = self; 378 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 379 sc->chip |= URTWN_CHIP_88E; 380 381 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 382 MTX_NETWORK_LOCK, MTX_DEF); 383 callout_init(&sc->sc_watchdog_ch, 0); 384 mbufq_init(&sc->sc_snd, ifqmaxlen); 385 386 iface_index = URTWN_IFACE_INDEX; 387 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 388 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 389 if (error) { 390 device_printf(self, "could not allocate USB transfers, " 391 "err=%s\n", usbd_errstr(error)); 392 goto detach; 393 } 394 395 URTWN_LOCK(sc); 396 397 error = urtwn_read_chipid(sc); 398 if (error) { 399 device_printf(sc->sc_dev, "unsupported test chip\n"); 400 URTWN_UNLOCK(sc); 401 goto detach; 402 } 403 404 /* Determine number of Tx/Rx chains. */ 405 if (sc->chip & URTWN_CHIP_92C) { 406 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 407 sc->nrxchains = 2; 408 } else { 409 sc->ntxchains = 1; 410 sc->nrxchains = 1; 411 } 412 413 if (sc->chip & URTWN_CHIP_88E) 414 urtwn_r88e_read_rom(sc); 415 else 416 urtwn_read_rom(sc); 417 418 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 419 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 420 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 421 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 422 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 423 "8188CUS", sc->ntxchains, sc->nrxchains); 424 425 URTWN_UNLOCK(sc); 426 427 ic->ic_softc = sc; 428 ic->ic_name = device_get_nameunit(self); 429 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 430 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 431 432 /* set device capabilities */ 433 ic->ic_caps = 434 IEEE80211_C_STA /* station mode */ 435 | IEEE80211_C_MONITOR /* monitor mode */ 436 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 437 | IEEE80211_C_SHSLOT /* short slot time supported */ 438 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 439 | IEEE80211_C_WPA /* 802.11i */ 440 ; 441 442 bands = 0; 443 setbit(&bands, IEEE80211_MODE_11B); 444 setbit(&bands, IEEE80211_MODE_11G); 445 ieee80211_init_channels(ic, NULL, &bands); 446 447 ieee80211_ifattach(ic); 448 ic->ic_raw_xmit = urtwn_raw_xmit; 449 ic->ic_scan_start = urtwn_scan_start; 450 ic->ic_scan_end = urtwn_scan_end; 451 ic->ic_set_channel = urtwn_set_channel; 452 ic->ic_transmit = urtwn_transmit; 453 ic->ic_parent = urtwn_parent; 454 ic->ic_vap_create = urtwn_vap_create; 455 ic->ic_vap_delete = urtwn_vap_delete; 456 ic->ic_update_mcast = urtwn_update_mcast; 457 458 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 459 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 460 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 461 URTWN_RX_RADIOTAP_PRESENT); 462 463 if (bootverbose) 464 ieee80211_announce(ic); 465 466 return (0); 467 468detach: 469 urtwn_detach(self); 470 return (ENXIO); /* failure */ 471} 472 473static int 474urtwn_detach(device_t self) 475{ 476 struct urtwn_softc *sc = device_get_softc(self); 477 struct ieee80211com *ic = &sc->sc_ic; 478 unsigned int x; 479 480 /* Prevent further ioctls. */ 481 URTWN_LOCK(sc); 482 sc->sc_flags |= URTWN_DETACHED; 483 urtwn_stop(sc); 484 URTWN_UNLOCK(sc); 485 486 callout_drain(&sc->sc_watchdog_ch); 487 488 /* stop all USB transfers */ 489 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 490 491 /* Prevent further allocations from RX/TX data lists. */ 492 URTWN_LOCK(sc); 493 STAILQ_INIT(&sc->sc_tx_active); 494 STAILQ_INIT(&sc->sc_tx_inactive); 495 STAILQ_INIT(&sc->sc_tx_pending); 496 497 STAILQ_INIT(&sc->sc_rx_active); 498 STAILQ_INIT(&sc->sc_rx_inactive); 499 URTWN_UNLOCK(sc); 500 501 /* drain USB transfers */ 502 for (x = 0; x != URTWN_N_TRANSFER; x++) 503 usbd_transfer_drain(sc->sc_xfer[x]); 504 505 /* Free data buffers. */ 506 URTWN_LOCK(sc); 507 urtwn_free_tx_list(sc); 508 urtwn_free_rx_list(sc); 509 URTWN_UNLOCK(sc); 510 511 ieee80211_ifdetach(ic); 512 mtx_destroy(&sc->sc_mtx); 513 514 return (0); 515} 516 517static void 518urtwn_drain_mbufq(struct urtwn_softc *sc) 519{ 520 struct mbuf *m; 521 struct ieee80211_node *ni; 522 URTWN_ASSERT_LOCKED(sc); 523 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 524 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 525 m->m_pkthdr.rcvif = NULL; 526 ieee80211_free_node(ni); 527 m_freem(m); 528 } 529} 530 531static usb_error_t 532urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 533 void *data) 534{ 535 usb_error_t err; 536 int ntries = 10; 537 538 URTWN_ASSERT_LOCKED(sc); 539 540 while (ntries--) { 541 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 542 req, data, 0, NULL, 250 /* ms */); 543 if (err == 0) 544 break; 545 546 DPRINTFN(1, "Control request failed, %s (retrying)\n", 547 usbd_errstr(err)); 548 usb_pause_mtx(&sc->sc_mtx, hz / 100); 549 } 550 return (err); 551} 552 553static struct ieee80211vap * 554urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 555 enum ieee80211_opmode opmode, int flags, 556 const uint8_t bssid[IEEE80211_ADDR_LEN], 557 const uint8_t mac[IEEE80211_ADDR_LEN]) 558{ 559 struct urtwn_vap *uvp; 560 struct ieee80211vap *vap; 561 562 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 563 return (NULL); 564 565 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 566 vap = &uvp->vap; 567 /* enable s/w bmiss handling for sta mode */ 568 569 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 570 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 571 /* out of memory */ 572 free(uvp, M_80211_VAP); 573 return (NULL); 574 } 575 576 /* override state transition machine */ 577 uvp->newstate = vap->iv_newstate; 578 vap->iv_newstate = urtwn_newstate; 579 580 /* complete setup */ 581 ieee80211_vap_attach(vap, ieee80211_media_change, 582 ieee80211_media_status, mac); 583 ic->ic_opmode = opmode; 584 return (vap); 585} 586 587static void 588urtwn_vap_delete(struct ieee80211vap *vap) 589{ 590 struct urtwn_vap *uvp = URTWN_VAP(vap); 591 592 ieee80211_vap_detach(vap); 593 free(uvp, M_80211_VAP); 594} 595 596static struct mbuf * 597urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 598{ 599 struct ieee80211com *ic = &sc->sc_ic; 600 struct ieee80211_frame *wh; 601 struct mbuf *m; 602 struct r92c_rx_stat *stat; 603 uint32_t rxdw0, rxdw3; 604 uint8_t rate; 605 int8_t rssi = 0; 606 int infosz; 607 608 /* 609 * don't pass packets to the ieee80211 framework if the driver isn't 610 * RUNNING. 611 */ 612 if (!(sc->sc_flags & URTWN_RUNNING)) 613 return (NULL); 614 615 stat = (struct r92c_rx_stat *)buf; 616 rxdw0 = le32toh(stat->rxdw0); 617 rxdw3 = le32toh(stat->rxdw3); 618 619 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 620 /* 621 * This should not happen since we setup our Rx filter 622 * to not receive these frames. 623 */ 624 counter_u64_add(ic->ic_ierrors, 1); 625 return (NULL); 626 } 627 if (pktlen < sizeof(*wh) || pktlen > MCLBYTES) { 628 counter_u64_add(ic->ic_ierrors, 1); 629 return (NULL); 630 } 631 632 rate = MS(rxdw3, R92C_RXDW3_RATE); 633 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 634 635 /* Get RSSI from PHY status descriptor if present. */ 636 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 637 if (sc->chip & URTWN_CHIP_88E) 638 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 639 else 640 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 641 /* Update our average RSSI. */ 642 urtwn_update_avgrssi(sc, rate, rssi); 643 /* 644 * Convert the RSSI to a range that will be accepted 645 * by net80211. 646 */ 647 rssi = URTWN_RSSI(rssi); 648 } 649 650 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 651 if (m == NULL) { 652 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 653 return (NULL); 654 } 655 656 /* Finalize mbuf. */ 657 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 658 memcpy(mtod(m, uint8_t *), wh, pktlen); 659 m->m_pkthdr.len = m->m_len = pktlen; 660 661 if (ieee80211_radiotap_active(ic)) { 662 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 663 664 tap->wr_flags = 0; 665 /* Map HW rate index to 802.11 rate. */ 666 if (!(rxdw3 & R92C_RXDW3_HT)) { 667 switch (rate) { 668 /* CCK. */ 669 case 0: tap->wr_rate = 2; break; 670 case 1: tap->wr_rate = 4; break; 671 case 2: tap->wr_rate = 11; break; 672 case 3: tap->wr_rate = 22; break; 673 /* OFDM. */ 674 case 4: tap->wr_rate = 12; break; 675 case 5: tap->wr_rate = 18; break; 676 case 6: tap->wr_rate = 24; break; 677 case 7: tap->wr_rate = 36; break; 678 case 8: tap->wr_rate = 48; break; 679 case 9: tap->wr_rate = 72; break; 680 case 10: tap->wr_rate = 96; break; 681 case 11: tap->wr_rate = 108; break; 682 } 683 } else if (rate >= 12) { /* MCS0~15. */ 684 /* Bit 7 set means HT MCS instead of rate. */ 685 tap->wr_rate = 0x80 | (rate - 12); 686 } 687 tap->wr_dbm_antsignal = rssi; 688 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 689 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 690 } 691 692 *rssi_p = rssi; 693 694 return (m); 695} 696 697static struct mbuf * 698urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 699 int8_t *nf) 700{ 701 struct urtwn_softc *sc = data->sc; 702 struct ieee80211com *ic = &sc->sc_ic; 703 struct r92c_rx_stat *stat; 704 struct mbuf *m, *m0 = NULL, *prevm = NULL; 705 uint32_t rxdw0; 706 uint8_t *buf; 707 int len, totlen, pktlen, infosz, npkts; 708 709 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 710 711 if (len < sizeof(*stat)) { 712 counter_u64_add(ic->ic_ierrors, 1); 713 return (NULL); 714 } 715 716 buf = data->buf; 717 /* Get the number of encapsulated frames. */ 718 stat = (struct r92c_rx_stat *)buf; 719 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 720 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 721 722 /* Process all of them. */ 723 while (npkts-- > 0) { 724 if (len < sizeof(*stat)) 725 break; 726 stat = (struct r92c_rx_stat *)buf; 727 rxdw0 = le32toh(stat->rxdw0); 728 729 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 730 if (pktlen == 0) 731 break; 732 733 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 734 735 /* Make sure everything fits in xfer. */ 736 totlen = sizeof(*stat) + infosz + pktlen; 737 if (totlen > len) 738 break; 739 740 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 741 if (m0 == NULL) 742 m0 = m; 743 if (prevm == NULL) 744 prevm = m; 745 else { 746 prevm->m_next = m; 747 prevm = m; 748 } 749 750 /* Next chunk is 128-byte aligned. */ 751 totlen = (totlen + 127) & ~127; 752 buf += totlen; 753 len -= totlen; 754 } 755 756 return (m0); 757} 758 759static void 760urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 761{ 762 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 763 struct ieee80211com *ic = &sc->sc_ic; 764 struct ieee80211_frame *wh; 765 struct ieee80211_node *ni; 766 struct mbuf *m = NULL, *next; 767 struct urtwn_data *data; 768 int8_t nf; 769 int rssi = 1; 770 771 URTWN_ASSERT_LOCKED(sc); 772 773 switch (USB_GET_STATE(xfer)) { 774 case USB_ST_TRANSFERRED: 775 data = STAILQ_FIRST(&sc->sc_rx_active); 776 if (data == NULL) 777 goto tr_setup; 778 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 779 m = urtwn_rxeof(xfer, data, &rssi, &nf); 780 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 781 /* FALLTHROUGH */ 782 case USB_ST_SETUP: 783tr_setup: 784 data = STAILQ_FIRST(&sc->sc_rx_inactive); 785 if (data == NULL) { 786 KASSERT(m == NULL, ("mbuf isn't NULL")); 787 return; 788 } 789 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 790 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 791 usbd_xfer_set_frame_data(xfer, 0, data->buf, 792 usbd_xfer_max_len(xfer)); 793 usbd_transfer_submit(xfer); 794 795 /* 796 * To avoid LOR we should unlock our private mutex here to call 797 * ieee80211_input() because here is at the end of a USB 798 * callback and safe to unlock. 799 */ 800 URTWN_UNLOCK(sc); 801 while (m != NULL) { 802 next = m->m_next; 803 m->m_next = NULL; 804 wh = mtod(m, struct ieee80211_frame *); 805 ni = ieee80211_find_rxnode(ic, 806 (struct ieee80211_frame_min *)wh); 807 nf = URTWN_NOISE_FLOOR; 808 if (ni != NULL) { 809 (void)ieee80211_input(ni, m, rssi, nf); 810 ieee80211_free_node(ni); 811 } else 812 (void)ieee80211_input_all(ic, m, rssi, nf); 813 m = next; 814 } 815 URTWN_LOCK(sc); 816 break; 817 default: 818 /* needs it to the inactive queue due to a error. */ 819 data = STAILQ_FIRST(&sc->sc_rx_active); 820 if (data != NULL) { 821 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 822 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 823 } 824 if (error != USB_ERR_CANCELLED) { 825 usbd_xfer_set_stall(xfer); 826 counter_u64_add(ic->ic_ierrors, 1); 827 goto tr_setup; 828 } 829 break; 830 } 831} 832 833static void 834urtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 835{ 836 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 837 838 URTWN_ASSERT_LOCKED(sc); 839 /* XXX status? */ 840 ieee80211_tx_complete(data->ni, data->m, 0); 841 data->ni = NULL; 842 data->m = NULL; 843 sc->sc_txtimer = 0; 844} 845 846static int 847urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 848 int ndata, int maxsz) 849{ 850 int i, error; 851 852 for (i = 0; i < ndata; i++) { 853 struct urtwn_data *dp = &data[i]; 854 dp->sc = sc; 855 dp->m = NULL; 856 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 857 if (dp->buf == NULL) { 858 device_printf(sc->sc_dev, 859 "could not allocate buffer\n"); 860 error = ENOMEM; 861 goto fail; 862 } 863 dp->ni = NULL; 864 } 865 866 return (0); 867fail: 868 urtwn_free_list(sc, data, ndata); 869 return (error); 870} 871 872static int 873urtwn_alloc_rx_list(struct urtwn_softc *sc) 874{ 875 int error, i; 876 877 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 878 URTWN_RXBUFSZ); 879 if (error != 0) 880 return (error); 881 882 STAILQ_INIT(&sc->sc_rx_active); 883 STAILQ_INIT(&sc->sc_rx_inactive); 884 885 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 886 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 887 888 return (0); 889} 890 891static int 892urtwn_alloc_tx_list(struct urtwn_softc *sc) 893{ 894 int error, i; 895 896 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 897 URTWN_TXBUFSZ); 898 if (error != 0) 899 return (error); 900 901 STAILQ_INIT(&sc->sc_tx_active); 902 STAILQ_INIT(&sc->sc_tx_inactive); 903 STAILQ_INIT(&sc->sc_tx_pending); 904 905 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 906 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 907 908 return (0); 909} 910 911static void 912urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 913{ 914 int i; 915 916 for (i = 0; i < ndata; i++) { 917 struct urtwn_data *dp = &data[i]; 918 919 if (dp->buf != NULL) { 920 free(dp->buf, M_USBDEV); 921 dp->buf = NULL; 922 } 923 if (dp->ni != NULL) { 924 ieee80211_free_node(dp->ni); 925 dp->ni = NULL; 926 } 927 } 928} 929 930static void 931urtwn_free_rx_list(struct urtwn_softc *sc) 932{ 933 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 934} 935 936static void 937urtwn_free_tx_list(struct urtwn_softc *sc) 938{ 939 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 940} 941 942static void 943urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 944{ 945 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 946 struct urtwn_data *data; 947 948 URTWN_ASSERT_LOCKED(sc); 949 950 switch (USB_GET_STATE(xfer)){ 951 case USB_ST_TRANSFERRED: 952 data = STAILQ_FIRST(&sc->sc_tx_active); 953 if (data == NULL) 954 goto tr_setup; 955 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 956 urtwn_txeof(xfer, data); 957 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 958 /* FALLTHROUGH */ 959 case USB_ST_SETUP: 960tr_setup: 961 data = STAILQ_FIRST(&sc->sc_tx_pending); 962 if (data == NULL) { 963 DPRINTF("%s: empty pending queue\n", __func__); 964 goto finish; 965 } 966 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 967 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 968 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 969 usbd_transfer_submit(xfer); 970 break; 971 default: 972 data = STAILQ_FIRST(&sc->sc_tx_active); 973 if (data == NULL) 974 goto tr_setup; 975 if (data->ni != NULL) { 976 if_inc_counter(data->ni->ni_vap->iv_ifp, 977 IFCOUNTER_OERRORS, 1); 978 ieee80211_free_node(data->ni); 979 data->ni = NULL; 980 } 981 if (error != USB_ERR_CANCELLED) { 982 usbd_xfer_set_stall(xfer); 983 goto tr_setup; 984 } 985 break; 986 } 987finish: 988 /* Kick-start more transmit */ 989 urtwn_start(sc); 990} 991 992static struct urtwn_data * 993_urtwn_getbuf(struct urtwn_softc *sc) 994{ 995 struct urtwn_data *bf; 996 997 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 998 if (bf != NULL) 999 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1000 else 1001 bf = NULL; 1002 if (bf == NULL) 1003 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 1004 return (bf); 1005} 1006 1007static struct urtwn_data * 1008urtwn_getbuf(struct urtwn_softc *sc) 1009{ 1010 struct urtwn_data *bf; 1011 1012 URTWN_ASSERT_LOCKED(sc); 1013 1014 bf = _urtwn_getbuf(sc); 1015 if (bf == NULL) 1016 DPRINTF("%s: stop queue\n", __func__); 1017 return (bf); 1018} 1019 1020static int 1021urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1022 int len) 1023{ 1024 usb_device_request_t req; 1025 1026 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1027 req.bRequest = R92C_REQ_REGS; 1028 USETW(req.wValue, addr); 1029 USETW(req.wIndex, 0); 1030 USETW(req.wLength, len); 1031 return (urtwn_do_request(sc, &req, buf)); 1032} 1033 1034static void 1035urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1036{ 1037 urtwn_write_region_1(sc, addr, &val, 1); 1038} 1039 1040 1041static void 1042urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1043{ 1044 val = htole16(val); 1045 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1046} 1047 1048static void 1049urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1050{ 1051 val = htole32(val); 1052 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1053} 1054 1055static int 1056urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1057 int len) 1058{ 1059 usb_device_request_t req; 1060 1061 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1062 req.bRequest = R92C_REQ_REGS; 1063 USETW(req.wValue, addr); 1064 USETW(req.wIndex, 0); 1065 USETW(req.wLength, len); 1066 return (urtwn_do_request(sc, &req, buf)); 1067} 1068 1069static uint8_t 1070urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1071{ 1072 uint8_t val; 1073 1074 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1075 return (0xff); 1076 return (val); 1077} 1078 1079static uint16_t 1080urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1081{ 1082 uint16_t val; 1083 1084 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1085 return (0xffff); 1086 return (le16toh(val)); 1087} 1088 1089static uint32_t 1090urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1091{ 1092 uint32_t val; 1093 1094 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1095 return (0xffffffff); 1096 return (le32toh(val)); 1097} 1098 1099static int 1100urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1101{ 1102 struct r92c_fw_cmd cmd; 1103 int ntries; 1104 1105 /* Wait for current FW box to be empty. */ 1106 for (ntries = 0; ntries < 100; ntries++) { 1107 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1108 break; 1109 urtwn_ms_delay(sc); 1110 } 1111 if (ntries == 100) { 1112 device_printf(sc->sc_dev, 1113 "could not send firmware command\n"); 1114 return (ETIMEDOUT); 1115 } 1116 memset(&cmd, 0, sizeof(cmd)); 1117 cmd.id = id; 1118 if (len > 3) 1119 cmd.id |= R92C_CMD_FLAG_EXT; 1120 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1121 memcpy(cmd.msg, buf, len); 1122 1123 /* Write the first word last since that will trigger the FW. */ 1124 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1125 (uint8_t *)&cmd + 4, 2); 1126 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1127 (uint8_t *)&cmd + 0, 4); 1128 1129 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1130 return (0); 1131} 1132 1133static __inline void 1134urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1135{ 1136 1137 sc->sc_rf_write(sc, chain, addr, val); 1138} 1139 1140static void 1141urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1142 uint32_t val) 1143{ 1144 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1145 SM(R92C_LSSI_PARAM_ADDR, addr) | 1146 SM(R92C_LSSI_PARAM_DATA, val)); 1147} 1148 1149static void 1150urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1151uint32_t val) 1152{ 1153 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1154 SM(R88E_LSSI_PARAM_ADDR, addr) | 1155 SM(R92C_LSSI_PARAM_DATA, val)); 1156} 1157 1158static uint32_t 1159urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1160{ 1161 uint32_t reg[R92C_MAX_CHAINS], val; 1162 1163 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1164 if (chain != 0) 1165 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1166 1167 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1168 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1169 urtwn_ms_delay(sc); 1170 1171 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1172 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1173 R92C_HSSI_PARAM2_READ_EDGE); 1174 urtwn_ms_delay(sc); 1175 1176 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1177 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1178 urtwn_ms_delay(sc); 1179 1180 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1181 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1182 else 1183 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1184 return (MS(val, R92C_LSSI_READBACK_DATA)); 1185} 1186 1187static int 1188urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1189{ 1190 int ntries; 1191 1192 urtwn_write_4(sc, R92C_LLT_INIT, 1193 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1194 SM(R92C_LLT_INIT_ADDR, addr) | 1195 SM(R92C_LLT_INIT_DATA, data)); 1196 /* Wait for write operation to complete. */ 1197 for (ntries = 0; ntries < 20; ntries++) { 1198 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1199 R92C_LLT_INIT_OP_NO_ACTIVE) 1200 return (0); 1201 urtwn_ms_delay(sc); 1202 } 1203 return (ETIMEDOUT); 1204} 1205 1206static uint8_t 1207urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1208{ 1209 uint32_t reg; 1210 int ntries; 1211 1212 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1213 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1214 reg &= ~R92C_EFUSE_CTRL_VALID; 1215 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1216 /* Wait for read operation to complete. */ 1217 for (ntries = 0; ntries < 100; ntries++) { 1218 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1219 if (reg & R92C_EFUSE_CTRL_VALID) 1220 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1221 urtwn_ms_delay(sc); 1222 } 1223 device_printf(sc->sc_dev, 1224 "could not read efuse byte at address 0x%x\n", addr); 1225 return (0xff); 1226} 1227 1228static void 1229urtwn_efuse_read(struct urtwn_softc *sc) 1230{ 1231 uint8_t *rom = (uint8_t *)&sc->rom; 1232 uint16_t addr = 0; 1233 uint32_t reg; 1234 uint8_t off, msk; 1235 int i; 1236 1237 urtwn_efuse_switch_power(sc); 1238 1239 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1240 while (addr < 512) { 1241 reg = urtwn_efuse_read_1(sc, addr); 1242 if (reg == 0xff) 1243 break; 1244 addr++; 1245 off = reg >> 4; 1246 msk = reg & 0xf; 1247 for (i = 0; i < 4; i++) { 1248 if (msk & (1 << i)) 1249 continue; 1250 rom[off * 8 + i * 2 + 0] = 1251 urtwn_efuse_read_1(sc, addr); 1252 addr++; 1253 rom[off * 8 + i * 2 + 1] = 1254 urtwn_efuse_read_1(sc, addr); 1255 addr++; 1256 } 1257 } 1258#ifdef URTWN_DEBUG 1259 if (urtwn_debug >= 2) { 1260 /* Dump ROM content. */ 1261 printf("\n"); 1262 for (i = 0; i < sizeof(sc->rom); i++) 1263 printf("%02x:", rom[i]); 1264 printf("\n"); 1265 } 1266#endif 1267 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1268} 1269 1270static void 1271urtwn_efuse_switch_power(struct urtwn_softc *sc) 1272{ 1273 uint32_t reg; 1274 1275 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1276 1277 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1278 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1279 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1280 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1281 } 1282 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1283 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1284 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1285 reg | R92C_SYS_FUNC_EN_ELDR); 1286 } 1287 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1288 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1289 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1290 urtwn_write_2(sc, R92C_SYS_CLKR, 1291 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1292 } 1293} 1294 1295static int 1296urtwn_read_chipid(struct urtwn_softc *sc) 1297{ 1298 uint32_t reg; 1299 1300 if (sc->chip & URTWN_CHIP_88E) 1301 return (0); 1302 1303 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1304 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1305 return (EIO); 1306 1307 if (reg & R92C_SYS_CFG_TYPE_92C) { 1308 sc->chip |= URTWN_CHIP_92C; 1309 /* Check if it is a castrated 8192C. */ 1310 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1311 R92C_HPON_FSM_CHIP_BONDING_ID) == 1312 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1313 sc->chip |= URTWN_CHIP_92C_1T2R; 1314 } 1315 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1316 sc->chip |= URTWN_CHIP_UMC; 1317 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1318 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1319 } 1320 return (0); 1321} 1322 1323static void 1324urtwn_read_rom(struct urtwn_softc *sc) 1325{ 1326 struct r92c_rom *rom = &sc->rom; 1327 1328 /* Read full ROM image. */ 1329 urtwn_efuse_read(sc); 1330 1331 /* XXX Weird but this is what the vendor driver does. */ 1332 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1333 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1334 1335 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1336 1337 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1338 DPRINTF("regulatory type=%d\n", sc->regulatory); 1339 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1340 1341 sc->sc_rf_write = urtwn_r92c_rf_write; 1342 sc->sc_power_on = urtwn_r92c_power_on; 1343 sc->sc_dma_init = urtwn_r92c_dma_init; 1344} 1345 1346static void 1347urtwn_r88e_read_rom(struct urtwn_softc *sc) 1348{ 1349 uint8_t *rom = sc->r88e_rom; 1350 uint16_t addr = 0; 1351 uint32_t reg; 1352 uint8_t off, msk, tmp; 1353 int i; 1354 1355 off = 0; 1356 urtwn_efuse_switch_power(sc); 1357 1358 /* Read full ROM image. */ 1359 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1360 while (addr < 512) { 1361 reg = urtwn_efuse_read_1(sc, addr); 1362 if (reg == 0xff) 1363 break; 1364 addr++; 1365 if ((reg & 0x1f) == 0x0f) { 1366 tmp = (reg & 0xe0) >> 5; 1367 reg = urtwn_efuse_read_1(sc, addr); 1368 if ((reg & 0x0f) != 0x0f) 1369 off = ((reg & 0xf0) >> 1) | tmp; 1370 addr++; 1371 } else 1372 off = reg >> 4; 1373 msk = reg & 0xf; 1374 for (i = 0; i < 4; i++) { 1375 if (msk & (1 << i)) 1376 continue; 1377 rom[off * 8 + i * 2 + 0] = 1378 urtwn_efuse_read_1(sc, addr); 1379 addr++; 1380 rom[off * 8 + i * 2 + 1] = 1381 urtwn_efuse_read_1(sc, addr); 1382 addr++; 1383 } 1384 } 1385 1386 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1387 1388 addr = 0x10; 1389 for (i = 0; i < 6; i++) 1390 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1391 for (i = 0; i < 5; i++) 1392 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1393 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1394 if (sc->bw20_tx_pwr_diff & 0x08) 1395 sc->bw20_tx_pwr_diff |= 0xf0; 1396 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1397 if (sc->ofdm_tx_pwr_diff & 0x08) 1398 sc->ofdm_tx_pwr_diff |= 0xf0; 1399 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1400 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &sc->r88e_rom[0xd7]); 1401 1402 sc->sc_rf_write = urtwn_r88e_rf_write; 1403 sc->sc_power_on = urtwn_r88e_power_on; 1404 sc->sc_dma_init = urtwn_r88e_dma_init; 1405} 1406 1407/* 1408 * Initialize rate adaptation in firmware. 1409 */ 1410static int 1411urtwn_ra_init(struct urtwn_softc *sc) 1412{ 1413 static const uint8_t map[] = 1414 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1415 struct ieee80211com *ic = &sc->sc_ic; 1416 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1417 struct ieee80211_node *ni; 1418 struct ieee80211_rateset *rs; 1419 struct r92c_fw_cmd_macid_cfg cmd; 1420 uint32_t rates, basicrates; 1421 uint8_t mode; 1422 int maxrate, maxbasicrate, error, i, j; 1423 1424 ni = ieee80211_ref_node(vap->iv_bss); 1425 rs = &ni->ni_rates; 1426 1427 /* Get normal and basic rates mask. */ 1428 rates = basicrates = 0; 1429 maxrate = maxbasicrate = 0; 1430 for (i = 0; i < rs->rs_nrates; i++) { 1431 /* Convert 802.11 rate to HW rate index. */ 1432 for (j = 0; j < nitems(map); j++) 1433 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1434 break; 1435 if (j == nitems(map)) /* Unknown rate, skip. */ 1436 continue; 1437 rates |= 1 << j; 1438 if (j > maxrate) 1439 maxrate = j; 1440 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1441 basicrates |= 1 << j; 1442 if (j > maxbasicrate) 1443 maxbasicrate = j; 1444 } 1445 } 1446 if (ic->ic_curmode == IEEE80211_MODE_11B) 1447 mode = R92C_RAID_11B; 1448 else 1449 mode = R92C_RAID_11BG; 1450 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1451 mode, rates, basicrates); 1452 1453 /* Set rates mask for group addressed frames. */ 1454 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1455 cmd.mask = htole32(mode << 28 | basicrates); 1456 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1457 if (error != 0) { 1458 ieee80211_free_node(ni); 1459 device_printf(sc->sc_dev, 1460 "could not add broadcast station\n"); 1461 return (error); 1462 } 1463 /* Set initial MRR rate. */ 1464 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1465 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1466 maxbasicrate); 1467 1468 /* Set rates mask for unicast frames. */ 1469 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1470 cmd.mask = htole32(mode << 28 | rates); 1471 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1472 if (error != 0) { 1473 ieee80211_free_node(ni); 1474 device_printf(sc->sc_dev, "could not add BSS station\n"); 1475 return (error); 1476 } 1477 /* Set initial MRR rate. */ 1478 DPRINTF("maxrate=%d\n", maxrate); 1479 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1480 maxrate); 1481 1482 /* Indicate highest supported rate. */ 1483 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1484 ieee80211_free_node(ni); 1485 1486 return (0); 1487} 1488 1489void 1490urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1491{ 1492 struct ieee80211com *ic = &sc->sc_ic; 1493 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1494 struct ieee80211_node *ni = vap->iv_bss; 1495 1496 uint64_t tsf; 1497 1498 /* Enable TSF synchronization. */ 1499 urtwn_write_1(sc, R92C_BCN_CTRL, 1500 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1501 1502 urtwn_write_1(sc, R92C_BCN_CTRL, 1503 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1504 1505 /* Set initial TSF. */ 1506 memcpy(&tsf, ni->ni_tstamp.data, 8); 1507 tsf = le64toh(tsf); 1508 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1509 tsf -= IEEE80211_DUR_TU; 1510 urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1511 urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1512 1513 urtwn_write_1(sc, R92C_BCN_CTRL, 1514 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1515} 1516 1517static void 1518urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1519{ 1520 uint8_t reg; 1521 1522 if (led == URTWN_LED_LINK) { 1523 if (sc->chip & URTWN_CHIP_88E) { 1524 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1525 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1526 if (!on) { 1527 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1528 urtwn_write_1(sc, R92C_LEDCFG2, 1529 reg | R92C_LEDCFG0_DIS); 1530 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1531 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1532 0xfe); 1533 } 1534 } else { 1535 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1536 if (!on) 1537 reg |= R92C_LEDCFG0_DIS; 1538 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1539 } 1540 sc->ledlink = on; /* Save LED state. */ 1541 } 1542} 1543 1544static int 1545urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1546{ 1547 struct urtwn_vap *uvp = URTWN_VAP(vap); 1548 struct ieee80211com *ic = vap->iv_ic; 1549 struct urtwn_softc *sc = ic->ic_softc; 1550 struct ieee80211_node *ni; 1551 enum ieee80211_state ostate; 1552 uint32_t reg; 1553 1554 ostate = vap->iv_state; 1555 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1556 ieee80211_state_name[nstate]); 1557 1558 IEEE80211_UNLOCK(ic); 1559 URTWN_LOCK(sc); 1560 callout_stop(&sc->sc_watchdog_ch); 1561 1562 if (ostate == IEEE80211_S_RUN) { 1563 /* Turn link LED off. */ 1564 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1565 1566 /* Set media status to 'No Link'. */ 1567 reg = urtwn_read_4(sc, R92C_CR); 1568 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1569 urtwn_write_4(sc, R92C_CR, reg); 1570 1571 /* Stop Rx of data frames. */ 1572 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1573 1574 /* Rest TSF. */ 1575 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1576 1577 /* Disable TSF synchronization. */ 1578 urtwn_write_1(sc, R92C_BCN_CTRL, 1579 urtwn_read_1(sc, R92C_BCN_CTRL) | 1580 R92C_BCN_CTRL_DIS_TSF_UDT0); 1581 1582 /* Reset EDCA parameters. */ 1583 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1584 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1585 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1586 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1587 } 1588 1589 switch (nstate) { 1590 case IEEE80211_S_INIT: 1591 /* Turn link LED off. */ 1592 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1593 break; 1594 case IEEE80211_S_SCAN: 1595 if (ostate != IEEE80211_S_SCAN) { 1596 /* Allow Rx from any BSSID. */ 1597 urtwn_write_4(sc, R92C_RCR, 1598 urtwn_read_4(sc, R92C_RCR) & 1599 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1600 1601 /* Set gain for scanning. */ 1602 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1603 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1604 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1605 1606 if (!(sc->chip & URTWN_CHIP_88E)) { 1607 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1608 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1609 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1610 } 1611 } 1612 /* Pause AC Tx queues. */ 1613 urtwn_write_1(sc, R92C_TXPAUSE, 1614 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1615 break; 1616 case IEEE80211_S_AUTH: 1617 /* Set initial gain under link. */ 1618 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1619 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1620 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1621 1622 if (!(sc->chip & URTWN_CHIP_88E)) { 1623 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1624 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1625 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1626 } 1627 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1628 break; 1629 case IEEE80211_S_RUN: 1630 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1631 /* Enable Rx of data frames. */ 1632 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1633 1634 /* Turn link LED on. */ 1635 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1636 break; 1637 } 1638 1639 ni = ieee80211_ref_node(vap->iv_bss); 1640 /* Set media status to 'Associated'. */ 1641 reg = urtwn_read_4(sc, R92C_CR); 1642 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1643 urtwn_write_4(sc, R92C_CR, reg); 1644 1645 /* Set BSSID. */ 1646 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1647 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1648 1649 if (ic->ic_curmode == IEEE80211_MODE_11B) 1650 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1651 else /* 802.11b/g */ 1652 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1653 1654 /* Enable Rx of data frames. */ 1655 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1656 1657 /* Flush all AC queues. */ 1658 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1659 1660 /* Set beacon interval. */ 1661 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1662 1663 /* Allow Rx from our BSSID only. */ 1664 urtwn_write_4(sc, R92C_RCR, 1665 urtwn_read_4(sc, R92C_RCR) | 1666 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1667 1668 /* Enable TSF synchronization. */ 1669 urtwn_tsf_sync_enable(sc); 1670 1671 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1672 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1673 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1674 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1675 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1676 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1677 1678 /* Intialize rate adaptation. */ 1679 if (sc->chip & URTWN_CHIP_88E) 1680 ni->ni_txrate = 1681 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1682 else 1683 urtwn_ra_init(sc); 1684 /* Turn link LED on. */ 1685 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1686 1687 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1688 /* Reset temperature calibration state machine. */ 1689 sc->thcal_state = 0; 1690 sc->thcal_lctemp = 0; 1691 ieee80211_free_node(ni); 1692 break; 1693 default: 1694 break; 1695 } 1696 URTWN_UNLOCK(sc); 1697 IEEE80211_LOCK(ic); 1698 return(uvp->newstate(vap, nstate, arg)); 1699} 1700 1701static void 1702urtwn_watchdog(void *arg) 1703{ 1704 struct urtwn_softc *sc = arg; 1705 1706 if (sc->sc_txtimer > 0) { 1707 if (--sc->sc_txtimer == 0) { 1708 device_printf(sc->sc_dev, "device timeout\n"); 1709 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1710 return; 1711 } 1712 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1713 } 1714} 1715 1716static void 1717urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1718{ 1719 int pwdb; 1720 1721 /* Convert antenna signal to percentage. */ 1722 if (rssi <= -100 || rssi >= 20) 1723 pwdb = 0; 1724 else if (rssi >= 0) 1725 pwdb = 100; 1726 else 1727 pwdb = 100 + rssi; 1728 if (!(sc->chip & URTWN_CHIP_88E)) { 1729 if (rate <= 3) { 1730 /* CCK gain is smaller than OFDM/MCS gain. */ 1731 pwdb += 6; 1732 if (pwdb > 100) 1733 pwdb = 100; 1734 if (pwdb <= 14) 1735 pwdb -= 4; 1736 else if (pwdb <= 26) 1737 pwdb -= 8; 1738 else if (pwdb <= 34) 1739 pwdb -= 6; 1740 else if (pwdb <= 42) 1741 pwdb -= 2; 1742 } 1743 } 1744 if (sc->avg_pwdb == -1) /* Init. */ 1745 sc->avg_pwdb = pwdb; 1746 else if (sc->avg_pwdb < pwdb) 1747 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1748 else 1749 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1750 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1751} 1752 1753static int8_t 1754urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1755{ 1756 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1757 struct r92c_rx_phystat *phy; 1758 struct r92c_rx_cck *cck; 1759 uint8_t rpt; 1760 int8_t rssi; 1761 1762 if (rate <= 3) { 1763 cck = (struct r92c_rx_cck *)physt; 1764 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1765 rpt = (cck->agc_rpt >> 5) & 0x3; 1766 rssi = (cck->agc_rpt & 0x1f) << 1; 1767 } else { 1768 rpt = (cck->agc_rpt >> 6) & 0x3; 1769 rssi = cck->agc_rpt & 0x3e; 1770 } 1771 rssi = cckoff[rpt] - rssi; 1772 } else { /* OFDM/HT. */ 1773 phy = (struct r92c_rx_phystat *)physt; 1774 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1775 } 1776 return (rssi); 1777} 1778 1779static int8_t 1780urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1781{ 1782 struct r92c_rx_phystat *phy; 1783 struct r88e_rx_cck *cck; 1784 uint8_t cck_agc_rpt, lna_idx, vga_idx; 1785 int8_t rssi; 1786 1787 rssi = 0; 1788 if (rate <= 3) { 1789 cck = (struct r88e_rx_cck *)physt; 1790 cck_agc_rpt = cck->agc_rpt; 1791 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1792 vga_idx = cck_agc_rpt & 0x1f; 1793 switch (lna_idx) { 1794 case 7: 1795 if (vga_idx <= 27) 1796 rssi = -100 + 2* (27 - vga_idx); 1797 else 1798 rssi = -100; 1799 break; 1800 case 6: 1801 rssi = -48 + 2 * (2 - vga_idx); 1802 break; 1803 case 5: 1804 rssi = -42 + 2 * (7 - vga_idx); 1805 break; 1806 case 4: 1807 rssi = -36 + 2 * (7 - vga_idx); 1808 break; 1809 case 3: 1810 rssi = -24 + 2 * (7 - vga_idx); 1811 break; 1812 case 2: 1813 rssi = -12 + 2 * (5 - vga_idx); 1814 break; 1815 case 1: 1816 rssi = 8 - (2 * vga_idx); 1817 break; 1818 case 0: 1819 rssi = 14 - (2 * vga_idx); 1820 break; 1821 } 1822 rssi += 6; 1823 } else { /* OFDM/HT. */ 1824 phy = (struct r92c_rx_phystat *)physt; 1825 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1826 } 1827 return (rssi); 1828} 1829 1830static int 1831urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1832 struct mbuf *m0, struct urtwn_data *data) 1833{ 1834 struct ieee80211_frame *wh; 1835 struct ieee80211_key *k; 1836 struct ieee80211com *ic = &sc->sc_ic; 1837 struct ieee80211vap *vap = ni->ni_vap; 1838 struct usb_xfer *xfer; 1839 struct r92c_tx_desc *txd; 1840 uint8_t raid, type; 1841 uint16_t sum; 1842 int i, xferlen; 1843 struct usb_xfer *urtwn_pipes[4] = { 1844 sc->sc_xfer[URTWN_BULK_TX_BE], 1845 sc->sc_xfer[URTWN_BULK_TX_BK], 1846 sc->sc_xfer[URTWN_BULK_TX_VI], 1847 sc->sc_xfer[URTWN_BULK_TX_VO] 1848 }; 1849 1850 URTWN_ASSERT_LOCKED(sc); 1851 1852 /* 1853 * Software crypto. 1854 */ 1855 wh = mtod(m0, struct ieee80211_frame *); 1856 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1857 1858 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1859 k = ieee80211_crypto_encap(ni, m0); 1860 if (k == NULL) { 1861 device_printf(sc->sc_dev, 1862 "ieee80211_crypto_encap returns NULL.\n"); 1863 /* XXX we don't expect the fragmented frames */ 1864 return (ENOBUFS); 1865 } 1866 1867 /* in case packet header moved, reset pointer */ 1868 wh = mtod(m0, struct ieee80211_frame *); 1869 } 1870 1871 switch (type) { 1872 case IEEE80211_FC0_TYPE_CTL: 1873 case IEEE80211_FC0_TYPE_MGT: 1874 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1875 break; 1876 default: 1877 KASSERT(M_WME_GETAC(m0) < 4, 1878 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1879 xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1880 break; 1881 } 1882 1883 /* Fill Tx descriptor. */ 1884 txd = (struct r92c_tx_desc *)data->buf; 1885 memset(txd, 0, sizeof(*txd)); 1886 1887 txd->txdw0 |= htole32( 1888 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1889 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1890 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1891 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1892 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1893 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1894 type == IEEE80211_FC0_TYPE_DATA) { 1895 if (ic->ic_curmode == IEEE80211_MODE_11B) 1896 raid = R92C_RAID_11B; 1897 else 1898 raid = R92C_RAID_11BG; 1899 if (sc->chip & URTWN_CHIP_88E) { 1900 txd->txdw1 |= htole32( 1901 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1902 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1903 SM(R92C_TXDW1_RAID, raid)); 1904 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1905 } else { 1906 txd->txdw1 |= htole32( 1907 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1908 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1909 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1910 } 1911 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1912 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1913 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1914 R92C_TXDW4_HWRTSEN); 1915 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1916 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1917 R92C_TXDW4_HWRTSEN); 1918 } 1919 } 1920 /* Send RTS at OFDM24. */ 1921 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1922 txd->txdw5 |= htole32(0x0001ff00); 1923 /* Send data at OFDM54. */ 1924 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1925 } else { 1926 txd->txdw1 |= htole32( 1927 SM(R92C_TXDW1_MACID, 0) | 1928 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1929 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1930 1931 /* Force CCK1. */ 1932 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1933 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1934 } 1935 /* Set sequence number (already little endian). */ 1936 txd->txdseq |= *(uint16_t *)wh->i_seq; 1937 1938 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 1939 /* Use HW sequence numbering for non-QoS frames. */ 1940 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1941 txd->txdseq |= htole16(0x8000); 1942 } else 1943 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1944 1945 /* Compute Tx descriptor checksum. */ 1946 sum = 0; 1947 for (i = 0; i < sizeof(*txd) / 2; i++) 1948 sum ^= ((uint16_t *)txd)[i]; 1949 txd->txdsum = sum; /* NB: already little endian. */ 1950 1951 if (ieee80211_radiotap_active_vap(vap)) { 1952 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1953 1954 tap->wt_flags = 0; 1955 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1956 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1957 ieee80211_radiotap_tx(vap, m0); 1958 } 1959 1960 xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1961 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1962 1963 data->buflen = xferlen; 1964 data->ni = ni; 1965 data->m = m0; 1966 1967 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1968 usbd_transfer_start(xfer); 1969 return (0); 1970} 1971 1972static int 1973urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1974{ 1975 struct urtwn_softc *sc = ic->ic_softc; 1976 int error; 1977 1978 URTWN_LOCK(sc); 1979 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1980 URTWN_UNLOCK(sc); 1981 return (ENXIO); 1982 } 1983 error = mbufq_enqueue(&sc->sc_snd, m); 1984 if (error) { 1985 URTWN_UNLOCK(sc); 1986 return (error); 1987 } 1988 urtwn_start(sc); 1989 URTWN_UNLOCK(sc); 1990 1991 return (0); 1992} 1993 1994static void 1995urtwn_start(struct urtwn_softc *sc) 1996{ 1997 struct ieee80211_node *ni; 1998 struct mbuf *m; 1999 struct urtwn_data *bf; 2000 2001 URTWN_ASSERT_LOCKED(sc); 2002 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2003 bf = urtwn_getbuf(sc); 2004 if (bf == NULL) { 2005 mbufq_prepend(&sc->sc_snd, m); 2006 break; 2007 } 2008 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2009 m->m_pkthdr.rcvif = NULL; 2010 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 2011 if_inc_counter(ni->ni_vap->iv_ifp, 2012 IFCOUNTER_OERRORS, 1); 2013 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2014 m_freem(m); 2015 ieee80211_free_node(ni); 2016 break; 2017 } 2018 sc->sc_txtimer = 5; 2019 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2020 } 2021} 2022 2023static void 2024urtwn_parent(struct ieee80211com *ic) 2025{ 2026 struct urtwn_softc *sc = ic->ic_softc; 2027 int startall = 0; 2028 2029 URTWN_LOCK(sc); 2030 if (sc->sc_flags & URTWN_DETACHED) { 2031 URTWN_UNLOCK(sc); 2032 return; 2033 } 2034 if (ic->ic_nrunning > 0) { 2035 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2036 urtwn_init(sc); 2037 startall = 1; 2038 } 2039 } else if (sc->sc_flags & URTWN_RUNNING) 2040 urtwn_stop(sc); 2041 URTWN_UNLOCK(sc); 2042 2043 if (startall) 2044 ieee80211_start_all(ic); 2045} 2046 2047static __inline int 2048urtwn_power_on(struct urtwn_softc *sc) 2049{ 2050 2051 return sc->sc_power_on(sc); 2052} 2053 2054static int 2055urtwn_r92c_power_on(struct urtwn_softc *sc) 2056{ 2057 uint32_t reg; 2058 int ntries; 2059 2060 /* Wait for autoload done bit. */ 2061 for (ntries = 0; ntries < 1000; ntries++) { 2062 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2063 break; 2064 urtwn_ms_delay(sc); 2065 } 2066 if (ntries == 1000) { 2067 device_printf(sc->sc_dev, 2068 "timeout waiting for chip autoload\n"); 2069 return (ETIMEDOUT); 2070 } 2071 2072 /* Unlock ISO/CLK/Power control register. */ 2073 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2074 /* Move SPS into PWM mode. */ 2075 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2076 urtwn_ms_delay(sc); 2077 2078 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2079 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2080 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2081 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2082 urtwn_ms_delay(sc); 2083 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2084 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2085 ~R92C_SYS_ISO_CTRL_MD2PP); 2086 } 2087 2088 /* Auto enable WLAN. */ 2089 urtwn_write_2(sc, R92C_APS_FSMCO, 2090 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2091 for (ntries = 0; ntries < 1000; ntries++) { 2092 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2093 R92C_APS_FSMCO_APFM_ONMAC)) 2094 break; 2095 urtwn_ms_delay(sc); 2096 } 2097 if (ntries == 1000) { 2098 device_printf(sc->sc_dev, 2099 "timeout waiting for MAC auto ON\n"); 2100 return (ETIMEDOUT); 2101 } 2102 2103 /* Enable radio, GPIO and LED functions. */ 2104 urtwn_write_2(sc, R92C_APS_FSMCO, 2105 R92C_APS_FSMCO_AFSM_HSUS | 2106 R92C_APS_FSMCO_PDN_EN | 2107 R92C_APS_FSMCO_PFM_ALDN); 2108 /* Release RF digital isolation. */ 2109 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2110 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2111 2112 /* Initialize MAC. */ 2113 urtwn_write_1(sc, R92C_APSD_CTRL, 2114 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2115 for (ntries = 0; ntries < 200; ntries++) { 2116 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2117 R92C_APSD_CTRL_OFF_STATUS)) 2118 break; 2119 urtwn_ms_delay(sc); 2120 } 2121 if (ntries == 200) { 2122 device_printf(sc->sc_dev, 2123 "timeout waiting for MAC initialization\n"); 2124 return (ETIMEDOUT); 2125 } 2126 2127 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2128 reg = urtwn_read_2(sc, R92C_CR); 2129 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2130 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2131 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2132 R92C_CR_ENSEC; 2133 urtwn_write_2(sc, R92C_CR, reg); 2134 2135 urtwn_write_1(sc, 0xfe10, 0x19); 2136 return (0); 2137} 2138 2139static int 2140urtwn_r88e_power_on(struct urtwn_softc *sc) 2141{ 2142 uint32_t reg; 2143 int ntries; 2144 2145 /* Wait for power ready bit. */ 2146 for (ntries = 0; ntries < 5000; ntries++) { 2147 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2148 break; 2149 urtwn_ms_delay(sc); 2150 } 2151 if (ntries == 5000) { 2152 device_printf(sc->sc_dev, 2153 "timeout waiting for chip power up\n"); 2154 return (ETIMEDOUT); 2155 } 2156 2157 /* Reset BB. */ 2158 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2159 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2160 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2161 2162 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2163 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2164 2165 /* Disable HWPDN. */ 2166 urtwn_write_2(sc, R92C_APS_FSMCO, 2167 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2168 2169 /* Disable WL suspend. */ 2170 urtwn_write_2(sc, R92C_APS_FSMCO, 2171 urtwn_read_2(sc, R92C_APS_FSMCO) & 2172 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2173 2174 urtwn_write_2(sc, R92C_APS_FSMCO, 2175 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2176 for (ntries = 0; ntries < 5000; ntries++) { 2177 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2178 R92C_APS_FSMCO_APFM_ONMAC)) 2179 break; 2180 urtwn_ms_delay(sc); 2181 } 2182 if (ntries == 5000) 2183 return (ETIMEDOUT); 2184 2185 /* Enable LDO normal mode. */ 2186 urtwn_write_1(sc, R92C_LPLDO_CTRL, 2187 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2188 2189 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2190 urtwn_write_2(sc, R92C_CR, 0); 2191 reg = urtwn_read_2(sc, R92C_CR); 2192 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2193 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2194 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2195 urtwn_write_2(sc, R92C_CR, reg); 2196 2197 return (0); 2198} 2199 2200static int 2201urtwn_llt_init(struct urtwn_softc *sc) 2202{ 2203 int i, error, page_count, pktbuf_count; 2204 2205 page_count = (sc->chip & URTWN_CHIP_88E) ? 2206 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2207 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2208 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2209 2210 /* Reserve pages [0; page_count]. */ 2211 for (i = 0; i < page_count; i++) { 2212 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2213 return (error); 2214 } 2215 /* NB: 0xff indicates end-of-list. */ 2216 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2217 return (error); 2218 /* 2219 * Use pages [page_count + 1; pktbuf_count - 1] 2220 * as ring buffer. 2221 */ 2222 for (++i; i < pktbuf_count - 1; i++) { 2223 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2224 return (error); 2225 } 2226 /* Make the last page point to the beginning of the ring buffer. */ 2227 error = urtwn_llt_write(sc, i, page_count + 1); 2228 return (error); 2229} 2230 2231static void 2232urtwn_fw_reset(struct urtwn_softc *sc) 2233{ 2234 uint16_t reg; 2235 int ntries; 2236 2237 /* Tell 8051 to reset itself. */ 2238 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2239 2240 /* Wait until 8051 resets by itself. */ 2241 for (ntries = 0; ntries < 100; ntries++) { 2242 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2243 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2244 return; 2245 urtwn_ms_delay(sc); 2246 } 2247 /* Force 8051 reset. */ 2248 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2249} 2250 2251static void 2252urtwn_r88e_fw_reset(struct urtwn_softc *sc) 2253{ 2254 uint16_t reg; 2255 2256 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2257 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2258 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2259} 2260 2261static int 2262urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2263{ 2264 uint32_t reg; 2265 int off, mlen, error = 0; 2266 2267 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2268 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2269 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2270 2271 off = R92C_FW_START_ADDR; 2272 while (len > 0) { 2273 if (len > 196) 2274 mlen = 196; 2275 else if (len > 4) 2276 mlen = 4; 2277 else 2278 mlen = 1; 2279 /* XXX fix this deconst */ 2280 error = urtwn_write_region_1(sc, off, 2281 __DECONST(uint8_t *, buf), mlen); 2282 if (error != 0) 2283 break; 2284 off += mlen; 2285 buf += mlen; 2286 len -= mlen; 2287 } 2288 return (error); 2289} 2290 2291static int 2292urtwn_load_firmware(struct urtwn_softc *sc) 2293{ 2294 const struct firmware *fw; 2295 const struct r92c_fw_hdr *hdr; 2296 const char *imagename; 2297 const u_char *ptr; 2298 size_t len; 2299 uint32_t reg; 2300 int mlen, ntries, page, error; 2301 2302 URTWN_UNLOCK(sc); 2303 /* Read firmware image from the filesystem. */ 2304 if (sc->chip & URTWN_CHIP_88E) 2305 imagename = "urtwn-rtl8188eufw"; 2306 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2307 URTWN_CHIP_UMC_A_CUT) 2308 imagename = "urtwn-rtl8192cfwU"; 2309 else 2310 imagename = "urtwn-rtl8192cfwT"; 2311 2312 fw = firmware_get(imagename); 2313 URTWN_LOCK(sc); 2314 if (fw == NULL) { 2315 device_printf(sc->sc_dev, 2316 "failed loadfirmware of file %s\n", imagename); 2317 return (ENOENT); 2318 } 2319 2320 len = fw->datasize; 2321 2322 if (len < sizeof(*hdr)) { 2323 device_printf(sc->sc_dev, "firmware too short\n"); 2324 error = EINVAL; 2325 goto fail; 2326 } 2327 ptr = fw->data; 2328 hdr = (const struct r92c_fw_hdr *)ptr; 2329 /* Check if there is a valid FW header and skip it. */ 2330 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2331 (le16toh(hdr->signature) >> 4) == 0x88e || 2332 (le16toh(hdr->signature) >> 4) == 0x92c) { 2333 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2334 le16toh(hdr->version), le16toh(hdr->subversion), 2335 hdr->month, hdr->date, hdr->hour, hdr->minute); 2336 ptr += sizeof(*hdr); 2337 len -= sizeof(*hdr); 2338 } 2339 2340 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2341 if (sc->chip & URTWN_CHIP_88E) 2342 urtwn_r88e_fw_reset(sc); 2343 else 2344 urtwn_fw_reset(sc); 2345 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2346 } 2347 2348 if (!(sc->chip & URTWN_CHIP_88E)) { 2349 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2350 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2351 R92C_SYS_FUNC_EN_CPUEN); 2352 } 2353 urtwn_write_1(sc, R92C_MCUFWDL, 2354 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2355 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2356 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2357 2358 /* Reset the FWDL checksum. */ 2359 urtwn_write_1(sc, R92C_MCUFWDL, 2360 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2361 2362 for (page = 0; len > 0; page++) { 2363 mlen = min(len, R92C_FW_PAGE_SIZE); 2364 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2365 if (error != 0) { 2366 device_printf(sc->sc_dev, 2367 "could not load firmware page\n"); 2368 goto fail; 2369 } 2370 ptr += mlen; 2371 len -= mlen; 2372 } 2373 urtwn_write_1(sc, R92C_MCUFWDL, 2374 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2375 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2376 2377 /* Wait for checksum report. */ 2378 for (ntries = 0; ntries < 1000; ntries++) { 2379 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2380 break; 2381 urtwn_ms_delay(sc); 2382 } 2383 if (ntries == 1000) { 2384 device_printf(sc->sc_dev, 2385 "timeout waiting for checksum report\n"); 2386 error = ETIMEDOUT; 2387 goto fail; 2388 } 2389 2390 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2391 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2392 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2393 if (sc->chip & URTWN_CHIP_88E) 2394 urtwn_r88e_fw_reset(sc); 2395 /* Wait for firmware readiness. */ 2396 for (ntries = 0; ntries < 1000; ntries++) { 2397 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2398 break; 2399 urtwn_ms_delay(sc); 2400 } 2401 if (ntries == 1000) { 2402 device_printf(sc->sc_dev, 2403 "timeout waiting for firmware readiness\n"); 2404 error = ETIMEDOUT; 2405 goto fail; 2406 } 2407fail: 2408 firmware_put(fw, FIRMWARE_UNLOAD); 2409 return (error); 2410} 2411 2412static __inline int 2413urtwn_dma_init(struct urtwn_softc *sc) 2414{ 2415 2416 return sc->sc_dma_init(sc); 2417} 2418 2419static int 2420urtwn_r92c_dma_init(struct urtwn_softc *sc) 2421{ 2422 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2423 uint32_t reg; 2424 int error; 2425 2426 /* Initialize LLT table. */ 2427 error = urtwn_llt_init(sc); 2428 if (error != 0) 2429 return (error); 2430 2431 /* Get Tx queues to USB endpoints mapping. */ 2432 hashq = hasnq = haslq = 0; 2433 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2434 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2435 if (MS(reg, R92C_USB_EP_HQ) != 0) 2436 hashq = 1; 2437 if (MS(reg, R92C_USB_EP_NQ) != 0) 2438 hasnq = 1; 2439 if (MS(reg, R92C_USB_EP_LQ) != 0) 2440 haslq = 1; 2441 nqueues = hashq + hasnq + haslq; 2442 if (nqueues == 0) 2443 return (EIO); 2444 /* Get the number of pages for each queue. */ 2445 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2446 /* The remaining pages are assigned to the high priority queue. */ 2447 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2448 2449 /* Set number of pages for normal priority queue. */ 2450 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2451 urtwn_write_4(sc, R92C_RQPN, 2452 /* Set number of pages for public queue. */ 2453 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2454 /* Set number of pages for high priority queue. */ 2455 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2456 /* Set number of pages for low priority queue. */ 2457 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2458 /* Load values. */ 2459 R92C_RQPN_LD); 2460 2461 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2462 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2463 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2464 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2465 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2466 2467 /* Set queue to USB pipe mapping. */ 2468 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2469 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2470 if (nqueues == 1) { 2471 if (hashq) 2472 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2473 else if (hasnq) 2474 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2475 else 2476 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2477 } else if (nqueues == 2) { 2478 /* All 2-endpoints configs have a high priority queue. */ 2479 if (!hashq) 2480 return (EIO); 2481 if (hasnq) 2482 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2483 else 2484 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2485 } else 2486 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2487 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2488 2489 /* Set Tx/Rx transfer page boundary. */ 2490 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2491 2492 /* Set Tx/Rx transfer page size. */ 2493 urtwn_write_1(sc, R92C_PBP, 2494 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2495 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2496 return (0); 2497} 2498 2499static int 2500urtwn_r88e_dma_init(struct urtwn_softc *sc) 2501{ 2502 struct usb_interface *iface; 2503 uint32_t reg; 2504 int nqueues; 2505 int error; 2506 2507 /* Initialize LLT table. */ 2508 error = urtwn_llt_init(sc); 2509 if (error != 0) 2510 return (error); 2511 2512 /* Get Tx queues to USB endpoints mapping. */ 2513 iface = usbd_get_iface(sc->sc_udev, 0); 2514 nqueues = iface->idesc->bNumEndpoints - 1; 2515 if (nqueues == 0) 2516 return (EIO); 2517 2518 /* Set number of pages for normal priority queue. */ 2519 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2520 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2521 2522 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2523 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2524 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2525 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2526 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2527 2528 /* Set queue to USB pipe mapping. */ 2529 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2530 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2531 if (nqueues == 1) 2532 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2533 else if (nqueues == 2) 2534 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2535 else 2536 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2537 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2538 2539 /* Set Tx/Rx transfer page boundary. */ 2540 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2541 2542 /* Set Tx/Rx transfer page size. */ 2543 urtwn_write_1(sc, R92C_PBP, 2544 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2545 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2546 2547 return (0); 2548} 2549 2550static void 2551urtwn_mac_init(struct urtwn_softc *sc) 2552{ 2553 int i; 2554 2555 /* Write MAC initialization values. */ 2556 if (sc->chip & URTWN_CHIP_88E) { 2557 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2558 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2559 rtl8188eu_mac[i].val); 2560 } 2561 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2562 } else { 2563 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2564 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2565 rtl8192cu_mac[i].val); 2566 } 2567} 2568 2569static void 2570urtwn_bb_init(struct urtwn_softc *sc) 2571{ 2572 const struct urtwn_bb_prog *prog; 2573 uint32_t reg; 2574 uint8_t crystalcap; 2575 int i; 2576 2577 /* Enable BB and RF. */ 2578 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2579 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2580 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2581 R92C_SYS_FUNC_EN_DIO_RF); 2582 2583 if (!(sc->chip & URTWN_CHIP_88E)) 2584 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2585 2586 urtwn_write_1(sc, R92C_RF_CTRL, 2587 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2588 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2589 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2590 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2591 2592 if (!(sc->chip & URTWN_CHIP_88E)) { 2593 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2594 urtwn_write_1(sc, 0x15, 0xe9); 2595 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2596 } 2597 2598 /* Select BB programming based on board type. */ 2599 if (sc->chip & URTWN_CHIP_88E) 2600 prog = &rtl8188eu_bb_prog; 2601 else if (!(sc->chip & URTWN_CHIP_92C)) { 2602 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2603 prog = &rtl8188ce_bb_prog; 2604 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2605 prog = &rtl8188ru_bb_prog; 2606 else 2607 prog = &rtl8188cu_bb_prog; 2608 } else { 2609 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2610 prog = &rtl8192ce_bb_prog; 2611 else 2612 prog = &rtl8192cu_bb_prog; 2613 } 2614 /* Write BB initialization values. */ 2615 for (i = 0; i < prog->count; i++) { 2616 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2617 urtwn_ms_delay(sc); 2618 } 2619 2620 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2621 /* 8192C 1T only configuration. */ 2622 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2623 reg = (reg & ~0x00000003) | 0x2; 2624 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2625 2626 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2627 reg = (reg & ~0x00300033) | 0x00200022; 2628 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2629 2630 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2631 reg = (reg & ~0xff000000) | 0x45 << 24; 2632 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2633 2634 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2635 reg = (reg & ~0x000000ff) | 0x23; 2636 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2637 2638 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2639 reg = (reg & ~0x00000030) | 1 << 4; 2640 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2641 2642 reg = urtwn_bb_read(sc, 0xe74); 2643 reg = (reg & ~0x0c000000) | 2 << 26; 2644 urtwn_bb_write(sc, 0xe74, reg); 2645 reg = urtwn_bb_read(sc, 0xe78); 2646 reg = (reg & ~0x0c000000) | 2 << 26; 2647 urtwn_bb_write(sc, 0xe78, reg); 2648 reg = urtwn_bb_read(sc, 0xe7c); 2649 reg = (reg & ~0x0c000000) | 2 << 26; 2650 urtwn_bb_write(sc, 0xe7c, reg); 2651 reg = urtwn_bb_read(sc, 0xe80); 2652 reg = (reg & ~0x0c000000) | 2 << 26; 2653 urtwn_bb_write(sc, 0xe80, reg); 2654 reg = urtwn_bb_read(sc, 0xe88); 2655 reg = (reg & ~0x0c000000) | 2 << 26; 2656 urtwn_bb_write(sc, 0xe88, reg); 2657 } 2658 2659 /* Write AGC values. */ 2660 for (i = 0; i < prog->agccount; i++) { 2661 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2662 prog->agcvals[i]); 2663 urtwn_ms_delay(sc); 2664 } 2665 2666 if (sc->chip & URTWN_CHIP_88E) { 2667 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2668 urtwn_ms_delay(sc); 2669 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2670 urtwn_ms_delay(sc); 2671 2672 crystalcap = sc->r88e_rom[0xb9]; 2673 if (crystalcap == 0xff) 2674 crystalcap = 0x20; 2675 crystalcap &= 0x3f; 2676 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2677 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2678 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2679 crystalcap | crystalcap << 6)); 2680 } else { 2681 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2682 R92C_HSSI_PARAM2_CCK_HIPWR) 2683 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2684 } 2685} 2686 2687static void 2688urtwn_rf_init(struct urtwn_softc *sc) 2689{ 2690 const struct urtwn_rf_prog *prog; 2691 uint32_t reg, type; 2692 int i, j, idx, off; 2693 2694 /* Select RF programming based on board type. */ 2695 if (sc->chip & URTWN_CHIP_88E) 2696 prog = rtl8188eu_rf_prog; 2697 else if (!(sc->chip & URTWN_CHIP_92C)) { 2698 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2699 prog = rtl8188ce_rf_prog; 2700 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2701 prog = rtl8188ru_rf_prog; 2702 else 2703 prog = rtl8188cu_rf_prog; 2704 } else 2705 prog = rtl8192ce_rf_prog; 2706 2707 for (i = 0; i < sc->nrxchains; i++) { 2708 /* Save RF_ENV control type. */ 2709 idx = i / 2; 2710 off = (i % 2) * 16; 2711 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2712 type = (reg >> off) & 0x10; 2713 2714 /* Set RF_ENV enable. */ 2715 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2716 reg |= 0x100000; 2717 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2718 urtwn_ms_delay(sc); 2719 /* Set RF_ENV output high. */ 2720 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2721 reg |= 0x10; 2722 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2723 urtwn_ms_delay(sc); 2724 /* Set address and data lengths of RF registers. */ 2725 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2726 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2727 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2728 urtwn_ms_delay(sc); 2729 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2730 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2731 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2732 urtwn_ms_delay(sc); 2733 2734 /* Write RF initialization values for this chain. */ 2735 for (j = 0; j < prog[i].count; j++) { 2736 if (prog[i].regs[j] >= 0xf9 && 2737 prog[i].regs[j] <= 0xfe) { 2738 /* 2739 * These are fake RF registers offsets that 2740 * indicate a delay is required. 2741 */ 2742 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2743 continue; 2744 } 2745 urtwn_rf_write(sc, i, prog[i].regs[j], 2746 prog[i].vals[j]); 2747 urtwn_ms_delay(sc); 2748 } 2749 2750 /* Restore RF_ENV control type. */ 2751 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2752 reg &= ~(0x10 << off) | (type << off); 2753 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2754 2755 /* Cache RF register CHNLBW. */ 2756 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2757 } 2758 2759 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2760 URTWN_CHIP_UMC_A_CUT) { 2761 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2762 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2763 } 2764} 2765 2766static void 2767urtwn_cam_init(struct urtwn_softc *sc) 2768{ 2769 /* Invalidate all CAM entries. */ 2770 urtwn_write_4(sc, R92C_CAMCMD, 2771 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2772} 2773 2774static void 2775urtwn_pa_bias_init(struct urtwn_softc *sc) 2776{ 2777 uint8_t reg; 2778 int i; 2779 2780 for (i = 0; i < sc->nrxchains; i++) { 2781 if (sc->pa_setting & (1 << i)) 2782 continue; 2783 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2784 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2785 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2786 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2787 } 2788 if (!(sc->pa_setting & 0x10)) { 2789 reg = urtwn_read_1(sc, 0x16); 2790 reg = (reg & ~0xf0) | 0x90; 2791 urtwn_write_1(sc, 0x16, reg); 2792 } 2793} 2794 2795static void 2796urtwn_rxfilter_init(struct urtwn_softc *sc) 2797{ 2798 /* Initialize Rx filter. */ 2799 /* TODO: use better filter for monitor mode. */ 2800 urtwn_write_4(sc, R92C_RCR, 2801 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2802 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2803 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2804 /* Accept all multicast frames. */ 2805 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2806 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2807 /* Accept all management frames. */ 2808 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2809 /* Reject all control frames. */ 2810 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2811 /* Accept all data frames. */ 2812 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2813} 2814 2815static void 2816urtwn_edca_init(struct urtwn_softc *sc) 2817{ 2818 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2819 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2820 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2821 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2822 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2823 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2824 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2825 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2826} 2827 2828static void 2829urtwn_write_txpower(struct urtwn_softc *sc, int chain, 2830 uint16_t power[URTWN_RIDX_COUNT]) 2831{ 2832 uint32_t reg; 2833 2834 /* Write per-CCK rate Tx power. */ 2835 if (chain == 0) { 2836 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2837 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2838 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2839 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2840 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2841 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2842 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2843 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2844 } else { 2845 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2846 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2847 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2848 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2849 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2850 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2851 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2852 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2853 } 2854 /* Write per-OFDM rate Tx power. */ 2855 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2856 SM(R92C_TXAGC_RATE06, power[ 4]) | 2857 SM(R92C_TXAGC_RATE09, power[ 5]) | 2858 SM(R92C_TXAGC_RATE12, power[ 6]) | 2859 SM(R92C_TXAGC_RATE18, power[ 7])); 2860 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2861 SM(R92C_TXAGC_RATE24, power[ 8]) | 2862 SM(R92C_TXAGC_RATE36, power[ 9]) | 2863 SM(R92C_TXAGC_RATE48, power[10]) | 2864 SM(R92C_TXAGC_RATE54, power[11])); 2865 /* Write per-MCS Tx power. */ 2866 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2867 SM(R92C_TXAGC_MCS00, power[12]) | 2868 SM(R92C_TXAGC_MCS01, power[13]) | 2869 SM(R92C_TXAGC_MCS02, power[14]) | 2870 SM(R92C_TXAGC_MCS03, power[15])); 2871 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2872 SM(R92C_TXAGC_MCS04, power[16]) | 2873 SM(R92C_TXAGC_MCS05, power[17]) | 2874 SM(R92C_TXAGC_MCS06, power[18]) | 2875 SM(R92C_TXAGC_MCS07, power[19])); 2876 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2877 SM(R92C_TXAGC_MCS08, power[20]) | 2878 SM(R92C_TXAGC_MCS09, power[21]) | 2879 SM(R92C_TXAGC_MCS10, power[22]) | 2880 SM(R92C_TXAGC_MCS11, power[23])); 2881 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2882 SM(R92C_TXAGC_MCS12, power[24]) | 2883 SM(R92C_TXAGC_MCS13, power[25]) | 2884 SM(R92C_TXAGC_MCS14, power[26]) | 2885 SM(R92C_TXAGC_MCS15, power[27])); 2886} 2887 2888static void 2889urtwn_get_txpower(struct urtwn_softc *sc, int chain, 2890 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2891 uint16_t power[URTWN_RIDX_COUNT]) 2892{ 2893 struct ieee80211com *ic = &sc->sc_ic; 2894 struct r92c_rom *rom = &sc->rom; 2895 uint16_t cckpow, ofdmpow, htpow, diff, max; 2896 const struct urtwn_txpwr *base; 2897 int ridx, chan, group; 2898 2899 /* Determine channel group. */ 2900 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2901 if (chan <= 3) 2902 group = 0; 2903 else if (chan <= 9) 2904 group = 1; 2905 else 2906 group = 2; 2907 2908 /* Get original Tx power based on board type and RF chain. */ 2909 if (!(sc->chip & URTWN_CHIP_92C)) { 2910 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2911 base = &rtl8188ru_txagc[chain]; 2912 else 2913 base = &rtl8192cu_txagc[chain]; 2914 } else 2915 base = &rtl8192cu_txagc[chain]; 2916 2917 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2918 if (sc->regulatory == 0) { 2919 for (ridx = 0; ridx <= 3; ridx++) 2920 power[ridx] = base->pwr[0][ridx]; 2921 } 2922 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 2923 if (sc->regulatory == 3) { 2924 power[ridx] = base->pwr[0][ridx]; 2925 /* Apply vendor limits. */ 2926 if (extc != NULL) 2927 max = rom->ht40_max_pwr[group]; 2928 else 2929 max = rom->ht20_max_pwr[group]; 2930 max = (max >> (chain * 4)) & 0xf; 2931 if (power[ridx] > max) 2932 power[ridx] = max; 2933 } else if (sc->regulatory == 1) { 2934 if (extc == NULL) 2935 power[ridx] = base->pwr[group][ridx]; 2936 } else if (sc->regulatory != 2) 2937 power[ridx] = base->pwr[0][ridx]; 2938 } 2939 2940 /* Compute per-CCK rate Tx power. */ 2941 cckpow = rom->cck_tx_pwr[chain][group]; 2942 for (ridx = 0; ridx <= 3; ridx++) { 2943 power[ridx] += cckpow; 2944 if (power[ridx] > R92C_MAX_TX_PWR) 2945 power[ridx] = R92C_MAX_TX_PWR; 2946 } 2947 2948 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2949 if (sc->ntxchains > 1) { 2950 /* Apply reduction for 2 spatial streams. */ 2951 diff = rom->ht40_2s_tx_pwr_diff[group]; 2952 diff = (diff >> (chain * 4)) & 0xf; 2953 htpow = (htpow > diff) ? htpow - diff : 0; 2954 } 2955 2956 /* Compute per-OFDM rate Tx power. */ 2957 diff = rom->ofdm_tx_pwr_diff[group]; 2958 diff = (diff >> (chain * 4)) & 0xf; 2959 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2960 for (ridx = 4; ridx <= 11; ridx++) { 2961 power[ridx] += ofdmpow; 2962 if (power[ridx] > R92C_MAX_TX_PWR) 2963 power[ridx] = R92C_MAX_TX_PWR; 2964 } 2965 2966 /* Compute per-MCS Tx power. */ 2967 if (extc == NULL) { 2968 diff = rom->ht20_tx_pwr_diff[group]; 2969 diff = (diff >> (chain * 4)) & 0xf; 2970 htpow += diff; /* HT40->HT20 correction. */ 2971 } 2972 for (ridx = 12; ridx <= 27; ridx++) { 2973 power[ridx] += htpow; 2974 if (power[ridx] > R92C_MAX_TX_PWR) 2975 power[ridx] = R92C_MAX_TX_PWR; 2976 } 2977#ifdef URTWN_DEBUG 2978 if (urtwn_debug >= 4) { 2979 /* Dump per-rate Tx power values. */ 2980 printf("Tx power for chain %d:\n", chain); 2981 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 2982 printf("Rate %d = %u\n", ridx, power[ridx]); 2983 } 2984#endif 2985} 2986 2987static void 2988urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 2989 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2990 uint16_t power[URTWN_RIDX_COUNT]) 2991{ 2992 struct ieee80211com *ic = &sc->sc_ic; 2993 uint16_t cckpow, ofdmpow, bw20pow, htpow; 2994 const struct urtwn_r88e_txpwr *base; 2995 int ridx, chan, group; 2996 2997 /* Determine channel group. */ 2998 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2999 if (chan <= 2) 3000 group = 0; 3001 else if (chan <= 5) 3002 group = 1; 3003 else if (chan <= 8) 3004 group = 2; 3005 else if (chan <= 11) 3006 group = 3; 3007 else if (chan <= 13) 3008 group = 4; 3009 else 3010 group = 5; 3011 3012 /* Get original Tx power based on board type and RF chain. */ 3013 base = &rtl8188eu_txagc[chain]; 3014 3015 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3016 if (sc->regulatory == 0) { 3017 for (ridx = 0; ridx <= 3; ridx++) 3018 power[ridx] = base->pwr[0][ridx]; 3019 } 3020 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3021 if (sc->regulatory == 3) 3022 power[ridx] = base->pwr[0][ridx]; 3023 else if (sc->regulatory == 1) { 3024 if (extc == NULL) 3025 power[ridx] = base->pwr[group][ridx]; 3026 } else if (sc->regulatory != 2) 3027 power[ridx] = base->pwr[0][ridx]; 3028 } 3029 3030 /* Compute per-CCK rate Tx power. */ 3031 cckpow = sc->cck_tx_pwr[group]; 3032 for (ridx = 0; ridx <= 3; ridx++) { 3033 power[ridx] += cckpow; 3034 if (power[ridx] > R92C_MAX_TX_PWR) 3035 power[ridx] = R92C_MAX_TX_PWR; 3036 } 3037 3038 htpow = sc->ht40_tx_pwr[group]; 3039 3040 /* Compute per-OFDM rate Tx power. */ 3041 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3042 for (ridx = 4; ridx <= 11; ridx++) { 3043 power[ridx] += ofdmpow; 3044 if (power[ridx] > R92C_MAX_TX_PWR) 3045 power[ridx] = R92C_MAX_TX_PWR; 3046 } 3047 3048 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3049 for (ridx = 12; ridx <= 27; ridx++) { 3050 power[ridx] += bw20pow; 3051 if (power[ridx] > R92C_MAX_TX_PWR) 3052 power[ridx] = R92C_MAX_TX_PWR; 3053 } 3054} 3055 3056static void 3057urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3058 struct ieee80211_channel *extc) 3059{ 3060 uint16_t power[URTWN_RIDX_COUNT]; 3061 int i; 3062 3063 for (i = 0; i < sc->ntxchains; i++) { 3064 /* Compute per-rate Tx power values. */ 3065 if (sc->chip & URTWN_CHIP_88E) 3066 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3067 else 3068 urtwn_get_txpower(sc, i, c, extc, power); 3069 /* Write per-rate Tx power values to hardware. */ 3070 urtwn_write_txpower(sc, i, power); 3071 } 3072} 3073 3074static void 3075urtwn_scan_start(struct ieee80211com *ic) 3076{ 3077 /* XXX do nothing? */ 3078} 3079 3080static void 3081urtwn_scan_end(struct ieee80211com *ic) 3082{ 3083 /* XXX do nothing? */ 3084} 3085 3086static void 3087urtwn_set_channel(struct ieee80211com *ic) 3088{ 3089 struct urtwn_softc *sc = ic->ic_softc; 3090 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3091 3092 URTWN_LOCK(sc); 3093 if (vap->iv_state == IEEE80211_S_SCAN) { 3094 /* Make link LED blink during scan. */ 3095 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3096 } 3097 urtwn_set_chan(sc, ic->ic_curchan, NULL); 3098 URTWN_UNLOCK(sc); 3099} 3100 3101static void 3102urtwn_update_mcast(struct ieee80211com *ic) 3103{ 3104 /* XXX do nothing? */ 3105} 3106 3107static void 3108urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3109 struct ieee80211_channel *extc) 3110{ 3111 struct ieee80211com *ic = &sc->sc_ic; 3112 uint32_t reg; 3113 u_int chan; 3114 int i; 3115 3116 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3117 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3118 device_printf(sc->sc_dev, 3119 "%s: invalid channel %x\n", __func__, chan); 3120 return; 3121 } 3122 3123 /* Set Tx power for this new channel. */ 3124 urtwn_set_txpower(sc, c, extc); 3125 3126 for (i = 0; i < sc->nrxchains; i++) { 3127 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3128 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3129 } 3130#ifndef IEEE80211_NO_HT 3131 if (extc != NULL) { 3132 /* Is secondary channel below or above primary? */ 3133 int prichlo = c->ic_freq < extc->ic_freq; 3134 3135 urtwn_write_1(sc, R92C_BWOPMODE, 3136 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3137 3138 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3139 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3140 urtwn_write_1(sc, R92C_RRSR + 2, reg); 3141 3142 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3143 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3144 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3145 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3146 3147 /* Set CCK side band. */ 3148 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3149 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3150 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3151 3152 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3153 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3154 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3155 3156 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3157 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3158 ~R92C_FPGA0_ANAPARAM2_CBW20); 3159 3160 reg = urtwn_bb_read(sc, 0x818); 3161 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3162 urtwn_bb_write(sc, 0x818, reg); 3163 3164 /* Select 40MHz bandwidth. */ 3165 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3166 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3167 } else 3168#endif 3169 { 3170 urtwn_write_1(sc, R92C_BWOPMODE, 3171 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3172 3173 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3174 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3175 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3176 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3177 3178 if (!(sc->chip & URTWN_CHIP_88E)) { 3179 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3180 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3181 R92C_FPGA0_ANAPARAM2_CBW20); 3182 } 3183 3184 /* Select 20MHz bandwidth. */ 3185 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3186 (sc->rf_chnlbw[0] & ~0xfff) | chan | 3187 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3188 R92C_RF_CHNLBW_BW20)); 3189 } 3190} 3191 3192static void 3193urtwn_iq_calib(struct urtwn_softc *sc) 3194{ 3195 /* TODO */ 3196} 3197 3198static void 3199urtwn_lc_calib(struct urtwn_softc *sc) 3200{ 3201 uint32_t rf_ac[2]; 3202 uint8_t txmode; 3203 int i; 3204 3205 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3206 if ((txmode & 0x70) != 0) { 3207 /* Disable all continuous Tx. */ 3208 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3209 3210 /* Set RF mode to standby mode. */ 3211 for (i = 0; i < sc->nrxchains; i++) { 3212 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3213 urtwn_rf_write(sc, i, R92C_RF_AC, 3214 RW(rf_ac[i], R92C_RF_AC_MODE, 3215 R92C_RF_AC_MODE_STANDBY)); 3216 } 3217 } else { 3218 /* Block all Tx queues. */ 3219 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3220 } 3221 /* Start calibration. */ 3222 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3223 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3224 3225 /* Give calibration the time to complete. */ 3226 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3227 3228 /* Restore configuration. */ 3229 if ((txmode & 0x70) != 0) { 3230 /* Restore Tx mode. */ 3231 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3232 /* Restore RF mode. */ 3233 for (i = 0; i < sc->nrxchains; i++) 3234 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3235 } else { 3236 /* Unblock all Tx queues. */ 3237 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3238 } 3239} 3240 3241static void 3242urtwn_init(struct urtwn_softc *sc) 3243{ 3244 struct ieee80211com *ic = &sc->sc_ic; 3245 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3246 uint8_t macaddr[IEEE80211_ADDR_LEN]; 3247 uint32_t reg; 3248 int error; 3249 3250 URTWN_ASSERT_LOCKED(sc); 3251 3252 if (sc->sc_flags & URTWN_RUNNING) 3253 urtwn_stop(sc); 3254 3255 /* Init firmware commands ring. */ 3256 sc->fwcur = 0; 3257 3258 /* Allocate Tx/Rx buffers. */ 3259 error = urtwn_alloc_rx_list(sc); 3260 if (error != 0) 3261 goto fail; 3262 3263 error = urtwn_alloc_tx_list(sc); 3264 if (error != 0) 3265 goto fail; 3266 3267 /* Power on adapter. */ 3268 error = urtwn_power_on(sc); 3269 if (error != 0) 3270 goto fail; 3271 3272 /* Initialize DMA. */ 3273 error = urtwn_dma_init(sc); 3274 if (error != 0) 3275 goto fail; 3276 3277 /* Set info size in Rx descriptors (in 64-bit words). */ 3278 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3279 3280 /* Init interrupts. */ 3281 if (sc->chip & URTWN_CHIP_88E) { 3282 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3283 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3284 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3285 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3286 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3287 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3288 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3289 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3290 } else { 3291 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3292 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3293 } 3294 3295 /* Set MAC address. */ 3296 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3297 urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3298 3299 /* Set initial network type. */ 3300 reg = urtwn_read_4(sc, R92C_CR); 3301 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3302 urtwn_write_4(sc, R92C_CR, reg); 3303 3304 urtwn_rxfilter_init(sc); 3305 3306 /* Set response rate. */ 3307 reg = urtwn_read_4(sc, R92C_RRSR); 3308 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3309 urtwn_write_4(sc, R92C_RRSR, reg); 3310 3311 /* Set short/long retry limits. */ 3312 urtwn_write_2(sc, R92C_RL, 3313 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3314 3315 /* Initialize EDCA parameters. */ 3316 urtwn_edca_init(sc); 3317 3318 /* Setup rate fallback. */ 3319 if (!(sc->chip & URTWN_CHIP_88E)) { 3320 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3321 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3322 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3323 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3324 } 3325 3326 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3327 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3328 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3329 /* Set ACK timeout. */ 3330 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3331 3332 /* Setup USB aggregation. */ 3333 reg = urtwn_read_4(sc, R92C_TDECTRL); 3334 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3335 urtwn_write_4(sc, R92C_TDECTRL, reg); 3336 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3337 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3338 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3339 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3340 if (sc->chip & URTWN_CHIP_88E) 3341 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3342 else { 3343 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3344 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3345 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3346 R92C_USB_SPECIAL_OPTION_AGG_EN); 3347 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3348 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3349 } 3350 3351 /* Initialize beacon parameters. */ 3352 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3353 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3354 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3355 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3356 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3357 3358 if (!(sc->chip & URTWN_CHIP_88E)) { 3359 /* Setup AMPDU aggregation. */ 3360 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3361 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3362 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3363 3364 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3365 } 3366 3367 /* Load 8051 microcode. */ 3368 error = urtwn_load_firmware(sc); 3369 if (error != 0) 3370 goto fail; 3371 3372 /* Initialize MAC/BB/RF blocks. */ 3373 urtwn_mac_init(sc); 3374 urtwn_bb_init(sc); 3375 urtwn_rf_init(sc); 3376 3377 if (sc->chip & URTWN_CHIP_88E) { 3378 urtwn_write_2(sc, R92C_CR, 3379 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3380 R92C_CR_MACRXEN); 3381 } 3382 3383 /* Turn CCK and OFDM blocks on. */ 3384 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3385 reg |= R92C_RFMOD_CCK_EN; 3386 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3387 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3388 reg |= R92C_RFMOD_OFDM_EN; 3389 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3390 3391 /* Clear per-station keys table. */ 3392 urtwn_cam_init(sc); 3393 3394 /* Enable hardware sequence numbering. */ 3395 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3396 3397 /* Perform LO and IQ calibrations. */ 3398 urtwn_iq_calib(sc); 3399 /* Perform LC calibration. */ 3400 urtwn_lc_calib(sc); 3401 3402 /* Fix USB interference issue. */ 3403 if (!(sc->chip & URTWN_CHIP_88E)) { 3404 urtwn_write_1(sc, 0xfe40, 0xe0); 3405 urtwn_write_1(sc, 0xfe41, 0x8d); 3406 urtwn_write_1(sc, 0xfe42, 0x80); 3407 3408 urtwn_pa_bias_init(sc); 3409 } 3410 3411 /* Initialize GPIO setting. */ 3412 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3413 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3414 3415 /* Fix for lower temperature. */ 3416 if (!(sc->chip & URTWN_CHIP_88E)) 3417 urtwn_write_1(sc, 0x15, 0xe9); 3418 3419 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3420 3421 sc->sc_flags |= URTWN_RUNNING; 3422 3423 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3424fail: 3425 return; 3426} 3427 3428static void 3429urtwn_stop(struct urtwn_softc *sc) 3430{ 3431 3432 URTWN_ASSERT_LOCKED(sc); 3433 sc->sc_flags &= ~URTWN_RUNNING; 3434 callout_stop(&sc->sc_watchdog_ch); 3435 urtwn_abort_xfers(sc); 3436 3437 urtwn_drain_mbufq(sc); 3438} 3439 3440static void 3441urtwn_abort_xfers(struct urtwn_softc *sc) 3442{ 3443 int i; 3444 3445 URTWN_ASSERT_LOCKED(sc); 3446 3447 /* abort any pending transfers */ 3448 for (i = 0; i < URTWN_N_TRANSFER; i++) 3449 usbd_transfer_stop(sc->sc_xfer[i]); 3450} 3451 3452static int 3453urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3454 const struct ieee80211_bpf_params *params) 3455{ 3456 struct ieee80211com *ic = ni->ni_ic; 3457 struct urtwn_softc *sc = ic->ic_softc; 3458 struct urtwn_data *bf; 3459 3460 /* prevent management frames from being sent if we're not ready */ 3461 if (!(sc->sc_flags & URTWN_RUNNING)) { 3462 m_freem(m); 3463 ieee80211_free_node(ni); 3464 return (ENETDOWN); 3465 } 3466 URTWN_LOCK(sc); 3467 bf = urtwn_getbuf(sc); 3468 if (bf == NULL) { 3469 ieee80211_free_node(ni); 3470 m_freem(m); 3471 URTWN_UNLOCK(sc); 3472 return (ENOBUFS); 3473 } 3474 3475 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3476 m_freem(m); 3477 ieee80211_free_node(ni); 3478 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3479 URTWN_UNLOCK(sc); 3480 return (EIO); 3481 } 3482 sc->sc_txtimer = 5; 3483 URTWN_UNLOCK(sc); 3484 3485 return (0); 3486} 3487 3488static void 3489urtwn_ms_delay(struct urtwn_softc *sc) 3490{ 3491 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3492} 3493 3494static device_method_t urtwn_methods[] = { 3495 /* Device interface */ 3496 DEVMETHOD(device_probe, urtwn_match), 3497 DEVMETHOD(device_attach, urtwn_attach), 3498 DEVMETHOD(device_detach, urtwn_detach), 3499 3500 DEVMETHOD_END 3501}; 3502 3503static driver_t urtwn_driver = { 3504 "urtwn", 3505 urtwn_methods, 3506 sizeof(struct urtwn_softc) 3507}; 3508 3509static devclass_t urtwn_devclass; 3510 3511DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3512MODULE_DEPEND(urtwn, usb, 1, 1, 1); 3513MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3514MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3515MODULE_VERSION(urtwn, 1); 3516