if_urtwn.c revision 288534
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 288534 2015-10-03 06:07:01Z adrian $"); 22 23/* 24 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25 */ 26 27#include "opt_wlan.h" 28 29#include <sys/param.h> 30#include <sys/sockio.h> 31#include <sys/sysctl.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/mbuf.h> 35#include <sys/kernel.h> 36#include <sys/socket.h> 37#include <sys/systm.h> 38#include <sys/malloc.h> 39#include <sys/module.h> 40#include <sys/bus.h> 41#include <sys/endian.h> 42#include <sys/linker.h> 43#include <sys/firmware.h> 44#include <sys/kdb.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48#include <sys/rman.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_var.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/in_var.h> 62#include <netinet/if_ether.h> 63#include <netinet/ip.h> 64 65#include <net80211/ieee80211_var.h> 66#include <net80211/ieee80211_input.h> 67#include <net80211/ieee80211_regdomain.h> 68#include <net80211/ieee80211_radiotap.h> 69#include <net80211/ieee80211_ratectl.h> 70 71#include <dev/usb/usb.h> 72#include <dev/usb/usbdi.h> 73#include "usbdevs.h" 74 75#define USB_DEBUG_VAR urtwn_debug 76#include <dev/usb/usb_debug.h> 77 78#include <dev/usb/wlan/if_urtwnreg.h> 79 80#ifdef USB_DEBUG 81static int urtwn_debug = 0; 82 83SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 84SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 85 "Debug level"); 86#endif 87 88#define URTWN_RSSI(r) (r) - 110 89#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 90 91/* various supported device vendors/products */ 92static const STRUCT_USB_HOST_ID urtwn_devs[] = { 93#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 94#define URTWN_RTL8188E_DEV(v,p) \ 95 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 96#define URTWN_RTL8188E 1 97 URTWN_DEV(ABOCOM, RTL8188CU_1), 98 URTWN_DEV(ABOCOM, RTL8188CU_2), 99 URTWN_DEV(ABOCOM, RTL8192CU), 100 URTWN_DEV(ASUS, RTL8192CU), 101 URTWN_DEV(ASUS, USBN10NANO), 102 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 103 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 104 URTWN_DEV(AZUREWAVE, RTL8188CU), 105 URTWN_DEV(BELKIN, F7D2102), 106 URTWN_DEV(BELKIN, RTL8188CU), 107 URTWN_DEV(BELKIN, RTL8192CU), 108 URTWN_DEV(CHICONY, RTL8188CUS_1), 109 URTWN_DEV(CHICONY, RTL8188CUS_2), 110 URTWN_DEV(CHICONY, RTL8188CUS_3), 111 URTWN_DEV(CHICONY, RTL8188CUS_4), 112 URTWN_DEV(CHICONY, RTL8188CUS_5), 113 URTWN_DEV(COREGA, RTL8192CU), 114 URTWN_DEV(DLINK, RTL8188CU), 115 URTWN_DEV(DLINK, RTL8192CU_1), 116 URTWN_DEV(DLINK, RTL8192CU_2), 117 URTWN_DEV(DLINK, RTL8192CU_3), 118 URTWN_DEV(DLINK, DWA131B), 119 URTWN_DEV(EDIMAX, EW7811UN), 120 URTWN_DEV(EDIMAX, RTL8192CU), 121 URTWN_DEV(FEIXUN, RTL8188CU), 122 URTWN_DEV(FEIXUN, RTL8192CU), 123 URTWN_DEV(GUILLEMOT, HWNUP150), 124 URTWN_DEV(HAWKING, RTL8192CU), 125 URTWN_DEV(HP3, RTL8188CU), 126 URTWN_DEV(NETGEAR, WNA1000M), 127 URTWN_DEV(NETGEAR, RTL8192CU), 128 URTWN_DEV(NETGEAR4, RTL8188CU), 129 URTWN_DEV(NOVATECH, RTL8188CU), 130 URTWN_DEV(PLANEX2, RTL8188CU_1), 131 URTWN_DEV(PLANEX2, RTL8188CU_2), 132 URTWN_DEV(PLANEX2, RTL8188CU_3), 133 URTWN_DEV(PLANEX2, RTL8188CU_4), 134 URTWN_DEV(PLANEX2, RTL8188CUS), 135 URTWN_DEV(PLANEX2, RTL8192CU), 136 URTWN_DEV(REALTEK, RTL8188CE_0), 137 URTWN_DEV(REALTEK, RTL8188CE_1), 138 URTWN_DEV(REALTEK, RTL8188CTV), 139 URTWN_DEV(REALTEK, RTL8188CU_0), 140 URTWN_DEV(REALTEK, RTL8188CU_1), 141 URTWN_DEV(REALTEK, RTL8188CU_2), 142 URTWN_DEV(REALTEK, RTL8188CU_3), 143 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 144 URTWN_DEV(REALTEK, RTL8188CUS), 145 URTWN_DEV(REALTEK, RTL8188RU_1), 146 URTWN_DEV(REALTEK, RTL8188RU_2), 147 URTWN_DEV(REALTEK, RTL8188RU_3), 148 URTWN_DEV(REALTEK, RTL8191CU), 149 URTWN_DEV(REALTEK, RTL8192CE), 150 URTWN_DEV(REALTEK, RTL8192CU), 151 URTWN_DEV(SITECOMEU, RTL8188CU_1), 152 URTWN_DEV(SITECOMEU, RTL8188CU_2), 153 URTWN_DEV(SITECOMEU, RTL8192CU), 154 URTWN_DEV(TRENDNET, RTL8188CU), 155 URTWN_DEV(TRENDNET, RTL8192CU), 156 URTWN_DEV(ZYXEL, RTL8192CU), 157 /* URTWN_RTL8188E */ 158 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 159 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 160 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 161 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 162 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 163#undef URTWN_RTL8188E_DEV 164#undef URTWN_DEV 165}; 166 167static device_probe_t urtwn_match; 168static device_attach_t urtwn_attach; 169static device_detach_t urtwn_detach; 170 171static usb_callback_t urtwn_bulk_tx_callback; 172static usb_callback_t urtwn_bulk_rx_callback; 173 174static void urtwn_drain_mbufq(struct urtwn_softc *sc); 175static usb_error_t urtwn_do_request(struct urtwn_softc *, 176 struct usb_device_request *, void *); 177static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 178 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 179 const uint8_t [IEEE80211_ADDR_LEN], 180 const uint8_t [IEEE80211_ADDR_LEN]); 181static void urtwn_vap_delete(struct ieee80211vap *); 182static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 183 int *); 184static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 185 int *, int8_t *); 186static void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 187static int urtwn_alloc_list(struct urtwn_softc *, 188 struct urtwn_data[], int, int); 189static int urtwn_alloc_rx_list(struct urtwn_softc *); 190static int urtwn_alloc_tx_list(struct urtwn_softc *); 191static void urtwn_free_tx_list(struct urtwn_softc *); 192static void urtwn_free_rx_list(struct urtwn_softc *); 193static void urtwn_free_list(struct urtwn_softc *, 194 struct urtwn_data data[], int); 195static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 196static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 197static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 198 uint8_t *, int); 199static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 200static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 201static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 202static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 203 uint8_t *, int); 204static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 205static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 206static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 207static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 208 const void *, int); 209static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 210 uint8_t, uint32_t); 211static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 212 uint8_t, uint32_t); 213static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 214static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 215 uint32_t); 216static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 217static void urtwn_efuse_read(struct urtwn_softc *); 218static void urtwn_efuse_switch_power(struct urtwn_softc *); 219static int urtwn_read_chipid(struct urtwn_softc *); 220static void urtwn_read_rom(struct urtwn_softc *); 221static void urtwn_r88e_read_rom(struct urtwn_softc *); 222static int urtwn_ra_init(struct urtwn_softc *); 223static void urtwn_tsf_sync_enable(struct urtwn_softc *); 224static void urtwn_set_led(struct urtwn_softc *, int, int); 225static int urtwn_newstate(struct ieee80211vap *, 226 enum ieee80211_state, int); 227static void urtwn_watchdog(void *); 228static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 229static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 230static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 231static int urtwn_tx_start(struct urtwn_softc *, 232 struct ieee80211_node *, struct mbuf *, 233 struct urtwn_data *); 234static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 235static void urtwn_start(struct urtwn_softc *); 236static void urtwn_parent(struct ieee80211com *); 237static int urtwn_r92c_power_on(struct urtwn_softc *); 238static int urtwn_r88e_power_on(struct urtwn_softc *); 239static int urtwn_llt_init(struct urtwn_softc *); 240static void urtwn_fw_reset(struct urtwn_softc *); 241static void urtwn_r88e_fw_reset(struct urtwn_softc *); 242static int urtwn_fw_loadpage(struct urtwn_softc *, int, 243 const uint8_t *, int); 244static int urtwn_load_firmware(struct urtwn_softc *); 245static int urtwn_r92c_dma_init(struct urtwn_softc *); 246static int urtwn_r88e_dma_init(struct urtwn_softc *); 247static void urtwn_mac_init(struct urtwn_softc *); 248static void urtwn_bb_init(struct urtwn_softc *); 249static void urtwn_rf_init(struct urtwn_softc *); 250static void urtwn_cam_init(struct urtwn_softc *); 251static void urtwn_pa_bias_init(struct urtwn_softc *); 252static void urtwn_rxfilter_init(struct urtwn_softc *); 253static void urtwn_edca_init(struct urtwn_softc *); 254static void urtwn_write_txpower(struct urtwn_softc *, int, 255 uint16_t[]); 256static void urtwn_get_txpower(struct urtwn_softc *, int, 257 struct ieee80211_channel *, 258 struct ieee80211_channel *, uint16_t[]); 259static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 260 struct ieee80211_channel *, 261 struct ieee80211_channel *, uint16_t[]); 262static void urtwn_set_txpower(struct urtwn_softc *, 263 struct ieee80211_channel *, 264 struct ieee80211_channel *); 265static void urtwn_scan_start(struct ieee80211com *); 266static void urtwn_scan_end(struct ieee80211com *); 267static void urtwn_set_channel(struct ieee80211com *); 268static void urtwn_set_chan(struct urtwn_softc *, 269 struct ieee80211_channel *, 270 struct ieee80211_channel *); 271static void urtwn_update_mcast(struct ieee80211com *); 272static void urtwn_iq_calib(struct urtwn_softc *); 273static void urtwn_lc_calib(struct urtwn_softc *); 274static void urtwn_init(struct urtwn_softc *); 275static void urtwn_stop(struct urtwn_softc *); 276static void urtwn_abort_xfers(struct urtwn_softc *); 277static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 278 const struct ieee80211_bpf_params *); 279static void urtwn_ms_delay(struct urtwn_softc *); 280 281/* Aliases. */ 282#define urtwn_bb_write urtwn_write_4 283#define urtwn_bb_read urtwn_read_4 284 285static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 286 [URTWN_BULK_RX] = { 287 .type = UE_BULK, 288 .endpoint = UE_ADDR_ANY, 289 .direction = UE_DIR_IN, 290 .bufsize = URTWN_RXBUFSZ, 291 .flags = { 292 .pipe_bof = 1, 293 .short_xfer_ok = 1 294 }, 295 .callback = urtwn_bulk_rx_callback, 296 }, 297 [URTWN_BULK_TX_BE] = { 298 .type = UE_BULK, 299 .endpoint = 0x03, 300 .direction = UE_DIR_OUT, 301 .bufsize = URTWN_TXBUFSZ, 302 .flags = { 303 .ext_buffer = 1, 304 .pipe_bof = 1, 305 .force_short_xfer = 1 306 }, 307 .callback = urtwn_bulk_tx_callback, 308 .timeout = URTWN_TX_TIMEOUT, /* ms */ 309 }, 310 [URTWN_BULK_TX_BK] = { 311 .type = UE_BULK, 312 .endpoint = 0x03, 313 .direction = UE_DIR_OUT, 314 .bufsize = URTWN_TXBUFSZ, 315 .flags = { 316 .ext_buffer = 1, 317 .pipe_bof = 1, 318 .force_short_xfer = 1, 319 }, 320 .callback = urtwn_bulk_tx_callback, 321 .timeout = URTWN_TX_TIMEOUT, /* ms */ 322 }, 323 [URTWN_BULK_TX_VI] = { 324 .type = UE_BULK, 325 .endpoint = 0x02, 326 .direction = UE_DIR_OUT, 327 .bufsize = URTWN_TXBUFSZ, 328 .flags = { 329 .ext_buffer = 1, 330 .pipe_bof = 1, 331 .force_short_xfer = 1 332 }, 333 .callback = urtwn_bulk_tx_callback, 334 .timeout = URTWN_TX_TIMEOUT, /* ms */ 335 }, 336 [URTWN_BULK_TX_VO] = { 337 .type = UE_BULK, 338 .endpoint = 0x02, 339 .direction = UE_DIR_OUT, 340 .bufsize = URTWN_TXBUFSZ, 341 .flags = { 342 .ext_buffer = 1, 343 .pipe_bof = 1, 344 .force_short_xfer = 1 345 }, 346 .callback = urtwn_bulk_tx_callback, 347 .timeout = URTWN_TX_TIMEOUT, /* ms */ 348 }, 349}; 350 351static int 352urtwn_match(device_t self) 353{ 354 struct usb_attach_arg *uaa = device_get_ivars(self); 355 356 if (uaa->usb_mode != USB_MODE_HOST) 357 return (ENXIO); 358 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 359 return (ENXIO); 360 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 361 return (ENXIO); 362 363 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 364} 365 366static int 367urtwn_attach(device_t self) 368{ 369 struct usb_attach_arg *uaa = device_get_ivars(self); 370 struct urtwn_softc *sc = device_get_softc(self); 371 struct ieee80211com *ic = &sc->sc_ic; 372 uint8_t iface_index, bands; 373 int error; 374 375 device_set_usb_desc(self); 376 sc->sc_udev = uaa->device; 377 sc->sc_dev = self; 378 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 379 sc->chip |= URTWN_CHIP_88E; 380 381 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 382 MTX_NETWORK_LOCK, MTX_DEF); 383 callout_init(&sc->sc_watchdog_ch, 0); 384 mbufq_init(&sc->sc_snd, ifqmaxlen); 385 386 iface_index = URTWN_IFACE_INDEX; 387 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 388 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 389 if (error) { 390 device_printf(self, "could not allocate USB transfers, " 391 "err=%s\n", usbd_errstr(error)); 392 goto detach; 393 } 394 395 URTWN_LOCK(sc); 396 397 error = urtwn_read_chipid(sc); 398 if (error) { 399 device_printf(sc->sc_dev, "unsupported test chip\n"); 400 URTWN_UNLOCK(sc); 401 goto detach; 402 } 403 404 /* Determine number of Tx/Rx chains. */ 405 if (sc->chip & URTWN_CHIP_92C) { 406 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 407 sc->nrxchains = 2; 408 } else { 409 sc->ntxchains = 1; 410 sc->nrxchains = 1; 411 } 412 413 if (sc->chip & URTWN_CHIP_88E) 414 urtwn_r88e_read_rom(sc); 415 else 416 urtwn_read_rom(sc); 417 418 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 419 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 420 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 421 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 422 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 423 "8188CUS", sc->ntxchains, sc->nrxchains); 424 425 URTWN_UNLOCK(sc); 426 427 ic->ic_softc = sc; 428 ic->ic_name = device_get_nameunit(self); 429 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 430 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 431 432 /* set device capabilities */ 433 ic->ic_caps = 434 IEEE80211_C_STA /* station mode */ 435 | IEEE80211_C_MONITOR /* monitor mode */ 436 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 437 | IEEE80211_C_SHSLOT /* short slot time supported */ 438 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 439 | IEEE80211_C_WPA /* 802.11i */ 440 ; 441 442 bands = 0; 443 setbit(&bands, IEEE80211_MODE_11B); 444 setbit(&bands, IEEE80211_MODE_11G); 445 ieee80211_init_channels(ic, NULL, &bands); 446 447 ieee80211_ifattach(ic); 448 ic->ic_raw_xmit = urtwn_raw_xmit; 449 ic->ic_scan_start = urtwn_scan_start; 450 ic->ic_scan_end = urtwn_scan_end; 451 ic->ic_set_channel = urtwn_set_channel; 452 ic->ic_transmit = urtwn_transmit; 453 ic->ic_parent = urtwn_parent; 454 ic->ic_vap_create = urtwn_vap_create; 455 ic->ic_vap_delete = urtwn_vap_delete; 456 ic->ic_update_mcast = urtwn_update_mcast; 457 458 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 459 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 460 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 461 URTWN_RX_RADIOTAP_PRESENT); 462 463 if (bootverbose) 464 ieee80211_announce(ic); 465 466 return (0); 467 468detach: 469 urtwn_detach(self); 470 return (ENXIO); /* failure */ 471} 472 473static void 474urtwn_drain_mbufq(struct urtwn_softc *sc) 475{ 476 struct mbuf *m; 477 struct ieee80211_node *ni; 478 URTWN_ASSERT_LOCKED(sc); 479 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 480 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 481 m->m_pkthdr.rcvif = NULL; 482 ieee80211_free_node(ni); 483 m_freem(m); 484 } 485} 486 487static int 488urtwn_detach(device_t self) 489{ 490 struct urtwn_softc *sc = device_get_softc(self); 491 struct ieee80211com *ic = &sc->sc_ic; 492 unsigned int x; 493 494 /* Prevent further ioctls. */ 495 URTWN_LOCK(sc); 496 sc->sc_flags |= URTWN_DETACHED; 497 urtwn_stop(sc); 498 URTWN_UNLOCK(sc); 499 500 callout_drain(&sc->sc_watchdog_ch); 501 502 /* stop all USB transfers */ 503 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 504 505 /* Prevent further allocations from RX/TX data lists. */ 506 URTWN_LOCK(sc); 507 STAILQ_INIT(&sc->sc_tx_active); 508 STAILQ_INIT(&sc->sc_tx_inactive); 509 STAILQ_INIT(&sc->sc_tx_pending); 510 511 STAILQ_INIT(&sc->sc_rx_active); 512 STAILQ_INIT(&sc->sc_rx_inactive); 513 URTWN_UNLOCK(sc); 514 515 /* drain USB transfers */ 516 for (x = 0; x != URTWN_N_TRANSFER; x++) 517 usbd_transfer_drain(sc->sc_xfer[x]); 518 519 /* Free data buffers. */ 520 URTWN_LOCK(sc); 521 urtwn_free_tx_list(sc); 522 urtwn_free_rx_list(sc); 523 URTWN_UNLOCK(sc); 524 525 ieee80211_ifdetach(ic); 526 mtx_destroy(&sc->sc_mtx); 527 528 return (0); 529} 530 531static void 532urtwn_free_tx_list(struct urtwn_softc *sc) 533{ 534 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 535} 536 537static void 538urtwn_free_rx_list(struct urtwn_softc *sc) 539{ 540 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 541} 542 543static void 544urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 545{ 546 int i; 547 548 for (i = 0; i < ndata; i++) { 549 struct urtwn_data *dp = &data[i]; 550 551 if (dp->buf != NULL) { 552 free(dp->buf, M_USBDEV); 553 dp->buf = NULL; 554 } 555 if (dp->ni != NULL) { 556 ieee80211_free_node(dp->ni); 557 dp->ni = NULL; 558 } 559 } 560} 561 562static usb_error_t 563urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 564 void *data) 565{ 566 usb_error_t err; 567 int ntries = 10; 568 569 URTWN_ASSERT_LOCKED(sc); 570 571 while (ntries--) { 572 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 573 req, data, 0, NULL, 250 /* ms */); 574 if (err == 0) 575 break; 576 577 DPRINTFN(1, "Control request failed, %s (retrying)\n", 578 usbd_errstr(err)); 579 usb_pause_mtx(&sc->sc_mtx, hz / 100); 580 } 581 return (err); 582} 583 584static struct ieee80211vap * 585urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 586 enum ieee80211_opmode opmode, int flags, 587 const uint8_t bssid[IEEE80211_ADDR_LEN], 588 const uint8_t mac[IEEE80211_ADDR_LEN]) 589{ 590 struct urtwn_vap *uvp; 591 struct ieee80211vap *vap; 592 593 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 594 return (NULL); 595 596 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 597 vap = &uvp->vap; 598 /* enable s/w bmiss handling for sta mode */ 599 600 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 601 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 602 /* out of memory */ 603 free(uvp, M_80211_VAP); 604 return (NULL); 605 } 606 607 /* override state transition machine */ 608 uvp->newstate = vap->iv_newstate; 609 vap->iv_newstate = urtwn_newstate; 610 611 /* complete setup */ 612 ieee80211_vap_attach(vap, ieee80211_media_change, 613 ieee80211_media_status, mac); 614 ic->ic_opmode = opmode; 615 return (vap); 616} 617 618static void 619urtwn_vap_delete(struct ieee80211vap *vap) 620{ 621 struct urtwn_vap *uvp = URTWN_VAP(vap); 622 623 ieee80211_vap_detach(vap); 624 free(uvp, M_80211_VAP); 625} 626 627static struct mbuf * 628urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 629{ 630 struct ieee80211com *ic = &sc->sc_ic; 631 struct ieee80211_frame *wh; 632 struct mbuf *m; 633 struct r92c_rx_stat *stat; 634 uint32_t rxdw0, rxdw3; 635 uint8_t rate; 636 int8_t rssi = 0; 637 int infosz; 638 639 /* 640 * don't pass packets to the ieee80211 framework if the driver isn't 641 * RUNNING. 642 */ 643 if (!(sc->sc_flags & URTWN_RUNNING)) 644 return (NULL); 645 646 stat = (struct r92c_rx_stat *)buf; 647 rxdw0 = le32toh(stat->rxdw0); 648 rxdw3 = le32toh(stat->rxdw3); 649 650 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 651 /* 652 * This should not happen since we setup our Rx filter 653 * to not receive these frames. 654 */ 655 counter_u64_add(ic->ic_ierrors, 1); 656 return (NULL); 657 } 658 if (pktlen < sizeof(*wh) || pktlen > MCLBYTES) { 659 counter_u64_add(ic->ic_ierrors, 1); 660 return (NULL); 661 } 662 663 rate = MS(rxdw3, R92C_RXDW3_RATE); 664 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 665 666 /* Get RSSI from PHY status descriptor if present. */ 667 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 668 if (sc->chip & URTWN_CHIP_88E) 669 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 670 else 671 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 672 /* Update our average RSSI. */ 673 urtwn_update_avgrssi(sc, rate, rssi); 674 /* 675 * Convert the RSSI to a range that will be accepted 676 * by net80211. 677 */ 678 rssi = URTWN_RSSI(rssi); 679 } 680 681 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 682 if (m == NULL) { 683 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 684 return (NULL); 685 } 686 687 /* Finalize mbuf. */ 688 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 689 memcpy(mtod(m, uint8_t *), wh, pktlen); 690 m->m_pkthdr.len = m->m_len = pktlen; 691 692 if (ieee80211_radiotap_active(ic)) { 693 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 694 695 tap->wr_flags = 0; 696 /* Map HW rate index to 802.11 rate. */ 697 if (!(rxdw3 & R92C_RXDW3_HT)) { 698 switch (rate) { 699 /* CCK. */ 700 case 0: tap->wr_rate = 2; break; 701 case 1: tap->wr_rate = 4; break; 702 case 2: tap->wr_rate = 11; break; 703 case 3: tap->wr_rate = 22; break; 704 /* OFDM. */ 705 case 4: tap->wr_rate = 12; break; 706 case 5: tap->wr_rate = 18; break; 707 case 6: tap->wr_rate = 24; break; 708 case 7: tap->wr_rate = 36; break; 709 case 8: tap->wr_rate = 48; break; 710 case 9: tap->wr_rate = 72; break; 711 case 10: tap->wr_rate = 96; break; 712 case 11: tap->wr_rate = 108; break; 713 } 714 } else if (rate >= 12) { /* MCS0~15. */ 715 /* Bit 7 set means HT MCS instead of rate. */ 716 tap->wr_rate = 0x80 | (rate - 12); 717 } 718 tap->wr_dbm_antsignal = rssi; 719 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 720 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 721 } 722 723 *rssi_p = rssi; 724 725 return (m); 726} 727 728static struct mbuf * 729urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 730 int8_t *nf) 731{ 732 struct urtwn_softc *sc = data->sc; 733 struct ieee80211com *ic = &sc->sc_ic; 734 struct r92c_rx_stat *stat; 735 struct mbuf *m, *m0 = NULL, *prevm = NULL; 736 uint32_t rxdw0; 737 uint8_t *buf; 738 int len, totlen, pktlen, infosz, npkts; 739 740 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 741 742 if (len < sizeof(*stat)) { 743 counter_u64_add(ic->ic_ierrors, 1); 744 return (NULL); 745 } 746 747 buf = data->buf; 748 /* Get the number of encapsulated frames. */ 749 stat = (struct r92c_rx_stat *)buf; 750 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 751 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 752 753 /* Process all of them. */ 754 while (npkts-- > 0) { 755 if (len < sizeof(*stat)) 756 break; 757 stat = (struct r92c_rx_stat *)buf; 758 rxdw0 = le32toh(stat->rxdw0); 759 760 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 761 if (pktlen == 0) 762 break; 763 764 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 765 766 /* Make sure everything fits in xfer. */ 767 totlen = sizeof(*stat) + infosz + pktlen; 768 if (totlen > len) 769 break; 770 771 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 772 if (m0 == NULL) 773 m0 = m; 774 if (prevm == NULL) 775 prevm = m; 776 else { 777 prevm->m_next = m; 778 prevm = m; 779 } 780 781 /* Next chunk is 128-byte aligned. */ 782 totlen = (totlen + 127) & ~127; 783 buf += totlen; 784 len -= totlen; 785 } 786 787 return (m0); 788} 789 790static void 791urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 792{ 793 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 794 struct ieee80211com *ic = &sc->sc_ic; 795 struct ieee80211_frame *wh; 796 struct ieee80211_node *ni; 797 struct mbuf *m = NULL, *next; 798 struct urtwn_data *data; 799 int8_t nf; 800 int rssi = 1; 801 802 URTWN_ASSERT_LOCKED(sc); 803 804 switch (USB_GET_STATE(xfer)) { 805 case USB_ST_TRANSFERRED: 806 data = STAILQ_FIRST(&sc->sc_rx_active); 807 if (data == NULL) 808 goto tr_setup; 809 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 810 m = urtwn_rxeof(xfer, data, &rssi, &nf); 811 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 812 /* FALLTHROUGH */ 813 case USB_ST_SETUP: 814tr_setup: 815 data = STAILQ_FIRST(&sc->sc_rx_inactive); 816 if (data == NULL) { 817 KASSERT(m == NULL, ("mbuf isn't NULL")); 818 return; 819 } 820 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 821 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 822 usbd_xfer_set_frame_data(xfer, 0, data->buf, 823 usbd_xfer_max_len(xfer)); 824 usbd_transfer_submit(xfer); 825 826 /* 827 * To avoid LOR we should unlock our private mutex here to call 828 * ieee80211_input() because here is at the end of a USB 829 * callback and safe to unlock. 830 */ 831 URTWN_UNLOCK(sc); 832 while (m != NULL) { 833 next = m->m_next; 834 m->m_next = NULL; 835 wh = mtod(m, struct ieee80211_frame *); 836 ni = ieee80211_find_rxnode(ic, 837 (struct ieee80211_frame_min *)wh); 838 nf = URTWN_NOISE_FLOOR; 839 if (ni != NULL) { 840 (void)ieee80211_input(ni, m, rssi, nf); 841 ieee80211_free_node(ni); 842 } else 843 (void)ieee80211_input_all(ic, m, rssi, nf); 844 m = next; 845 } 846 URTWN_LOCK(sc); 847 break; 848 default: 849 /* needs it to the inactive queue due to a error. */ 850 data = STAILQ_FIRST(&sc->sc_rx_active); 851 if (data != NULL) { 852 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 853 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 854 } 855 if (error != USB_ERR_CANCELLED) { 856 usbd_xfer_set_stall(xfer); 857 counter_u64_add(ic->ic_ierrors, 1); 858 goto tr_setup; 859 } 860 break; 861 } 862} 863 864static void 865urtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 866{ 867 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 868 869 URTWN_ASSERT_LOCKED(sc); 870 /* XXX status? */ 871 ieee80211_tx_complete(data->ni, data->m, 0); 872 data->ni = NULL; 873 data->m = NULL; 874 sc->sc_txtimer = 0; 875} 876 877static void 878urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 879{ 880 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 881 struct urtwn_data *data; 882 883 URTWN_ASSERT_LOCKED(sc); 884 885 switch (USB_GET_STATE(xfer)){ 886 case USB_ST_TRANSFERRED: 887 data = STAILQ_FIRST(&sc->sc_tx_active); 888 if (data == NULL) 889 goto tr_setup; 890 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 891 urtwn_txeof(xfer, data); 892 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 893 /* FALLTHROUGH */ 894 case USB_ST_SETUP: 895tr_setup: 896 data = STAILQ_FIRST(&sc->sc_tx_pending); 897 if (data == NULL) { 898 DPRINTF("%s: empty pending queue\n", __func__); 899 goto finish; 900 } 901 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 902 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 903 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 904 usbd_transfer_submit(xfer); 905 break; 906 default: 907 data = STAILQ_FIRST(&sc->sc_tx_active); 908 if (data == NULL) 909 goto tr_setup; 910 if (data->ni != NULL) { 911 if_inc_counter(data->ni->ni_vap->iv_ifp, 912 IFCOUNTER_OERRORS, 1); 913 ieee80211_free_node(data->ni); 914 data->ni = NULL; 915 } 916 if (error != USB_ERR_CANCELLED) { 917 usbd_xfer_set_stall(xfer); 918 goto tr_setup; 919 } 920 break; 921 } 922finish: 923 /* Kick-start more transmit */ 924 urtwn_start(sc); 925} 926 927static struct urtwn_data * 928_urtwn_getbuf(struct urtwn_softc *sc) 929{ 930 struct urtwn_data *bf; 931 932 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 933 if (bf != NULL) 934 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 935 else 936 bf = NULL; 937 if (bf == NULL) 938 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 939 return (bf); 940} 941 942static struct urtwn_data * 943urtwn_getbuf(struct urtwn_softc *sc) 944{ 945 struct urtwn_data *bf; 946 947 URTWN_ASSERT_LOCKED(sc); 948 949 bf = _urtwn_getbuf(sc); 950 if (bf == NULL) 951 DPRINTF("%s: stop queue\n", __func__); 952 return (bf); 953} 954 955static int 956urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 957 int len) 958{ 959 usb_device_request_t req; 960 961 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 962 req.bRequest = R92C_REQ_REGS; 963 USETW(req.wValue, addr); 964 USETW(req.wIndex, 0); 965 USETW(req.wLength, len); 966 return (urtwn_do_request(sc, &req, buf)); 967} 968 969static void 970urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 971{ 972 urtwn_write_region_1(sc, addr, &val, 1); 973} 974 975 976static void 977urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 978{ 979 val = htole16(val); 980 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 981} 982 983static void 984urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 985{ 986 val = htole32(val); 987 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 988} 989 990static int 991urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 992 int len) 993{ 994 usb_device_request_t req; 995 996 req.bmRequestType = UT_READ_VENDOR_DEVICE; 997 req.bRequest = R92C_REQ_REGS; 998 USETW(req.wValue, addr); 999 USETW(req.wIndex, 0); 1000 USETW(req.wLength, len); 1001 return (urtwn_do_request(sc, &req, buf)); 1002} 1003 1004static uint8_t 1005urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1006{ 1007 uint8_t val; 1008 1009 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1010 return (0xff); 1011 return (val); 1012} 1013 1014static uint16_t 1015urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1016{ 1017 uint16_t val; 1018 1019 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1020 return (0xffff); 1021 return (le16toh(val)); 1022} 1023 1024static uint32_t 1025urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1026{ 1027 uint32_t val; 1028 1029 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1030 return (0xffffffff); 1031 return (le32toh(val)); 1032} 1033 1034static int 1035urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1036{ 1037 struct r92c_fw_cmd cmd; 1038 int ntries; 1039 1040 /* Wait for current FW box to be empty. */ 1041 for (ntries = 0; ntries < 100; ntries++) { 1042 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1043 break; 1044 urtwn_ms_delay(sc); 1045 } 1046 if (ntries == 100) { 1047 device_printf(sc->sc_dev, 1048 "could not send firmware command\n"); 1049 return (ETIMEDOUT); 1050 } 1051 memset(&cmd, 0, sizeof(cmd)); 1052 cmd.id = id; 1053 if (len > 3) 1054 cmd.id |= R92C_CMD_FLAG_EXT; 1055 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1056 memcpy(cmd.msg, buf, len); 1057 1058 /* Write the first word last since that will trigger the FW. */ 1059 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1060 (uint8_t *)&cmd + 4, 2); 1061 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1062 (uint8_t *)&cmd + 0, 4); 1063 1064 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1065 return (0); 1066} 1067 1068static __inline void 1069urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1070{ 1071 1072 sc->sc_rf_write(sc, chain, addr, val); 1073} 1074 1075static void 1076urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1077 uint32_t val) 1078{ 1079 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1080 SM(R92C_LSSI_PARAM_ADDR, addr) | 1081 SM(R92C_LSSI_PARAM_DATA, val)); 1082} 1083 1084static void 1085urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1086uint32_t val) 1087{ 1088 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1089 SM(R88E_LSSI_PARAM_ADDR, addr) | 1090 SM(R92C_LSSI_PARAM_DATA, val)); 1091} 1092 1093static uint32_t 1094urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1095{ 1096 uint32_t reg[R92C_MAX_CHAINS], val; 1097 1098 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1099 if (chain != 0) 1100 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1101 1102 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1103 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1104 urtwn_ms_delay(sc); 1105 1106 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1107 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1108 R92C_HSSI_PARAM2_READ_EDGE); 1109 urtwn_ms_delay(sc); 1110 1111 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1112 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1113 urtwn_ms_delay(sc); 1114 1115 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1116 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1117 else 1118 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1119 return (MS(val, R92C_LSSI_READBACK_DATA)); 1120} 1121 1122static int 1123urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1124{ 1125 int ntries; 1126 1127 urtwn_write_4(sc, R92C_LLT_INIT, 1128 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1129 SM(R92C_LLT_INIT_ADDR, addr) | 1130 SM(R92C_LLT_INIT_DATA, data)); 1131 /* Wait for write operation to complete. */ 1132 for (ntries = 0; ntries < 20; ntries++) { 1133 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1134 R92C_LLT_INIT_OP_NO_ACTIVE) 1135 return (0); 1136 urtwn_ms_delay(sc); 1137 } 1138 return (ETIMEDOUT); 1139} 1140 1141static uint8_t 1142urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1143{ 1144 uint32_t reg; 1145 int ntries; 1146 1147 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1148 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1149 reg &= ~R92C_EFUSE_CTRL_VALID; 1150 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1151 /* Wait for read operation to complete. */ 1152 for (ntries = 0; ntries < 100; ntries++) { 1153 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1154 if (reg & R92C_EFUSE_CTRL_VALID) 1155 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1156 urtwn_ms_delay(sc); 1157 } 1158 device_printf(sc->sc_dev, 1159 "could not read efuse byte at address 0x%x\n", addr); 1160 return (0xff); 1161} 1162 1163static void 1164urtwn_efuse_read(struct urtwn_softc *sc) 1165{ 1166 uint8_t *rom = (uint8_t *)&sc->rom; 1167 uint16_t addr = 0; 1168 uint32_t reg; 1169 uint8_t off, msk; 1170 int i; 1171 1172 urtwn_efuse_switch_power(sc); 1173 1174 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1175 while (addr < 512) { 1176 reg = urtwn_efuse_read_1(sc, addr); 1177 if (reg == 0xff) 1178 break; 1179 addr++; 1180 off = reg >> 4; 1181 msk = reg & 0xf; 1182 for (i = 0; i < 4; i++) { 1183 if (msk & (1 << i)) 1184 continue; 1185 rom[off * 8 + i * 2 + 0] = 1186 urtwn_efuse_read_1(sc, addr); 1187 addr++; 1188 rom[off * 8 + i * 2 + 1] = 1189 urtwn_efuse_read_1(sc, addr); 1190 addr++; 1191 } 1192 } 1193#ifdef URTWN_DEBUG 1194 if (urtwn_debug >= 2) { 1195 /* Dump ROM content. */ 1196 printf("\n"); 1197 for (i = 0; i < sizeof(sc->rom); i++) 1198 printf("%02x:", rom[i]); 1199 printf("\n"); 1200 } 1201#endif 1202 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1203} 1204 1205static void 1206urtwn_efuse_switch_power(struct urtwn_softc *sc) 1207{ 1208 uint32_t reg; 1209 1210 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1211 1212 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1213 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1214 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1215 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1216 } 1217 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1218 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1219 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1220 reg | R92C_SYS_FUNC_EN_ELDR); 1221 } 1222 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1223 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1224 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1225 urtwn_write_2(sc, R92C_SYS_CLKR, 1226 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1227 } 1228} 1229 1230static int 1231urtwn_read_chipid(struct urtwn_softc *sc) 1232{ 1233 uint32_t reg; 1234 1235 if (sc->chip & URTWN_CHIP_88E) 1236 return (0); 1237 1238 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1239 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1240 return (EIO); 1241 1242 if (reg & R92C_SYS_CFG_TYPE_92C) { 1243 sc->chip |= URTWN_CHIP_92C; 1244 /* Check if it is a castrated 8192C. */ 1245 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1246 R92C_HPON_FSM_CHIP_BONDING_ID) == 1247 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1248 sc->chip |= URTWN_CHIP_92C_1T2R; 1249 } 1250 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1251 sc->chip |= URTWN_CHIP_UMC; 1252 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1253 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1254 } 1255 return (0); 1256} 1257 1258static void 1259urtwn_read_rom(struct urtwn_softc *sc) 1260{ 1261 struct r92c_rom *rom = &sc->rom; 1262 1263 /* Read full ROM image. */ 1264 urtwn_efuse_read(sc); 1265 1266 /* XXX Weird but this is what the vendor driver does. */ 1267 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1268 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1269 1270 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1271 1272 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1273 DPRINTF("regulatory type=%d\n", sc->regulatory); 1274 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1275 1276 sc->sc_rf_write = urtwn_r92c_rf_write; 1277 sc->sc_power_on = urtwn_r92c_power_on; 1278 sc->sc_dma_init = urtwn_r92c_dma_init; 1279} 1280 1281static void 1282urtwn_r88e_read_rom(struct urtwn_softc *sc) 1283{ 1284 uint8_t *rom = sc->r88e_rom; 1285 uint16_t addr = 0; 1286 uint32_t reg; 1287 uint8_t off, msk, tmp; 1288 int i; 1289 1290 off = 0; 1291 urtwn_efuse_switch_power(sc); 1292 1293 /* Read full ROM image. */ 1294 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1295 while (addr < 512) { 1296 reg = urtwn_efuse_read_1(sc, addr); 1297 if (reg == 0xff) 1298 break; 1299 addr++; 1300 if ((reg & 0x1f) == 0x0f) { 1301 tmp = (reg & 0xe0) >> 5; 1302 reg = urtwn_efuse_read_1(sc, addr); 1303 if ((reg & 0x0f) != 0x0f) 1304 off = ((reg & 0xf0) >> 1) | tmp; 1305 addr++; 1306 } else 1307 off = reg >> 4; 1308 msk = reg & 0xf; 1309 for (i = 0; i < 4; i++) { 1310 if (msk & (1 << i)) 1311 continue; 1312 rom[off * 8 + i * 2 + 0] = 1313 urtwn_efuse_read_1(sc, addr); 1314 addr++; 1315 rom[off * 8 + i * 2 + 1] = 1316 urtwn_efuse_read_1(sc, addr); 1317 addr++; 1318 } 1319 } 1320 1321 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1322 1323 addr = 0x10; 1324 for (i = 0; i < 6; i++) 1325 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1326 for (i = 0; i < 5; i++) 1327 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1328 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1329 if (sc->bw20_tx_pwr_diff & 0x08) 1330 sc->bw20_tx_pwr_diff |= 0xf0; 1331 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1332 if (sc->ofdm_tx_pwr_diff & 0x08) 1333 sc->ofdm_tx_pwr_diff |= 0xf0; 1334 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1335 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &sc->r88e_rom[0xd7]); 1336 1337 sc->sc_rf_write = urtwn_r88e_rf_write; 1338 sc->sc_power_on = urtwn_r88e_power_on; 1339 sc->sc_dma_init = urtwn_r88e_dma_init; 1340} 1341 1342/* 1343 * Initialize rate adaptation in firmware. 1344 */ 1345static int 1346urtwn_ra_init(struct urtwn_softc *sc) 1347{ 1348 static const uint8_t map[] = 1349 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1350 struct ieee80211com *ic = &sc->sc_ic; 1351 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1352 struct ieee80211_node *ni; 1353 struct ieee80211_rateset *rs; 1354 struct r92c_fw_cmd_macid_cfg cmd; 1355 uint32_t rates, basicrates; 1356 uint8_t mode; 1357 int maxrate, maxbasicrate, error, i, j; 1358 1359 ni = ieee80211_ref_node(vap->iv_bss); 1360 rs = &ni->ni_rates; 1361 1362 /* Get normal and basic rates mask. */ 1363 rates = basicrates = 0; 1364 maxrate = maxbasicrate = 0; 1365 for (i = 0; i < rs->rs_nrates; i++) { 1366 /* Convert 802.11 rate to HW rate index. */ 1367 for (j = 0; j < nitems(map); j++) 1368 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1369 break; 1370 if (j == nitems(map)) /* Unknown rate, skip. */ 1371 continue; 1372 rates |= 1 << j; 1373 if (j > maxrate) 1374 maxrate = j; 1375 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1376 basicrates |= 1 << j; 1377 if (j > maxbasicrate) 1378 maxbasicrate = j; 1379 } 1380 } 1381 if (ic->ic_curmode == IEEE80211_MODE_11B) 1382 mode = R92C_RAID_11B; 1383 else 1384 mode = R92C_RAID_11BG; 1385 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1386 mode, rates, basicrates); 1387 1388 /* Set rates mask for group addressed frames. */ 1389 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1390 cmd.mask = htole32(mode << 28 | basicrates); 1391 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1392 if (error != 0) { 1393 ieee80211_free_node(ni); 1394 device_printf(sc->sc_dev, 1395 "could not add broadcast station\n"); 1396 return (error); 1397 } 1398 /* Set initial MRR rate. */ 1399 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1400 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1401 maxbasicrate); 1402 1403 /* Set rates mask for unicast frames. */ 1404 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1405 cmd.mask = htole32(mode << 28 | rates); 1406 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1407 if (error != 0) { 1408 ieee80211_free_node(ni); 1409 device_printf(sc->sc_dev, "could not add BSS station\n"); 1410 return (error); 1411 } 1412 /* Set initial MRR rate. */ 1413 DPRINTF("maxrate=%d\n", maxrate); 1414 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1415 maxrate); 1416 1417 /* Indicate highest supported rate. */ 1418 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1419 ieee80211_free_node(ni); 1420 1421 return (0); 1422} 1423 1424void 1425urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1426{ 1427 struct ieee80211com *ic = &sc->sc_ic; 1428 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1429 struct ieee80211_node *ni = vap->iv_bss; 1430 1431 uint64_t tsf; 1432 1433 /* Enable TSF synchronization. */ 1434 urtwn_write_1(sc, R92C_BCN_CTRL, 1435 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1436 1437 urtwn_write_1(sc, R92C_BCN_CTRL, 1438 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1439 1440 /* Set initial TSF. */ 1441 memcpy(&tsf, ni->ni_tstamp.data, 8); 1442 tsf = le64toh(tsf); 1443 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1444 tsf -= IEEE80211_DUR_TU; 1445 urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1446 urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1447 1448 urtwn_write_1(sc, R92C_BCN_CTRL, 1449 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1450} 1451 1452static void 1453urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1454{ 1455 uint8_t reg; 1456 1457 if (led == URTWN_LED_LINK) { 1458 if (sc->chip & URTWN_CHIP_88E) { 1459 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1460 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1461 if (!on) { 1462 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1463 urtwn_write_1(sc, R92C_LEDCFG2, 1464 reg | R92C_LEDCFG0_DIS); 1465 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1466 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1467 0xfe); 1468 } 1469 } else { 1470 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1471 if (!on) 1472 reg |= R92C_LEDCFG0_DIS; 1473 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1474 } 1475 sc->ledlink = on; /* Save LED state. */ 1476 } 1477} 1478 1479static int 1480urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1481{ 1482 struct urtwn_vap *uvp = URTWN_VAP(vap); 1483 struct ieee80211com *ic = vap->iv_ic; 1484 struct urtwn_softc *sc = ic->ic_softc; 1485 struct ieee80211_node *ni; 1486 enum ieee80211_state ostate; 1487 uint32_t reg; 1488 1489 ostate = vap->iv_state; 1490 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1491 ieee80211_state_name[nstate]); 1492 1493 IEEE80211_UNLOCK(ic); 1494 URTWN_LOCK(sc); 1495 callout_stop(&sc->sc_watchdog_ch); 1496 1497 if (ostate == IEEE80211_S_RUN) { 1498 /* Turn link LED off. */ 1499 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1500 1501 /* Set media status to 'No Link'. */ 1502 reg = urtwn_read_4(sc, R92C_CR); 1503 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1504 urtwn_write_4(sc, R92C_CR, reg); 1505 1506 /* Stop Rx of data frames. */ 1507 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1508 1509 /* Rest TSF. */ 1510 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1511 1512 /* Disable TSF synchronization. */ 1513 urtwn_write_1(sc, R92C_BCN_CTRL, 1514 urtwn_read_1(sc, R92C_BCN_CTRL) | 1515 R92C_BCN_CTRL_DIS_TSF_UDT0); 1516 1517 /* Reset EDCA parameters. */ 1518 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1519 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1520 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1521 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1522 } 1523 1524 switch (nstate) { 1525 case IEEE80211_S_INIT: 1526 /* Turn link LED off. */ 1527 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1528 break; 1529 case IEEE80211_S_SCAN: 1530 if (ostate != IEEE80211_S_SCAN) { 1531 /* Allow Rx from any BSSID. */ 1532 urtwn_write_4(sc, R92C_RCR, 1533 urtwn_read_4(sc, R92C_RCR) & 1534 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1535 1536 /* Set gain for scanning. */ 1537 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1538 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1539 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1540 1541 if (!(sc->chip & URTWN_CHIP_88E)) { 1542 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1543 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1544 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1545 } 1546 } 1547 /* Pause AC Tx queues. */ 1548 urtwn_write_1(sc, R92C_TXPAUSE, 1549 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1550 break; 1551 case IEEE80211_S_AUTH: 1552 /* Set initial gain under link. */ 1553 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1554 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1555 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1556 1557 if (!(sc->chip & URTWN_CHIP_88E)) { 1558 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1559 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1560 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1561 } 1562 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1563 break; 1564 case IEEE80211_S_RUN: 1565 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1566 /* Enable Rx of data frames. */ 1567 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1568 1569 /* Turn link LED on. */ 1570 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1571 break; 1572 } 1573 1574 ni = ieee80211_ref_node(vap->iv_bss); 1575 /* Set media status to 'Associated'. */ 1576 reg = urtwn_read_4(sc, R92C_CR); 1577 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1578 urtwn_write_4(sc, R92C_CR, reg); 1579 1580 /* Set BSSID. */ 1581 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1582 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1583 1584 if (ic->ic_curmode == IEEE80211_MODE_11B) 1585 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1586 else /* 802.11b/g */ 1587 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1588 1589 /* Enable Rx of data frames. */ 1590 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1591 1592 /* Flush all AC queues. */ 1593 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1594 1595 /* Set beacon interval. */ 1596 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1597 1598 /* Allow Rx from our BSSID only. */ 1599 urtwn_write_4(sc, R92C_RCR, 1600 urtwn_read_4(sc, R92C_RCR) | 1601 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1602 1603 /* Enable TSF synchronization. */ 1604 urtwn_tsf_sync_enable(sc); 1605 1606 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1607 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1608 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1609 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1610 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1611 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1612 1613 /* Intialize rate adaptation. */ 1614 if (sc->chip & URTWN_CHIP_88E) 1615 ni->ni_txrate = 1616 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1617 else 1618 urtwn_ra_init(sc); 1619 /* Turn link LED on. */ 1620 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1621 1622 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1623 /* Reset temperature calibration state machine. */ 1624 sc->thcal_state = 0; 1625 sc->thcal_lctemp = 0; 1626 ieee80211_free_node(ni); 1627 break; 1628 default: 1629 break; 1630 } 1631 URTWN_UNLOCK(sc); 1632 IEEE80211_LOCK(ic); 1633 return(uvp->newstate(vap, nstate, arg)); 1634} 1635 1636static void 1637urtwn_watchdog(void *arg) 1638{ 1639 struct urtwn_softc *sc = arg; 1640 1641 if (sc->sc_txtimer > 0) { 1642 if (--sc->sc_txtimer == 0) { 1643 device_printf(sc->sc_dev, "device timeout\n"); 1644 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1645 return; 1646 } 1647 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1648 } 1649} 1650 1651static void 1652urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1653{ 1654 int pwdb; 1655 1656 /* Convert antenna signal to percentage. */ 1657 if (rssi <= -100 || rssi >= 20) 1658 pwdb = 0; 1659 else if (rssi >= 0) 1660 pwdb = 100; 1661 else 1662 pwdb = 100 + rssi; 1663 if (!(sc->chip & URTWN_CHIP_88E)) { 1664 if (rate <= 3) { 1665 /* CCK gain is smaller than OFDM/MCS gain. */ 1666 pwdb += 6; 1667 if (pwdb > 100) 1668 pwdb = 100; 1669 if (pwdb <= 14) 1670 pwdb -= 4; 1671 else if (pwdb <= 26) 1672 pwdb -= 8; 1673 else if (pwdb <= 34) 1674 pwdb -= 6; 1675 else if (pwdb <= 42) 1676 pwdb -= 2; 1677 } 1678 } 1679 if (sc->avg_pwdb == -1) /* Init. */ 1680 sc->avg_pwdb = pwdb; 1681 else if (sc->avg_pwdb < pwdb) 1682 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1683 else 1684 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1685 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1686} 1687 1688static int8_t 1689urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1690{ 1691 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1692 struct r92c_rx_phystat *phy; 1693 struct r92c_rx_cck *cck; 1694 uint8_t rpt; 1695 int8_t rssi; 1696 1697 if (rate <= 3) { 1698 cck = (struct r92c_rx_cck *)physt; 1699 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1700 rpt = (cck->agc_rpt >> 5) & 0x3; 1701 rssi = (cck->agc_rpt & 0x1f) << 1; 1702 } else { 1703 rpt = (cck->agc_rpt >> 6) & 0x3; 1704 rssi = cck->agc_rpt & 0x3e; 1705 } 1706 rssi = cckoff[rpt] - rssi; 1707 } else { /* OFDM/HT. */ 1708 phy = (struct r92c_rx_phystat *)physt; 1709 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1710 } 1711 return (rssi); 1712} 1713 1714static int8_t 1715urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1716{ 1717 struct r92c_rx_phystat *phy; 1718 struct r88e_rx_cck *cck; 1719 uint8_t cck_agc_rpt, lna_idx, vga_idx; 1720 int8_t rssi; 1721 1722 rssi = 0; 1723 if (rate <= 3) { 1724 cck = (struct r88e_rx_cck *)physt; 1725 cck_agc_rpt = cck->agc_rpt; 1726 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1727 vga_idx = cck_agc_rpt & 0x1f; 1728 switch (lna_idx) { 1729 case 7: 1730 if (vga_idx <= 27) 1731 rssi = -100 + 2* (27 - vga_idx); 1732 else 1733 rssi = -100; 1734 break; 1735 case 6: 1736 rssi = -48 + 2 * (2 - vga_idx); 1737 break; 1738 case 5: 1739 rssi = -42 + 2 * (7 - vga_idx); 1740 break; 1741 case 4: 1742 rssi = -36 + 2 * (7 - vga_idx); 1743 break; 1744 case 3: 1745 rssi = -24 + 2 * (7 - vga_idx); 1746 break; 1747 case 2: 1748 rssi = -12 + 2 * (5 - vga_idx); 1749 break; 1750 case 1: 1751 rssi = 8 - (2 * vga_idx); 1752 break; 1753 case 0: 1754 rssi = 14 - (2 * vga_idx); 1755 break; 1756 } 1757 rssi += 6; 1758 } else { /* OFDM/HT. */ 1759 phy = (struct r92c_rx_phystat *)physt; 1760 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1761 } 1762 return (rssi); 1763} 1764 1765 1766static int 1767urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1768 struct mbuf *m0, struct urtwn_data *data) 1769{ 1770 struct ieee80211_frame *wh; 1771 struct ieee80211_key *k; 1772 struct ieee80211com *ic = &sc->sc_ic; 1773 struct ieee80211vap *vap = ni->ni_vap; 1774 struct usb_xfer *xfer; 1775 struct r92c_tx_desc *txd; 1776 uint8_t raid, type; 1777 uint16_t sum; 1778 int i, xferlen; 1779 struct usb_xfer *urtwn_pipes[4] = { 1780 sc->sc_xfer[URTWN_BULK_TX_BE], 1781 sc->sc_xfer[URTWN_BULK_TX_BK], 1782 sc->sc_xfer[URTWN_BULK_TX_VI], 1783 sc->sc_xfer[URTWN_BULK_TX_VO] 1784 }; 1785 1786 URTWN_ASSERT_LOCKED(sc); 1787 1788 /* 1789 * Software crypto. 1790 */ 1791 wh = mtod(m0, struct ieee80211_frame *); 1792 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1793 1794 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1795 k = ieee80211_crypto_encap(ni, m0); 1796 if (k == NULL) { 1797 device_printf(sc->sc_dev, 1798 "ieee80211_crypto_encap returns NULL.\n"); 1799 /* XXX we don't expect the fragmented frames */ 1800 return (ENOBUFS); 1801 } 1802 1803 /* in case packet header moved, reset pointer */ 1804 wh = mtod(m0, struct ieee80211_frame *); 1805 } 1806 1807 switch (type) { 1808 case IEEE80211_FC0_TYPE_CTL: 1809 case IEEE80211_FC0_TYPE_MGT: 1810 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1811 break; 1812 default: 1813 KASSERT(M_WME_GETAC(m0) < 4, 1814 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1815 xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1816 break; 1817 } 1818 1819 /* Fill Tx descriptor. */ 1820 txd = (struct r92c_tx_desc *)data->buf; 1821 memset(txd, 0, sizeof(*txd)); 1822 1823 txd->txdw0 |= htole32( 1824 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1825 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1826 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1827 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1828 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1829 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1830 type == IEEE80211_FC0_TYPE_DATA) { 1831 if (ic->ic_curmode == IEEE80211_MODE_11B) 1832 raid = R92C_RAID_11B; 1833 else 1834 raid = R92C_RAID_11BG; 1835 if (sc->chip & URTWN_CHIP_88E) { 1836 txd->txdw1 |= htole32( 1837 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1838 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1839 SM(R92C_TXDW1_RAID, raid)); 1840 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1841 } else { 1842 txd->txdw1 |= htole32( 1843 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1844 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1845 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1846 } 1847 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1848 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1849 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1850 R92C_TXDW4_HWRTSEN); 1851 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1852 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1853 R92C_TXDW4_HWRTSEN); 1854 } 1855 } 1856 /* Send RTS at OFDM24. */ 1857 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1858 txd->txdw5 |= htole32(0x0001ff00); 1859 /* Send data at OFDM54. */ 1860 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1861 } else { 1862 txd->txdw1 |= htole32( 1863 SM(R92C_TXDW1_MACID, 0) | 1864 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1865 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1866 1867 /* Force CCK1. */ 1868 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1869 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1870 } 1871 /* Set sequence number (already little endian). */ 1872 txd->txdseq |= *(uint16_t *)wh->i_seq; 1873 1874 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 1875 /* Use HW sequence numbering for non-QoS frames. */ 1876 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1877 txd->txdseq |= htole16(0x8000); 1878 } else 1879 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1880 1881 /* Compute Tx descriptor checksum. */ 1882 sum = 0; 1883 for (i = 0; i < sizeof(*txd) / 2; i++) 1884 sum ^= ((uint16_t *)txd)[i]; 1885 txd->txdsum = sum; /* NB: already little endian. */ 1886 1887 if (ieee80211_radiotap_active_vap(vap)) { 1888 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1889 1890 tap->wt_flags = 0; 1891 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1892 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1893 ieee80211_radiotap_tx(vap, m0); 1894 } 1895 1896 xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1897 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1898 1899 data->buflen = xferlen; 1900 data->ni = ni; 1901 data->m = m0; 1902 1903 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1904 usbd_transfer_start(xfer); 1905 return (0); 1906} 1907 1908static int 1909urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1910{ 1911 struct urtwn_softc *sc = ic->ic_softc; 1912 int error; 1913 1914 URTWN_LOCK(sc); 1915 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1916 URTWN_UNLOCK(sc); 1917 return (ENXIO); 1918 } 1919 error = mbufq_enqueue(&sc->sc_snd, m); 1920 if (error) { 1921 URTWN_UNLOCK(sc); 1922 return (error); 1923 } 1924 urtwn_start(sc); 1925 URTWN_UNLOCK(sc); 1926 1927 return (0); 1928} 1929 1930static void 1931urtwn_start(struct urtwn_softc *sc) 1932{ 1933 struct ieee80211_node *ni; 1934 struct mbuf *m; 1935 struct urtwn_data *bf; 1936 1937 URTWN_ASSERT_LOCKED(sc); 1938 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1939 bf = urtwn_getbuf(sc); 1940 if (bf == NULL) { 1941 mbufq_prepend(&sc->sc_snd, m); 1942 break; 1943 } 1944 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1945 m->m_pkthdr.rcvif = NULL; 1946 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 1947 if_inc_counter(ni->ni_vap->iv_ifp, 1948 IFCOUNTER_OERRORS, 1); 1949 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1950 m_freem(m); 1951 ieee80211_free_node(ni); 1952 break; 1953 } 1954 sc->sc_txtimer = 5; 1955 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1956 } 1957} 1958 1959static void 1960urtwn_parent(struct ieee80211com *ic) 1961{ 1962 struct urtwn_softc *sc = ic->ic_softc; 1963 int startall = 0; 1964 1965 URTWN_LOCK(sc); 1966 if (sc->sc_flags & URTWN_DETACHED) { 1967 URTWN_UNLOCK(sc); 1968 return; 1969 } 1970 if (ic->ic_nrunning > 0) { 1971 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1972 urtwn_init(sc); 1973 startall = 1; 1974 } 1975 } else if (sc->sc_flags & URTWN_RUNNING) 1976 urtwn_stop(sc); 1977 URTWN_UNLOCK(sc); 1978 1979 if (startall) 1980 ieee80211_start_all(ic); 1981} 1982 1983static int 1984urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1985 int ndata, int maxsz) 1986{ 1987 int i, error; 1988 1989 for (i = 0; i < ndata; i++) { 1990 struct urtwn_data *dp = &data[i]; 1991 dp->sc = sc; 1992 dp->m = NULL; 1993 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1994 if (dp->buf == NULL) { 1995 device_printf(sc->sc_dev, 1996 "could not allocate buffer\n"); 1997 error = ENOMEM; 1998 goto fail; 1999 } 2000 dp->ni = NULL; 2001 } 2002 2003 return (0); 2004fail: 2005 urtwn_free_list(sc, data, ndata); 2006 return (error); 2007} 2008 2009static int 2010urtwn_alloc_rx_list(struct urtwn_softc *sc) 2011{ 2012 int error, i; 2013 2014 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 2015 URTWN_RXBUFSZ); 2016 if (error != 0) 2017 return (error); 2018 2019 STAILQ_INIT(&sc->sc_rx_active); 2020 STAILQ_INIT(&sc->sc_rx_inactive); 2021 2022 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 2023 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 2024 2025 return (0); 2026} 2027 2028static int 2029urtwn_alloc_tx_list(struct urtwn_softc *sc) 2030{ 2031 int error, i; 2032 2033 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 2034 URTWN_TXBUFSZ); 2035 if (error != 0) 2036 return (error); 2037 2038 STAILQ_INIT(&sc->sc_tx_active); 2039 STAILQ_INIT(&sc->sc_tx_inactive); 2040 STAILQ_INIT(&sc->sc_tx_pending); 2041 2042 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 2043 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 2044 2045 return (0); 2046} 2047 2048static __inline int 2049urtwn_power_on(struct urtwn_softc *sc) 2050{ 2051 2052 return sc->sc_power_on(sc); 2053} 2054 2055static int 2056urtwn_r92c_power_on(struct urtwn_softc *sc) 2057{ 2058 uint32_t reg; 2059 int ntries; 2060 2061 /* Wait for autoload done bit. */ 2062 for (ntries = 0; ntries < 1000; ntries++) { 2063 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2064 break; 2065 urtwn_ms_delay(sc); 2066 } 2067 if (ntries == 1000) { 2068 device_printf(sc->sc_dev, 2069 "timeout waiting for chip autoload\n"); 2070 return (ETIMEDOUT); 2071 } 2072 2073 /* Unlock ISO/CLK/Power control register. */ 2074 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2075 /* Move SPS into PWM mode. */ 2076 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2077 urtwn_ms_delay(sc); 2078 2079 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2080 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2081 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2082 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2083 urtwn_ms_delay(sc); 2084 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2085 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2086 ~R92C_SYS_ISO_CTRL_MD2PP); 2087 } 2088 2089 /* Auto enable WLAN. */ 2090 urtwn_write_2(sc, R92C_APS_FSMCO, 2091 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2092 for (ntries = 0; ntries < 1000; ntries++) { 2093 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2094 R92C_APS_FSMCO_APFM_ONMAC)) 2095 break; 2096 urtwn_ms_delay(sc); 2097 } 2098 if (ntries == 1000) { 2099 device_printf(sc->sc_dev, 2100 "timeout waiting for MAC auto ON\n"); 2101 return (ETIMEDOUT); 2102 } 2103 2104 /* Enable radio, GPIO and LED functions. */ 2105 urtwn_write_2(sc, R92C_APS_FSMCO, 2106 R92C_APS_FSMCO_AFSM_HSUS | 2107 R92C_APS_FSMCO_PDN_EN | 2108 R92C_APS_FSMCO_PFM_ALDN); 2109 /* Release RF digital isolation. */ 2110 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2111 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2112 2113 /* Initialize MAC. */ 2114 urtwn_write_1(sc, R92C_APSD_CTRL, 2115 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2116 for (ntries = 0; ntries < 200; ntries++) { 2117 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2118 R92C_APSD_CTRL_OFF_STATUS)) 2119 break; 2120 urtwn_ms_delay(sc); 2121 } 2122 if (ntries == 200) { 2123 device_printf(sc->sc_dev, 2124 "timeout waiting for MAC initialization\n"); 2125 return (ETIMEDOUT); 2126 } 2127 2128 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2129 reg = urtwn_read_2(sc, R92C_CR); 2130 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2131 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2132 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2133 R92C_CR_ENSEC; 2134 urtwn_write_2(sc, R92C_CR, reg); 2135 2136 urtwn_write_1(sc, 0xfe10, 0x19); 2137 return (0); 2138} 2139 2140static int 2141urtwn_r88e_power_on(struct urtwn_softc *sc) 2142{ 2143 uint32_t reg; 2144 int ntries; 2145 2146 /* Wait for power ready bit. */ 2147 for (ntries = 0; ntries < 5000; ntries++) { 2148 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2149 break; 2150 urtwn_ms_delay(sc); 2151 } 2152 if (ntries == 5000) { 2153 device_printf(sc->sc_dev, 2154 "timeout waiting for chip power up\n"); 2155 return (ETIMEDOUT); 2156 } 2157 2158 /* Reset BB. */ 2159 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2160 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2161 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2162 2163 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2164 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2165 2166 /* Disable HWPDN. */ 2167 urtwn_write_2(sc, R92C_APS_FSMCO, 2168 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2169 2170 /* Disable WL suspend. */ 2171 urtwn_write_2(sc, R92C_APS_FSMCO, 2172 urtwn_read_2(sc, R92C_APS_FSMCO) & 2173 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2174 2175 urtwn_write_2(sc, R92C_APS_FSMCO, 2176 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2177 for (ntries = 0; ntries < 5000; ntries++) { 2178 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2179 R92C_APS_FSMCO_APFM_ONMAC)) 2180 break; 2181 urtwn_ms_delay(sc); 2182 } 2183 if (ntries == 5000) 2184 return (ETIMEDOUT); 2185 2186 /* Enable LDO normal mode. */ 2187 urtwn_write_1(sc, R92C_LPLDO_CTRL, 2188 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2189 2190 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2191 urtwn_write_2(sc, R92C_CR, 0); 2192 reg = urtwn_read_2(sc, R92C_CR); 2193 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2194 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2195 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2196 urtwn_write_2(sc, R92C_CR, reg); 2197 2198 return (0); 2199} 2200 2201static int 2202urtwn_llt_init(struct urtwn_softc *sc) 2203{ 2204 int i, error, page_count, pktbuf_count; 2205 2206 page_count = (sc->chip & URTWN_CHIP_88E) ? 2207 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2208 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2209 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2210 2211 /* Reserve pages [0; page_count]. */ 2212 for (i = 0; i < page_count; i++) { 2213 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2214 return (error); 2215 } 2216 /* NB: 0xff indicates end-of-list. */ 2217 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2218 return (error); 2219 /* 2220 * Use pages [page_count + 1; pktbuf_count - 1] 2221 * as ring buffer. 2222 */ 2223 for (++i; i < pktbuf_count - 1; i++) { 2224 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2225 return (error); 2226 } 2227 /* Make the last page point to the beginning of the ring buffer. */ 2228 error = urtwn_llt_write(sc, i, page_count + 1); 2229 return (error); 2230} 2231 2232static void 2233urtwn_fw_reset(struct urtwn_softc *sc) 2234{ 2235 uint16_t reg; 2236 int ntries; 2237 2238 /* Tell 8051 to reset itself. */ 2239 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2240 2241 /* Wait until 8051 resets by itself. */ 2242 for (ntries = 0; ntries < 100; ntries++) { 2243 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2244 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2245 return; 2246 urtwn_ms_delay(sc); 2247 } 2248 /* Force 8051 reset. */ 2249 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2250} 2251 2252static void 2253urtwn_r88e_fw_reset(struct urtwn_softc *sc) 2254{ 2255 uint16_t reg; 2256 2257 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2258 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2259 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2260} 2261 2262static int 2263urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2264{ 2265 uint32_t reg; 2266 int off, mlen, error = 0; 2267 2268 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2269 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2270 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2271 2272 off = R92C_FW_START_ADDR; 2273 while (len > 0) { 2274 if (len > 196) 2275 mlen = 196; 2276 else if (len > 4) 2277 mlen = 4; 2278 else 2279 mlen = 1; 2280 /* XXX fix this deconst */ 2281 error = urtwn_write_region_1(sc, off, 2282 __DECONST(uint8_t *, buf), mlen); 2283 if (error != 0) 2284 break; 2285 off += mlen; 2286 buf += mlen; 2287 len -= mlen; 2288 } 2289 return (error); 2290} 2291 2292static int 2293urtwn_load_firmware(struct urtwn_softc *sc) 2294{ 2295 const struct firmware *fw; 2296 const struct r92c_fw_hdr *hdr; 2297 const char *imagename; 2298 const u_char *ptr; 2299 size_t len; 2300 uint32_t reg; 2301 int mlen, ntries, page, error; 2302 2303 URTWN_UNLOCK(sc); 2304 /* Read firmware image from the filesystem. */ 2305 if (sc->chip & URTWN_CHIP_88E) 2306 imagename = "urtwn-rtl8188eufw"; 2307 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2308 URTWN_CHIP_UMC_A_CUT) 2309 imagename = "urtwn-rtl8192cfwU"; 2310 else 2311 imagename = "urtwn-rtl8192cfwT"; 2312 2313 fw = firmware_get(imagename); 2314 URTWN_LOCK(sc); 2315 if (fw == NULL) { 2316 device_printf(sc->sc_dev, 2317 "failed loadfirmware of file %s\n", imagename); 2318 return (ENOENT); 2319 } 2320 2321 len = fw->datasize; 2322 2323 if (len < sizeof(*hdr)) { 2324 device_printf(sc->sc_dev, "firmware too short\n"); 2325 error = EINVAL; 2326 goto fail; 2327 } 2328 ptr = fw->data; 2329 hdr = (const struct r92c_fw_hdr *)ptr; 2330 /* Check if there is a valid FW header and skip it. */ 2331 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2332 (le16toh(hdr->signature) >> 4) == 0x88e || 2333 (le16toh(hdr->signature) >> 4) == 0x92c) { 2334 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2335 le16toh(hdr->version), le16toh(hdr->subversion), 2336 hdr->month, hdr->date, hdr->hour, hdr->minute); 2337 ptr += sizeof(*hdr); 2338 len -= sizeof(*hdr); 2339 } 2340 2341 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2342 if (sc->chip & URTWN_CHIP_88E) 2343 urtwn_r88e_fw_reset(sc); 2344 else 2345 urtwn_fw_reset(sc); 2346 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2347 } 2348 2349 if (!(sc->chip & URTWN_CHIP_88E)) { 2350 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2351 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2352 R92C_SYS_FUNC_EN_CPUEN); 2353 } 2354 urtwn_write_1(sc, R92C_MCUFWDL, 2355 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2356 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2357 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2358 2359 /* Reset the FWDL checksum. */ 2360 urtwn_write_1(sc, R92C_MCUFWDL, 2361 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2362 2363 for (page = 0; len > 0; page++) { 2364 mlen = min(len, R92C_FW_PAGE_SIZE); 2365 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2366 if (error != 0) { 2367 device_printf(sc->sc_dev, 2368 "could not load firmware page\n"); 2369 goto fail; 2370 } 2371 ptr += mlen; 2372 len -= mlen; 2373 } 2374 urtwn_write_1(sc, R92C_MCUFWDL, 2375 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2376 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2377 2378 /* Wait for checksum report. */ 2379 for (ntries = 0; ntries < 1000; ntries++) { 2380 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2381 break; 2382 urtwn_ms_delay(sc); 2383 } 2384 if (ntries == 1000) { 2385 device_printf(sc->sc_dev, 2386 "timeout waiting for checksum report\n"); 2387 error = ETIMEDOUT; 2388 goto fail; 2389 } 2390 2391 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2392 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2393 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2394 if (sc->chip & URTWN_CHIP_88E) 2395 urtwn_r88e_fw_reset(sc); 2396 /* Wait for firmware readiness. */ 2397 for (ntries = 0; ntries < 1000; ntries++) { 2398 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2399 break; 2400 urtwn_ms_delay(sc); 2401 } 2402 if (ntries == 1000) { 2403 device_printf(sc->sc_dev, 2404 "timeout waiting for firmware readiness\n"); 2405 error = ETIMEDOUT; 2406 goto fail; 2407 } 2408fail: 2409 firmware_put(fw, FIRMWARE_UNLOAD); 2410 return (error); 2411} 2412 2413static __inline int 2414urtwn_dma_init(struct urtwn_softc *sc) 2415{ 2416 2417 return sc->sc_dma_init(sc); 2418} 2419 2420static int 2421urtwn_r92c_dma_init(struct urtwn_softc *sc) 2422{ 2423 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2424 uint32_t reg; 2425 int error; 2426 2427 /* Initialize LLT table. */ 2428 error = urtwn_llt_init(sc); 2429 if (error != 0) 2430 return (error); 2431 2432 /* Get Tx queues to USB endpoints mapping. */ 2433 hashq = hasnq = haslq = 0; 2434 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2435 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2436 if (MS(reg, R92C_USB_EP_HQ) != 0) 2437 hashq = 1; 2438 if (MS(reg, R92C_USB_EP_NQ) != 0) 2439 hasnq = 1; 2440 if (MS(reg, R92C_USB_EP_LQ) != 0) 2441 haslq = 1; 2442 nqueues = hashq + hasnq + haslq; 2443 if (nqueues == 0) 2444 return (EIO); 2445 /* Get the number of pages for each queue. */ 2446 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2447 /* The remaining pages are assigned to the high priority queue. */ 2448 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2449 2450 /* Set number of pages for normal priority queue. */ 2451 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2452 urtwn_write_4(sc, R92C_RQPN, 2453 /* Set number of pages for public queue. */ 2454 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2455 /* Set number of pages for high priority queue. */ 2456 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2457 /* Set number of pages for low priority queue. */ 2458 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2459 /* Load values. */ 2460 R92C_RQPN_LD); 2461 2462 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2463 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2464 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2465 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2466 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2467 2468 /* Set queue to USB pipe mapping. */ 2469 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2470 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2471 if (nqueues == 1) { 2472 if (hashq) 2473 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2474 else if (hasnq) 2475 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2476 else 2477 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2478 } else if (nqueues == 2) { 2479 /* All 2-endpoints configs have a high priority queue. */ 2480 if (!hashq) 2481 return (EIO); 2482 if (hasnq) 2483 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2484 else 2485 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2486 } else 2487 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2488 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2489 2490 /* Set Tx/Rx transfer page boundary. */ 2491 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2492 2493 /* Set Tx/Rx transfer page size. */ 2494 urtwn_write_1(sc, R92C_PBP, 2495 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2496 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2497 return (0); 2498} 2499 2500static int 2501urtwn_r88e_dma_init(struct urtwn_softc *sc) 2502{ 2503 struct usb_interface *iface; 2504 uint32_t reg; 2505 int nqueues; 2506 int error; 2507 2508 /* Initialize LLT table. */ 2509 error = urtwn_llt_init(sc); 2510 if (error != 0) 2511 return (error); 2512 2513 /* Get Tx queues to USB endpoints mapping. */ 2514 iface = usbd_get_iface(sc->sc_udev, 0); 2515 nqueues = iface->idesc->bNumEndpoints - 1; 2516 if (nqueues == 0) 2517 return (EIO); 2518 2519 /* Set number of pages for normal priority queue. */ 2520 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2521 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2522 2523 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2524 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2525 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2526 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2527 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2528 2529 /* Set queue to USB pipe mapping. */ 2530 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2531 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2532 if (nqueues == 1) 2533 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2534 else if (nqueues == 2) 2535 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2536 else 2537 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2538 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2539 2540 /* Set Tx/Rx transfer page boundary. */ 2541 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2542 2543 /* Set Tx/Rx transfer page size. */ 2544 urtwn_write_1(sc, R92C_PBP, 2545 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2546 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2547 2548 return (0); 2549} 2550 2551static void 2552urtwn_mac_init(struct urtwn_softc *sc) 2553{ 2554 int i; 2555 2556 /* Write MAC initialization values. */ 2557 if (sc->chip & URTWN_CHIP_88E) { 2558 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2559 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2560 rtl8188eu_mac[i].val); 2561 } 2562 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2563 } else { 2564 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2565 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2566 rtl8192cu_mac[i].val); 2567 } 2568} 2569 2570static void 2571urtwn_bb_init(struct urtwn_softc *sc) 2572{ 2573 const struct urtwn_bb_prog *prog; 2574 uint32_t reg; 2575 uint8_t crystalcap; 2576 int i; 2577 2578 /* Enable BB and RF. */ 2579 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2580 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2581 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2582 R92C_SYS_FUNC_EN_DIO_RF); 2583 2584 if (!(sc->chip & URTWN_CHIP_88E)) 2585 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2586 2587 urtwn_write_1(sc, R92C_RF_CTRL, 2588 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2589 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2590 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2591 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2592 2593 if (!(sc->chip & URTWN_CHIP_88E)) { 2594 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2595 urtwn_write_1(sc, 0x15, 0xe9); 2596 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2597 } 2598 2599 /* Select BB programming based on board type. */ 2600 if (sc->chip & URTWN_CHIP_88E) 2601 prog = &rtl8188eu_bb_prog; 2602 else if (!(sc->chip & URTWN_CHIP_92C)) { 2603 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2604 prog = &rtl8188ce_bb_prog; 2605 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2606 prog = &rtl8188ru_bb_prog; 2607 else 2608 prog = &rtl8188cu_bb_prog; 2609 } else { 2610 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2611 prog = &rtl8192ce_bb_prog; 2612 else 2613 prog = &rtl8192cu_bb_prog; 2614 } 2615 /* Write BB initialization values. */ 2616 for (i = 0; i < prog->count; i++) { 2617 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2618 urtwn_ms_delay(sc); 2619 } 2620 2621 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2622 /* 8192C 1T only configuration. */ 2623 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2624 reg = (reg & ~0x00000003) | 0x2; 2625 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2626 2627 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2628 reg = (reg & ~0x00300033) | 0x00200022; 2629 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2630 2631 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2632 reg = (reg & ~0xff000000) | 0x45 << 24; 2633 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2634 2635 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2636 reg = (reg & ~0x000000ff) | 0x23; 2637 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2638 2639 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2640 reg = (reg & ~0x00000030) | 1 << 4; 2641 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2642 2643 reg = urtwn_bb_read(sc, 0xe74); 2644 reg = (reg & ~0x0c000000) | 2 << 26; 2645 urtwn_bb_write(sc, 0xe74, reg); 2646 reg = urtwn_bb_read(sc, 0xe78); 2647 reg = (reg & ~0x0c000000) | 2 << 26; 2648 urtwn_bb_write(sc, 0xe78, reg); 2649 reg = urtwn_bb_read(sc, 0xe7c); 2650 reg = (reg & ~0x0c000000) | 2 << 26; 2651 urtwn_bb_write(sc, 0xe7c, reg); 2652 reg = urtwn_bb_read(sc, 0xe80); 2653 reg = (reg & ~0x0c000000) | 2 << 26; 2654 urtwn_bb_write(sc, 0xe80, reg); 2655 reg = urtwn_bb_read(sc, 0xe88); 2656 reg = (reg & ~0x0c000000) | 2 << 26; 2657 urtwn_bb_write(sc, 0xe88, reg); 2658 } 2659 2660 /* Write AGC values. */ 2661 for (i = 0; i < prog->agccount; i++) { 2662 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2663 prog->agcvals[i]); 2664 urtwn_ms_delay(sc); 2665 } 2666 2667 if (sc->chip & URTWN_CHIP_88E) { 2668 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2669 urtwn_ms_delay(sc); 2670 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2671 urtwn_ms_delay(sc); 2672 2673 crystalcap = sc->r88e_rom[0xb9]; 2674 if (crystalcap == 0xff) 2675 crystalcap = 0x20; 2676 crystalcap &= 0x3f; 2677 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2678 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2679 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2680 crystalcap | crystalcap << 6)); 2681 } else { 2682 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2683 R92C_HSSI_PARAM2_CCK_HIPWR) 2684 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2685 } 2686} 2687 2688void 2689urtwn_rf_init(struct urtwn_softc *sc) 2690{ 2691 const struct urtwn_rf_prog *prog; 2692 uint32_t reg, type; 2693 int i, j, idx, off; 2694 2695 /* Select RF programming based on board type. */ 2696 if (sc->chip & URTWN_CHIP_88E) 2697 prog = rtl8188eu_rf_prog; 2698 else if (!(sc->chip & URTWN_CHIP_92C)) { 2699 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2700 prog = rtl8188ce_rf_prog; 2701 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2702 prog = rtl8188ru_rf_prog; 2703 else 2704 prog = rtl8188cu_rf_prog; 2705 } else 2706 prog = rtl8192ce_rf_prog; 2707 2708 for (i = 0; i < sc->nrxchains; i++) { 2709 /* Save RF_ENV control type. */ 2710 idx = i / 2; 2711 off = (i % 2) * 16; 2712 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2713 type = (reg >> off) & 0x10; 2714 2715 /* Set RF_ENV enable. */ 2716 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2717 reg |= 0x100000; 2718 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2719 urtwn_ms_delay(sc); 2720 /* Set RF_ENV output high. */ 2721 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2722 reg |= 0x10; 2723 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2724 urtwn_ms_delay(sc); 2725 /* Set address and data lengths of RF registers. */ 2726 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2727 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2728 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2729 urtwn_ms_delay(sc); 2730 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2731 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2732 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2733 urtwn_ms_delay(sc); 2734 2735 /* Write RF initialization values for this chain. */ 2736 for (j = 0; j < prog[i].count; j++) { 2737 if (prog[i].regs[j] >= 0xf9 && 2738 prog[i].regs[j] <= 0xfe) { 2739 /* 2740 * These are fake RF registers offsets that 2741 * indicate a delay is required. 2742 */ 2743 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2744 continue; 2745 } 2746 urtwn_rf_write(sc, i, prog[i].regs[j], 2747 prog[i].vals[j]); 2748 urtwn_ms_delay(sc); 2749 } 2750 2751 /* Restore RF_ENV control type. */ 2752 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2753 reg &= ~(0x10 << off) | (type << off); 2754 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2755 2756 /* Cache RF register CHNLBW. */ 2757 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2758 } 2759 2760 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2761 URTWN_CHIP_UMC_A_CUT) { 2762 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2763 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2764 } 2765} 2766 2767static void 2768urtwn_cam_init(struct urtwn_softc *sc) 2769{ 2770 /* Invalidate all CAM entries. */ 2771 urtwn_write_4(sc, R92C_CAMCMD, 2772 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2773} 2774 2775static void 2776urtwn_pa_bias_init(struct urtwn_softc *sc) 2777{ 2778 uint8_t reg; 2779 int i; 2780 2781 for (i = 0; i < sc->nrxchains; i++) { 2782 if (sc->pa_setting & (1 << i)) 2783 continue; 2784 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2785 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2786 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2787 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2788 } 2789 if (!(sc->pa_setting & 0x10)) { 2790 reg = urtwn_read_1(sc, 0x16); 2791 reg = (reg & ~0xf0) | 0x90; 2792 urtwn_write_1(sc, 0x16, reg); 2793 } 2794} 2795 2796static void 2797urtwn_rxfilter_init(struct urtwn_softc *sc) 2798{ 2799 /* Initialize Rx filter. */ 2800 /* TODO: use better filter for monitor mode. */ 2801 urtwn_write_4(sc, R92C_RCR, 2802 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2803 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2804 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2805 /* Accept all multicast frames. */ 2806 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2807 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2808 /* Accept all management frames. */ 2809 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2810 /* Reject all control frames. */ 2811 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2812 /* Accept all data frames. */ 2813 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2814} 2815 2816static void 2817urtwn_edca_init(struct urtwn_softc *sc) 2818{ 2819 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2820 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2821 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2822 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2823 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2824 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2825 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2826 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2827} 2828 2829void 2830urtwn_write_txpower(struct urtwn_softc *sc, int chain, 2831 uint16_t power[URTWN_RIDX_COUNT]) 2832{ 2833 uint32_t reg; 2834 2835 /* Write per-CCK rate Tx power. */ 2836 if (chain == 0) { 2837 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2838 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2839 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2840 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2841 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2842 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2843 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2844 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2845 } else { 2846 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2847 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2848 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2849 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2850 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2851 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2852 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2853 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2854 } 2855 /* Write per-OFDM rate Tx power. */ 2856 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2857 SM(R92C_TXAGC_RATE06, power[ 4]) | 2858 SM(R92C_TXAGC_RATE09, power[ 5]) | 2859 SM(R92C_TXAGC_RATE12, power[ 6]) | 2860 SM(R92C_TXAGC_RATE18, power[ 7])); 2861 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2862 SM(R92C_TXAGC_RATE24, power[ 8]) | 2863 SM(R92C_TXAGC_RATE36, power[ 9]) | 2864 SM(R92C_TXAGC_RATE48, power[10]) | 2865 SM(R92C_TXAGC_RATE54, power[11])); 2866 /* Write per-MCS Tx power. */ 2867 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2868 SM(R92C_TXAGC_MCS00, power[12]) | 2869 SM(R92C_TXAGC_MCS01, power[13]) | 2870 SM(R92C_TXAGC_MCS02, power[14]) | 2871 SM(R92C_TXAGC_MCS03, power[15])); 2872 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2873 SM(R92C_TXAGC_MCS04, power[16]) | 2874 SM(R92C_TXAGC_MCS05, power[17]) | 2875 SM(R92C_TXAGC_MCS06, power[18]) | 2876 SM(R92C_TXAGC_MCS07, power[19])); 2877 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2878 SM(R92C_TXAGC_MCS08, power[20]) | 2879 SM(R92C_TXAGC_MCS09, power[21]) | 2880 SM(R92C_TXAGC_MCS10, power[22]) | 2881 SM(R92C_TXAGC_MCS11, power[23])); 2882 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2883 SM(R92C_TXAGC_MCS12, power[24]) | 2884 SM(R92C_TXAGC_MCS13, power[25]) | 2885 SM(R92C_TXAGC_MCS14, power[26]) | 2886 SM(R92C_TXAGC_MCS15, power[27])); 2887} 2888 2889void 2890urtwn_get_txpower(struct urtwn_softc *sc, int chain, 2891 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2892 uint16_t power[URTWN_RIDX_COUNT]) 2893{ 2894 struct ieee80211com *ic = &sc->sc_ic; 2895 struct r92c_rom *rom = &sc->rom; 2896 uint16_t cckpow, ofdmpow, htpow, diff, max; 2897 const struct urtwn_txpwr *base; 2898 int ridx, chan, group; 2899 2900 /* Determine channel group. */ 2901 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2902 if (chan <= 3) 2903 group = 0; 2904 else if (chan <= 9) 2905 group = 1; 2906 else 2907 group = 2; 2908 2909 /* Get original Tx power based on board type and RF chain. */ 2910 if (!(sc->chip & URTWN_CHIP_92C)) { 2911 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2912 base = &rtl8188ru_txagc[chain]; 2913 else 2914 base = &rtl8192cu_txagc[chain]; 2915 } else 2916 base = &rtl8192cu_txagc[chain]; 2917 2918 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2919 if (sc->regulatory == 0) { 2920 for (ridx = 0; ridx <= 3; ridx++) 2921 power[ridx] = base->pwr[0][ridx]; 2922 } 2923 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 2924 if (sc->regulatory == 3) { 2925 power[ridx] = base->pwr[0][ridx]; 2926 /* Apply vendor limits. */ 2927 if (extc != NULL) 2928 max = rom->ht40_max_pwr[group]; 2929 else 2930 max = rom->ht20_max_pwr[group]; 2931 max = (max >> (chain * 4)) & 0xf; 2932 if (power[ridx] > max) 2933 power[ridx] = max; 2934 } else if (sc->regulatory == 1) { 2935 if (extc == NULL) 2936 power[ridx] = base->pwr[group][ridx]; 2937 } else if (sc->regulatory != 2) 2938 power[ridx] = base->pwr[0][ridx]; 2939 } 2940 2941 /* Compute per-CCK rate Tx power. */ 2942 cckpow = rom->cck_tx_pwr[chain][group]; 2943 for (ridx = 0; ridx <= 3; ridx++) { 2944 power[ridx] += cckpow; 2945 if (power[ridx] > R92C_MAX_TX_PWR) 2946 power[ridx] = R92C_MAX_TX_PWR; 2947 } 2948 2949 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2950 if (sc->ntxchains > 1) { 2951 /* Apply reduction for 2 spatial streams. */ 2952 diff = rom->ht40_2s_tx_pwr_diff[group]; 2953 diff = (diff >> (chain * 4)) & 0xf; 2954 htpow = (htpow > diff) ? htpow - diff : 0; 2955 } 2956 2957 /* Compute per-OFDM rate Tx power. */ 2958 diff = rom->ofdm_tx_pwr_diff[group]; 2959 diff = (diff >> (chain * 4)) & 0xf; 2960 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2961 for (ridx = 4; ridx <= 11; ridx++) { 2962 power[ridx] += ofdmpow; 2963 if (power[ridx] > R92C_MAX_TX_PWR) 2964 power[ridx] = R92C_MAX_TX_PWR; 2965 } 2966 2967 /* Compute per-MCS Tx power. */ 2968 if (extc == NULL) { 2969 diff = rom->ht20_tx_pwr_diff[group]; 2970 diff = (diff >> (chain * 4)) & 0xf; 2971 htpow += diff; /* HT40->HT20 correction. */ 2972 } 2973 for (ridx = 12; ridx <= 27; ridx++) { 2974 power[ridx] += htpow; 2975 if (power[ridx] > R92C_MAX_TX_PWR) 2976 power[ridx] = R92C_MAX_TX_PWR; 2977 } 2978#ifdef URTWN_DEBUG 2979 if (urtwn_debug >= 4) { 2980 /* Dump per-rate Tx power values. */ 2981 printf("Tx power for chain %d:\n", chain); 2982 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 2983 printf("Rate %d = %u\n", ridx, power[ridx]); 2984 } 2985#endif 2986} 2987 2988void 2989urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 2990 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2991 uint16_t power[URTWN_RIDX_COUNT]) 2992{ 2993 struct ieee80211com *ic = &sc->sc_ic; 2994 uint16_t cckpow, ofdmpow, bw20pow, htpow; 2995 const struct urtwn_r88e_txpwr *base; 2996 int ridx, chan, group; 2997 2998 /* Determine channel group. */ 2999 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3000 if (chan <= 2) 3001 group = 0; 3002 else if (chan <= 5) 3003 group = 1; 3004 else if (chan <= 8) 3005 group = 2; 3006 else if (chan <= 11) 3007 group = 3; 3008 else if (chan <= 13) 3009 group = 4; 3010 else 3011 group = 5; 3012 3013 /* Get original Tx power based on board type and RF chain. */ 3014 base = &rtl8188eu_txagc[chain]; 3015 3016 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3017 if (sc->regulatory == 0) { 3018 for (ridx = 0; ridx <= 3; ridx++) 3019 power[ridx] = base->pwr[0][ridx]; 3020 } 3021 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3022 if (sc->regulatory == 3) 3023 power[ridx] = base->pwr[0][ridx]; 3024 else if (sc->regulatory == 1) { 3025 if (extc == NULL) 3026 power[ridx] = base->pwr[group][ridx]; 3027 } else if (sc->regulatory != 2) 3028 power[ridx] = base->pwr[0][ridx]; 3029 } 3030 3031 /* Compute per-CCK rate Tx power. */ 3032 cckpow = sc->cck_tx_pwr[group]; 3033 for (ridx = 0; ridx <= 3; ridx++) { 3034 power[ridx] += cckpow; 3035 if (power[ridx] > R92C_MAX_TX_PWR) 3036 power[ridx] = R92C_MAX_TX_PWR; 3037 } 3038 3039 htpow = sc->ht40_tx_pwr[group]; 3040 3041 /* Compute per-OFDM rate Tx power. */ 3042 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3043 for (ridx = 4; ridx <= 11; ridx++) { 3044 power[ridx] += ofdmpow; 3045 if (power[ridx] > R92C_MAX_TX_PWR) 3046 power[ridx] = R92C_MAX_TX_PWR; 3047 } 3048 3049 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3050 for (ridx = 12; ridx <= 27; ridx++) { 3051 power[ridx] += bw20pow; 3052 if (power[ridx] > R92C_MAX_TX_PWR) 3053 power[ridx] = R92C_MAX_TX_PWR; 3054 } 3055} 3056 3057void 3058urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3059 struct ieee80211_channel *extc) 3060{ 3061 uint16_t power[URTWN_RIDX_COUNT]; 3062 int i; 3063 3064 for (i = 0; i < sc->ntxchains; i++) { 3065 /* Compute per-rate Tx power values. */ 3066 if (sc->chip & URTWN_CHIP_88E) 3067 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3068 else 3069 urtwn_get_txpower(sc, i, c, extc, power); 3070 /* Write per-rate Tx power values to hardware. */ 3071 urtwn_write_txpower(sc, i, power); 3072 } 3073} 3074 3075static void 3076urtwn_scan_start(struct ieee80211com *ic) 3077{ 3078 /* XXX do nothing? */ 3079} 3080 3081static void 3082urtwn_scan_end(struct ieee80211com *ic) 3083{ 3084 /* XXX do nothing? */ 3085} 3086 3087static void 3088urtwn_set_channel(struct ieee80211com *ic) 3089{ 3090 struct urtwn_softc *sc = ic->ic_softc; 3091 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3092 3093 URTWN_LOCK(sc); 3094 if (vap->iv_state == IEEE80211_S_SCAN) { 3095 /* Make link LED blink during scan. */ 3096 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3097 } 3098 urtwn_set_chan(sc, ic->ic_curchan, NULL); 3099 URTWN_UNLOCK(sc); 3100} 3101 3102static void 3103urtwn_update_mcast(struct ieee80211com *ic) 3104{ 3105 /* XXX do nothing? */ 3106} 3107 3108static void 3109urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3110 struct ieee80211_channel *extc) 3111{ 3112 struct ieee80211com *ic = &sc->sc_ic; 3113 uint32_t reg; 3114 u_int chan; 3115 int i; 3116 3117 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3118 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3119 device_printf(sc->sc_dev, 3120 "%s: invalid channel %x\n", __func__, chan); 3121 return; 3122 } 3123 3124 /* Set Tx power for this new channel. */ 3125 urtwn_set_txpower(sc, c, extc); 3126 3127 for (i = 0; i < sc->nrxchains; i++) { 3128 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3129 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3130 } 3131#ifndef IEEE80211_NO_HT 3132 if (extc != NULL) { 3133 /* Is secondary channel below or above primary? */ 3134 int prichlo = c->ic_freq < extc->ic_freq; 3135 3136 urtwn_write_1(sc, R92C_BWOPMODE, 3137 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3138 3139 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3140 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3141 urtwn_write_1(sc, R92C_RRSR + 2, reg); 3142 3143 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3144 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3145 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3146 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3147 3148 /* Set CCK side band. */ 3149 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3150 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3151 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3152 3153 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3154 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3155 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3156 3157 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3158 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3159 ~R92C_FPGA0_ANAPARAM2_CBW20); 3160 3161 reg = urtwn_bb_read(sc, 0x818); 3162 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3163 urtwn_bb_write(sc, 0x818, reg); 3164 3165 /* Select 40MHz bandwidth. */ 3166 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3167 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3168 } else 3169#endif 3170 { 3171 urtwn_write_1(sc, R92C_BWOPMODE, 3172 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3173 3174 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3175 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3176 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3177 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3178 3179 if (!(sc->chip & URTWN_CHIP_88E)) { 3180 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3181 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3182 R92C_FPGA0_ANAPARAM2_CBW20); 3183 } 3184 3185 /* Select 20MHz bandwidth. */ 3186 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3187 (sc->rf_chnlbw[0] & ~0xfff) | chan | 3188 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3189 R92C_RF_CHNLBW_BW20)); 3190 } 3191} 3192 3193static void 3194urtwn_iq_calib(struct urtwn_softc *sc) 3195{ 3196 /* TODO */ 3197} 3198 3199static void 3200urtwn_lc_calib(struct urtwn_softc *sc) 3201{ 3202 uint32_t rf_ac[2]; 3203 uint8_t txmode; 3204 int i; 3205 3206 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3207 if ((txmode & 0x70) != 0) { 3208 /* Disable all continuous Tx. */ 3209 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3210 3211 /* Set RF mode to standby mode. */ 3212 for (i = 0; i < sc->nrxchains; i++) { 3213 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3214 urtwn_rf_write(sc, i, R92C_RF_AC, 3215 RW(rf_ac[i], R92C_RF_AC_MODE, 3216 R92C_RF_AC_MODE_STANDBY)); 3217 } 3218 } else { 3219 /* Block all Tx queues. */ 3220 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3221 } 3222 /* Start calibration. */ 3223 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3224 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3225 3226 /* Give calibration the time to complete. */ 3227 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3228 3229 /* Restore configuration. */ 3230 if ((txmode & 0x70) != 0) { 3231 /* Restore Tx mode. */ 3232 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3233 /* Restore RF mode. */ 3234 for (i = 0; i < sc->nrxchains; i++) 3235 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3236 } else { 3237 /* Unblock all Tx queues. */ 3238 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3239 } 3240} 3241 3242static void 3243urtwn_init(struct urtwn_softc *sc) 3244{ 3245 struct ieee80211com *ic = &sc->sc_ic; 3246 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3247 uint8_t macaddr[IEEE80211_ADDR_LEN]; 3248 uint32_t reg; 3249 int error; 3250 3251 URTWN_ASSERT_LOCKED(sc); 3252 3253 if (sc->sc_flags & URTWN_RUNNING) 3254 urtwn_stop(sc); 3255 3256 /* Init firmware commands ring. */ 3257 sc->fwcur = 0; 3258 3259 /* Allocate Tx/Rx buffers. */ 3260 error = urtwn_alloc_rx_list(sc); 3261 if (error != 0) 3262 goto fail; 3263 3264 error = urtwn_alloc_tx_list(sc); 3265 if (error != 0) 3266 goto fail; 3267 3268 /* Power on adapter. */ 3269 error = urtwn_power_on(sc); 3270 if (error != 0) 3271 goto fail; 3272 3273 /* Initialize DMA. */ 3274 error = urtwn_dma_init(sc); 3275 if (error != 0) 3276 goto fail; 3277 3278 /* Set info size in Rx descriptors (in 64-bit words). */ 3279 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3280 3281 /* Init interrupts. */ 3282 if (sc->chip & URTWN_CHIP_88E) { 3283 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3284 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3285 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3286 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3287 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3288 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3289 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3290 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3291 } else { 3292 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3293 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3294 } 3295 3296 /* Set MAC address. */ 3297 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3298 urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3299 3300 /* Set initial network type. */ 3301 reg = urtwn_read_4(sc, R92C_CR); 3302 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3303 urtwn_write_4(sc, R92C_CR, reg); 3304 3305 urtwn_rxfilter_init(sc); 3306 3307 /* Set response rate. */ 3308 reg = urtwn_read_4(sc, R92C_RRSR); 3309 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3310 urtwn_write_4(sc, R92C_RRSR, reg); 3311 3312 /* Set short/long retry limits. */ 3313 urtwn_write_2(sc, R92C_RL, 3314 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3315 3316 /* Initialize EDCA parameters. */ 3317 urtwn_edca_init(sc); 3318 3319 /* Setup rate fallback. */ 3320 if (!(sc->chip & URTWN_CHIP_88E)) { 3321 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3322 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3323 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3324 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3325 } 3326 3327 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3328 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3329 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3330 /* Set ACK timeout. */ 3331 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3332 3333 /* Setup USB aggregation. */ 3334 reg = urtwn_read_4(sc, R92C_TDECTRL); 3335 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3336 urtwn_write_4(sc, R92C_TDECTRL, reg); 3337 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3338 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3339 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3340 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3341 if (sc->chip & URTWN_CHIP_88E) 3342 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3343 else { 3344 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3345 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3346 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3347 R92C_USB_SPECIAL_OPTION_AGG_EN); 3348 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3349 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3350 } 3351 3352 /* Initialize beacon parameters. */ 3353 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3354 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3355 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3356 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3357 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3358 3359 if (!(sc->chip & URTWN_CHIP_88E)) { 3360 /* Setup AMPDU aggregation. */ 3361 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3362 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3363 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3364 3365 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3366 } 3367 3368 /* Load 8051 microcode. */ 3369 error = urtwn_load_firmware(sc); 3370 if (error != 0) 3371 goto fail; 3372 3373 /* Initialize MAC/BB/RF blocks. */ 3374 urtwn_mac_init(sc); 3375 urtwn_bb_init(sc); 3376 urtwn_rf_init(sc); 3377 3378 if (sc->chip & URTWN_CHIP_88E) { 3379 urtwn_write_2(sc, R92C_CR, 3380 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3381 R92C_CR_MACRXEN); 3382 } 3383 3384 /* Turn CCK and OFDM blocks on. */ 3385 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3386 reg |= R92C_RFMOD_CCK_EN; 3387 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3388 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3389 reg |= R92C_RFMOD_OFDM_EN; 3390 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3391 3392 /* Clear per-station keys table. */ 3393 urtwn_cam_init(sc); 3394 3395 /* Enable hardware sequence numbering. */ 3396 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3397 3398 /* Perform LO and IQ calibrations. */ 3399 urtwn_iq_calib(sc); 3400 /* Perform LC calibration. */ 3401 urtwn_lc_calib(sc); 3402 3403 /* Fix USB interference issue. */ 3404 if (!(sc->chip & URTWN_CHIP_88E)) { 3405 urtwn_write_1(sc, 0xfe40, 0xe0); 3406 urtwn_write_1(sc, 0xfe41, 0x8d); 3407 urtwn_write_1(sc, 0xfe42, 0x80); 3408 3409 urtwn_pa_bias_init(sc); 3410 } 3411 3412 /* Initialize GPIO setting. */ 3413 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3414 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3415 3416 /* Fix for lower temperature. */ 3417 if (!(sc->chip & URTWN_CHIP_88E)) 3418 urtwn_write_1(sc, 0x15, 0xe9); 3419 3420 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3421 3422 sc->sc_flags |= URTWN_RUNNING; 3423 3424 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3425fail: 3426 return; 3427} 3428 3429static void 3430urtwn_stop(struct urtwn_softc *sc) 3431{ 3432 3433 URTWN_ASSERT_LOCKED(sc); 3434 sc->sc_flags &= ~URTWN_RUNNING; 3435 callout_stop(&sc->sc_watchdog_ch); 3436 urtwn_abort_xfers(sc); 3437 3438 urtwn_drain_mbufq(sc); 3439} 3440 3441static void 3442urtwn_abort_xfers(struct urtwn_softc *sc) 3443{ 3444 int i; 3445 3446 URTWN_ASSERT_LOCKED(sc); 3447 3448 /* abort any pending transfers */ 3449 for (i = 0; i < URTWN_N_TRANSFER; i++) 3450 usbd_transfer_stop(sc->sc_xfer[i]); 3451} 3452 3453static int 3454urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3455 const struct ieee80211_bpf_params *params) 3456{ 3457 struct ieee80211com *ic = ni->ni_ic; 3458 struct urtwn_softc *sc = ic->ic_softc; 3459 struct urtwn_data *bf; 3460 3461 /* prevent management frames from being sent if we're not ready */ 3462 if (!(sc->sc_flags & URTWN_RUNNING)) { 3463 m_freem(m); 3464 ieee80211_free_node(ni); 3465 return (ENETDOWN); 3466 } 3467 URTWN_LOCK(sc); 3468 bf = urtwn_getbuf(sc); 3469 if (bf == NULL) { 3470 ieee80211_free_node(ni); 3471 m_freem(m); 3472 URTWN_UNLOCK(sc); 3473 return (ENOBUFS); 3474 } 3475 3476 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3477 m_freem(m); 3478 ieee80211_free_node(ni); 3479 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3480 URTWN_UNLOCK(sc); 3481 return (EIO); 3482 } 3483 sc->sc_txtimer = 5; 3484 URTWN_UNLOCK(sc); 3485 3486 return (0); 3487} 3488 3489static void 3490urtwn_ms_delay(struct urtwn_softc *sc) 3491{ 3492 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3493} 3494 3495static device_method_t urtwn_methods[] = { 3496 /* Device interface */ 3497 DEVMETHOD(device_probe, urtwn_match), 3498 DEVMETHOD(device_attach, urtwn_attach), 3499 DEVMETHOD(device_detach, urtwn_detach), 3500 3501 DEVMETHOD_END 3502}; 3503 3504static driver_t urtwn_driver = { 3505 "urtwn", 3506 urtwn_methods, 3507 sizeof(struct urtwn_softc) 3508}; 3509 3510static devclass_t urtwn_devclass; 3511 3512DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3513MODULE_DEPEND(urtwn, usb, 1, 1, 1); 3514MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3515MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3516MODULE_VERSION(urtwn, 1); 3517