if_urtwn.c revision 288088
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 288088 2015-09-22 02:48:59Z adrian $"); 22 23/* 24 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25 */ 26 27#include <sys/param.h> 28#include <sys/sockio.h> 29#include <sys/sysctl.h> 30#include <sys/lock.h> 31#include <sys/mutex.h> 32#include <sys/mbuf.h> 33#include <sys/kernel.h> 34#include <sys/socket.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/bus.h> 39#include <sys/endian.h> 40#include <sys/linker.h> 41#include <sys/firmware.h> 42#include <sys/kdb.h> 43 44#include <machine/bus.h> 45#include <machine/resource.h> 46#include <sys/rman.h> 47 48#include <net/bpf.h> 49#include <net/if.h> 50#include <net/if_var.h> 51#include <net/if_arp.h> 52#include <net/ethernet.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55#include <net/if_types.h> 56 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/if_ether.h> 61#include <netinet/ip.h> 62 63#include <net80211/ieee80211_var.h> 64#include <net80211/ieee80211_input.h> 65#include <net80211/ieee80211_regdomain.h> 66#include <net80211/ieee80211_radiotap.h> 67#include <net80211/ieee80211_ratectl.h> 68 69#include <dev/usb/usb.h> 70#include <dev/usb/usbdi.h> 71#include "usbdevs.h" 72 73#define USB_DEBUG_VAR urtwn_debug 74#include <dev/usb/usb_debug.h> 75 76#include <dev/usb/wlan/if_urtwnreg.h> 77 78#ifdef USB_DEBUG 79static int urtwn_debug = 0; 80 81SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 82SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 83 "Debug level"); 84#endif 85 86#define URTWN_RSSI(r) (r) - 110 87#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 88 89/* various supported device vendors/products */ 90static const STRUCT_USB_HOST_ID urtwn_devs[] = { 91#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 92#define URTWN_RTL8188E_DEV(v,p) \ 93 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 94#define URTWN_RTL8188E 1 95 URTWN_DEV(ABOCOM, RTL8188CU_1), 96 URTWN_DEV(ABOCOM, RTL8188CU_2), 97 URTWN_DEV(ABOCOM, RTL8192CU), 98 URTWN_DEV(ASUS, RTL8192CU), 99 URTWN_DEV(ASUS, USBN10NANO), 100 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 101 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 102 URTWN_DEV(AZUREWAVE, RTL8188CU), 103 URTWN_DEV(BELKIN, F7D2102), 104 URTWN_DEV(BELKIN, RTL8188CU), 105 URTWN_DEV(BELKIN, RTL8192CU), 106 URTWN_DEV(CHICONY, RTL8188CUS_1), 107 URTWN_DEV(CHICONY, RTL8188CUS_2), 108 URTWN_DEV(CHICONY, RTL8188CUS_3), 109 URTWN_DEV(CHICONY, RTL8188CUS_4), 110 URTWN_DEV(CHICONY, RTL8188CUS_5), 111 URTWN_DEV(COREGA, RTL8192CU), 112 URTWN_DEV(DLINK, RTL8188CU), 113 URTWN_DEV(DLINK, RTL8192CU_1), 114 URTWN_DEV(DLINK, RTL8192CU_2), 115 URTWN_DEV(DLINK, RTL8192CU_3), 116 URTWN_DEV(DLINK, DWA131B), 117 URTWN_DEV(EDIMAX, EW7811UN), 118 URTWN_DEV(EDIMAX, RTL8192CU), 119 URTWN_DEV(FEIXUN, RTL8188CU), 120 URTWN_DEV(FEIXUN, RTL8192CU), 121 URTWN_DEV(GUILLEMOT, HWNUP150), 122 URTWN_DEV(HAWKING, RTL8192CU), 123 URTWN_DEV(HP3, RTL8188CU), 124 URTWN_DEV(NETGEAR, WNA1000M), 125 URTWN_DEV(NETGEAR, RTL8192CU), 126 URTWN_DEV(NETGEAR4, RTL8188CU), 127 URTWN_DEV(NOVATECH, RTL8188CU), 128 URTWN_DEV(PLANEX2, RTL8188CU_1), 129 URTWN_DEV(PLANEX2, RTL8188CU_2), 130 URTWN_DEV(PLANEX2, RTL8188CU_3), 131 URTWN_DEV(PLANEX2, RTL8188CU_4), 132 URTWN_DEV(PLANEX2, RTL8188CUS), 133 URTWN_DEV(PLANEX2, RTL8192CU), 134 URTWN_DEV(REALTEK, RTL8188CE_0), 135 URTWN_DEV(REALTEK, RTL8188CE_1), 136 URTWN_DEV(REALTEK, RTL8188CTV), 137 URTWN_DEV(REALTEK, RTL8188CU_0), 138 URTWN_DEV(REALTEK, RTL8188CU_1), 139 URTWN_DEV(REALTEK, RTL8188CU_2), 140 URTWN_DEV(REALTEK, RTL8188CU_3), 141 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 142 URTWN_DEV(REALTEK, RTL8188CUS), 143 URTWN_DEV(REALTEK, RTL8188RU_1), 144 URTWN_DEV(REALTEK, RTL8188RU_2), 145 URTWN_DEV(REALTEK, RTL8188RU_3), 146 URTWN_DEV(REALTEK, RTL8191CU), 147 URTWN_DEV(REALTEK, RTL8192CE), 148 URTWN_DEV(REALTEK, RTL8192CU), 149 URTWN_DEV(SITECOMEU, RTL8188CU_1), 150 URTWN_DEV(SITECOMEU, RTL8188CU_2), 151 URTWN_DEV(SITECOMEU, RTL8192CU), 152 URTWN_DEV(TRENDNET, RTL8188CU), 153 URTWN_DEV(TRENDNET, RTL8192CU), 154 URTWN_DEV(ZYXEL, RTL8192CU), 155 /* URTWN_RTL8188E */ 156 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 157 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 158 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 159 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 160 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 161#undef URTWN_RTL8188E_DEV 162#undef URTWN_DEV 163}; 164 165static device_probe_t urtwn_match; 166static device_attach_t urtwn_attach; 167static device_detach_t urtwn_detach; 168 169static usb_callback_t urtwn_bulk_tx_callback; 170static usb_callback_t urtwn_bulk_rx_callback; 171 172static usb_error_t urtwn_do_request(struct urtwn_softc *, 173 struct usb_device_request *, void *); 174static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 175 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 176 const uint8_t [IEEE80211_ADDR_LEN], 177 const uint8_t [IEEE80211_ADDR_LEN]); 178static void urtwn_vap_delete(struct ieee80211vap *); 179static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 180 int *); 181static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 182 int *, int8_t *); 183static void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 184static int urtwn_alloc_list(struct urtwn_softc *, 185 struct urtwn_data[], int, int); 186static int urtwn_alloc_rx_list(struct urtwn_softc *); 187static int urtwn_alloc_tx_list(struct urtwn_softc *); 188static void urtwn_free_tx_list(struct urtwn_softc *); 189static void urtwn_free_rx_list(struct urtwn_softc *); 190static void urtwn_free_list(struct urtwn_softc *, 191 struct urtwn_data data[], int); 192static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 193static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 194static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 195 uint8_t *, int); 196static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 197static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 198static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 199static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 200 uint8_t *, int); 201static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 202static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 203static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 204static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 205 const void *, int); 206static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 207 uint8_t, uint32_t); 208static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 209 uint8_t, uint32_t); 210static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 211static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 212 uint32_t); 213static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 214static void urtwn_efuse_read(struct urtwn_softc *); 215static void urtwn_efuse_switch_power(struct urtwn_softc *); 216static int urtwn_read_chipid(struct urtwn_softc *); 217static void urtwn_read_rom(struct urtwn_softc *); 218static void urtwn_r88e_read_rom(struct urtwn_softc *); 219static int urtwn_ra_init(struct urtwn_softc *); 220static void urtwn_tsf_sync_enable(struct urtwn_softc *); 221static void urtwn_set_led(struct urtwn_softc *, int, int); 222static int urtwn_newstate(struct ieee80211vap *, 223 enum ieee80211_state, int); 224static void urtwn_watchdog(void *); 225static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 226static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 227static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 228static int urtwn_tx_start(struct urtwn_softc *, 229 struct ieee80211_node *, struct mbuf *, 230 struct urtwn_data *); 231static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 232static void urtwn_start(struct urtwn_softc *); 233static void urtwn_parent(struct ieee80211com *); 234static int urtwn_r92c_power_on(struct urtwn_softc *); 235static int urtwn_r88e_power_on(struct urtwn_softc *); 236static int urtwn_llt_init(struct urtwn_softc *); 237static void urtwn_fw_reset(struct urtwn_softc *); 238static void urtwn_r88e_fw_reset(struct urtwn_softc *); 239static int urtwn_fw_loadpage(struct urtwn_softc *, int, 240 const uint8_t *, int); 241static int urtwn_load_firmware(struct urtwn_softc *); 242static int urtwn_r92c_dma_init(struct urtwn_softc *); 243static int urtwn_r88e_dma_init(struct urtwn_softc *); 244static void urtwn_mac_init(struct urtwn_softc *); 245static void urtwn_bb_init(struct urtwn_softc *); 246static void urtwn_rf_init(struct urtwn_softc *); 247static void urtwn_cam_init(struct urtwn_softc *); 248static void urtwn_pa_bias_init(struct urtwn_softc *); 249static void urtwn_rxfilter_init(struct urtwn_softc *); 250static void urtwn_edca_init(struct urtwn_softc *); 251static void urtwn_write_txpower(struct urtwn_softc *, int, 252 uint16_t[]); 253static void urtwn_get_txpower(struct urtwn_softc *, int, 254 struct ieee80211_channel *, 255 struct ieee80211_channel *, uint16_t[]); 256static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 257 struct ieee80211_channel *, 258 struct ieee80211_channel *, uint16_t[]); 259static void urtwn_set_txpower(struct urtwn_softc *, 260 struct ieee80211_channel *, 261 struct ieee80211_channel *); 262static void urtwn_scan_start(struct ieee80211com *); 263static void urtwn_scan_end(struct ieee80211com *); 264static void urtwn_set_channel(struct ieee80211com *); 265static void urtwn_set_chan(struct urtwn_softc *, 266 struct ieee80211_channel *, 267 struct ieee80211_channel *); 268static void urtwn_update_mcast(struct ieee80211com *); 269static void urtwn_iq_calib(struct urtwn_softc *); 270static void urtwn_lc_calib(struct urtwn_softc *); 271static void urtwn_init(struct urtwn_softc *); 272static void urtwn_stop(struct urtwn_softc *); 273static void urtwn_abort_xfers(struct urtwn_softc *); 274static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 275 const struct ieee80211_bpf_params *); 276static void urtwn_ms_delay(struct urtwn_softc *); 277 278/* Aliases. */ 279#define urtwn_bb_write urtwn_write_4 280#define urtwn_bb_read urtwn_read_4 281 282static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 283 [URTWN_BULK_RX] = { 284 .type = UE_BULK, 285 .endpoint = UE_ADDR_ANY, 286 .direction = UE_DIR_IN, 287 .bufsize = URTWN_RXBUFSZ, 288 .flags = { 289 .pipe_bof = 1, 290 .short_xfer_ok = 1 291 }, 292 .callback = urtwn_bulk_rx_callback, 293 }, 294 [URTWN_BULK_TX_BE] = { 295 .type = UE_BULK, 296 .endpoint = 0x03, 297 .direction = UE_DIR_OUT, 298 .bufsize = URTWN_TXBUFSZ, 299 .flags = { 300 .ext_buffer = 1, 301 .pipe_bof = 1, 302 .force_short_xfer = 1 303 }, 304 .callback = urtwn_bulk_tx_callback, 305 .timeout = URTWN_TX_TIMEOUT, /* ms */ 306 }, 307 [URTWN_BULK_TX_BK] = { 308 .type = UE_BULK, 309 .endpoint = 0x03, 310 .direction = UE_DIR_OUT, 311 .bufsize = URTWN_TXBUFSZ, 312 .flags = { 313 .ext_buffer = 1, 314 .pipe_bof = 1, 315 .force_short_xfer = 1, 316 }, 317 .callback = urtwn_bulk_tx_callback, 318 .timeout = URTWN_TX_TIMEOUT, /* ms */ 319 }, 320 [URTWN_BULK_TX_VI] = { 321 .type = UE_BULK, 322 .endpoint = 0x02, 323 .direction = UE_DIR_OUT, 324 .bufsize = URTWN_TXBUFSZ, 325 .flags = { 326 .ext_buffer = 1, 327 .pipe_bof = 1, 328 .force_short_xfer = 1 329 }, 330 .callback = urtwn_bulk_tx_callback, 331 .timeout = URTWN_TX_TIMEOUT, /* ms */ 332 }, 333 [URTWN_BULK_TX_VO] = { 334 .type = UE_BULK, 335 .endpoint = 0x02, 336 .direction = UE_DIR_OUT, 337 .bufsize = URTWN_TXBUFSZ, 338 .flags = { 339 .ext_buffer = 1, 340 .pipe_bof = 1, 341 .force_short_xfer = 1 342 }, 343 .callback = urtwn_bulk_tx_callback, 344 .timeout = URTWN_TX_TIMEOUT, /* ms */ 345 }, 346}; 347 348static int 349urtwn_match(device_t self) 350{ 351 struct usb_attach_arg *uaa = device_get_ivars(self); 352 353 if (uaa->usb_mode != USB_MODE_HOST) 354 return (ENXIO); 355 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 356 return (ENXIO); 357 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 358 return (ENXIO); 359 360 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 361} 362 363static int 364urtwn_attach(device_t self) 365{ 366 struct usb_attach_arg *uaa = device_get_ivars(self); 367 struct urtwn_softc *sc = device_get_softc(self); 368 struct ieee80211com *ic = &sc->sc_ic; 369 uint8_t iface_index, bands; 370 int error; 371 372 device_set_usb_desc(self); 373 sc->sc_udev = uaa->device; 374 sc->sc_dev = self; 375 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 376 sc->chip |= URTWN_CHIP_88E; 377 378 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 379 MTX_NETWORK_LOCK, MTX_DEF); 380 callout_init(&sc->sc_watchdog_ch, 0); 381 mbufq_init(&sc->sc_snd, ifqmaxlen); 382 383 iface_index = URTWN_IFACE_INDEX; 384 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 385 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 386 if (error) { 387 device_printf(self, "could not allocate USB transfers, " 388 "err=%s\n", usbd_errstr(error)); 389 goto detach; 390 } 391 392 URTWN_LOCK(sc); 393 394 error = urtwn_read_chipid(sc); 395 if (error) { 396 device_printf(sc->sc_dev, "unsupported test chip\n"); 397 URTWN_UNLOCK(sc); 398 goto detach; 399 } 400 401 /* Determine number of Tx/Rx chains. */ 402 if (sc->chip & URTWN_CHIP_92C) { 403 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 404 sc->nrxchains = 2; 405 } else { 406 sc->ntxchains = 1; 407 sc->nrxchains = 1; 408 } 409 410 if (sc->chip & URTWN_CHIP_88E) 411 urtwn_r88e_read_rom(sc); 412 else 413 urtwn_read_rom(sc); 414 415 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 416 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 417 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 418 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 419 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 420 "8188CUS", sc->ntxchains, sc->nrxchains); 421 422 URTWN_UNLOCK(sc); 423 424 ic->ic_softc = sc; 425 ic->ic_name = device_get_nameunit(self); 426 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 427 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 428 429 /* set device capabilities */ 430 ic->ic_caps = 431 IEEE80211_C_STA /* station mode */ 432 | IEEE80211_C_MONITOR /* monitor mode */ 433 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 434 | IEEE80211_C_SHSLOT /* short slot time supported */ 435 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 436 | IEEE80211_C_WPA /* 802.11i */ 437 ; 438 439 bands = 0; 440 setbit(&bands, IEEE80211_MODE_11B); 441 setbit(&bands, IEEE80211_MODE_11G); 442 ieee80211_init_channels(ic, NULL, &bands); 443 444 ieee80211_ifattach(ic); 445 ic->ic_raw_xmit = urtwn_raw_xmit; 446 ic->ic_scan_start = urtwn_scan_start; 447 ic->ic_scan_end = urtwn_scan_end; 448 ic->ic_set_channel = urtwn_set_channel; 449 ic->ic_transmit = urtwn_transmit; 450 ic->ic_parent = urtwn_parent; 451 ic->ic_vap_create = urtwn_vap_create; 452 ic->ic_vap_delete = urtwn_vap_delete; 453 ic->ic_update_mcast = urtwn_update_mcast; 454 455 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 456 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 457 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 458 URTWN_RX_RADIOTAP_PRESENT); 459 460 if (bootverbose) 461 ieee80211_announce(ic); 462 463 return (0); 464 465detach: 466 urtwn_detach(self); 467 return (ENXIO); /* failure */ 468} 469 470static int 471urtwn_detach(device_t self) 472{ 473 struct urtwn_softc *sc = device_get_softc(self); 474 struct ieee80211com *ic = &sc->sc_ic; 475 unsigned int x; 476 477 /* Prevent further ioctls. */ 478 URTWN_LOCK(sc); 479 sc->sc_flags |= URTWN_DETACHED; 480 urtwn_stop(sc); 481 URTWN_UNLOCK(sc); 482 483 callout_drain(&sc->sc_watchdog_ch); 484 485 /* Prevent further allocations from RX/TX data lists. */ 486 URTWN_LOCK(sc); 487 STAILQ_INIT(&sc->sc_tx_active); 488 STAILQ_INIT(&sc->sc_tx_inactive); 489 STAILQ_INIT(&sc->sc_tx_pending); 490 491 STAILQ_INIT(&sc->sc_rx_active); 492 STAILQ_INIT(&sc->sc_rx_inactive); 493 URTWN_UNLOCK(sc); 494 495 /* drain USB transfers */ 496 for (x = 0; x != URTWN_N_TRANSFER; x++) 497 usbd_transfer_drain(sc->sc_xfer[x]); 498 499 /* Free data buffers. */ 500 URTWN_LOCK(sc); 501 urtwn_free_tx_list(sc); 502 urtwn_free_rx_list(sc); 503 URTWN_UNLOCK(sc); 504 505 /* stop all USB transfers */ 506 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 507 ieee80211_ifdetach(ic); 508 mbufq_drain(&sc->sc_snd); 509 mtx_destroy(&sc->sc_mtx); 510 511 return (0); 512} 513 514static void 515urtwn_free_tx_list(struct urtwn_softc *sc) 516{ 517 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 518} 519 520static void 521urtwn_free_rx_list(struct urtwn_softc *sc) 522{ 523 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 524} 525 526static void 527urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 528{ 529 int i; 530 531 for (i = 0; i < ndata; i++) { 532 struct urtwn_data *dp = &data[i]; 533 534 if (dp->buf != NULL) { 535 free(dp->buf, M_USBDEV); 536 dp->buf = NULL; 537 } 538 if (dp->ni != NULL) { 539 ieee80211_free_node(dp->ni); 540 dp->ni = NULL; 541 } 542 } 543} 544 545static usb_error_t 546urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 547 void *data) 548{ 549 usb_error_t err; 550 int ntries = 10; 551 552 URTWN_ASSERT_LOCKED(sc); 553 554 while (ntries--) { 555 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 556 req, data, 0, NULL, 250 /* ms */); 557 if (err == 0) 558 break; 559 560 DPRINTFN(1, "Control request failed, %s (retrying)\n", 561 usbd_errstr(err)); 562 usb_pause_mtx(&sc->sc_mtx, hz / 100); 563 } 564 return (err); 565} 566 567static struct ieee80211vap * 568urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 569 enum ieee80211_opmode opmode, int flags, 570 const uint8_t bssid[IEEE80211_ADDR_LEN], 571 const uint8_t mac[IEEE80211_ADDR_LEN]) 572{ 573 struct urtwn_vap *uvp; 574 struct ieee80211vap *vap; 575 576 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 577 return (NULL); 578 579 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 580 vap = &uvp->vap; 581 /* enable s/w bmiss handling for sta mode */ 582 583 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 584 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 585 /* out of memory */ 586 free(uvp, M_80211_VAP); 587 return (NULL); 588 } 589 590 /* override state transition machine */ 591 uvp->newstate = vap->iv_newstate; 592 vap->iv_newstate = urtwn_newstate; 593 594 /* complete setup */ 595 ieee80211_vap_attach(vap, ieee80211_media_change, 596 ieee80211_media_status, mac); 597 ic->ic_opmode = opmode; 598 return (vap); 599} 600 601static void 602urtwn_vap_delete(struct ieee80211vap *vap) 603{ 604 struct urtwn_vap *uvp = URTWN_VAP(vap); 605 606 ieee80211_vap_detach(vap); 607 free(uvp, M_80211_VAP); 608} 609 610static struct mbuf * 611urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 612{ 613 struct ieee80211com *ic = &sc->sc_ic; 614 struct ieee80211_frame *wh; 615 struct mbuf *m; 616 struct r92c_rx_stat *stat; 617 uint32_t rxdw0, rxdw3; 618 uint8_t rate; 619 int8_t rssi = 0; 620 int infosz; 621 622 /* 623 * don't pass packets to the ieee80211 framework if the driver isn't 624 * RUNNING. 625 */ 626 if (!(sc->sc_flags & URTWN_RUNNING)) 627 return (NULL); 628 629 stat = (struct r92c_rx_stat *)buf; 630 rxdw0 = le32toh(stat->rxdw0); 631 rxdw3 = le32toh(stat->rxdw3); 632 633 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 634 /* 635 * This should not happen since we setup our Rx filter 636 * to not receive these frames. 637 */ 638 counter_u64_add(ic->ic_ierrors, 1); 639 return (NULL); 640 } 641 if (pktlen < sizeof(*wh) || pktlen > MCLBYTES) { 642 counter_u64_add(ic->ic_ierrors, 1); 643 return (NULL); 644 } 645 646 rate = MS(rxdw3, R92C_RXDW3_RATE); 647 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 648 649 /* Get RSSI from PHY status descriptor if present. */ 650 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 651 if (sc->chip & URTWN_CHIP_88E) 652 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 653 else 654 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 655 /* Update our average RSSI. */ 656 urtwn_update_avgrssi(sc, rate, rssi); 657 /* 658 * Convert the RSSI to a range that will be accepted 659 * by net80211. 660 */ 661 rssi = URTWN_RSSI(rssi); 662 } 663 664 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 665 if (m == NULL) { 666 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 667 return (NULL); 668 } 669 670 /* Finalize mbuf. */ 671 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 672 memcpy(mtod(m, uint8_t *), wh, pktlen); 673 m->m_pkthdr.len = m->m_len = pktlen; 674 675 if (ieee80211_radiotap_active(ic)) { 676 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 677 678 tap->wr_flags = 0; 679 /* Map HW rate index to 802.11 rate. */ 680 if (!(rxdw3 & R92C_RXDW3_HT)) { 681 switch (rate) { 682 /* CCK. */ 683 case 0: tap->wr_rate = 2; break; 684 case 1: tap->wr_rate = 4; break; 685 case 2: tap->wr_rate = 11; break; 686 case 3: tap->wr_rate = 22; break; 687 /* OFDM. */ 688 case 4: tap->wr_rate = 12; break; 689 case 5: tap->wr_rate = 18; break; 690 case 6: tap->wr_rate = 24; break; 691 case 7: tap->wr_rate = 36; break; 692 case 8: tap->wr_rate = 48; break; 693 case 9: tap->wr_rate = 72; break; 694 case 10: tap->wr_rate = 96; break; 695 case 11: tap->wr_rate = 108; break; 696 } 697 } else if (rate >= 12) { /* MCS0~15. */ 698 /* Bit 7 set means HT MCS instead of rate. */ 699 tap->wr_rate = 0x80 | (rate - 12); 700 } 701 tap->wr_dbm_antsignal = rssi; 702 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 703 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 704 } 705 706 *rssi_p = rssi; 707 708 return (m); 709} 710 711static struct mbuf * 712urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 713 int8_t *nf) 714{ 715 struct urtwn_softc *sc = data->sc; 716 struct ieee80211com *ic = &sc->sc_ic; 717 struct r92c_rx_stat *stat; 718 struct mbuf *m, *m0 = NULL, *prevm = NULL; 719 uint32_t rxdw0; 720 uint8_t *buf; 721 int len, totlen, pktlen, infosz, npkts; 722 723 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 724 725 if (len < sizeof(*stat)) { 726 counter_u64_add(ic->ic_ierrors, 1); 727 return (NULL); 728 } 729 730 buf = data->buf; 731 /* Get the number of encapsulated frames. */ 732 stat = (struct r92c_rx_stat *)buf; 733 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 734 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 735 736 /* Process all of them. */ 737 while (npkts-- > 0) { 738 if (len < sizeof(*stat)) 739 break; 740 stat = (struct r92c_rx_stat *)buf; 741 rxdw0 = le32toh(stat->rxdw0); 742 743 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 744 if (pktlen == 0) 745 break; 746 747 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 748 749 /* Make sure everything fits in xfer. */ 750 totlen = sizeof(*stat) + infosz + pktlen; 751 if (totlen > len) 752 break; 753 754 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 755 if (m0 == NULL) 756 m0 = m; 757 if (prevm == NULL) 758 prevm = m; 759 else { 760 prevm->m_next = m; 761 prevm = m; 762 } 763 764 /* Next chunk is 128-byte aligned. */ 765 totlen = (totlen + 127) & ~127; 766 buf += totlen; 767 len -= totlen; 768 } 769 770 return (m0); 771} 772 773static void 774urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 775{ 776 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 777 struct ieee80211com *ic = &sc->sc_ic; 778 struct ieee80211_frame *wh; 779 struct ieee80211_node *ni; 780 struct mbuf *m = NULL, *next; 781 struct urtwn_data *data; 782 int8_t nf; 783 int rssi = 1; 784 785 URTWN_ASSERT_LOCKED(sc); 786 787 switch (USB_GET_STATE(xfer)) { 788 case USB_ST_TRANSFERRED: 789 data = STAILQ_FIRST(&sc->sc_rx_active); 790 if (data == NULL) 791 goto tr_setup; 792 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 793 m = urtwn_rxeof(xfer, data, &rssi, &nf); 794 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 795 /* FALLTHROUGH */ 796 case USB_ST_SETUP: 797tr_setup: 798 data = STAILQ_FIRST(&sc->sc_rx_inactive); 799 if (data == NULL) { 800 KASSERT(m == NULL, ("mbuf isn't NULL")); 801 return; 802 } 803 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 804 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 805 usbd_xfer_set_frame_data(xfer, 0, data->buf, 806 usbd_xfer_max_len(xfer)); 807 usbd_transfer_submit(xfer); 808 809 /* 810 * To avoid LOR we should unlock our private mutex here to call 811 * ieee80211_input() because here is at the end of a USB 812 * callback and safe to unlock. 813 */ 814 URTWN_UNLOCK(sc); 815 while (m != NULL) { 816 next = m->m_next; 817 m->m_next = NULL; 818 wh = mtod(m, struct ieee80211_frame *); 819 ni = ieee80211_find_rxnode(ic, 820 (struct ieee80211_frame_min *)wh); 821 nf = URTWN_NOISE_FLOOR; 822 if (ni != NULL) { 823 (void)ieee80211_input(ni, m, rssi, nf); 824 ieee80211_free_node(ni); 825 } else 826 (void)ieee80211_input_all(ic, m, rssi, nf); 827 m = next; 828 } 829 URTWN_LOCK(sc); 830 break; 831 default: 832 /* needs it to the inactive queue due to a error. */ 833 data = STAILQ_FIRST(&sc->sc_rx_active); 834 if (data != NULL) { 835 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 836 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 837 } 838 if (error != USB_ERR_CANCELLED) { 839 usbd_xfer_set_stall(xfer); 840 counter_u64_add(ic->ic_ierrors, 1); 841 goto tr_setup; 842 } 843 break; 844 } 845} 846 847static void 848urtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 849{ 850 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 851 852 URTWN_ASSERT_LOCKED(sc); 853 /* XXX status? */ 854 ieee80211_tx_complete(data->ni, data->m, 0); 855 data->ni = NULL; 856 data->m = NULL; 857 sc->sc_txtimer = 0; 858} 859 860static void 861urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 862{ 863 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 864 struct urtwn_data *data; 865 866 URTWN_ASSERT_LOCKED(sc); 867 868 switch (USB_GET_STATE(xfer)){ 869 case USB_ST_TRANSFERRED: 870 data = STAILQ_FIRST(&sc->sc_tx_active); 871 if (data == NULL) 872 goto tr_setup; 873 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 874 urtwn_txeof(xfer, data); 875 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 876 /* FALLTHROUGH */ 877 case USB_ST_SETUP: 878tr_setup: 879 data = STAILQ_FIRST(&sc->sc_tx_pending); 880 if (data == NULL) { 881 DPRINTF("%s: empty pending queue\n", __func__); 882 return; 883 } 884 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 885 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 886 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 887 usbd_transfer_submit(xfer); 888 urtwn_start(sc); 889 break; 890 default: 891 data = STAILQ_FIRST(&sc->sc_tx_active); 892 if (data == NULL) 893 goto tr_setup; 894 if (data->ni != NULL) { 895 if_inc_counter(data->ni->ni_vap->iv_ifp, 896 IFCOUNTER_OERRORS, 1); 897 ieee80211_free_node(data->ni); 898 data->ni = NULL; 899 } 900 if (error != USB_ERR_CANCELLED) { 901 usbd_xfer_set_stall(xfer); 902 goto tr_setup; 903 } 904 break; 905 } 906} 907 908static struct urtwn_data * 909_urtwn_getbuf(struct urtwn_softc *sc) 910{ 911 struct urtwn_data *bf; 912 913 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 914 if (bf != NULL) 915 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 916 else 917 bf = NULL; 918 if (bf == NULL) 919 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 920 return (bf); 921} 922 923static struct urtwn_data * 924urtwn_getbuf(struct urtwn_softc *sc) 925{ 926 struct urtwn_data *bf; 927 928 URTWN_ASSERT_LOCKED(sc); 929 930 bf = _urtwn_getbuf(sc); 931 if (bf == NULL) 932 DPRINTF("%s: stop queue\n", __func__); 933 return (bf); 934} 935 936static int 937urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 938 int len) 939{ 940 usb_device_request_t req; 941 942 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 943 req.bRequest = R92C_REQ_REGS; 944 USETW(req.wValue, addr); 945 USETW(req.wIndex, 0); 946 USETW(req.wLength, len); 947 return (urtwn_do_request(sc, &req, buf)); 948} 949 950static void 951urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 952{ 953 urtwn_write_region_1(sc, addr, &val, 1); 954} 955 956 957static void 958urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 959{ 960 val = htole16(val); 961 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 962} 963 964static void 965urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 966{ 967 val = htole32(val); 968 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 969} 970 971static int 972urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 973 int len) 974{ 975 usb_device_request_t req; 976 977 req.bmRequestType = UT_READ_VENDOR_DEVICE; 978 req.bRequest = R92C_REQ_REGS; 979 USETW(req.wValue, addr); 980 USETW(req.wIndex, 0); 981 USETW(req.wLength, len); 982 return (urtwn_do_request(sc, &req, buf)); 983} 984 985static uint8_t 986urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 987{ 988 uint8_t val; 989 990 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 991 return (0xff); 992 return (val); 993} 994 995static uint16_t 996urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 997{ 998 uint16_t val; 999 1000 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1001 return (0xffff); 1002 return (le16toh(val)); 1003} 1004 1005static uint32_t 1006urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1007{ 1008 uint32_t val; 1009 1010 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1011 return (0xffffffff); 1012 return (le32toh(val)); 1013} 1014 1015static int 1016urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1017{ 1018 struct r92c_fw_cmd cmd; 1019 int ntries; 1020 1021 /* Wait for current FW box to be empty. */ 1022 for (ntries = 0; ntries < 100; ntries++) { 1023 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1024 break; 1025 urtwn_ms_delay(sc); 1026 } 1027 if (ntries == 100) { 1028 device_printf(sc->sc_dev, 1029 "could not send firmware command\n"); 1030 return (ETIMEDOUT); 1031 } 1032 memset(&cmd, 0, sizeof(cmd)); 1033 cmd.id = id; 1034 if (len > 3) 1035 cmd.id |= R92C_CMD_FLAG_EXT; 1036 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1037 memcpy(cmd.msg, buf, len); 1038 1039 /* Write the first word last since that will trigger the FW. */ 1040 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1041 (uint8_t *)&cmd + 4, 2); 1042 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1043 (uint8_t *)&cmd + 0, 4); 1044 1045 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1046 return (0); 1047} 1048 1049static __inline void 1050urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1051{ 1052 1053 sc->sc_rf_write(sc, chain, addr, val); 1054} 1055 1056static void 1057urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1058 uint32_t val) 1059{ 1060 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1061 SM(R92C_LSSI_PARAM_ADDR, addr) | 1062 SM(R92C_LSSI_PARAM_DATA, val)); 1063} 1064 1065static void 1066urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1067uint32_t val) 1068{ 1069 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1070 SM(R88E_LSSI_PARAM_ADDR, addr) | 1071 SM(R92C_LSSI_PARAM_DATA, val)); 1072} 1073 1074static uint32_t 1075urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1076{ 1077 uint32_t reg[R92C_MAX_CHAINS], val; 1078 1079 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1080 if (chain != 0) 1081 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1082 1083 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1084 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1085 urtwn_ms_delay(sc); 1086 1087 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1088 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1089 R92C_HSSI_PARAM2_READ_EDGE); 1090 urtwn_ms_delay(sc); 1091 1092 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1093 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1094 urtwn_ms_delay(sc); 1095 1096 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1097 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1098 else 1099 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1100 return (MS(val, R92C_LSSI_READBACK_DATA)); 1101} 1102 1103static int 1104urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1105{ 1106 int ntries; 1107 1108 urtwn_write_4(sc, R92C_LLT_INIT, 1109 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1110 SM(R92C_LLT_INIT_ADDR, addr) | 1111 SM(R92C_LLT_INIT_DATA, data)); 1112 /* Wait for write operation to complete. */ 1113 for (ntries = 0; ntries < 20; ntries++) { 1114 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1115 R92C_LLT_INIT_OP_NO_ACTIVE) 1116 return (0); 1117 urtwn_ms_delay(sc); 1118 } 1119 return (ETIMEDOUT); 1120} 1121 1122static uint8_t 1123urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1124{ 1125 uint32_t reg; 1126 int ntries; 1127 1128 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1129 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1130 reg &= ~R92C_EFUSE_CTRL_VALID; 1131 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1132 /* Wait for read operation to complete. */ 1133 for (ntries = 0; ntries < 100; ntries++) { 1134 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1135 if (reg & R92C_EFUSE_CTRL_VALID) 1136 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1137 urtwn_ms_delay(sc); 1138 } 1139 device_printf(sc->sc_dev, 1140 "could not read efuse byte at address 0x%x\n", addr); 1141 return (0xff); 1142} 1143 1144static void 1145urtwn_efuse_read(struct urtwn_softc *sc) 1146{ 1147 uint8_t *rom = (uint8_t *)&sc->rom; 1148 uint16_t addr = 0; 1149 uint32_t reg; 1150 uint8_t off, msk; 1151 int i; 1152 1153 urtwn_efuse_switch_power(sc); 1154 1155 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1156 while (addr < 512) { 1157 reg = urtwn_efuse_read_1(sc, addr); 1158 if (reg == 0xff) 1159 break; 1160 addr++; 1161 off = reg >> 4; 1162 msk = reg & 0xf; 1163 for (i = 0; i < 4; i++) { 1164 if (msk & (1 << i)) 1165 continue; 1166 rom[off * 8 + i * 2 + 0] = 1167 urtwn_efuse_read_1(sc, addr); 1168 addr++; 1169 rom[off * 8 + i * 2 + 1] = 1170 urtwn_efuse_read_1(sc, addr); 1171 addr++; 1172 } 1173 } 1174#ifdef URTWN_DEBUG 1175 if (urtwn_debug >= 2) { 1176 /* Dump ROM content. */ 1177 printf("\n"); 1178 for (i = 0; i < sizeof(sc->rom); i++) 1179 printf("%02x:", rom[i]); 1180 printf("\n"); 1181 } 1182#endif 1183 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1184} 1185 1186static void 1187urtwn_efuse_switch_power(struct urtwn_softc *sc) 1188{ 1189 uint32_t reg; 1190 1191 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1192 1193 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1194 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1195 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1196 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1197 } 1198 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1199 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1200 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1201 reg | R92C_SYS_FUNC_EN_ELDR); 1202 } 1203 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1204 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1205 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1206 urtwn_write_2(sc, R92C_SYS_CLKR, 1207 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1208 } 1209} 1210 1211static int 1212urtwn_read_chipid(struct urtwn_softc *sc) 1213{ 1214 uint32_t reg; 1215 1216 if (sc->chip & URTWN_CHIP_88E) 1217 return (0); 1218 1219 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1220 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1221 return (EIO); 1222 1223 if (reg & R92C_SYS_CFG_TYPE_92C) { 1224 sc->chip |= URTWN_CHIP_92C; 1225 /* Check if it is a castrated 8192C. */ 1226 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1227 R92C_HPON_FSM_CHIP_BONDING_ID) == 1228 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1229 sc->chip |= URTWN_CHIP_92C_1T2R; 1230 } 1231 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1232 sc->chip |= URTWN_CHIP_UMC; 1233 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1234 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1235 } 1236 return (0); 1237} 1238 1239static void 1240urtwn_read_rom(struct urtwn_softc *sc) 1241{ 1242 struct r92c_rom *rom = &sc->rom; 1243 1244 /* Read full ROM image. */ 1245 urtwn_efuse_read(sc); 1246 1247 /* XXX Weird but this is what the vendor driver does. */ 1248 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1249 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1250 1251 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1252 1253 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1254 DPRINTF("regulatory type=%d\n", sc->regulatory); 1255 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1256 1257 sc->sc_rf_write = urtwn_r92c_rf_write; 1258 sc->sc_power_on = urtwn_r92c_power_on; 1259 sc->sc_dma_init = urtwn_r92c_dma_init; 1260} 1261 1262static void 1263urtwn_r88e_read_rom(struct urtwn_softc *sc) 1264{ 1265 uint8_t *rom = sc->r88e_rom; 1266 uint16_t addr = 0; 1267 uint32_t reg; 1268 uint8_t off, msk, tmp; 1269 int i; 1270 1271 off = 0; 1272 urtwn_efuse_switch_power(sc); 1273 1274 /* Read full ROM image. */ 1275 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1276 while (addr < 512) { 1277 reg = urtwn_efuse_read_1(sc, addr); 1278 if (reg == 0xff) 1279 break; 1280 addr++; 1281 if ((reg & 0x1f) == 0x0f) { 1282 tmp = (reg & 0xe0) >> 5; 1283 reg = urtwn_efuse_read_1(sc, addr); 1284 if ((reg & 0x0f) != 0x0f) 1285 off = ((reg & 0xf0) >> 1) | tmp; 1286 addr++; 1287 } else 1288 off = reg >> 4; 1289 msk = reg & 0xf; 1290 for (i = 0; i < 4; i++) { 1291 if (msk & (1 << i)) 1292 continue; 1293 rom[off * 8 + i * 2 + 0] = 1294 urtwn_efuse_read_1(sc, addr); 1295 addr++; 1296 rom[off * 8 + i * 2 + 1] = 1297 urtwn_efuse_read_1(sc, addr); 1298 addr++; 1299 } 1300 } 1301 1302 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1303 1304 addr = 0x10; 1305 for (i = 0; i < 6; i++) 1306 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1307 for (i = 0; i < 5; i++) 1308 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1309 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1310 if (sc->bw20_tx_pwr_diff & 0x08) 1311 sc->bw20_tx_pwr_diff |= 0xf0; 1312 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1313 if (sc->ofdm_tx_pwr_diff & 0x08) 1314 sc->ofdm_tx_pwr_diff |= 0xf0; 1315 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1316 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &sc->r88e_rom[0xd7]); 1317 1318 sc->sc_rf_write = urtwn_r88e_rf_write; 1319 sc->sc_power_on = urtwn_r88e_power_on; 1320 sc->sc_dma_init = urtwn_r88e_dma_init; 1321} 1322 1323/* 1324 * Initialize rate adaptation in firmware. 1325 */ 1326static int 1327urtwn_ra_init(struct urtwn_softc *sc) 1328{ 1329 static const uint8_t map[] = 1330 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1331 struct ieee80211com *ic = &sc->sc_ic; 1332 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1333 struct ieee80211_node *ni; 1334 struct ieee80211_rateset *rs; 1335 struct r92c_fw_cmd_macid_cfg cmd; 1336 uint32_t rates, basicrates; 1337 uint8_t mode; 1338 int maxrate, maxbasicrate, error, i, j; 1339 1340 ni = ieee80211_ref_node(vap->iv_bss); 1341 rs = &ni->ni_rates; 1342 1343 /* Get normal and basic rates mask. */ 1344 rates = basicrates = 0; 1345 maxrate = maxbasicrate = 0; 1346 for (i = 0; i < rs->rs_nrates; i++) { 1347 /* Convert 802.11 rate to HW rate index. */ 1348 for (j = 0; j < nitems(map); j++) 1349 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1350 break; 1351 if (j == nitems(map)) /* Unknown rate, skip. */ 1352 continue; 1353 rates |= 1 << j; 1354 if (j > maxrate) 1355 maxrate = j; 1356 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1357 basicrates |= 1 << j; 1358 if (j > maxbasicrate) 1359 maxbasicrate = j; 1360 } 1361 } 1362 if (ic->ic_curmode == IEEE80211_MODE_11B) 1363 mode = R92C_RAID_11B; 1364 else 1365 mode = R92C_RAID_11BG; 1366 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1367 mode, rates, basicrates); 1368 1369 /* Set rates mask for group addressed frames. */ 1370 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1371 cmd.mask = htole32(mode << 28 | basicrates); 1372 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1373 if (error != 0) { 1374 ieee80211_free_node(ni); 1375 device_printf(sc->sc_dev, 1376 "could not add broadcast station\n"); 1377 return (error); 1378 } 1379 /* Set initial MRR rate. */ 1380 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1381 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1382 maxbasicrate); 1383 1384 /* Set rates mask for unicast frames. */ 1385 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1386 cmd.mask = htole32(mode << 28 | rates); 1387 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1388 if (error != 0) { 1389 ieee80211_free_node(ni); 1390 device_printf(sc->sc_dev, "could not add BSS station\n"); 1391 return (error); 1392 } 1393 /* Set initial MRR rate. */ 1394 DPRINTF("maxrate=%d\n", maxrate); 1395 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1396 maxrate); 1397 1398 /* Indicate highest supported rate. */ 1399 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1400 ieee80211_free_node(ni); 1401 1402 return (0); 1403} 1404 1405void 1406urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1407{ 1408 struct ieee80211com *ic = &sc->sc_ic; 1409 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1410 struct ieee80211_node *ni = vap->iv_bss; 1411 1412 uint64_t tsf; 1413 1414 /* Enable TSF synchronization. */ 1415 urtwn_write_1(sc, R92C_BCN_CTRL, 1416 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1417 1418 urtwn_write_1(sc, R92C_BCN_CTRL, 1419 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1420 1421 /* Set initial TSF. */ 1422 memcpy(&tsf, ni->ni_tstamp.data, 8); 1423 tsf = le64toh(tsf); 1424 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1425 tsf -= IEEE80211_DUR_TU; 1426 urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1427 urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1428 1429 urtwn_write_1(sc, R92C_BCN_CTRL, 1430 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1431} 1432 1433static void 1434urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1435{ 1436 uint8_t reg; 1437 1438 if (led == URTWN_LED_LINK) { 1439 if (sc->chip & URTWN_CHIP_88E) { 1440 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1441 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1442 if (!on) { 1443 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1444 urtwn_write_1(sc, R92C_LEDCFG2, 1445 reg | R92C_LEDCFG0_DIS); 1446 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1447 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1448 0xfe); 1449 } 1450 } else { 1451 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1452 if (!on) 1453 reg |= R92C_LEDCFG0_DIS; 1454 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1455 } 1456 sc->ledlink = on; /* Save LED state. */ 1457 } 1458} 1459 1460static int 1461urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1462{ 1463 struct urtwn_vap *uvp = URTWN_VAP(vap); 1464 struct ieee80211com *ic = vap->iv_ic; 1465 struct urtwn_softc *sc = ic->ic_softc; 1466 struct ieee80211_node *ni; 1467 enum ieee80211_state ostate; 1468 uint32_t reg; 1469 1470 ostate = vap->iv_state; 1471 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1472 ieee80211_state_name[nstate]); 1473 1474 IEEE80211_UNLOCK(ic); 1475 URTWN_LOCK(sc); 1476 callout_stop(&sc->sc_watchdog_ch); 1477 1478 if (ostate == IEEE80211_S_RUN) { 1479 /* Turn link LED off. */ 1480 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1481 1482 /* Set media status to 'No Link'. */ 1483 reg = urtwn_read_4(sc, R92C_CR); 1484 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1485 urtwn_write_4(sc, R92C_CR, reg); 1486 1487 /* Stop Rx of data frames. */ 1488 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1489 1490 /* Rest TSF. */ 1491 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1492 1493 /* Disable TSF synchronization. */ 1494 urtwn_write_1(sc, R92C_BCN_CTRL, 1495 urtwn_read_1(sc, R92C_BCN_CTRL) | 1496 R92C_BCN_CTRL_DIS_TSF_UDT0); 1497 1498 /* Reset EDCA parameters. */ 1499 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1500 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1501 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1502 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1503 } 1504 1505 switch (nstate) { 1506 case IEEE80211_S_INIT: 1507 /* Turn link LED off. */ 1508 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1509 break; 1510 case IEEE80211_S_SCAN: 1511 if (ostate != IEEE80211_S_SCAN) { 1512 /* Allow Rx from any BSSID. */ 1513 urtwn_write_4(sc, R92C_RCR, 1514 urtwn_read_4(sc, R92C_RCR) & 1515 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1516 1517 /* Set gain for scanning. */ 1518 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1519 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1520 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1521 1522 if (!(sc->chip & URTWN_CHIP_88E)) { 1523 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1524 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1525 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1526 } 1527 } 1528 /* Pause AC Tx queues. */ 1529 urtwn_write_1(sc, R92C_TXPAUSE, 1530 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1531 break; 1532 case IEEE80211_S_AUTH: 1533 /* Set initial gain under link. */ 1534 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1535 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1536 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1537 1538 if (!(sc->chip & URTWN_CHIP_88E)) { 1539 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1540 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1541 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1542 } 1543 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1544 break; 1545 case IEEE80211_S_RUN: 1546 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1547 /* Enable Rx of data frames. */ 1548 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1549 1550 /* Turn link LED on. */ 1551 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1552 break; 1553 } 1554 1555 ni = ieee80211_ref_node(vap->iv_bss); 1556 /* Set media status to 'Associated'. */ 1557 reg = urtwn_read_4(sc, R92C_CR); 1558 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1559 urtwn_write_4(sc, R92C_CR, reg); 1560 1561 /* Set BSSID. */ 1562 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1563 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1564 1565 if (ic->ic_curmode == IEEE80211_MODE_11B) 1566 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1567 else /* 802.11b/g */ 1568 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1569 1570 /* Enable Rx of data frames. */ 1571 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1572 1573 /* Flush all AC queues. */ 1574 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1575 1576 /* Set beacon interval. */ 1577 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1578 1579 /* Allow Rx from our BSSID only. */ 1580 urtwn_write_4(sc, R92C_RCR, 1581 urtwn_read_4(sc, R92C_RCR) | 1582 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1583 1584 /* Enable TSF synchronization. */ 1585 urtwn_tsf_sync_enable(sc); 1586 1587 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1588 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1589 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1590 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1591 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1592 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1593 1594 /* Intialize rate adaptation. */ 1595 if (sc->chip & URTWN_CHIP_88E) 1596 ni->ni_txrate = 1597 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1598 else 1599 urtwn_ra_init(sc); 1600 /* Turn link LED on. */ 1601 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1602 1603 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1604 /* Reset temperature calibration state machine. */ 1605 sc->thcal_state = 0; 1606 sc->thcal_lctemp = 0; 1607 ieee80211_free_node(ni); 1608 break; 1609 default: 1610 break; 1611 } 1612 URTWN_UNLOCK(sc); 1613 IEEE80211_LOCK(ic); 1614 return(uvp->newstate(vap, nstate, arg)); 1615} 1616 1617static void 1618urtwn_watchdog(void *arg) 1619{ 1620 struct urtwn_softc *sc = arg; 1621 1622 if (sc->sc_txtimer > 0) { 1623 if (--sc->sc_txtimer == 0) { 1624 device_printf(sc->sc_dev, "device timeout\n"); 1625 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1626 return; 1627 } 1628 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1629 } 1630} 1631 1632static void 1633urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1634{ 1635 int pwdb; 1636 1637 /* Convert antenna signal to percentage. */ 1638 if (rssi <= -100 || rssi >= 20) 1639 pwdb = 0; 1640 else if (rssi >= 0) 1641 pwdb = 100; 1642 else 1643 pwdb = 100 + rssi; 1644 if (!(sc->chip & URTWN_CHIP_88E)) { 1645 if (rate <= 3) { 1646 /* CCK gain is smaller than OFDM/MCS gain. */ 1647 pwdb += 6; 1648 if (pwdb > 100) 1649 pwdb = 100; 1650 if (pwdb <= 14) 1651 pwdb -= 4; 1652 else if (pwdb <= 26) 1653 pwdb -= 8; 1654 else if (pwdb <= 34) 1655 pwdb -= 6; 1656 else if (pwdb <= 42) 1657 pwdb -= 2; 1658 } 1659 } 1660 if (sc->avg_pwdb == -1) /* Init. */ 1661 sc->avg_pwdb = pwdb; 1662 else if (sc->avg_pwdb < pwdb) 1663 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1664 else 1665 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1666 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1667} 1668 1669static int8_t 1670urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1671{ 1672 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1673 struct r92c_rx_phystat *phy; 1674 struct r92c_rx_cck *cck; 1675 uint8_t rpt; 1676 int8_t rssi; 1677 1678 if (rate <= 3) { 1679 cck = (struct r92c_rx_cck *)physt; 1680 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1681 rpt = (cck->agc_rpt >> 5) & 0x3; 1682 rssi = (cck->agc_rpt & 0x1f) << 1; 1683 } else { 1684 rpt = (cck->agc_rpt >> 6) & 0x3; 1685 rssi = cck->agc_rpt & 0x3e; 1686 } 1687 rssi = cckoff[rpt] - rssi; 1688 } else { /* OFDM/HT. */ 1689 phy = (struct r92c_rx_phystat *)physt; 1690 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1691 } 1692 return (rssi); 1693} 1694 1695static int8_t 1696urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1697{ 1698 struct r92c_rx_phystat *phy; 1699 struct r88e_rx_cck *cck; 1700 uint8_t cck_agc_rpt, lna_idx, vga_idx; 1701 int8_t rssi; 1702 1703 rssi = 0; 1704 if (rate <= 3) { 1705 cck = (struct r88e_rx_cck *)physt; 1706 cck_agc_rpt = cck->agc_rpt; 1707 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1708 vga_idx = cck_agc_rpt & 0x1f; 1709 switch (lna_idx) { 1710 case 7: 1711 if (vga_idx <= 27) 1712 rssi = -100 + 2* (27 - vga_idx); 1713 else 1714 rssi = -100; 1715 break; 1716 case 6: 1717 rssi = -48 + 2 * (2 - vga_idx); 1718 break; 1719 case 5: 1720 rssi = -42 + 2 * (7 - vga_idx); 1721 break; 1722 case 4: 1723 rssi = -36 + 2 * (7 - vga_idx); 1724 break; 1725 case 3: 1726 rssi = -24 + 2 * (7 - vga_idx); 1727 break; 1728 case 2: 1729 rssi = -12 + 2 * (5 - vga_idx); 1730 break; 1731 case 1: 1732 rssi = 8 - (2 * vga_idx); 1733 break; 1734 case 0: 1735 rssi = 14 - (2 * vga_idx); 1736 break; 1737 } 1738 rssi += 6; 1739 } else { /* OFDM/HT. */ 1740 phy = (struct r92c_rx_phystat *)physt; 1741 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1742 } 1743 return (rssi); 1744} 1745 1746 1747static int 1748urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1749 struct mbuf *m0, struct urtwn_data *data) 1750{ 1751 struct ieee80211_frame *wh; 1752 struct ieee80211_key *k; 1753 struct ieee80211com *ic = &sc->sc_ic; 1754 struct ieee80211vap *vap = ni->ni_vap; 1755 struct usb_xfer *xfer; 1756 struct r92c_tx_desc *txd; 1757 uint8_t raid, type; 1758 uint16_t sum; 1759 int i, hasqos, xferlen; 1760 struct usb_xfer *urtwn_pipes[4] = { 1761 sc->sc_xfer[URTWN_BULK_TX_BE], 1762 sc->sc_xfer[URTWN_BULK_TX_BK], 1763 sc->sc_xfer[URTWN_BULK_TX_VI], 1764 sc->sc_xfer[URTWN_BULK_TX_VO] 1765 }; 1766 1767 URTWN_ASSERT_LOCKED(sc); 1768 1769 /* 1770 * Software crypto. 1771 */ 1772 wh = mtod(m0, struct ieee80211_frame *); 1773 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1774 1775 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1776 k = ieee80211_crypto_encap(ni, m0); 1777 if (k == NULL) { 1778 device_printf(sc->sc_dev, 1779 "ieee80211_crypto_encap returns NULL.\n"); 1780 /* XXX we don't expect the fragmented frames */ 1781 m_freem(m0); 1782 return (ENOBUFS); 1783 } 1784 1785 /* in case packet header moved, reset pointer */ 1786 wh = mtod(m0, struct ieee80211_frame *); 1787 } 1788 1789 switch (type) { 1790 case IEEE80211_FC0_TYPE_CTL: 1791 case IEEE80211_FC0_TYPE_MGT: 1792 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1793 break; 1794 default: 1795 KASSERT(M_WME_GETAC(m0) < 4, 1796 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1797 xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1798 break; 1799 } 1800 1801 hasqos = 0; 1802 1803 /* Fill Tx descriptor. */ 1804 txd = (struct r92c_tx_desc *)data->buf; 1805 memset(txd, 0, sizeof(*txd)); 1806 1807 txd->txdw0 |= htole32( 1808 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1809 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1810 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1811 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1812 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1813 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1814 type == IEEE80211_FC0_TYPE_DATA) { 1815 if (ic->ic_curmode == IEEE80211_MODE_11B) 1816 raid = R92C_RAID_11B; 1817 else 1818 raid = R92C_RAID_11BG; 1819 if (sc->chip & URTWN_CHIP_88E) { 1820 txd->txdw1 |= htole32( 1821 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1822 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1823 SM(R92C_TXDW1_RAID, raid)); 1824 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1825 } else { 1826 txd->txdw1 |= htole32( 1827 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1828 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1829 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1830 } 1831 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1832 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1833 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1834 R92C_TXDW4_HWRTSEN); 1835 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1836 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1837 R92C_TXDW4_HWRTSEN); 1838 } 1839 } 1840 /* Send RTS at OFDM24. */ 1841 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1842 txd->txdw5 |= htole32(0x0001ff00); 1843 /* Send data at OFDM54. */ 1844 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1845 } else { 1846 txd->txdw1 |= htole32( 1847 SM(R92C_TXDW1_MACID, 0) | 1848 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1849 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1850 1851 /* Force CCK1. */ 1852 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1853 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1854 } 1855 /* Set sequence number (already little endian). */ 1856 txd->txdseq |= *(uint16_t *)wh->i_seq; 1857 1858 if (!hasqos) { 1859 /* Use HW sequence numbering for non-QoS frames. */ 1860 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1861 txd->txdseq |= htole16(0x8000); 1862 } else 1863 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1864 1865 /* Compute Tx descriptor checksum. */ 1866 sum = 0; 1867 for (i = 0; i < sizeof(*txd) / 2; i++) 1868 sum ^= ((uint16_t *)txd)[i]; 1869 txd->txdsum = sum; /* NB: already little endian. */ 1870 1871 if (ieee80211_radiotap_active_vap(vap)) { 1872 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1873 1874 tap->wt_flags = 0; 1875 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1876 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1877 ieee80211_radiotap_tx(vap, m0); 1878 } 1879 1880 xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1881 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1882 1883 data->buflen = xferlen; 1884 data->ni = ni; 1885 data->m = m0; 1886 1887 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1888 usbd_transfer_start(xfer); 1889 return (0); 1890} 1891 1892static int 1893urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1894{ 1895 struct urtwn_softc *sc = ic->ic_softc; 1896 int error; 1897 1898 URTWN_LOCK(sc); 1899 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1900 URTWN_UNLOCK(sc); 1901 return (ENXIO); 1902 } 1903 error = mbufq_enqueue(&sc->sc_snd, m); 1904 if (error) { 1905 URTWN_UNLOCK(sc); 1906 return (error); 1907 } 1908 urtwn_start(sc); 1909 URTWN_UNLOCK(sc); 1910 1911 return (0); 1912} 1913 1914static void 1915urtwn_start(struct urtwn_softc *sc) 1916{ 1917 struct ieee80211_node *ni; 1918 struct mbuf *m; 1919 struct urtwn_data *bf; 1920 1921 URTWN_ASSERT_LOCKED(sc); 1922 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1923 bf = urtwn_getbuf(sc); 1924 if (bf == NULL) { 1925 mbufq_prepend(&sc->sc_snd, m); 1926 break; 1927 } 1928 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1929 m->m_pkthdr.rcvif = NULL; 1930 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 1931 if_inc_counter(ni->ni_vap->iv_ifp, 1932 IFCOUNTER_OERRORS, 1); 1933 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1934 ieee80211_free_node(ni); 1935 break; 1936 } 1937 sc->sc_txtimer = 5; 1938 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1939 } 1940} 1941 1942static void 1943urtwn_parent(struct ieee80211com *ic) 1944{ 1945 struct urtwn_softc *sc = ic->ic_softc; 1946 int startall = 0; 1947 1948 URTWN_LOCK(sc); 1949 if (sc->sc_flags & URTWN_DETACHED) { 1950 URTWN_UNLOCK(sc); 1951 return; 1952 } 1953 if (ic->ic_nrunning > 0) { 1954 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1955 urtwn_init(sc); 1956 startall = 1; 1957 } 1958 } else if (sc->sc_flags & URTWN_RUNNING) 1959 urtwn_stop(sc); 1960 URTWN_UNLOCK(sc); 1961 1962 if (startall) 1963 ieee80211_start_all(ic); 1964} 1965 1966static int 1967urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1968 int ndata, int maxsz) 1969{ 1970 int i, error; 1971 1972 for (i = 0; i < ndata; i++) { 1973 struct urtwn_data *dp = &data[i]; 1974 dp->sc = sc; 1975 dp->m = NULL; 1976 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1977 if (dp->buf == NULL) { 1978 device_printf(sc->sc_dev, 1979 "could not allocate buffer\n"); 1980 error = ENOMEM; 1981 goto fail; 1982 } 1983 dp->ni = NULL; 1984 } 1985 1986 return (0); 1987fail: 1988 urtwn_free_list(sc, data, ndata); 1989 return (error); 1990} 1991 1992static int 1993urtwn_alloc_rx_list(struct urtwn_softc *sc) 1994{ 1995 int error, i; 1996 1997 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1998 URTWN_RXBUFSZ); 1999 if (error != 0) 2000 return (error); 2001 2002 STAILQ_INIT(&sc->sc_rx_active); 2003 STAILQ_INIT(&sc->sc_rx_inactive); 2004 2005 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 2006 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 2007 2008 return (0); 2009} 2010 2011static int 2012urtwn_alloc_tx_list(struct urtwn_softc *sc) 2013{ 2014 int error, i; 2015 2016 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 2017 URTWN_TXBUFSZ); 2018 if (error != 0) 2019 return (error); 2020 2021 STAILQ_INIT(&sc->sc_tx_active); 2022 STAILQ_INIT(&sc->sc_tx_inactive); 2023 STAILQ_INIT(&sc->sc_tx_pending); 2024 2025 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 2026 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 2027 2028 return (0); 2029} 2030 2031static __inline int 2032urtwn_power_on(struct urtwn_softc *sc) 2033{ 2034 2035 return sc->sc_power_on(sc); 2036} 2037 2038static int 2039urtwn_r92c_power_on(struct urtwn_softc *sc) 2040{ 2041 uint32_t reg; 2042 int ntries; 2043 2044 /* Wait for autoload done bit. */ 2045 for (ntries = 0; ntries < 1000; ntries++) { 2046 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2047 break; 2048 urtwn_ms_delay(sc); 2049 } 2050 if (ntries == 1000) { 2051 device_printf(sc->sc_dev, 2052 "timeout waiting for chip autoload\n"); 2053 return (ETIMEDOUT); 2054 } 2055 2056 /* Unlock ISO/CLK/Power control register. */ 2057 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2058 /* Move SPS into PWM mode. */ 2059 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2060 urtwn_ms_delay(sc); 2061 2062 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2063 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2064 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2065 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2066 urtwn_ms_delay(sc); 2067 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2068 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2069 ~R92C_SYS_ISO_CTRL_MD2PP); 2070 } 2071 2072 /* Auto enable WLAN. */ 2073 urtwn_write_2(sc, R92C_APS_FSMCO, 2074 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2075 for (ntries = 0; ntries < 1000; ntries++) { 2076 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2077 R92C_APS_FSMCO_APFM_ONMAC)) 2078 break; 2079 urtwn_ms_delay(sc); 2080 } 2081 if (ntries == 1000) { 2082 device_printf(sc->sc_dev, 2083 "timeout waiting for MAC auto ON\n"); 2084 return (ETIMEDOUT); 2085 } 2086 2087 /* Enable radio, GPIO and LED functions. */ 2088 urtwn_write_2(sc, R92C_APS_FSMCO, 2089 R92C_APS_FSMCO_AFSM_HSUS | 2090 R92C_APS_FSMCO_PDN_EN | 2091 R92C_APS_FSMCO_PFM_ALDN); 2092 /* Release RF digital isolation. */ 2093 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2094 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2095 2096 /* Initialize MAC. */ 2097 urtwn_write_1(sc, R92C_APSD_CTRL, 2098 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2099 for (ntries = 0; ntries < 200; ntries++) { 2100 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2101 R92C_APSD_CTRL_OFF_STATUS)) 2102 break; 2103 urtwn_ms_delay(sc); 2104 } 2105 if (ntries == 200) { 2106 device_printf(sc->sc_dev, 2107 "timeout waiting for MAC initialization\n"); 2108 return (ETIMEDOUT); 2109 } 2110 2111 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2112 reg = urtwn_read_2(sc, R92C_CR); 2113 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2114 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2115 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2116 R92C_CR_ENSEC; 2117 urtwn_write_2(sc, R92C_CR, reg); 2118 2119 urtwn_write_1(sc, 0xfe10, 0x19); 2120 return (0); 2121} 2122 2123static int 2124urtwn_r88e_power_on(struct urtwn_softc *sc) 2125{ 2126 uint32_t reg; 2127 int ntries; 2128 2129 /* Wait for power ready bit. */ 2130 for (ntries = 0; ntries < 5000; ntries++) { 2131 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2132 break; 2133 urtwn_ms_delay(sc); 2134 } 2135 if (ntries == 5000) { 2136 device_printf(sc->sc_dev, 2137 "timeout waiting for chip power up\n"); 2138 return (ETIMEDOUT); 2139 } 2140 2141 /* Reset BB. */ 2142 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2143 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2144 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2145 2146 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2147 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2148 2149 /* Disable HWPDN. */ 2150 urtwn_write_2(sc, R92C_APS_FSMCO, 2151 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2152 2153 /* Disable WL suspend. */ 2154 urtwn_write_2(sc, R92C_APS_FSMCO, 2155 urtwn_read_2(sc, R92C_APS_FSMCO) & 2156 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2157 2158 urtwn_write_2(sc, R92C_APS_FSMCO, 2159 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2160 for (ntries = 0; ntries < 5000; ntries++) { 2161 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2162 R92C_APS_FSMCO_APFM_ONMAC)) 2163 break; 2164 urtwn_ms_delay(sc); 2165 } 2166 if (ntries == 5000) 2167 return (ETIMEDOUT); 2168 2169 /* Enable LDO normal mode. */ 2170 urtwn_write_1(sc, R92C_LPLDO_CTRL, 2171 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2172 2173 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2174 urtwn_write_2(sc, R92C_CR, 0); 2175 reg = urtwn_read_2(sc, R92C_CR); 2176 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2177 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2178 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2179 urtwn_write_2(sc, R92C_CR, reg); 2180 2181 return (0); 2182} 2183 2184static int 2185urtwn_llt_init(struct urtwn_softc *sc) 2186{ 2187 int i, error, page_count, pktbuf_count; 2188 2189 page_count = (sc->chip & URTWN_CHIP_88E) ? 2190 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2191 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2192 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2193 2194 /* Reserve pages [0; page_count]. */ 2195 for (i = 0; i < page_count; i++) { 2196 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2197 return (error); 2198 } 2199 /* NB: 0xff indicates end-of-list. */ 2200 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2201 return (error); 2202 /* 2203 * Use pages [page_count + 1; pktbuf_count - 1] 2204 * as ring buffer. 2205 */ 2206 for (++i; i < pktbuf_count - 1; i++) { 2207 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2208 return (error); 2209 } 2210 /* Make the last page point to the beginning of the ring buffer. */ 2211 error = urtwn_llt_write(sc, i, page_count + 1); 2212 return (error); 2213} 2214 2215static void 2216urtwn_fw_reset(struct urtwn_softc *sc) 2217{ 2218 uint16_t reg; 2219 int ntries; 2220 2221 /* Tell 8051 to reset itself. */ 2222 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2223 2224 /* Wait until 8051 resets by itself. */ 2225 for (ntries = 0; ntries < 100; ntries++) { 2226 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2227 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2228 return; 2229 urtwn_ms_delay(sc); 2230 } 2231 /* Force 8051 reset. */ 2232 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2233} 2234 2235static void 2236urtwn_r88e_fw_reset(struct urtwn_softc *sc) 2237{ 2238 uint16_t reg; 2239 2240 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2241 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2242 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2243} 2244 2245static int 2246urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2247{ 2248 uint32_t reg; 2249 int off, mlen, error = 0; 2250 2251 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2252 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2253 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2254 2255 off = R92C_FW_START_ADDR; 2256 while (len > 0) { 2257 if (len > 196) 2258 mlen = 196; 2259 else if (len > 4) 2260 mlen = 4; 2261 else 2262 mlen = 1; 2263 /* XXX fix this deconst */ 2264 error = urtwn_write_region_1(sc, off, 2265 __DECONST(uint8_t *, buf), mlen); 2266 if (error != 0) 2267 break; 2268 off += mlen; 2269 buf += mlen; 2270 len -= mlen; 2271 } 2272 return (error); 2273} 2274 2275static int 2276urtwn_load_firmware(struct urtwn_softc *sc) 2277{ 2278 const struct firmware *fw; 2279 const struct r92c_fw_hdr *hdr; 2280 const char *imagename; 2281 const u_char *ptr; 2282 size_t len; 2283 uint32_t reg; 2284 int mlen, ntries, page, error; 2285 2286 URTWN_UNLOCK(sc); 2287 /* Read firmware image from the filesystem. */ 2288 if (sc->chip & URTWN_CHIP_88E) 2289 imagename = "urtwn-rtl8188eufw"; 2290 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2291 URTWN_CHIP_UMC_A_CUT) 2292 imagename = "urtwn-rtl8192cfwU"; 2293 else 2294 imagename = "urtwn-rtl8192cfwT"; 2295 2296 fw = firmware_get(imagename); 2297 URTWN_LOCK(sc); 2298 if (fw == NULL) { 2299 device_printf(sc->sc_dev, 2300 "failed loadfirmware of file %s\n", imagename); 2301 return (ENOENT); 2302 } 2303 2304 len = fw->datasize; 2305 2306 if (len < sizeof(*hdr)) { 2307 device_printf(sc->sc_dev, "firmware too short\n"); 2308 error = EINVAL; 2309 goto fail; 2310 } 2311 ptr = fw->data; 2312 hdr = (const struct r92c_fw_hdr *)ptr; 2313 /* Check if there is a valid FW header and skip it. */ 2314 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2315 (le16toh(hdr->signature) >> 4) == 0x88e || 2316 (le16toh(hdr->signature) >> 4) == 0x92c) { 2317 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2318 le16toh(hdr->version), le16toh(hdr->subversion), 2319 hdr->month, hdr->date, hdr->hour, hdr->minute); 2320 ptr += sizeof(*hdr); 2321 len -= sizeof(*hdr); 2322 } 2323 2324 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2325 if (sc->chip & URTWN_CHIP_88E) 2326 urtwn_r88e_fw_reset(sc); 2327 else 2328 urtwn_fw_reset(sc); 2329 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2330 } 2331 2332 if (!(sc->chip & URTWN_CHIP_88E)) { 2333 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2334 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2335 R92C_SYS_FUNC_EN_CPUEN); 2336 } 2337 urtwn_write_1(sc, R92C_MCUFWDL, 2338 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2339 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2340 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2341 2342 /* Reset the FWDL checksum. */ 2343 urtwn_write_1(sc, R92C_MCUFWDL, 2344 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2345 2346 for (page = 0; len > 0; page++) { 2347 mlen = min(len, R92C_FW_PAGE_SIZE); 2348 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2349 if (error != 0) { 2350 device_printf(sc->sc_dev, 2351 "could not load firmware page\n"); 2352 goto fail; 2353 } 2354 ptr += mlen; 2355 len -= mlen; 2356 } 2357 urtwn_write_1(sc, R92C_MCUFWDL, 2358 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2359 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2360 2361 /* Wait for checksum report. */ 2362 for (ntries = 0; ntries < 1000; ntries++) { 2363 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2364 break; 2365 urtwn_ms_delay(sc); 2366 } 2367 if (ntries == 1000) { 2368 device_printf(sc->sc_dev, 2369 "timeout waiting for checksum report\n"); 2370 error = ETIMEDOUT; 2371 goto fail; 2372 } 2373 2374 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2375 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2376 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2377 if (sc->chip & URTWN_CHIP_88E) 2378 urtwn_r88e_fw_reset(sc); 2379 /* Wait for firmware readiness. */ 2380 for (ntries = 0; ntries < 1000; ntries++) { 2381 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2382 break; 2383 urtwn_ms_delay(sc); 2384 } 2385 if (ntries == 1000) { 2386 device_printf(sc->sc_dev, 2387 "timeout waiting for firmware readiness\n"); 2388 error = ETIMEDOUT; 2389 goto fail; 2390 } 2391fail: 2392 firmware_put(fw, FIRMWARE_UNLOAD); 2393 return (error); 2394} 2395 2396static __inline int 2397urtwn_dma_init(struct urtwn_softc *sc) 2398{ 2399 2400 return sc->sc_dma_init(sc); 2401} 2402 2403static int 2404urtwn_r92c_dma_init(struct urtwn_softc *sc) 2405{ 2406 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2407 uint32_t reg; 2408 int error; 2409 2410 /* Initialize LLT table. */ 2411 error = urtwn_llt_init(sc); 2412 if (error != 0) 2413 return (error); 2414 2415 /* Get Tx queues to USB endpoints mapping. */ 2416 hashq = hasnq = haslq = 0; 2417 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2418 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2419 if (MS(reg, R92C_USB_EP_HQ) != 0) 2420 hashq = 1; 2421 if (MS(reg, R92C_USB_EP_NQ) != 0) 2422 hasnq = 1; 2423 if (MS(reg, R92C_USB_EP_LQ) != 0) 2424 haslq = 1; 2425 nqueues = hashq + hasnq + haslq; 2426 if (nqueues == 0) 2427 return (EIO); 2428 /* Get the number of pages for each queue. */ 2429 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2430 /* The remaining pages are assigned to the high priority queue. */ 2431 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2432 2433 /* Set number of pages for normal priority queue. */ 2434 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2435 urtwn_write_4(sc, R92C_RQPN, 2436 /* Set number of pages for public queue. */ 2437 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2438 /* Set number of pages for high priority queue. */ 2439 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2440 /* Set number of pages for low priority queue. */ 2441 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2442 /* Load values. */ 2443 R92C_RQPN_LD); 2444 2445 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2446 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2447 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2448 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2449 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2450 2451 /* Set queue to USB pipe mapping. */ 2452 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2453 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2454 if (nqueues == 1) { 2455 if (hashq) 2456 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2457 else if (hasnq) 2458 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2459 else 2460 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2461 } else if (nqueues == 2) { 2462 /* All 2-endpoints configs have a high priority queue. */ 2463 if (!hashq) 2464 return (EIO); 2465 if (hasnq) 2466 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2467 else 2468 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2469 } else 2470 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2471 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2472 2473 /* Set Tx/Rx transfer page boundary. */ 2474 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2475 2476 /* Set Tx/Rx transfer page size. */ 2477 urtwn_write_1(sc, R92C_PBP, 2478 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2479 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2480 return (0); 2481} 2482 2483static int 2484urtwn_r88e_dma_init(struct urtwn_softc *sc) 2485{ 2486 struct usb_interface *iface; 2487 uint32_t reg; 2488 int nqueues; 2489 int error; 2490 2491 /* Initialize LLT table. */ 2492 error = urtwn_llt_init(sc); 2493 if (error != 0) 2494 return (error); 2495 2496 /* Get Tx queues to USB endpoints mapping. */ 2497 iface = usbd_get_iface(sc->sc_udev, 0); 2498 nqueues = iface->idesc->bNumEndpoints - 1; 2499 if (nqueues == 0) 2500 return (EIO); 2501 2502 /* Set number of pages for normal priority queue. */ 2503 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2504 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2505 2506 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2507 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2508 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2509 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2510 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2511 2512 /* Set queue to USB pipe mapping. */ 2513 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2514 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2515 if (nqueues == 1) 2516 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2517 else if (nqueues == 2) 2518 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2519 else 2520 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2521 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2522 2523 /* Set Tx/Rx transfer page boundary. */ 2524 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2525 2526 /* Set Tx/Rx transfer page size. */ 2527 urtwn_write_1(sc, R92C_PBP, 2528 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2529 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2530 2531 return (0); 2532} 2533 2534static void 2535urtwn_mac_init(struct urtwn_softc *sc) 2536{ 2537 int i; 2538 2539 /* Write MAC initialization values. */ 2540 if (sc->chip & URTWN_CHIP_88E) { 2541 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2542 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2543 rtl8188eu_mac[i].val); 2544 } 2545 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2546 } else { 2547 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2548 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2549 rtl8192cu_mac[i].val); 2550 } 2551} 2552 2553static void 2554urtwn_bb_init(struct urtwn_softc *sc) 2555{ 2556 const struct urtwn_bb_prog *prog; 2557 uint32_t reg; 2558 uint8_t crystalcap; 2559 int i; 2560 2561 /* Enable BB and RF. */ 2562 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2563 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2564 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2565 R92C_SYS_FUNC_EN_DIO_RF); 2566 2567 if (!(sc->chip & URTWN_CHIP_88E)) 2568 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2569 2570 urtwn_write_1(sc, R92C_RF_CTRL, 2571 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2572 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2573 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2574 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2575 2576 if (!(sc->chip & URTWN_CHIP_88E)) { 2577 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2578 urtwn_write_1(sc, 0x15, 0xe9); 2579 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2580 } 2581 2582 /* Select BB programming based on board type. */ 2583 if (sc->chip & URTWN_CHIP_88E) 2584 prog = &rtl8188eu_bb_prog; 2585 else if (!(sc->chip & URTWN_CHIP_92C)) { 2586 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2587 prog = &rtl8188ce_bb_prog; 2588 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2589 prog = &rtl8188ru_bb_prog; 2590 else 2591 prog = &rtl8188cu_bb_prog; 2592 } else { 2593 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2594 prog = &rtl8192ce_bb_prog; 2595 else 2596 prog = &rtl8192cu_bb_prog; 2597 } 2598 /* Write BB initialization values. */ 2599 for (i = 0; i < prog->count; i++) { 2600 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2601 urtwn_ms_delay(sc); 2602 } 2603 2604 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2605 /* 8192C 1T only configuration. */ 2606 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2607 reg = (reg & ~0x00000003) | 0x2; 2608 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2609 2610 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2611 reg = (reg & ~0x00300033) | 0x00200022; 2612 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2613 2614 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2615 reg = (reg & ~0xff000000) | 0x45 << 24; 2616 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2617 2618 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2619 reg = (reg & ~0x000000ff) | 0x23; 2620 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2621 2622 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2623 reg = (reg & ~0x00000030) | 1 << 4; 2624 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2625 2626 reg = urtwn_bb_read(sc, 0xe74); 2627 reg = (reg & ~0x0c000000) | 2 << 26; 2628 urtwn_bb_write(sc, 0xe74, reg); 2629 reg = urtwn_bb_read(sc, 0xe78); 2630 reg = (reg & ~0x0c000000) | 2 << 26; 2631 urtwn_bb_write(sc, 0xe78, reg); 2632 reg = urtwn_bb_read(sc, 0xe7c); 2633 reg = (reg & ~0x0c000000) | 2 << 26; 2634 urtwn_bb_write(sc, 0xe7c, reg); 2635 reg = urtwn_bb_read(sc, 0xe80); 2636 reg = (reg & ~0x0c000000) | 2 << 26; 2637 urtwn_bb_write(sc, 0xe80, reg); 2638 reg = urtwn_bb_read(sc, 0xe88); 2639 reg = (reg & ~0x0c000000) | 2 << 26; 2640 urtwn_bb_write(sc, 0xe88, reg); 2641 } 2642 2643 /* Write AGC values. */ 2644 for (i = 0; i < prog->agccount; i++) { 2645 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2646 prog->agcvals[i]); 2647 urtwn_ms_delay(sc); 2648 } 2649 2650 if (sc->chip & URTWN_CHIP_88E) { 2651 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2652 urtwn_ms_delay(sc); 2653 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2654 urtwn_ms_delay(sc); 2655 2656 crystalcap = sc->r88e_rom[0xb9]; 2657 if (crystalcap == 0xff) 2658 crystalcap = 0x20; 2659 crystalcap &= 0x3f; 2660 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2661 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2662 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2663 crystalcap | crystalcap << 6)); 2664 } else { 2665 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2666 R92C_HSSI_PARAM2_CCK_HIPWR) 2667 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2668 } 2669} 2670 2671void 2672urtwn_rf_init(struct urtwn_softc *sc) 2673{ 2674 const struct urtwn_rf_prog *prog; 2675 uint32_t reg, type; 2676 int i, j, idx, off; 2677 2678 /* Select RF programming based on board type. */ 2679 if (sc->chip & URTWN_CHIP_88E) 2680 prog = rtl8188eu_rf_prog; 2681 else if (!(sc->chip & URTWN_CHIP_92C)) { 2682 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2683 prog = rtl8188ce_rf_prog; 2684 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2685 prog = rtl8188ru_rf_prog; 2686 else 2687 prog = rtl8188cu_rf_prog; 2688 } else 2689 prog = rtl8192ce_rf_prog; 2690 2691 for (i = 0; i < sc->nrxchains; i++) { 2692 /* Save RF_ENV control type. */ 2693 idx = i / 2; 2694 off = (i % 2) * 16; 2695 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2696 type = (reg >> off) & 0x10; 2697 2698 /* Set RF_ENV enable. */ 2699 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2700 reg |= 0x100000; 2701 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2702 urtwn_ms_delay(sc); 2703 /* Set RF_ENV output high. */ 2704 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2705 reg |= 0x10; 2706 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2707 urtwn_ms_delay(sc); 2708 /* Set address and data lengths of RF registers. */ 2709 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2710 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2711 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2712 urtwn_ms_delay(sc); 2713 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2714 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2715 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2716 urtwn_ms_delay(sc); 2717 2718 /* Write RF initialization values for this chain. */ 2719 for (j = 0; j < prog[i].count; j++) { 2720 if (prog[i].regs[j] >= 0xf9 && 2721 prog[i].regs[j] <= 0xfe) { 2722 /* 2723 * These are fake RF registers offsets that 2724 * indicate a delay is required. 2725 */ 2726 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2727 continue; 2728 } 2729 urtwn_rf_write(sc, i, prog[i].regs[j], 2730 prog[i].vals[j]); 2731 urtwn_ms_delay(sc); 2732 } 2733 2734 /* Restore RF_ENV control type. */ 2735 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2736 reg &= ~(0x10 << off) | (type << off); 2737 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2738 2739 /* Cache RF register CHNLBW. */ 2740 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2741 } 2742 2743 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2744 URTWN_CHIP_UMC_A_CUT) { 2745 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2746 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2747 } 2748} 2749 2750static void 2751urtwn_cam_init(struct urtwn_softc *sc) 2752{ 2753 /* Invalidate all CAM entries. */ 2754 urtwn_write_4(sc, R92C_CAMCMD, 2755 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2756} 2757 2758static void 2759urtwn_pa_bias_init(struct urtwn_softc *sc) 2760{ 2761 uint8_t reg; 2762 int i; 2763 2764 for (i = 0; i < sc->nrxchains; i++) { 2765 if (sc->pa_setting & (1 << i)) 2766 continue; 2767 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2768 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2769 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2770 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2771 } 2772 if (!(sc->pa_setting & 0x10)) { 2773 reg = urtwn_read_1(sc, 0x16); 2774 reg = (reg & ~0xf0) | 0x90; 2775 urtwn_write_1(sc, 0x16, reg); 2776 } 2777} 2778 2779static void 2780urtwn_rxfilter_init(struct urtwn_softc *sc) 2781{ 2782 /* Initialize Rx filter. */ 2783 /* TODO: use better filter for monitor mode. */ 2784 urtwn_write_4(sc, R92C_RCR, 2785 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2786 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2787 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2788 /* Accept all multicast frames. */ 2789 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2790 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2791 /* Accept all management frames. */ 2792 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2793 /* Reject all control frames. */ 2794 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2795 /* Accept all data frames. */ 2796 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2797} 2798 2799static void 2800urtwn_edca_init(struct urtwn_softc *sc) 2801{ 2802 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2803 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2804 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2805 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2806 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2807 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2808 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2809 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2810} 2811 2812void 2813urtwn_write_txpower(struct urtwn_softc *sc, int chain, 2814 uint16_t power[URTWN_RIDX_COUNT]) 2815{ 2816 uint32_t reg; 2817 2818 /* Write per-CCK rate Tx power. */ 2819 if (chain == 0) { 2820 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2821 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2822 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2823 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2824 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2825 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2826 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2827 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2828 } else { 2829 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2830 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2831 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2832 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2833 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2834 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2835 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2836 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2837 } 2838 /* Write per-OFDM rate Tx power. */ 2839 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2840 SM(R92C_TXAGC_RATE06, power[ 4]) | 2841 SM(R92C_TXAGC_RATE09, power[ 5]) | 2842 SM(R92C_TXAGC_RATE12, power[ 6]) | 2843 SM(R92C_TXAGC_RATE18, power[ 7])); 2844 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2845 SM(R92C_TXAGC_RATE24, power[ 8]) | 2846 SM(R92C_TXAGC_RATE36, power[ 9]) | 2847 SM(R92C_TXAGC_RATE48, power[10]) | 2848 SM(R92C_TXAGC_RATE54, power[11])); 2849 /* Write per-MCS Tx power. */ 2850 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2851 SM(R92C_TXAGC_MCS00, power[12]) | 2852 SM(R92C_TXAGC_MCS01, power[13]) | 2853 SM(R92C_TXAGC_MCS02, power[14]) | 2854 SM(R92C_TXAGC_MCS03, power[15])); 2855 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2856 SM(R92C_TXAGC_MCS04, power[16]) | 2857 SM(R92C_TXAGC_MCS05, power[17]) | 2858 SM(R92C_TXAGC_MCS06, power[18]) | 2859 SM(R92C_TXAGC_MCS07, power[19])); 2860 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2861 SM(R92C_TXAGC_MCS08, power[20]) | 2862 SM(R92C_TXAGC_MCS09, power[21]) | 2863 SM(R92C_TXAGC_MCS10, power[22]) | 2864 SM(R92C_TXAGC_MCS11, power[23])); 2865 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2866 SM(R92C_TXAGC_MCS12, power[24]) | 2867 SM(R92C_TXAGC_MCS13, power[25]) | 2868 SM(R92C_TXAGC_MCS14, power[26]) | 2869 SM(R92C_TXAGC_MCS15, power[27])); 2870} 2871 2872void 2873urtwn_get_txpower(struct urtwn_softc *sc, int chain, 2874 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2875 uint16_t power[URTWN_RIDX_COUNT]) 2876{ 2877 struct ieee80211com *ic = &sc->sc_ic; 2878 struct r92c_rom *rom = &sc->rom; 2879 uint16_t cckpow, ofdmpow, htpow, diff, max; 2880 const struct urtwn_txpwr *base; 2881 int ridx, chan, group; 2882 2883 /* Determine channel group. */ 2884 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2885 if (chan <= 3) 2886 group = 0; 2887 else if (chan <= 9) 2888 group = 1; 2889 else 2890 group = 2; 2891 2892 /* Get original Tx power based on board type and RF chain. */ 2893 if (!(sc->chip & URTWN_CHIP_92C)) { 2894 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2895 base = &rtl8188ru_txagc[chain]; 2896 else 2897 base = &rtl8192cu_txagc[chain]; 2898 } else 2899 base = &rtl8192cu_txagc[chain]; 2900 2901 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2902 if (sc->regulatory == 0) { 2903 for (ridx = 0; ridx <= 3; ridx++) 2904 power[ridx] = base->pwr[0][ridx]; 2905 } 2906 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 2907 if (sc->regulatory == 3) { 2908 power[ridx] = base->pwr[0][ridx]; 2909 /* Apply vendor limits. */ 2910 if (extc != NULL) 2911 max = rom->ht40_max_pwr[group]; 2912 else 2913 max = rom->ht20_max_pwr[group]; 2914 max = (max >> (chain * 4)) & 0xf; 2915 if (power[ridx] > max) 2916 power[ridx] = max; 2917 } else if (sc->regulatory == 1) { 2918 if (extc == NULL) 2919 power[ridx] = base->pwr[group][ridx]; 2920 } else if (sc->regulatory != 2) 2921 power[ridx] = base->pwr[0][ridx]; 2922 } 2923 2924 /* Compute per-CCK rate Tx power. */ 2925 cckpow = rom->cck_tx_pwr[chain][group]; 2926 for (ridx = 0; ridx <= 3; ridx++) { 2927 power[ridx] += cckpow; 2928 if (power[ridx] > R92C_MAX_TX_PWR) 2929 power[ridx] = R92C_MAX_TX_PWR; 2930 } 2931 2932 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2933 if (sc->ntxchains > 1) { 2934 /* Apply reduction for 2 spatial streams. */ 2935 diff = rom->ht40_2s_tx_pwr_diff[group]; 2936 diff = (diff >> (chain * 4)) & 0xf; 2937 htpow = (htpow > diff) ? htpow - diff : 0; 2938 } 2939 2940 /* Compute per-OFDM rate Tx power. */ 2941 diff = rom->ofdm_tx_pwr_diff[group]; 2942 diff = (diff >> (chain * 4)) & 0xf; 2943 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2944 for (ridx = 4; ridx <= 11; ridx++) { 2945 power[ridx] += ofdmpow; 2946 if (power[ridx] > R92C_MAX_TX_PWR) 2947 power[ridx] = R92C_MAX_TX_PWR; 2948 } 2949 2950 /* Compute per-MCS Tx power. */ 2951 if (extc == NULL) { 2952 diff = rom->ht20_tx_pwr_diff[group]; 2953 diff = (diff >> (chain * 4)) & 0xf; 2954 htpow += diff; /* HT40->HT20 correction. */ 2955 } 2956 for (ridx = 12; ridx <= 27; ridx++) { 2957 power[ridx] += htpow; 2958 if (power[ridx] > R92C_MAX_TX_PWR) 2959 power[ridx] = R92C_MAX_TX_PWR; 2960 } 2961#ifdef URTWN_DEBUG 2962 if (urtwn_debug >= 4) { 2963 /* Dump per-rate Tx power values. */ 2964 printf("Tx power for chain %d:\n", chain); 2965 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 2966 printf("Rate %d = %u\n", ridx, power[ridx]); 2967 } 2968#endif 2969} 2970 2971void 2972urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 2973 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2974 uint16_t power[URTWN_RIDX_COUNT]) 2975{ 2976 struct ieee80211com *ic = &sc->sc_ic; 2977 uint16_t cckpow, ofdmpow, bw20pow, htpow; 2978 const struct urtwn_r88e_txpwr *base; 2979 int ridx, chan, group; 2980 2981 /* Determine channel group. */ 2982 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2983 if (chan <= 2) 2984 group = 0; 2985 else if (chan <= 5) 2986 group = 1; 2987 else if (chan <= 8) 2988 group = 2; 2989 else if (chan <= 11) 2990 group = 3; 2991 else if (chan <= 13) 2992 group = 4; 2993 else 2994 group = 5; 2995 2996 /* Get original Tx power based on board type and RF chain. */ 2997 base = &rtl8188eu_txagc[chain]; 2998 2999 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3000 if (sc->regulatory == 0) { 3001 for (ridx = 0; ridx <= 3; ridx++) 3002 power[ridx] = base->pwr[0][ridx]; 3003 } 3004 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3005 if (sc->regulatory == 3) 3006 power[ridx] = base->pwr[0][ridx]; 3007 else if (sc->regulatory == 1) { 3008 if (extc == NULL) 3009 power[ridx] = base->pwr[group][ridx]; 3010 } else if (sc->regulatory != 2) 3011 power[ridx] = base->pwr[0][ridx]; 3012 } 3013 3014 /* Compute per-CCK rate Tx power. */ 3015 cckpow = sc->cck_tx_pwr[group]; 3016 for (ridx = 0; ridx <= 3; ridx++) { 3017 power[ridx] += cckpow; 3018 if (power[ridx] > R92C_MAX_TX_PWR) 3019 power[ridx] = R92C_MAX_TX_PWR; 3020 } 3021 3022 htpow = sc->ht40_tx_pwr[group]; 3023 3024 /* Compute per-OFDM rate Tx power. */ 3025 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3026 for (ridx = 4; ridx <= 11; ridx++) { 3027 power[ridx] += ofdmpow; 3028 if (power[ridx] > R92C_MAX_TX_PWR) 3029 power[ridx] = R92C_MAX_TX_PWR; 3030 } 3031 3032 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3033 for (ridx = 12; ridx <= 27; ridx++) { 3034 power[ridx] += bw20pow; 3035 if (power[ridx] > R92C_MAX_TX_PWR) 3036 power[ridx] = R92C_MAX_TX_PWR; 3037 } 3038} 3039 3040void 3041urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3042 struct ieee80211_channel *extc) 3043{ 3044 uint16_t power[URTWN_RIDX_COUNT]; 3045 int i; 3046 3047 for (i = 0; i < sc->ntxchains; i++) { 3048 /* Compute per-rate Tx power values. */ 3049 if (sc->chip & URTWN_CHIP_88E) 3050 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3051 else 3052 urtwn_get_txpower(sc, i, c, extc, power); 3053 /* Write per-rate Tx power values to hardware. */ 3054 urtwn_write_txpower(sc, i, power); 3055 } 3056} 3057 3058static void 3059urtwn_scan_start(struct ieee80211com *ic) 3060{ 3061 /* XXX do nothing? */ 3062} 3063 3064static void 3065urtwn_scan_end(struct ieee80211com *ic) 3066{ 3067 /* XXX do nothing? */ 3068} 3069 3070static void 3071urtwn_set_channel(struct ieee80211com *ic) 3072{ 3073 struct urtwn_softc *sc = ic->ic_softc; 3074 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3075 3076 URTWN_LOCK(sc); 3077 if (vap->iv_state == IEEE80211_S_SCAN) { 3078 /* Make link LED blink during scan. */ 3079 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3080 } 3081 urtwn_set_chan(sc, ic->ic_curchan, NULL); 3082 URTWN_UNLOCK(sc); 3083} 3084 3085static void 3086urtwn_update_mcast(struct ieee80211com *ic) 3087{ 3088 /* XXX do nothing? */ 3089} 3090 3091static void 3092urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3093 struct ieee80211_channel *extc) 3094{ 3095 struct ieee80211com *ic = &sc->sc_ic; 3096 uint32_t reg; 3097 u_int chan; 3098 int i; 3099 3100 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3101 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3102 device_printf(sc->sc_dev, 3103 "%s: invalid channel %x\n", __func__, chan); 3104 return; 3105 } 3106 3107 /* Set Tx power for this new channel. */ 3108 urtwn_set_txpower(sc, c, extc); 3109 3110 for (i = 0; i < sc->nrxchains; i++) { 3111 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3112 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3113 } 3114#ifndef IEEE80211_NO_HT 3115 if (extc != NULL) { 3116 /* Is secondary channel below or above primary? */ 3117 int prichlo = c->ic_freq < extc->ic_freq; 3118 3119 urtwn_write_1(sc, R92C_BWOPMODE, 3120 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3121 3122 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3123 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3124 urtwn_write_1(sc, R92C_RRSR + 2, reg); 3125 3126 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3127 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3128 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3129 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3130 3131 /* Set CCK side band. */ 3132 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3133 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3134 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3135 3136 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3137 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3138 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3139 3140 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3141 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3142 ~R92C_FPGA0_ANAPARAM2_CBW20); 3143 3144 reg = urtwn_bb_read(sc, 0x818); 3145 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3146 urtwn_bb_write(sc, 0x818, reg); 3147 3148 /* Select 40MHz bandwidth. */ 3149 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3150 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3151 } else 3152#endif 3153 { 3154 urtwn_write_1(sc, R92C_BWOPMODE, 3155 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3156 3157 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3158 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3159 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3160 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3161 3162 if (!(sc->chip & URTWN_CHIP_88E)) { 3163 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3164 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3165 R92C_FPGA0_ANAPARAM2_CBW20); 3166 } 3167 3168 /* Select 20MHz bandwidth. */ 3169 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3170 (sc->rf_chnlbw[0] & ~0xfff) | chan | 3171 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3172 R92C_RF_CHNLBW_BW20)); 3173 } 3174} 3175 3176static void 3177urtwn_iq_calib(struct urtwn_softc *sc) 3178{ 3179 /* TODO */ 3180} 3181 3182static void 3183urtwn_lc_calib(struct urtwn_softc *sc) 3184{ 3185 uint32_t rf_ac[2]; 3186 uint8_t txmode; 3187 int i; 3188 3189 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3190 if ((txmode & 0x70) != 0) { 3191 /* Disable all continuous Tx. */ 3192 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3193 3194 /* Set RF mode to standby mode. */ 3195 for (i = 0; i < sc->nrxchains; i++) { 3196 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3197 urtwn_rf_write(sc, i, R92C_RF_AC, 3198 RW(rf_ac[i], R92C_RF_AC_MODE, 3199 R92C_RF_AC_MODE_STANDBY)); 3200 } 3201 } else { 3202 /* Block all Tx queues. */ 3203 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3204 } 3205 /* Start calibration. */ 3206 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3207 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3208 3209 /* Give calibration the time to complete. */ 3210 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3211 3212 /* Restore configuration. */ 3213 if ((txmode & 0x70) != 0) { 3214 /* Restore Tx mode. */ 3215 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3216 /* Restore RF mode. */ 3217 for (i = 0; i < sc->nrxchains; i++) 3218 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3219 } else { 3220 /* Unblock all Tx queues. */ 3221 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3222 } 3223} 3224 3225static void 3226urtwn_init(struct urtwn_softc *sc) 3227{ 3228 struct ieee80211com *ic = &sc->sc_ic; 3229 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3230 uint8_t macaddr[IEEE80211_ADDR_LEN]; 3231 uint32_t reg; 3232 int error; 3233 3234 URTWN_ASSERT_LOCKED(sc); 3235 3236 if (sc->sc_flags & URTWN_RUNNING) 3237 urtwn_stop(sc); 3238 3239 /* Init firmware commands ring. */ 3240 sc->fwcur = 0; 3241 3242 /* Allocate Tx/Rx buffers. */ 3243 error = urtwn_alloc_rx_list(sc); 3244 if (error != 0) 3245 goto fail; 3246 3247 error = urtwn_alloc_tx_list(sc); 3248 if (error != 0) 3249 goto fail; 3250 3251 /* Power on adapter. */ 3252 error = urtwn_power_on(sc); 3253 if (error != 0) 3254 goto fail; 3255 3256 /* Initialize DMA. */ 3257 error = urtwn_dma_init(sc); 3258 if (error != 0) 3259 goto fail; 3260 3261 /* Set info size in Rx descriptors (in 64-bit words). */ 3262 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3263 3264 /* Init interrupts. */ 3265 if (sc->chip & URTWN_CHIP_88E) { 3266 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3267 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3268 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3269 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3270 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3271 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3272 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3273 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3274 } else { 3275 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3276 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3277 } 3278 3279 /* Set MAC address. */ 3280 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3281 urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3282 3283 /* Set initial network type. */ 3284 reg = urtwn_read_4(sc, R92C_CR); 3285 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3286 urtwn_write_4(sc, R92C_CR, reg); 3287 3288 urtwn_rxfilter_init(sc); 3289 3290 /* Set response rate. */ 3291 reg = urtwn_read_4(sc, R92C_RRSR); 3292 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3293 urtwn_write_4(sc, R92C_RRSR, reg); 3294 3295 /* Set short/long retry limits. */ 3296 urtwn_write_2(sc, R92C_RL, 3297 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3298 3299 /* Initialize EDCA parameters. */ 3300 urtwn_edca_init(sc); 3301 3302 /* Setup rate fallback. */ 3303 if (!(sc->chip & URTWN_CHIP_88E)) { 3304 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3305 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3306 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3307 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3308 } 3309 3310 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3311 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3312 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3313 /* Set ACK timeout. */ 3314 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3315 3316 /* Setup USB aggregation. */ 3317 reg = urtwn_read_4(sc, R92C_TDECTRL); 3318 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3319 urtwn_write_4(sc, R92C_TDECTRL, reg); 3320 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3321 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3322 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3323 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3324 if (sc->chip & URTWN_CHIP_88E) 3325 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3326 else { 3327 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3328 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3329 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3330 R92C_USB_SPECIAL_OPTION_AGG_EN); 3331 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3332 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3333 } 3334 3335 /* Initialize beacon parameters. */ 3336 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3337 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3338 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3339 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3340 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3341 3342 if (!(sc->chip & URTWN_CHIP_88E)) { 3343 /* Setup AMPDU aggregation. */ 3344 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3345 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3346 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3347 3348 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3349 } 3350 3351 /* Load 8051 microcode. */ 3352 error = urtwn_load_firmware(sc); 3353 if (error != 0) 3354 goto fail; 3355 3356 /* Initialize MAC/BB/RF blocks. */ 3357 urtwn_mac_init(sc); 3358 urtwn_bb_init(sc); 3359 urtwn_rf_init(sc); 3360 3361 if (sc->chip & URTWN_CHIP_88E) { 3362 urtwn_write_2(sc, R92C_CR, 3363 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3364 R92C_CR_MACRXEN); 3365 } 3366 3367 /* Turn CCK and OFDM blocks on. */ 3368 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3369 reg |= R92C_RFMOD_CCK_EN; 3370 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3371 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3372 reg |= R92C_RFMOD_OFDM_EN; 3373 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3374 3375 /* Clear per-station keys table. */ 3376 urtwn_cam_init(sc); 3377 3378 /* Enable hardware sequence numbering. */ 3379 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3380 3381 /* Perform LO and IQ calibrations. */ 3382 urtwn_iq_calib(sc); 3383 /* Perform LC calibration. */ 3384 urtwn_lc_calib(sc); 3385 3386 /* Fix USB interference issue. */ 3387 if (!(sc->chip & URTWN_CHIP_88E)) { 3388 urtwn_write_1(sc, 0xfe40, 0xe0); 3389 urtwn_write_1(sc, 0xfe41, 0x8d); 3390 urtwn_write_1(sc, 0xfe42, 0x80); 3391 3392 urtwn_pa_bias_init(sc); 3393 } 3394 3395 /* Initialize GPIO setting. */ 3396 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3397 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3398 3399 /* Fix for lower temperature. */ 3400 if (!(sc->chip & URTWN_CHIP_88E)) 3401 urtwn_write_1(sc, 0x15, 0xe9); 3402 3403 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3404 3405 sc->sc_flags |= URTWN_RUNNING; 3406 3407 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3408fail: 3409 return; 3410} 3411 3412static void 3413urtwn_stop(struct urtwn_softc *sc) 3414{ 3415 3416 URTWN_ASSERT_LOCKED(sc); 3417 sc->sc_flags &= ~URTWN_RUNNING; 3418 callout_stop(&sc->sc_watchdog_ch); 3419 urtwn_abort_xfers(sc); 3420} 3421 3422static void 3423urtwn_abort_xfers(struct urtwn_softc *sc) 3424{ 3425 int i; 3426 3427 URTWN_ASSERT_LOCKED(sc); 3428 3429 /* abort any pending transfers */ 3430 for (i = 0; i < URTWN_N_TRANSFER; i++) 3431 usbd_transfer_stop(sc->sc_xfer[i]); 3432} 3433 3434static int 3435urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3436 const struct ieee80211_bpf_params *params) 3437{ 3438 struct ieee80211com *ic = ni->ni_ic; 3439 struct urtwn_softc *sc = ic->ic_softc; 3440 struct urtwn_data *bf; 3441 3442 /* prevent management frames from being sent if we're not ready */ 3443 if (!(sc->sc_flags & URTWN_RUNNING)) { 3444 m_freem(m); 3445 ieee80211_free_node(ni); 3446 return (ENETDOWN); 3447 } 3448 URTWN_LOCK(sc); 3449 bf = urtwn_getbuf(sc); 3450 if (bf == NULL) { 3451 ieee80211_free_node(ni); 3452 m_freem(m); 3453 URTWN_UNLOCK(sc); 3454 return (ENOBUFS); 3455 } 3456 3457 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3458 ieee80211_free_node(ni); 3459 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3460 URTWN_UNLOCK(sc); 3461 return (EIO); 3462 } 3463 URTWN_UNLOCK(sc); 3464 3465 sc->sc_txtimer = 5; 3466 return (0); 3467} 3468 3469static void 3470urtwn_ms_delay(struct urtwn_softc *sc) 3471{ 3472 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3473} 3474 3475static device_method_t urtwn_methods[] = { 3476 /* Device interface */ 3477 DEVMETHOD(device_probe, urtwn_match), 3478 DEVMETHOD(device_attach, urtwn_attach), 3479 DEVMETHOD(device_detach, urtwn_detach), 3480 3481 DEVMETHOD_END 3482}; 3483 3484static driver_t urtwn_driver = { 3485 "urtwn", 3486 urtwn_methods, 3487 sizeof(struct urtwn_softc) 3488}; 3489 3490static devclass_t urtwn_devclass; 3491 3492DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3493MODULE_DEPEND(urtwn, usb, 1, 1, 1); 3494MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3495MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3496MODULE_VERSION(urtwn, 1); 3497