if_urtwn.c revision 287197
1251538Srpaulo/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2251538Srpaulo 3251538Srpaulo/*- 4251538Srpaulo * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5264912Skevlo * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6251538Srpaulo * 7251538Srpaulo * Permission to use, copy, modify, and distribute this software for any 8251538Srpaulo * purpose with or without fee is hereby granted, provided that the above 9251538Srpaulo * copyright notice and this permission notice appear in all copies. 10251538Srpaulo * 11251538Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12251538Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13251538Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14251538Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15251538Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16251538Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17251538Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18251538Srpaulo */ 19251538Srpaulo 20251538Srpaulo#include <sys/cdefs.h> 21251538Srpaulo__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 287197 2015-08-27 08:56:39Z glebius $"); 22251538Srpaulo 23251538Srpaulo/* 24264912Skevlo * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25251538Srpaulo */ 26251538Srpaulo 27251538Srpaulo#include <sys/param.h> 28251538Srpaulo#include <sys/sockio.h> 29251538Srpaulo#include <sys/sysctl.h> 30251538Srpaulo#include <sys/lock.h> 31251538Srpaulo#include <sys/mutex.h> 32251538Srpaulo#include <sys/mbuf.h> 33251538Srpaulo#include <sys/kernel.h> 34251538Srpaulo#include <sys/socket.h> 35251538Srpaulo#include <sys/systm.h> 36251538Srpaulo#include <sys/malloc.h> 37251538Srpaulo#include <sys/module.h> 38251538Srpaulo#include <sys/bus.h> 39251538Srpaulo#include <sys/endian.h> 40251538Srpaulo#include <sys/linker.h> 41251538Srpaulo#include <sys/firmware.h> 42251538Srpaulo#include <sys/kdb.h> 43251538Srpaulo 44251538Srpaulo#include <machine/bus.h> 45251538Srpaulo#include <machine/resource.h> 46251538Srpaulo#include <sys/rman.h> 47251538Srpaulo 48251538Srpaulo#include <net/bpf.h> 49251538Srpaulo#include <net/if.h> 50257176Sglebius#include <net/if_var.h> 51251538Srpaulo#include <net/if_arp.h> 52251538Srpaulo#include <net/ethernet.h> 53251538Srpaulo#include <net/if_dl.h> 54251538Srpaulo#include <net/if_media.h> 55251538Srpaulo#include <net/if_types.h> 56251538Srpaulo 57251538Srpaulo#include <netinet/in.h> 58251538Srpaulo#include <netinet/in_systm.h> 59251538Srpaulo#include <netinet/in_var.h> 60251538Srpaulo#include <netinet/if_ether.h> 61251538Srpaulo#include <netinet/ip.h> 62251538Srpaulo 63251538Srpaulo#include <net80211/ieee80211_var.h> 64251538Srpaulo#include <net80211/ieee80211_regdomain.h> 65251538Srpaulo#include <net80211/ieee80211_radiotap.h> 66251538Srpaulo#include <net80211/ieee80211_ratectl.h> 67251538Srpaulo 68251538Srpaulo#include <dev/usb/usb.h> 69251538Srpaulo#include <dev/usb/usbdi.h> 70251538Srpaulo#include "usbdevs.h" 71251538Srpaulo 72251538Srpaulo#define USB_DEBUG_VAR urtwn_debug 73251538Srpaulo#include <dev/usb/usb_debug.h> 74251538Srpaulo 75251538Srpaulo#include <dev/usb/wlan/if_urtwnreg.h> 76251538Srpaulo 77251538Srpaulo#ifdef USB_DEBUG 78251538Srpaulostatic int urtwn_debug = 0; 79251538Srpaulo 80251538SrpauloSYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 81276701ShselaskySYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 82251538Srpaulo "Debug level"); 83251538Srpaulo#endif 84251538Srpaulo 85252406Srpaulo#define URTWN_RSSI(r) (r) - 110 86251538Srpaulo#define IEEE80211_HAS_ADDR4(wh) \ 87251538Srpaulo (((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) 88251538Srpaulo 89251538Srpaulo/* various supported device vendors/products */ 90251596Srpaulostatic const STRUCT_USB_HOST_ID urtwn_devs[] = { 91251538Srpaulo#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 92264912Skevlo#define URTWN_RTL8188E_DEV(v,p) \ 93264912Skevlo { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 94264912Skevlo#define URTWN_RTL8188E 1 95251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_1), 96251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_2), 97251538Srpaulo URTWN_DEV(ABOCOM, RTL8192CU), 98251538Srpaulo URTWN_DEV(ASUS, RTL8192CU), 99266721Skevlo URTWN_DEV(ASUS, USBN10NANO), 100251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_1), 101251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_2), 102251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CU), 103251538Srpaulo URTWN_DEV(BELKIN, F7D2102), 104251538Srpaulo URTWN_DEV(BELKIN, RTL8188CU), 105251538Srpaulo URTWN_DEV(BELKIN, RTL8192CU), 106251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_1), 107251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_2), 108251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_3), 109251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_4), 110251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_5), 111251538Srpaulo URTWN_DEV(COREGA, RTL8192CU), 112251538Srpaulo URTWN_DEV(DLINK, RTL8188CU), 113251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_1), 114251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_2), 115251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_3), 116252196Skevlo URTWN_DEV(DLINK, DWA131B), 117251538Srpaulo URTWN_DEV(EDIMAX, EW7811UN), 118251538Srpaulo URTWN_DEV(EDIMAX, RTL8192CU), 119251538Srpaulo URTWN_DEV(FEIXUN, RTL8188CU), 120251538Srpaulo URTWN_DEV(FEIXUN, RTL8192CU), 121251538Srpaulo URTWN_DEV(GUILLEMOT, HWNUP150), 122251538Srpaulo URTWN_DEV(HAWKING, RTL8192CU), 123251538Srpaulo URTWN_DEV(HP3, RTL8188CU), 124251538Srpaulo URTWN_DEV(NETGEAR, WNA1000M), 125251538Srpaulo URTWN_DEV(NETGEAR, RTL8192CU), 126251538Srpaulo URTWN_DEV(NETGEAR4, RTL8188CU), 127251538Srpaulo URTWN_DEV(NOVATECH, RTL8188CU), 128251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_1), 129251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_2), 130251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_3), 131251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_4), 132251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CUS), 133251538Srpaulo URTWN_DEV(PLANEX2, RTL8192CU), 134251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_0), 135251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_1), 136251538Srpaulo URTWN_DEV(REALTEK, RTL8188CTV), 137251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_0), 138251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_1), 139251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_2), 140282119Skevlo URTWN_DEV(REALTEK, RTL8188CU_3), 141251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_COMBO), 142251538Srpaulo URTWN_DEV(REALTEK, RTL8188CUS), 143251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_1), 144251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_2), 145272410Shselasky URTWN_DEV(REALTEK, RTL8188RU_3), 146251538Srpaulo URTWN_DEV(REALTEK, RTL8191CU), 147251538Srpaulo URTWN_DEV(REALTEK, RTL8192CE), 148251538Srpaulo URTWN_DEV(REALTEK, RTL8192CU), 149251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_1), 150251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_2), 151251538Srpaulo URTWN_DEV(SITECOMEU, RTL8192CU), 152251538Srpaulo URTWN_DEV(TRENDNET, RTL8188CU), 153251538Srpaulo URTWN_DEV(TRENDNET, RTL8192CU), 154251538Srpaulo URTWN_DEV(ZYXEL, RTL8192CU), 155264912Skevlo /* URTWN_RTL8188E */ 156273589Skevlo URTWN_RTL8188E_DEV(DLINK, DWA123D1), 157270191Skevlo URTWN_RTL8188E_DEV(DLINK, DWA125D1), 158273589Skevlo URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 159264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 160264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 161264912Skevlo#undef URTWN_RTL8188E_DEV 162251538Srpaulo#undef URTWN_DEV 163251538Srpaulo}; 164251538Srpaulo 165251538Srpaulostatic device_probe_t urtwn_match; 166251538Srpaulostatic device_attach_t urtwn_attach; 167251538Srpaulostatic device_detach_t urtwn_detach; 168251538Srpaulo 169251538Srpaulostatic usb_callback_t urtwn_bulk_tx_callback; 170251538Srpaulostatic usb_callback_t urtwn_bulk_rx_callback; 171251538Srpaulo 172287197Sglebiusstatic usb_error_t urtwn_do_request(struct urtwn_softc *, 173287197Sglebius struct usb_device_request *, void *); 174251538Srpaulostatic struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 175251538Srpaulo const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 176251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN], 177251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN]); 178251538Srpaulostatic void urtwn_vap_delete(struct ieee80211vap *); 179281069Srpaulostatic struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 180251538Srpaulo int *); 181281069Srpaulostatic struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 182251538Srpaulo int *, int8_t *); 183251538Srpaulostatic void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 184281069Srpaulostatic int urtwn_alloc_list(struct urtwn_softc *, 185251538Srpaulo struct urtwn_data[], int, int); 186251538Srpaulostatic int urtwn_alloc_rx_list(struct urtwn_softc *); 187251538Srpaulostatic int urtwn_alloc_tx_list(struct urtwn_softc *); 188251538Srpaulostatic void urtwn_free_tx_list(struct urtwn_softc *); 189251538Srpaulostatic void urtwn_free_rx_list(struct urtwn_softc *); 190251538Srpaulostatic void urtwn_free_list(struct urtwn_softc *, 191251538Srpaulo struct urtwn_data data[], int); 192251538Srpaulostatic struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 193251538Srpaulostatic struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 194281069Srpaulostatic int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 195251538Srpaulo uint8_t *, int); 196251538Srpaulostatic void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 197251538Srpaulostatic void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 198251538Srpaulostatic void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 199281069Srpaulostatic int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 200251538Srpaulo uint8_t *, int); 201251538Srpaulostatic uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 202251538Srpaulostatic uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 203251538Srpaulostatic uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 204281069Srpaulostatic int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 205251538Srpaulo const void *, int); 206264912Skevlostatic void urtwn_r92c_rf_write(struct urtwn_softc *, int, 207264912Skevlo uint8_t, uint32_t); 208281069Srpaulostatic void urtwn_r88e_rf_write(struct urtwn_softc *, int, 209264912Skevlo uint8_t, uint32_t); 210251538Srpaulostatic uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 211281069Srpaulostatic int urtwn_llt_write(struct urtwn_softc *, uint32_t, 212251538Srpaulo uint32_t); 213251538Srpaulostatic uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 214251538Srpaulostatic void urtwn_efuse_read(struct urtwn_softc *); 215264912Skevlostatic void urtwn_efuse_switch_power(struct urtwn_softc *); 216251538Srpaulostatic int urtwn_read_chipid(struct urtwn_softc *); 217251538Srpaulostatic void urtwn_read_rom(struct urtwn_softc *); 218264912Skevlostatic void urtwn_r88e_read_rom(struct urtwn_softc *); 219251538Srpaulostatic int urtwn_ra_init(struct urtwn_softc *); 220251538Srpaulostatic void urtwn_tsf_sync_enable(struct urtwn_softc *); 221251538Srpaulostatic void urtwn_set_led(struct urtwn_softc *, int, int); 222281069Srpaulostatic int urtwn_newstate(struct ieee80211vap *, 223251538Srpaulo enum ieee80211_state, int); 224251538Srpaulostatic void urtwn_watchdog(void *); 225251538Srpaulostatic void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 226251538Srpaulostatic int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 227264912Skevlostatic int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 228251538Srpaulostatic int urtwn_tx_start(struct urtwn_softc *, 229251538Srpaulo struct ieee80211_node *, struct mbuf *, 230251538Srpaulo struct urtwn_data *); 231287197Sglebiusstatic int urtwn_transmit(struct ieee80211com *, struct mbuf *); 232287197Sglebiusstatic void urtwn_start(struct urtwn_softc *); 233287197Sglebiusstatic void urtwn_parent(struct ieee80211com *); 234264912Skevlostatic int urtwn_r92c_power_on(struct urtwn_softc *); 235264912Skevlostatic int urtwn_r88e_power_on(struct urtwn_softc *); 236251538Srpaulostatic int urtwn_llt_init(struct urtwn_softc *); 237251538Srpaulostatic void urtwn_fw_reset(struct urtwn_softc *); 238264912Skevlostatic void urtwn_r88e_fw_reset(struct urtwn_softc *); 239281069Srpaulostatic int urtwn_fw_loadpage(struct urtwn_softc *, int, 240251538Srpaulo const uint8_t *, int); 241251538Srpaulostatic int urtwn_load_firmware(struct urtwn_softc *); 242264912Skevlostatic int urtwn_r92c_dma_init(struct urtwn_softc *); 243264912Skevlostatic int urtwn_r88e_dma_init(struct urtwn_softc *); 244251538Srpaulostatic void urtwn_mac_init(struct urtwn_softc *); 245251538Srpaulostatic void urtwn_bb_init(struct urtwn_softc *); 246251538Srpaulostatic void urtwn_rf_init(struct urtwn_softc *); 247251538Srpaulostatic void urtwn_cam_init(struct urtwn_softc *); 248251538Srpaulostatic void urtwn_pa_bias_init(struct urtwn_softc *); 249251538Srpaulostatic void urtwn_rxfilter_init(struct urtwn_softc *); 250251538Srpaulostatic void urtwn_edca_init(struct urtwn_softc *); 251281069Srpaulostatic void urtwn_write_txpower(struct urtwn_softc *, int, 252251538Srpaulo uint16_t[]); 253251538Srpaulostatic void urtwn_get_txpower(struct urtwn_softc *, int, 254281069Srpaulo struct ieee80211_channel *, 255251538Srpaulo struct ieee80211_channel *, uint16_t[]); 256264912Skevlostatic void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 257281069Srpaulo struct ieee80211_channel *, 258264912Skevlo struct ieee80211_channel *, uint16_t[]); 259251538Srpaulostatic void urtwn_set_txpower(struct urtwn_softc *, 260281069Srpaulo struct ieee80211_channel *, 261251538Srpaulo struct ieee80211_channel *); 262251538Srpaulostatic void urtwn_scan_start(struct ieee80211com *); 263251538Srpaulostatic void urtwn_scan_end(struct ieee80211com *); 264251538Srpaulostatic void urtwn_set_channel(struct ieee80211com *); 265251538Srpaulostatic void urtwn_set_chan(struct urtwn_softc *, 266281069Srpaulo struct ieee80211_channel *, 267251538Srpaulo struct ieee80211_channel *); 268283540Sglebiusstatic void urtwn_update_mcast(struct ieee80211com *); 269251538Srpaulostatic void urtwn_iq_calib(struct urtwn_softc *); 270251538Srpaulostatic void urtwn_lc_calib(struct urtwn_softc *); 271287197Sglebiusstatic void urtwn_init(struct urtwn_softc *); 272287197Sglebiusstatic void urtwn_stop(struct urtwn_softc *); 273251538Srpaulostatic void urtwn_abort_xfers(struct urtwn_softc *); 274251538Srpaulostatic int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 275251538Srpaulo const struct ieee80211_bpf_params *); 276266472Shselaskystatic void urtwn_ms_delay(struct urtwn_softc *); 277251538Srpaulo 278251538Srpaulo/* Aliases. */ 279251538Srpaulo#define urtwn_bb_write urtwn_write_4 280251538Srpaulo#define urtwn_bb_read urtwn_read_4 281251538Srpaulo 282251538Srpaulostatic const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 283251538Srpaulo [URTWN_BULK_RX] = { 284251538Srpaulo .type = UE_BULK, 285251538Srpaulo .endpoint = UE_ADDR_ANY, 286251538Srpaulo .direction = UE_DIR_IN, 287251538Srpaulo .bufsize = URTWN_RXBUFSZ, 288251538Srpaulo .flags = { 289251538Srpaulo .pipe_bof = 1, 290251538Srpaulo .short_xfer_ok = 1 291251538Srpaulo }, 292251538Srpaulo .callback = urtwn_bulk_rx_callback, 293251538Srpaulo }, 294251538Srpaulo [URTWN_BULK_TX_BE] = { 295251538Srpaulo .type = UE_BULK, 296251538Srpaulo .endpoint = 0x03, 297251538Srpaulo .direction = UE_DIR_OUT, 298251538Srpaulo .bufsize = URTWN_TXBUFSZ, 299251538Srpaulo .flags = { 300251538Srpaulo .ext_buffer = 1, 301251538Srpaulo .pipe_bof = 1, 302251538Srpaulo .force_short_xfer = 1 303251538Srpaulo }, 304251538Srpaulo .callback = urtwn_bulk_tx_callback, 305251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 306251538Srpaulo }, 307251538Srpaulo [URTWN_BULK_TX_BK] = { 308251538Srpaulo .type = UE_BULK, 309251538Srpaulo .endpoint = 0x03, 310251538Srpaulo .direction = UE_DIR_OUT, 311251538Srpaulo .bufsize = URTWN_TXBUFSZ, 312251538Srpaulo .flags = { 313251538Srpaulo .ext_buffer = 1, 314251538Srpaulo .pipe_bof = 1, 315251538Srpaulo .force_short_xfer = 1, 316251538Srpaulo }, 317251538Srpaulo .callback = urtwn_bulk_tx_callback, 318251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 319251538Srpaulo }, 320251538Srpaulo [URTWN_BULK_TX_VI] = { 321251538Srpaulo .type = UE_BULK, 322251538Srpaulo .endpoint = 0x02, 323251538Srpaulo .direction = UE_DIR_OUT, 324251538Srpaulo .bufsize = URTWN_TXBUFSZ, 325251538Srpaulo .flags = { 326251538Srpaulo .ext_buffer = 1, 327251538Srpaulo .pipe_bof = 1, 328251538Srpaulo .force_short_xfer = 1 329251538Srpaulo }, 330251538Srpaulo .callback = urtwn_bulk_tx_callback, 331251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 332251538Srpaulo }, 333251538Srpaulo [URTWN_BULK_TX_VO] = { 334251538Srpaulo .type = UE_BULK, 335251538Srpaulo .endpoint = 0x02, 336251538Srpaulo .direction = UE_DIR_OUT, 337251538Srpaulo .bufsize = URTWN_TXBUFSZ, 338251538Srpaulo .flags = { 339251538Srpaulo .ext_buffer = 1, 340251538Srpaulo .pipe_bof = 1, 341251538Srpaulo .force_short_xfer = 1 342251538Srpaulo }, 343251538Srpaulo .callback = urtwn_bulk_tx_callback, 344251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 345251538Srpaulo }, 346251538Srpaulo}; 347251538Srpaulo 348251538Srpaulostatic int 349251538Srpaulourtwn_match(device_t self) 350251538Srpaulo{ 351251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 352251538Srpaulo 353251538Srpaulo if (uaa->usb_mode != USB_MODE_HOST) 354251538Srpaulo return (ENXIO); 355251538Srpaulo if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 356251538Srpaulo return (ENXIO); 357251538Srpaulo if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 358251538Srpaulo return (ENXIO); 359251538Srpaulo 360251538Srpaulo return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 361251538Srpaulo} 362251538Srpaulo 363251538Srpaulostatic int 364251538Srpaulourtwn_attach(device_t self) 365251538Srpaulo{ 366251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 367251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 368287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 369251538Srpaulo uint8_t iface_index, bands; 370251538Srpaulo int error; 371251538Srpaulo 372251538Srpaulo device_set_usb_desc(self); 373251538Srpaulo sc->sc_udev = uaa->device; 374251538Srpaulo sc->sc_dev = self; 375264912Skevlo if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 376264912Skevlo sc->chip |= URTWN_CHIP_88E; 377251538Srpaulo 378251538Srpaulo mtx_init(&sc->sc_mtx, device_get_nameunit(self), 379251538Srpaulo MTX_NETWORK_LOCK, MTX_DEF); 380251538Srpaulo callout_init(&sc->sc_watchdog_ch, 0); 381287197Sglebius mbufq_init(&sc->sc_snd, ifqmaxlen); 382251538Srpaulo 383251538Srpaulo iface_index = URTWN_IFACE_INDEX; 384251538Srpaulo error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 385251538Srpaulo urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 386251538Srpaulo if (error) { 387251538Srpaulo device_printf(self, "could not allocate USB transfers, " 388251538Srpaulo "err=%s\n", usbd_errstr(error)); 389251538Srpaulo goto detach; 390251538Srpaulo } 391251538Srpaulo 392251538Srpaulo URTWN_LOCK(sc); 393251538Srpaulo 394251538Srpaulo error = urtwn_read_chipid(sc); 395251538Srpaulo if (error) { 396251538Srpaulo device_printf(sc->sc_dev, "unsupported test chip\n"); 397251538Srpaulo URTWN_UNLOCK(sc); 398251538Srpaulo goto detach; 399251538Srpaulo } 400251538Srpaulo 401251538Srpaulo /* Determine number of Tx/Rx chains. */ 402251538Srpaulo if (sc->chip & URTWN_CHIP_92C) { 403251538Srpaulo sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 404251538Srpaulo sc->nrxchains = 2; 405251538Srpaulo } else { 406251538Srpaulo sc->ntxchains = 1; 407251538Srpaulo sc->nrxchains = 1; 408251538Srpaulo } 409251538Srpaulo 410264912Skevlo if (sc->chip & URTWN_CHIP_88E) 411264912Skevlo urtwn_r88e_read_rom(sc); 412264912Skevlo else 413264912Skevlo urtwn_read_rom(sc); 414264912Skevlo 415251538Srpaulo device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 416251538Srpaulo (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 417264912Skevlo (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 418251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 419251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 420251538Srpaulo "8188CUS", sc->ntxchains, sc->nrxchains); 421251538Srpaulo 422251538Srpaulo URTWN_UNLOCK(sc); 423251538Srpaulo 424283537Sglebius ic->ic_softc = sc; 425283527Sglebius ic->ic_name = device_get_nameunit(self); 426251538Srpaulo ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 427251538Srpaulo ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 428251538Srpaulo 429251538Srpaulo /* set device capabilities */ 430251538Srpaulo ic->ic_caps = 431251538Srpaulo IEEE80211_C_STA /* station mode */ 432251538Srpaulo | IEEE80211_C_MONITOR /* monitor mode */ 433251538Srpaulo | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 434251538Srpaulo | IEEE80211_C_SHSLOT /* short slot time supported */ 435251538Srpaulo | IEEE80211_C_BGSCAN /* capable of bg scanning */ 436251538Srpaulo | IEEE80211_C_WPA /* 802.11i */ 437251538Srpaulo ; 438251538Srpaulo 439251538Srpaulo bands = 0; 440251538Srpaulo setbit(&bands, IEEE80211_MODE_11B); 441251538Srpaulo setbit(&bands, IEEE80211_MODE_11G); 442251538Srpaulo ieee80211_init_channels(ic, NULL, &bands); 443251538Srpaulo 444287197Sglebius ieee80211_ifattach(ic); 445251538Srpaulo ic->ic_raw_xmit = urtwn_raw_xmit; 446251538Srpaulo ic->ic_scan_start = urtwn_scan_start; 447251538Srpaulo ic->ic_scan_end = urtwn_scan_end; 448251538Srpaulo ic->ic_set_channel = urtwn_set_channel; 449287197Sglebius ic->ic_transmit = urtwn_transmit; 450287197Sglebius ic->ic_parent = urtwn_parent; 451251538Srpaulo ic->ic_vap_create = urtwn_vap_create; 452251538Srpaulo ic->ic_vap_delete = urtwn_vap_delete; 453251538Srpaulo ic->ic_update_mcast = urtwn_update_mcast; 454251538Srpaulo 455281069Srpaulo ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 456251538Srpaulo sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 457251538Srpaulo &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 458251538Srpaulo URTWN_RX_RADIOTAP_PRESENT); 459251538Srpaulo 460251538Srpaulo if (bootverbose) 461251538Srpaulo ieee80211_announce(ic); 462251538Srpaulo 463251538Srpaulo return (0); 464251538Srpaulo 465251538Srpaulodetach: 466251538Srpaulo urtwn_detach(self); 467251538Srpaulo return (ENXIO); /* failure */ 468251538Srpaulo} 469251538Srpaulo 470251538Srpaulostatic int 471251538Srpaulourtwn_detach(device_t self) 472251538Srpaulo{ 473251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 474287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 475263153Skevlo unsigned int x; 476281069Srpaulo 477263153Skevlo /* Prevent further ioctls. */ 478263153Skevlo URTWN_LOCK(sc); 479263153Skevlo sc->sc_flags |= URTWN_DETACHED; 480287197Sglebius urtwn_stop(sc); 481263153Skevlo URTWN_UNLOCK(sc); 482251538Srpaulo 483251538Srpaulo callout_drain(&sc->sc_watchdog_ch); 484251538Srpaulo 485263153Skevlo /* Prevent further allocations from RX/TX data lists. */ 486263153Skevlo URTWN_LOCK(sc); 487263153Skevlo STAILQ_INIT(&sc->sc_tx_active); 488263153Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 489263153Skevlo STAILQ_INIT(&sc->sc_tx_pending); 490263153Skevlo 491263153Skevlo STAILQ_INIT(&sc->sc_rx_active); 492263153Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 493263153Skevlo URTWN_UNLOCK(sc); 494263153Skevlo 495263153Skevlo /* drain USB transfers */ 496263153Skevlo for (x = 0; x != URTWN_N_TRANSFER; x++) 497263153Skevlo usbd_transfer_drain(sc->sc_xfer[x]); 498263153Skevlo 499263153Skevlo /* Free data buffers. */ 500263153Skevlo URTWN_LOCK(sc); 501263153Skevlo urtwn_free_tx_list(sc); 502263153Skevlo urtwn_free_rx_list(sc); 503263153Skevlo URTWN_UNLOCK(sc); 504263153Skevlo 505251538Srpaulo /* stop all USB transfers */ 506251538Srpaulo usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 507251538Srpaulo ieee80211_ifdetach(ic); 508287197Sglebius mbufq_drain(&sc->sc_snd); 509251538Srpaulo mtx_destroy(&sc->sc_mtx); 510251538Srpaulo 511251538Srpaulo return (0); 512251538Srpaulo} 513251538Srpaulo 514251538Srpaulostatic void 515251538Srpaulourtwn_free_tx_list(struct urtwn_softc *sc) 516251538Srpaulo{ 517251538Srpaulo urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 518251538Srpaulo} 519251538Srpaulo 520251538Srpaulostatic void 521251538Srpaulourtwn_free_rx_list(struct urtwn_softc *sc) 522251538Srpaulo{ 523251538Srpaulo urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 524251538Srpaulo} 525251538Srpaulo 526251538Srpaulostatic void 527251538Srpaulourtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 528251538Srpaulo{ 529251538Srpaulo int i; 530251538Srpaulo 531251538Srpaulo for (i = 0; i < ndata; i++) { 532251538Srpaulo struct urtwn_data *dp = &data[i]; 533251538Srpaulo 534251538Srpaulo if (dp->buf != NULL) { 535251538Srpaulo free(dp->buf, M_USBDEV); 536251538Srpaulo dp->buf = NULL; 537251538Srpaulo } 538251538Srpaulo if (dp->ni != NULL) { 539251538Srpaulo ieee80211_free_node(dp->ni); 540251538Srpaulo dp->ni = NULL; 541251538Srpaulo } 542251538Srpaulo } 543251538Srpaulo} 544251538Srpaulo 545251538Srpaulostatic usb_error_t 546251538Srpaulourtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 547251538Srpaulo void *data) 548251538Srpaulo{ 549251538Srpaulo usb_error_t err; 550251538Srpaulo int ntries = 10; 551251538Srpaulo 552251538Srpaulo URTWN_ASSERT_LOCKED(sc); 553251538Srpaulo 554251538Srpaulo while (ntries--) { 555251538Srpaulo err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 556251538Srpaulo req, data, 0, NULL, 250 /* ms */); 557251538Srpaulo if (err == 0) 558251538Srpaulo break; 559251538Srpaulo 560251538Srpaulo DPRINTFN(1, "Control request failed, %s (retrying)\n", 561251538Srpaulo usbd_errstr(err)); 562251538Srpaulo usb_pause_mtx(&sc->sc_mtx, hz / 100); 563251538Srpaulo } 564251538Srpaulo return (err); 565251538Srpaulo} 566251538Srpaulo 567251538Srpaulostatic struct ieee80211vap * 568251538Srpaulourtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 569251538Srpaulo enum ieee80211_opmode opmode, int flags, 570251538Srpaulo const uint8_t bssid[IEEE80211_ADDR_LEN], 571251538Srpaulo const uint8_t mac[IEEE80211_ADDR_LEN]) 572251538Srpaulo{ 573251538Srpaulo struct urtwn_vap *uvp; 574251538Srpaulo struct ieee80211vap *vap; 575251538Srpaulo 576251538Srpaulo if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 577251538Srpaulo return (NULL); 578251538Srpaulo 579287197Sglebius uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 580251538Srpaulo vap = &uvp->vap; 581251538Srpaulo /* enable s/w bmiss handling for sta mode */ 582251538Srpaulo 583281069Srpaulo if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 584287197Sglebius flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 585257743Shselasky /* out of memory */ 586257743Shselasky free(uvp, M_80211_VAP); 587257743Shselasky return (NULL); 588257743Shselasky } 589257743Shselasky 590251538Srpaulo /* override state transition machine */ 591251538Srpaulo uvp->newstate = vap->iv_newstate; 592251538Srpaulo vap->iv_newstate = urtwn_newstate; 593251538Srpaulo 594251538Srpaulo /* complete setup */ 595251538Srpaulo ieee80211_vap_attach(vap, ieee80211_media_change, 596287197Sglebius ieee80211_media_status, mac); 597251538Srpaulo ic->ic_opmode = opmode; 598251538Srpaulo return (vap); 599251538Srpaulo} 600251538Srpaulo 601251538Srpaulostatic void 602251538Srpaulourtwn_vap_delete(struct ieee80211vap *vap) 603251538Srpaulo{ 604251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 605251538Srpaulo 606251538Srpaulo ieee80211_vap_detach(vap); 607251538Srpaulo free(uvp, M_80211_VAP); 608251538Srpaulo} 609251538Srpaulo 610251538Srpaulostatic struct mbuf * 611251538Srpaulourtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 612251538Srpaulo{ 613287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 614251538Srpaulo struct ieee80211_frame *wh; 615251538Srpaulo struct mbuf *m; 616251538Srpaulo struct r92c_rx_stat *stat; 617251538Srpaulo uint32_t rxdw0, rxdw3; 618251538Srpaulo uint8_t rate; 619251538Srpaulo int8_t rssi = 0; 620251538Srpaulo int infosz; 621251538Srpaulo 622251538Srpaulo /* 623251538Srpaulo * don't pass packets to the ieee80211 framework if the driver isn't 624251538Srpaulo * RUNNING. 625251538Srpaulo */ 626287197Sglebius if (!(sc->sc_flags & URTWN_RUNNING)) 627251538Srpaulo return (NULL); 628251538Srpaulo 629251538Srpaulo stat = (struct r92c_rx_stat *)buf; 630251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 631251538Srpaulo rxdw3 = le32toh(stat->rxdw3); 632251538Srpaulo 633251538Srpaulo if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 634251538Srpaulo /* 635251538Srpaulo * This should not happen since we setup our Rx filter 636251538Srpaulo * to not receive these frames. 637251538Srpaulo */ 638287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 639251538Srpaulo return (NULL); 640251538Srpaulo } 641271303Skevlo if (pktlen < sizeof(*wh) || pktlen > MCLBYTES) { 642287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 643271303Skevlo return (NULL); 644271303Skevlo } 645251538Srpaulo 646251538Srpaulo rate = MS(rxdw3, R92C_RXDW3_RATE); 647251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 648251538Srpaulo 649251538Srpaulo /* Get RSSI from PHY status descriptor if present. */ 650251538Srpaulo if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 651281069Srpaulo if (sc->chip & URTWN_CHIP_88E) 652264912Skevlo rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 653264912Skevlo else 654264912Skevlo rssi = urtwn_get_rssi(sc, rate, &stat[1]); 655251538Srpaulo /* Update our average RSSI. */ 656251538Srpaulo urtwn_update_avgrssi(sc, rate, rssi); 657252405Srpaulo /* 658252405Srpaulo * Convert the RSSI to a range that will be accepted 659252405Srpaulo * by net80211. 660252405Srpaulo */ 661252405Srpaulo rssi = URTWN_RSSI(rssi); 662251538Srpaulo } 663251538Srpaulo 664260463Skevlo m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 665251538Srpaulo if (m == NULL) { 666251538Srpaulo device_printf(sc->sc_dev, "could not create RX mbuf\n"); 667251538Srpaulo return (NULL); 668251538Srpaulo } 669251538Srpaulo 670251538Srpaulo /* Finalize mbuf. */ 671251538Srpaulo wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 672251538Srpaulo memcpy(mtod(m, uint8_t *), wh, pktlen); 673251538Srpaulo m->m_pkthdr.len = m->m_len = pktlen; 674251538Srpaulo 675251538Srpaulo if (ieee80211_radiotap_active(ic)) { 676251538Srpaulo struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 677251538Srpaulo 678251538Srpaulo tap->wr_flags = 0; 679251538Srpaulo /* Map HW rate index to 802.11 rate. */ 680251538Srpaulo if (!(rxdw3 & R92C_RXDW3_HT)) { 681251538Srpaulo switch (rate) { 682251538Srpaulo /* CCK. */ 683251538Srpaulo case 0: tap->wr_rate = 2; break; 684251538Srpaulo case 1: tap->wr_rate = 4; break; 685251538Srpaulo case 2: tap->wr_rate = 11; break; 686251538Srpaulo case 3: tap->wr_rate = 22; break; 687251538Srpaulo /* OFDM. */ 688251538Srpaulo case 4: tap->wr_rate = 12; break; 689251538Srpaulo case 5: tap->wr_rate = 18; break; 690251538Srpaulo case 6: tap->wr_rate = 24; break; 691251538Srpaulo case 7: tap->wr_rate = 36; break; 692251538Srpaulo case 8: tap->wr_rate = 48; break; 693251538Srpaulo case 9: tap->wr_rate = 72; break; 694251538Srpaulo case 10: tap->wr_rate = 96; break; 695251538Srpaulo case 11: tap->wr_rate = 108; break; 696251538Srpaulo } 697251538Srpaulo } else if (rate >= 12) { /* MCS0~15. */ 698251538Srpaulo /* Bit 7 set means HT MCS instead of rate. */ 699251538Srpaulo tap->wr_rate = 0x80 | (rate - 12); 700251538Srpaulo } 701251538Srpaulo tap->wr_dbm_antsignal = rssi; 702251538Srpaulo tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 703251538Srpaulo tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 704251538Srpaulo } 705251538Srpaulo 706251538Srpaulo *rssi_p = rssi; 707251538Srpaulo 708251538Srpaulo return (m); 709251538Srpaulo} 710251538Srpaulo 711251538Srpaulostatic struct mbuf * 712251538Srpaulourtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 713251538Srpaulo int8_t *nf) 714251538Srpaulo{ 715251538Srpaulo struct urtwn_softc *sc = data->sc; 716287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 717251538Srpaulo struct r92c_rx_stat *stat; 718251538Srpaulo struct mbuf *m, *m0 = NULL, *prevm = NULL; 719251538Srpaulo uint32_t rxdw0; 720251538Srpaulo uint8_t *buf; 721251538Srpaulo int len, totlen, pktlen, infosz, npkts; 722251538Srpaulo 723251538Srpaulo usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 724251538Srpaulo 725251538Srpaulo if (len < sizeof(*stat)) { 726287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 727251538Srpaulo return (NULL); 728251538Srpaulo } 729251538Srpaulo 730251538Srpaulo buf = data->buf; 731251538Srpaulo /* Get the number of encapsulated frames. */ 732251538Srpaulo stat = (struct r92c_rx_stat *)buf; 733251538Srpaulo npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 734251538Srpaulo DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 735251538Srpaulo 736251538Srpaulo /* Process all of them. */ 737251538Srpaulo while (npkts-- > 0) { 738251538Srpaulo if (len < sizeof(*stat)) 739251538Srpaulo break; 740251538Srpaulo stat = (struct r92c_rx_stat *)buf; 741251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 742251538Srpaulo 743251538Srpaulo pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 744251538Srpaulo if (pktlen == 0) 745251538Srpaulo break; 746251538Srpaulo 747251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 748251538Srpaulo 749251538Srpaulo /* Make sure everything fits in xfer. */ 750251538Srpaulo totlen = sizeof(*stat) + infosz + pktlen; 751251538Srpaulo if (totlen > len) 752251538Srpaulo break; 753251538Srpaulo 754251538Srpaulo m = urtwn_rx_frame(sc, buf, pktlen, rssi); 755251538Srpaulo if (m0 == NULL) 756251538Srpaulo m0 = m; 757251538Srpaulo if (prevm == NULL) 758251538Srpaulo prevm = m; 759251538Srpaulo else { 760251538Srpaulo prevm->m_next = m; 761251538Srpaulo prevm = m; 762251538Srpaulo } 763251538Srpaulo 764251538Srpaulo /* Next chunk is 128-byte aligned. */ 765251538Srpaulo totlen = (totlen + 127) & ~127; 766251538Srpaulo buf += totlen; 767251538Srpaulo len -= totlen; 768251538Srpaulo } 769251538Srpaulo 770251538Srpaulo return (m0); 771251538Srpaulo} 772251538Srpaulo 773251538Srpaulostatic void 774251538Srpaulourtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 775251538Srpaulo{ 776251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 777287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 778251538Srpaulo struct ieee80211_frame *wh; 779251538Srpaulo struct ieee80211_node *ni; 780251538Srpaulo struct mbuf *m = NULL, *next; 781251538Srpaulo struct urtwn_data *data; 782251538Srpaulo int8_t nf; 783251538Srpaulo int rssi = 1; 784251538Srpaulo 785251538Srpaulo URTWN_ASSERT_LOCKED(sc); 786251538Srpaulo 787251538Srpaulo switch (USB_GET_STATE(xfer)) { 788251538Srpaulo case USB_ST_TRANSFERRED: 789251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 790251538Srpaulo if (data == NULL) 791251538Srpaulo goto tr_setup; 792251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 793251538Srpaulo m = urtwn_rxeof(xfer, data, &rssi, &nf); 794251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 795251538Srpaulo /* FALLTHROUGH */ 796251538Srpaulo case USB_ST_SETUP: 797251538Srpaulotr_setup: 798251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_inactive); 799251538Srpaulo if (data == NULL) { 800251538Srpaulo KASSERT(m == NULL, ("mbuf isn't NULL")); 801251538Srpaulo return; 802251538Srpaulo } 803251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 804251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 805251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, 806251538Srpaulo usbd_xfer_max_len(xfer)); 807251538Srpaulo usbd_transfer_submit(xfer); 808251538Srpaulo 809251538Srpaulo /* 810251538Srpaulo * To avoid LOR we should unlock our private mutex here to call 811251538Srpaulo * ieee80211_input() because here is at the end of a USB 812251538Srpaulo * callback and safe to unlock. 813251538Srpaulo */ 814251538Srpaulo URTWN_UNLOCK(sc); 815251538Srpaulo while (m != NULL) { 816251538Srpaulo next = m->m_next; 817251538Srpaulo m->m_next = NULL; 818251538Srpaulo wh = mtod(m, struct ieee80211_frame *); 819251538Srpaulo ni = ieee80211_find_rxnode(ic, 820251538Srpaulo (struct ieee80211_frame_min *)wh); 821251538Srpaulo nf = URTWN_NOISE_FLOOR; 822251538Srpaulo if (ni != NULL) { 823251538Srpaulo (void)ieee80211_input(ni, m, rssi, nf); 824251538Srpaulo ieee80211_free_node(ni); 825251538Srpaulo } else 826251538Srpaulo (void)ieee80211_input_all(ic, m, rssi, nf); 827251538Srpaulo m = next; 828251538Srpaulo } 829251538Srpaulo URTWN_LOCK(sc); 830251538Srpaulo break; 831251538Srpaulo default: 832251538Srpaulo /* needs it to the inactive queue due to a error. */ 833251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 834251538Srpaulo if (data != NULL) { 835251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 836251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 837251538Srpaulo } 838251538Srpaulo if (error != USB_ERR_CANCELLED) { 839251538Srpaulo usbd_xfer_set_stall(xfer); 840287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 841251538Srpaulo goto tr_setup; 842251538Srpaulo } 843251538Srpaulo break; 844251538Srpaulo } 845251538Srpaulo} 846251538Srpaulo 847251538Srpaulostatic void 848251538Srpaulourtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 849251538Srpaulo{ 850251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 851251538Srpaulo 852251538Srpaulo URTWN_ASSERT_LOCKED(sc); 853287197Sglebius /* XXX status? */ 854287197Sglebius ieee80211_tx_complete(data->ni, data->m, 0); 855287197Sglebius data->ni = NULL; 856287197Sglebius data->m = NULL; 857251538Srpaulo sc->sc_txtimer = 0; 858251538Srpaulo} 859251538Srpaulo 860251538Srpaulostatic void 861251538Srpaulourtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 862251538Srpaulo{ 863251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 864251538Srpaulo struct urtwn_data *data; 865251538Srpaulo 866251538Srpaulo URTWN_ASSERT_LOCKED(sc); 867251538Srpaulo 868251538Srpaulo switch (USB_GET_STATE(xfer)){ 869251538Srpaulo case USB_ST_TRANSFERRED: 870251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 871251538Srpaulo if (data == NULL) 872251538Srpaulo goto tr_setup; 873251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 874251538Srpaulo urtwn_txeof(xfer, data); 875251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 876251538Srpaulo /* FALLTHROUGH */ 877251538Srpaulo case USB_ST_SETUP: 878251538Srpaulotr_setup: 879251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_pending); 880251538Srpaulo if (data == NULL) { 881251538Srpaulo DPRINTF("%s: empty pending queue\n", __func__); 882251538Srpaulo return; 883251538Srpaulo } 884251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 885251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 886251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 887251538Srpaulo usbd_transfer_submit(xfer); 888287197Sglebius urtwn_start(sc); 889251538Srpaulo break; 890251538Srpaulo default: 891251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 892251538Srpaulo if (data == NULL) 893251538Srpaulo goto tr_setup; 894251538Srpaulo if (data->ni != NULL) { 895287197Sglebius if_inc_counter(data->ni->ni_vap->iv_ifp, 896287197Sglebius IFCOUNTER_OERRORS, 1); 897251538Srpaulo ieee80211_free_node(data->ni); 898251538Srpaulo data->ni = NULL; 899251538Srpaulo } 900251538Srpaulo if (error != USB_ERR_CANCELLED) { 901251538Srpaulo usbd_xfer_set_stall(xfer); 902251538Srpaulo goto tr_setup; 903251538Srpaulo } 904251538Srpaulo break; 905251538Srpaulo } 906251538Srpaulo} 907251538Srpaulo 908251538Srpaulostatic struct urtwn_data * 909251538Srpaulo_urtwn_getbuf(struct urtwn_softc *sc) 910251538Srpaulo{ 911251538Srpaulo struct urtwn_data *bf; 912251538Srpaulo 913251538Srpaulo bf = STAILQ_FIRST(&sc->sc_tx_inactive); 914251538Srpaulo if (bf != NULL) 915251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 916251538Srpaulo else 917251538Srpaulo bf = NULL; 918251538Srpaulo if (bf == NULL) 919251538Srpaulo DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 920251538Srpaulo return (bf); 921251538Srpaulo} 922251538Srpaulo 923251538Srpaulostatic struct urtwn_data * 924251538Srpaulourtwn_getbuf(struct urtwn_softc *sc) 925251538Srpaulo{ 926251538Srpaulo struct urtwn_data *bf; 927251538Srpaulo 928251538Srpaulo URTWN_ASSERT_LOCKED(sc); 929251538Srpaulo 930251538Srpaulo bf = _urtwn_getbuf(sc); 931287197Sglebius if (bf == NULL) 932251538Srpaulo DPRINTF("%s: stop queue\n", __func__); 933251538Srpaulo return (bf); 934251538Srpaulo} 935251538Srpaulo 936251538Srpaulostatic int 937251538Srpaulourtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 938251538Srpaulo int len) 939251538Srpaulo{ 940251538Srpaulo usb_device_request_t req; 941251538Srpaulo 942251538Srpaulo req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 943251538Srpaulo req.bRequest = R92C_REQ_REGS; 944251538Srpaulo USETW(req.wValue, addr); 945251538Srpaulo USETW(req.wIndex, 0); 946251538Srpaulo USETW(req.wLength, len); 947251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 948251538Srpaulo} 949251538Srpaulo 950251538Srpaulostatic void 951251538Srpaulourtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 952251538Srpaulo{ 953251538Srpaulo urtwn_write_region_1(sc, addr, &val, 1); 954251538Srpaulo} 955251538Srpaulo 956251538Srpaulo 957251538Srpaulostatic void 958251538Srpaulourtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 959251538Srpaulo{ 960251538Srpaulo val = htole16(val); 961251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 962251538Srpaulo} 963251538Srpaulo 964251538Srpaulostatic void 965251538Srpaulourtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 966251538Srpaulo{ 967251538Srpaulo val = htole32(val); 968251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 969251538Srpaulo} 970251538Srpaulo 971251538Srpaulostatic int 972251538Srpaulourtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 973251538Srpaulo int len) 974251538Srpaulo{ 975251538Srpaulo usb_device_request_t req; 976251538Srpaulo 977251538Srpaulo req.bmRequestType = UT_READ_VENDOR_DEVICE; 978251538Srpaulo req.bRequest = R92C_REQ_REGS; 979251538Srpaulo USETW(req.wValue, addr); 980251538Srpaulo USETW(req.wIndex, 0); 981251538Srpaulo USETW(req.wLength, len); 982251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 983251538Srpaulo} 984251538Srpaulo 985251538Srpaulostatic uint8_t 986251538Srpaulourtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 987251538Srpaulo{ 988251538Srpaulo uint8_t val; 989251538Srpaulo 990251538Srpaulo if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 991251538Srpaulo return (0xff); 992251538Srpaulo return (val); 993251538Srpaulo} 994251538Srpaulo 995251538Srpaulostatic uint16_t 996251538Srpaulourtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 997251538Srpaulo{ 998251538Srpaulo uint16_t val; 999251538Srpaulo 1000251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1001251538Srpaulo return (0xffff); 1002251538Srpaulo return (le16toh(val)); 1003251538Srpaulo} 1004251538Srpaulo 1005251538Srpaulostatic uint32_t 1006251538Srpaulourtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1007251538Srpaulo{ 1008251538Srpaulo uint32_t val; 1009251538Srpaulo 1010251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1011251538Srpaulo return (0xffffffff); 1012251538Srpaulo return (le32toh(val)); 1013251538Srpaulo} 1014251538Srpaulo 1015251538Srpaulostatic int 1016251538Srpaulourtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1017251538Srpaulo{ 1018251538Srpaulo struct r92c_fw_cmd cmd; 1019251538Srpaulo int ntries; 1020251538Srpaulo 1021251538Srpaulo /* Wait for current FW box to be empty. */ 1022251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1023251538Srpaulo if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1024251538Srpaulo break; 1025266472Shselasky urtwn_ms_delay(sc); 1026251538Srpaulo } 1027251538Srpaulo if (ntries == 100) { 1028251538Srpaulo device_printf(sc->sc_dev, 1029251538Srpaulo "could not send firmware command\n"); 1030251538Srpaulo return (ETIMEDOUT); 1031251538Srpaulo } 1032251538Srpaulo memset(&cmd, 0, sizeof(cmd)); 1033251538Srpaulo cmd.id = id; 1034251538Srpaulo if (len > 3) 1035251538Srpaulo cmd.id |= R92C_CMD_FLAG_EXT; 1036251538Srpaulo KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1037251538Srpaulo memcpy(cmd.msg, buf, len); 1038251538Srpaulo 1039251538Srpaulo /* Write the first word last since that will trigger the FW. */ 1040251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1041251538Srpaulo (uint8_t *)&cmd + 4, 2); 1042251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1043251538Srpaulo (uint8_t *)&cmd + 0, 4); 1044251538Srpaulo 1045251538Srpaulo sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1046251538Srpaulo return (0); 1047251538Srpaulo} 1048251538Srpaulo 1049264912Skevlostatic __inline void 1050251538Srpaulourtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1051251538Srpaulo{ 1052264912Skevlo 1053264912Skevlo sc->sc_rf_write(sc, chain, addr, val); 1054264912Skevlo} 1055264912Skevlo 1056264912Skevlostatic void 1057264912Skevlourtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1058264912Skevlo uint32_t val) 1059264912Skevlo{ 1060251538Srpaulo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1061251538Srpaulo SM(R92C_LSSI_PARAM_ADDR, addr) | 1062251538Srpaulo SM(R92C_LSSI_PARAM_DATA, val)); 1063251538Srpaulo} 1064251538Srpaulo 1065264912Skevlostatic void 1066264912Skevlourtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1067264912Skevlouint32_t val) 1068264912Skevlo{ 1069264912Skevlo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1070264912Skevlo SM(R88E_LSSI_PARAM_ADDR, addr) | 1071264912Skevlo SM(R92C_LSSI_PARAM_DATA, val)); 1072264912Skevlo} 1073264912Skevlo 1074251538Srpaulostatic uint32_t 1075251538Srpaulourtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1076251538Srpaulo{ 1077251538Srpaulo uint32_t reg[R92C_MAX_CHAINS], val; 1078251538Srpaulo 1079251538Srpaulo reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1080251538Srpaulo if (chain != 0) 1081251538Srpaulo reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1082251538Srpaulo 1083251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1084251538Srpaulo reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1085266472Shselasky urtwn_ms_delay(sc); 1086251538Srpaulo 1087251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1088251538Srpaulo RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1089251538Srpaulo R92C_HSSI_PARAM2_READ_EDGE); 1090266472Shselasky urtwn_ms_delay(sc); 1091251538Srpaulo 1092251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1093251538Srpaulo reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1094266472Shselasky urtwn_ms_delay(sc); 1095251538Srpaulo 1096251538Srpaulo if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1097251538Srpaulo val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1098251538Srpaulo else 1099251538Srpaulo val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1100251538Srpaulo return (MS(val, R92C_LSSI_READBACK_DATA)); 1101251538Srpaulo} 1102251538Srpaulo 1103251538Srpaulostatic int 1104251538Srpaulourtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1105251538Srpaulo{ 1106251538Srpaulo int ntries; 1107251538Srpaulo 1108251538Srpaulo urtwn_write_4(sc, R92C_LLT_INIT, 1109251538Srpaulo SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1110251538Srpaulo SM(R92C_LLT_INIT_ADDR, addr) | 1111251538Srpaulo SM(R92C_LLT_INIT_DATA, data)); 1112251538Srpaulo /* Wait for write operation to complete. */ 1113251538Srpaulo for (ntries = 0; ntries < 20; ntries++) { 1114251538Srpaulo if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1115251538Srpaulo R92C_LLT_INIT_OP_NO_ACTIVE) 1116251538Srpaulo return (0); 1117266472Shselasky urtwn_ms_delay(sc); 1118251538Srpaulo } 1119251538Srpaulo return (ETIMEDOUT); 1120251538Srpaulo} 1121251538Srpaulo 1122251538Srpaulostatic uint8_t 1123251538Srpaulourtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1124251538Srpaulo{ 1125251538Srpaulo uint32_t reg; 1126251538Srpaulo int ntries; 1127251538Srpaulo 1128251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1129251538Srpaulo reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1130251538Srpaulo reg &= ~R92C_EFUSE_CTRL_VALID; 1131251538Srpaulo urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1132251538Srpaulo /* Wait for read operation to complete. */ 1133251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1134251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1135251538Srpaulo if (reg & R92C_EFUSE_CTRL_VALID) 1136251538Srpaulo return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1137266472Shselasky urtwn_ms_delay(sc); 1138251538Srpaulo } 1139281069Srpaulo device_printf(sc->sc_dev, 1140251538Srpaulo "could not read efuse byte at address 0x%x\n", addr); 1141251538Srpaulo return (0xff); 1142251538Srpaulo} 1143251538Srpaulo 1144251538Srpaulostatic void 1145251538Srpaulourtwn_efuse_read(struct urtwn_softc *sc) 1146251538Srpaulo{ 1147251538Srpaulo uint8_t *rom = (uint8_t *)&sc->rom; 1148251538Srpaulo uint16_t addr = 0; 1149251538Srpaulo uint32_t reg; 1150282623Skevlo uint8_t off, msk; 1151251538Srpaulo int i; 1152251538Srpaulo 1153264912Skevlo urtwn_efuse_switch_power(sc); 1154264912Skevlo 1155251538Srpaulo memset(&sc->rom, 0xff, sizeof(sc->rom)); 1156251538Srpaulo while (addr < 512) { 1157251538Srpaulo reg = urtwn_efuse_read_1(sc, addr); 1158251538Srpaulo if (reg == 0xff) 1159251538Srpaulo break; 1160251538Srpaulo addr++; 1161251538Srpaulo off = reg >> 4; 1162251538Srpaulo msk = reg & 0xf; 1163251538Srpaulo for (i = 0; i < 4; i++) { 1164251538Srpaulo if (msk & (1 << i)) 1165251538Srpaulo continue; 1166251538Srpaulo rom[off * 8 + i * 2 + 0] = 1167251538Srpaulo urtwn_efuse_read_1(sc, addr); 1168251538Srpaulo addr++; 1169251538Srpaulo rom[off * 8 + i * 2 + 1] = 1170251538Srpaulo urtwn_efuse_read_1(sc, addr); 1171251538Srpaulo addr++; 1172251538Srpaulo } 1173251538Srpaulo } 1174251538Srpaulo#ifdef URTWN_DEBUG 1175251538Srpaulo if (urtwn_debug >= 2) { 1176251538Srpaulo /* Dump ROM content. */ 1177251538Srpaulo printf("\n"); 1178251538Srpaulo for (i = 0; i < sizeof(sc->rom); i++) 1179251538Srpaulo printf("%02x:", rom[i]); 1180251538Srpaulo printf("\n"); 1181251538Srpaulo } 1182251538Srpaulo#endif 1183282623Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1184282623Skevlo} 1185281592Skevlo 1186264912Skevlostatic void 1187264912Skevlourtwn_efuse_switch_power(struct urtwn_softc *sc) 1188264912Skevlo{ 1189264912Skevlo uint32_t reg; 1190251538Srpaulo 1191282623Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1192281918Skevlo 1193264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1194264912Skevlo if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1195264912Skevlo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1196264912Skevlo reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1197264912Skevlo } 1198264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1199264912Skevlo if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1200264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1201264912Skevlo reg | R92C_SYS_FUNC_EN_ELDR); 1202264912Skevlo } 1203264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1204264912Skevlo if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1205264912Skevlo (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1206264912Skevlo urtwn_write_2(sc, R92C_SYS_CLKR, 1207264912Skevlo reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1208264912Skevlo } 1209264912Skevlo} 1210264912Skevlo 1211251538Srpaulostatic int 1212251538Srpaulourtwn_read_chipid(struct urtwn_softc *sc) 1213251538Srpaulo{ 1214251538Srpaulo uint32_t reg; 1215251538Srpaulo 1216264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1217264912Skevlo return (0); 1218264912Skevlo 1219251538Srpaulo reg = urtwn_read_4(sc, R92C_SYS_CFG); 1220251538Srpaulo if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1221251538Srpaulo return (EIO); 1222251538Srpaulo 1223251538Srpaulo if (reg & R92C_SYS_CFG_TYPE_92C) { 1224251538Srpaulo sc->chip |= URTWN_CHIP_92C; 1225251538Srpaulo /* Check if it is a castrated 8192C. */ 1226251538Srpaulo if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1227251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID) == 1228251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1229251538Srpaulo sc->chip |= URTWN_CHIP_92C_1T2R; 1230251538Srpaulo } 1231251538Srpaulo if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1232251538Srpaulo sc->chip |= URTWN_CHIP_UMC; 1233251538Srpaulo if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1234251538Srpaulo sc->chip |= URTWN_CHIP_UMC_A_CUT; 1235251538Srpaulo } 1236251538Srpaulo return (0); 1237251538Srpaulo} 1238251538Srpaulo 1239251538Srpaulostatic void 1240251538Srpaulourtwn_read_rom(struct urtwn_softc *sc) 1241251538Srpaulo{ 1242251538Srpaulo struct r92c_rom *rom = &sc->rom; 1243251538Srpaulo 1244251538Srpaulo /* Read full ROM image. */ 1245251538Srpaulo urtwn_efuse_read(sc); 1246251538Srpaulo 1247251538Srpaulo /* XXX Weird but this is what the vendor driver does. */ 1248251538Srpaulo sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1249251538Srpaulo DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1250251538Srpaulo 1251251538Srpaulo sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1252251538Srpaulo 1253251538Srpaulo sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1254251538Srpaulo DPRINTF("regulatory type=%d\n", sc->regulatory); 1255287197Sglebius IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1256251538Srpaulo 1257264912Skevlo sc->sc_rf_write = urtwn_r92c_rf_write; 1258264912Skevlo sc->sc_power_on = urtwn_r92c_power_on; 1259264912Skevlo sc->sc_dma_init = urtwn_r92c_dma_init; 1260251538Srpaulo} 1261251538Srpaulo 1262264912Skevlostatic void 1263264912Skevlourtwn_r88e_read_rom(struct urtwn_softc *sc) 1264264912Skevlo{ 1265264912Skevlo uint8_t *rom = sc->r88e_rom; 1266264912Skevlo uint16_t addr = 0; 1267264912Skevlo uint32_t reg; 1268264912Skevlo uint8_t off, msk, tmp; 1269264912Skevlo int i; 1270264912Skevlo 1271264982Sandreast off = 0; 1272264912Skevlo urtwn_efuse_switch_power(sc); 1273264912Skevlo 1274264912Skevlo /* Read full ROM image. */ 1275264912Skevlo memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1276281918Skevlo while (addr < 512) { 1277264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1278264912Skevlo if (reg == 0xff) 1279264912Skevlo break; 1280264912Skevlo addr++; 1281264912Skevlo if ((reg & 0x1f) == 0x0f) { 1282264912Skevlo tmp = (reg & 0xe0) >> 5; 1283264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1284264912Skevlo if ((reg & 0x0f) != 0x0f) 1285264912Skevlo off = ((reg & 0xf0) >> 1) | tmp; 1286264912Skevlo addr++; 1287264912Skevlo } else 1288264912Skevlo off = reg >> 4; 1289264912Skevlo msk = reg & 0xf; 1290264912Skevlo for (i = 0; i < 4; i++) { 1291264912Skevlo if (msk & (1 << i)) 1292264912Skevlo continue; 1293264912Skevlo rom[off * 8 + i * 2 + 0] = 1294264912Skevlo urtwn_efuse_read_1(sc, addr); 1295264912Skevlo addr++; 1296264912Skevlo rom[off * 8 + i * 2 + 1] = 1297264912Skevlo urtwn_efuse_read_1(sc, addr); 1298264912Skevlo addr++; 1299264912Skevlo } 1300264912Skevlo } 1301264912Skevlo 1302281918Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1303281918Skevlo 1304264912Skevlo addr = 0x10; 1305264912Skevlo for (i = 0; i < 6; i++) 1306264912Skevlo sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1307264912Skevlo for (i = 0; i < 5; i++) 1308264912Skevlo sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1309264912Skevlo sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1310264912Skevlo if (sc->bw20_tx_pwr_diff & 0x08) 1311264912Skevlo sc->bw20_tx_pwr_diff |= 0xf0; 1312264912Skevlo sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1313264912Skevlo if (sc->ofdm_tx_pwr_diff & 0x08) 1314264912Skevlo sc->ofdm_tx_pwr_diff |= 0xf0; 1315264912Skevlo sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1316287197Sglebius IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &sc->r88e_rom[0xd7]); 1317264912Skevlo 1318264912Skevlo sc->sc_rf_write = urtwn_r88e_rf_write; 1319264912Skevlo sc->sc_power_on = urtwn_r88e_power_on; 1320264912Skevlo sc->sc_dma_init = urtwn_r88e_dma_init; 1321264912Skevlo} 1322264912Skevlo 1323251538Srpaulo/* 1324251538Srpaulo * Initialize rate adaptation in firmware. 1325251538Srpaulo */ 1326251538Srpaulostatic int 1327251538Srpaulourtwn_ra_init(struct urtwn_softc *sc) 1328251538Srpaulo{ 1329251538Srpaulo static const uint8_t map[] = 1330251538Srpaulo { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1331287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1332251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1333251538Srpaulo struct ieee80211_node *ni; 1334251538Srpaulo struct ieee80211_rateset *rs; 1335251538Srpaulo struct r92c_fw_cmd_macid_cfg cmd; 1336251538Srpaulo uint32_t rates, basicrates; 1337251538Srpaulo uint8_t mode; 1338251538Srpaulo int maxrate, maxbasicrate, error, i, j; 1339251538Srpaulo 1340251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1341251538Srpaulo rs = &ni->ni_rates; 1342251538Srpaulo 1343251538Srpaulo /* Get normal and basic rates mask. */ 1344251538Srpaulo rates = basicrates = 0; 1345251538Srpaulo maxrate = maxbasicrate = 0; 1346251538Srpaulo for (i = 0; i < rs->rs_nrates; i++) { 1347251538Srpaulo /* Convert 802.11 rate to HW rate index. */ 1348251538Srpaulo for (j = 0; j < nitems(map); j++) 1349251538Srpaulo if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1350251538Srpaulo break; 1351251538Srpaulo if (j == nitems(map)) /* Unknown rate, skip. */ 1352251538Srpaulo continue; 1353251538Srpaulo rates |= 1 << j; 1354251538Srpaulo if (j > maxrate) 1355251538Srpaulo maxrate = j; 1356251538Srpaulo if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1357251538Srpaulo basicrates |= 1 << j; 1358251538Srpaulo if (j > maxbasicrate) 1359251538Srpaulo maxbasicrate = j; 1360251538Srpaulo } 1361251538Srpaulo } 1362251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1363251538Srpaulo mode = R92C_RAID_11B; 1364251538Srpaulo else 1365251538Srpaulo mode = R92C_RAID_11BG; 1366251538Srpaulo DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1367251538Srpaulo mode, rates, basicrates); 1368251538Srpaulo 1369251538Srpaulo /* Set rates mask for group addressed frames. */ 1370251538Srpaulo cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1371251538Srpaulo cmd.mask = htole32(mode << 28 | basicrates); 1372251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1373251538Srpaulo if (error != 0) { 1374252401Srpaulo ieee80211_free_node(ni); 1375251538Srpaulo device_printf(sc->sc_dev, 1376251538Srpaulo "could not add broadcast station\n"); 1377251538Srpaulo return (error); 1378251538Srpaulo } 1379251538Srpaulo /* Set initial MRR rate. */ 1380251538Srpaulo DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1381251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1382251538Srpaulo maxbasicrate); 1383251538Srpaulo 1384251538Srpaulo /* Set rates mask for unicast frames. */ 1385251538Srpaulo cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1386251538Srpaulo cmd.mask = htole32(mode << 28 | rates); 1387251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1388251538Srpaulo if (error != 0) { 1389252401Srpaulo ieee80211_free_node(ni); 1390251538Srpaulo device_printf(sc->sc_dev, "could not add BSS station\n"); 1391251538Srpaulo return (error); 1392251538Srpaulo } 1393251538Srpaulo /* Set initial MRR rate. */ 1394251538Srpaulo DPRINTF("maxrate=%d\n", maxrate); 1395251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1396251538Srpaulo maxrate); 1397251538Srpaulo 1398251538Srpaulo /* Indicate highest supported rate. */ 1399252403Srpaulo ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1400252401Srpaulo ieee80211_free_node(ni); 1401252401Srpaulo 1402251538Srpaulo return (0); 1403251538Srpaulo} 1404251538Srpaulo 1405251538Srpaulovoid 1406251538Srpaulourtwn_tsf_sync_enable(struct urtwn_softc *sc) 1407251538Srpaulo{ 1408287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1409251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1410251538Srpaulo struct ieee80211_node *ni = vap->iv_bss; 1411251538Srpaulo 1412251538Srpaulo uint64_t tsf; 1413251538Srpaulo 1414251538Srpaulo /* Enable TSF synchronization. */ 1415251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1416251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1417251538Srpaulo 1418251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1419251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1420251538Srpaulo 1421251538Srpaulo /* Set initial TSF. */ 1422251538Srpaulo memcpy(&tsf, ni->ni_tstamp.data, 8); 1423251538Srpaulo tsf = le64toh(tsf); 1424251538Srpaulo tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1425251538Srpaulo tsf -= IEEE80211_DUR_TU; 1426251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1427251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1428251538Srpaulo 1429251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1430251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1431251538Srpaulo} 1432251538Srpaulo 1433251538Srpaulostatic void 1434251538Srpaulourtwn_set_led(struct urtwn_softc *sc, int led, int on) 1435251538Srpaulo{ 1436251538Srpaulo uint8_t reg; 1437281069Srpaulo 1438251538Srpaulo if (led == URTWN_LED_LINK) { 1439264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 1440264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1441264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1442264912Skevlo if (!on) { 1443264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1444264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, 1445264912Skevlo reg | R92C_LEDCFG0_DIS); 1446264912Skevlo urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1447264912Skevlo urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1448264912Skevlo 0xfe); 1449264912Skevlo } 1450264912Skevlo } else { 1451264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1452264912Skevlo if (!on) 1453264912Skevlo reg |= R92C_LEDCFG0_DIS; 1454264912Skevlo urtwn_write_1(sc, R92C_LEDCFG0, reg); 1455264912Skevlo } 1456264912Skevlo sc->ledlink = on; /* Save LED state. */ 1457251538Srpaulo } 1458251538Srpaulo} 1459251538Srpaulo 1460251538Srpaulostatic int 1461251538Srpaulourtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1462251538Srpaulo{ 1463251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 1464251538Srpaulo struct ieee80211com *ic = vap->iv_ic; 1465286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 1466251538Srpaulo struct ieee80211_node *ni; 1467251538Srpaulo enum ieee80211_state ostate; 1468251538Srpaulo uint32_t reg; 1469251538Srpaulo 1470251538Srpaulo ostate = vap->iv_state; 1471251538Srpaulo DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1472251538Srpaulo ieee80211_state_name[nstate]); 1473251538Srpaulo 1474251538Srpaulo IEEE80211_UNLOCK(ic); 1475251538Srpaulo URTWN_LOCK(sc); 1476251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 1477251538Srpaulo 1478251538Srpaulo if (ostate == IEEE80211_S_RUN) { 1479251538Srpaulo /* Turn link LED off. */ 1480251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1481251538Srpaulo 1482251538Srpaulo /* Set media status to 'No Link'. */ 1483251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 1484251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1485251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 1486251538Srpaulo 1487251538Srpaulo /* Stop Rx of data frames. */ 1488251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1489251538Srpaulo 1490251538Srpaulo /* Rest TSF. */ 1491251538Srpaulo urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1492251538Srpaulo 1493251538Srpaulo /* Disable TSF synchronization. */ 1494251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1495251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | 1496251538Srpaulo R92C_BCN_CTRL_DIS_TSF_UDT0); 1497251538Srpaulo 1498251538Srpaulo /* Reset EDCA parameters. */ 1499251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1500251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1501251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1502251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1503251538Srpaulo } 1504251538Srpaulo 1505251538Srpaulo switch (nstate) { 1506251538Srpaulo case IEEE80211_S_INIT: 1507251538Srpaulo /* Turn link LED off. */ 1508251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1509251538Srpaulo break; 1510251538Srpaulo case IEEE80211_S_SCAN: 1511251538Srpaulo if (ostate != IEEE80211_S_SCAN) { 1512251538Srpaulo /* Allow Rx from any BSSID. */ 1513251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1514251538Srpaulo urtwn_read_4(sc, R92C_RCR) & 1515251538Srpaulo ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1516251538Srpaulo 1517251538Srpaulo /* Set gain for scanning. */ 1518251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1519251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1520251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1521251538Srpaulo 1522264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1523264912Skevlo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1524264912Skevlo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1525264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1526264912Skevlo } 1527251538Srpaulo } 1528251538Srpaulo /* Pause AC Tx queues. */ 1529251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 1530251538Srpaulo urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1531251538Srpaulo break; 1532251538Srpaulo case IEEE80211_S_AUTH: 1533251538Srpaulo /* Set initial gain under link. */ 1534251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1535251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1536251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1537251538Srpaulo 1538264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1539264912Skevlo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1540264912Skevlo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1541264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1542264912Skevlo } 1543251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 1544251538Srpaulo break; 1545251538Srpaulo case IEEE80211_S_RUN: 1546251538Srpaulo if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1547251538Srpaulo /* Enable Rx of data frames. */ 1548251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1549251538Srpaulo 1550251538Srpaulo /* Turn link LED on. */ 1551251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1552251538Srpaulo break; 1553251538Srpaulo } 1554251538Srpaulo 1555251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1556251538Srpaulo /* Set media status to 'Associated'. */ 1557251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 1558251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1559251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 1560251538Srpaulo 1561251538Srpaulo /* Set BSSID. */ 1562251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1563251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1564251538Srpaulo 1565251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1566251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1567251538Srpaulo else /* 802.11b/g */ 1568251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1569251538Srpaulo 1570251538Srpaulo /* Enable Rx of data frames. */ 1571251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1572251538Srpaulo 1573251538Srpaulo /* Flush all AC queues. */ 1574251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0); 1575251538Srpaulo 1576251538Srpaulo /* Set beacon interval. */ 1577251538Srpaulo urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1578251538Srpaulo 1579251538Srpaulo /* Allow Rx from our BSSID only. */ 1580251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1581251538Srpaulo urtwn_read_4(sc, R92C_RCR) | 1582251538Srpaulo R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1583251538Srpaulo 1584251538Srpaulo /* Enable TSF synchronization. */ 1585251538Srpaulo urtwn_tsf_sync_enable(sc); 1586251538Srpaulo 1587251538Srpaulo urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1588251538Srpaulo urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1589251538Srpaulo urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1590251538Srpaulo urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1591251538Srpaulo urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1592251538Srpaulo urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1593251538Srpaulo 1594251538Srpaulo /* Intialize rate adaptation. */ 1595264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1596264912Skevlo ni->ni_txrate = 1597264912Skevlo ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1598281069Srpaulo else 1599264912Skevlo urtwn_ra_init(sc); 1600251538Srpaulo /* Turn link LED on. */ 1601251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1602251538Srpaulo 1603251538Srpaulo sc->avg_pwdb = -1; /* Reset average RSSI. */ 1604251538Srpaulo /* Reset temperature calibration state machine. */ 1605251538Srpaulo sc->thcal_state = 0; 1606251538Srpaulo sc->thcal_lctemp = 0; 1607251538Srpaulo ieee80211_free_node(ni); 1608251538Srpaulo break; 1609251538Srpaulo default: 1610251538Srpaulo break; 1611251538Srpaulo } 1612251538Srpaulo URTWN_UNLOCK(sc); 1613251538Srpaulo IEEE80211_LOCK(ic); 1614251538Srpaulo return(uvp->newstate(vap, nstate, arg)); 1615251538Srpaulo} 1616251538Srpaulo 1617251538Srpaulostatic void 1618251538Srpaulourtwn_watchdog(void *arg) 1619251538Srpaulo{ 1620251538Srpaulo struct urtwn_softc *sc = arg; 1621251538Srpaulo 1622251538Srpaulo if (sc->sc_txtimer > 0) { 1623251538Srpaulo if (--sc->sc_txtimer == 0) { 1624251538Srpaulo device_printf(sc->sc_dev, "device timeout\n"); 1625287197Sglebius counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1626251538Srpaulo return; 1627251538Srpaulo } 1628251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1629251538Srpaulo } 1630251538Srpaulo} 1631251538Srpaulo 1632251538Srpaulostatic void 1633251538Srpaulourtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1634251538Srpaulo{ 1635251538Srpaulo int pwdb; 1636251538Srpaulo 1637251538Srpaulo /* Convert antenna signal to percentage. */ 1638251538Srpaulo if (rssi <= -100 || rssi >= 20) 1639251538Srpaulo pwdb = 0; 1640251538Srpaulo else if (rssi >= 0) 1641251538Srpaulo pwdb = 100; 1642251538Srpaulo else 1643251538Srpaulo pwdb = 100 + rssi; 1644264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1645264912Skevlo if (rate <= 3) { 1646264912Skevlo /* CCK gain is smaller than OFDM/MCS gain. */ 1647264912Skevlo pwdb += 6; 1648264912Skevlo if (pwdb > 100) 1649264912Skevlo pwdb = 100; 1650264912Skevlo if (pwdb <= 14) 1651264912Skevlo pwdb -= 4; 1652264912Skevlo else if (pwdb <= 26) 1653264912Skevlo pwdb -= 8; 1654264912Skevlo else if (pwdb <= 34) 1655264912Skevlo pwdb -= 6; 1656264912Skevlo else if (pwdb <= 42) 1657264912Skevlo pwdb -= 2; 1658264912Skevlo } 1659251538Srpaulo } 1660251538Srpaulo if (sc->avg_pwdb == -1) /* Init. */ 1661251538Srpaulo sc->avg_pwdb = pwdb; 1662251538Srpaulo else if (sc->avg_pwdb < pwdb) 1663251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1664251538Srpaulo else 1665251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1666251538Srpaulo DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1667251538Srpaulo} 1668251538Srpaulo 1669251538Srpaulostatic int8_t 1670251538Srpaulourtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1671251538Srpaulo{ 1672251538Srpaulo static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1673251538Srpaulo struct r92c_rx_phystat *phy; 1674251538Srpaulo struct r92c_rx_cck *cck; 1675251538Srpaulo uint8_t rpt; 1676251538Srpaulo int8_t rssi; 1677251538Srpaulo 1678251538Srpaulo if (rate <= 3) { 1679251538Srpaulo cck = (struct r92c_rx_cck *)physt; 1680251538Srpaulo if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1681251538Srpaulo rpt = (cck->agc_rpt >> 5) & 0x3; 1682251538Srpaulo rssi = (cck->agc_rpt & 0x1f) << 1; 1683251538Srpaulo } else { 1684251538Srpaulo rpt = (cck->agc_rpt >> 6) & 0x3; 1685251538Srpaulo rssi = cck->agc_rpt & 0x3e; 1686251538Srpaulo } 1687251538Srpaulo rssi = cckoff[rpt] - rssi; 1688251538Srpaulo } else { /* OFDM/HT. */ 1689251538Srpaulo phy = (struct r92c_rx_phystat *)physt; 1690251538Srpaulo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1691251538Srpaulo } 1692251538Srpaulo return (rssi); 1693251538Srpaulo} 1694251538Srpaulo 1695264912Skevlostatic int8_t 1696264912Skevlourtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1697264912Skevlo{ 1698264912Skevlo struct r92c_rx_phystat *phy; 1699264912Skevlo struct r88e_rx_cck *cck; 1700264912Skevlo uint8_t cck_agc_rpt, lna_idx, vga_idx; 1701264912Skevlo int8_t rssi; 1702264912Skevlo 1703264972Skevlo rssi = 0; 1704264912Skevlo if (rate <= 3) { 1705264912Skevlo cck = (struct r88e_rx_cck *)physt; 1706264912Skevlo cck_agc_rpt = cck->agc_rpt; 1707264912Skevlo lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1708281069Srpaulo vga_idx = cck_agc_rpt & 0x1f; 1709264912Skevlo switch (lna_idx) { 1710264912Skevlo case 7: 1711264912Skevlo if (vga_idx <= 27) 1712264912Skevlo rssi = -100 + 2* (27 - vga_idx); 1713264912Skevlo else 1714264912Skevlo rssi = -100; 1715264912Skevlo break; 1716264912Skevlo case 6: 1717264912Skevlo rssi = -48 + 2 * (2 - vga_idx); 1718264912Skevlo break; 1719264912Skevlo case 5: 1720264912Skevlo rssi = -42 + 2 * (7 - vga_idx); 1721264912Skevlo break; 1722264912Skevlo case 4: 1723264912Skevlo rssi = -36 + 2 * (7 - vga_idx); 1724264912Skevlo break; 1725264912Skevlo case 3: 1726264912Skevlo rssi = -24 + 2 * (7 - vga_idx); 1727264912Skevlo break; 1728264912Skevlo case 2: 1729264912Skevlo rssi = -12 + 2 * (5 - vga_idx); 1730264912Skevlo break; 1731264912Skevlo case 1: 1732264912Skevlo rssi = 8 - (2 * vga_idx); 1733264912Skevlo break; 1734264912Skevlo case 0: 1735264912Skevlo rssi = 14 - (2 * vga_idx); 1736264912Skevlo break; 1737264912Skevlo } 1738264912Skevlo rssi += 6; 1739264912Skevlo } else { /* OFDM/HT. */ 1740264912Skevlo phy = (struct r92c_rx_phystat *)physt; 1741264912Skevlo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1742264912Skevlo } 1743264912Skevlo return (rssi); 1744264912Skevlo} 1745264912Skevlo 1746264912Skevlo 1747251538Srpaulostatic int 1748281069Srpaulourtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1749251538Srpaulo struct mbuf *m0, struct urtwn_data *data) 1750251538Srpaulo{ 1751251538Srpaulo struct ieee80211_frame *wh; 1752251538Srpaulo struct ieee80211_key *k; 1753287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1754251538Srpaulo struct ieee80211vap *vap = ni->ni_vap; 1755251538Srpaulo struct usb_xfer *xfer; 1756251538Srpaulo struct r92c_tx_desc *txd; 1757251538Srpaulo uint8_t raid, type; 1758251538Srpaulo uint16_t sum; 1759251538Srpaulo int i, hasqos, xferlen; 1760251538Srpaulo struct usb_xfer *urtwn_pipes[4] = { 1761251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BE], 1762251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BK], 1763251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VI], 1764251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VO] 1765251538Srpaulo }; 1766251538Srpaulo 1767251538Srpaulo URTWN_ASSERT_LOCKED(sc); 1768251538Srpaulo 1769251538Srpaulo /* 1770251538Srpaulo * Software crypto. 1771251538Srpaulo */ 1772251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1773264912Skevlo type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1774264912Skevlo 1775260444Skevlo if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1776251538Srpaulo k = ieee80211_crypto_encap(ni, m0); 1777251538Srpaulo if (k == NULL) { 1778251538Srpaulo device_printf(sc->sc_dev, 1779251538Srpaulo "ieee80211_crypto_encap returns NULL.\n"); 1780251538Srpaulo /* XXX we don't expect the fragmented frames */ 1781251538Srpaulo m_freem(m0); 1782251538Srpaulo return (ENOBUFS); 1783251538Srpaulo } 1784251538Srpaulo 1785251538Srpaulo /* in case packet header moved, reset pointer */ 1786251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1787251538Srpaulo } 1788281069Srpaulo 1789264912Skevlo switch (type) { 1790251538Srpaulo case IEEE80211_FC0_TYPE_CTL: 1791251538Srpaulo case IEEE80211_FC0_TYPE_MGT: 1792251538Srpaulo xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1793251538Srpaulo break; 1794251538Srpaulo default: 1795251538Srpaulo KASSERT(M_WME_GETAC(m0) < 4, 1796251538Srpaulo ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1797251538Srpaulo xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1798251538Srpaulo break; 1799251538Srpaulo } 1800281069Srpaulo 1801251538Srpaulo hasqos = 0; 1802251538Srpaulo 1803251538Srpaulo /* Fill Tx descriptor. */ 1804251538Srpaulo txd = (struct r92c_tx_desc *)data->buf; 1805251538Srpaulo memset(txd, 0, sizeof(*txd)); 1806251538Srpaulo 1807251538Srpaulo txd->txdw0 |= htole32( 1808251538Srpaulo SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1809251538Srpaulo SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1810251538Srpaulo R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1811251538Srpaulo if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1812251538Srpaulo txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1813251538Srpaulo if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1814251538Srpaulo type == IEEE80211_FC0_TYPE_DATA) { 1815251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1816251538Srpaulo raid = R92C_RAID_11B; 1817251538Srpaulo else 1818251538Srpaulo raid = R92C_RAID_11BG; 1819264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 1820264912Skevlo txd->txdw1 |= htole32( 1821264912Skevlo SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1822264912Skevlo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1823264912Skevlo SM(R92C_TXDW1_RAID, raid)); 1824264912Skevlo txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1825264912Skevlo } else { 1826264912Skevlo txd->txdw1 |= htole32( 1827264912Skevlo SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1828264912Skevlo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1829264912Skevlo SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1830264912Skevlo } 1831251538Srpaulo if (ic->ic_flags & IEEE80211_F_USEPROT) { 1832251538Srpaulo if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1833251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1834251538Srpaulo R92C_TXDW4_HWRTSEN); 1835251538Srpaulo } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1836251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1837251538Srpaulo R92C_TXDW4_HWRTSEN); 1838251538Srpaulo } 1839251538Srpaulo } 1840251538Srpaulo /* Send RTS at OFDM24. */ 1841251538Srpaulo txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1842251538Srpaulo txd->txdw5 |= htole32(0x0001ff00); 1843251538Srpaulo /* Send data at OFDM54. */ 1844282623Skevlo txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1845251538Srpaulo } else { 1846251538Srpaulo txd->txdw1 |= htole32( 1847251538Srpaulo SM(R92C_TXDW1_MACID, 0) | 1848251538Srpaulo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1849251538Srpaulo SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1850251538Srpaulo 1851251538Srpaulo /* Force CCK1. */ 1852251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1853251538Srpaulo txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1854251538Srpaulo } 1855251538Srpaulo /* Set sequence number (already little endian). */ 1856251538Srpaulo txd->txdseq |= *(uint16_t *)wh->i_seq; 1857251538Srpaulo 1858251538Srpaulo if (!hasqos) { 1859251538Srpaulo /* Use HW sequence numbering for non-QoS frames. */ 1860251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1861251538Srpaulo txd->txdseq |= htole16(0x8000); 1862251538Srpaulo } else 1863251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1864251538Srpaulo 1865251538Srpaulo /* Compute Tx descriptor checksum. */ 1866251538Srpaulo sum = 0; 1867251538Srpaulo for (i = 0; i < sizeof(*txd) / 2; i++) 1868251538Srpaulo sum ^= ((uint16_t *)txd)[i]; 1869251538Srpaulo txd->txdsum = sum; /* NB: already little endian. */ 1870251538Srpaulo 1871251538Srpaulo if (ieee80211_radiotap_active_vap(vap)) { 1872251538Srpaulo struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1873251538Srpaulo 1874251538Srpaulo tap->wt_flags = 0; 1875251538Srpaulo tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1876251538Srpaulo tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1877251538Srpaulo ieee80211_radiotap_tx(vap, m0); 1878251538Srpaulo } 1879251538Srpaulo 1880251538Srpaulo xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1881251538Srpaulo m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1882251538Srpaulo 1883251538Srpaulo data->buflen = xferlen; 1884251538Srpaulo data->ni = ni; 1885251538Srpaulo data->m = m0; 1886251538Srpaulo 1887251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1888251538Srpaulo usbd_transfer_start(xfer); 1889251538Srpaulo return (0); 1890251538Srpaulo} 1891251538Srpaulo 1892287197Sglebiusstatic int 1893287197Sglebiusurtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1894251538Srpaulo{ 1895287197Sglebius struct urtwn_softc *sc = ic->ic_softc; 1896287197Sglebius int error; 1897261863Srpaulo 1898261863Srpaulo URTWN_LOCK(sc); 1899287197Sglebius if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1900287197Sglebius URTWN_UNLOCK(sc); 1901287197Sglebius return (ENXIO); 1902287197Sglebius } 1903287197Sglebius error = mbufq_enqueue(&sc->sc_snd, m); 1904287197Sglebius if (error) { 1905287197Sglebius URTWN_UNLOCK(sc); 1906287197Sglebius return (error); 1907287197Sglebius } 1908287197Sglebius urtwn_start(sc); 1909261863Srpaulo URTWN_UNLOCK(sc); 1910287197Sglebius 1911287197Sglebius return (0); 1912261863Srpaulo} 1913261863Srpaulo 1914261863Srpaulostatic void 1915287197Sglebiusurtwn_start(struct urtwn_softc *sc) 1916261863Srpaulo{ 1917251538Srpaulo struct ieee80211_node *ni; 1918251538Srpaulo struct mbuf *m; 1919251538Srpaulo struct urtwn_data *bf; 1920251538Srpaulo 1921261863Srpaulo URTWN_ASSERT_LOCKED(sc); 1922287197Sglebius while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1923251538Srpaulo bf = urtwn_getbuf(sc); 1924251538Srpaulo if (bf == NULL) { 1925287197Sglebius mbufq_prepend(&sc->sc_snd, m); 1926251538Srpaulo break; 1927251538Srpaulo } 1928251538Srpaulo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1929251538Srpaulo m->m_pkthdr.rcvif = NULL; 1930251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 1931287197Sglebius if_inc_counter(ni->ni_vap->iv_ifp, 1932287197Sglebius IFCOUNTER_OERRORS, 1); 1933251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1934251538Srpaulo ieee80211_free_node(ni); 1935251538Srpaulo break; 1936251538Srpaulo } 1937251538Srpaulo sc->sc_txtimer = 5; 1938251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1939251538Srpaulo } 1940251538Srpaulo} 1941251538Srpaulo 1942287197Sglebiusstatic void 1943287197Sglebiusurtwn_parent(struct ieee80211com *ic) 1944251538Srpaulo{ 1945286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 1946287197Sglebius int startall = 0; 1947251538Srpaulo 1948263153Skevlo URTWN_LOCK(sc); 1949287197Sglebius if (sc->sc_flags & URTWN_DETACHED) { 1950287197Sglebius URTWN_UNLOCK(sc); 1951287197Sglebius return; 1952287197Sglebius } 1953287197Sglebius if (ic->ic_nrunning > 0) { 1954287197Sglebius if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1955287197Sglebius urtwn_init(sc); 1956287197Sglebius startall = 1; 1957287197Sglebius } 1958287197Sglebius } else if (sc->sc_flags & URTWN_RUNNING) 1959287197Sglebius urtwn_stop(sc); 1960263153Skevlo URTWN_UNLOCK(sc); 1961263153Skevlo 1962287197Sglebius if (startall) 1963287197Sglebius ieee80211_start_all(ic); 1964251538Srpaulo} 1965251538Srpaulo 1966251538Srpaulostatic int 1967251538Srpaulourtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1968251538Srpaulo int ndata, int maxsz) 1969251538Srpaulo{ 1970251538Srpaulo int i, error; 1971251538Srpaulo 1972251538Srpaulo for (i = 0; i < ndata; i++) { 1973251538Srpaulo struct urtwn_data *dp = &data[i]; 1974251538Srpaulo dp->sc = sc; 1975251538Srpaulo dp->m = NULL; 1976251538Srpaulo dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1977251538Srpaulo if (dp->buf == NULL) { 1978251538Srpaulo device_printf(sc->sc_dev, 1979251538Srpaulo "could not allocate buffer\n"); 1980251538Srpaulo error = ENOMEM; 1981251538Srpaulo goto fail; 1982251538Srpaulo } 1983251538Srpaulo dp->ni = NULL; 1984251538Srpaulo } 1985251538Srpaulo 1986251538Srpaulo return (0); 1987251538Srpaulofail: 1988251538Srpaulo urtwn_free_list(sc, data, ndata); 1989251538Srpaulo return (error); 1990251538Srpaulo} 1991251538Srpaulo 1992251538Srpaulostatic int 1993251538Srpaulourtwn_alloc_rx_list(struct urtwn_softc *sc) 1994251538Srpaulo{ 1995251538Srpaulo int error, i; 1996251538Srpaulo 1997251538Srpaulo error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1998251538Srpaulo URTWN_RXBUFSZ); 1999251538Srpaulo if (error != 0) 2000251538Srpaulo return (error); 2001251538Srpaulo 2002251538Srpaulo STAILQ_INIT(&sc->sc_rx_active); 2003251538Srpaulo STAILQ_INIT(&sc->sc_rx_inactive); 2004251538Srpaulo 2005251538Srpaulo for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 2006251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 2007251538Srpaulo 2008251538Srpaulo return (0); 2009251538Srpaulo} 2010251538Srpaulo 2011251538Srpaulostatic int 2012251538Srpaulourtwn_alloc_tx_list(struct urtwn_softc *sc) 2013251538Srpaulo{ 2014251538Srpaulo int error, i; 2015251538Srpaulo 2016251538Srpaulo error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 2017251538Srpaulo URTWN_TXBUFSZ); 2018251538Srpaulo if (error != 0) 2019251538Srpaulo return (error); 2020251538Srpaulo 2021251538Srpaulo STAILQ_INIT(&sc->sc_tx_active); 2022251538Srpaulo STAILQ_INIT(&sc->sc_tx_inactive); 2023251538Srpaulo STAILQ_INIT(&sc->sc_tx_pending); 2024251538Srpaulo 2025251538Srpaulo for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 2026251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 2027251538Srpaulo 2028251538Srpaulo return (0); 2029251538Srpaulo} 2030251538Srpaulo 2031264912Skevlostatic __inline int 2032251538Srpaulourtwn_power_on(struct urtwn_softc *sc) 2033251538Srpaulo{ 2034264912Skevlo 2035264912Skevlo return sc->sc_power_on(sc); 2036264912Skevlo} 2037264912Skevlo 2038264912Skevlostatic int 2039264912Skevlourtwn_r92c_power_on(struct urtwn_softc *sc) 2040264912Skevlo{ 2041251538Srpaulo uint32_t reg; 2042251538Srpaulo int ntries; 2043251538Srpaulo 2044251538Srpaulo /* Wait for autoload done bit. */ 2045251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2046251538Srpaulo if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2047251538Srpaulo break; 2048266472Shselasky urtwn_ms_delay(sc); 2049251538Srpaulo } 2050251538Srpaulo if (ntries == 1000) { 2051251538Srpaulo device_printf(sc->sc_dev, 2052251538Srpaulo "timeout waiting for chip autoload\n"); 2053251538Srpaulo return (ETIMEDOUT); 2054251538Srpaulo } 2055251538Srpaulo 2056251538Srpaulo /* Unlock ISO/CLK/Power control register. */ 2057251538Srpaulo urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2058251538Srpaulo /* Move SPS into PWM mode. */ 2059251538Srpaulo urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2060266472Shselasky urtwn_ms_delay(sc); 2061251538Srpaulo 2062251538Srpaulo reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2063251538Srpaulo if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2064251538Srpaulo urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2065251538Srpaulo reg | R92C_LDOV12D_CTRL_LDV12_EN); 2066266472Shselasky urtwn_ms_delay(sc); 2067251538Srpaulo urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2068251538Srpaulo urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2069251538Srpaulo ~R92C_SYS_ISO_CTRL_MD2PP); 2070251538Srpaulo } 2071251538Srpaulo 2072251538Srpaulo /* Auto enable WLAN. */ 2073251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2074251538Srpaulo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2075251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2076262822Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2077262822Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2078251538Srpaulo break; 2079266472Shselasky urtwn_ms_delay(sc); 2080251538Srpaulo } 2081251538Srpaulo if (ntries == 1000) { 2082251538Srpaulo device_printf(sc->sc_dev, 2083251538Srpaulo "timeout waiting for MAC auto ON\n"); 2084251538Srpaulo return (ETIMEDOUT); 2085251538Srpaulo } 2086251538Srpaulo 2087251538Srpaulo /* Enable radio, GPIO and LED functions. */ 2088251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2089251538Srpaulo R92C_APS_FSMCO_AFSM_HSUS | 2090251538Srpaulo R92C_APS_FSMCO_PDN_EN | 2091251538Srpaulo R92C_APS_FSMCO_PFM_ALDN); 2092251538Srpaulo /* Release RF digital isolation. */ 2093251538Srpaulo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2094251538Srpaulo urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2095251538Srpaulo 2096251538Srpaulo /* Initialize MAC. */ 2097251538Srpaulo urtwn_write_1(sc, R92C_APSD_CTRL, 2098251538Srpaulo urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2099251538Srpaulo for (ntries = 0; ntries < 200; ntries++) { 2100251538Srpaulo if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2101251538Srpaulo R92C_APSD_CTRL_OFF_STATUS)) 2102251538Srpaulo break; 2103266472Shselasky urtwn_ms_delay(sc); 2104251538Srpaulo } 2105251538Srpaulo if (ntries == 200) { 2106251538Srpaulo device_printf(sc->sc_dev, 2107251538Srpaulo "timeout waiting for MAC initialization\n"); 2108251538Srpaulo return (ETIMEDOUT); 2109251538Srpaulo } 2110251538Srpaulo 2111251538Srpaulo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2112251538Srpaulo reg = urtwn_read_2(sc, R92C_CR); 2113251538Srpaulo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2114251538Srpaulo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2115251538Srpaulo R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2116251538Srpaulo R92C_CR_ENSEC; 2117251538Srpaulo urtwn_write_2(sc, R92C_CR, reg); 2118251538Srpaulo 2119251538Srpaulo urtwn_write_1(sc, 0xfe10, 0x19); 2120251538Srpaulo return (0); 2121251538Srpaulo} 2122251538Srpaulo 2123251538Srpaulostatic int 2124264912Skevlourtwn_r88e_power_on(struct urtwn_softc *sc) 2125264912Skevlo{ 2126264912Skevlo uint32_t reg; 2127264912Skevlo int ntries; 2128264912Skevlo 2129264912Skevlo /* Wait for power ready bit. */ 2130264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2131281918Skevlo if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2132264912Skevlo break; 2133266472Shselasky urtwn_ms_delay(sc); 2134264912Skevlo } 2135264912Skevlo if (ntries == 5000) { 2136264912Skevlo device_printf(sc->sc_dev, 2137264912Skevlo "timeout waiting for chip power up\n"); 2138264912Skevlo return (ETIMEDOUT); 2139264912Skevlo } 2140264912Skevlo 2141264912Skevlo /* Reset BB. */ 2142264912Skevlo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2143264912Skevlo urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2144264912Skevlo R92C_SYS_FUNC_EN_BB_GLB_RST)); 2145264912Skevlo 2146281918Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2147281918Skevlo urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2148264912Skevlo 2149264912Skevlo /* Disable HWPDN. */ 2150281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2151281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2152264912Skevlo 2153264912Skevlo /* Disable WL suspend. */ 2154281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2155281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & 2156281918Skevlo ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2157264912Skevlo 2158281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2159281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2160264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2161281918Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2162281918Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2163264912Skevlo break; 2164266472Shselasky urtwn_ms_delay(sc); 2165264912Skevlo } 2166264912Skevlo if (ntries == 5000) 2167264912Skevlo return (ETIMEDOUT); 2168264912Skevlo 2169264912Skevlo /* Enable LDO normal mode. */ 2170281918Skevlo urtwn_write_1(sc, R92C_LPLDO_CTRL, 2171281918Skevlo urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2172264912Skevlo 2173264912Skevlo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2174264912Skevlo urtwn_write_2(sc, R92C_CR, 0); 2175264912Skevlo reg = urtwn_read_2(sc, R92C_CR); 2176264912Skevlo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2177264912Skevlo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2178264912Skevlo R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2179264912Skevlo urtwn_write_2(sc, R92C_CR, reg); 2180264912Skevlo 2181264912Skevlo return (0); 2182264912Skevlo} 2183264912Skevlo 2184264912Skevlostatic int 2185251538Srpaulourtwn_llt_init(struct urtwn_softc *sc) 2186251538Srpaulo{ 2187264912Skevlo int i, error, page_count, pktbuf_count; 2188251538Srpaulo 2189264912Skevlo page_count = (sc->chip & URTWN_CHIP_88E) ? 2190264912Skevlo R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2191264912Skevlo pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2192264912Skevlo R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2193264912Skevlo 2194264912Skevlo /* Reserve pages [0; page_count]. */ 2195264912Skevlo for (i = 0; i < page_count; i++) { 2196251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2197251538Srpaulo return (error); 2198251538Srpaulo } 2199251538Srpaulo /* NB: 0xff indicates end-of-list. */ 2200251538Srpaulo if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2201251538Srpaulo return (error); 2202251538Srpaulo /* 2203264912Skevlo * Use pages [page_count + 1; pktbuf_count - 1] 2204251538Srpaulo * as ring buffer. 2205251538Srpaulo */ 2206264912Skevlo for (++i; i < pktbuf_count - 1; i++) { 2207251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2208251538Srpaulo return (error); 2209251538Srpaulo } 2210251538Srpaulo /* Make the last page point to the beginning of the ring buffer. */ 2211264912Skevlo error = urtwn_llt_write(sc, i, page_count + 1); 2212251538Srpaulo return (error); 2213251538Srpaulo} 2214251538Srpaulo 2215251538Srpaulostatic void 2216251538Srpaulourtwn_fw_reset(struct urtwn_softc *sc) 2217251538Srpaulo{ 2218251538Srpaulo uint16_t reg; 2219251538Srpaulo int ntries; 2220251538Srpaulo 2221251538Srpaulo /* Tell 8051 to reset itself. */ 2222251538Srpaulo urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2223251538Srpaulo 2224251538Srpaulo /* Wait until 8051 resets by itself. */ 2225251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 2226251538Srpaulo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2227251538Srpaulo if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2228251538Srpaulo return; 2229266472Shselasky urtwn_ms_delay(sc); 2230251538Srpaulo } 2231251538Srpaulo /* Force 8051 reset. */ 2232251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2233251538Srpaulo} 2234251538Srpaulo 2235264912Skevlostatic void 2236264912Skevlourtwn_r88e_fw_reset(struct urtwn_softc *sc) 2237264912Skevlo{ 2238264912Skevlo uint16_t reg; 2239264912Skevlo 2240264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2241264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2242264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2243264912Skevlo} 2244264912Skevlo 2245251538Srpaulostatic int 2246251538Srpaulourtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2247251538Srpaulo{ 2248251538Srpaulo uint32_t reg; 2249251538Srpaulo int off, mlen, error = 0; 2250251538Srpaulo 2251251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2252251538Srpaulo reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2253251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2254251538Srpaulo 2255251538Srpaulo off = R92C_FW_START_ADDR; 2256251538Srpaulo while (len > 0) { 2257251538Srpaulo if (len > 196) 2258251538Srpaulo mlen = 196; 2259251538Srpaulo else if (len > 4) 2260251538Srpaulo mlen = 4; 2261251538Srpaulo else 2262251538Srpaulo mlen = 1; 2263251538Srpaulo /* XXX fix this deconst */ 2264281069Srpaulo error = urtwn_write_region_1(sc, off, 2265251538Srpaulo __DECONST(uint8_t *, buf), mlen); 2266251538Srpaulo if (error != 0) 2267251538Srpaulo break; 2268251538Srpaulo off += mlen; 2269251538Srpaulo buf += mlen; 2270251538Srpaulo len -= mlen; 2271251538Srpaulo } 2272251538Srpaulo return (error); 2273251538Srpaulo} 2274251538Srpaulo 2275251538Srpaulostatic int 2276251538Srpaulourtwn_load_firmware(struct urtwn_softc *sc) 2277251538Srpaulo{ 2278251538Srpaulo const struct firmware *fw; 2279251538Srpaulo const struct r92c_fw_hdr *hdr; 2280251538Srpaulo const char *imagename; 2281251538Srpaulo const u_char *ptr; 2282251538Srpaulo size_t len; 2283251538Srpaulo uint32_t reg; 2284251538Srpaulo int mlen, ntries, page, error; 2285251538Srpaulo 2286264864Skevlo URTWN_UNLOCK(sc); 2287251538Srpaulo /* Read firmware image from the filesystem. */ 2288264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2289264912Skevlo imagename = "urtwn-rtl8188eufw"; 2290264912Skevlo else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2291264912Skevlo URTWN_CHIP_UMC_A_CUT) 2292251538Srpaulo imagename = "urtwn-rtl8192cfwU"; 2293251538Srpaulo else 2294251538Srpaulo imagename = "urtwn-rtl8192cfwT"; 2295251538Srpaulo 2296251538Srpaulo fw = firmware_get(imagename); 2297264864Skevlo URTWN_LOCK(sc); 2298251538Srpaulo if (fw == NULL) { 2299251538Srpaulo device_printf(sc->sc_dev, 2300251538Srpaulo "failed loadfirmware of file %s\n", imagename); 2301251538Srpaulo return (ENOENT); 2302251538Srpaulo } 2303251538Srpaulo 2304251538Srpaulo len = fw->datasize; 2305251538Srpaulo 2306251538Srpaulo if (len < sizeof(*hdr)) { 2307251538Srpaulo device_printf(sc->sc_dev, "firmware too short\n"); 2308251538Srpaulo error = EINVAL; 2309251538Srpaulo goto fail; 2310251538Srpaulo } 2311251538Srpaulo ptr = fw->data; 2312251538Srpaulo hdr = (const struct r92c_fw_hdr *)ptr; 2313251538Srpaulo /* Check if there is a valid FW header and skip it. */ 2314251538Srpaulo if ((le16toh(hdr->signature) >> 4) == 0x88c || 2315264912Skevlo (le16toh(hdr->signature) >> 4) == 0x88e || 2316251538Srpaulo (le16toh(hdr->signature) >> 4) == 0x92c) { 2317251538Srpaulo DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2318251538Srpaulo le16toh(hdr->version), le16toh(hdr->subversion), 2319251538Srpaulo hdr->month, hdr->date, hdr->hour, hdr->minute); 2320251538Srpaulo ptr += sizeof(*hdr); 2321251538Srpaulo len -= sizeof(*hdr); 2322251538Srpaulo } 2323251538Srpaulo 2324264912Skevlo if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2325264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2326264912Skevlo urtwn_r88e_fw_reset(sc); 2327264912Skevlo else 2328264912Skevlo urtwn_fw_reset(sc); 2329251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 0); 2330251538Srpaulo } 2331264912Skevlo 2332268487Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2333268487Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2334268487Skevlo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2335268487Skevlo R92C_SYS_FUNC_EN_CPUEN); 2336268487Skevlo } 2337251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2338251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2339251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 2, 2340251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2341251538Srpaulo 2342263154Skevlo /* Reset the FWDL checksum. */ 2343263154Skevlo urtwn_write_1(sc, R92C_MCUFWDL, 2344263154Skevlo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2345263154Skevlo 2346251538Srpaulo for (page = 0; len > 0; page++) { 2347251538Srpaulo mlen = min(len, R92C_FW_PAGE_SIZE); 2348251538Srpaulo error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2349251538Srpaulo if (error != 0) { 2350251538Srpaulo device_printf(sc->sc_dev, 2351251538Srpaulo "could not load firmware page\n"); 2352251538Srpaulo goto fail; 2353251538Srpaulo } 2354251538Srpaulo ptr += mlen; 2355251538Srpaulo len -= mlen; 2356251538Srpaulo } 2357251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2358251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2359251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2360251538Srpaulo 2361251538Srpaulo /* Wait for checksum report. */ 2362251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2363251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2364251538Srpaulo break; 2365266472Shselasky urtwn_ms_delay(sc); 2366251538Srpaulo } 2367251538Srpaulo if (ntries == 1000) { 2368251538Srpaulo device_printf(sc->sc_dev, 2369251538Srpaulo "timeout waiting for checksum report\n"); 2370251538Srpaulo error = ETIMEDOUT; 2371251538Srpaulo goto fail; 2372251538Srpaulo } 2373251538Srpaulo 2374251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2375251538Srpaulo reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2376251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2377264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2378264912Skevlo urtwn_r88e_fw_reset(sc); 2379251538Srpaulo /* Wait for firmware readiness. */ 2380251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2381251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2382251538Srpaulo break; 2383266472Shselasky urtwn_ms_delay(sc); 2384251538Srpaulo } 2385251538Srpaulo if (ntries == 1000) { 2386251538Srpaulo device_printf(sc->sc_dev, 2387251538Srpaulo "timeout waiting for firmware readiness\n"); 2388251538Srpaulo error = ETIMEDOUT; 2389251538Srpaulo goto fail; 2390251538Srpaulo } 2391251538Srpaulofail: 2392251538Srpaulo firmware_put(fw, FIRMWARE_UNLOAD); 2393251538Srpaulo return (error); 2394251538Srpaulo} 2395251538Srpaulo 2396264912Skevlostatic __inline int 2397251538Srpaulourtwn_dma_init(struct urtwn_softc *sc) 2398251538Srpaulo{ 2399281069Srpaulo 2400264912Skevlo return sc->sc_dma_init(sc); 2401264912Skevlo} 2402264912Skevlo 2403264912Skevlostatic int 2404264912Skevlourtwn_r92c_dma_init(struct urtwn_softc *sc) 2405264912Skevlo{ 2406251538Srpaulo int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2407251538Srpaulo uint32_t reg; 2408251538Srpaulo int error; 2409251538Srpaulo 2410251538Srpaulo /* Initialize LLT table. */ 2411251538Srpaulo error = urtwn_llt_init(sc); 2412251538Srpaulo if (error != 0) 2413251538Srpaulo return (error); 2414251538Srpaulo 2415251538Srpaulo /* Get Tx queues to USB endpoints mapping. */ 2416251538Srpaulo hashq = hasnq = haslq = 0; 2417251538Srpaulo reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2418251538Srpaulo DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2419251538Srpaulo if (MS(reg, R92C_USB_EP_HQ) != 0) 2420251538Srpaulo hashq = 1; 2421251538Srpaulo if (MS(reg, R92C_USB_EP_NQ) != 0) 2422251538Srpaulo hasnq = 1; 2423251538Srpaulo if (MS(reg, R92C_USB_EP_LQ) != 0) 2424251538Srpaulo haslq = 1; 2425251538Srpaulo nqueues = hashq + hasnq + haslq; 2426251538Srpaulo if (nqueues == 0) 2427251538Srpaulo return (EIO); 2428251538Srpaulo /* Get the number of pages for each queue. */ 2429251538Srpaulo nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2430251538Srpaulo /* The remaining pages are assigned to the high priority queue. */ 2431251538Srpaulo nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2432251538Srpaulo 2433251538Srpaulo /* Set number of pages for normal priority queue. */ 2434251538Srpaulo urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2435251538Srpaulo urtwn_write_4(sc, R92C_RQPN, 2436251538Srpaulo /* Set number of pages for public queue. */ 2437251538Srpaulo SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2438251538Srpaulo /* Set number of pages for high priority queue. */ 2439251538Srpaulo SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2440251538Srpaulo /* Set number of pages for low priority queue. */ 2441251538Srpaulo SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2442251538Srpaulo /* Load values. */ 2443251538Srpaulo R92C_RQPN_LD); 2444251538Srpaulo 2445251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2446251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2447251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2448251538Srpaulo urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2449251538Srpaulo urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2450251538Srpaulo 2451251538Srpaulo /* Set queue to USB pipe mapping. */ 2452251538Srpaulo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2453251538Srpaulo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2454251538Srpaulo if (nqueues == 1) { 2455251538Srpaulo if (hashq) 2456251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2457251538Srpaulo else if (hasnq) 2458251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2459251538Srpaulo else 2460251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2461251538Srpaulo } else if (nqueues == 2) { 2462251538Srpaulo /* All 2-endpoints configs have a high priority queue. */ 2463251538Srpaulo if (!hashq) 2464251538Srpaulo return (EIO); 2465251538Srpaulo if (hasnq) 2466251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2467251538Srpaulo else 2468251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2469251538Srpaulo } else 2470251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2471251538Srpaulo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2472251538Srpaulo 2473251538Srpaulo /* Set Tx/Rx transfer page boundary. */ 2474251538Srpaulo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2475251538Srpaulo 2476251538Srpaulo /* Set Tx/Rx transfer page size. */ 2477251538Srpaulo urtwn_write_1(sc, R92C_PBP, 2478251538Srpaulo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2479251538Srpaulo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2480251538Srpaulo return (0); 2481251538Srpaulo} 2482251538Srpaulo 2483264912Skevlostatic int 2484264912Skevlourtwn_r88e_dma_init(struct urtwn_softc *sc) 2485264912Skevlo{ 2486264912Skevlo struct usb_interface *iface; 2487264912Skevlo uint32_t reg; 2488264912Skevlo int nqueues; 2489264912Skevlo int error; 2490264912Skevlo 2491264912Skevlo /* Initialize LLT table. */ 2492264912Skevlo error = urtwn_llt_init(sc); 2493264912Skevlo if (error != 0) 2494264912Skevlo return (error); 2495264912Skevlo 2496264912Skevlo /* Get Tx queues to USB endpoints mapping. */ 2497264912Skevlo iface = usbd_get_iface(sc->sc_udev, 0); 2498264912Skevlo nqueues = iface->idesc->bNumEndpoints - 1; 2499264912Skevlo if (nqueues == 0) 2500264912Skevlo return (EIO); 2501264912Skevlo 2502264912Skevlo /* Set number of pages for normal priority queue. */ 2503264912Skevlo urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2504264912Skevlo urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2505264912Skevlo 2506264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2507264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2508264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2509264912Skevlo urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2510264912Skevlo urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2511264912Skevlo 2512264912Skevlo /* Set queue to USB pipe mapping. */ 2513264912Skevlo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2514264912Skevlo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2515264912Skevlo if (nqueues == 1) 2516264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2517264912Skevlo else if (nqueues == 2) 2518264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2519264912Skevlo else 2520264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2521264912Skevlo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2522264912Skevlo 2523264912Skevlo /* Set Tx/Rx transfer page boundary. */ 2524264912Skevlo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2525264912Skevlo 2526264912Skevlo /* Set Tx/Rx transfer page size. */ 2527264912Skevlo urtwn_write_1(sc, R92C_PBP, 2528264912Skevlo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2529264912Skevlo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2530264912Skevlo 2531264912Skevlo return (0); 2532264912Skevlo} 2533264912Skevlo 2534251538Srpaulostatic void 2535251538Srpaulourtwn_mac_init(struct urtwn_softc *sc) 2536251538Srpaulo{ 2537251538Srpaulo int i; 2538251538Srpaulo 2539251538Srpaulo /* Write MAC initialization values. */ 2540264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2541264912Skevlo for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2542264912Skevlo urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2543264912Skevlo rtl8188eu_mac[i].val); 2544264912Skevlo } 2545264912Skevlo urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2546264912Skevlo } else { 2547264912Skevlo for (i = 0; i < nitems(rtl8192cu_mac); i++) 2548264912Skevlo urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2549264912Skevlo rtl8192cu_mac[i].val); 2550264912Skevlo } 2551251538Srpaulo} 2552251538Srpaulo 2553251538Srpaulostatic void 2554251538Srpaulourtwn_bb_init(struct urtwn_softc *sc) 2555251538Srpaulo{ 2556251538Srpaulo const struct urtwn_bb_prog *prog; 2557251538Srpaulo uint32_t reg; 2558264912Skevlo uint8_t crystalcap; 2559251538Srpaulo int i; 2560251538Srpaulo 2561251538Srpaulo /* Enable BB and RF. */ 2562251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2563251538Srpaulo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2564251538Srpaulo R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2565251538Srpaulo R92C_SYS_FUNC_EN_DIO_RF); 2566251538Srpaulo 2567264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 2568264912Skevlo urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2569251538Srpaulo 2570251538Srpaulo urtwn_write_1(sc, R92C_RF_CTRL, 2571251538Srpaulo R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2572251538Srpaulo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2573251538Srpaulo R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2574251538Srpaulo R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2575251538Srpaulo 2576264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2577264912Skevlo urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2578264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 2579264912Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2580264912Skevlo } 2581251538Srpaulo 2582251538Srpaulo /* Select BB programming based on board type. */ 2583264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2584264912Skevlo prog = &rtl8188eu_bb_prog; 2585264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2586251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2587251538Srpaulo prog = &rtl8188ce_bb_prog; 2588251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2589251538Srpaulo prog = &rtl8188ru_bb_prog; 2590251538Srpaulo else 2591251538Srpaulo prog = &rtl8188cu_bb_prog; 2592251538Srpaulo } else { 2593251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2594251538Srpaulo prog = &rtl8192ce_bb_prog; 2595251538Srpaulo else 2596251538Srpaulo prog = &rtl8192cu_bb_prog; 2597251538Srpaulo } 2598251538Srpaulo /* Write BB initialization values. */ 2599251538Srpaulo for (i = 0; i < prog->count; i++) { 2600251538Srpaulo urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2601266472Shselasky urtwn_ms_delay(sc); 2602251538Srpaulo } 2603251538Srpaulo 2604251538Srpaulo if (sc->chip & URTWN_CHIP_92C_1T2R) { 2605251538Srpaulo /* 8192C 1T only configuration. */ 2606251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2607251538Srpaulo reg = (reg & ~0x00000003) | 0x2; 2608251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2609251538Srpaulo 2610251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2611251538Srpaulo reg = (reg & ~0x00300033) | 0x00200022; 2612251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2613251538Srpaulo 2614251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2615251538Srpaulo reg = (reg & ~0xff000000) | 0x45 << 24; 2616251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2617251538Srpaulo 2618251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2619251538Srpaulo reg = (reg & ~0x000000ff) | 0x23; 2620251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2621251538Srpaulo 2622251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2623251538Srpaulo reg = (reg & ~0x00000030) | 1 << 4; 2624251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2625251538Srpaulo 2626251538Srpaulo reg = urtwn_bb_read(sc, 0xe74); 2627251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2628251538Srpaulo urtwn_bb_write(sc, 0xe74, reg); 2629251538Srpaulo reg = urtwn_bb_read(sc, 0xe78); 2630251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2631251538Srpaulo urtwn_bb_write(sc, 0xe78, reg); 2632251538Srpaulo reg = urtwn_bb_read(sc, 0xe7c); 2633251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2634251538Srpaulo urtwn_bb_write(sc, 0xe7c, reg); 2635251538Srpaulo reg = urtwn_bb_read(sc, 0xe80); 2636251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2637251538Srpaulo urtwn_bb_write(sc, 0xe80, reg); 2638251538Srpaulo reg = urtwn_bb_read(sc, 0xe88); 2639251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2640251538Srpaulo urtwn_bb_write(sc, 0xe88, reg); 2641251538Srpaulo } 2642251538Srpaulo 2643251538Srpaulo /* Write AGC values. */ 2644251538Srpaulo for (i = 0; i < prog->agccount; i++) { 2645251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2646251538Srpaulo prog->agcvals[i]); 2647266472Shselasky urtwn_ms_delay(sc); 2648251538Srpaulo } 2649251538Srpaulo 2650264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2651264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2652266472Shselasky urtwn_ms_delay(sc); 2653264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2654266472Shselasky urtwn_ms_delay(sc); 2655264912Skevlo 2656264912Skevlo crystalcap = sc->r88e_rom[0xb9]; 2657264912Skevlo if (crystalcap == 0xff) 2658264912Skevlo crystalcap = 0x20; 2659264912Skevlo crystalcap &= 0x3f; 2660264912Skevlo reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2661264912Skevlo urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2662264912Skevlo RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2663264912Skevlo crystalcap | crystalcap << 6)); 2664264912Skevlo } else { 2665264912Skevlo if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2666264912Skevlo R92C_HSSI_PARAM2_CCK_HIPWR) 2667264912Skevlo sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2668264912Skevlo } 2669251538Srpaulo} 2670251538Srpaulo 2671251538Srpaulovoid 2672251538Srpaulourtwn_rf_init(struct urtwn_softc *sc) 2673251538Srpaulo{ 2674251538Srpaulo const struct urtwn_rf_prog *prog; 2675251538Srpaulo uint32_t reg, type; 2676251538Srpaulo int i, j, idx, off; 2677251538Srpaulo 2678251538Srpaulo /* Select RF programming based on board type. */ 2679264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2680264912Skevlo prog = rtl8188eu_rf_prog; 2681264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2682251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2683251538Srpaulo prog = rtl8188ce_rf_prog; 2684251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2685251538Srpaulo prog = rtl8188ru_rf_prog; 2686251538Srpaulo else 2687251538Srpaulo prog = rtl8188cu_rf_prog; 2688251538Srpaulo } else 2689251538Srpaulo prog = rtl8192ce_rf_prog; 2690251538Srpaulo 2691251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2692251538Srpaulo /* Save RF_ENV control type. */ 2693251538Srpaulo idx = i / 2; 2694251538Srpaulo off = (i % 2) * 16; 2695251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2696251538Srpaulo type = (reg >> off) & 0x10; 2697251538Srpaulo 2698251538Srpaulo /* Set RF_ENV enable. */ 2699251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2700251538Srpaulo reg |= 0x100000; 2701251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2702266472Shselasky urtwn_ms_delay(sc); 2703251538Srpaulo /* Set RF_ENV output high. */ 2704251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2705251538Srpaulo reg |= 0x10; 2706251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2707266472Shselasky urtwn_ms_delay(sc); 2708251538Srpaulo /* Set address and data lengths of RF registers. */ 2709251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2710251538Srpaulo reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2711251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2712266472Shselasky urtwn_ms_delay(sc); 2713251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2714251538Srpaulo reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2715251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2716266472Shselasky urtwn_ms_delay(sc); 2717251538Srpaulo 2718251538Srpaulo /* Write RF initialization values for this chain. */ 2719251538Srpaulo for (j = 0; j < prog[i].count; j++) { 2720251538Srpaulo if (prog[i].regs[j] >= 0xf9 && 2721251538Srpaulo prog[i].regs[j] <= 0xfe) { 2722251538Srpaulo /* 2723251538Srpaulo * These are fake RF registers offsets that 2724251538Srpaulo * indicate a delay is required. 2725251538Srpaulo */ 2726266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2727251538Srpaulo continue; 2728251538Srpaulo } 2729251538Srpaulo urtwn_rf_write(sc, i, prog[i].regs[j], 2730251538Srpaulo prog[i].vals[j]); 2731266472Shselasky urtwn_ms_delay(sc); 2732251538Srpaulo } 2733251538Srpaulo 2734251538Srpaulo /* Restore RF_ENV control type. */ 2735251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2736251538Srpaulo reg &= ~(0x10 << off) | (type << off); 2737251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2738251538Srpaulo 2739251538Srpaulo /* Cache RF register CHNLBW. */ 2740251538Srpaulo sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2741251538Srpaulo } 2742251538Srpaulo 2743251538Srpaulo if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2744251538Srpaulo URTWN_CHIP_UMC_A_CUT) { 2745251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2746251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2747251538Srpaulo } 2748251538Srpaulo} 2749251538Srpaulo 2750251538Srpaulostatic void 2751251538Srpaulourtwn_cam_init(struct urtwn_softc *sc) 2752251538Srpaulo{ 2753251538Srpaulo /* Invalidate all CAM entries. */ 2754251538Srpaulo urtwn_write_4(sc, R92C_CAMCMD, 2755251538Srpaulo R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2756251538Srpaulo} 2757251538Srpaulo 2758251538Srpaulostatic void 2759251538Srpaulourtwn_pa_bias_init(struct urtwn_softc *sc) 2760251538Srpaulo{ 2761251538Srpaulo uint8_t reg; 2762251538Srpaulo int i; 2763251538Srpaulo 2764251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2765251538Srpaulo if (sc->pa_setting & (1 << i)) 2766251538Srpaulo continue; 2767251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2768251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2769251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2770251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2771251538Srpaulo } 2772251538Srpaulo if (!(sc->pa_setting & 0x10)) { 2773251538Srpaulo reg = urtwn_read_1(sc, 0x16); 2774251538Srpaulo reg = (reg & ~0xf0) | 0x90; 2775251538Srpaulo urtwn_write_1(sc, 0x16, reg); 2776251538Srpaulo } 2777251538Srpaulo} 2778251538Srpaulo 2779251538Srpaulostatic void 2780251538Srpaulourtwn_rxfilter_init(struct urtwn_softc *sc) 2781251538Srpaulo{ 2782251538Srpaulo /* Initialize Rx filter. */ 2783251538Srpaulo /* TODO: use better filter for monitor mode. */ 2784251538Srpaulo urtwn_write_4(sc, R92C_RCR, 2785251538Srpaulo R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2786251538Srpaulo R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2787251538Srpaulo R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2788251538Srpaulo /* Accept all multicast frames. */ 2789251538Srpaulo urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2790251538Srpaulo urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2791251538Srpaulo /* Accept all management frames. */ 2792251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2793251538Srpaulo /* Reject all control frames. */ 2794251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2795251538Srpaulo /* Accept all data frames. */ 2796251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2797251538Srpaulo} 2798251538Srpaulo 2799251538Srpaulostatic void 2800251538Srpaulourtwn_edca_init(struct urtwn_softc *sc) 2801251538Srpaulo{ 2802251538Srpaulo urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2803251538Srpaulo urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2804251538Srpaulo urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2805251538Srpaulo urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2806251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2807251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2808251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2809251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2810251538Srpaulo} 2811251538Srpaulo 2812251538Srpaulovoid 2813251538Srpaulourtwn_write_txpower(struct urtwn_softc *sc, int chain, 2814251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2815251538Srpaulo{ 2816251538Srpaulo uint32_t reg; 2817251538Srpaulo 2818251538Srpaulo /* Write per-CCK rate Tx power. */ 2819251538Srpaulo if (chain == 0) { 2820251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2821251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2822251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2823251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2824251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2825251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2826251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2827251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2828251538Srpaulo } else { 2829251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2830251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2831251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2832251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2833251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2834251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2835251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2836251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2837251538Srpaulo } 2838251538Srpaulo /* Write per-OFDM rate Tx power. */ 2839251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2840251538Srpaulo SM(R92C_TXAGC_RATE06, power[ 4]) | 2841251538Srpaulo SM(R92C_TXAGC_RATE09, power[ 5]) | 2842251538Srpaulo SM(R92C_TXAGC_RATE12, power[ 6]) | 2843251538Srpaulo SM(R92C_TXAGC_RATE18, power[ 7])); 2844251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2845251538Srpaulo SM(R92C_TXAGC_RATE24, power[ 8]) | 2846251538Srpaulo SM(R92C_TXAGC_RATE36, power[ 9]) | 2847251538Srpaulo SM(R92C_TXAGC_RATE48, power[10]) | 2848251538Srpaulo SM(R92C_TXAGC_RATE54, power[11])); 2849251538Srpaulo /* Write per-MCS Tx power. */ 2850251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2851251538Srpaulo SM(R92C_TXAGC_MCS00, power[12]) | 2852251538Srpaulo SM(R92C_TXAGC_MCS01, power[13]) | 2853251538Srpaulo SM(R92C_TXAGC_MCS02, power[14]) | 2854251538Srpaulo SM(R92C_TXAGC_MCS03, power[15])); 2855251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2856251538Srpaulo SM(R92C_TXAGC_MCS04, power[16]) | 2857251538Srpaulo SM(R92C_TXAGC_MCS05, power[17]) | 2858251538Srpaulo SM(R92C_TXAGC_MCS06, power[18]) | 2859251538Srpaulo SM(R92C_TXAGC_MCS07, power[19])); 2860251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2861251538Srpaulo SM(R92C_TXAGC_MCS08, power[20]) | 2862261506Skevlo SM(R92C_TXAGC_MCS09, power[21]) | 2863251538Srpaulo SM(R92C_TXAGC_MCS10, power[22]) | 2864251538Srpaulo SM(R92C_TXAGC_MCS11, power[23])); 2865251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2866251538Srpaulo SM(R92C_TXAGC_MCS12, power[24]) | 2867251538Srpaulo SM(R92C_TXAGC_MCS13, power[25]) | 2868251538Srpaulo SM(R92C_TXAGC_MCS14, power[26]) | 2869251538Srpaulo SM(R92C_TXAGC_MCS15, power[27])); 2870251538Srpaulo} 2871251538Srpaulo 2872251538Srpaulovoid 2873251538Srpaulourtwn_get_txpower(struct urtwn_softc *sc, int chain, 2874251538Srpaulo struct ieee80211_channel *c, struct ieee80211_channel *extc, 2875251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2876251538Srpaulo{ 2877287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 2878251538Srpaulo struct r92c_rom *rom = &sc->rom; 2879251538Srpaulo uint16_t cckpow, ofdmpow, htpow, diff, max; 2880251538Srpaulo const struct urtwn_txpwr *base; 2881251538Srpaulo int ridx, chan, group; 2882251538Srpaulo 2883251538Srpaulo /* Determine channel group. */ 2884251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2885251538Srpaulo if (chan <= 3) 2886251538Srpaulo group = 0; 2887251538Srpaulo else if (chan <= 9) 2888251538Srpaulo group = 1; 2889251538Srpaulo else 2890251538Srpaulo group = 2; 2891251538Srpaulo 2892251538Srpaulo /* Get original Tx power based on board type and RF chain. */ 2893251538Srpaulo if (!(sc->chip & URTWN_CHIP_92C)) { 2894251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2895251538Srpaulo base = &rtl8188ru_txagc[chain]; 2896251538Srpaulo else 2897251538Srpaulo base = &rtl8192cu_txagc[chain]; 2898251538Srpaulo } else 2899251538Srpaulo base = &rtl8192cu_txagc[chain]; 2900251538Srpaulo 2901251538Srpaulo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2902251538Srpaulo if (sc->regulatory == 0) { 2903251538Srpaulo for (ridx = 0; ridx <= 3; ridx++) 2904251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2905251538Srpaulo } 2906251538Srpaulo for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 2907251538Srpaulo if (sc->regulatory == 3) { 2908251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2909251538Srpaulo /* Apply vendor limits. */ 2910251538Srpaulo if (extc != NULL) 2911251538Srpaulo max = rom->ht40_max_pwr[group]; 2912251538Srpaulo else 2913251538Srpaulo max = rom->ht20_max_pwr[group]; 2914251538Srpaulo max = (max >> (chain * 4)) & 0xf; 2915251538Srpaulo if (power[ridx] > max) 2916251538Srpaulo power[ridx] = max; 2917251538Srpaulo } else if (sc->regulatory == 1) { 2918251538Srpaulo if (extc == NULL) 2919251538Srpaulo power[ridx] = base->pwr[group][ridx]; 2920251538Srpaulo } else if (sc->regulatory != 2) 2921251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2922251538Srpaulo } 2923251538Srpaulo 2924251538Srpaulo /* Compute per-CCK rate Tx power. */ 2925251538Srpaulo cckpow = rom->cck_tx_pwr[chain][group]; 2926251538Srpaulo for (ridx = 0; ridx <= 3; ridx++) { 2927251538Srpaulo power[ridx] += cckpow; 2928251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2929251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2930251538Srpaulo } 2931251538Srpaulo 2932251538Srpaulo htpow = rom->ht40_1s_tx_pwr[chain][group]; 2933251538Srpaulo if (sc->ntxchains > 1) { 2934251538Srpaulo /* Apply reduction for 2 spatial streams. */ 2935251538Srpaulo diff = rom->ht40_2s_tx_pwr_diff[group]; 2936251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2937251538Srpaulo htpow = (htpow > diff) ? htpow - diff : 0; 2938251538Srpaulo } 2939251538Srpaulo 2940251538Srpaulo /* Compute per-OFDM rate Tx power. */ 2941251538Srpaulo diff = rom->ofdm_tx_pwr_diff[group]; 2942251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2943251538Srpaulo ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2944251538Srpaulo for (ridx = 4; ridx <= 11; ridx++) { 2945251538Srpaulo power[ridx] += ofdmpow; 2946251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2947251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2948251538Srpaulo } 2949251538Srpaulo 2950251538Srpaulo /* Compute per-MCS Tx power. */ 2951251538Srpaulo if (extc == NULL) { 2952251538Srpaulo diff = rom->ht20_tx_pwr_diff[group]; 2953251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2954251538Srpaulo htpow += diff; /* HT40->HT20 correction. */ 2955251538Srpaulo } 2956251538Srpaulo for (ridx = 12; ridx <= 27; ridx++) { 2957251538Srpaulo power[ridx] += htpow; 2958251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2959251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2960251538Srpaulo } 2961251538Srpaulo#ifdef URTWN_DEBUG 2962251538Srpaulo if (urtwn_debug >= 4) { 2963251538Srpaulo /* Dump per-rate Tx power values. */ 2964251538Srpaulo printf("Tx power for chain %d:\n", chain); 2965251538Srpaulo for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 2966251538Srpaulo printf("Rate %d = %u\n", ridx, power[ridx]); 2967251538Srpaulo } 2968251538Srpaulo#endif 2969251538Srpaulo} 2970251538Srpaulo 2971251538Srpaulovoid 2972264912Skevlourtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 2973264912Skevlo struct ieee80211_channel *c, struct ieee80211_channel *extc, 2974264912Skevlo uint16_t power[URTWN_RIDX_COUNT]) 2975264912Skevlo{ 2976287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 2977264912Skevlo uint16_t cckpow, ofdmpow, bw20pow, htpow; 2978264912Skevlo const struct urtwn_r88e_txpwr *base; 2979264912Skevlo int ridx, chan, group; 2980264912Skevlo 2981264912Skevlo /* Determine channel group. */ 2982264912Skevlo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2983264912Skevlo if (chan <= 2) 2984264912Skevlo group = 0; 2985264912Skevlo else if (chan <= 5) 2986264912Skevlo group = 1; 2987264912Skevlo else if (chan <= 8) 2988264912Skevlo group = 2; 2989264912Skevlo else if (chan <= 11) 2990264912Skevlo group = 3; 2991264912Skevlo else if (chan <= 13) 2992264912Skevlo group = 4; 2993264912Skevlo else 2994264912Skevlo group = 5; 2995264912Skevlo 2996264912Skevlo /* Get original Tx power based on board type and RF chain. */ 2997264912Skevlo base = &rtl8188eu_txagc[chain]; 2998264912Skevlo 2999264912Skevlo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3000264912Skevlo if (sc->regulatory == 0) { 3001264912Skevlo for (ridx = 0; ridx <= 3; ridx++) 3002264912Skevlo power[ridx] = base->pwr[0][ridx]; 3003264912Skevlo } 3004264912Skevlo for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3005264912Skevlo if (sc->regulatory == 3) 3006264912Skevlo power[ridx] = base->pwr[0][ridx]; 3007264912Skevlo else if (sc->regulatory == 1) { 3008264912Skevlo if (extc == NULL) 3009264912Skevlo power[ridx] = base->pwr[group][ridx]; 3010264912Skevlo } else if (sc->regulatory != 2) 3011264912Skevlo power[ridx] = base->pwr[0][ridx]; 3012264912Skevlo } 3013264912Skevlo 3014264912Skevlo /* Compute per-CCK rate Tx power. */ 3015264912Skevlo cckpow = sc->cck_tx_pwr[group]; 3016264912Skevlo for (ridx = 0; ridx <= 3; ridx++) { 3017264912Skevlo power[ridx] += cckpow; 3018264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3019264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3020264912Skevlo } 3021264912Skevlo 3022264912Skevlo htpow = sc->ht40_tx_pwr[group]; 3023264912Skevlo 3024264912Skevlo /* Compute per-OFDM rate Tx power. */ 3025264912Skevlo ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3026264912Skevlo for (ridx = 4; ridx <= 11; ridx++) { 3027264912Skevlo power[ridx] += ofdmpow; 3028264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3029264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3030264912Skevlo } 3031264912Skevlo 3032264912Skevlo bw20pow = htpow + sc->bw20_tx_pwr_diff; 3033264912Skevlo for (ridx = 12; ridx <= 27; ridx++) { 3034264912Skevlo power[ridx] += bw20pow; 3035264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3036264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3037264912Skevlo } 3038264912Skevlo} 3039264912Skevlo 3040264912Skevlovoid 3041251538Srpaulourtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3042251538Srpaulo struct ieee80211_channel *extc) 3043251538Srpaulo{ 3044251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]; 3045251538Srpaulo int i; 3046251538Srpaulo 3047251538Srpaulo for (i = 0; i < sc->ntxchains; i++) { 3048251538Srpaulo /* Compute per-rate Tx power values. */ 3049264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3050264912Skevlo urtwn_r88e_get_txpower(sc, i, c, extc, power); 3051264912Skevlo else 3052264912Skevlo urtwn_get_txpower(sc, i, c, extc, power); 3053251538Srpaulo /* Write per-rate Tx power values to hardware. */ 3054251538Srpaulo urtwn_write_txpower(sc, i, power); 3055251538Srpaulo } 3056251538Srpaulo} 3057251538Srpaulo 3058251538Srpaulostatic void 3059251538Srpaulourtwn_scan_start(struct ieee80211com *ic) 3060251538Srpaulo{ 3061251538Srpaulo /* XXX do nothing? */ 3062251538Srpaulo} 3063251538Srpaulo 3064251538Srpaulostatic void 3065251538Srpaulourtwn_scan_end(struct ieee80211com *ic) 3066251538Srpaulo{ 3067251538Srpaulo /* XXX do nothing? */ 3068251538Srpaulo} 3069251538Srpaulo 3070251538Srpaulostatic void 3071251538Srpaulourtwn_set_channel(struct ieee80211com *ic) 3072251538Srpaulo{ 3073286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 3074281070Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3075251538Srpaulo 3076251538Srpaulo URTWN_LOCK(sc); 3077281070Srpaulo if (vap->iv_state == IEEE80211_S_SCAN) { 3078281070Srpaulo /* Make link LED blink during scan. */ 3079281070Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3080281070Srpaulo } 3081251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 3082251538Srpaulo URTWN_UNLOCK(sc); 3083251538Srpaulo} 3084251538Srpaulo 3085251538Srpaulostatic void 3086283540Sglebiusurtwn_update_mcast(struct ieee80211com *ic) 3087251538Srpaulo{ 3088251538Srpaulo /* XXX do nothing? */ 3089251538Srpaulo} 3090251538Srpaulo 3091251538Srpaulostatic void 3092251538Srpaulourtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3093251538Srpaulo struct ieee80211_channel *extc) 3094251538Srpaulo{ 3095287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3096251538Srpaulo uint32_t reg; 3097251538Srpaulo u_int chan; 3098251538Srpaulo int i; 3099251538Srpaulo 3100251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3101251538Srpaulo if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3102251538Srpaulo device_printf(sc->sc_dev, 3103251538Srpaulo "%s: invalid channel %x\n", __func__, chan); 3104251538Srpaulo return; 3105251538Srpaulo } 3106251538Srpaulo 3107251538Srpaulo /* Set Tx power for this new channel. */ 3108251538Srpaulo urtwn_set_txpower(sc, c, extc); 3109251538Srpaulo 3110251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3111251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3112251538Srpaulo RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3113251538Srpaulo } 3114251538Srpaulo#ifndef IEEE80211_NO_HT 3115251538Srpaulo if (extc != NULL) { 3116251538Srpaulo /* Is secondary channel below or above primary? */ 3117251538Srpaulo int prichlo = c->ic_freq < extc->ic_freq; 3118251538Srpaulo 3119251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3120251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3121251538Srpaulo 3122251538Srpaulo reg = urtwn_read_1(sc, R92C_RRSR + 2); 3123251538Srpaulo reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3124251538Srpaulo urtwn_write_1(sc, R92C_RRSR + 2, reg); 3125251538Srpaulo 3126251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3127251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3128251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3129251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3130251538Srpaulo 3131251538Srpaulo /* Set CCK side band. */ 3132251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3133251538Srpaulo reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3134251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3135251538Srpaulo 3136251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3137251538Srpaulo reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3138251538Srpaulo urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3139251538Srpaulo 3140251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3141251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3142251538Srpaulo ~R92C_FPGA0_ANAPARAM2_CBW20); 3143251538Srpaulo 3144251538Srpaulo reg = urtwn_bb_read(sc, 0x818); 3145251538Srpaulo reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3146251538Srpaulo urtwn_bb_write(sc, 0x818, reg); 3147251538Srpaulo 3148251538Srpaulo /* Select 40MHz bandwidth. */ 3149251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3150251538Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan); 3151251538Srpaulo } else 3152251538Srpaulo#endif 3153251538Srpaulo { 3154251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3155251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3156251538Srpaulo 3157251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3158251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3159251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3160251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3161251538Srpaulo 3162264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3163264912Skevlo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3164264912Skevlo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3165264912Skevlo R92C_FPGA0_ANAPARAM2_CBW20); 3166264912Skevlo } 3167281069Srpaulo 3168251538Srpaulo /* Select 20MHz bandwidth. */ 3169251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3170281069Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan | 3171264912Skevlo ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3172264912Skevlo R92C_RF_CHNLBW_BW20)); 3173251538Srpaulo } 3174251538Srpaulo} 3175251538Srpaulo 3176251538Srpaulostatic void 3177251538Srpaulourtwn_iq_calib(struct urtwn_softc *sc) 3178251538Srpaulo{ 3179251538Srpaulo /* TODO */ 3180251538Srpaulo} 3181251538Srpaulo 3182251538Srpaulostatic void 3183251538Srpaulourtwn_lc_calib(struct urtwn_softc *sc) 3184251538Srpaulo{ 3185251538Srpaulo uint32_t rf_ac[2]; 3186251538Srpaulo uint8_t txmode; 3187251538Srpaulo int i; 3188251538Srpaulo 3189251538Srpaulo txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3190251538Srpaulo if ((txmode & 0x70) != 0) { 3191251538Srpaulo /* Disable all continuous Tx. */ 3192251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3193251538Srpaulo 3194251538Srpaulo /* Set RF mode to standby mode. */ 3195251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3196251538Srpaulo rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3197251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, 3198251538Srpaulo RW(rf_ac[i], R92C_RF_AC_MODE, 3199251538Srpaulo R92C_RF_AC_MODE_STANDBY)); 3200251538Srpaulo } 3201251538Srpaulo } else { 3202251538Srpaulo /* Block all Tx queues. */ 3203251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3204251538Srpaulo } 3205251538Srpaulo /* Start calibration. */ 3206251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3207251538Srpaulo urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3208251538Srpaulo 3209251538Srpaulo /* Give calibration the time to complete. */ 3210266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3211251538Srpaulo 3212251538Srpaulo /* Restore configuration. */ 3213251538Srpaulo if ((txmode & 0x70) != 0) { 3214251538Srpaulo /* Restore Tx mode. */ 3215251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3216251538Srpaulo /* Restore RF mode. */ 3217251538Srpaulo for (i = 0; i < sc->nrxchains; i++) 3218251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3219251538Srpaulo } else { 3220251538Srpaulo /* Unblock all Tx queues. */ 3221251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3222251538Srpaulo } 3223251538Srpaulo} 3224251538Srpaulo 3225251538Srpaulostatic void 3226287197Sglebiusurtwn_init(struct urtwn_softc *sc) 3227251538Srpaulo{ 3228287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3229287197Sglebius struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3230287197Sglebius uint8_t macaddr[IEEE80211_ADDR_LEN]; 3231251538Srpaulo uint32_t reg; 3232251538Srpaulo int error; 3233251538Srpaulo 3234264864Skevlo URTWN_ASSERT_LOCKED(sc); 3235264864Skevlo 3236287197Sglebius if (sc->sc_flags & URTWN_RUNNING) 3237287197Sglebius urtwn_stop(sc); 3238251538Srpaulo 3239251538Srpaulo /* Init firmware commands ring. */ 3240251538Srpaulo sc->fwcur = 0; 3241251538Srpaulo 3242251538Srpaulo /* Allocate Tx/Rx buffers. */ 3243251538Srpaulo error = urtwn_alloc_rx_list(sc); 3244251538Srpaulo if (error != 0) 3245251538Srpaulo goto fail; 3246281069Srpaulo 3247251538Srpaulo error = urtwn_alloc_tx_list(sc); 3248251538Srpaulo if (error != 0) 3249251538Srpaulo goto fail; 3250251538Srpaulo 3251251538Srpaulo /* Power on adapter. */ 3252251538Srpaulo error = urtwn_power_on(sc); 3253251538Srpaulo if (error != 0) 3254251538Srpaulo goto fail; 3255251538Srpaulo 3256251538Srpaulo /* Initialize DMA. */ 3257251538Srpaulo error = urtwn_dma_init(sc); 3258251538Srpaulo if (error != 0) 3259251538Srpaulo goto fail; 3260251538Srpaulo 3261251538Srpaulo /* Set info size in Rx descriptors (in 64-bit words). */ 3262251538Srpaulo urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3263251538Srpaulo 3264251538Srpaulo /* Init interrupts. */ 3265264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3266264912Skevlo urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3267264912Skevlo urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3268264912Skevlo R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3269264912Skevlo urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3270264912Skevlo R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3271264912Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3272264912Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3273264912Skevlo R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3274264912Skevlo } else { 3275264912Skevlo urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3276264912Skevlo urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3277264912Skevlo } 3278251538Srpaulo 3279251538Srpaulo /* Set MAC address. */ 3280287197Sglebius IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3281287197Sglebius urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3282251538Srpaulo 3283251538Srpaulo /* Set initial network type. */ 3284251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 3285251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3286251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 3287251538Srpaulo 3288251538Srpaulo urtwn_rxfilter_init(sc); 3289251538Srpaulo 3290282623Skevlo /* Set response rate. */ 3291251538Srpaulo reg = urtwn_read_4(sc, R92C_RRSR); 3292251538Srpaulo reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3293251538Srpaulo urtwn_write_4(sc, R92C_RRSR, reg); 3294251538Srpaulo 3295251538Srpaulo /* Set short/long retry limits. */ 3296251538Srpaulo urtwn_write_2(sc, R92C_RL, 3297251538Srpaulo SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3298251538Srpaulo 3299251538Srpaulo /* Initialize EDCA parameters. */ 3300251538Srpaulo urtwn_edca_init(sc); 3301251538Srpaulo 3302251538Srpaulo /* Setup rate fallback. */ 3303264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3304264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3305264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3306264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3307264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3308264912Skevlo } 3309251538Srpaulo 3310251538Srpaulo urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3311251538Srpaulo urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3312251538Srpaulo R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3313251538Srpaulo /* Set ACK timeout. */ 3314251538Srpaulo urtwn_write_1(sc, R92C_ACKTO, 0x40); 3315251538Srpaulo 3316251538Srpaulo /* Setup USB aggregation. */ 3317251538Srpaulo reg = urtwn_read_4(sc, R92C_TDECTRL); 3318251538Srpaulo reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3319251538Srpaulo urtwn_write_4(sc, R92C_TDECTRL, reg); 3320251538Srpaulo urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3321251538Srpaulo urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3322251538Srpaulo R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3323251538Srpaulo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3324264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3325264912Skevlo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3326282266Skevlo else { 3327264912Skevlo urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3328282266Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3329282266Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3330282266Skevlo R92C_USB_SPECIAL_OPTION_AGG_EN); 3331282266Skevlo urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3332282266Skevlo urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3333282266Skevlo } 3334251538Srpaulo 3335251538Srpaulo /* Initialize beacon parameters. */ 3336264912Skevlo urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3337251538Srpaulo urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3338251538Srpaulo urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3339251538Srpaulo urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3340251538Srpaulo urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3341251538Srpaulo 3342264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3343264912Skevlo /* Setup AMPDU aggregation. */ 3344264912Skevlo urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3345264912Skevlo urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3346264912Skevlo urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3347251538Srpaulo 3348264912Skevlo urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3349264912Skevlo } 3350251538Srpaulo 3351251538Srpaulo /* Load 8051 microcode. */ 3352251538Srpaulo error = urtwn_load_firmware(sc); 3353251538Srpaulo if (error != 0) 3354251538Srpaulo goto fail; 3355251538Srpaulo 3356251538Srpaulo /* Initialize MAC/BB/RF blocks. */ 3357251538Srpaulo urtwn_mac_init(sc); 3358251538Srpaulo urtwn_bb_init(sc); 3359251538Srpaulo urtwn_rf_init(sc); 3360251538Srpaulo 3361264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3362264912Skevlo urtwn_write_2(sc, R92C_CR, 3363264912Skevlo urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3364264912Skevlo R92C_CR_MACRXEN); 3365264912Skevlo } 3366264912Skevlo 3367251538Srpaulo /* Turn CCK and OFDM blocks on. */ 3368251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3369251538Srpaulo reg |= R92C_RFMOD_CCK_EN; 3370251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3371251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3372251538Srpaulo reg |= R92C_RFMOD_OFDM_EN; 3373251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3374251538Srpaulo 3375251538Srpaulo /* Clear per-station keys table. */ 3376251538Srpaulo urtwn_cam_init(sc); 3377251538Srpaulo 3378251538Srpaulo /* Enable hardware sequence numbering. */ 3379251538Srpaulo urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3380251538Srpaulo 3381251538Srpaulo /* Perform LO and IQ calibrations. */ 3382251538Srpaulo urtwn_iq_calib(sc); 3383251538Srpaulo /* Perform LC calibration. */ 3384251538Srpaulo urtwn_lc_calib(sc); 3385251538Srpaulo 3386251538Srpaulo /* Fix USB interference issue. */ 3387264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3388264912Skevlo urtwn_write_1(sc, 0xfe40, 0xe0); 3389264912Skevlo urtwn_write_1(sc, 0xfe41, 0x8d); 3390264912Skevlo urtwn_write_1(sc, 0xfe42, 0x80); 3391251538Srpaulo 3392264912Skevlo urtwn_pa_bias_init(sc); 3393264912Skevlo } 3394251538Srpaulo 3395251538Srpaulo /* Initialize GPIO setting. */ 3396251538Srpaulo urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3397251538Srpaulo urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3398251538Srpaulo 3399251538Srpaulo /* Fix for lower temperature. */ 3400264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 3401264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 3402251538Srpaulo 3403251538Srpaulo usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3404251538Srpaulo 3405287197Sglebius sc->sc_flags |= URTWN_RUNNING; 3406251538Srpaulo 3407251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3408251538Srpaulofail: 3409251538Srpaulo return; 3410251538Srpaulo} 3411251538Srpaulo 3412251538Srpaulostatic void 3413287197Sglebiusurtwn_stop(struct urtwn_softc *sc) 3414251538Srpaulo{ 3415251538Srpaulo 3416264864Skevlo URTWN_ASSERT_LOCKED(sc); 3417287197Sglebius sc->sc_flags &= ~URTWN_RUNNING; 3418251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 3419251538Srpaulo urtwn_abort_xfers(sc); 3420251538Srpaulo} 3421251538Srpaulo 3422251538Srpaulostatic void 3423251538Srpaulourtwn_abort_xfers(struct urtwn_softc *sc) 3424251538Srpaulo{ 3425251538Srpaulo int i; 3426251538Srpaulo 3427251538Srpaulo URTWN_ASSERT_LOCKED(sc); 3428251538Srpaulo 3429251538Srpaulo /* abort any pending transfers */ 3430251538Srpaulo for (i = 0; i < URTWN_N_TRANSFER; i++) 3431251538Srpaulo usbd_transfer_stop(sc->sc_xfer[i]); 3432251538Srpaulo} 3433251538Srpaulo 3434251538Srpaulostatic int 3435251538Srpaulourtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3436251538Srpaulo const struct ieee80211_bpf_params *params) 3437251538Srpaulo{ 3438251538Srpaulo struct ieee80211com *ic = ni->ni_ic; 3439286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 3440251538Srpaulo struct urtwn_data *bf; 3441251538Srpaulo 3442251538Srpaulo /* prevent management frames from being sent if we're not ready */ 3443287197Sglebius if (!(sc->sc_flags & URTWN_RUNNING)) { 3444251538Srpaulo m_freem(m); 3445251538Srpaulo ieee80211_free_node(ni); 3446251538Srpaulo return (ENETDOWN); 3447251538Srpaulo } 3448251538Srpaulo URTWN_LOCK(sc); 3449251538Srpaulo bf = urtwn_getbuf(sc); 3450251538Srpaulo if (bf == NULL) { 3451251538Srpaulo ieee80211_free_node(ni); 3452251538Srpaulo m_freem(m); 3453251538Srpaulo URTWN_UNLOCK(sc); 3454251538Srpaulo return (ENOBUFS); 3455251538Srpaulo } 3456251538Srpaulo 3457251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3458251538Srpaulo ieee80211_free_node(ni); 3459251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3460251538Srpaulo URTWN_UNLOCK(sc); 3461251538Srpaulo return (EIO); 3462251538Srpaulo } 3463251538Srpaulo URTWN_UNLOCK(sc); 3464251538Srpaulo 3465251538Srpaulo sc->sc_txtimer = 5; 3466251538Srpaulo return (0); 3467251538Srpaulo} 3468251538Srpaulo 3469266472Shselaskystatic void 3470266472Shselaskyurtwn_ms_delay(struct urtwn_softc *sc) 3471266472Shselasky{ 3472266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3473266472Shselasky} 3474266472Shselasky 3475251538Srpaulostatic device_method_t urtwn_methods[] = { 3476251538Srpaulo /* Device interface */ 3477251538Srpaulo DEVMETHOD(device_probe, urtwn_match), 3478251538Srpaulo DEVMETHOD(device_attach, urtwn_attach), 3479251538Srpaulo DEVMETHOD(device_detach, urtwn_detach), 3480251538Srpaulo 3481264912Skevlo DEVMETHOD_END 3482251538Srpaulo}; 3483251538Srpaulo 3484251538Srpaulostatic driver_t urtwn_driver = { 3485251538Srpaulo "urtwn", 3486251538Srpaulo urtwn_methods, 3487251538Srpaulo sizeof(struct urtwn_softc) 3488251538Srpaulo}; 3489251538Srpaulo 3490251538Srpaulostatic devclass_t urtwn_devclass; 3491251538Srpaulo 3492251538SrpauloDRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3493251538SrpauloMODULE_DEPEND(urtwn, usb, 1, 1, 1); 3494251538SrpauloMODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3495251538SrpauloMODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3496251538SrpauloMODULE_VERSION(urtwn, 1); 3497