if_urtwn.c revision 282119
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 282119 2015-04-28 03:24:27Z kevlo $"); 22 23/* 24 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25 */ 26 27#include <sys/param.h> 28#include <sys/sockio.h> 29#include <sys/sysctl.h> 30#include <sys/lock.h> 31#include <sys/mutex.h> 32#include <sys/mbuf.h> 33#include <sys/kernel.h> 34#include <sys/socket.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/bus.h> 39#include <sys/endian.h> 40#include <sys/linker.h> 41#include <sys/firmware.h> 42#include <sys/kdb.h> 43 44#include <machine/bus.h> 45#include <machine/resource.h> 46#include <sys/rman.h> 47 48#include <net/bpf.h> 49#include <net/if.h> 50#include <net/if_var.h> 51#include <net/if_arp.h> 52#include <net/ethernet.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55#include <net/if_types.h> 56 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/if_ether.h> 61#include <netinet/ip.h> 62 63#include <net80211/ieee80211_var.h> 64#include <net80211/ieee80211_regdomain.h> 65#include <net80211/ieee80211_radiotap.h> 66#include <net80211/ieee80211_ratectl.h> 67 68#include <dev/usb/usb.h> 69#include <dev/usb/usbdi.h> 70#include "usbdevs.h" 71 72#define USB_DEBUG_VAR urtwn_debug 73#include <dev/usb/usb_debug.h> 74 75#include <dev/usb/wlan/if_urtwnreg.h> 76 77#ifdef USB_DEBUG 78static int urtwn_debug = 0; 79 80SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 81SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 82 "Debug level"); 83#endif 84 85#define URTWN_RSSI(r) (r) - 110 86#define IEEE80211_HAS_ADDR4(wh) \ 87 (((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) 88 89/* various supported device vendors/products */ 90static const STRUCT_USB_HOST_ID urtwn_devs[] = { 91#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 92#define URTWN_RTL8188E_DEV(v,p) \ 93 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 94#define URTWN_RTL8188E 1 95 URTWN_DEV(ABOCOM, RTL8188CU_1), 96 URTWN_DEV(ABOCOM, RTL8188CU_2), 97 URTWN_DEV(ABOCOM, RTL8192CU), 98 URTWN_DEV(ASUS, RTL8192CU), 99 URTWN_DEV(ASUS, USBN10NANO), 100 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 101 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 102 URTWN_DEV(AZUREWAVE, RTL8188CU), 103 URTWN_DEV(BELKIN, F7D2102), 104 URTWN_DEV(BELKIN, RTL8188CU), 105 URTWN_DEV(BELKIN, RTL8192CU), 106 URTWN_DEV(CHICONY, RTL8188CUS_1), 107 URTWN_DEV(CHICONY, RTL8188CUS_2), 108 URTWN_DEV(CHICONY, RTL8188CUS_3), 109 URTWN_DEV(CHICONY, RTL8188CUS_4), 110 URTWN_DEV(CHICONY, RTL8188CUS_5), 111 URTWN_DEV(COREGA, RTL8192CU), 112 URTWN_DEV(DLINK, RTL8188CU), 113 URTWN_DEV(DLINK, RTL8192CU_1), 114 URTWN_DEV(DLINK, RTL8192CU_2), 115 URTWN_DEV(DLINK, RTL8192CU_3), 116 URTWN_DEV(DLINK, DWA131B), 117 URTWN_DEV(EDIMAX, EW7811UN), 118 URTWN_DEV(EDIMAX, RTL8192CU), 119 URTWN_DEV(FEIXUN, RTL8188CU), 120 URTWN_DEV(FEIXUN, RTL8192CU), 121 URTWN_DEV(GUILLEMOT, HWNUP150), 122 URTWN_DEV(HAWKING, RTL8192CU), 123 URTWN_DEV(HP3, RTL8188CU), 124 URTWN_DEV(NETGEAR, WNA1000M), 125 URTWN_DEV(NETGEAR, RTL8192CU), 126 URTWN_DEV(NETGEAR4, RTL8188CU), 127 URTWN_DEV(NOVATECH, RTL8188CU), 128 URTWN_DEV(PLANEX2, RTL8188CU_1), 129 URTWN_DEV(PLANEX2, RTL8188CU_2), 130 URTWN_DEV(PLANEX2, RTL8188CU_3), 131 URTWN_DEV(PLANEX2, RTL8188CU_4), 132 URTWN_DEV(PLANEX2, RTL8188CUS), 133 URTWN_DEV(PLANEX2, RTL8192CU), 134 URTWN_DEV(REALTEK, RTL8188CE_0), 135 URTWN_DEV(REALTEK, RTL8188CE_1), 136 URTWN_DEV(REALTEK, RTL8188CTV), 137 URTWN_DEV(REALTEK, RTL8188CU_0), 138 URTWN_DEV(REALTEK, RTL8188CU_1), 139 URTWN_DEV(REALTEK, RTL8188CU_2), 140 URTWN_DEV(REALTEK, RTL8188CU_3), 141 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 142 URTWN_DEV(REALTEK, RTL8188CUS), 143 URTWN_DEV(REALTEK, RTL8188RU_1), 144 URTWN_DEV(REALTEK, RTL8188RU_2), 145 URTWN_DEV(REALTEK, RTL8188RU_3), 146 URTWN_DEV(REALTEK, RTL8191CU), 147 URTWN_DEV(REALTEK, RTL8192CE), 148 URTWN_DEV(REALTEK, RTL8192CU), 149 URTWN_DEV(SITECOMEU, RTL8188CU_1), 150 URTWN_DEV(SITECOMEU, RTL8188CU_2), 151 URTWN_DEV(SITECOMEU, RTL8192CU), 152 URTWN_DEV(TRENDNET, RTL8188CU), 153 URTWN_DEV(TRENDNET, RTL8192CU), 154 URTWN_DEV(ZYXEL, RTL8192CU), 155 /* URTWN_RTL8188E */ 156 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 157 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 158 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 159 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 160 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 161#undef URTWN_RTL8188E_DEV 162#undef URTWN_DEV 163}; 164 165static device_probe_t urtwn_match; 166static device_attach_t urtwn_attach; 167static device_detach_t urtwn_detach; 168 169static usb_callback_t urtwn_bulk_tx_callback; 170static usb_callback_t urtwn_bulk_rx_callback; 171 172static usb_error_t urtwn_do_request(struct urtwn_softc *sc, 173 struct usb_device_request *req, void *data); 174static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 175 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 176 const uint8_t [IEEE80211_ADDR_LEN], 177 const uint8_t [IEEE80211_ADDR_LEN]); 178static void urtwn_vap_delete(struct ieee80211vap *); 179static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 180 int *); 181static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 182 int *, int8_t *); 183static void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 184static int urtwn_alloc_list(struct urtwn_softc *, 185 struct urtwn_data[], int, int); 186static int urtwn_alloc_rx_list(struct urtwn_softc *); 187static int urtwn_alloc_tx_list(struct urtwn_softc *); 188static void urtwn_free_tx_list(struct urtwn_softc *); 189static void urtwn_free_rx_list(struct urtwn_softc *); 190static void urtwn_free_list(struct urtwn_softc *, 191 struct urtwn_data data[], int); 192static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 193static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 194static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 195 uint8_t *, int); 196static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 197static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 198static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 199static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 200 uint8_t *, int); 201static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 202static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 203static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 204static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 205 const void *, int); 206static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 207 uint8_t, uint32_t); 208static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 209 uint8_t, uint32_t); 210static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 211static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 212 uint32_t); 213static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 214static void urtwn_efuse_read(struct urtwn_softc *); 215static void urtwn_efuse_switch_power(struct urtwn_softc *); 216static int urtwn_read_chipid(struct urtwn_softc *); 217static void urtwn_read_rom(struct urtwn_softc *); 218static void urtwn_r88e_read_rom(struct urtwn_softc *); 219static int urtwn_ra_init(struct urtwn_softc *); 220static void urtwn_tsf_sync_enable(struct urtwn_softc *); 221static void urtwn_set_led(struct urtwn_softc *, int, int); 222static int urtwn_newstate(struct ieee80211vap *, 223 enum ieee80211_state, int); 224static void urtwn_watchdog(void *); 225static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 226static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 227static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 228static int urtwn_tx_start(struct urtwn_softc *, 229 struct ieee80211_node *, struct mbuf *, 230 struct urtwn_data *); 231static void urtwn_start(struct ifnet *); 232static void urtwn_start_locked(struct ifnet *, 233 struct urtwn_softc *); 234static int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 235static int urtwn_r92c_power_on(struct urtwn_softc *); 236static int urtwn_r88e_power_on(struct urtwn_softc *); 237static int urtwn_llt_init(struct urtwn_softc *); 238static void urtwn_fw_reset(struct urtwn_softc *); 239static void urtwn_r88e_fw_reset(struct urtwn_softc *); 240static int urtwn_fw_loadpage(struct urtwn_softc *, int, 241 const uint8_t *, int); 242static int urtwn_load_firmware(struct urtwn_softc *); 243static int urtwn_r92c_dma_init(struct urtwn_softc *); 244static int urtwn_r88e_dma_init(struct urtwn_softc *); 245static void urtwn_mac_init(struct urtwn_softc *); 246static void urtwn_bb_init(struct urtwn_softc *); 247static void urtwn_rf_init(struct urtwn_softc *); 248static void urtwn_cam_init(struct urtwn_softc *); 249static void urtwn_pa_bias_init(struct urtwn_softc *); 250static void urtwn_rxfilter_init(struct urtwn_softc *); 251static void urtwn_edca_init(struct urtwn_softc *); 252static void urtwn_write_txpower(struct urtwn_softc *, int, 253 uint16_t[]); 254static void urtwn_get_txpower(struct urtwn_softc *, int, 255 struct ieee80211_channel *, 256 struct ieee80211_channel *, uint16_t[]); 257static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 258 struct ieee80211_channel *, 259 struct ieee80211_channel *, uint16_t[]); 260static void urtwn_set_txpower(struct urtwn_softc *, 261 struct ieee80211_channel *, 262 struct ieee80211_channel *); 263static void urtwn_scan_start(struct ieee80211com *); 264static void urtwn_scan_end(struct ieee80211com *); 265static void urtwn_set_channel(struct ieee80211com *); 266static void urtwn_set_chan(struct urtwn_softc *, 267 struct ieee80211_channel *, 268 struct ieee80211_channel *); 269static void urtwn_update_mcast(struct ifnet *); 270static void urtwn_iq_calib(struct urtwn_softc *); 271static void urtwn_lc_calib(struct urtwn_softc *); 272static void urtwn_init(void *); 273static void urtwn_init_locked(void *); 274static void urtwn_stop(struct ifnet *); 275static void urtwn_stop_locked(struct ifnet *); 276static void urtwn_abort_xfers(struct urtwn_softc *); 277static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 278 const struct ieee80211_bpf_params *); 279static void urtwn_ms_delay(struct urtwn_softc *); 280 281/* Aliases. */ 282#define urtwn_bb_write urtwn_write_4 283#define urtwn_bb_read urtwn_read_4 284 285static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 286 [URTWN_BULK_RX] = { 287 .type = UE_BULK, 288 .endpoint = UE_ADDR_ANY, 289 .direction = UE_DIR_IN, 290 .bufsize = URTWN_RXBUFSZ, 291 .flags = { 292 .pipe_bof = 1, 293 .short_xfer_ok = 1 294 }, 295 .callback = urtwn_bulk_rx_callback, 296 }, 297 [URTWN_BULK_TX_BE] = { 298 .type = UE_BULK, 299 .endpoint = 0x03, 300 .direction = UE_DIR_OUT, 301 .bufsize = URTWN_TXBUFSZ, 302 .flags = { 303 .ext_buffer = 1, 304 .pipe_bof = 1, 305 .force_short_xfer = 1 306 }, 307 .callback = urtwn_bulk_tx_callback, 308 .timeout = URTWN_TX_TIMEOUT, /* ms */ 309 }, 310 [URTWN_BULK_TX_BK] = { 311 .type = UE_BULK, 312 .endpoint = 0x03, 313 .direction = UE_DIR_OUT, 314 .bufsize = URTWN_TXBUFSZ, 315 .flags = { 316 .ext_buffer = 1, 317 .pipe_bof = 1, 318 .force_short_xfer = 1, 319 }, 320 .callback = urtwn_bulk_tx_callback, 321 .timeout = URTWN_TX_TIMEOUT, /* ms */ 322 }, 323 [URTWN_BULK_TX_VI] = { 324 .type = UE_BULK, 325 .endpoint = 0x02, 326 .direction = UE_DIR_OUT, 327 .bufsize = URTWN_TXBUFSZ, 328 .flags = { 329 .ext_buffer = 1, 330 .pipe_bof = 1, 331 .force_short_xfer = 1 332 }, 333 .callback = urtwn_bulk_tx_callback, 334 .timeout = URTWN_TX_TIMEOUT, /* ms */ 335 }, 336 [URTWN_BULK_TX_VO] = { 337 .type = UE_BULK, 338 .endpoint = 0x02, 339 .direction = UE_DIR_OUT, 340 .bufsize = URTWN_TXBUFSZ, 341 .flags = { 342 .ext_buffer = 1, 343 .pipe_bof = 1, 344 .force_short_xfer = 1 345 }, 346 .callback = urtwn_bulk_tx_callback, 347 .timeout = URTWN_TX_TIMEOUT, /* ms */ 348 }, 349}; 350 351static int 352urtwn_match(device_t self) 353{ 354 struct usb_attach_arg *uaa = device_get_ivars(self); 355 356 if (uaa->usb_mode != USB_MODE_HOST) 357 return (ENXIO); 358 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 359 return (ENXIO); 360 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 361 return (ENXIO); 362 363 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 364} 365 366static int 367urtwn_attach(device_t self) 368{ 369 struct usb_attach_arg *uaa = device_get_ivars(self); 370 struct urtwn_softc *sc = device_get_softc(self); 371 struct ifnet *ifp; 372 struct ieee80211com *ic; 373 uint8_t iface_index, bands; 374 int error; 375 376 device_set_usb_desc(self); 377 sc->sc_udev = uaa->device; 378 sc->sc_dev = self; 379 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 380 sc->chip |= URTWN_CHIP_88E; 381 382 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 383 MTX_NETWORK_LOCK, MTX_DEF); 384 callout_init(&sc->sc_watchdog_ch, 0); 385 386 iface_index = URTWN_IFACE_INDEX; 387 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 388 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 389 if (error) { 390 device_printf(self, "could not allocate USB transfers, " 391 "err=%s\n", usbd_errstr(error)); 392 goto detach; 393 } 394 395 URTWN_LOCK(sc); 396 397 error = urtwn_read_chipid(sc); 398 if (error) { 399 device_printf(sc->sc_dev, "unsupported test chip\n"); 400 URTWN_UNLOCK(sc); 401 goto detach; 402 } 403 404 /* Determine number of Tx/Rx chains. */ 405 if (sc->chip & URTWN_CHIP_92C) { 406 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 407 sc->nrxchains = 2; 408 } else { 409 sc->ntxchains = 1; 410 sc->nrxchains = 1; 411 } 412 413 if (sc->chip & URTWN_CHIP_88E) 414 urtwn_r88e_read_rom(sc); 415 else 416 urtwn_read_rom(sc); 417 418 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 419 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 420 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 421 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 422 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 423 "8188CUS", sc->ntxchains, sc->nrxchains); 424 425 URTWN_UNLOCK(sc); 426 427 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 428 if (ifp == NULL) { 429 device_printf(sc->sc_dev, "can not if_alloc()\n"); 430 goto detach; 431 } 432 ic = ifp->if_l2com; 433 434 ifp->if_softc = sc; 435 if_initname(ifp, "urtwn", device_get_unit(sc->sc_dev)); 436 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 437 ifp->if_init = urtwn_init; 438 ifp->if_ioctl = urtwn_ioctl; 439 ifp->if_start = urtwn_start; 440 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 441 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 442 IFQ_SET_READY(&ifp->if_snd); 443 444 ic->ic_ifp = ifp; 445 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 446 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 447 448 /* set device capabilities */ 449 ic->ic_caps = 450 IEEE80211_C_STA /* station mode */ 451 | IEEE80211_C_MONITOR /* monitor mode */ 452 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 453 | IEEE80211_C_SHSLOT /* short slot time supported */ 454 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 455 | IEEE80211_C_WPA /* 802.11i */ 456 ; 457 458 bands = 0; 459 setbit(&bands, IEEE80211_MODE_11B); 460 setbit(&bands, IEEE80211_MODE_11G); 461 ieee80211_init_channels(ic, NULL, &bands); 462 463 ieee80211_ifattach(ic, sc->sc_bssid); 464 ic->ic_raw_xmit = urtwn_raw_xmit; 465 ic->ic_scan_start = urtwn_scan_start; 466 ic->ic_scan_end = urtwn_scan_end; 467 ic->ic_set_channel = urtwn_set_channel; 468 469 ic->ic_vap_create = urtwn_vap_create; 470 ic->ic_vap_delete = urtwn_vap_delete; 471 ic->ic_update_mcast = urtwn_update_mcast; 472 473 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 474 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 475 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 476 URTWN_RX_RADIOTAP_PRESENT); 477 478 if (bootverbose) 479 ieee80211_announce(ic); 480 481 return (0); 482 483detach: 484 urtwn_detach(self); 485 return (ENXIO); /* failure */ 486} 487 488static int 489urtwn_detach(device_t self) 490{ 491 struct urtwn_softc *sc = device_get_softc(self); 492 struct ifnet *ifp = sc->sc_ifp; 493 struct ieee80211com *ic = ifp->if_l2com; 494 unsigned int x; 495 496 /* Prevent further ioctls. */ 497 URTWN_LOCK(sc); 498 sc->sc_flags |= URTWN_DETACHED; 499 URTWN_UNLOCK(sc); 500 501 urtwn_stop(ifp); 502 503 callout_drain(&sc->sc_watchdog_ch); 504 505 /* Prevent further allocations from RX/TX data lists. */ 506 URTWN_LOCK(sc); 507 STAILQ_INIT(&sc->sc_tx_active); 508 STAILQ_INIT(&sc->sc_tx_inactive); 509 STAILQ_INIT(&sc->sc_tx_pending); 510 511 STAILQ_INIT(&sc->sc_rx_active); 512 STAILQ_INIT(&sc->sc_rx_inactive); 513 URTWN_UNLOCK(sc); 514 515 /* drain USB transfers */ 516 for (x = 0; x != URTWN_N_TRANSFER; x++) 517 usbd_transfer_drain(sc->sc_xfer[x]); 518 519 /* Free data buffers. */ 520 URTWN_LOCK(sc); 521 urtwn_free_tx_list(sc); 522 urtwn_free_rx_list(sc); 523 URTWN_UNLOCK(sc); 524 525 /* stop all USB transfers */ 526 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 527 ieee80211_ifdetach(ic); 528 529 if_free(ifp); 530 mtx_destroy(&sc->sc_mtx); 531 532 return (0); 533} 534 535static void 536urtwn_free_tx_list(struct urtwn_softc *sc) 537{ 538 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 539} 540 541static void 542urtwn_free_rx_list(struct urtwn_softc *sc) 543{ 544 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 545} 546 547static void 548urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 549{ 550 int i; 551 552 for (i = 0; i < ndata; i++) { 553 struct urtwn_data *dp = &data[i]; 554 555 if (dp->buf != NULL) { 556 free(dp->buf, M_USBDEV); 557 dp->buf = NULL; 558 } 559 if (dp->ni != NULL) { 560 ieee80211_free_node(dp->ni); 561 dp->ni = NULL; 562 } 563 } 564} 565 566static usb_error_t 567urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 568 void *data) 569{ 570 usb_error_t err; 571 int ntries = 10; 572 573 URTWN_ASSERT_LOCKED(sc); 574 575 while (ntries--) { 576 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 577 req, data, 0, NULL, 250 /* ms */); 578 if (err == 0) 579 break; 580 581 DPRINTFN(1, "Control request failed, %s (retrying)\n", 582 usbd_errstr(err)); 583 usb_pause_mtx(&sc->sc_mtx, hz / 100); 584 } 585 return (err); 586} 587 588static struct ieee80211vap * 589urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 590 enum ieee80211_opmode opmode, int flags, 591 const uint8_t bssid[IEEE80211_ADDR_LEN], 592 const uint8_t mac[IEEE80211_ADDR_LEN]) 593{ 594 struct urtwn_vap *uvp; 595 struct ieee80211vap *vap; 596 597 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 598 return (NULL); 599 600 uvp = (struct urtwn_vap *) malloc(sizeof(struct urtwn_vap), 601 M_80211_VAP, M_NOWAIT | M_ZERO); 602 if (uvp == NULL) 603 return (NULL); 604 vap = &uvp->vap; 605 /* enable s/w bmiss handling for sta mode */ 606 607 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 608 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac) != 0) { 609 /* out of memory */ 610 free(uvp, M_80211_VAP); 611 return (NULL); 612 } 613 614 /* override state transition machine */ 615 uvp->newstate = vap->iv_newstate; 616 vap->iv_newstate = urtwn_newstate; 617 618 /* complete setup */ 619 ieee80211_vap_attach(vap, ieee80211_media_change, 620 ieee80211_media_status); 621 ic->ic_opmode = opmode; 622 return (vap); 623} 624 625static void 626urtwn_vap_delete(struct ieee80211vap *vap) 627{ 628 struct urtwn_vap *uvp = URTWN_VAP(vap); 629 630 ieee80211_vap_detach(vap); 631 free(uvp, M_80211_VAP); 632} 633 634static struct mbuf * 635urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 636{ 637 struct ifnet *ifp = sc->sc_ifp; 638 struct ieee80211com *ic = ifp->if_l2com; 639 struct ieee80211_frame *wh; 640 struct mbuf *m; 641 struct r92c_rx_stat *stat; 642 uint32_t rxdw0, rxdw3; 643 uint8_t rate; 644 int8_t rssi = 0; 645 int infosz; 646 647 /* 648 * don't pass packets to the ieee80211 framework if the driver isn't 649 * RUNNING. 650 */ 651 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 652 return (NULL); 653 654 stat = (struct r92c_rx_stat *)buf; 655 rxdw0 = le32toh(stat->rxdw0); 656 rxdw3 = le32toh(stat->rxdw3); 657 658 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 659 /* 660 * This should not happen since we setup our Rx filter 661 * to not receive these frames. 662 */ 663 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 664 return (NULL); 665 } 666 if (pktlen < sizeof(*wh) || pktlen > MCLBYTES) { 667 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 668 return (NULL); 669 } 670 671 rate = MS(rxdw3, R92C_RXDW3_RATE); 672 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 673 674 /* Get RSSI from PHY status descriptor if present. */ 675 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 676 if (sc->chip & URTWN_CHIP_88E) 677 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 678 else 679 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 680 /* Update our average RSSI. */ 681 urtwn_update_avgrssi(sc, rate, rssi); 682 /* 683 * Convert the RSSI to a range that will be accepted 684 * by net80211. 685 */ 686 rssi = URTWN_RSSI(rssi); 687 } 688 689 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 690 if (m == NULL) { 691 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 692 return (NULL); 693 } 694 695 /* Finalize mbuf. */ 696 m->m_pkthdr.rcvif = ifp; 697 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 698 memcpy(mtod(m, uint8_t *), wh, pktlen); 699 m->m_pkthdr.len = m->m_len = pktlen; 700 701 if (ieee80211_radiotap_active(ic)) { 702 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 703 704 tap->wr_flags = 0; 705 /* Map HW rate index to 802.11 rate. */ 706 if (!(rxdw3 & R92C_RXDW3_HT)) { 707 switch (rate) { 708 /* CCK. */ 709 case 0: tap->wr_rate = 2; break; 710 case 1: tap->wr_rate = 4; break; 711 case 2: tap->wr_rate = 11; break; 712 case 3: tap->wr_rate = 22; break; 713 /* OFDM. */ 714 case 4: tap->wr_rate = 12; break; 715 case 5: tap->wr_rate = 18; break; 716 case 6: tap->wr_rate = 24; break; 717 case 7: tap->wr_rate = 36; break; 718 case 8: tap->wr_rate = 48; break; 719 case 9: tap->wr_rate = 72; break; 720 case 10: tap->wr_rate = 96; break; 721 case 11: tap->wr_rate = 108; break; 722 } 723 } else if (rate >= 12) { /* MCS0~15. */ 724 /* Bit 7 set means HT MCS instead of rate. */ 725 tap->wr_rate = 0x80 | (rate - 12); 726 } 727 tap->wr_dbm_antsignal = rssi; 728 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 729 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 730 } 731 732 *rssi_p = rssi; 733 734 return (m); 735} 736 737static struct mbuf * 738urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 739 int8_t *nf) 740{ 741 struct urtwn_softc *sc = data->sc; 742 struct ifnet *ifp = sc->sc_ifp; 743 struct r92c_rx_stat *stat; 744 struct mbuf *m, *m0 = NULL, *prevm = NULL; 745 uint32_t rxdw0; 746 uint8_t *buf; 747 int len, totlen, pktlen, infosz, npkts; 748 749 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 750 751 if (len < sizeof(*stat)) { 752 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 753 return (NULL); 754 } 755 756 buf = data->buf; 757 /* Get the number of encapsulated frames. */ 758 stat = (struct r92c_rx_stat *)buf; 759 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 760 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 761 762 /* Process all of them. */ 763 while (npkts-- > 0) { 764 if (len < sizeof(*stat)) 765 break; 766 stat = (struct r92c_rx_stat *)buf; 767 rxdw0 = le32toh(stat->rxdw0); 768 769 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 770 if (pktlen == 0) 771 break; 772 773 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 774 775 /* Make sure everything fits in xfer. */ 776 totlen = sizeof(*stat) + infosz + pktlen; 777 if (totlen > len) 778 break; 779 780 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 781 if (m0 == NULL) 782 m0 = m; 783 if (prevm == NULL) 784 prevm = m; 785 else { 786 prevm->m_next = m; 787 prevm = m; 788 } 789 790 /* Next chunk is 128-byte aligned. */ 791 totlen = (totlen + 127) & ~127; 792 buf += totlen; 793 len -= totlen; 794 } 795 796 return (m0); 797} 798 799static void 800urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 801{ 802 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 803 struct ifnet *ifp = sc->sc_ifp; 804 struct ieee80211com *ic = ifp->if_l2com; 805 struct ieee80211_frame *wh; 806 struct ieee80211_node *ni; 807 struct mbuf *m = NULL, *next; 808 struct urtwn_data *data; 809 int8_t nf; 810 int rssi = 1; 811 812 URTWN_ASSERT_LOCKED(sc); 813 814 switch (USB_GET_STATE(xfer)) { 815 case USB_ST_TRANSFERRED: 816 data = STAILQ_FIRST(&sc->sc_rx_active); 817 if (data == NULL) 818 goto tr_setup; 819 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 820 m = urtwn_rxeof(xfer, data, &rssi, &nf); 821 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 822 /* FALLTHROUGH */ 823 case USB_ST_SETUP: 824tr_setup: 825 data = STAILQ_FIRST(&sc->sc_rx_inactive); 826 if (data == NULL) { 827 KASSERT(m == NULL, ("mbuf isn't NULL")); 828 return; 829 } 830 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 831 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 832 usbd_xfer_set_frame_data(xfer, 0, data->buf, 833 usbd_xfer_max_len(xfer)); 834 usbd_transfer_submit(xfer); 835 836 /* 837 * To avoid LOR we should unlock our private mutex here to call 838 * ieee80211_input() because here is at the end of a USB 839 * callback and safe to unlock. 840 */ 841 URTWN_UNLOCK(sc); 842 while (m != NULL) { 843 next = m->m_next; 844 m->m_next = NULL; 845 wh = mtod(m, struct ieee80211_frame *); 846 ni = ieee80211_find_rxnode(ic, 847 (struct ieee80211_frame_min *)wh); 848 nf = URTWN_NOISE_FLOOR; 849 if (ni != NULL) { 850 (void)ieee80211_input(ni, m, rssi, nf); 851 ieee80211_free_node(ni); 852 } else 853 (void)ieee80211_input_all(ic, m, rssi, nf); 854 m = next; 855 } 856 URTWN_LOCK(sc); 857 break; 858 default: 859 /* needs it to the inactive queue due to a error. */ 860 data = STAILQ_FIRST(&sc->sc_rx_active); 861 if (data != NULL) { 862 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 863 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 864 } 865 if (error != USB_ERR_CANCELLED) { 866 usbd_xfer_set_stall(xfer); 867 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 868 goto tr_setup; 869 } 870 break; 871 } 872} 873 874static void 875urtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 876{ 877 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 878 struct ifnet *ifp = sc->sc_ifp; 879 struct mbuf *m; 880 881 URTWN_ASSERT_LOCKED(sc); 882 883 /* 884 * Do any tx complete callback. Note this must be done before releasing 885 * the node reference. 886 */ 887 if (data->m) { 888 m = data->m; 889 if (m->m_flags & M_TXCB) { 890 /* XXX status? */ 891 ieee80211_process_callback(data->ni, m, 0); 892 } 893 m_freem(m); 894 data->m = NULL; 895 } 896 if (data->ni) { 897 ieee80211_free_node(data->ni); 898 data->ni = NULL; 899 } 900 sc->sc_txtimer = 0; 901 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 902 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 903} 904 905static void 906urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 907{ 908 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 909 struct ifnet *ifp = sc->sc_ifp; 910 struct urtwn_data *data; 911 912 URTWN_ASSERT_LOCKED(sc); 913 914 switch (USB_GET_STATE(xfer)){ 915 case USB_ST_TRANSFERRED: 916 data = STAILQ_FIRST(&sc->sc_tx_active); 917 if (data == NULL) 918 goto tr_setup; 919 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 920 urtwn_txeof(xfer, data); 921 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 922 /* FALLTHROUGH */ 923 case USB_ST_SETUP: 924tr_setup: 925 data = STAILQ_FIRST(&sc->sc_tx_pending); 926 if (data == NULL) { 927 DPRINTF("%s: empty pending queue\n", __func__); 928 return; 929 } 930 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 931 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 932 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 933 usbd_transfer_submit(xfer); 934 urtwn_start_locked(ifp, sc); 935 break; 936 default: 937 data = STAILQ_FIRST(&sc->sc_tx_active); 938 if (data == NULL) 939 goto tr_setup; 940 if (data->ni != NULL) { 941 ieee80211_free_node(data->ni); 942 data->ni = NULL; 943 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 944 } 945 if (error != USB_ERR_CANCELLED) { 946 usbd_xfer_set_stall(xfer); 947 goto tr_setup; 948 } 949 break; 950 } 951} 952 953static struct urtwn_data * 954_urtwn_getbuf(struct urtwn_softc *sc) 955{ 956 struct urtwn_data *bf; 957 958 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 959 if (bf != NULL) 960 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 961 else 962 bf = NULL; 963 if (bf == NULL) 964 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 965 return (bf); 966} 967 968static struct urtwn_data * 969urtwn_getbuf(struct urtwn_softc *sc) 970{ 971 struct urtwn_data *bf; 972 973 URTWN_ASSERT_LOCKED(sc); 974 975 bf = _urtwn_getbuf(sc); 976 if (bf == NULL) { 977 struct ifnet *ifp = sc->sc_ifp; 978 DPRINTF("%s: stop queue\n", __func__); 979 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 980 } 981 return (bf); 982} 983 984static int 985urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 986 int len) 987{ 988 usb_device_request_t req; 989 990 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 991 req.bRequest = R92C_REQ_REGS; 992 USETW(req.wValue, addr); 993 USETW(req.wIndex, 0); 994 USETW(req.wLength, len); 995 return (urtwn_do_request(sc, &req, buf)); 996} 997 998static void 999urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1000{ 1001 urtwn_write_region_1(sc, addr, &val, 1); 1002} 1003 1004 1005static void 1006urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1007{ 1008 val = htole16(val); 1009 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1010} 1011 1012static void 1013urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1014{ 1015 val = htole32(val); 1016 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1017} 1018 1019static int 1020urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1021 int len) 1022{ 1023 usb_device_request_t req; 1024 1025 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1026 req.bRequest = R92C_REQ_REGS; 1027 USETW(req.wValue, addr); 1028 USETW(req.wIndex, 0); 1029 USETW(req.wLength, len); 1030 return (urtwn_do_request(sc, &req, buf)); 1031} 1032 1033static uint8_t 1034urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1035{ 1036 uint8_t val; 1037 1038 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1039 return (0xff); 1040 return (val); 1041} 1042 1043static uint16_t 1044urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1045{ 1046 uint16_t val; 1047 1048 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1049 return (0xffff); 1050 return (le16toh(val)); 1051} 1052 1053static uint32_t 1054urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1055{ 1056 uint32_t val; 1057 1058 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1059 return (0xffffffff); 1060 return (le32toh(val)); 1061} 1062 1063static int 1064urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1065{ 1066 struct r92c_fw_cmd cmd; 1067 int ntries; 1068 1069 /* Wait for current FW box to be empty. */ 1070 for (ntries = 0; ntries < 100; ntries++) { 1071 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1072 break; 1073 urtwn_ms_delay(sc); 1074 } 1075 if (ntries == 100) { 1076 device_printf(sc->sc_dev, 1077 "could not send firmware command\n"); 1078 return (ETIMEDOUT); 1079 } 1080 memset(&cmd, 0, sizeof(cmd)); 1081 cmd.id = id; 1082 if (len > 3) 1083 cmd.id |= R92C_CMD_FLAG_EXT; 1084 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1085 memcpy(cmd.msg, buf, len); 1086 1087 /* Write the first word last since that will trigger the FW. */ 1088 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1089 (uint8_t *)&cmd + 4, 2); 1090 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1091 (uint8_t *)&cmd + 0, 4); 1092 1093 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1094 return (0); 1095} 1096 1097static __inline void 1098urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1099{ 1100 1101 sc->sc_rf_write(sc, chain, addr, val); 1102} 1103 1104static void 1105urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1106 uint32_t val) 1107{ 1108 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1109 SM(R92C_LSSI_PARAM_ADDR, addr) | 1110 SM(R92C_LSSI_PARAM_DATA, val)); 1111} 1112 1113static void 1114urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1115uint32_t val) 1116{ 1117 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1118 SM(R88E_LSSI_PARAM_ADDR, addr) | 1119 SM(R92C_LSSI_PARAM_DATA, val)); 1120} 1121 1122static uint32_t 1123urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1124{ 1125 uint32_t reg[R92C_MAX_CHAINS], val; 1126 1127 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1128 if (chain != 0) 1129 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1130 1131 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1132 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1133 urtwn_ms_delay(sc); 1134 1135 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1136 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1137 R92C_HSSI_PARAM2_READ_EDGE); 1138 urtwn_ms_delay(sc); 1139 1140 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1141 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1142 urtwn_ms_delay(sc); 1143 1144 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1145 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1146 else 1147 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1148 return (MS(val, R92C_LSSI_READBACK_DATA)); 1149} 1150 1151static int 1152urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1153{ 1154 int ntries; 1155 1156 urtwn_write_4(sc, R92C_LLT_INIT, 1157 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1158 SM(R92C_LLT_INIT_ADDR, addr) | 1159 SM(R92C_LLT_INIT_DATA, data)); 1160 /* Wait for write operation to complete. */ 1161 for (ntries = 0; ntries < 20; ntries++) { 1162 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1163 R92C_LLT_INIT_OP_NO_ACTIVE) 1164 return (0); 1165 urtwn_ms_delay(sc); 1166 } 1167 return (ETIMEDOUT); 1168} 1169 1170static uint8_t 1171urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1172{ 1173 uint32_t reg; 1174 int ntries; 1175 1176 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1177 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1178 reg &= ~R92C_EFUSE_CTRL_VALID; 1179 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1180 /* Wait for read operation to complete. */ 1181 for (ntries = 0; ntries < 100; ntries++) { 1182 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1183 if (reg & R92C_EFUSE_CTRL_VALID) 1184 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1185 urtwn_ms_delay(sc); 1186 } 1187 device_printf(sc->sc_dev, 1188 "could not read efuse byte at address 0x%x\n", addr); 1189 return (0xff); 1190} 1191 1192static void 1193urtwn_efuse_read(struct urtwn_softc *sc) 1194{ 1195 uint8_t *rom = (uint8_t *)&sc->rom; 1196 uint16_t addr = 0; 1197 uint32_t reg; 1198 uint8_t off, msk, vol; 1199 int i; 1200 1201 urtwn_efuse_switch_power(sc); 1202 1203 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1204 while (addr < 512) { 1205 reg = urtwn_efuse_read_1(sc, addr); 1206 if (reg == 0xff) 1207 break; 1208 addr++; 1209 off = reg >> 4; 1210 msk = reg & 0xf; 1211 for (i = 0; i < 4; i++) { 1212 if (msk & (1 << i)) 1213 continue; 1214 rom[off * 8 + i * 2 + 0] = 1215 urtwn_efuse_read_1(sc, addr); 1216 addr++; 1217 rom[off * 8 + i * 2 + 1] = 1218 urtwn_efuse_read_1(sc, addr); 1219 addr++; 1220 } 1221 } 1222#ifdef URTWN_DEBUG 1223 if (urtwn_debug >= 2) { 1224 /* Dump ROM content. */ 1225 printf("\n"); 1226 for (i = 0; i < sizeof(sc->rom); i++) 1227 printf("%02x:", rom[i]); 1228 printf("\n"); 1229 } 1230#endif 1231 /* Disable LDO 2.5V. */ 1232 vol = urtwn_read_1(sc, R92C_EFUSE_TEST + 3); 1233 urtwn_write_1(sc, R92C_EFUSE_TEST + 3, vol & ~(0x80)); 1234 1235} 1236static void 1237urtwn_efuse_switch_power(struct urtwn_softc *sc) 1238{ 1239 uint32_t reg; 1240 1241 if (sc->chip & URTWN_CHIP_88E) 1242 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1243 1244 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1245 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1246 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1247 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1248 } 1249 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1250 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1251 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1252 reg | R92C_SYS_FUNC_EN_ELDR); 1253 } 1254 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1255 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1256 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1257 urtwn_write_2(sc, R92C_SYS_CLKR, 1258 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1259 } 1260 1261 if (!(sc->chip & URTWN_CHIP_88E)) { 1262 uint8_t vol; 1263 1264 /* Enable LDO 2.5V. */ 1265 vol = urtwn_read_1(sc, R92C_EFUSE_TEST + 3); 1266 vol &= 0x0f; 1267 vol |= 0x30; 1268 urtwn_write_1(sc, R92C_EFUSE_TEST + 3, (vol | 0x80)); 1269 } 1270} 1271 1272static int 1273urtwn_read_chipid(struct urtwn_softc *sc) 1274{ 1275 uint32_t reg; 1276 1277 if (sc->chip & URTWN_CHIP_88E) 1278 return (0); 1279 1280 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1281 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1282 return (EIO); 1283 1284 if (reg & R92C_SYS_CFG_TYPE_92C) { 1285 sc->chip |= URTWN_CHIP_92C; 1286 /* Check if it is a castrated 8192C. */ 1287 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1288 R92C_HPON_FSM_CHIP_BONDING_ID) == 1289 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1290 sc->chip |= URTWN_CHIP_92C_1T2R; 1291 } 1292 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1293 sc->chip |= URTWN_CHIP_UMC; 1294 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1295 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1296 } 1297 return (0); 1298} 1299 1300static void 1301urtwn_read_rom(struct urtwn_softc *sc) 1302{ 1303 struct r92c_rom *rom = &sc->rom; 1304 1305 /* Read full ROM image. */ 1306 urtwn_efuse_read(sc); 1307 1308 /* XXX Weird but this is what the vendor driver does. */ 1309 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1310 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1311 1312 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1313 1314 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1315 DPRINTF("regulatory type=%d\n", sc->regulatory); 1316 IEEE80211_ADDR_COPY(sc->sc_bssid, rom->macaddr); 1317 1318 sc->sc_rf_write = urtwn_r92c_rf_write; 1319 sc->sc_power_on = urtwn_r92c_power_on; 1320 sc->sc_dma_init = urtwn_r92c_dma_init; 1321} 1322 1323static void 1324urtwn_r88e_read_rom(struct urtwn_softc *sc) 1325{ 1326 uint8_t *rom = sc->r88e_rom; 1327 uint16_t addr = 0; 1328 uint32_t reg; 1329 uint8_t off, msk, tmp; 1330 int i; 1331 1332 off = 0; 1333 urtwn_efuse_switch_power(sc); 1334 1335 /* Read full ROM image. */ 1336 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1337 while (addr < 512) { 1338 reg = urtwn_efuse_read_1(sc, addr); 1339 if (reg == 0xff) 1340 break; 1341 addr++; 1342 if ((reg & 0x1f) == 0x0f) { 1343 tmp = (reg & 0xe0) >> 5; 1344 reg = urtwn_efuse_read_1(sc, addr); 1345 if ((reg & 0x0f) != 0x0f) 1346 off = ((reg & 0xf0) >> 1) | tmp; 1347 addr++; 1348 } else 1349 off = reg >> 4; 1350 msk = reg & 0xf; 1351 for (i = 0; i < 4; i++) { 1352 if (msk & (1 << i)) 1353 continue; 1354 rom[off * 8 + i * 2 + 0] = 1355 urtwn_efuse_read_1(sc, addr); 1356 addr++; 1357 rom[off * 8 + i * 2 + 1] = 1358 urtwn_efuse_read_1(sc, addr); 1359 addr++; 1360 } 1361 } 1362 1363 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1364 1365 addr = 0x10; 1366 for (i = 0; i < 6; i++) 1367 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1368 for (i = 0; i < 5; i++) 1369 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1370 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1371 if (sc->bw20_tx_pwr_diff & 0x08) 1372 sc->bw20_tx_pwr_diff |= 0xf0; 1373 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1374 if (sc->ofdm_tx_pwr_diff & 0x08) 1375 sc->ofdm_tx_pwr_diff |= 0xf0; 1376 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1377 IEEE80211_ADDR_COPY(sc->sc_bssid, &sc->r88e_rom[0xd7]); 1378 1379 sc->sc_rf_write = urtwn_r88e_rf_write; 1380 sc->sc_power_on = urtwn_r88e_power_on; 1381 sc->sc_dma_init = urtwn_r88e_dma_init; 1382} 1383 1384/* 1385 * Initialize rate adaptation in firmware. 1386 */ 1387static int 1388urtwn_ra_init(struct urtwn_softc *sc) 1389{ 1390 static const uint8_t map[] = 1391 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1392 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1393 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1394 struct ieee80211_node *ni; 1395 struct ieee80211_rateset *rs; 1396 struct r92c_fw_cmd_macid_cfg cmd; 1397 uint32_t rates, basicrates; 1398 uint8_t mode; 1399 int maxrate, maxbasicrate, error, i, j; 1400 1401 ni = ieee80211_ref_node(vap->iv_bss); 1402 rs = &ni->ni_rates; 1403 1404 /* Get normal and basic rates mask. */ 1405 rates = basicrates = 0; 1406 maxrate = maxbasicrate = 0; 1407 for (i = 0; i < rs->rs_nrates; i++) { 1408 /* Convert 802.11 rate to HW rate index. */ 1409 for (j = 0; j < nitems(map); j++) 1410 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1411 break; 1412 if (j == nitems(map)) /* Unknown rate, skip. */ 1413 continue; 1414 rates |= 1 << j; 1415 if (j > maxrate) 1416 maxrate = j; 1417 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1418 basicrates |= 1 << j; 1419 if (j > maxbasicrate) 1420 maxbasicrate = j; 1421 } 1422 } 1423 if (ic->ic_curmode == IEEE80211_MODE_11B) 1424 mode = R92C_RAID_11B; 1425 else 1426 mode = R92C_RAID_11BG; 1427 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1428 mode, rates, basicrates); 1429 1430 /* Set rates mask for group addressed frames. */ 1431 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1432 cmd.mask = htole32(mode << 28 | basicrates); 1433 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1434 if (error != 0) { 1435 ieee80211_free_node(ni); 1436 device_printf(sc->sc_dev, 1437 "could not add broadcast station\n"); 1438 return (error); 1439 } 1440 /* Set initial MRR rate. */ 1441 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1442 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1443 maxbasicrate); 1444 1445 /* Set rates mask for unicast frames. */ 1446 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1447 cmd.mask = htole32(mode << 28 | rates); 1448 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1449 if (error != 0) { 1450 ieee80211_free_node(ni); 1451 device_printf(sc->sc_dev, "could not add BSS station\n"); 1452 return (error); 1453 } 1454 /* Set initial MRR rate. */ 1455 DPRINTF("maxrate=%d\n", maxrate); 1456 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1457 maxrate); 1458 1459 /* Indicate highest supported rate. */ 1460 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1461 ieee80211_free_node(ni); 1462 1463 return (0); 1464} 1465 1466void 1467urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1468{ 1469 struct ifnet *ifp = sc->sc_ifp; 1470 struct ieee80211com *ic = ifp->if_l2com; 1471 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1472 struct ieee80211_node *ni = vap->iv_bss; 1473 1474 uint64_t tsf; 1475 1476 /* Enable TSF synchronization. */ 1477 urtwn_write_1(sc, R92C_BCN_CTRL, 1478 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1479 1480 urtwn_write_1(sc, R92C_BCN_CTRL, 1481 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1482 1483 /* Set initial TSF. */ 1484 memcpy(&tsf, ni->ni_tstamp.data, 8); 1485 tsf = le64toh(tsf); 1486 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1487 tsf -= IEEE80211_DUR_TU; 1488 urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1489 urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1490 1491 urtwn_write_1(sc, R92C_BCN_CTRL, 1492 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1493} 1494 1495static void 1496urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1497{ 1498 uint8_t reg; 1499 1500 if (led == URTWN_LED_LINK) { 1501 if (sc->chip & URTWN_CHIP_88E) { 1502 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1503 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1504 if (!on) { 1505 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1506 urtwn_write_1(sc, R92C_LEDCFG2, 1507 reg | R92C_LEDCFG0_DIS); 1508 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1509 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1510 0xfe); 1511 } 1512 } else { 1513 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1514 if (!on) 1515 reg |= R92C_LEDCFG0_DIS; 1516 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1517 } 1518 sc->ledlink = on; /* Save LED state. */ 1519 } 1520} 1521 1522static int 1523urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1524{ 1525 struct urtwn_vap *uvp = URTWN_VAP(vap); 1526 struct ieee80211com *ic = vap->iv_ic; 1527 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1528 struct ieee80211_node *ni; 1529 enum ieee80211_state ostate; 1530 uint32_t reg; 1531 1532 ostate = vap->iv_state; 1533 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1534 ieee80211_state_name[nstate]); 1535 1536 IEEE80211_UNLOCK(ic); 1537 URTWN_LOCK(sc); 1538 callout_stop(&sc->sc_watchdog_ch); 1539 1540 if (ostate == IEEE80211_S_RUN) { 1541 /* Turn link LED off. */ 1542 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1543 1544 /* Set media status to 'No Link'. */ 1545 reg = urtwn_read_4(sc, R92C_CR); 1546 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1547 urtwn_write_4(sc, R92C_CR, reg); 1548 1549 /* Stop Rx of data frames. */ 1550 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1551 1552 /* Rest TSF. */ 1553 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1554 1555 /* Disable TSF synchronization. */ 1556 urtwn_write_1(sc, R92C_BCN_CTRL, 1557 urtwn_read_1(sc, R92C_BCN_CTRL) | 1558 R92C_BCN_CTRL_DIS_TSF_UDT0); 1559 1560 /* Reset EDCA parameters. */ 1561 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1562 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1563 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1564 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1565 } 1566 1567 switch (nstate) { 1568 case IEEE80211_S_INIT: 1569 /* Turn link LED off. */ 1570 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1571 break; 1572 case IEEE80211_S_SCAN: 1573 if (ostate != IEEE80211_S_SCAN) { 1574 /* Allow Rx from any BSSID. */ 1575 urtwn_write_4(sc, R92C_RCR, 1576 urtwn_read_4(sc, R92C_RCR) & 1577 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1578 1579 /* Set gain for scanning. */ 1580 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1581 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1582 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1583 1584 if (!(sc->chip & URTWN_CHIP_88E)) { 1585 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1586 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1587 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1588 } 1589 } 1590 /* Pause AC Tx queues. */ 1591 urtwn_write_1(sc, R92C_TXPAUSE, 1592 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1593 break; 1594 case IEEE80211_S_AUTH: 1595 /* Set initial gain under link. */ 1596 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1597 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1598 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1599 1600 if (!(sc->chip & URTWN_CHIP_88E)) { 1601 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1602 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1603 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1604 } 1605 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1606 break; 1607 case IEEE80211_S_RUN: 1608 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1609 /* Enable Rx of data frames. */ 1610 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1611 1612 /* Turn link LED on. */ 1613 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1614 break; 1615 } 1616 1617 ni = ieee80211_ref_node(vap->iv_bss); 1618 /* Set media status to 'Associated'. */ 1619 reg = urtwn_read_4(sc, R92C_CR); 1620 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1621 urtwn_write_4(sc, R92C_CR, reg); 1622 1623 /* Set BSSID. */ 1624 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1625 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1626 1627 if (ic->ic_curmode == IEEE80211_MODE_11B) 1628 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1629 else /* 802.11b/g */ 1630 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1631 1632 /* Enable Rx of data frames. */ 1633 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1634 1635 /* Flush all AC queues. */ 1636 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1637 1638 /* Set beacon interval. */ 1639 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1640 1641 /* Allow Rx from our BSSID only. */ 1642 urtwn_write_4(sc, R92C_RCR, 1643 urtwn_read_4(sc, R92C_RCR) | 1644 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1645 1646 /* Enable TSF synchronization. */ 1647 urtwn_tsf_sync_enable(sc); 1648 1649 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1650 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1651 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1652 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1653 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1654 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1655 1656 /* Intialize rate adaptation. */ 1657 if (sc->chip & URTWN_CHIP_88E) 1658 ni->ni_txrate = 1659 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1660 else 1661 urtwn_ra_init(sc); 1662 /* Turn link LED on. */ 1663 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1664 1665 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1666 /* Reset temperature calibration state machine. */ 1667 sc->thcal_state = 0; 1668 sc->thcal_lctemp = 0; 1669 ieee80211_free_node(ni); 1670 break; 1671 default: 1672 break; 1673 } 1674 URTWN_UNLOCK(sc); 1675 IEEE80211_LOCK(ic); 1676 return(uvp->newstate(vap, nstate, arg)); 1677} 1678 1679static void 1680urtwn_watchdog(void *arg) 1681{ 1682 struct urtwn_softc *sc = arg; 1683 struct ifnet *ifp = sc->sc_ifp; 1684 1685 if (sc->sc_txtimer > 0) { 1686 if (--sc->sc_txtimer == 0) { 1687 device_printf(sc->sc_dev, "device timeout\n"); 1688 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1689 return; 1690 } 1691 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1692 } 1693} 1694 1695static void 1696urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1697{ 1698 int pwdb; 1699 1700 /* Convert antenna signal to percentage. */ 1701 if (rssi <= -100 || rssi >= 20) 1702 pwdb = 0; 1703 else if (rssi >= 0) 1704 pwdb = 100; 1705 else 1706 pwdb = 100 + rssi; 1707 if (!(sc->chip & URTWN_CHIP_88E)) { 1708 if (rate <= 3) { 1709 /* CCK gain is smaller than OFDM/MCS gain. */ 1710 pwdb += 6; 1711 if (pwdb > 100) 1712 pwdb = 100; 1713 if (pwdb <= 14) 1714 pwdb -= 4; 1715 else if (pwdb <= 26) 1716 pwdb -= 8; 1717 else if (pwdb <= 34) 1718 pwdb -= 6; 1719 else if (pwdb <= 42) 1720 pwdb -= 2; 1721 } 1722 } 1723 if (sc->avg_pwdb == -1) /* Init. */ 1724 sc->avg_pwdb = pwdb; 1725 else if (sc->avg_pwdb < pwdb) 1726 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1727 else 1728 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1729 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1730} 1731 1732static int8_t 1733urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1734{ 1735 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1736 struct r92c_rx_phystat *phy; 1737 struct r92c_rx_cck *cck; 1738 uint8_t rpt; 1739 int8_t rssi; 1740 1741 if (rate <= 3) { 1742 cck = (struct r92c_rx_cck *)physt; 1743 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1744 rpt = (cck->agc_rpt >> 5) & 0x3; 1745 rssi = (cck->agc_rpt & 0x1f) << 1; 1746 } else { 1747 rpt = (cck->agc_rpt >> 6) & 0x3; 1748 rssi = cck->agc_rpt & 0x3e; 1749 } 1750 rssi = cckoff[rpt] - rssi; 1751 } else { /* OFDM/HT. */ 1752 phy = (struct r92c_rx_phystat *)physt; 1753 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1754 } 1755 return (rssi); 1756} 1757 1758static int8_t 1759urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1760{ 1761 struct r92c_rx_phystat *phy; 1762 struct r88e_rx_cck *cck; 1763 uint8_t cck_agc_rpt, lna_idx, vga_idx; 1764 int8_t rssi; 1765 1766 rssi = 0; 1767 if (rate <= 3) { 1768 cck = (struct r88e_rx_cck *)physt; 1769 cck_agc_rpt = cck->agc_rpt; 1770 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1771 vga_idx = cck_agc_rpt & 0x1f; 1772 switch (lna_idx) { 1773 case 7: 1774 if (vga_idx <= 27) 1775 rssi = -100 + 2* (27 - vga_idx); 1776 else 1777 rssi = -100; 1778 break; 1779 case 6: 1780 rssi = -48 + 2 * (2 - vga_idx); 1781 break; 1782 case 5: 1783 rssi = -42 + 2 * (7 - vga_idx); 1784 break; 1785 case 4: 1786 rssi = -36 + 2 * (7 - vga_idx); 1787 break; 1788 case 3: 1789 rssi = -24 + 2 * (7 - vga_idx); 1790 break; 1791 case 2: 1792 rssi = -12 + 2 * (5 - vga_idx); 1793 break; 1794 case 1: 1795 rssi = 8 - (2 * vga_idx); 1796 break; 1797 case 0: 1798 rssi = 14 - (2 * vga_idx); 1799 break; 1800 } 1801 rssi += 6; 1802 } else { /* OFDM/HT. */ 1803 phy = (struct r92c_rx_phystat *)physt; 1804 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1805 } 1806 return (rssi); 1807} 1808 1809 1810static int 1811urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1812 struct mbuf *m0, struct urtwn_data *data) 1813{ 1814 struct ifnet *ifp = sc->sc_ifp; 1815 struct ieee80211_frame *wh; 1816 struct ieee80211_key *k; 1817 struct ieee80211com *ic = ifp->if_l2com; 1818 struct ieee80211vap *vap = ni->ni_vap; 1819 struct usb_xfer *xfer; 1820 struct r92c_tx_desc *txd; 1821 uint8_t raid, type; 1822 uint16_t sum; 1823 int i, hasqos, xferlen; 1824 struct usb_xfer *urtwn_pipes[4] = { 1825 sc->sc_xfer[URTWN_BULK_TX_BE], 1826 sc->sc_xfer[URTWN_BULK_TX_BK], 1827 sc->sc_xfer[URTWN_BULK_TX_VI], 1828 sc->sc_xfer[URTWN_BULK_TX_VO] 1829 }; 1830 1831 URTWN_ASSERT_LOCKED(sc); 1832 1833 /* 1834 * Software crypto. 1835 */ 1836 wh = mtod(m0, struct ieee80211_frame *); 1837 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1838 1839 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1840 k = ieee80211_crypto_encap(ni, m0); 1841 if (k == NULL) { 1842 device_printf(sc->sc_dev, 1843 "ieee80211_crypto_encap returns NULL.\n"); 1844 /* XXX we don't expect the fragmented frames */ 1845 m_freem(m0); 1846 return (ENOBUFS); 1847 } 1848 1849 /* in case packet header moved, reset pointer */ 1850 wh = mtod(m0, struct ieee80211_frame *); 1851 } 1852 1853 switch (type) { 1854 case IEEE80211_FC0_TYPE_CTL: 1855 case IEEE80211_FC0_TYPE_MGT: 1856 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1857 break; 1858 default: 1859 KASSERT(M_WME_GETAC(m0) < 4, 1860 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1861 xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1862 break; 1863 } 1864 1865 hasqos = 0; 1866 1867 /* Fill Tx descriptor. */ 1868 txd = (struct r92c_tx_desc *)data->buf; 1869 memset(txd, 0, sizeof(*txd)); 1870 1871 txd->txdw0 |= htole32( 1872 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1873 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1874 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1875 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1876 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1877 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1878 type == IEEE80211_FC0_TYPE_DATA) { 1879 if (ic->ic_curmode == IEEE80211_MODE_11B) 1880 raid = R92C_RAID_11B; 1881 else 1882 raid = R92C_RAID_11BG; 1883 if (sc->chip & URTWN_CHIP_88E) { 1884 txd->txdw1 |= htole32( 1885 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1886 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1887 SM(R92C_TXDW1_RAID, raid)); 1888 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1889 } else { 1890 txd->txdw1 |= htole32( 1891 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1892 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1893 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1894 } 1895 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1896 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1897 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1898 R92C_TXDW4_HWRTSEN); 1899 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1900 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1901 R92C_TXDW4_HWRTSEN); 1902 } 1903 } 1904 /* Send RTS at OFDM24. */ 1905 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1906 txd->txdw5 |= htole32(0x0001ff00); 1907 /* Send data at OFDM54. */ 1908 if (sc->chip & URTWN_CHIP_88E) 1909 txd->txdw5 |= htole32(0x13 & 0x3f); 1910 else 1911 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1912 } else { 1913 txd->txdw1 |= htole32( 1914 SM(R92C_TXDW1_MACID, 0) | 1915 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1916 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1917 1918 /* Force CCK1. */ 1919 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1920 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1921 } 1922 /* Set sequence number (already little endian). */ 1923 txd->txdseq |= *(uint16_t *)wh->i_seq; 1924 1925 if (!hasqos) { 1926 /* Use HW sequence numbering for non-QoS frames. */ 1927 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1928 txd->txdseq |= htole16(0x8000); 1929 } else 1930 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1931 1932 /* Compute Tx descriptor checksum. */ 1933 sum = 0; 1934 for (i = 0; i < sizeof(*txd) / 2; i++) 1935 sum ^= ((uint16_t *)txd)[i]; 1936 txd->txdsum = sum; /* NB: already little endian. */ 1937 1938 if (ieee80211_radiotap_active_vap(vap)) { 1939 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1940 1941 tap->wt_flags = 0; 1942 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1943 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1944 ieee80211_radiotap_tx(vap, m0); 1945 } 1946 1947 xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1948 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1949 1950 data->buflen = xferlen; 1951 data->ni = ni; 1952 data->m = m0; 1953 1954 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1955 usbd_transfer_start(xfer); 1956 return (0); 1957} 1958 1959static void 1960urtwn_start(struct ifnet *ifp) 1961{ 1962 struct urtwn_softc *sc = ifp->if_softc; 1963 1964 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1965 return; 1966 URTWN_LOCK(sc); 1967 urtwn_start_locked(ifp, sc); 1968 URTWN_UNLOCK(sc); 1969} 1970 1971static void 1972urtwn_start_locked(struct ifnet *ifp, struct urtwn_softc *sc) 1973{ 1974 struct ieee80211_node *ni; 1975 struct mbuf *m; 1976 struct urtwn_data *bf; 1977 1978 URTWN_ASSERT_LOCKED(sc); 1979 for (;;) { 1980 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1981 if (m == NULL) 1982 break; 1983 bf = urtwn_getbuf(sc); 1984 if (bf == NULL) { 1985 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1986 break; 1987 } 1988 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1989 m->m_pkthdr.rcvif = NULL; 1990 1991 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 1992 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1993 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1994 ieee80211_free_node(ni); 1995 break; 1996 } 1997 1998 sc->sc_txtimer = 5; 1999 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2000 } 2001} 2002 2003static int 2004urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2005{ 2006 struct urtwn_softc *sc = ifp->if_softc; 2007 struct ieee80211com *ic = ifp->if_l2com; 2008 struct ifreq *ifr = (struct ifreq *) data; 2009 int error = 0, startall = 0; 2010 2011 URTWN_LOCK(sc); 2012 error = (sc->sc_flags & URTWN_DETACHED) ? ENXIO : 0; 2013 URTWN_UNLOCK(sc); 2014 if (error != 0) 2015 return (error); 2016 2017 switch (cmd) { 2018 case SIOCSIFFLAGS: 2019 if (ifp->if_flags & IFF_UP) { 2020 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2021 urtwn_init(ifp->if_softc); 2022 startall = 1; 2023 } 2024 } else { 2025 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2026 urtwn_stop(ifp); 2027 } 2028 if (startall) 2029 ieee80211_start_all(ic); 2030 break; 2031 case SIOCGIFMEDIA: 2032 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 2033 break; 2034 case SIOCGIFADDR: 2035 error = ether_ioctl(ifp, cmd, data); 2036 break; 2037 default: 2038 error = EINVAL; 2039 break; 2040 } 2041 return (error); 2042} 2043 2044static int 2045urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 2046 int ndata, int maxsz) 2047{ 2048 int i, error; 2049 2050 for (i = 0; i < ndata; i++) { 2051 struct urtwn_data *dp = &data[i]; 2052 dp->sc = sc; 2053 dp->m = NULL; 2054 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 2055 if (dp->buf == NULL) { 2056 device_printf(sc->sc_dev, 2057 "could not allocate buffer\n"); 2058 error = ENOMEM; 2059 goto fail; 2060 } 2061 dp->ni = NULL; 2062 } 2063 2064 return (0); 2065fail: 2066 urtwn_free_list(sc, data, ndata); 2067 return (error); 2068} 2069 2070static int 2071urtwn_alloc_rx_list(struct urtwn_softc *sc) 2072{ 2073 int error, i; 2074 2075 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 2076 URTWN_RXBUFSZ); 2077 if (error != 0) 2078 return (error); 2079 2080 STAILQ_INIT(&sc->sc_rx_active); 2081 STAILQ_INIT(&sc->sc_rx_inactive); 2082 2083 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 2084 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 2085 2086 return (0); 2087} 2088 2089static int 2090urtwn_alloc_tx_list(struct urtwn_softc *sc) 2091{ 2092 int error, i; 2093 2094 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 2095 URTWN_TXBUFSZ); 2096 if (error != 0) 2097 return (error); 2098 2099 STAILQ_INIT(&sc->sc_tx_active); 2100 STAILQ_INIT(&sc->sc_tx_inactive); 2101 STAILQ_INIT(&sc->sc_tx_pending); 2102 2103 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 2104 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 2105 2106 return (0); 2107} 2108 2109static __inline int 2110urtwn_power_on(struct urtwn_softc *sc) 2111{ 2112 2113 return sc->sc_power_on(sc); 2114} 2115 2116static int 2117urtwn_r92c_power_on(struct urtwn_softc *sc) 2118{ 2119 uint32_t reg; 2120 int ntries; 2121 2122 /* Wait for autoload done bit. */ 2123 for (ntries = 0; ntries < 1000; ntries++) { 2124 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2125 break; 2126 urtwn_ms_delay(sc); 2127 } 2128 if (ntries == 1000) { 2129 device_printf(sc->sc_dev, 2130 "timeout waiting for chip autoload\n"); 2131 return (ETIMEDOUT); 2132 } 2133 2134 /* Unlock ISO/CLK/Power control register. */ 2135 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2136 /* Move SPS into PWM mode. */ 2137 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2138 urtwn_ms_delay(sc); 2139 2140 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2141 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2142 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2143 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2144 urtwn_ms_delay(sc); 2145 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2146 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2147 ~R92C_SYS_ISO_CTRL_MD2PP); 2148 } 2149 2150 /* Auto enable WLAN. */ 2151 urtwn_write_2(sc, R92C_APS_FSMCO, 2152 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2153 for (ntries = 0; ntries < 1000; ntries++) { 2154 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2155 R92C_APS_FSMCO_APFM_ONMAC)) 2156 break; 2157 urtwn_ms_delay(sc); 2158 } 2159 if (ntries == 1000) { 2160 device_printf(sc->sc_dev, 2161 "timeout waiting for MAC auto ON\n"); 2162 return (ETIMEDOUT); 2163 } 2164 2165 /* Enable radio, GPIO and LED functions. */ 2166 urtwn_write_2(sc, R92C_APS_FSMCO, 2167 R92C_APS_FSMCO_AFSM_HSUS | 2168 R92C_APS_FSMCO_PDN_EN | 2169 R92C_APS_FSMCO_PFM_ALDN); 2170 /* Release RF digital isolation. */ 2171 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2172 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2173 2174 /* Initialize MAC. */ 2175 urtwn_write_1(sc, R92C_APSD_CTRL, 2176 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2177 for (ntries = 0; ntries < 200; ntries++) { 2178 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2179 R92C_APSD_CTRL_OFF_STATUS)) 2180 break; 2181 urtwn_ms_delay(sc); 2182 } 2183 if (ntries == 200) { 2184 device_printf(sc->sc_dev, 2185 "timeout waiting for MAC initialization\n"); 2186 return (ETIMEDOUT); 2187 } 2188 2189 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2190 reg = urtwn_read_2(sc, R92C_CR); 2191 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2192 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2193 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2194 R92C_CR_ENSEC; 2195 urtwn_write_2(sc, R92C_CR, reg); 2196 2197 urtwn_write_1(sc, 0xfe10, 0x19); 2198 return (0); 2199} 2200 2201static int 2202urtwn_r88e_power_on(struct urtwn_softc *sc) 2203{ 2204 uint32_t reg; 2205 int ntries; 2206 2207 /* Wait for power ready bit. */ 2208 for (ntries = 0; ntries < 5000; ntries++) { 2209 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2210 break; 2211 urtwn_ms_delay(sc); 2212 } 2213 if (ntries == 5000) { 2214 device_printf(sc->sc_dev, 2215 "timeout waiting for chip power up\n"); 2216 return (ETIMEDOUT); 2217 } 2218 2219 /* Reset BB. */ 2220 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2221 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2222 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2223 2224 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2225 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2226 2227 /* Disable HWPDN. */ 2228 urtwn_write_2(sc, R92C_APS_FSMCO, 2229 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2230 2231 /* Disable WL suspend. */ 2232 urtwn_write_2(sc, R92C_APS_FSMCO, 2233 urtwn_read_2(sc, R92C_APS_FSMCO) & 2234 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2235 2236 urtwn_write_2(sc, R92C_APS_FSMCO, 2237 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2238 for (ntries = 0; ntries < 5000; ntries++) { 2239 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2240 R92C_APS_FSMCO_APFM_ONMAC)) 2241 break; 2242 urtwn_ms_delay(sc); 2243 } 2244 if (ntries == 5000) 2245 return (ETIMEDOUT); 2246 2247 /* Enable LDO normal mode. */ 2248 urtwn_write_1(sc, R92C_LPLDO_CTRL, 2249 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2250 2251 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2252 urtwn_write_2(sc, R92C_CR, 0); 2253 reg = urtwn_read_2(sc, R92C_CR); 2254 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2255 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2256 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2257 urtwn_write_2(sc, R92C_CR, reg); 2258 2259 return (0); 2260} 2261 2262static int 2263urtwn_llt_init(struct urtwn_softc *sc) 2264{ 2265 int i, error, page_count, pktbuf_count; 2266 2267 page_count = (sc->chip & URTWN_CHIP_88E) ? 2268 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2269 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2270 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2271 2272 /* Reserve pages [0; page_count]. */ 2273 for (i = 0; i < page_count; i++) { 2274 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2275 return (error); 2276 } 2277 /* NB: 0xff indicates end-of-list. */ 2278 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2279 return (error); 2280 /* 2281 * Use pages [page_count + 1; pktbuf_count - 1] 2282 * as ring buffer. 2283 */ 2284 for (++i; i < pktbuf_count - 1; i++) { 2285 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2286 return (error); 2287 } 2288 /* Make the last page point to the beginning of the ring buffer. */ 2289 error = urtwn_llt_write(sc, i, page_count + 1); 2290 return (error); 2291} 2292 2293static void 2294urtwn_fw_reset(struct urtwn_softc *sc) 2295{ 2296 uint16_t reg; 2297 int ntries; 2298 2299 /* Tell 8051 to reset itself. */ 2300 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2301 2302 /* Wait until 8051 resets by itself. */ 2303 for (ntries = 0; ntries < 100; ntries++) { 2304 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2305 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2306 return; 2307 urtwn_ms_delay(sc); 2308 } 2309 /* Force 8051 reset. */ 2310 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2311} 2312 2313static void 2314urtwn_r88e_fw_reset(struct urtwn_softc *sc) 2315{ 2316 uint16_t reg; 2317 2318 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2319 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2320 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2321} 2322 2323static int 2324urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2325{ 2326 uint32_t reg; 2327 int off, mlen, error = 0; 2328 2329 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2330 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2331 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2332 2333 off = R92C_FW_START_ADDR; 2334 while (len > 0) { 2335 if (len > 196) 2336 mlen = 196; 2337 else if (len > 4) 2338 mlen = 4; 2339 else 2340 mlen = 1; 2341 /* XXX fix this deconst */ 2342 error = urtwn_write_region_1(sc, off, 2343 __DECONST(uint8_t *, buf), mlen); 2344 if (error != 0) 2345 break; 2346 off += mlen; 2347 buf += mlen; 2348 len -= mlen; 2349 } 2350 return (error); 2351} 2352 2353static int 2354urtwn_load_firmware(struct urtwn_softc *sc) 2355{ 2356 const struct firmware *fw; 2357 const struct r92c_fw_hdr *hdr; 2358 const char *imagename; 2359 const u_char *ptr; 2360 size_t len; 2361 uint32_t reg; 2362 int mlen, ntries, page, error; 2363 2364 URTWN_UNLOCK(sc); 2365 /* Read firmware image from the filesystem. */ 2366 if (sc->chip & URTWN_CHIP_88E) 2367 imagename = "urtwn-rtl8188eufw"; 2368 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2369 URTWN_CHIP_UMC_A_CUT) 2370 imagename = "urtwn-rtl8192cfwU"; 2371 else 2372 imagename = "urtwn-rtl8192cfwT"; 2373 2374 fw = firmware_get(imagename); 2375 URTWN_LOCK(sc); 2376 if (fw == NULL) { 2377 device_printf(sc->sc_dev, 2378 "failed loadfirmware of file %s\n", imagename); 2379 return (ENOENT); 2380 } 2381 2382 len = fw->datasize; 2383 2384 if (len < sizeof(*hdr)) { 2385 device_printf(sc->sc_dev, "firmware too short\n"); 2386 error = EINVAL; 2387 goto fail; 2388 } 2389 ptr = fw->data; 2390 hdr = (const struct r92c_fw_hdr *)ptr; 2391 /* Check if there is a valid FW header and skip it. */ 2392 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2393 (le16toh(hdr->signature) >> 4) == 0x88e || 2394 (le16toh(hdr->signature) >> 4) == 0x92c) { 2395 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2396 le16toh(hdr->version), le16toh(hdr->subversion), 2397 hdr->month, hdr->date, hdr->hour, hdr->minute); 2398 ptr += sizeof(*hdr); 2399 len -= sizeof(*hdr); 2400 } 2401 2402 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2403 if (sc->chip & URTWN_CHIP_88E) 2404 urtwn_r88e_fw_reset(sc); 2405 else 2406 urtwn_fw_reset(sc); 2407 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2408 } 2409 2410 if (!(sc->chip & URTWN_CHIP_88E)) { 2411 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2412 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2413 R92C_SYS_FUNC_EN_CPUEN); 2414 } 2415 urtwn_write_1(sc, R92C_MCUFWDL, 2416 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2417 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2418 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2419 2420 /* Reset the FWDL checksum. */ 2421 urtwn_write_1(sc, R92C_MCUFWDL, 2422 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2423 2424 for (page = 0; len > 0; page++) { 2425 mlen = min(len, R92C_FW_PAGE_SIZE); 2426 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2427 if (error != 0) { 2428 device_printf(sc->sc_dev, 2429 "could not load firmware page\n"); 2430 goto fail; 2431 } 2432 ptr += mlen; 2433 len -= mlen; 2434 } 2435 urtwn_write_1(sc, R92C_MCUFWDL, 2436 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2437 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2438 2439 /* Wait for checksum report. */ 2440 for (ntries = 0; ntries < 1000; ntries++) { 2441 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2442 break; 2443 urtwn_ms_delay(sc); 2444 } 2445 if (ntries == 1000) { 2446 device_printf(sc->sc_dev, 2447 "timeout waiting for checksum report\n"); 2448 error = ETIMEDOUT; 2449 goto fail; 2450 } 2451 2452 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2453 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2454 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2455 if (sc->chip & URTWN_CHIP_88E) 2456 urtwn_r88e_fw_reset(sc); 2457 /* Wait for firmware readiness. */ 2458 for (ntries = 0; ntries < 1000; ntries++) { 2459 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2460 break; 2461 urtwn_ms_delay(sc); 2462 } 2463 if (ntries == 1000) { 2464 device_printf(sc->sc_dev, 2465 "timeout waiting for firmware readiness\n"); 2466 error = ETIMEDOUT; 2467 goto fail; 2468 } 2469fail: 2470 firmware_put(fw, FIRMWARE_UNLOAD); 2471 return (error); 2472} 2473 2474static __inline int 2475urtwn_dma_init(struct urtwn_softc *sc) 2476{ 2477 2478 return sc->sc_dma_init(sc); 2479} 2480 2481static int 2482urtwn_r92c_dma_init(struct urtwn_softc *sc) 2483{ 2484 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2485 uint32_t reg; 2486 int error; 2487 2488 /* Initialize LLT table. */ 2489 error = urtwn_llt_init(sc); 2490 if (error != 0) 2491 return (error); 2492 2493 /* Get Tx queues to USB endpoints mapping. */ 2494 hashq = hasnq = haslq = 0; 2495 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2496 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2497 if (MS(reg, R92C_USB_EP_HQ) != 0) 2498 hashq = 1; 2499 if (MS(reg, R92C_USB_EP_NQ) != 0) 2500 hasnq = 1; 2501 if (MS(reg, R92C_USB_EP_LQ) != 0) 2502 haslq = 1; 2503 nqueues = hashq + hasnq + haslq; 2504 if (nqueues == 0) 2505 return (EIO); 2506 /* Get the number of pages for each queue. */ 2507 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2508 /* The remaining pages are assigned to the high priority queue. */ 2509 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2510 2511 /* Set number of pages for normal priority queue. */ 2512 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2513 urtwn_write_4(sc, R92C_RQPN, 2514 /* Set number of pages for public queue. */ 2515 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2516 /* Set number of pages for high priority queue. */ 2517 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2518 /* Set number of pages for low priority queue. */ 2519 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2520 /* Load values. */ 2521 R92C_RQPN_LD); 2522 2523 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2524 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2525 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2526 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2527 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2528 2529 /* Set queue to USB pipe mapping. */ 2530 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2531 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2532 if (nqueues == 1) { 2533 if (hashq) 2534 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2535 else if (hasnq) 2536 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2537 else 2538 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2539 } else if (nqueues == 2) { 2540 /* All 2-endpoints configs have a high priority queue. */ 2541 if (!hashq) 2542 return (EIO); 2543 if (hasnq) 2544 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2545 else 2546 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2547 } else 2548 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2549 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2550 2551 /* Set Tx/Rx transfer page boundary. */ 2552 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2553 2554 /* Set Tx/Rx transfer page size. */ 2555 urtwn_write_1(sc, R92C_PBP, 2556 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2557 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2558 return (0); 2559} 2560 2561static int 2562urtwn_r88e_dma_init(struct urtwn_softc *sc) 2563{ 2564 struct usb_interface *iface; 2565 uint32_t reg; 2566 int nqueues; 2567 int error; 2568 2569 /* Initialize LLT table. */ 2570 error = urtwn_llt_init(sc); 2571 if (error != 0) 2572 return (error); 2573 2574 /* Get Tx queues to USB endpoints mapping. */ 2575 iface = usbd_get_iface(sc->sc_udev, 0); 2576 nqueues = iface->idesc->bNumEndpoints - 1; 2577 if (nqueues == 0) 2578 return (EIO); 2579 2580 /* Set number of pages for normal priority queue. */ 2581 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2582 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2583 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2584 2585 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2586 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2587 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2588 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2589 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2590 2591 /* Set queue to USB pipe mapping. */ 2592 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2593 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2594 if (nqueues == 1) 2595 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2596 else if (nqueues == 2) 2597 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2598 else 2599 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2600 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2601 2602 /* Set Tx/Rx transfer page boundary. */ 2603 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2604 2605 /* Set Tx/Rx transfer page size. */ 2606 urtwn_write_1(sc, R92C_PBP, 2607 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2608 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2609 2610 return (0); 2611} 2612 2613static void 2614urtwn_mac_init(struct urtwn_softc *sc) 2615{ 2616 int i; 2617 2618 /* Write MAC initialization values. */ 2619 if (sc->chip & URTWN_CHIP_88E) { 2620 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2621 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2622 rtl8188eu_mac[i].val); 2623 } 2624 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2625 } else { 2626 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2627 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2628 rtl8192cu_mac[i].val); 2629 } 2630} 2631 2632static void 2633urtwn_bb_init(struct urtwn_softc *sc) 2634{ 2635 const struct urtwn_bb_prog *prog; 2636 uint32_t reg; 2637 uint8_t crystalcap; 2638 int i; 2639 2640 /* Enable BB and RF. */ 2641 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2642 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2643 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2644 R92C_SYS_FUNC_EN_DIO_RF); 2645 2646 if (!(sc->chip & URTWN_CHIP_88E)) 2647 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2648 2649 urtwn_write_1(sc, R92C_RF_CTRL, 2650 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2651 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2652 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2653 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2654 2655 if (!(sc->chip & URTWN_CHIP_88E)) { 2656 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2657 urtwn_write_1(sc, 0x15, 0xe9); 2658 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2659 } 2660 2661 /* Select BB programming based on board type. */ 2662 if (sc->chip & URTWN_CHIP_88E) 2663 prog = &rtl8188eu_bb_prog; 2664 else if (!(sc->chip & URTWN_CHIP_92C)) { 2665 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2666 prog = &rtl8188ce_bb_prog; 2667 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2668 prog = &rtl8188ru_bb_prog; 2669 else 2670 prog = &rtl8188cu_bb_prog; 2671 } else { 2672 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2673 prog = &rtl8192ce_bb_prog; 2674 else 2675 prog = &rtl8192cu_bb_prog; 2676 } 2677 /* Write BB initialization values. */ 2678 for (i = 0; i < prog->count; i++) { 2679 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2680 urtwn_ms_delay(sc); 2681 } 2682 2683 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2684 /* 8192C 1T only configuration. */ 2685 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2686 reg = (reg & ~0x00000003) | 0x2; 2687 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2688 2689 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2690 reg = (reg & ~0x00300033) | 0x00200022; 2691 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2692 2693 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2694 reg = (reg & ~0xff000000) | 0x45 << 24; 2695 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2696 2697 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2698 reg = (reg & ~0x000000ff) | 0x23; 2699 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2700 2701 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2702 reg = (reg & ~0x00000030) | 1 << 4; 2703 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2704 2705 reg = urtwn_bb_read(sc, 0xe74); 2706 reg = (reg & ~0x0c000000) | 2 << 26; 2707 urtwn_bb_write(sc, 0xe74, reg); 2708 reg = urtwn_bb_read(sc, 0xe78); 2709 reg = (reg & ~0x0c000000) | 2 << 26; 2710 urtwn_bb_write(sc, 0xe78, reg); 2711 reg = urtwn_bb_read(sc, 0xe7c); 2712 reg = (reg & ~0x0c000000) | 2 << 26; 2713 urtwn_bb_write(sc, 0xe7c, reg); 2714 reg = urtwn_bb_read(sc, 0xe80); 2715 reg = (reg & ~0x0c000000) | 2 << 26; 2716 urtwn_bb_write(sc, 0xe80, reg); 2717 reg = urtwn_bb_read(sc, 0xe88); 2718 reg = (reg & ~0x0c000000) | 2 << 26; 2719 urtwn_bb_write(sc, 0xe88, reg); 2720 } 2721 2722 /* Write AGC values. */ 2723 for (i = 0; i < prog->agccount; i++) { 2724 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2725 prog->agcvals[i]); 2726 urtwn_ms_delay(sc); 2727 } 2728 2729 if (sc->chip & URTWN_CHIP_88E) { 2730 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2731 urtwn_ms_delay(sc); 2732 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2733 urtwn_ms_delay(sc); 2734 2735 crystalcap = sc->r88e_rom[0xb9]; 2736 if (crystalcap == 0xff) 2737 crystalcap = 0x20; 2738 crystalcap &= 0x3f; 2739 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2740 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2741 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2742 crystalcap | crystalcap << 6)); 2743 } else { 2744 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2745 R92C_HSSI_PARAM2_CCK_HIPWR) 2746 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2747 } 2748} 2749 2750void 2751urtwn_rf_init(struct urtwn_softc *sc) 2752{ 2753 const struct urtwn_rf_prog *prog; 2754 uint32_t reg, type; 2755 int i, j, idx, off; 2756 2757 /* Select RF programming based on board type. */ 2758 if (sc->chip & URTWN_CHIP_88E) 2759 prog = rtl8188eu_rf_prog; 2760 else if (!(sc->chip & URTWN_CHIP_92C)) { 2761 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2762 prog = rtl8188ce_rf_prog; 2763 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2764 prog = rtl8188ru_rf_prog; 2765 else 2766 prog = rtl8188cu_rf_prog; 2767 } else 2768 prog = rtl8192ce_rf_prog; 2769 2770 for (i = 0; i < sc->nrxchains; i++) { 2771 /* Save RF_ENV control type. */ 2772 idx = i / 2; 2773 off = (i % 2) * 16; 2774 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2775 type = (reg >> off) & 0x10; 2776 2777 /* Set RF_ENV enable. */ 2778 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2779 reg |= 0x100000; 2780 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2781 urtwn_ms_delay(sc); 2782 /* Set RF_ENV output high. */ 2783 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2784 reg |= 0x10; 2785 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2786 urtwn_ms_delay(sc); 2787 /* Set address and data lengths of RF registers. */ 2788 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2789 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2790 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2791 urtwn_ms_delay(sc); 2792 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2793 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2794 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2795 urtwn_ms_delay(sc); 2796 2797 /* Write RF initialization values for this chain. */ 2798 for (j = 0; j < prog[i].count; j++) { 2799 if (prog[i].regs[j] >= 0xf9 && 2800 prog[i].regs[j] <= 0xfe) { 2801 /* 2802 * These are fake RF registers offsets that 2803 * indicate a delay is required. 2804 */ 2805 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2806 continue; 2807 } 2808 urtwn_rf_write(sc, i, prog[i].regs[j], 2809 prog[i].vals[j]); 2810 urtwn_ms_delay(sc); 2811 } 2812 2813 /* Restore RF_ENV control type. */ 2814 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2815 reg &= ~(0x10 << off) | (type << off); 2816 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2817 2818 /* Cache RF register CHNLBW. */ 2819 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2820 } 2821 2822 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2823 URTWN_CHIP_UMC_A_CUT) { 2824 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2825 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2826 } 2827} 2828 2829static void 2830urtwn_cam_init(struct urtwn_softc *sc) 2831{ 2832 /* Invalidate all CAM entries. */ 2833 urtwn_write_4(sc, R92C_CAMCMD, 2834 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2835} 2836 2837static void 2838urtwn_pa_bias_init(struct urtwn_softc *sc) 2839{ 2840 uint8_t reg; 2841 int i; 2842 2843 for (i = 0; i < sc->nrxchains; i++) { 2844 if (sc->pa_setting & (1 << i)) 2845 continue; 2846 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2847 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2848 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2849 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2850 } 2851 if (!(sc->pa_setting & 0x10)) { 2852 reg = urtwn_read_1(sc, 0x16); 2853 reg = (reg & ~0xf0) | 0x90; 2854 urtwn_write_1(sc, 0x16, reg); 2855 } 2856} 2857 2858static void 2859urtwn_rxfilter_init(struct urtwn_softc *sc) 2860{ 2861 /* Initialize Rx filter. */ 2862 /* TODO: use better filter for monitor mode. */ 2863 urtwn_write_4(sc, R92C_RCR, 2864 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2865 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2866 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2867 /* Accept all multicast frames. */ 2868 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2869 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2870 /* Accept all management frames. */ 2871 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2872 /* Reject all control frames. */ 2873 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2874 /* Accept all data frames. */ 2875 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2876} 2877 2878static void 2879urtwn_edca_init(struct urtwn_softc *sc) 2880{ 2881 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2882 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2883 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2884 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2885 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2886 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2887 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2888 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2889} 2890 2891void 2892urtwn_write_txpower(struct urtwn_softc *sc, int chain, 2893 uint16_t power[URTWN_RIDX_COUNT]) 2894{ 2895 uint32_t reg; 2896 2897 /* Write per-CCK rate Tx power. */ 2898 if (chain == 0) { 2899 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2900 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2901 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2902 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2903 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2904 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2905 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2906 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2907 } else { 2908 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2909 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2910 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2911 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2912 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2913 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2914 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2915 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2916 } 2917 /* Write per-OFDM rate Tx power. */ 2918 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2919 SM(R92C_TXAGC_RATE06, power[ 4]) | 2920 SM(R92C_TXAGC_RATE09, power[ 5]) | 2921 SM(R92C_TXAGC_RATE12, power[ 6]) | 2922 SM(R92C_TXAGC_RATE18, power[ 7])); 2923 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2924 SM(R92C_TXAGC_RATE24, power[ 8]) | 2925 SM(R92C_TXAGC_RATE36, power[ 9]) | 2926 SM(R92C_TXAGC_RATE48, power[10]) | 2927 SM(R92C_TXAGC_RATE54, power[11])); 2928 /* Write per-MCS Tx power. */ 2929 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2930 SM(R92C_TXAGC_MCS00, power[12]) | 2931 SM(R92C_TXAGC_MCS01, power[13]) | 2932 SM(R92C_TXAGC_MCS02, power[14]) | 2933 SM(R92C_TXAGC_MCS03, power[15])); 2934 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2935 SM(R92C_TXAGC_MCS04, power[16]) | 2936 SM(R92C_TXAGC_MCS05, power[17]) | 2937 SM(R92C_TXAGC_MCS06, power[18]) | 2938 SM(R92C_TXAGC_MCS07, power[19])); 2939 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2940 SM(R92C_TXAGC_MCS08, power[20]) | 2941 SM(R92C_TXAGC_MCS09, power[21]) | 2942 SM(R92C_TXAGC_MCS10, power[22]) | 2943 SM(R92C_TXAGC_MCS11, power[23])); 2944 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2945 SM(R92C_TXAGC_MCS12, power[24]) | 2946 SM(R92C_TXAGC_MCS13, power[25]) | 2947 SM(R92C_TXAGC_MCS14, power[26]) | 2948 SM(R92C_TXAGC_MCS15, power[27])); 2949} 2950 2951void 2952urtwn_get_txpower(struct urtwn_softc *sc, int chain, 2953 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2954 uint16_t power[URTWN_RIDX_COUNT]) 2955{ 2956 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2957 struct r92c_rom *rom = &sc->rom; 2958 uint16_t cckpow, ofdmpow, htpow, diff, max; 2959 const struct urtwn_txpwr *base; 2960 int ridx, chan, group; 2961 2962 /* Determine channel group. */ 2963 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2964 if (chan <= 3) 2965 group = 0; 2966 else if (chan <= 9) 2967 group = 1; 2968 else 2969 group = 2; 2970 2971 /* Get original Tx power based on board type and RF chain. */ 2972 if (!(sc->chip & URTWN_CHIP_92C)) { 2973 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2974 base = &rtl8188ru_txagc[chain]; 2975 else 2976 base = &rtl8192cu_txagc[chain]; 2977 } else 2978 base = &rtl8192cu_txagc[chain]; 2979 2980 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2981 if (sc->regulatory == 0) { 2982 for (ridx = 0; ridx <= 3; ridx++) 2983 power[ridx] = base->pwr[0][ridx]; 2984 } 2985 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 2986 if (sc->regulatory == 3) { 2987 power[ridx] = base->pwr[0][ridx]; 2988 /* Apply vendor limits. */ 2989 if (extc != NULL) 2990 max = rom->ht40_max_pwr[group]; 2991 else 2992 max = rom->ht20_max_pwr[group]; 2993 max = (max >> (chain * 4)) & 0xf; 2994 if (power[ridx] > max) 2995 power[ridx] = max; 2996 } else if (sc->regulatory == 1) { 2997 if (extc == NULL) 2998 power[ridx] = base->pwr[group][ridx]; 2999 } else if (sc->regulatory != 2) 3000 power[ridx] = base->pwr[0][ridx]; 3001 } 3002 3003 /* Compute per-CCK rate Tx power. */ 3004 cckpow = rom->cck_tx_pwr[chain][group]; 3005 for (ridx = 0; ridx <= 3; ridx++) { 3006 power[ridx] += cckpow; 3007 if (power[ridx] > R92C_MAX_TX_PWR) 3008 power[ridx] = R92C_MAX_TX_PWR; 3009 } 3010 3011 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3012 if (sc->ntxchains > 1) { 3013 /* Apply reduction for 2 spatial streams. */ 3014 diff = rom->ht40_2s_tx_pwr_diff[group]; 3015 diff = (diff >> (chain * 4)) & 0xf; 3016 htpow = (htpow > diff) ? htpow - diff : 0; 3017 } 3018 3019 /* Compute per-OFDM rate Tx power. */ 3020 diff = rom->ofdm_tx_pwr_diff[group]; 3021 diff = (diff >> (chain * 4)) & 0xf; 3022 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3023 for (ridx = 4; ridx <= 11; ridx++) { 3024 power[ridx] += ofdmpow; 3025 if (power[ridx] > R92C_MAX_TX_PWR) 3026 power[ridx] = R92C_MAX_TX_PWR; 3027 } 3028 3029 /* Compute per-MCS Tx power. */ 3030 if (extc == NULL) { 3031 diff = rom->ht20_tx_pwr_diff[group]; 3032 diff = (diff >> (chain * 4)) & 0xf; 3033 htpow += diff; /* HT40->HT20 correction. */ 3034 } 3035 for (ridx = 12; ridx <= 27; ridx++) { 3036 power[ridx] += htpow; 3037 if (power[ridx] > R92C_MAX_TX_PWR) 3038 power[ridx] = R92C_MAX_TX_PWR; 3039 } 3040#ifdef URTWN_DEBUG 3041 if (urtwn_debug >= 4) { 3042 /* Dump per-rate Tx power values. */ 3043 printf("Tx power for chain %d:\n", chain); 3044 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 3045 printf("Rate %d = %u\n", ridx, power[ridx]); 3046 } 3047#endif 3048} 3049 3050void 3051urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3052 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3053 uint16_t power[URTWN_RIDX_COUNT]) 3054{ 3055 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3056 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3057 const struct urtwn_r88e_txpwr *base; 3058 int ridx, chan, group; 3059 3060 /* Determine channel group. */ 3061 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3062 if (chan <= 2) 3063 group = 0; 3064 else if (chan <= 5) 3065 group = 1; 3066 else if (chan <= 8) 3067 group = 2; 3068 else if (chan <= 11) 3069 group = 3; 3070 else if (chan <= 13) 3071 group = 4; 3072 else 3073 group = 5; 3074 3075 /* Get original Tx power based on board type and RF chain. */ 3076 base = &rtl8188eu_txagc[chain]; 3077 3078 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3079 if (sc->regulatory == 0) { 3080 for (ridx = 0; ridx <= 3; ridx++) 3081 power[ridx] = base->pwr[0][ridx]; 3082 } 3083 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3084 if (sc->regulatory == 3) 3085 power[ridx] = base->pwr[0][ridx]; 3086 else if (sc->regulatory == 1) { 3087 if (extc == NULL) 3088 power[ridx] = base->pwr[group][ridx]; 3089 } else if (sc->regulatory != 2) 3090 power[ridx] = base->pwr[0][ridx]; 3091 } 3092 3093 /* Compute per-CCK rate Tx power. */ 3094 cckpow = sc->cck_tx_pwr[group]; 3095 for (ridx = 0; ridx <= 3; ridx++) { 3096 power[ridx] += cckpow; 3097 if (power[ridx] > R92C_MAX_TX_PWR) 3098 power[ridx] = R92C_MAX_TX_PWR; 3099 } 3100 3101 htpow = sc->ht40_tx_pwr[group]; 3102 3103 /* Compute per-OFDM rate Tx power. */ 3104 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3105 for (ridx = 4; ridx <= 11; ridx++) { 3106 power[ridx] += ofdmpow; 3107 if (power[ridx] > R92C_MAX_TX_PWR) 3108 power[ridx] = R92C_MAX_TX_PWR; 3109 } 3110 3111 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3112 for (ridx = 12; ridx <= 27; ridx++) { 3113 power[ridx] += bw20pow; 3114 if (power[ridx] > R92C_MAX_TX_PWR) 3115 power[ridx] = R92C_MAX_TX_PWR; 3116 } 3117} 3118 3119void 3120urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3121 struct ieee80211_channel *extc) 3122{ 3123 uint16_t power[URTWN_RIDX_COUNT]; 3124 int i; 3125 3126 for (i = 0; i < sc->ntxchains; i++) { 3127 /* Compute per-rate Tx power values. */ 3128 if (sc->chip & URTWN_CHIP_88E) 3129 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3130 else 3131 urtwn_get_txpower(sc, i, c, extc, power); 3132 /* Write per-rate Tx power values to hardware. */ 3133 urtwn_write_txpower(sc, i, power); 3134 } 3135} 3136 3137static void 3138urtwn_scan_start(struct ieee80211com *ic) 3139{ 3140 /* XXX do nothing? */ 3141} 3142 3143static void 3144urtwn_scan_end(struct ieee80211com *ic) 3145{ 3146 /* XXX do nothing? */ 3147} 3148 3149static void 3150urtwn_set_channel(struct ieee80211com *ic) 3151{ 3152 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 3153 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3154 3155 URTWN_LOCK(sc); 3156 if (vap->iv_state == IEEE80211_S_SCAN) { 3157 /* Make link LED blink during scan. */ 3158 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3159 } 3160 urtwn_set_chan(sc, ic->ic_curchan, NULL); 3161 URTWN_UNLOCK(sc); 3162} 3163 3164static void 3165urtwn_update_mcast(struct ifnet *ifp) 3166{ 3167 /* XXX do nothing? */ 3168} 3169 3170static void 3171urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3172 struct ieee80211_channel *extc) 3173{ 3174 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3175 uint32_t reg; 3176 u_int chan; 3177 int i; 3178 3179 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3180 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3181 device_printf(sc->sc_dev, 3182 "%s: invalid channel %x\n", __func__, chan); 3183 return; 3184 } 3185 3186 /* Set Tx power for this new channel. */ 3187 urtwn_set_txpower(sc, c, extc); 3188 3189 for (i = 0; i < sc->nrxchains; i++) { 3190 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3191 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3192 } 3193#ifndef IEEE80211_NO_HT 3194 if (extc != NULL) { 3195 /* Is secondary channel below or above primary? */ 3196 int prichlo = c->ic_freq < extc->ic_freq; 3197 3198 urtwn_write_1(sc, R92C_BWOPMODE, 3199 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3200 3201 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3202 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3203 urtwn_write_1(sc, R92C_RRSR + 2, reg); 3204 3205 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3206 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3207 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3208 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3209 3210 /* Set CCK side band. */ 3211 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3212 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3213 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3214 3215 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3216 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3217 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3218 3219 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3220 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3221 ~R92C_FPGA0_ANAPARAM2_CBW20); 3222 3223 reg = urtwn_bb_read(sc, 0x818); 3224 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3225 urtwn_bb_write(sc, 0x818, reg); 3226 3227 /* Select 40MHz bandwidth. */ 3228 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3229 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3230 } else 3231#endif 3232 { 3233 urtwn_write_1(sc, R92C_BWOPMODE, 3234 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3235 3236 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3237 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3238 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3239 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3240 3241 if (!(sc->chip & URTWN_CHIP_88E)) { 3242 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3243 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3244 R92C_FPGA0_ANAPARAM2_CBW20); 3245 } 3246 3247 /* Select 20MHz bandwidth. */ 3248 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3249 (sc->rf_chnlbw[0] & ~0xfff) | chan | 3250 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3251 R92C_RF_CHNLBW_BW20)); 3252 } 3253} 3254 3255static void 3256urtwn_iq_calib(struct urtwn_softc *sc) 3257{ 3258 /* TODO */ 3259} 3260 3261static void 3262urtwn_lc_calib(struct urtwn_softc *sc) 3263{ 3264 uint32_t rf_ac[2]; 3265 uint8_t txmode; 3266 int i; 3267 3268 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3269 if ((txmode & 0x70) != 0) { 3270 /* Disable all continuous Tx. */ 3271 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3272 3273 /* Set RF mode to standby mode. */ 3274 for (i = 0; i < sc->nrxchains; i++) { 3275 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3276 urtwn_rf_write(sc, i, R92C_RF_AC, 3277 RW(rf_ac[i], R92C_RF_AC_MODE, 3278 R92C_RF_AC_MODE_STANDBY)); 3279 } 3280 } else { 3281 /* Block all Tx queues. */ 3282 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3283 } 3284 /* Start calibration. */ 3285 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3286 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3287 3288 /* Give calibration the time to complete. */ 3289 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3290 3291 /* Restore configuration. */ 3292 if ((txmode & 0x70) != 0) { 3293 /* Restore Tx mode. */ 3294 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3295 /* Restore RF mode. */ 3296 for (i = 0; i < sc->nrxchains; i++) 3297 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3298 } else { 3299 /* Unblock all Tx queues. */ 3300 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3301 } 3302} 3303 3304static void 3305urtwn_init_locked(void *arg) 3306{ 3307 struct urtwn_softc *sc = arg; 3308 struct ifnet *ifp = sc->sc_ifp; 3309 uint32_t reg; 3310 int error; 3311 3312 URTWN_ASSERT_LOCKED(sc); 3313 3314 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3315 urtwn_stop_locked(ifp); 3316 3317 /* Init firmware commands ring. */ 3318 sc->fwcur = 0; 3319 3320 /* Allocate Tx/Rx buffers. */ 3321 error = urtwn_alloc_rx_list(sc); 3322 if (error != 0) 3323 goto fail; 3324 3325 error = urtwn_alloc_tx_list(sc); 3326 if (error != 0) 3327 goto fail; 3328 3329 /* Power on adapter. */ 3330 error = urtwn_power_on(sc); 3331 if (error != 0) 3332 goto fail; 3333 3334 /* Initialize DMA. */ 3335 error = urtwn_dma_init(sc); 3336 if (error != 0) 3337 goto fail; 3338 3339 /* Set info size in Rx descriptors (in 64-bit words). */ 3340 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3341 3342 /* Init interrupts. */ 3343 if (sc->chip & URTWN_CHIP_88E) { 3344 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3345 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3346 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3347 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3348 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3349 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3350 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3351 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3352 } else { 3353 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3354 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3355 } 3356 3357 /* Set MAC address. */ 3358 urtwn_write_region_1(sc, R92C_MACID, IF_LLADDR(ifp), 3359 IEEE80211_ADDR_LEN); 3360 3361 /* Set initial network type. */ 3362 reg = urtwn_read_4(sc, R92C_CR); 3363 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3364 urtwn_write_4(sc, R92C_CR, reg); 3365 3366 urtwn_rxfilter_init(sc); 3367 3368 reg = urtwn_read_4(sc, R92C_RRSR); 3369 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3370 urtwn_write_4(sc, R92C_RRSR, reg); 3371 3372 /* Set short/long retry limits. */ 3373 urtwn_write_2(sc, R92C_RL, 3374 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3375 3376 /* Initialize EDCA parameters. */ 3377 urtwn_edca_init(sc); 3378 3379 /* Setup rate fallback. */ 3380 if (!(sc->chip & URTWN_CHIP_88E)) { 3381 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3382 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3383 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3384 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3385 } 3386 3387 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3388 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3389 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3390 /* Set ACK timeout. */ 3391 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3392 3393 /* Setup USB aggregation. */ 3394 reg = urtwn_read_4(sc, R92C_TDECTRL); 3395 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3396 urtwn_write_4(sc, R92C_TDECTRL, reg); 3397 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3398 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3399 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3400 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3401 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3402 R92C_USB_SPECIAL_OPTION_AGG_EN); 3403 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3404 if (sc->chip & URTWN_CHIP_88E) 3405 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3406 else 3407 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3408 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3409 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3410 3411 /* Initialize beacon parameters. */ 3412 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3413 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3414 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3415 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3416 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3417 3418 if (!(sc->chip & URTWN_CHIP_88E)) { 3419 /* Setup AMPDU aggregation. */ 3420 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3421 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3422 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3423 3424 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3425 } 3426 3427 /* Load 8051 microcode. */ 3428 error = urtwn_load_firmware(sc); 3429 if (error != 0) 3430 goto fail; 3431 3432 /* Initialize MAC/BB/RF blocks. */ 3433 urtwn_mac_init(sc); 3434 urtwn_bb_init(sc); 3435 urtwn_rf_init(sc); 3436 3437 if (sc->chip & URTWN_CHIP_88E) { 3438 urtwn_write_2(sc, R92C_CR, 3439 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3440 R92C_CR_MACRXEN); 3441 } 3442 3443 /* Turn CCK and OFDM blocks on. */ 3444 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3445 reg |= R92C_RFMOD_CCK_EN; 3446 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3447 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3448 reg |= R92C_RFMOD_OFDM_EN; 3449 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3450 3451 /* Clear per-station keys table. */ 3452 urtwn_cam_init(sc); 3453 3454 /* Enable hardware sequence numbering. */ 3455 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3456 3457 /* Perform LO and IQ calibrations. */ 3458 urtwn_iq_calib(sc); 3459 /* Perform LC calibration. */ 3460 urtwn_lc_calib(sc); 3461 3462 /* Fix USB interference issue. */ 3463 if (!(sc->chip & URTWN_CHIP_88E)) { 3464 urtwn_write_1(sc, 0xfe40, 0xe0); 3465 urtwn_write_1(sc, 0xfe41, 0x8d); 3466 urtwn_write_1(sc, 0xfe42, 0x80); 3467 3468 urtwn_pa_bias_init(sc); 3469 } 3470 3471 /* Initialize GPIO setting. */ 3472 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3473 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3474 3475 /* Fix for lower temperature. */ 3476 if (!(sc->chip & URTWN_CHIP_88E)) 3477 urtwn_write_1(sc, 0x15, 0xe9); 3478 3479 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3480 3481 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3482 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3483 3484 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3485fail: 3486 return; 3487} 3488 3489static void 3490urtwn_init(void *arg) 3491{ 3492 struct urtwn_softc *sc = arg; 3493 3494 URTWN_LOCK(sc); 3495 urtwn_init_locked(arg); 3496 URTWN_UNLOCK(sc); 3497} 3498 3499static void 3500urtwn_stop_locked(struct ifnet *ifp) 3501{ 3502 struct urtwn_softc *sc = ifp->if_softc; 3503 3504 URTWN_ASSERT_LOCKED(sc); 3505 3506 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3507 3508 callout_stop(&sc->sc_watchdog_ch); 3509 urtwn_abort_xfers(sc); 3510} 3511 3512static void 3513urtwn_stop(struct ifnet *ifp) 3514{ 3515 struct urtwn_softc *sc = ifp->if_softc; 3516 3517 URTWN_LOCK(sc); 3518 urtwn_stop_locked(ifp); 3519 URTWN_UNLOCK(sc); 3520} 3521 3522static void 3523urtwn_abort_xfers(struct urtwn_softc *sc) 3524{ 3525 int i; 3526 3527 URTWN_ASSERT_LOCKED(sc); 3528 3529 /* abort any pending transfers */ 3530 for (i = 0; i < URTWN_N_TRANSFER; i++) 3531 usbd_transfer_stop(sc->sc_xfer[i]); 3532} 3533 3534static int 3535urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3536 const struct ieee80211_bpf_params *params) 3537{ 3538 struct ieee80211com *ic = ni->ni_ic; 3539 struct ifnet *ifp = ic->ic_ifp; 3540 struct urtwn_softc *sc = ifp->if_softc; 3541 struct urtwn_data *bf; 3542 3543 /* prevent management frames from being sent if we're not ready */ 3544 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3545 m_freem(m); 3546 ieee80211_free_node(ni); 3547 return (ENETDOWN); 3548 } 3549 URTWN_LOCK(sc); 3550 bf = urtwn_getbuf(sc); 3551 if (bf == NULL) { 3552 ieee80211_free_node(ni); 3553 m_freem(m); 3554 URTWN_UNLOCK(sc); 3555 return (ENOBUFS); 3556 } 3557 3558 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 3559 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3560 ieee80211_free_node(ni); 3561 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3562 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3563 URTWN_UNLOCK(sc); 3564 return (EIO); 3565 } 3566 URTWN_UNLOCK(sc); 3567 3568 sc->sc_txtimer = 5; 3569 return (0); 3570} 3571 3572static void 3573urtwn_ms_delay(struct urtwn_softc *sc) 3574{ 3575 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3576} 3577 3578static device_method_t urtwn_methods[] = { 3579 /* Device interface */ 3580 DEVMETHOD(device_probe, urtwn_match), 3581 DEVMETHOD(device_attach, urtwn_attach), 3582 DEVMETHOD(device_detach, urtwn_detach), 3583 3584 DEVMETHOD_END 3585}; 3586 3587static driver_t urtwn_driver = { 3588 "urtwn", 3589 urtwn_methods, 3590 sizeof(struct urtwn_softc) 3591}; 3592 3593static devclass_t urtwn_devclass; 3594 3595DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3596MODULE_DEPEND(urtwn, usb, 1, 1, 1); 3597MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3598MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3599MODULE_VERSION(urtwn, 1); 3600