if_urtwn.c revision 266472
1251538Srpaulo/*	$OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $	*/
2251538Srpaulo
3251538Srpaulo/*-
4251538Srpaulo * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
5264912Skevlo * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
6251538Srpaulo *
7251538Srpaulo * Permission to use, copy, modify, and distribute this software for any
8251538Srpaulo * purpose with or without fee is hereby granted, provided that the above
9251538Srpaulo * copyright notice and this permission notice appear in all copies.
10251538Srpaulo *
11251538Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12251538Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13251538Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14251538Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15251538Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16251538Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17251538Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18251538Srpaulo */
19251538Srpaulo
20251538Srpaulo#include <sys/cdefs.h>
21251538Srpaulo__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 266472 2014-05-20 15:53:17Z hselasky $");
22251538Srpaulo
23251538Srpaulo/*
24264912Skevlo * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU.
25251538Srpaulo */
26251538Srpaulo
27251538Srpaulo#include <sys/param.h>
28251538Srpaulo#include <sys/sockio.h>
29251538Srpaulo#include <sys/sysctl.h>
30251538Srpaulo#include <sys/lock.h>
31251538Srpaulo#include <sys/mutex.h>
32251538Srpaulo#include <sys/mbuf.h>
33251538Srpaulo#include <sys/kernel.h>
34251538Srpaulo#include <sys/socket.h>
35251538Srpaulo#include <sys/systm.h>
36251538Srpaulo#include <sys/malloc.h>
37251538Srpaulo#include <sys/module.h>
38251538Srpaulo#include <sys/bus.h>
39251538Srpaulo#include <sys/endian.h>
40251538Srpaulo#include <sys/linker.h>
41251538Srpaulo#include <sys/firmware.h>
42251538Srpaulo#include <sys/kdb.h>
43251538Srpaulo
44251538Srpaulo#include <machine/bus.h>
45251538Srpaulo#include <machine/resource.h>
46251538Srpaulo#include <sys/rman.h>
47251538Srpaulo
48251538Srpaulo#include <net/bpf.h>
49251538Srpaulo#include <net/if.h>
50257176Sglebius#include <net/if_var.h>
51251538Srpaulo#include <net/if_arp.h>
52251538Srpaulo#include <net/ethernet.h>
53251538Srpaulo#include <net/if_dl.h>
54251538Srpaulo#include <net/if_media.h>
55251538Srpaulo#include <net/if_types.h>
56251538Srpaulo
57251538Srpaulo#include <netinet/in.h>
58251538Srpaulo#include <netinet/in_systm.h>
59251538Srpaulo#include <netinet/in_var.h>
60251538Srpaulo#include <netinet/if_ether.h>
61251538Srpaulo#include <netinet/ip.h>
62251538Srpaulo
63251538Srpaulo#include <net80211/ieee80211_var.h>
64251538Srpaulo#include <net80211/ieee80211_regdomain.h>
65251538Srpaulo#include <net80211/ieee80211_radiotap.h>
66251538Srpaulo#include <net80211/ieee80211_ratectl.h>
67251538Srpaulo
68251538Srpaulo#include <dev/usb/usb.h>
69251538Srpaulo#include <dev/usb/usbdi.h>
70251538Srpaulo#include "usbdevs.h"
71251538Srpaulo
72251538Srpaulo#define USB_DEBUG_VAR urtwn_debug
73251538Srpaulo#include <dev/usb/usb_debug.h>
74251538Srpaulo
75251538Srpaulo#include <dev/usb/wlan/if_urtwnreg.h>
76251538Srpaulo
77251538Srpaulo#ifdef USB_DEBUG
78251538Srpaulostatic int urtwn_debug = 0;
79251538Srpaulo
80251538SrpauloSYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn");
81251538SrpauloSYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RW, &urtwn_debug, 0,
82251538Srpaulo    "Debug level");
83251538Srpaulo#endif
84251538Srpaulo
85252406Srpaulo#define	URTWN_RSSI(r)  (r) - 110
86251538Srpaulo#define	IEEE80211_HAS_ADDR4(wh)	\
87251538Srpaulo	(((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS)
88251538Srpaulo
89251538Srpaulo/* various supported device vendors/products */
90251596Srpaulostatic const STRUCT_USB_HOST_ID urtwn_devs[] = {
91251538Srpaulo#define URTWN_DEV(v,p)  { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
92264912Skevlo#define	URTWN_RTL8188E_DEV(v,p)	\
93264912Skevlo	{ USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) }
94264912Skevlo#define URTWN_RTL8188E  1
95251538Srpaulo	URTWN_DEV(ABOCOM,	RTL8188CU_1),
96251538Srpaulo	URTWN_DEV(ABOCOM,	RTL8188CU_2),
97251538Srpaulo	URTWN_DEV(ABOCOM,	RTL8192CU),
98251538Srpaulo	URTWN_DEV(ASUS,		RTL8192CU),
99251538Srpaulo	URTWN_DEV(AZUREWAVE,	RTL8188CE_1),
100251538Srpaulo	URTWN_DEV(AZUREWAVE,	RTL8188CE_2),
101251538Srpaulo	URTWN_DEV(AZUREWAVE,	RTL8188CU),
102251538Srpaulo	URTWN_DEV(BELKIN,	F7D2102),
103251538Srpaulo	URTWN_DEV(BELKIN,	RTL8188CU),
104251538Srpaulo	URTWN_DEV(BELKIN,	RTL8192CU),
105251538Srpaulo	URTWN_DEV(CHICONY,	RTL8188CUS_1),
106251538Srpaulo	URTWN_DEV(CHICONY,	RTL8188CUS_2),
107251538Srpaulo	URTWN_DEV(CHICONY,	RTL8188CUS_3),
108251538Srpaulo	URTWN_DEV(CHICONY,	RTL8188CUS_4),
109251538Srpaulo	URTWN_DEV(CHICONY,	RTL8188CUS_5),
110251538Srpaulo	URTWN_DEV(COREGA,	RTL8192CU),
111251538Srpaulo	URTWN_DEV(DLINK,	RTL8188CU),
112251538Srpaulo	URTWN_DEV(DLINK,	RTL8192CU_1),
113251538Srpaulo	URTWN_DEV(DLINK,	RTL8192CU_2),
114251538Srpaulo	URTWN_DEV(DLINK,	RTL8192CU_3),
115252196Skevlo	URTWN_DEV(DLINK,	DWA131B),
116251538Srpaulo	URTWN_DEV(EDIMAX,	EW7811UN),
117251538Srpaulo	URTWN_DEV(EDIMAX,	RTL8192CU),
118251538Srpaulo	URTWN_DEV(FEIXUN,	RTL8188CU),
119251538Srpaulo	URTWN_DEV(FEIXUN,	RTL8192CU),
120251538Srpaulo	URTWN_DEV(GUILLEMOT,	HWNUP150),
121251538Srpaulo	URTWN_DEV(HAWKING,	RTL8192CU),
122251538Srpaulo	URTWN_DEV(HP3,		RTL8188CU),
123251538Srpaulo	URTWN_DEV(NETGEAR,	WNA1000M),
124251538Srpaulo	URTWN_DEV(NETGEAR,	RTL8192CU),
125251538Srpaulo	URTWN_DEV(NETGEAR4,	RTL8188CU),
126251538Srpaulo	URTWN_DEV(NOVATECH,	RTL8188CU),
127251538Srpaulo	URTWN_DEV(PLANEX2,	RTL8188CU_1),
128251538Srpaulo	URTWN_DEV(PLANEX2,	RTL8188CU_2),
129251538Srpaulo	URTWN_DEV(PLANEX2,	RTL8188CU_3),
130251538Srpaulo	URTWN_DEV(PLANEX2,	RTL8188CU_4),
131251538Srpaulo	URTWN_DEV(PLANEX2,	RTL8188CUS),
132251538Srpaulo	URTWN_DEV(PLANEX2,	RTL8192CU),
133251538Srpaulo	URTWN_DEV(REALTEK,	RTL8188CE_0),
134251538Srpaulo	URTWN_DEV(REALTEK,	RTL8188CE_1),
135251538Srpaulo	URTWN_DEV(REALTEK,	RTL8188CTV),
136251538Srpaulo	URTWN_DEV(REALTEK,	RTL8188CU_0),
137251538Srpaulo	URTWN_DEV(REALTEK,	RTL8188CU_1),
138251538Srpaulo	URTWN_DEV(REALTEK,	RTL8188CU_2),
139251538Srpaulo	URTWN_DEV(REALTEK,	RTL8188CU_COMBO),
140251538Srpaulo	URTWN_DEV(REALTEK,	RTL8188CUS),
141251538Srpaulo	URTWN_DEV(REALTEK,	RTL8188RU_1),
142251538Srpaulo	URTWN_DEV(REALTEK,	RTL8188RU_2),
143251538Srpaulo	URTWN_DEV(REALTEK,	RTL8191CU),
144251538Srpaulo	URTWN_DEV(REALTEK,	RTL8192CE),
145251538Srpaulo	URTWN_DEV(REALTEK,	RTL8192CU),
146257543Salfred	URTWN_DEV(REALTEK, 	RTL8188CU_0),
147251538Srpaulo	URTWN_DEV(SITECOMEU,	RTL8188CU_1),
148251538Srpaulo	URTWN_DEV(SITECOMEU,	RTL8188CU_2),
149251538Srpaulo	URTWN_DEV(SITECOMEU,	RTL8192CU),
150251538Srpaulo	URTWN_DEV(TRENDNET,	RTL8188CU),
151251538Srpaulo	URTWN_DEV(TRENDNET,	RTL8192CU),
152251538Srpaulo	URTWN_DEV(ZYXEL,	RTL8192CU),
153264912Skevlo	/* URTWN_RTL8188E */
154264912Skevlo	URTWN_RTL8188E_DEV(REALTEK,	RTL8188ETV),
155264912Skevlo	URTWN_RTL8188E_DEV(REALTEK,	RTL8188EU),
156264912Skevlo#undef URTWN_RTL8188E_DEV
157251538Srpaulo#undef URTWN_DEV
158251538Srpaulo};
159251538Srpaulo
160251538Srpaulostatic device_probe_t	urtwn_match;
161251538Srpaulostatic device_attach_t	urtwn_attach;
162251538Srpaulostatic device_detach_t	urtwn_detach;
163251538Srpaulo
164251538Srpaulostatic usb_callback_t   urtwn_bulk_tx_callback;
165251538Srpaulostatic usb_callback_t	urtwn_bulk_rx_callback;
166251538Srpaulo
167251538Srpaulostatic usb_error_t	urtwn_do_request(struct urtwn_softc *sc,
168251538Srpaulo			    struct usb_device_request *req, void *data);
169251538Srpaulostatic struct ieee80211vap *urtwn_vap_create(struct ieee80211com *,
170251538Srpaulo		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
171251538Srpaulo                    const uint8_t [IEEE80211_ADDR_LEN],
172251538Srpaulo                    const uint8_t [IEEE80211_ADDR_LEN]);
173251538Srpaulostatic void		urtwn_vap_delete(struct ieee80211vap *);
174251538Srpaulostatic struct mbuf *	urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int,
175251538Srpaulo			    int *);
176251538Srpaulostatic struct mbuf *	urtwn_rxeof(struct usb_xfer *, struct urtwn_data *,
177251538Srpaulo			    int *, int8_t *);
178251538Srpaulostatic void		urtwn_txeof(struct usb_xfer *, struct urtwn_data *);
179251538Srpaulostatic int		urtwn_alloc_list(struct urtwn_softc *,
180251538Srpaulo			    struct urtwn_data[], int, int);
181251538Srpaulostatic int		urtwn_alloc_rx_list(struct urtwn_softc *);
182251538Srpaulostatic int		urtwn_alloc_tx_list(struct urtwn_softc *);
183251538Srpaulostatic void		urtwn_free_tx_list(struct urtwn_softc *);
184251538Srpaulostatic void		urtwn_free_rx_list(struct urtwn_softc *);
185251538Srpaulostatic void		urtwn_free_list(struct urtwn_softc *,
186251538Srpaulo			    struct urtwn_data data[], int);
187251538Srpaulostatic struct urtwn_data *	_urtwn_getbuf(struct urtwn_softc *);
188251538Srpaulostatic struct urtwn_data *	urtwn_getbuf(struct urtwn_softc *);
189251538Srpaulostatic int		urtwn_write_region_1(struct urtwn_softc *, uint16_t,
190251538Srpaulo			    uint8_t *, int);
191251538Srpaulostatic void		urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t);
192251538Srpaulostatic void		urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t);
193251538Srpaulostatic void		urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t);
194251538Srpaulostatic int		urtwn_read_region_1(struct urtwn_softc *, uint16_t,
195251538Srpaulo			    uint8_t *, int);
196251538Srpaulostatic uint8_t		urtwn_read_1(struct urtwn_softc *, uint16_t);
197251538Srpaulostatic uint16_t		urtwn_read_2(struct urtwn_softc *, uint16_t);
198251538Srpaulostatic uint32_t		urtwn_read_4(struct urtwn_softc *, uint16_t);
199251538Srpaulostatic int		urtwn_fw_cmd(struct urtwn_softc *, uint8_t,
200251538Srpaulo			    const void *, int);
201264912Skevlostatic void		urtwn_r92c_rf_write(struct urtwn_softc *, int,
202264912Skevlo			    uint8_t, uint32_t);
203264912Skevlostatic void		urtwn_r88e_rf_write(struct urtwn_softc *, int,
204264912Skevlo			    uint8_t, uint32_t);
205251538Srpaulostatic uint32_t		urtwn_rf_read(struct urtwn_softc *, int, uint8_t);
206251538Srpaulostatic int		urtwn_llt_write(struct urtwn_softc *, uint32_t,
207251538Srpaulo			    uint32_t);
208251538Srpaulostatic uint8_t		urtwn_efuse_read_1(struct urtwn_softc *, uint16_t);
209251538Srpaulostatic void		urtwn_efuse_read(struct urtwn_softc *);
210264912Skevlostatic void		urtwn_efuse_switch_power(struct urtwn_softc *);
211251538Srpaulostatic int		urtwn_read_chipid(struct urtwn_softc *);
212251538Srpaulostatic void		urtwn_read_rom(struct urtwn_softc *);
213264912Skevlostatic void		urtwn_r88e_read_rom(struct urtwn_softc *);
214251538Srpaulostatic int		urtwn_ra_init(struct urtwn_softc *);
215251538Srpaulostatic void		urtwn_tsf_sync_enable(struct urtwn_softc *);
216251538Srpaulostatic void		urtwn_set_led(struct urtwn_softc *, int, int);
217251538Srpaulostatic int		urtwn_newstate(struct ieee80211vap *,
218251538Srpaulo			    enum ieee80211_state, int);
219251538Srpaulostatic void		urtwn_watchdog(void *);
220251538Srpaulostatic void		urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t);
221251538Srpaulostatic int8_t		urtwn_get_rssi(struct urtwn_softc *, int, void *);
222264912Skevlostatic int8_t		urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *);
223251538Srpaulostatic int		urtwn_tx_start(struct urtwn_softc *,
224251538Srpaulo			    struct ieee80211_node *, struct mbuf *,
225251538Srpaulo			    struct urtwn_data *);
226251538Srpaulostatic void		urtwn_start(struct ifnet *);
227261863Srpaulostatic void		urtwn_start_locked(struct ifnet *,
228261863Srpaulo			    struct urtwn_softc *);
229251538Srpaulostatic int		urtwn_ioctl(struct ifnet *, u_long, caddr_t);
230264912Skevlostatic int		urtwn_r92c_power_on(struct urtwn_softc *);
231264912Skevlostatic int		urtwn_r88e_power_on(struct urtwn_softc *);
232251538Srpaulostatic int		urtwn_llt_init(struct urtwn_softc *);
233251538Srpaulostatic void		urtwn_fw_reset(struct urtwn_softc *);
234264912Skevlostatic void		urtwn_r88e_fw_reset(struct urtwn_softc *);
235251538Srpaulostatic int		urtwn_fw_loadpage(struct urtwn_softc *, int,
236251538Srpaulo			    const uint8_t *, int);
237251538Srpaulostatic int		urtwn_load_firmware(struct urtwn_softc *);
238264912Skevlostatic int		urtwn_r92c_dma_init(struct urtwn_softc *);
239264912Skevlostatic int		urtwn_r88e_dma_init(struct urtwn_softc *);
240251538Srpaulostatic void		urtwn_mac_init(struct urtwn_softc *);
241251538Srpaulostatic void		urtwn_bb_init(struct urtwn_softc *);
242251538Srpaulostatic void		urtwn_rf_init(struct urtwn_softc *);
243251538Srpaulostatic void		urtwn_cam_init(struct urtwn_softc *);
244251538Srpaulostatic void		urtwn_pa_bias_init(struct urtwn_softc *);
245251538Srpaulostatic void		urtwn_rxfilter_init(struct urtwn_softc *);
246251538Srpaulostatic void		urtwn_edca_init(struct urtwn_softc *);
247251538Srpaulostatic void		urtwn_write_txpower(struct urtwn_softc *, int,
248251538Srpaulo			    uint16_t[]);
249251538Srpaulostatic void		urtwn_get_txpower(struct urtwn_softc *, int,
250251538Srpaulo		      	    struct ieee80211_channel *,
251251538Srpaulo			    struct ieee80211_channel *, uint16_t[]);
252264912Skevlostatic void		urtwn_r88e_get_txpower(struct urtwn_softc *, int,
253264912Skevlo		      	    struct ieee80211_channel *,
254264912Skevlo			    struct ieee80211_channel *, uint16_t[]);
255251538Srpaulostatic void		urtwn_set_txpower(struct urtwn_softc *,
256251538Srpaulo		    	    struct ieee80211_channel *,
257251538Srpaulo			    struct ieee80211_channel *);
258251538Srpaulostatic void		urtwn_scan_start(struct ieee80211com *);
259251538Srpaulostatic void		urtwn_scan_end(struct ieee80211com *);
260251538Srpaulostatic void		urtwn_set_channel(struct ieee80211com *);
261251538Srpaulostatic void		urtwn_set_chan(struct urtwn_softc *,
262251538Srpaulo		    	    struct ieee80211_channel *,
263251538Srpaulo			    struct ieee80211_channel *);
264251538Srpaulostatic void		urtwn_update_mcast(struct ifnet *);
265251538Srpaulostatic void		urtwn_iq_calib(struct urtwn_softc *);
266251538Srpaulostatic void		urtwn_lc_calib(struct urtwn_softc *);
267251538Srpaulostatic void		urtwn_init(void *);
268251538Srpaulostatic void		urtwn_init_locked(void *);
269263153Skevlostatic void		urtwn_stop(struct ifnet *);
270263153Skevlostatic void		urtwn_stop_locked(struct ifnet *);
271251538Srpaulostatic void		urtwn_abort_xfers(struct urtwn_softc *);
272251538Srpaulostatic int		urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
273251538Srpaulo			    const struct ieee80211_bpf_params *);
274266472Shselaskystatic void		urtwn_ms_delay(struct urtwn_softc *);
275251538Srpaulo
276251538Srpaulo/* Aliases. */
277251538Srpaulo#define	urtwn_bb_write	urtwn_write_4
278251538Srpaulo#define urtwn_bb_read	urtwn_read_4
279251538Srpaulo
280251538Srpaulostatic const struct usb_config urtwn_config[URTWN_N_TRANSFER] = {
281251538Srpaulo	[URTWN_BULK_RX] = {
282251538Srpaulo		.type = UE_BULK,
283251538Srpaulo		.endpoint = UE_ADDR_ANY,
284251538Srpaulo		.direction = UE_DIR_IN,
285251538Srpaulo		.bufsize = URTWN_RXBUFSZ,
286251538Srpaulo		.flags = {
287251538Srpaulo			.pipe_bof = 1,
288251538Srpaulo			.short_xfer_ok = 1
289251538Srpaulo		},
290251538Srpaulo		.callback = urtwn_bulk_rx_callback,
291251538Srpaulo	},
292251538Srpaulo	[URTWN_BULK_TX_BE] = {
293251538Srpaulo		.type = UE_BULK,
294251538Srpaulo		.endpoint = 0x03,
295251538Srpaulo		.direction = UE_DIR_OUT,
296251538Srpaulo		.bufsize = URTWN_TXBUFSZ,
297251538Srpaulo		.flags = {
298251538Srpaulo			.ext_buffer = 1,
299251538Srpaulo			.pipe_bof = 1,
300251538Srpaulo			.force_short_xfer = 1
301251538Srpaulo		},
302251538Srpaulo		.callback = urtwn_bulk_tx_callback,
303251538Srpaulo		.timeout = URTWN_TX_TIMEOUT,	/* ms */
304251538Srpaulo	},
305251538Srpaulo	[URTWN_BULK_TX_BK] = {
306251538Srpaulo		.type = UE_BULK,
307251538Srpaulo		.endpoint = 0x03,
308251538Srpaulo		.direction = UE_DIR_OUT,
309251538Srpaulo		.bufsize = URTWN_TXBUFSZ,
310251538Srpaulo		.flags = {
311251538Srpaulo			.ext_buffer = 1,
312251538Srpaulo			.pipe_bof = 1,
313251538Srpaulo			.force_short_xfer = 1,
314251538Srpaulo		},
315251538Srpaulo		.callback = urtwn_bulk_tx_callback,
316251538Srpaulo		.timeout = URTWN_TX_TIMEOUT,	/* ms */
317251538Srpaulo	},
318251538Srpaulo	[URTWN_BULK_TX_VI] = {
319251538Srpaulo		.type = UE_BULK,
320251538Srpaulo		.endpoint = 0x02,
321251538Srpaulo		.direction = UE_DIR_OUT,
322251538Srpaulo		.bufsize = URTWN_TXBUFSZ,
323251538Srpaulo		.flags = {
324251538Srpaulo			.ext_buffer = 1,
325251538Srpaulo			.pipe_bof = 1,
326251538Srpaulo			.force_short_xfer = 1
327251538Srpaulo		},
328251538Srpaulo		.callback = urtwn_bulk_tx_callback,
329251538Srpaulo		.timeout = URTWN_TX_TIMEOUT,	/* ms */
330251538Srpaulo	},
331251538Srpaulo	[URTWN_BULK_TX_VO] = {
332251538Srpaulo		.type = UE_BULK,
333251538Srpaulo		.endpoint = 0x02,
334251538Srpaulo		.direction = UE_DIR_OUT,
335251538Srpaulo		.bufsize = URTWN_TXBUFSZ,
336251538Srpaulo		.flags = {
337251538Srpaulo			.ext_buffer = 1,
338251538Srpaulo			.pipe_bof = 1,
339251538Srpaulo			.force_short_xfer = 1
340251538Srpaulo		},
341251538Srpaulo		.callback = urtwn_bulk_tx_callback,
342251538Srpaulo		.timeout = URTWN_TX_TIMEOUT,	/* ms */
343251538Srpaulo	},
344251538Srpaulo};
345251538Srpaulo
346251538Srpaulostatic int
347251538Srpaulourtwn_match(device_t self)
348251538Srpaulo{
349251538Srpaulo	struct usb_attach_arg *uaa = device_get_ivars(self);
350251538Srpaulo
351251538Srpaulo	if (uaa->usb_mode != USB_MODE_HOST)
352251538Srpaulo		return (ENXIO);
353251538Srpaulo	if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX)
354251538Srpaulo		return (ENXIO);
355251538Srpaulo	if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX)
356251538Srpaulo		return (ENXIO);
357251538Srpaulo
358251538Srpaulo	return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa));
359251538Srpaulo}
360251538Srpaulo
361251538Srpaulostatic int
362251538Srpaulourtwn_attach(device_t self)
363251538Srpaulo{
364251538Srpaulo	struct usb_attach_arg *uaa = device_get_ivars(self);
365251538Srpaulo	struct urtwn_softc *sc = device_get_softc(self);
366251538Srpaulo	struct ifnet *ifp;
367251538Srpaulo	struct ieee80211com *ic;
368251538Srpaulo	uint8_t iface_index, bands;
369251538Srpaulo	int error;
370251538Srpaulo
371251538Srpaulo	device_set_usb_desc(self);
372251538Srpaulo	sc->sc_udev = uaa->device;
373251538Srpaulo	sc->sc_dev = self;
374264912Skevlo	if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E)
375264912Skevlo		sc->chip |= URTWN_CHIP_88E;
376251538Srpaulo
377251538Srpaulo	mtx_init(&sc->sc_mtx, device_get_nameunit(self),
378251538Srpaulo	    MTX_NETWORK_LOCK, MTX_DEF);
379251538Srpaulo	callout_init(&sc->sc_watchdog_ch, 0);
380251538Srpaulo
381251538Srpaulo	iface_index = URTWN_IFACE_INDEX;
382251538Srpaulo	error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
383251538Srpaulo	    urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx);
384251538Srpaulo	if (error) {
385251538Srpaulo		device_printf(self, "could not allocate USB transfers, "
386251538Srpaulo		    "err=%s\n", usbd_errstr(error));
387251538Srpaulo		goto detach;
388251538Srpaulo	}
389251538Srpaulo
390251538Srpaulo	URTWN_LOCK(sc);
391251538Srpaulo
392251538Srpaulo	error = urtwn_read_chipid(sc);
393251538Srpaulo	if (error) {
394251538Srpaulo		device_printf(sc->sc_dev, "unsupported test chip\n");
395251538Srpaulo		URTWN_UNLOCK(sc);
396251538Srpaulo		goto detach;
397251538Srpaulo	}
398251538Srpaulo
399251538Srpaulo	/* Determine number of Tx/Rx chains. */
400251538Srpaulo	if (sc->chip & URTWN_CHIP_92C) {
401251538Srpaulo		sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2;
402251538Srpaulo		sc->nrxchains = 2;
403251538Srpaulo	} else {
404251538Srpaulo		sc->ntxchains = 1;
405251538Srpaulo		sc->nrxchains = 1;
406251538Srpaulo	}
407251538Srpaulo
408264912Skevlo	if (sc->chip & URTWN_CHIP_88E)
409264912Skevlo		urtwn_r88e_read_rom(sc);
410264912Skevlo	else
411264912Skevlo		urtwn_read_rom(sc);
412264912Skevlo
413251538Srpaulo	device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n",
414251538Srpaulo	    (sc->chip & URTWN_CHIP_92C) ? "8192CU" :
415264912Skevlo	    (sc->chip & URTWN_CHIP_88E) ? "8188EU" :
416251538Srpaulo	    (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" :
417251538Srpaulo	    (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" :
418251538Srpaulo	    "8188CUS", sc->ntxchains, sc->nrxchains);
419251538Srpaulo
420251538Srpaulo	URTWN_UNLOCK(sc);
421251538Srpaulo
422251538Srpaulo	ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
423251538Srpaulo	if (ifp == NULL) {
424251538Srpaulo		device_printf(sc->sc_dev, "can not if_alloc()\n");
425251538Srpaulo		goto detach;
426251538Srpaulo	}
427251538Srpaulo	ic = ifp->if_l2com;
428251538Srpaulo
429251538Srpaulo	ifp->if_softc = sc;
430251538Srpaulo	if_initname(ifp, "urtwn", device_get_unit(sc->sc_dev));
431251538Srpaulo	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
432251538Srpaulo	ifp->if_init = urtwn_init;
433251538Srpaulo	ifp->if_ioctl = urtwn_ioctl;
434251538Srpaulo	ifp->if_start = urtwn_start;
435251538Srpaulo	IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
436251538Srpaulo	ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
437251538Srpaulo	IFQ_SET_READY(&ifp->if_snd);
438251538Srpaulo
439251538Srpaulo	ic->ic_ifp = ifp;
440251538Srpaulo	ic->ic_phytype = IEEE80211_T_OFDM;	/* not only, but not used */
441251538Srpaulo	ic->ic_opmode = IEEE80211_M_STA;	/* default to BSS mode */
442251538Srpaulo
443251538Srpaulo	/* set device capabilities */
444251538Srpaulo	ic->ic_caps =
445251538Srpaulo		  IEEE80211_C_STA		/* station mode */
446251538Srpaulo		| IEEE80211_C_MONITOR		/* monitor mode */
447251538Srpaulo		| IEEE80211_C_SHPREAMBLE	/* short preamble supported */
448251538Srpaulo		| IEEE80211_C_SHSLOT		/* short slot time supported */
449251538Srpaulo		| IEEE80211_C_BGSCAN		/* capable of bg scanning */
450251538Srpaulo		| IEEE80211_C_WPA		/* 802.11i */
451251538Srpaulo		;
452251538Srpaulo
453251538Srpaulo	bands = 0;
454251538Srpaulo	setbit(&bands, IEEE80211_MODE_11B);
455251538Srpaulo	setbit(&bands, IEEE80211_MODE_11G);
456251538Srpaulo	ieee80211_init_channels(ic, NULL, &bands);
457251538Srpaulo
458251538Srpaulo	ieee80211_ifattach(ic, sc->sc_bssid);
459251538Srpaulo	ic->ic_raw_xmit = urtwn_raw_xmit;
460251538Srpaulo	ic->ic_scan_start = urtwn_scan_start;
461251538Srpaulo	ic->ic_scan_end = urtwn_scan_end;
462251538Srpaulo	ic->ic_set_channel = urtwn_set_channel;
463251538Srpaulo
464251538Srpaulo	ic->ic_vap_create = urtwn_vap_create;
465251538Srpaulo	ic->ic_vap_delete = urtwn_vap_delete;
466251538Srpaulo	ic->ic_update_mcast = urtwn_update_mcast;
467251538Srpaulo
468251538Srpaulo	ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr,
469251538Srpaulo	    sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT,
470251538Srpaulo	    &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
471251538Srpaulo	    URTWN_RX_RADIOTAP_PRESENT);
472251538Srpaulo
473251538Srpaulo	if (bootverbose)
474251538Srpaulo		ieee80211_announce(ic);
475251538Srpaulo
476251538Srpaulo	return (0);
477251538Srpaulo
478251538Srpaulodetach:
479251538Srpaulo	urtwn_detach(self);
480251538Srpaulo	return (ENXIO);			/* failure */
481251538Srpaulo}
482251538Srpaulo
483251538Srpaulostatic int
484251538Srpaulourtwn_detach(device_t self)
485251538Srpaulo{
486251538Srpaulo	struct urtwn_softc *sc = device_get_softc(self);
487251538Srpaulo	struct ifnet *ifp = sc->sc_ifp;
488251538Srpaulo	struct ieee80211com *ic = ifp->if_l2com;
489263153Skevlo	unsigned int x;
490251538Srpaulo
491263153Skevlo	/* Prevent further ioctls. */
492263153Skevlo	URTWN_LOCK(sc);
493263153Skevlo	sc->sc_flags |= URTWN_DETACHED;
494263153Skevlo	URTWN_UNLOCK(sc);
495251538Srpaulo
496263153Skevlo	urtwn_stop(ifp);
497251538Srpaulo
498251538Srpaulo	callout_drain(&sc->sc_watchdog_ch);
499251538Srpaulo
500263153Skevlo	/* Prevent further allocations from RX/TX data lists. */
501263153Skevlo	URTWN_LOCK(sc);
502263153Skevlo	STAILQ_INIT(&sc->sc_tx_active);
503263153Skevlo	STAILQ_INIT(&sc->sc_tx_inactive);
504263153Skevlo	STAILQ_INIT(&sc->sc_tx_pending);
505263153Skevlo
506263153Skevlo	STAILQ_INIT(&sc->sc_rx_active);
507263153Skevlo	STAILQ_INIT(&sc->sc_rx_inactive);
508263153Skevlo	URTWN_UNLOCK(sc);
509263153Skevlo
510263153Skevlo	/* drain USB transfers */
511263153Skevlo	for (x = 0; x != URTWN_N_TRANSFER; x++)
512263153Skevlo		usbd_transfer_drain(sc->sc_xfer[x]);
513263153Skevlo
514263153Skevlo	/* Free data buffers. */
515263153Skevlo	URTWN_LOCK(sc);
516263153Skevlo	urtwn_free_tx_list(sc);
517263153Skevlo	urtwn_free_rx_list(sc);
518263153Skevlo	URTWN_UNLOCK(sc);
519263153Skevlo
520251538Srpaulo	/* stop all USB transfers */
521251538Srpaulo	usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER);
522251538Srpaulo	ieee80211_ifdetach(ic);
523251538Srpaulo
524251538Srpaulo	if_free(ifp);
525251538Srpaulo	mtx_destroy(&sc->sc_mtx);
526251538Srpaulo
527251538Srpaulo	return (0);
528251538Srpaulo}
529251538Srpaulo
530251538Srpaulostatic void
531251538Srpaulourtwn_free_tx_list(struct urtwn_softc *sc)
532251538Srpaulo{
533251538Srpaulo	urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT);
534251538Srpaulo}
535251538Srpaulo
536251538Srpaulostatic void
537251538Srpaulourtwn_free_rx_list(struct urtwn_softc *sc)
538251538Srpaulo{
539251538Srpaulo	urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT);
540251538Srpaulo}
541251538Srpaulo
542251538Srpaulostatic void
543251538Srpaulourtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata)
544251538Srpaulo{
545251538Srpaulo	int i;
546251538Srpaulo
547251538Srpaulo	for (i = 0; i < ndata; i++) {
548251538Srpaulo		struct urtwn_data *dp = &data[i];
549251538Srpaulo
550251538Srpaulo		if (dp->buf != NULL) {
551251538Srpaulo			free(dp->buf, M_USBDEV);
552251538Srpaulo			dp->buf = NULL;
553251538Srpaulo		}
554251538Srpaulo		if (dp->ni != NULL) {
555251538Srpaulo			ieee80211_free_node(dp->ni);
556251538Srpaulo			dp->ni = NULL;
557251538Srpaulo		}
558251538Srpaulo	}
559251538Srpaulo}
560251538Srpaulo
561251538Srpaulostatic usb_error_t
562251538Srpaulourtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req,
563251538Srpaulo    void *data)
564251538Srpaulo{
565251538Srpaulo	usb_error_t err;
566251538Srpaulo	int ntries = 10;
567251538Srpaulo
568251538Srpaulo	URTWN_ASSERT_LOCKED(sc);
569251538Srpaulo
570251538Srpaulo	while (ntries--) {
571251538Srpaulo		err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
572251538Srpaulo		    req, data, 0, NULL, 250 /* ms */);
573251538Srpaulo		if (err == 0)
574251538Srpaulo			break;
575251538Srpaulo
576251538Srpaulo		DPRINTFN(1, "Control request failed, %s (retrying)\n",
577251538Srpaulo		    usbd_errstr(err));
578251538Srpaulo		usb_pause_mtx(&sc->sc_mtx, hz / 100);
579251538Srpaulo	}
580251538Srpaulo	return (err);
581251538Srpaulo}
582251538Srpaulo
583251538Srpaulostatic struct ieee80211vap *
584251538Srpaulourtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
585251538Srpaulo    enum ieee80211_opmode opmode, int flags,
586251538Srpaulo    const uint8_t bssid[IEEE80211_ADDR_LEN],
587251538Srpaulo    const uint8_t mac[IEEE80211_ADDR_LEN])
588251538Srpaulo{
589251538Srpaulo	struct urtwn_vap *uvp;
590251538Srpaulo	struct ieee80211vap *vap;
591251538Srpaulo
592251538Srpaulo	if (!TAILQ_EMPTY(&ic->ic_vaps))		/* only one at a time */
593251538Srpaulo		return (NULL);
594251538Srpaulo
595251538Srpaulo	uvp = (struct urtwn_vap *) malloc(sizeof(struct urtwn_vap),
596251538Srpaulo	    M_80211_VAP, M_NOWAIT | M_ZERO);
597251538Srpaulo	if (uvp == NULL)
598251538Srpaulo		return (NULL);
599251538Srpaulo	vap = &uvp->vap;
600251538Srpaulo	/* enable s/w bmiss handling for sta mode */
601251538Srpaulo
602257743Shselasky	if (ieee80211_vap_setup(ic, vap, name, unit, opmode,
603257743Shselasky	    flags | IEEE80211_CLONE_NOBEACONS, bssid, mac) != 0) {
604257743Shselasky		/* out of memory */
605257743Shselasky		free(uvp, M_80211_VAP);
606257743Shselasky		return (NULL);
607257743Shselasky	}
608257743Shselasky
609251538Srpaulo	/* override state transition machine */
610251538Srpaulo	uvp->newstate = vap->iv_newstate;
611251538Srpaulo	vap->iv_newstate = urtwn_newstate;
612251538Srpaulo
613251538Srpaulo	/* complete setup */
614251538Srpaulo	ieee80211_vap_attach(vap, ieee80211_media_change,
615251538Srpaulo	    ieee80211_media_status);
616251538Srpaulo	ic->ic_opmode = opmode;
617251538Srpaulo	return (vap);
618251538Srpaulo}
619251538Srpaulo
620251538Srpaulostatic void
621251538Srpaulourtwn_vap_delete(struct ieee80211vap *vap)
622251538Srpaulo{
623251538Srpaulo	struct urtwn_vap *uvp = URTWN_VAP(vap);
624251538Srpaulo
625251538Srpaulo	ieee80211_vap_detach(vap);
626251538Srpaulo	free(uvp, M_80211_VAP);
627251538Srpaulo}
628251538Srpaulo
629251538Srpaulostatic struct mbuf *
630251538Srpaulourtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p)
631251538Srpaulo{
632251538Srpaulo	struct ifnet *ifp = sc->sc_ifp;
633251538Srpaulo	struct ieee80211com *ic = ifp->if_l2com;
634251538Srpaulo	struct ieee80211_frame *wh;
635251538Srpaulo	struct mbuf *m;
636251538Srpaulo	struct r92c_rx_stat *stat;
637251538Srpaulo	uint32_t rxdw0, rxdw3;
638251538Srpaulo	uint8_t rate;
639251538Srpaulo	int8_t rssi = 0;
640251538Srpaulo	int infosz;
641251538Srpaulo
642251538Srpaulo	/*
643251538Srpaulo	 * don't pass packets to the ieee80211 framework if the driver isn't
644251538Srpaulo	 * RUNNING.
645251538Srpaulo	 */
646251538Srpaulo	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
647251538Srpaulo		return (NULL);
648251538Srpaulo
649251538Srpaulo	stat = (struct r92c_rx_stat *)buf;
650251538Srpaulo	rxdw0 = le32toh(stat->rxdw0);
651251538Srpaulo	rxdw3 = le32toh(stat->rxdw3);
652251538Srpaulo
653251538Srpaulo	if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) {
654251538Srpaulo		/*
655251538Srpaulo		 * This should not happen since we setup our Rx filter
656251538Srpaulo		 * to not receive these frames.
657251538Srpaulo		 */
658251538Srpaulo		ifp->if_ierrors++;
659251538Srpaulo		return (NULL);
660251538Srpaulo	}
661251538Srpaulo
662251538Srpaulo	rate = MS(rxdw3, R92C_RXDW3_RATE);
663251538Srpaulo	infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
664251538Srpaulo
665251538Srpaulo	/* Get RSSI from PHY status descriptor if present. */
666251538Srpaulo	if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) {
667264912Skevlo		if (sc->chip & URTWN_CHIP_88E)
668264912Skevlo			rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]);
669264912Skevlo		else
670264912Skevlo			rssi = urtwn_get_rssi(sc, rate, &stat[1]);
671251538Srpaulo		/* Update our average RSSI. */
672251538Srpaulo		urtwn_update_avgrssi(sc, rate, rssi);
673252405Srpaulo		/*
674252405Srpaulo		 * Convert the RSSI to a range that will be accepted
675252405Srpaulo		 * by net80211.
676252405Srpaulo		 */
677252405Srpaulo		rssi = URTWN_RSSI(rssi);
678251538Srpaulo	}
679251538Srpaulo
680260463Skevlo	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
681251538Srpaulo	if (m == NULL) {
682251538Srpaulo		device_printf(sc->sc_dev, "could not create RX mbuf\n");
683251538Srpaulo		return (NULL);
684251538Srpaulo	}
685251538Srpaulo
686251538Srpaulo	/* Finalize mbuf. */
687251538Srpaulo	m->m_pkthdr.rcvif = ifp;
688251538Srpaulo	wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz);
689251538Srpaulo	memcpy(mtod(m, uint8_t *), wh, pktlen);
690251538Srpaulo	m->m_pkthdr.len = m->m_len = pktlen;
691251538Srpaulo
692251538Srpaulo	if (ieee80211_radiotap_active(ic)) {
693251538Srpaulo		struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap;
694251538Srpaulo
695251538Srpaulo		tap->wr_flags = 0;
696251538Srpaulo		/* Map HW rate index to 802.11 rate. */
697251538Srpaulo		if (!(rxdw3 & R92C_RXDW3_HT)) {
698251538Srpaulo			switch (rate) {
699251538Srpaulo			/* CCK. */
700251538Srpaulo			case  0: tap->wr_rate =   2; break;
701251538Srpaulo			case  1: tap->wr_rate =   4; break;
702251538Srpaulo			case  2: tap->wr_rate =  11; break;
703251538Srpaulo			case  3: tap->wr_rate =  22; break;
704251538Srpaulo			/* OFDM. */
705251538Srpaulo			case  4: tap->wr_rate =  12; break;
706251538Srpaulo			case  5: tap->wr_rate =  18; break;
707251538Srpaulo			case  6: tap->wr_rate =  24; break;
708251538Srpaulo			case  7: tap->wr_rate =  36; break;
709251538Srpaulo			case  8: tap->wr_rate =  48; break;
710251538Srpaulo			case  9: tap->wr_rate =  72; break;
711251538Srpaulo			case 10: tap->wr_rate =  96; break;
712251538Srpaulo			case 11: tap->wr_rate = 108; break;
713251538Srpaulo			}
714251538Srpaulo		} else if (rate >= 12) {	/* MCS0~15. */
715251538Srpaulo			/* Bit 7 set means HT MCS instead of rate. */
716251538Srpaulo			tap->wr_rate = 0x80 | (rate - 12);
717251538Srpaulo		}
718251538Srpaulo		tap->wr_dbm_antsignal = rssi;
719251538Srpaulo		tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
720251538Srpaulo		tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
721251538Srpaulo	}
722251538Srpaulo
723251538Srpaulo	*rssi_p = rssi;
724251538Srpaulo
725251538Srpaulo	return (m);
726251538Srpaulo}
727251538Srpaulo
728251538Srpaulostatic struct mbuf *
729251538Srpaulourtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi,
730251538Srpaulo    int8_t *nf)
731251538Srpaulo{
732251538Srpaulo	struct urtwn_softc *sc = data->sc;
733251538Srpaulo	struct ifnet *ifp = sc->sc_ifp;
734251538Srpaulo	struct r92c_rx_stat *stat;
735251538Srpaulo	struct mbuf *m, *m0 = NULL, *prevm = NULL;
736251538Srpaulo	uint32_t rxdw0;
737251538Srpaulo	uint8_t *buf;
738251538Srpaulo	int len, totlen, pktlen, infosz, npkts;
739251538Srpaulo
740251538Srpaulo	usbd_xfer_status(xfer, &len, NULL, NULL, NULL);
741251538Srpaulo
742251538Srpaulo	if (len < sizeof(*stat)) {
743251538Srpaulo		ifp->if_ierrors++;
744251538Srpaulo		return (NULL);
745251538Srpaulo	}
746251538Srpaulo
747251538Srpaulo	buf = data->buf;
748251538Srpaulo	/* Get the number of encapsulated frames. */
749251538Srpaulo	stat = (struct r92c_rx_stat *)buf;
750251538Srpaulo	npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT);
751251538Srpaulo	DPRINTFN(6, "Rx %d frames in one chunk\n", npkts);
752251538Srpaulo
753251538Srpaulo	/* Process all of them. */
754251538Srpaulo	while (npkts-- > 0) {
755251538Srpaulo		if (len < sizeof(*stat))
756251538Srpaulo			break;
757251538Srpaulo		stat = (struct r92c_rx_stat *)buf;
758251538Srpaulo		rxdw0 = le32toh(stat->rxdw0);
759251538Srpaulo
760251538Srpaulo		pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN);
761251538Srpaulo		if (pktlen == 0)
762251538Srpaulo			break;
763251538Srpaulo
764251538Srpaulo		infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
765251538Srpaulo
766251538Srpaulo		/* Make sure everything fits in xfer. */
767251538Srpaulo		totlen = sizeof(*stat) + infosz + pktlen;
768251538Srpaulo		if (totlen > len)
769251538Srpaulo			break;
770251538Srpaulo
771251538Srpaulo		m = urtwn_rx_frame(sc, buf, pktlen, rssi);
772251538Srpaulo		if (m0 == NULL)
773251538Srpaulo			m0 = m;
774251538Srpaulo		if (prevm == NULL)
775251538Srpaulo			prevm = m;
776251538Srpaulo		else {
777251538Srpaulo			prevm->m_next = m;
778251538Srpaulo			prevm = m;
779251538Srpaulo		}
780251538Srpaulo
781251538Srpaulo		/* Next chunk is 128-byte aligned. */
782251538Srpaulo		totlen = (totlen + 127) & ~127;
783251538Srpaulo		buf += totlen;
784251538Srpaulo		len -= totlen;
785251538Srpaulo	}
786251538Srpaulo
787251538Srpaulo	return (m0);
788251538Srpaulo}
789251538Srpaulo
790251538Srpaulostatic void
791251538Srpaulourtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
792251538Srpaulo{
793251538Srpaulo	struct urtwn_softc *sc = usbd_xfer_softc(xfer);
794251538Srpaulo	struct ifnet *ifp = sc->sc_ifp;
795251538Srpaulo	struct ieee80211com *ic = ifp->if_l2com;
796251538Srpaulo	struct ieee80211_frame *wh;
797251538Srpaulo	struct ieee80211_node *ni;
798251538Srpaulo	struct mbuf *m = NULL, *next;
799251538Srpaulo	struct urtwn_data *data;
800251538Srpaulo	int8_t nf;
801251538Srpaulo	int rssi = 1;
802251538Srpaulo
803251538Srpaulo	URTWN_ASSERT_LOCKED(sc);
804251538Srpaulo
805251538Srpaulo	switch (USB_GET_STATE(xfer)) {
806251538Srpaulo	case USB_ST_TRANSFERRED:
807251538Srpaulo		data = STAILQ_FIRST(&sc->sc_rx_active);
808251538Srpaulo		if (data == NULL)
809251538Srpaulo			goto tr_setup;
810251538Srpaulo		STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
811251538Srpaulo		m = urtwn_rxeof(xfer, data, &rssi, &nf);
812251538Srpaulo		STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
813251538Srpaulo		/* FALLTHROUGH */
814251538Srpaulo	case USB_ST_SETUP:
815251538Srpaulotr_setup:
816251538Srpaulo		data = STAILQ_FIRST(&sc->sc_rx_inactive);
817251538Srpaulo		if (data == NULL) {
818251538Srpaulo			KASSERT(m == NULL, ("mbuf isn't NULL"));
819251538Srpaulo			return;
820251538Srpaulo		}
821251538Srpaulo		STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
822251538Srpaulo		STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
823251538Srpaulo		usbd_xfer_set_frame_data(xfer, 0, data->buf,
824251538Srpaulo		    usbd_xfer_max_len(xfer));
825251538Srpaulo		usbd_transfer_submit(xfer);
826251538Srpaulo
827251538Srpaulo		/*
828251538Srpaulo		 * To avoid LOR we should unlock our private mutex here to call
829251538Srpaulo		 * ieee80211_input() because here is at the end of a USB
830251538Srpaulo		 * callback and safe to unlock.
831251538Srpaulo		 */
832251538Srpaulo		URTWN_UNLOCK(sc);
833251538Srpaulo		while (m != NULL) {
834251538Srpaulo			next = m->m_next;
835251538Srpaulo			m->m_next = NULL;
836251538Srpaulo			wh = mtod(m, struct ieee80211_frame *);
837251538Srpaulo			ni = ieee80211_find_rxnode(ic,
838251538Srpaulo			    (struct ieee80211_frame_min *)wh);
839251538Srpaulo			nf = URTWN_NOISE_FLOOR;
840251538Srpaulo			if (ni != NULL) {
841251538Srpaulo				(void)ieee80211_input(ni, m, rssi, nf);
842251538Srpaulo				ieee80211_free_node(ni);
843251538Srpaulo			} else
844251538Srpaulo				(void)ieee80211_input_all(ic, m, rssi, nf);
845251538Srpaulo			m = next;
846251538Srpaulo		}
847251538Srpaulo		URTWN_LOCK(sc);
848251538Srpaulo		break;
849251538Srpaulo	default:
850251538Srpaulo		/* needs it to the inactive queue due to a error. */
851251538Srpaulo		data = STAILQ_FIRST(&sc->sc_rx_active);
852251538Srpaulo		if (data != NULL) {
853251538Srpaulo			STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
854251538Srpaulo			STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
855251538Srpaulo		}
856251538Srpaulo		if (error != USB_ERR_CANCELLED) {
857251538Srpaulo			usbd_xfer_set_stall(xfer);
858251538Srpaulo			ifp->if_ierrors++;
859251538Srpaulo			goto tr_setup;
860251538Srpaulo		}
861251538Srpaulo		break;
862251538Srpaulo	}
863251538Srpaulo}
864251538Srpaulo
865251538Srpaulostatic void
866251538Srpaulourtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data)
867251538Srpaulo{
868251538Srpaulo	struct urtwn_softc *sc = usbd_xfer_softc(xfer);
869251538Srpaulo	struct ifnet *ifp = sc->sc_ifp;
870251538Srpaulo	struct mbuf *m;
871251538Srpaulo
872251538Srpaulo	URTWN_ASSERT_LOCKED(sc);
873251538Srpaulo
874251538Srpaulo	/*
875251538Srpaulo	 * Do any tx complete callback.  Note this must be done before releasing
876251538Srpaulo	 * the node reference.
877251538Srpaulo	 */
878251538Srpaulo	if (data->m) {
879251538Srpaulo		m = data->m;
880251538Srpaulo		if (m->m_flags & M_TXCB) {
881251538Srpaulo			/* XXX status? */
882251538Srpaulo			ieee80211_process_callback(data->ni, m, 0);
883251538Srpaulo		}
884251538Srpaulo		m_freem(m);
885251538Srpaulo		data->m = NULL;
886251538Srpaulo	}
887251538Srpaulo	if (data->ni) {
888251538Srpaulo		ieee80211_free_node(data->ni);
889251538Srpaulo		data->ni = NULL;
890251538Srpaulo	}
891251538Srpaulo	sc->sc_txtimer = 0;
892251538Srpaulo	ifp->if_opackets++;
893251538Srpaulo	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
894251538Srpaulo}
895251538Srpaulo
896251538Srpaulostatic void
897251538Srpaulourtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error)
898251538Srpaulo{
899251538Srpaulo	struct urtwn_softc *sc = usbd_xfer_softc(xfer);
900251538Srpaulo	struct ifnet *ifp = sc->sc_ifp;
901251538Srpaulo	struct urtwn_data *data;
902251538Srpaulo
903251538Srpaulo	URTWN_ASSERT_LOCKED(sc);
904251538Srpaulo
905251538Srpaulo	switch (USB_GET_STATE(xfer)){
906251538Srpaulo	case USB_ST_TRANSFERRED:
907251538Srpaulo		data = STAILQ_FIRST(&sc->sc_tx_active);
908251538Srpaulo		if (data == NULL)
909251538Srpaulo			goto tr_setup;
910251538Srpaulo		STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
911251538Srpaulo		urtwn_txeof(xfer, data);
912251538Srpaulo		STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next);
913251538Srpaulo		/* FALLTHROUGH */
914251538Srpaulo	case USB_ST_SETUP:
915251538Srpaulotr_setup:
916251538Srpaulo		data = STAILQ_FIRST(&sc->sc_tx_pending);
917251538Srpaulo		if (data == NULL) {
918251538Srpaulo			DPRINTF("%s: empty pending queue\n", __func__);
919251538Srpaulo			return;
920251538Srpaulo		}
921251538Srpaulo		STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next);
922251538Srpaulo		STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next);
923251538Srpaulo		usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen);
924251538Srpaulo		usbd_transfer_submit(xfer);
925261863Srpaulo		urtwn_start_locked(ifp, sc);
926251538Srpaulo		break;
927251538Srpaulo	default:
928251538Srpaulo		data = STAILQ_FIRST(&sc->sc_tx_active);
929251538Srpaulo		if (data == NULL)
930251538Srpaulo			goto tr_setup;
931251538Srpaulo		if (data->ni != NULL) {
932251538Srpaulo			ieee80211_free_node(data->ni);
933251538Srpaulo			data->ni = NULL;
934251538Srpaulo			ifp->if_oerrors++;
935251538Srpaulo		}
936251538Srpaulo		if (error != USB_ERR_CANCELLED) {
937251538Srpaulo			usbd_xfer_set_stall(xfer);
938251538Srpaulo			goto tr_setup;
939251538Srpaulo		}
940251538Srpaulo		break;
941251538Srpaulo	}
942251538Srpaulo}
943251538Srpaulo
944251538Srpaulostatic struct urtwn_data *
945251538Srpaulo_urtwn_getbuf(struct urtwn_softc *sc)
946251538Srpaulo{
947251538Srpaulo	struct urtwn_data *bf;
948251538Srpaulo
949251538Srpaulo	bf = STAILQ_FIRST(&sc->sc_tx_inactive);
950251538Srpaulo	if (bf != NULL)
951251538Srpaulo		STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next);
952251538Srpaulo	else
953251538Srpaulo		bf = NULL;
954251538Srpaulo	if (bf == NULL)
955251538Srpaulo		DPRINTF("%s: %s\n", __func__, "out of xmit buffers");
956251538Srpaulo	return (bf);
957251538Srpaulo}
958251538Srpaulo
959251538Srpaulostatic struct urtwn_data *
960251538Srpaulourtwn_getbuf(struct urtwn_softc *sc)
961251538Srpaulo{
962251538Srpaulo        struct urtwn_data *bf;
963251538Srpaulo
964251538Srpaulo	URTWN_ASSERT_LOCKED(sc);
965251538Srpaulo
966251538Srpaulo	bf = _urtwn_getbuf(sc);
967251538Srpaulo	if (bf == NULL) {
968251538Srpaulo		struct ifnet *ifp = sc->sc_ifp;
969251538Srpaulo		DPRINTF("%s: stop queue\n", __func__);
970251538Srpaulo		ifp->if_drv_flags |= IFF_DRV_OACTIVE;
971251538Srpaulo	}
972251538Srpaulo	return (bf);
973251538Srpaulo}
974251538Srpaulo
975251538Srpaulostatic int
976251538Srpaulourtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
977251538Srpaulo    int len)
978251538Srpaulo{
979251538Srpaulo	usb_device_request_t req;
980251538Srpaulo
981251538Srpaulo	req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
982251538Srpaulo	req.bRequest = R92C_REQ_REGS;
983251538Srpaulo	USETW(req.wValue, addr);
984251538Srpaulo	USETW(req.wIndex, 0);
985251538Srpaulo	USETW(req.wLength, len);
986251538Srpaulo	return (urtwn_do_request(sc, &req, buf));
987251538Srpaulo}
988251538Srpaulo
989251538Srpaulostatic void
990251538Srpaulourtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val)
991251538Srpaulo{
992251538Srpaulo	urtwn_write_region_1(sc, addr, &val, 1);
993251538Srpaulo}
994251538Srpaulo
995251538Srpaulo
996251538Srpaulostatic void
997251538Srpaulourtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val)
998251538Srpaulo{
999251538Srpaulo	val = htole16(val);
1000251538Srpaulo	urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2);
1001251538Srpaulo}
1002251538Srpaulo
1003251538Srpaulostatic void
1004251538Srpaulourtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val)
1005251538Srpaulo{
1006251538Srpaulo	val = htole32(val);
1007251538Srpaulo	urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4);
1008251538Srpaulo}
1009251538Srpaulo
1010251538Srpaulostatic int
1011251538Srpaulourtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
1012251538Srpaulo    int len)
1013251538Srpaulo{
1014251538Srpaulo	usb_device_request_t req;
1015251538Srpaulo
1016251538Srpaulo	req.bmRequestType = UT_READ_VENDOR_DEVICE;
1017251538Srpaulo	req.bRequest = R92C_REQ_REGS;
1018251538Srpaulo	USETW(req.wValue, addr);
1019251538Srpaulo	USETW(req.wIndex, 0);
1020251538Srpaulo	USETW(req.wLength, len);
1021251538Srpaulo	return (urtwn_do_request(sc, &req, buf));
1022251538Srpaulo}
1023251538Srpaulo
1024251538Srpaulostatic uint8_t
1025251538Srpaulourtwn_read_1(struct urtwn_softc *sc, uint16_t addr)
1026251538Srpaulo{
1027251538Srpaulo	uint8_t val;
1028251538Srpaulo
1029251538Srpaulo	if (urtwn_read_region_1(sc, addr, &val, 1) != 0)
1030251538Srpaulo		return (0xff);
1031251538Srpaulo	return (val);
1032251538Srpaulo}
1033251538Srpaulo
1034251538Srpaulostatic uint16_t
1035251538Srpaulourtwn_read_2(struct urtwn_softc *sc, uint16_t addr)
1036251538Srpaulo{
1037251538Srpaulo	uint16_t val;
1038251538Srpaulo
1039251538Srpaulo	if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0)
1040251538Srpaulo		return (0xffff);
1041251538Srpaulo	return (le16toh(val));
1042251538Srpaulo}
1043251538Srpaulo
1044251538Srpaulostatic uint32_t
1045251538Srpaulourtwn_read_4(struct urtwn_softc *sc, uint16_t addr)
1046251538Srpaulo{
1047251538Srpaulo	uint32_t val;
1048251538Srpaulo
1049251538Srpaulo	if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0)
1050251538Srpaulo		return (0xffffffff);
1051251538Srpaulo	return (le32toh(val));
1052251538Srpaulo}
1053251538Srpaulo
1054251538Srpaulostatic int
1055251538Srpaulourtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len)
1056251538Srpaulo{
1057251538Srpaulo	struct r92c_fw_cmd cmd;
1058251538Srpaulo	int ntries;
1059251538Srpaulo
1060251538Srpaulo	/* Wait for current FW box to be empty. */
1061251538Srpaulo	for (ntries = 0; ntries < 100; ntries++) {
1062251538Srpaulo		if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))
1063251538Srpaulo			break;
1064266472Shselasky		urtwn_ms_delay(sc);
1065251538Srpaulo	}
1066251538Srpaulo	if (ntries == 100) {
1067251538Srpaulo		device_printf(sc->sc_dev,
1068251538Srpaulo		    "could not send firmware command\n");
1069251538Srpaulo		return (ETIMEDOUT);
1070251538Srpaulo	}
1071251538Srpaulo	memset(&cmd, 0, sizeof(cmd));
1072251538Srpaulo	cmd.id = id;
1073251538Srpaulo	if (len > 3)
1074251538Srpaulo		cmd.id |= R92C_CMD_FLAG_EXT;
1075251538Srpaulo	KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n"));
1076251538Srpaulo	memcpy(cmd.msg, buf, len);
1077251538Srpaulo
1078251538Srpaulo	/* Write the first word last since that will trigger the FW. */
1079251538Srpaulo	urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur),
1080251538Srpaulo	    (uint8_t *)&cmd + 4, 2);
1081251538Srpaulo	urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur),
1082251538Srpaulo	    (uint8_t *)&cmd + 0, 4);
1083251538Srpaulo
1084251538Srpaulo	sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX;
1085251538Srpaulo	return (0);
1086251538Srpaulo}
1087251538Srpaulo
1088264912Skevlostatic __inline void
1089251538Srpaulourtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val)
1090251538Srpaulo{
1091264912Skevlo
1092264912Skevlo	sc->sc_rf_write(sc, chain, addr, val);
1093264912Skevlo}
1094264912Skevlo
1095264912Skevlostatic void
1096264912Skevlourtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr,
1097264912Skevlo    uint32_t val)
1098264912Skevlo{
1099251538Srpaulo	urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1100251538Srpaulo	    SM(R92C_LSSI_PARAM_ADDR, addr) |
1101251538Srpaulo	    SM(R92C_LSSI_PARAM_DATA, val));
1102251538Srpaulo}
1103251538Srpaulo
1104264912Skevlostatic void
1105264912Skevlourtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr,
1106264912Skevlouint32_t val)
1107264912Skevlo{
1108264912Skevlo	urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1109264912Skevlo	    SM(R88E_LSSI_PARAM_ADDR, addr) |
1110264912Skevlo	    SM(R92C_LSSI_PARAM_DATA, val));
1111264912Skevlo}
1112264912Skevlo
1113251538Srpaulostatic uint32_t
1114251538Srpaulourtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr)
1115251538Srpaulo{
1116251538Srpaulo	uint32_t reg[R92C_MAX_CHAINS], val;
1117251538Srpaulo
1118251538Srpaulo	reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
1119251538Srpaulo	if (chain != 0)
1120251538Srpaulo		reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
1121251538Srpaulo
1122251538Srpaulo	urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1123251538Srpaulo	    reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
1124266472Shselasky	urtwn_ms_delay(sc);
1125251538Srpaulo
1126251538Srpaulo	urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
1127251538Srpaulo	    RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
1128251538Srpaulo	    R92C_HSSI_PARAM2_READ_EDGE);
1129266472Shselasky	urtwn_ms_delay(sc);
1130251538Srpaulo
1131251538Srpaulo	urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1132251538Srpaulo	    reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
1133266472Shselasky	urtwn_ms_delay(sc);
1134251538Srpaulo
1135251538Srpaulo	if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
1136251538Srpaulo		val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
1137251538Srpaulo	else
1138251538Srpaulo		val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
1139251538Srpaulo	return (MS(val, R92C_LSSI_READBACK_DATA));
1140251538Srpaulo}
1141251538Srpaulo
1142251538Srpaulostatic int
1143251538Srpaulourtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data)
1144251538Srpaulo{
1145251538Srpaulo	int ntries;
1146251538Srpaulo
1147251538Srpaulo	urtwn_write_4(sc, R92C_LLT_INIT,
1148251538Srpaulo	    SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
1149251538Srpaulo	    SM(R92C_LLT_INIT_ADDR, addr) |
1150251538Srpaulo	    SM(R92C_LLT_INIT_DATA, data));
1151251538Srpaulo	/* Wait for write operation to complete. */
1152251538Srpaulo	for (ntries = 0; ntries < 20; ntries++) {
1153251538Srpaulo		if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
1154251538Srpaulo		    R92C_LLT_INIT_OP_NO_ACTIVE)
1155251538Srpaulo			return (0);
1156266472Shselasky		urtwn_ms_delay(sc);
1157251538Srpaulo	}
1158251538Srpaulo	return (ETIMEDOUT);
1159251538Srpaulo}
1160251538Srpaulo
1161251538Srpaulostatic uint8_t
1162251538Srpaulourtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr)
1163251538Srpaulo{
1164251538Srpaulo	uint32_t reg;
1165251538Srpaulo	int ntries;
1166251538Srpaulo
1167251538Srpaulo	reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1168251538Srpaulo	reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr);
1169251538Srpaulo	reg &= ~R92C_EFUSE_CTRL_VALID;
1170251538Srpaulo	urtwn_write_4(sc, R92C_EFUSE_CTRL, reg);
1171251538Srpaulo	/* Wait for read operation to complete. */
1172251538Srpaulo	for (ntries = 0; ntries < 100; ntries++) {
1173251538Srpaulo		reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1174251538Srpaulo		if (reg & R92C_EFUSE_CTRL_VALID)
1175251538Srpaulo			return (MS(reg, R92C_EFUSE_CTRL_DATA));
1176266472Shselasky		urtwn_ms_delay(sc);
1177251538Srpaulo	}
1178251538Srpaulo	device_printf(sc->sc_dev,
1179251538Srpaulo	    "could not read efuse byte at address 0x%x\n", addr);
1180251538Srpaulo	return (0xff);
1181251538Srpaulo}
1182251538Srpaulo
1183251538Srpaulostatic void
1184251538Srpaulourtwn_efuse_read(struct urtwn_softc *sc)
1185251538Srpaulo{
1186251538Srpaulo	uint8_t *rom = (uint8_t *)&sc->rom;
1187251538Srpaulo	uint16_t addr = 0;
1188251538Srpaulo	uint32_t reg;
1189251538Srpaulo	uint8_t off, msk;
1190251538Srpaulo	int i;
1191251538Srpaulo
1192264912Skevlo	urtwn_efuse_switch_power(sc);
1193264912Skevlo
1194251538Srpaulo	memset(&sc->rom, 0xff, sizeof(sc->rom));
1195251538Srpaulo	while (addr < 512) {
1196251538Srpaulo		reg = urtwn_efuse_read_1(sc, addr);
1197251538Srpaulo		if (reg == 0xff)
1198251538Srpaulo			break;
1199251538Srpaulo		addr++;
1200251538Srpaulo		off = reg >> 4;
1201251538Srpaulo		msk = reg & 0xf;
1202251538Srpaulo		for (i = 0; i < 4; i++) {
1203251538Srpaulo			if (msk & (1 << i))
1204251538Srpaulo				continue;
1205251538Srpaulo			rom[off * 8 + i * 2 + 0] =
1206251538Srpaulo			    urtwn_efuse_read_1(sc, addr);
1207251538Srpaulo			addr++;
1208251538Srpaulo			rom[off * 8 + i * 2 + 1] =
1209251538Srpaulo			    urtwn_efuse_read_1(sc, addr);
1210251538Srpaulo			addr++;
1211251538Srpaulo		}
1212251538Srpaulo	}
1213251538Srpaulo#ifdef URTWN_DEBUG
1214251538Srpaulo	if (urtwn_debug >= 2) {
1215251538Srpaulo		/* Dump ROM content. */
1216251538Srpaulo		printf("\n");
1217251538Srpaulo		for (i = 0; i < sizeof(sc->rom); i++)
1218251538Srpaulo			printf("%02x:", rom[i]);
1219251538Srpaulo		printf("\n");
1220251538Srpaulo	}
1221251538Srpaulo#endif
1222251538Srpaulo}
1223264912Skevlostatic void
1224264912Skevlourtwn_efuse_switch_power(struct urtwn_softc *sc)
1225264912Skevlo{
1226264912Skevlo	uint32_t reg;
1227251538Srpaulo
1228264912Skevlo	reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);
1229264912Skevlo	if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
1230264912Skevlo		urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
1231264912Skevlo		    reg | R92C_SYS_ISO_CTRL_PWC_EV12V);
1232264912Skevlo	}
1233264912Skevlo	reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
1234264912Skevlo	if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {
1235264912Skevlo		urtwn_write_2(sc, R92C_SYS_FUNC_EN,
1236264912Skevlo		    reg | R92C_SYS_FUNC_EN_ELDR);
1237264912Skevlo	}
1238264912Skevlo	reg = urtwn_read_2(sc, R92C_SYS_CLKR);
1239264912Skevlo	if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=
1240264912Skevlo	    (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) {
1241264912Skevlo		urtwn_write_2(sc, R92C_SYS_CLKR,
1242264912Skevlo		    reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
1243264912Skevlo	}
1244264912Skevlo}
1245264912Skevlo
1246251538Srpaulostatic int
1247251538Srpaulourtwn_read_chipid(struct urtwn_softc *sc)
1248251538Srpaulo{
1249251538Srpaulo	uint32_t reg;
1250251538Srpaulo
1251264912Skevlo	if (sc->chip & URTWN_CHIP_88E)
1252264912Skevlo		return (0);
1253264912Skevlo
1254251538Srpaulo	reg = urtwn_read_4(sc, R92C_SYS_CFG);
1255251538Srpaulo	if (reg & R92C_SYS_CFG_TRP_VAUX_EN)
1256251538Srpaulo		return (EIO);
1257251538Srpaulo
1258251538Srpaulo	if (reg & R92C_SYS_CFG_TYPE_92C) {
1259251538Srpaulo		sc->chip |= URTWN_CHIP_92C;
1260251538Srpaulo		/* Check if it is a castrated 8192C. */
1261251538Srpaulo		if (MS(urtwn_read_4(sc, R92C_HPON_FSM),
1262251538Srpaulo		    R92C_HPON_FSM_CHIP_BONDING_ID) ==
1263251538Srpaulo		    R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R)
1264251538Srpaulo			sc->chip |= URTWN_CHIP_92C_1T2R;
1265251538Srpaulo	}
1266251538Srpaulo	if (reg & R92C_SYS_CFG_VENDOR_UMC) {
1267251538Srpaulo		sc->chip |= URTWN_CHIP_UMC;
1268251538Srpaulo		if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0)
1269251538Srpaulo			sc->chip |= URTWN_CHIP_UMC_A_CUT;
1270251538Srpaulo	}
1271251538Srpaulo	return (0);
1272251538Srpaulo}
1273251538Srpaulo
1274251538Srpaulostatic void
1275251538Srpaulourtwn_read_rom(struct urtwn_softc *sc)
1276251538Srpaulo{
1277251538Srpaulo	struct r92c_rom *rom = &sc->rom;
1278251538Srpaulo
1279251538Srpaulo	/* Read full ROM image. */
1280251538Srpaulo	urtwn_efuse_read(sc);
1281251538Srpaulo
1282251538Srpaulo	/* XXX Weird but this is what the vendor driver does. */
1283251538Srpaulo	sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa);
1284251538Srpaulo	DPRINTF("PA setting=0x%x\n", sc->pa_setting);
1285251538Srpaulo
1286251538Srpaulo	sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE);
1287251538Srpaulo
1288251538Srpaulo	sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY);
1289251538Srpaulo	DPRINTF("regulatory type=%d\n", sc->regulatory);
1290264912Skevlo	IEEE80211_ADDR_COPY(sc->sc_bssid, rom->macaddr);
1291251538Srpaulo
1292264912Skevlo	sc->sc_rf_write = urtwn_r92c_rf_write;
1293264912Skevlo	sc->sc_power_on = urtwn_r92c_power_on;
1294264912Skevlo	sc->sc_dma_init = urtwn_r92c_dma_init;
1295251538Srpaulo}
1296251538Srpaulo
1297264912Skevlostatic void
1298264912Skevlourtwn_r88e_read_rom(struct urtwn_softc *sc)
1299264912Skevlo{
1300264912Skevlo	uint8_t *rom = sc->r88e_rom;
1301264912Skevlo	uint16_t addr = 0;
1302264912Skevlo	uint32_t reg;
1303264912Skevlo	uint8_t off, msk, tmp;
1304264912Skevlo	int i;
1305264912Skevlo
1306264982Sandreast	off = 0;
1307264912Skevlo	urtwn_efuse_switch_power(sc);
1308264912Skevlo
1309264912Skevlo	/* Read full ROM image. */
1310264912Skevlo	memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom));
1311264912Skevlo	while (addr < 1024) {
1312264912Skevlo		reg = urtwn_efuse_read_1(sc, addr);
1313264912Skevlo		if (reg == 0xff)
1314264912Skevlo			break;
1315264912Skevlo		addr++;
1316264912Skevlo		if ((reg & 0x1f) == 0x0f) {
1317264912Skevlo			tmp = (reg & 0xe0) >> 5;
1318264912Skevlo			reg = urtwn_efuse_read_1(sc, addr);
1319264912Skevlo			if ((reg & 0x0f) != 0x0f)
1320264912Skevlo				off = ((reg & 0xf0) >> 1) | tmp;
1321264912Skevlo			addr++;
1322264912Skevlo		} else
1323264912Skevlo			off = reg >> 4;
1324264912Skevlo		msk = reg & 0xf;
1325264912Skevlo		for (i = 0; i < 4; i++) {
1326264912Skevlo			if (msk & (1 << i))
1327264912Skevlo				continue;
1328264912Skevlo			rom[off * 8 + i * 2 + 0] =
1329264912Skevlo			    urtwn_efuse_read_1(sc, addr);
1330264912Skevlo			addr++;
1331264912Skevlo			rom[off * 8 + i * 2 + 1] =
1332264912Skevlo			    urtwn_efuse_read_1(sc, addr);
1333264912Skevlo			addr++;
1334264912Skevlo		}
1335264912Skevlo	}
1336264912Skevlo
1337264912Skevlo	addr = 0x10;
1338264912Skevlo	for (i = 0; i < 6; i++)
1339264912Skevlo		sc->cck_tx_pwr[i] = sc->r88e_rom[addr++];
1340264912Skevlo	for (i = 0; i < 5; i++)
1341264912Skevlo		sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++];
1342264912Skevlo	sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4;
1343264912Skevlo	if (sc->bw20_tx_pwr_diff & 0x08)
1344264912Skevlo		sc->bw20_tx_pwr_diff |= 0xf0;
1345264912Skevlo	sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf);
1346264912Skevlo	if (sc->ofdm_tx_pwr_diff & 0x08)
1347264912Skevlo		sc->ofdm_tx_pwr_diff |= 0xf0;
1348264912Skevlo	sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY);
1349264912Skevlo	IEEE80211_ADDR_COPY(sc->sc_bssid, &sc->r88e_rom[0xd7]);
1350264912Skevlo
1351264912Skevlo	sc->sc_rf_write = urtwn_r88e_rf_write;
1352264912Skevlo	sc->sc_power_on = urtwn_r88e_power_on;
1353264912Skevlo	sc->sc_dma_init = urtwn_r88e_dma_init;
1354264912Skevlo}
1355264912Skevlo
1356251538Srpaulo/*
1357251538Srpaulo * Initialize rate adaptation in firmware.
1358251538Srpaulo */
1359251538Srpaulostatic int
1360251538Srpaulourtwn_ra_init(struct urtwn_softc *sc)
1361251538Srpaulo{
1362251538Srpaulo	static const uint8_t map[] =
1363251538Srpaulo	    { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 };
1364251538Srpaulo	struct ieee80211com *ic = sc->sc_ifp->if_l2com;
1365251538Srpaulo	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1366251538Srpaulo	struct ieee80211_node *ni;
1367251538Srpaulo	struct ieee80211_rateset *rs;
1368251538Srpaulo	struct r92c_fw_cmd_macid_cfg cmd;
1369251538Srpaulo	uint32_t rates, basicrates;
1370251538Srpaulo	uint8_t mode;
1371251538Srpaulo	int maxrate, maxbasicrate, error, i, j;
1372251538Srpaulo
1373251538Srpaulo	ni = ieee80211_ref_node(vap->iv_bss);
1374251538Srpaulo	rs = &ni->ni_rates;
1375251538Srpaulo
1376251538Srpaulo	/* Get normal and basic rates mask. */
1377251538Srpaulo	rates = basicrates = 0;
1378251538Srpaulo	maxrate = maxbasicrate = 0;
1379251538Srpaulo	for (i = 0; i < rs->rs_nrates; i++) {
1380251538Srpaulo		/* Convert 802.11 rate to HW rate index. */
1381251538Srpaulo		for (j = 0; j < nitems(map); j++)
1382251538Srpaulo			if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j])
1383251538Srpaulo				break;
1384251538Srpaulo		if (j == nitems(map))	/* Unknown rate, skip. */
1385251538Srpaulo			continue;
1386251538Srpaulo		rates |= 1 << j;
1387251538Srpaulo		if (j > maxrate)
1388251538Srpaulo			maxrate = j;
1389251538Srpaulo		if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) {
1390251538Srpaulo			basicrates |= 1 << j;
1391251538Srpaulo			if (j > maxbasicrate)
1392251538Srpaulo				maxbasicrate = j;
1393251538Srpaulo		}
1394251538Srpaulo	}
1395251538Srpaulo	if (ic->ic_curmode == IEEE80211_MODE_11B)
1396251538Srpaulo		mode = R92C_RAID_11B;
1397251538Srpaulo	else
1398251538Srpaulo		mode = R92C_RAID_11BG;
1399251538Srpaulo	DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n",
1400251538Srpaulo	    mode, rates, basicrates);
1401251538Srpaulo
1402251538Srpaulo	/* Set rates mask for group addressed frames. */
1403251538Srpaulo	cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID;
1404251538Srpaulo	cmd.mask = htole32(mode << 28 | basicrates);
1405251538Srpaulo	error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1406251538Srpaulo	if (error != 0) {
1407252401Srpaulo		ieee80211_free_node(ni);
1408251538Srpaulo		device_printf(sc->sc_dev,
1409251538Srpaulo		    "could not add broadcast station\n");
1410251538Srpaulo		return (error);
1411251538Srpaulo	}
1412251538Srpaulo	/* Set initial MRR rate. */
1413251538Srpaulo	DPRINTF("maxbasicrate=%d\n", maxbasicrate);
1414251538Srpaulo	urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC),
1415251538Srpaulo	    maxbasicrate);
1416251538Srpaulo
1417251538Srpaulo	/* Set rates mask for unicast frames. */
1418251538Srpaulo	cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID;
1419251538Srpaulo	cmd.mask = htole32(mode << 28 | rates);
1420251538Srpaulo	error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1421251538Srpaulo	if (error != 0) {
1422252401Srpaulo		ieee80211_free_node(ni);
1423251538Srpaulo		device_printf(sc->sc_dev, "could not add BSS station\n");
1424251538Srpaulo		return (error);
1425251538Srpaulo	}
1426251538Srpaulo	/* Set initial MRR rate. */
1427251538Srpaulo	DPRINTF("maxrate=%d\n", maxrate);
1428251538Srpaulo	urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS),
1429251538Srpaulo	    maxrate);
1430251538Srpaulo
1431251538Srpaulo	/* Indicate highest supported rate. */
1432252403Srpaulo	ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1];
1433252401Srpaulo	ieee80211_free_node(ni);
1434252401Srpaulo
1435251538Srpaulo	return (0);
1436251538Srpaulo}
1437251538Srpaulo
1438251538Srpaulovoid
1439251538Srpaulourtwn_tsf_sync_enable(struct urtwn_softc *sc)
1440251538Srpaulo{
1441251538Srpaulo	struct ifnet *ifp = sc->sc_ifp;
1442251538Srpaulo	struct ieee80211com *ic = ifp->if_l2com;
1443251538Srpaulo	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1444251538Srpaulo	struct ieee80211_node *ni = vap->iv_bss;
1445251538Srpaulo
1446251538Srpaulo	uint64_t tsf;
1447251538Srpaulo
1448251538Srpaulo	/* Enable TSF synchronization. */
1449251538Srpaulo	urtwn_write_1(sc, R92C_BCN_CTRL,
1450251538Srpaulo	    urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0);
1451251538Srpaulo
1452251538Srpaulo	urtwn_write_1(sc, R92C_BCN_CTRL,
1453251538Srpaulo	    urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN);
1454251538Srpaulo
1455251538Srpaulo	/* Set initial TSF. */
1456251538Srpaulo	memcpy(&tsf, ni->ni_tstamp.data, 8);
1457251538Srpaulo	tsf = le64toh(tsf);
1458251538Srpaulo	tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU));
1459251538Srpaulo	tsf -= IEEE80211_DUR_TU;
1460251538Srpaulo	urtwn_write_4(sc, R92C_TSFTR + 0, tsf);
1461251538Srpaulo	urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32);
1462251538Srpaulo
1463251538Srpaulo	urtwn_write_1(sc, R92C_BCN_CTRL,
1464251538Srpaulo	    urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN);
1465251538Srpaulo}
1466251538Srpaulo
1467251538Srpaulostatic void
1468251538Srpaulourtwn_set_led(struct urtwn_softc *sc, int led, int on)
1469251538Srpaulo{
1470251538Srpaulo	uint8_t reg;
1471264912Skevlo
1472251538Srpaulo	if (led == URTWN_LED_LINK) {
1473264912Skevlo		if (sc->chip & URTWN_CHIP_88E) {
1474264912Skevlo			reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;
1475264912Skevlo			urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60);
1476264912Skevlo			if (!on) {
1477264912Skevlo				reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90;
1478264912Skevlo				urtwn_write_1(sc, R92C_LEDCFG2,
1479264912Skevlo				    reg | R92C_LEDCFG0_DIS);
1480264912Skevlo				urtwn_write_1(sc, R92C_MAC_PINMUX_CFG,
1481264912Skevlo				    urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) &
1482264912Skevlo				    0xfe);
1483264912Skevlo			}
1484264912Skevlo		} else {
1485264912Skevlo			reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70;
1486264912Skevlo			if (!on)
1487264912Skevlo				reg |= R92C_LEDCFG0_DIS;
1488264912Skevlo			urtwn_write_1(sc, R92C_LEDCFG0, reg);
1489264912Skevlo		}
1490264912Skevlo		sc->ledlink = on;       /* Save LED state. */
1491251538Srpaulo	}
1492251538Srpaulo}
1493251538Srpaulo
1494251538Srpaulostatic int
1495251538Srpaulourtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1496251538Srpaulo{
1497251538Srpaulo	struct urtwn_vap *uvp = URTWN_VAP(vap);
1498251538Srpaulo	struct ieee80211com *ic = vap->iv_ic;
1499251538Srpaulo	struct urtwn_softc *sc = ic->ic_ifp->if_softc;
1500251538Srpaulo	struct ieee80211_node *ni;
1501251538Srpaulo	enum ieee80211_state ostate;
1502251538Srpaulo	uint32_t reg;
1503251538Srpaulo
1504251538Srpaulo	ostate = vap->iv_state;
1505251538Srpaulo	DPRINTF("%s -> %s\n", ieee80211_state_name[ostate],
1506251538Srpaulo	    ieee80211_state_name[nstate]);
1507251538Srpaulo
1508251538Srpaulo	IEEE80211_UNLOCK(ic);
1509251538Srpaulo	URTWN_LOCK(sc);
1510251538Srpaulo	callout_stop(&sc->sc_watchdog_ch);
1511251538Srpaulo
1512251538Srpaulo	if (ostate == IEEE80211_S_RUN) {
1513251538Srpaulo		/* Turn link LED off. */
1514251538Srpaulo		urtwn_set_led(sc, URTWN_LED_LINK, 0);
1515251538Srpaulo
1516251538Srpaulo		/* Set media status to 'No Link'. */
1517251538Srpaulo		reg = urtwn_read_4(sc, R92C_CR);
1518251538Srpaulo		reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK);
1519251538Srpaulo		urtwn_write_4(sc, R92C_CR, reg);
1520251538Srpaulo
1521251538Srpaulo		/* Stop Rx of data frames. */
1522251538Srpaulo		urtwn_write_2(sc, R92C_RXFLTMAP2, 0);
1523251538Srpaulo
1524251538Srpaulo		/* Rest TSF. */
1525251538Srpaulo		urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03);
1526251538Srpaulo
1527251538Srpaulo		/* Disable TSF synchronization. */
1528251538Srpaulo		urtwn_write_1(sc, R92C_BCN_CTRL,
1529251538Srpaulo		    urtwn_read_1(sc, R92C_BCN_CTRL) |
1530251538Srpaulo		    R92C_BCN_CTRL_DIS_TSF_UDT0);
1531251538Srpaulo
1532251538Srpaulo		/* Reset EDCA parameters. */
1533251538Srpaulo		urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
1534251538Srpaulo		urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317);
1535251538Srpaulo		urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320);
1536251538Srpaulo		urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444);
1537251538Srpaulo	}
1538251538Srpaulo
1539251538Srpaulo	switch (nstate) {
1540251538Srpaulo	case IEEE80211_S_INIT:
1541251538Srpaulo		/* Turn link LED off. */
1542251538Srpaulo		urtwn_set_led(sc, URTWN_LED_LINK, 0);
1543251538Srpaulo		break;
1544251538Srpaulo	case IEEE80211_S_SCAN:
1545251538Srpaulo		if (ostate != IEEE80211_S_SCAN) {
1546251538Srpaulo			/* Allow Rx from any BSSID. */
1547251538Srpaulo			urtwn_write_4(sc, R92C_RCR,
1548251538Srpaulo			    urtwn_read_4(sc, R92C_RCR) &
1549251538Srpaulo			    ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
1550251538Srpaulo
1551251538Srpaulo			/* Set gain for scanning. */
1552251538Srpaulo			reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1553251538Srpaulo			reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1554251538Srpaulo			urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
1555251538Srpaulo
1556264912Skevlo			if (!(sc->chip & URTWN_CHIP_88E)) {
1557264912Skevlo				reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1558264912Skevlo				reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1559264912Skevlo				urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
1560264912Skevlo			}
1561251538Srpaulo		}
1562251538Srpaulo		/* Make link LED blink during scan. */
1563251538Srpaulo		urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink);
1564251538Srpaulo
1565251538Srpaulo		/* Pause AC Tx queues. */
1566251538Srpaulo		urtwn_write_1(sc, R92C_TXPAUSE,
1567251538Srpaulo		    urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f);
1568251538Srpaulo
1569251538Srpaulo		urtwn_set_chan(sc, ic->ic_curchan, NULL);
1570251538Srpaulo		break;
1571251538Srpaulo	case IEEE80211_S_AUTH:
1572251538Srpaulo		/* Set initial gain under link. */
1573251538Srpaulo		reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1574251538Srpaulo		reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
1575251538Srpaulo		urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
1576251538Srpaulo
1577264912Skevlo		if (!(sc->chip & URTWN_CHIP_88E)) {
1578264912Skevlo			reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1579264912Skevlo			reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
1580264912Skevlo			urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
1581264912Skevlo		}
1582251538Srpaulo		urtwn_set_chan(sc, ic->ic_curchan, NULL);
1583251538Srpaulo		break;
1584251538Srpaulo	case IEEE80211_S_RUN:
1585251538Srpaulo		if (vap->iv_opmode == IEEE80211_M_MONITOR) {
1586251538Srpaulo			/* Enable Rx of data frames. */
1587251538Srpaulo			urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
1588251538Srpaulo
1589251538Srpaulo			/* Turn link LED on. */
1590251538Srpaulo			urtwn_set_led(sc, URTWN_LED_LINK, 1);
1591251538Srpaulo			break;
1592251538Srpaulo		}
1593251538Srpaulo
1594251538Srpaulo		ni = ieee80211_ref_node(vap->iv_bss);
1595251538Srpaulo		/* Set media status to 'Associated'. */
1596251538Srpaulo		reg = urtwn_read_4(sc, R92C_CR);
1597251538Srpaulo		reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA);
1598251538Srpaulo		urtwn_write_4(sc, R92C_CR, reg);
1599251538Srpaulo
1600251538Srpaulo		/* Set BSSID. */
1601251538Srpaulo		urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0]));
1602251538Srpaulo		urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4]));
1603251538Srpaulo
1604251538Srpaulo		if (ic->ic_curmode == IEEE80211_MODE_11B)
1605251538Srpaulo			urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0);
1606251538Srpaulo		else	/* 802.11b/g */
1607251538Srpaulo			urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3);
1608251538Srpaulo
1609251538Srpaulo		/* Enable Rx of data frames. */
1610251538Srpaulo		urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
1611251538Srpaulo
1612251538Srpaulo		/* Flush all AC queues. */
1613251538Srpaulo		urtwn_write_1(sc, R92C_TXPAUSE, 0);
1614251538Srpaulo
1615251538Srpaulo		/* Set beacon interval. */
1616251538Srpaulo		urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval);
1617251538Srpaulo
1618251538Srpaulo		/* Allow Rx from our BSSID only. */
1619251538Srpaulo		urtwn_write_4(sc, R92C_RCR,
1620251538Srpaulo		    urtwn_read_4(sc, R92C_RCR) |
1621251538Srpaulo		    R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN);
1622251538Srpaulo
1623251538Srpaulo		/* Enable TSF synchronization. */
1624251538Srpaulo		urtwn_tsf_sync_enable(sc);
1625251538Srpaulo
1626251538Srpaulo		urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10);
1627251538Srpaulo		urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10);
1628251538Srpaulo		urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10);
1629251538Srpaulo		urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10);
1630251538Srpaulo		urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10);
1631251538Srpaulo		urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10);
1632251538Srpaulo
1633251538Srpaulo		/* Intialize rate adaptation. */
1634264912Skevlo		if (sc->chip & URTWN_CHIP_88E)
1635264912Skevlo			ni->ni_txrate =
1636264912Skevlo			    ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1];
1637264912Skevlo		else
1638264912Skevlo			urtwn_ra_init(sc);
1639251538Srpaulo		/* Turn link LED on. */
1640251538Srpaulo		urtwn_set_led(sc, URTWN_LED_LINK, 1);
1641251538Srpaulo
1642251538Srpaulo		sc->avg_pwdb = -1;	/* Reset average RSSI. */
1643251538Srpaulo		/* Reset temperature calibration state machine. */
1644251538Srpaulo		sc->thcal_state = 0;
1645251538Srpaulo		sc->thcal_lctemp = 0;
1646251538Srpaulo		ieee80211_free_node(ni);
1647251538Srpaulo		break;
1648251538Srpaulo	default:
1649251538Srpaulo		break;
1650251538Srpaulo	}
1651251538Srpaulo	URTWN_UNLOCK(sc);
1652251538Srpaulo	IEEE80211_LOCK(ic);
1653251538Srpaulo	return(uvp->newstate(vap, nstate, arg));
1654251538Srpaulo}
1655251538Srpaulo
1656251538Srpaulostatic void
1657251538Srpaulourtwn_watchdog(void *arg)
1658251538Srpaulo{
1659251538Srpaulo	struct urtwn_softc *sc = arg;
1660251538Srpaulo	struct ifnet *ifp = sc->sc_ifp;
1661251538Srpaulo
1662251538Srpaulo	if (sc->sc_txtimer > 0) {
1663251538Srpaulo		if (--sc->sc_txtimer == 0) {
1664251538Srpaulo			device_printf(sc->sc_dev, "device timeout\n");
1665251538Srpaulo			ifp->if_oerrors++;
1666251538Srpaulo			return;
1667251538Srpaulo		}
1668251538Srpaulo		callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
1669251538Srpaulo	}
1670251538Srpaulo}
1671251538Srpaulo
1672251538Srpaulostatic void
1673251538Srpaulourtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi)
1674251538Srpaulo{
1675251538Srpaulo	int pwdb;
1676251538Srpaulo
1677251538Srpaulo	/* Convert antenna signal to percentage. */
1678251538Srpaulo	if (rssi <= -100 || rssi >= 20)
1679251538Srpaulo		pwdb = 0;
1680251538Srpaulo	else if (rssi >= 0)
1681251538Srpaulo		pwdb = 100;
1682251538Srpaulo	else
1683251538Srpaulo		pwdb = 100 + rssi;
1684264912Skevlo	if (!(sc->chip & URTWN_CHIP_88E)) {
1685264912Skevlo		if (rate <= 3) {
1686264912Skevlo			/* CCK gain is smaller than OFDM/MCS gain. */
1687264912Skevlo			pwdb += 6;
1688264912Skevlo			if (pwdb > 100)
1689264912Skevlo				pwdb = 100;
1690264912Skevlo			if (pwdb <= 14)
1691264912Skevlo				pwdb -= 4;
1692264912Skevlo			else if (pwdb <= 26)
1693264912Skevlo				pwdb -= 8;
1694264912Skevlo			else if (pwdb <= 34)
1695264912Skevlo				pwdb -= 6;
1696264912Skevlo			else if (pwdb <= 42)
1697264912Skevlo				pwdb -= 2;
1698264912Skevlo		}
1699251538Srpaulo	}
1700251538Srpaulo	if (sc->avg_pwdb == -1)	/* Init. */
1701251538Srpaulo		sc->avg_pwdb = pwdb;
1702251538Srpaulo	else if (sc->avg_pwdb < pwdb)
1703251538Srpaulo		sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1;
1704251538Srpaulo	else
1705251538Srpaulo		sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20);
1706251538Srpaulo	DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb);
1707251538Srpaulo}
1708251538Srpaulo
1709251538Srpaulostatic int8_t
1710251538Srpaulourtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt)
1711251538Srpaulo{
1712251538Srpaulo	static const int8_t cckoff[] = { 16, -12, -26, -46 };
1713251538Srpaulo	struct r92c_rx_phystat *phy;
1714251538Srpaulo	struct r92c_rx_cck *cck;
1715251538Srpaulo	uint8_t rpt;
1716251538Srpaulo	int8_t rssi;
1717251538Srpaulo
1718251538Srpaulo	if (rate <= 3) {
1719251538Srpaulo		cck = (struct r92c_rx_cck *)physt;
1720251538Srpaulo		if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) {
1721251538Srpaulo			rpt = (cck->agc_rpt >> 5) & 0x3;
1722251538Srpaulo			rssi = (cck->agc_rpt & 0x1f) << 1;
1723251538Srpaulo		} else {
1724251538Srpaulo			rpt = (cck->agc_rpt >> 6) & 0x3;
1725251538Srpaulo			rssi = cck->agc_rpt & 0x3e;
1726251538Srpaulo		}
1727251538Srpaulo		rssi = cckoff[rpt] - rssi;
1728251538Srpaulo	} else {	/* OFDM/HT. */
1729251538Srpaulo		phy = (struct r92c_rx_phystat *)physt;
1730251538Srpaulo		rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
1731251538Srpaulo	}
1732251538Srpaulo	return (rssi);
1733251538Srpaulo}
1734251538Srpaulo
1735264912Skevlostatic int8_t
1736264912Skevlourtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt)
1737264912Skevlo{
1738264912Skevlo	struct r92c_rx_phystat *phy;
1739264912Skevlo	struct r88e_rx_cck *cck;
1740264912Skevlo	uint8_t cck_agc_rpt, lna_idx, vga_idx;
1741264912Skevlo	int8_t rssi;
1742264912Skevlo
1743264972Skevlo	rssi = 0;
1744264912Skevlo	if (rate <= 3) {
1745264912Skevlo		cck = (struct r88e_rx_cck *)physt;
1746264912Skevlo		cck_agc_rpt = cck->agc_rpt;
1747264912Skevlo		lna_idx = (cck_agc_rpt & 0xe0) >> 5;
1748264912Skevlo		vga_idx = cck_agc_rpt & 0x1f;
1749264912Skevlo		switch (lna_idx) {
1750264912Skevlo		case 7:
1751264912Skevlo			if (vga_idx <= 27)
1752264912Skevlo				rssi = -100 + 2* (27 - vga_idx);
1753264912Skevlo			else
1754264912Skevlo				rssi = -100;
1755264912Skevlo			break;
1756264912Skevlo		case 6:
1757264912Skevlo			rssi = -48 + 2 * (2 - vga_idx);
1758264912Skevlo			break;
1759264912Skevlo		case 5:
1760264912Skevlo			rssi = -42 + 2 * (7 - vga_idx);
1761264912Skevlo			break;
1762264912Skevlo		case 4:
1763264912Skevlo			rssi = -36 + 2 * (7 - vga_idx);
1764264912Skevlo			break;
1765264912Skevlo		case 3:
1766264912Skevlo			rssi = -24 + 2 * (7 - vga_idx);
1767264912Skevlo			break;
1768264912Skevlo		case 2:
1769264912Skevlo			rssi = -12 + 2 * (5 - vga_idx);
1770264912Skevlo			break;
1771264912Skevlo		case 1:
1772264912Skevlo			rssi = 8 - (2 * vga_idx);
1773264912Skevlo			break;
1774264912Skevlo		case 0:
1775264912Skevlo			rssi = 14 - (2 * vga_idx);
1776264912Skevlo			break;
1777264912Skevlo		}
1778264912Skevlo		rssi += 6;
1779264912Skevlo	} else {	/* OFDM/HT. */
1780264912Skevlo		phy = (struct r92c_rx_phystat *)physt;
1781264912Skevlo		rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
1782264912Skevlo	}
1783264912Skevlo	return (rssi);
1784264912Skevlo}
1785264912Skevlo
1786264912Skevlo
1787251538Srpaulostatic int
1788251538Srpaulourtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni,
1789251538Srpaulo    struct mbuf *m0, struct urtwn_data *data)
1790251538Srpaulo{
1791251538Srpaulo	struct ifnet *ifp = sc->sc_ifp;
1792251538Srpaulo	struct ieee80211_frame *wh;
1793251538Srpaulo	struct ieee80211_key *k;
1794251538Srpaulo	struct ieee80211com *ic = ifp->if_l2com;
1795251538Srpaulo	struct ieee80211vap *vap = ni->ni_vap;
1796251538Srpaulo	struct usb_xfer *xfer;
1797251538Srpaulo	struct r92c_tx_desc *txd;
1798251538Srpaulo	uint8_t raid, type;
1799251538Srpaulo	uint16_t sum;
1800251538Srpaulo	int i, hasqos, xferlen;
1801251538Srpaulo	struct usb_xfer *urtwn_pipes[4] = {
1802251538Srpaulo		sc->sc_xfer[URTWN_BULK_TX_BE],
1803251538Srpaulo		sc->sc_xfer[URTWN_BULK_TX_BK],
1804251538Srpaulo		sc->sc_xfer[URTWN_BULK_TX_VI],
1805251538Srpaulo		sc->sc_xfer[URTWN_BULK_TX_VO]
1806251538Srpaulo	};
1807251538Srpaulo
1808251538Srpaulo	URTWN_ASSERT_LOCKED(sc);
1809251538Srpaulo
1810251538Srpaulo	/*
1811251538Srpaulo	 * Software crypto.
1812251538Srpaulo	 */
1813251538Srpaulo	wh = mtod(m0, struct ieee80211_frame *);
1814264912Skevlo	type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1815264912Skevlo
1816260444Skevlo	if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1817251538Srpaulo		k = ieee80211_crypto_encap(ni, m0);
1818251538Srpaulo		if (k == NULL) {
1819251538Srpaulo			device_printf(sc->sc_dev,
1820251538Srpaulo			    "ieee80211_crypto_encap returns NULL.\n");
1821251538Srpaulo			/* XXX we don't expect the fragmented frames */
1822251538Srpaulo			m_freem(m0);
1823251538Srpaulo			return (ENOBUFS);
1824251538Srpaulo		}
1825251538Srpaulo
1826251538Srpaulo		/* in case packet header moved, reset pointer */
1827251538Srpaulo		wh = mtod(m0, struct ieee80211_frame *);
1828251538Srpaulo	}
1829251538Srpaulo
1830264912Skevlo	switch (type) {
1831251538Srpaulo	case IEEE80211_FC0_TYPE_CTL:
1832251538Srpaulo	case IEEE80211_FC0_TYPE_MGT:
1833251538Srpaulo		xfer = sc->sc_xfer[URTWN_BULK_TX_VO];
1834251538Srpaulo		break;
1835251538Srpaulo	default:
1836251538Srpaulo		KASSERT(M_WME_GETAC(m0) < 4,
1837251538Srpaulo		    ("unsupported WME pipe %d", M_WME_GETAC(m0)));
1838251538Srpaulo		xfer = urtwn_pipes[M_WME_GETAC(m0)];
1839251538Srpaulo		break;
1840251538Srpaulo	}
1841251538Srpaulo
1842251538Srpaulo	hasqos = 0;
1843251538Srpaulo
1844251538Srpaulo	/* Fill Tx descriptor. */
1845251538Srpaulo	txd = (struct r92c_tx_desc *)data->buf;
1846251538Srpaulo	memset(txd, 0, sizeof(*txd));
1847251538Srpaulo
1848251538Srpaulo	txd->txdw0 |= htole32(
1849251538Srpaulo	    SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) |
1850251538Srpaulo	    SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
1851251538Srpaulo	    R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG);
1852251538Srpaulo	if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1853251538Srpaulo		txd->txdw0 |= htole32(R92C_TXDW0_BMCAST);
1854251538Srpaulo	if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1855251538Srpaulo	    type == IEEE80211_FC0_TYPE_DATA) {
1856251538Srpaulo		if (ic->ic_curmode == IEEE80211_MODE_11B)
1857251538Srpaulo			raid = R92C_RAID_11B;
1858251538Srpaulo		else
1859251538Srpaulo			raid = R92C_RAID_11BG;
1860264912Skevlo		if (sc->chip & URTWN_CHIP_88E) {
1861264912Skevlo			txd->txdw1 |= htole32(
1862264912Skevlo			    SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) |
1863264912Skevlo			    SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
1864264912Skevlo			    SM(R92C_TXDW1_RAID, raid));
1865264912Skevlo			txd->txdw2 |= htole32(R88E_TXDW2_AGGBK);
1866264912Skevlo		} else {
1867264912Skevlo			txd->txdw1 |= htole32(
1868264912Skevlo			    SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) |
1869264912Skevlo			    SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
1870264912Skevlo		 	    SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK);
1871264912Skevlo		}
1872251538Srpaulo		if (ic->ic_flags & IEEE80211_F_USEPROT) {
1873251538Srpaulo			if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
1874251538Srpaulo				txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF |
1875251538Srpaulo				    R92C_TXDW4_HWRTSEN);
1876251538Srpaulo			} else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
1877251538Srpaulo				txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |
1878251538Srpaulo				    R92C_TXDW4_HWRTSEN);
1879251538Srpaulo			}
1880251538Srpaulo		}
1881251538Srpaulo		/* Send RTS at OFDM24. */
1882251538Srpaulo		txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8));
1883251538Srpaulo		txd->txdw5 |= htole32(0x0001ff00);
1884251538Srpaulo		/* Send data at OFDM54. */
1885264912Skevlo		if (sc->chip & URTWN_CHIP_88E)
1886264912Skevlo			txd->txdw5 |= htole32(0x13 & 0x3f);
1887264912Skevlo		else
1888264912Skevlo			txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11));
1889251538Srpaulo	} else {
1890251538Srpaulo		txd->txdw1 |= htole32(
1891251538Srpaulo		    SM(R92C_TXDW1_MACID, 0) |
1892251538Srpaulo		    SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) |
1893251538Srpaulo		    SM(R92C_TXDW1_RAID, R92C_RAID_11B));
1894251538Srpaulo
1895251538Srpaulo		/* Force CCK1. */
1896251538Srpaulo		txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
1897251538Srpaulo		txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0));
1898251538Srpaulo	}
1899251538Srpaulo	/* Set sequence number (already little endian). */
1900251538Srpaulo	txd->txdseq |= *(uint16_t *)wh->i_seq;
1901251538Srpaulo
1902251538Srpaulo	if (!hasqos) {
1903251538Srpaulo		/* Use HW sequence numbering for non-QoS frames. */
1904251538Srpaulo		txd->txdw4  |= htole32(R92C_TXDW4_HWSEQ);
1905251538Srpaulo		txd->txdseq |= htole16(0x8000);
1906251538Srpaulo	} else
1907251538Srpaulo		txd->txdw4 |= htole32(R92C_TXDW4_QOS);
1908251538Srpaulo
1909251538Srpaulo	/* Compute Tx descriptor checksum. */
1910251538Srpaulo	sum = 0;
1911251538Srpaulo	for (i = 0; i < sizeof(*txd) / 2; i++)
1912251538Srpaulo		sum ^= ((uint16_t *)txd)[i];
1913251538Srpaulo	txd->txdsum = sum; 	/* NB: already little endian. */
1914251538Srpaulo
1915251538Srpaulo	if (ieee80211_radiotap_active_vap(vap)) {
1916251538Srpaulo		struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap;
1917251538Srpaulo
1918251538Srpaulo		tap->wt_flags = 0;
1919251538Srpaulo		tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1920251538Srpaulo		tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1921251538Srpaulo		ieee80211_radiotap_tx(vap, m0);
1922251538Srpaulo	}
1923251538Srpaulo
1924251538Srpaulo	xferlen = sizeof(*txd) + m0->m_pkthdr.len;
1925251538Srpaulo	m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]);
1926251538Srpaulo
1927251538Srpaulo	data->buflen = xferlen;
1928251538Srpaulo	data->ni = ni;
1929251538Srpaulo	data->m = m0;
1930251538Srpaulo
1931251538Srpaulo	STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
1932251538Srpaulo	usbd_transfer_start(xfer);
1933251538Srpaulo	return (0);
1934251538Srpaulo}
1935251538Srpaulo
1936251538Srpaulostatic void
1937251538Srpaulourtwn_start(struct ifnet *ifp)
1938251538Srpaulo{
1939251538Srpaulo	struct urtwn_softc *sc = ifp->if_softc;
1940261863Srpaulo
1941261863Srpaulo	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1942261863Srpaulo		return;
1943261863Srpaulo	URTWN_LOCK(sc);
1944261863Srpaulo	urtwn_start_locked(ifp, sc);
1945261863Srpaulo	URTWN_UNLOCK(sc);
1946261863Srpaulo}
1947261863Srpaulo
1948261863Srpaulostatic void
1949261863Srpaulourtwn_start_locked(struct ifnet *ifp, struct urtwn_softc *sc)
1950261863Srpaulo{
1951251538Srpaulo	struct ieee80211_node *ni;
1952251538Srpaulo	struct mbuf *m;
1953251538Srpaulo	struct urtwn_data *bf;
1954251538Srpaulo
1955261863Srpaulo	URTWN_ASSERT_LOCKED(sc);
1956251538Srpaulo	for (;;) {
1957251538Srpaulo		IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1958251538Srpaulo		if (m == NULL)
1959251538Srpaulo			break;
1960251538Srpaulo		bf = urtwn_getbuf(sc);
1961251538Srpaulo		if (bf == NULL) {
1962251538Srpaulo			IFQ_DRV_PREPEND(&ifp->if_snd, m);
1963251538Srpaulo			break;
1964251538Srpaulo		}
1965251538Srpaulo		ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1966251538Srpaulo		m->m_pkthdr.rcvif = NULL;
1967251538Srpaulo
1968251538Srpaulo		if (urtwn_tx_start(sc, ni, m, bf) != 0) {
1969251538Srpaulo			ifp->if_oerrors++;
1970251538Srpaulo			STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1971251538Srpaulo			ieee80211_free_node(ni);
1972251538Srpaulo			break;
1973251538Srpaulo		}
1974251538Srpaulo
1975251538Srpaulo		sc->sc_txtimer = 5;
1976251538Srpaulo		callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
1977251538Srpaulo	}
1978251538Srpaulo}
1979251538Srpaulo
1980251538Srpaulostatic int
1981251538Srpaulourtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1982251538Srpaulo{
1983263153Skevlo	struct urtwn_softc *sc = ifp->if_softc;
1984251538Srpaulo	struct ieee80211com *ic = ifp->if_l2com;
1985251538Srpaulo	struct ifreq *ifr = (struct ifreq *) data;
1986251538Srpaulo	int error = 0, startall = 0;
1987251538Srpaulo
1988263153Skevlo	URTWN_LOCK(sc);
1989263153Skevlo	error = (sc->sc_flags & URTWN_DETACHED) ? ENXIO : 0;
1990263153Skevlo	URTWN_UNLOCK(sc);
1991263153Skevlo	if (error != 0)
1992263153Skevlo		return (error);
1993263153Skevlo
1994251538Srpaulo	switch (cmd) {
1995251538Srpaulo	case SIOCSIFFLAGS:
1996251538Srpaulo		if (ifp->if_flags & IFF_UP) {
1997251538Srpaulo			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1998251538Srpaulo				urtwn_init(ifp->if_softc);
1999251538Srpaulo				startall = 1;
2000251538Srpaulo			}
2001251538Srpaulo		} else {
2002251538Srpaulo			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2003263153Skevlo				urtwn_stop(ifp);
2004251538Srpaulo		}
2005251538Srpaulo		if (startall)
2006251538Srpaulo			ieee80211_start_all(ic);
2007251538Srpaulo		break;
2008251538Srpaulo	case SIOCGIFMEDIA:
2009251538Srpaulo		error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
2010251538Srpaulo		break;
2011251538Srpaulo	case SIOCGIFADDR:
2012251538Srpaulo		error = ether_ioctl(ifp, cmd, data);
2013251538Srpaulo		break;
2014251538Srpaulo	default:
2015251538Srpaulo		error = EINVAL;
2016251538Srpaulo		break;
2017251538Srpaulo	}
2018251538Srpaulo	return (error);
2019251538Srpaulo}
2020251538Srpaulo
2021251538Srpaulostatic int
2022251538Srpaulourtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[],
2023251538Srpaulo    int ndata, int maxsz)
2024251538Srpaulo{
2025251538Srpaulo	int i, error;
2026251538Srpaulo
2027251538Srpaulo	for (i = 0; i < ndata; i++) {
2028251538Srpaulo		struct urtwn_data *dp = &data[i];
2029251538Srpaulo		dp->sc = sc;
2030251538Srpaulo		dp->m = NULL;
2031251538Srpaulo		dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT);
2032251538Srpaulo		if (dp->buf == NULL) {
2033251538Srpaulo			device_printf(sc->sc_dev,
2034251538Srpaulo			    "could not allocate buffer\n");
2035251538Srpaulo			error = ENOMEM;
2036251538Srpaulo			goto fail;
2037251538Srpaulo		}
2038251538Srpaulo		dp->ni = NULL;
2039251538Srpaulo	}
2040251538Srpaulo
2041251538Srpaulo	return (0);
2042251538Srpaulofail:
2043251538Srpaulo	urtwn_free_list(sc, data, ndata);
2044251538Srpaulo	return (error);
2045251538Srpaulo}
2046251538Srpaulo
2047251538Srpaulostatic int
2048251538Srpaulourtwn_alloc_rx_list(struct urtwn_softc *sc)
2049251538Srpaulo{
2050251538Srpaulo        int error, i;
2051251538Srpaulo
2052251538Srpaulo	error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT,
2053251538Srpaulo	    URTWN_RXBUFSZ);
2054251538Srpaulo	if (error != 0)
2055251538Srpaulo		return (error);
2056251538Srpaulo
2057251538Srpaulo	STAILQ_INIT(&sc->sc_rx_active);
2058251538Srpaulo	STAILQ_INIT(&sc->sc_rx_inactive);
2059251538Srpaulo
2060251538Srpaulo	for (i = 0; i < URTWN_RX_LIST_COUNT; i++)
2061251538Srpaulo		STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next);
2062251538Srpaulo
2063251538Srpaulo	return (0);
2064251538Srpaulo}
2065251538Srpaulo
2066251538Srpaulostatic int
2067251538Srpaulourtwn_alloc_tx_list(struct urtwn_softc *sc)
2068251538Srpaulo{
2069251538Srpaulo	int error, i;
2070251538Srpaulo
2071251538Srpaulo	error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT,
2072251538Srpaulo	    URTWN_TXBUFSZ);
2073251538Srpaulo	if (error != 0)
2074251538Srpaulo		return (error);
2075251538Srpaulo
2076251538Srpaulo	STAILQ_INIT(&sc->sc_tx_active);
2077251538Srpaulo	STAILQ_INIT(&sc->sc_tx_inactive);
2078251538Srpaulo	STAILQ_INIT(&sc->sc_tx_pending);
2079251538Srpaulo
2080251538Srpaulo	for (i = 0; i < URTWN_TX_LIST_COUNT; i++)
2081251538Srpaulo		STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next);
2082251538Srpaulo
2083251538Srpaulo	return (0);
2084251538Srpaulo}
2085251538Srpaulo
2086264912Skevlostatic __inline int
2087251538Srpaulourtwn_power_on(struct urtwn_softc *sc)
2088251538Srpaulo{
2089264912Skevlo
2090264912Skevlo	return sc->sc_power_on(sc);
2091264912Skevlo}
2092264912Skevlo
2093264912Skevlostatic int
2094264912Skevlourtwn_r92c_power_on(struct urtwn_softc *sc)
2095264912Skevlo{
2096251538Srpaulo	uint32_t reg;
2097251538Srpaulo	int ntries;
2098251538Srpaulo
2099251538Srpaulo	/* Wait for autoload done bit. */
2100251538Srpaulo	for (ntries = 0; ntries < 1000; ntries++) {
2101251538Srpaulo		if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
2102251538Srpaulo			break;
2103266472Shselasky		urtwn_ms_delay(sc);
2104251538Srpaulo	}
2105251538Srpaulo	if (ntries == 1000) {
2106251538Srpaulo		device_printf(sc->sc_dev,
2107251538Srpaulo		    "timeout waiting for chip autoload\n");
2108251538Srpaulo		return (ETIMEDOUT);
2109251538Srpaulo	}
2110251538Srpaulo
2111251538Srpaulo	/* Unlock ISO/CLK/Power control register. */
2112251538Srpaulo	urtwn_write_1(sc, R92C_RSV_CTRL, 0);
2113251538Srpaulo	/* Move SPS into PWM mode. */
2114251538Srpaulo	urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
2115266472Shselasky	urtwn_ms_delay(sc);
2116251538Srpaulo
2117251538Srpaulo	reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL);
2118251538Srpaulo	if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {
2119251538Srpaulo		urtwn_write_1(sc, R92C_LDOV12D_CTRL,
2120251538Srpaulo		    reg | R92C_LDOV12D_CTRL_LDV12_EN);
2121266472Shselasky		urtwn_ms_delay(sc);
2122251538Srpaulo		urtwn_write_1(sc, R92C_SYS_ISO_CTRL,
2123251538Srpaulo		    urtwn_read_1(sc, R92C_SYS_ISO_CTRL) &
2124251538Srpaulo		    ~R92C_SYS_ISO_CTRL_MD2PP);
2125251538Srpaulo	}
2126251538Srpaulo
2127251538Srpaulo	/* Auto enable WLAN. */
2128251538Srpaulo	urtwn_write_2(sc, R92C_APS_FSMCO,
2129251538Srpaulo	    urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
2130251538Srpaulo	for (ntries = 0; ntries < 1000; ntries++) {
2131262822Skevlo		if (!(urtwn_read_2(sc, R92C_APS_FSMCO) &
2132262822Skevlo		    R92C_APS_FSMCO_APFM_ONMAC))
2133251538Srpaulo			break;
2134266472Shselasky		urtwn_ms_delay(sc);
2135251538Srpaulo	}
2136251538Srpaulo	if (ntries == 1000) {
2137251538Srpaulo		device_printf(sc->sc_dev,
2138251538Srpaulo		    "timeout waiting for MAC auto ON\n");
2139251538Srpaulo		return (ETIMEDOUT);
2140251538Srpaulo	}
2141251538Srpaulo
2142251538Srpaulo	/* Enable radio, GPIO and LED functions. */
2143251538Srpaulo	urtwn_write_2(sc, R92C_APS_FSMCO,
2144251538Srpaulo	    R92C_APS_FSMCO_AFSM_HSUS |
2145251538Srpaulo	    R92C_APS_FSMCO_PDN_EN |
2146251538Srpaulo	    R92C_APS_FSMCO_PFM_ALDN);
2147251538Srpaulo	/* Release RF digital isolation. */
2148251538Srpaulo	urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
2149251538Srpaulo	    urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR);
2150251538Srpaulo
2151251538Srpaulo	/* Initialize MAC. */
2152251538Srpaulo	urtwn_write_1(sc, R92C_APSD_CTRL,
2153251538Srpaulo	    urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF);
2154251538Srpaulo	for (ntries = 0; ntries < 200; ntries++) {
2155251538Srpaulo		if (!(urtwn_read_1(sc, R92C_APSD_CTRL) &
2156251538Srpaulo		    R92C_APSD_CTRL_OFF_STATUS))
2157251538Srpaulo			break;
2158266472Shselasky		urtwn_ms_delay(sc);
2159251538Srpaulo	}
2160251538Srpaulo	if (ntries == 200) {
2161251538Srpaulo		device_printf(sc->sc_dev,
2162251538Srpaulo		    "timeout waiting for MAC initialization\n");
2163251538Srpaulo		return (ETIMEDOUT);
2164251538Srpaulo	}
2165251538Srpaulo
2166251538Srpaulo	/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
2167251538Srpaulo	reg = urtwn_read_2(sc, R92C_CR);
2168251538Srpaulo	reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
2169251538Srpaulo	    R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
2170251538Srpaulo	    R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
2171251538Srpaulo	    R92C_CR_ENSEC;
2172251538Srpaulo	urtwn_write_2(sc, R92C_CR, reg);
2173251538Srpaulo
2174251538Srpaulo	urtwn_write_1(sc, 0xfe10, 0x19);
2175251538Srpaulo	return (0);
2176251538Srpaulo}
2177251538Srpaulo
2178251538Srpaulostatic int
2179264912Skevlourtwn_r88e_power_on(struct urtwn_softc *sc)
2180264912Skevlo{
2181264912Skevlo	uint8_t val;
2182264912Skevlo	uint32_t reg;
2183264912Skevlo	int ntries;
2184264912Skevlo
2185264912Skevlo	/* Wait for power ready bit. */
2186264912Skevlo	for (ntries = 0; ntries < 5000; ntries++) {
2187264912Skevlo		val = urtwn_read_1(sc, 0x6) & 0x2;
2188264912Skevlo		if (val == 0x2)
2189264912Skevlo			break;
2190266472Shselasky		urtwn_ms_delay(sc);
2191264912Skevlo	}
2192264912Skevlo	if (ntries == 5000) {
2193264912Skevlo		device_printf(sc->sc_dev,
2194264912Skevlo		    "timeout waiting for chip power up\n");
2195264912Skevlo		return (ETIMEDOUT);
2196264912Skevlo	}
2197264912Skevlo
2198264912Skevlo	/* Reset BB. */
2199264912Skevlo	urtwn_write_1(sc, R92C_SYS_FUNC_EN,
2200264912Skevlo	    urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB |
2201264912Skevlo	    R92C_SYS_FUNC_EN_BB_GLB_RST));
2202264912Skevlo
2203264912Skevlo	urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80);
2204264912Skevlo
2205264912Skevlo	/* Disable HWPDN. */
2206264912Skevlo	urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80);
2207264912Skevlo
2208264912Skevlo	/* Disable WL suspend. */
2209264912Skevlo	urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18);
2210264912Skevlo
2211264912Skevlo	urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1);
2212264912Skevlo	for (ntries = 0; ntries < 5000; ntries++) {
2213264912Skevlo		if (!(urtwn_read_1(sc, 0x5) & 0x1))
2214264912Skevlo			break;
2215266472Shselasky		urtwn_ms_delay(sc);
2216264912Skevlo	}
2217264912Skevlo	if (ntries == 5000)
2218264912Skevlo		return (ETIMEDOUT);
2219264912Skevlo
2220264912Skevlo	/* Enable LDO normal mode. */
2221264912Skevlo	urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10);
2222264912Skevlo
2223264912Skevlo	/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
2224264912Skevlo	urtwn_write_2(sc, R92C_CR, 0);
2225264912Skevlo	reg = urtwn_read_2(sc, R92C_CR);
2226264912Skevlo	reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
2227264912Skevlo	    R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
2228264912Skevlo	    R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN;
2229264912Skevlo	urtwn_write_2(sc, R92C_CR, reg);
2230264912Skevlo
2231264912Skevlo	return (0);
2232264912Skevlo}
2233264912Skevlo
2234264912Skevlostatic int
2235251538Srpaulourtwn_llt_init(struct urtwn_softc *sc)
2236251538Srpaulo{
2237264912Skevlo	int i, error, page_count, pktbuf_count;
2238251538Srpaulo
2239264912Skevlo	page_count = (sc->chip & URTWN_CHIP_88E) ?
2240264912Skevlo	    R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT;
2241264912Skevlo	pktbuf_count = (sc->chip & URTWN_CHIP_88E) ?
2242264912Skevlo	    R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT;
2243264912Skevlo
2244264912Skevlo	/* Reserve pages [0; page_count]. */
2245264912Skevlo	for (i = 0; i < page_count; i++) {
2246251538Srpaulo		if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
2247251538Srpaulo			return (error);
2248251538Srpaulo	}
2249251538Srpaulo	/* NB: 0xff indicates end-of-list. */
2250251538Srpaulo	if ((error = urtwn_llt_write(sc, i, 0xff)) != 0)
2251251538Srpaulo		return (error);
2252251538Srpaulo	/*
2253264912Skevlo	 * Use pages [page_count + 1; pktbuf_count - 1]
2254251538Srpaulo	 * as ring buffer.
2255251538Srpaulo	 */
2256264912Skevlo	for (++i; i < pktbuf_count - 1; i++) {
2257251538Srpaulo		if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
2258251538Srpaulo			return (error);
2259251538Srpaulo	}
2260251538Srpaulo	/* Make the last page point to the beginning of the ring buffer. */
2261264912Skevlo	error = urtwn_llt_write(sc, i, page_count + 1);
2262251538Srpaulo	return (error);
2263251538Srpaulo}
2264251538Srpaulo
2265251538Srpaulostatic void
2266251538Srpaulourtwn_fw_reset(struct urtwn_softc *sc)
2267251538Srpaulo{
2268251538Srpaulo	uint16_t reg;
2269251538Srpaulo	int ntries;
2270251538Srpaulo
2271251538Srpaulo	/* Tell 8051 to reset itself. */
2272251538Srpaulo	urtwn_write_1(sc, R92C_HMETFR + 3, 0x20);
2273251538Srpaulo
2274251538Srpaulo	/* Wait until 8051 resets by itself. */
2275251538Srpaulo	for (ntries = 0; ntries < 100; ntries++) {
2276251538Srpaulo		reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
2277251538Srpaulo		if (!(reg & R92C_SYS_FUNC_EN_CPUEN))
2278251538Srpaulo			return;
2279266472Shselasky		urtwn_ms_delay(sc);
2280251538Srpaulo	}
2281251538Srpaulo	/* Force 8051 reset. */
2282251538Srpaulo	urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
2283264912Skevlo	urtwn_write_2(sc, R92C_SYS_FUNC_EN,
2284264912Skevlo	    urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
2285264912Skevlo	    R92C_SYS_FUNC_EN_CPUEN);
2286251538Srpaulo}
2287251538Srpaulo
2288264912Skevlostatic void
2289264912Skevlourtwn_r88e_fw_reset(struct urtwn_softc *sc)
2290264912Skevlo{
2291264912Skevlo	uint16_t reg;
2292264912Skevlo
2293264912Skevlo	reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
2294264912Skevlo	urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
2295264912Skevlo	urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN);
2296264912Skevlo}
2297264912Skevlo
2298251538Srpaulostatic int
2299251538Srpaulourtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len)
2300251538Srpaulo{
2301251538Srpaulo	uint32_t reg;
2302251538Srpaulo	int off, mlen, error = 0;
2303251538Srpaulo
2304251538Srpaulo	reg = urtwn_read_4(sc, R92C_MCUFWDL);
2305251538Srpaulo	reg = RW(reg, R92C_MCUFWDL_PAGE, page);
2306251538Srpaulo	urtwn_write_4(sc, R92C_MCUFWDL, reg);
2307251538Srpaulo
2308251538Srpaulo	off = R92C_FW_START_ADDR;
2309251538Srpaulo	while (len > 0) {
2310251538Srpaulo		if (len > 196)
2311251538Srpaulo			mlen = 196;
2312251538Srpaulo		else if (len > 4)
2313251538Srpaulo			mlen = 4;
2314251538Srpaulo		else
2315251538Srpaulo			mlen = 1;
2316251538Srpaulo		/* XXX fix this deconst */
2317251538Srpaulo		error = urtwn_write_region_1(sc, off,
2318251538Srpaulo		    __DECONST(uint8_t *, buf), mlen);
2319251538Srpaulo		if (error != 0)
2320251538Srpaulo			break;
2321251538Srpaulo		off += mlen;
2322251538Srpaulo		buf += mlen;
2323251538Srpaulo		len -= mlen;
2324251538Srpaulo	}
2325251538Srpaulo	return (error);
2326251538Srpaulo}
2327251538Srpaulo
2328251538Srpaulostatic int
2329251538Srpaulourtwn_load_firmware(struct urtwn_softc *sc)
2330251538Srpaulo{
2331251538Srpaulo	const struct firmware *fw;
2332251538Srpaulo	const struct r92c_fw_hdr *hdr;
2333251538Srpaulo	const char *imagename;
2334251538Srpaulo	const u_char *ptr;
2335251538Srpaulo	size_t len;
2336251538Srpaulo	uint32_t reg;
2337251538Srpaulo	int mlen, ntries, page, error;
2338251538Srpaulo
2339264864Skevlo	URTWN_UNLOCK(sc);
2340251538Srpaulo	/* Read firmware image from the filesystem. */
2341264912Skevlo	if (sc->chip & URTWN_CHIP_88E)
2342264912Skevlo		imagename = "urtwn-rtl8188eufw";
2343264912Skevlo	else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
2344264912Skevlo		    URTWN_CHIP_UMC_A_CUT)
2345251538Srpaulo		imagename = "urtwn-rtl8192cfwU";
2346251538Srpaulo	else
2347251538Srpaulo		imagename = "urtwn-rtl8192cfwT";
2348251538Srpaulo
2349251538Srpaulo	fw = firmware_get(imagename);
2350264864Skevlo	URTWN_LOCK(sc);
2351251538Srpaulo	if (fw == NULL) {
2352251538Srpaulo		device_printf(sc->sc_dev,
2353251538Srpaulo		    "failed loadfirmware of file %s\n", imagename);
2354251538Srpaulo		return (ENOENT);
2355251538Srpaulo	}
2356251538Srpaulo
2357251538Srpaulo	len = fw->datasize;
2358251538Srpaulo
2359251538Srpaulo	if (len < sizeof(*hdr)) {
2360251538Srpaulo		device_printf(sc->sc_dev, "firmware too short\n");
2361251538Srpaulo		error = EINVAL;
2362251538Srpaulo		goto fail;
2363251538Srpaulo	}
2364251538Srpaulo	ptr = fw->data;
2365251538Srpaulo	hdr = (const struct r92c_fw_hdr *)ptr;
2366251538Srpaulo	/* Check if there is a valid FW header and skip it. */
2367251538Srpaulo	if ((le16toh(hdr->signature) >> 4) == 0x88c ||
2368264912Skevlo	    (le16toh(hdr->signature) >> 4) == 0x88e ||
2369251538Srpaulo	    (le16toh(hdr->signature) >> 4) == 0x92c) {
2370251538Srpaulo		DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n",
2371251538Srpaulo		    le16toh(hdr->version), le16toh(hdr->subversion),
2372251538Srpaulo		    hdr->month, hdr->date, hdr->hour, hdr->minute);
2373251538Srpaulo		ptr += sizeof(*hdr);
2374251538Srpaulo		len -= sizeof(*hdr);
2375251538Srpaulo	}
2376251538Srpaulo
2377264912Skevlo	if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) {
2378264912Skevlo		if (sc->chip & URTWN_CHIP_88E)
2379264912Skevlo			urtwn_r88e_fw_reset(sc);
2380264912Skevlo		else
2381264912Skevlo			urtwn_fw_reset(sc);
2382251538Srpaulo		urtwn_write_1(sc, R92C_MCUFWDL, 0);
2383251538Srpaulo	}
2384264912Skevlo
2385251538Srpaulo	urtwn_write_1(sc, R92C_MCUFWDL,
2386251538Srpaulo	    urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN);
2387251538Srpaulo	urtwn_write_1(sc, R92C_MCUFWDL + 2,
2388251538Srpaulo	    urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08);
2389251538Srpaulo
2390263154Skevlo	/* Reset the FWDL checksum. */
2391263154Skevlo	urtwn_write_1(sc, R92C_MCUFWDL,
2392263154Skevlo	    urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT);
2393263154Skevlo
2394251538Srpaulo	for (page = 0; len > 0; page++) {
2395251538Srpaulo		mlen = min(len, R92C_FW_PAGE_SIZE);
2396251538Srpaulo		error = urtwn_fw_loadpage(sc, page, ptr, mlen);
2397251538Srpaulo		if (error != 0) {
2398251538Srpaulo			device_printf(sc->sc_dev,
2399251538Srpaulo			    "could not load firmware page\n");
2400251538Srpaulo			goto fail;
2401251538Srpaulo		}
2402251538Srpaulo		ptr += mlen;
2403251538Srpaulo		len -= mlen;
2404251538Srpaulo	}
2405251538Srpaulo	urtwn_write_1(sc, R92C_MCUFWDL,
2406251538Srpaulo	    urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN);
2407251538Srpaulo	urtwn_write_1(sc, R92C_MCUFWDL + 1, 0);
2408251538Srpaulo
2409251538Srpaulo	/* Wait for checksum report. */
2410251538Srpaulo	for (ntries = 0; ntries < 1000; ntries++) {
2411251538Srpaulo		if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
2412251538Srpaulo			break;
2413266472Shselasky		urtwn_ms_delay(sc);
2414251538Srpaulo	}
2415251538Srpaulo	if (ntries == 1000) {
2416251538Srpaulo		device_printf(sc->sc_dev,
2417251538Srpaulo		    "timeout waiting for checksum report\n");
2418251538Srpaulo		error = ETIMEDOUT;
2419251538Srpaulo		goto fail;
2420251538Srpaulo	}
2421251538Srpaulo
2422251538Srpaulo	reg = urtwn_read_4(sc, R92C_MCUFWDL);
2423251538Srpaulo	reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY;
2424251538Srpaulo	urtwn_write_4(sc, R92C_MCUFWDL, reg);
2425264912Skevlo	if (sc->chip & URTWN_CHIP_88E)
2426264912Skevlo		urtwn_r88e_fw_reset(sc);
2427251538Srpaulo	/* Wait for firmware readiness. */
2428251538Srpaulo	for (ntries = 0; ntries < 1000; ntries++) {
2429251538Srpaulo		if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
2430251538Srpaulo			break;
2431266472Shselasky		urtwn_ms_delay(sc);
2432251538Srpaulo	}
2433251538Srpaulo	if (ntries == 1000) {
2434251538Srpaulo		device_printf(sc->sc_dev,
2435251538Srpaulo		    "timeout waiting for firmware readiness\n");
2436251538Srpaulo		error = ETIMEDOUT;
2437251538Srpaulo		goto fail;
2438251538Srpaulo	}
2439251538Srpaulofail:
2440251538Srpaulo	firmware_put(fw, FIRMWARE_UNLOAD);
2441251538Srpaulo	return (error);
2442251538Srpaulo}
2443251538Srpaulo
2444264912Skevlostatic __inline int
2445251538Srpaulourtwn_dma_init(struct urtwn_softc *sc)
2446251538Srpaulo{
2447264912Skevlo
2448264912Skevlo	return sc->sc_dma_init(sc);
2449264912Skevlo}
2450264912Skevlo
2451264912Skevlostatic int
2452264912Skevlourtwn_r92c_dma_init(struct urtwn_softc *sc)
2453264912Skevlo{
2454251538Srpaulo	int hashq, hasnq, haslq, nqueues, nqpages, nrempages;
2455251538Srpaulo	uint32_t reg;
2456251538Srpaulo	int error;
2457251538Srpaulo
2458251538Srpaulo	/* Initialize LLT table. */
2459251538Srpaulo	error = urtwn_llt_init(sc);
2460251538Srpaulo	if (error != 0)
2461251538Srpaulo		return (error);
2462251538Srpaulo
2463251538Srpaulo	/* Get Tx queues to USB endpoints mapping. */
2464251538Srpaulo	hashq = hasnq = haslq = 0;
2465251538Srpaulo	reg = urtwn_read_2(sc, R92C_USB_EP + 1);
2466251538Srpaulo	DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg);
2467251538Srpaulo	if (MS(reg, R92C_USB_EP_HQ) != 0)
2468251538Srpaulo		hashq = 1;
2469251538Srpaulo	if (MS(reg, R92C_USB_EP_NQ) != 0)
2470251538Srpaulo		hasnq = 1;
2471251538Srpaulo	if (MS(reg, R92C_USB_EP_LQ) != 0)
2472251538Srpaulo		haslq = 1;
2473251538Srpaulo	nqueues = hashq + hasnq + haslq;
2474251538Srpaulo	if (nqueues == 0)
2475251538Srpaulo		return (EIO);
2476251538Srpaulo	/* Get the number of pages for each queue. */
2477251538Srpaulo	nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues;
2478251538Srpaulo	/* The remaining pages are assigned to the high priority queue. */
2479251538Srpaulo	nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues;
2480251538Srpaulo
2481251538Srpaulo	/* Set number of pages for normal priority queue. */
2482251538Srpaulo	urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0);
2483251538Srpaulo	urtwn_write_4(sc, R92C_RQPN,
2484251538Srpaulo	    /* Set number of pages for public queue. */
2485251538Srpaulo	    SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) |
2486251538Srpaulo	    /* Set number of pages for high priority queue. */
2487251538Srpaulo	    SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) |
2488251538Srpaulo	    /* Set number of pages for low priority queue. */
2489251538Srpaulo	    SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) |
2490251538Srpaulo	    /* Load values. */
2491251538Srpaulo	    R92C_RQPN_LD);
2492251538Srpaulo
2493251538Srpaulo	urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY);
2494251538Srpaulo	urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY);
2495251538Srpaulo	urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY);
2496251538Srpaulo	urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY);
2497251538Srpaulo	urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY);
2498251538Srpaulo
2499251538Srpaulo	/* Set queue to USB pipe mapping. */
2500251538Srpaulo	reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
2501251538Srpaulo	reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
2502251538Srpaulo	if (nqueues == 1) {
2503251538Srpaulo		if (hashq)
2504251538Srpaulo			reg |= R92C_TRXDMA_CTRL_QMAP_HQ;
2505251538Srpaulo		else if (hasnq)
2506251538Srpaulo			reg |= R92C_TRXDMA_CTRL_QMAP_NQ;
2507251538Srpaulo		else
2508251538Srpaulo			reg |= R92C_TRXDMA_CTRL_QMAP_LQ;
2509251538Srpaulo	} else if (nqueues == 2) {
2510251538Srpaulo		/* All 2-endpoints configs have a high priority queue. */
2511251538Srpaulo		if (!hashq)
2512251538Srpaulo			return (EIO);
2513251538Srpaulo		if (hasnq)
2514251538Srpaulo			reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;
2515251538Srpaulo		else
2516251538Srpaulo			reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ;
2517251538Srpaulo	} else
2518251538Srpaulo		reg |= R92C_TRXDMA_CTRL_QMAP_3EP;
2519251538Srpaulo	urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
2520251538Srpaulo
2521251538Srpaulo	/* Set Tx/Rx transfer page boundary. */
2522251538Srpaulo	urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff);
2523251538Srpaulo
2524251538Srpaulo	/* Set Tx/Rx transfer page size. */
2525251538Srpaulo	urtwn_write_1(sc, R92C_PBP,
2526251538Srpaulo	    SM(R92C_PBP_PSRX, R92C_PBP_128) |
2527251538Srpaulo	    SM(R92C_PBP_PSTX, R92C_PBP_128));
2528251538Srpaulo	return (0);
2529251538Srpaulo}
2530251538Srpaulo
2531264912Skevlostatic int
2532264912Skevlourtwn_r88e_dma_init(struct urtwn_softc *sc)
2533264912Skevlo{
2534264912Skevlo	struct usb_interface *iface;
2535264912Skevlo	uint32_t reg;
2536264912Skevlo	int nqueues;
2537264912Skevlo	int error;
2538264912Skevlo
2539264912Skevlo	/* Initialize LLT table. */
2540264912Skevlo	error = urtwn_llt_init(sc);
2541264912Skevlo	if (error != 0)
2542264912Skevlo		return (error);
2543264912Skevlo
2544264912Skevlo	/* Get Tx queues to USB endpoints mapping. */
2545264912Skevlo	iface = usbd_get_iface(sc->sc_udev, 0);
2546264912Skevlo	nqueues = iface->idesc->bNumEndpoints - 1;
2547264912Skevlo	if (nqueues == 0)
2548264912Skevlo		return (EIO);
2549264912Skevlo
2550264912Skevlo	/* Set number of pages for normal priority queue. */
2551264912Skevlo	urtwn_write_2(sc, R92C_RQPN_NPQ, 0);
2552264912Skevlo	urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d);
2553264912Skevlo	urtwn_write_4(sc, R92C_RQPN, 0x808e000d);
2554264912Skevlo
2555264912Skevlo	urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY);
2556264912Skevlo	urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY);
2557264912Skevlo	urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY);
2558264912Skevlo	urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY);
2559264912Skevlo	urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY);
2560264912Skevlo
2561264912Skevlo	/* Set queue to USB pipe mapping. */
2562264912Skevlo	reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
2563264912Skevlo	reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
2564264912Skevlo	if (nqueues == 1)
2565264912Skevlo		reg |= R92C_TRXDMA_CTRL_QMAP_LQ;
2566264912Skevlo	else if (nqueues == 2)
2567264912Skevlo		reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;
2568264912Skevlo	else
2569264912Skevlo		reg |= R92C_TRXDMA_CTRL_QMAP_3EP;
2570264912Skevlo	urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
2571264912Skevlo
2572264912Skevlo	/* Set Tx/Rx transfer page boundary. */
2573264912Skevlo	urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff);
2574264912Skevlo
2575264912Skevlo	/* Set Tx/Rx transfer page size. */
2576264912Skevlo	urtwn_write_1(sc, R92C_PBP,
2577264912Skevlo	    SM(R92C_PBP_PSRX, R92C_PBP_128) |
2578264912Skevlo	    SM(R92C_PBP_PSTX, R92C_PBP_128));
2579264912Skevlo
2580264912Skevlo	return (0);
2581264912Skevlo}
2582264912Skevlo
2583251538Srpaulostatic void
2584251538Srpaulourtwn_mac_init(struct urtwn_softc *sc)
2585251538Srpaulo{
2586251538Srpaulo	int i;
2587251538Srpaulo
2588251538Srpaulo	/* Write MAC initialization values. */
2589264912Skevlo	if (sc->chip & URTWN_CHIP_88E) {
2590264912Skevlo		for (i = 0; i < nitems(rtl8188eu_mac); i++) {
2591264912Skevlo			urtwn_write_1(sc, rtl8188eu_mac[i].reg,
2592264912Skevlo			    rtl8188eu_mac[i].val);
2593264912Skevlo		}
2594264912Skevlo		urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07);
2595264912Skevlo	} else {
2596264912Skevlo		for (i = 0; i < nitems(rtl8192cu_mac); i++)
2597264912Skevlo			urtwn_write_1(sc, rtl8192cu_mac[i].reg,
2598264912Skevlo			    rtl8192cu_mac[i].val);
2599264912Skevlo	}
2600251538Srpaulo}
2601251538Srpaulo
2602251538Srpaulostatic void
2603251538Srpaulourtwn_bb_init(struct urtwn_softc *sc)
2604251538Srpaulo{
2605251538Srpaulo	const struct urtwn_bb_prog *prog;
2606251538Srpaulo	uint32_t reg;
2607264912Skevlo	uint8_t crystalcap;
2608251538Srpaulo	int i;
2609251538Srpaulo
2610251538Srpaulo	/* Enable BB and RF. */
2611251538Srpaulo	urtwn_write_2(sc, R92C_SYS_FUNC_EN,
2612251538Srpaulo	    urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
2613251538Srpaulo	    R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
2614251538Srpaulo	    R92C_SYS_FUNC_EN_DIO_RF);
2615251538Srpaulo
2616264912Skevlo	if (!(sc->chip & URTWN_CHIP_88E))
2617264912Skevlo		urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
2618251538Srpaulo
2619251538Srpaulo	urtwn_write_1(sc, R92C_RF_CTRL,
2620251538Srpaulo	    R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
2621251538Srpaulo	urtwn_write_1(sc, R92C_SYS_FUNC_EN,
2622251538Srpaulo	    R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
2623251538Srpaulo	    R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
2624251538Srpaulo
2625264912Skevlo	if (!(sc->chip & URTWN_CHIP_88E)) {
2626264912Skevlo		urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f);
2627264912Skevlo		urtwn_write_1(sc, 0x15, 0xe9);
2628264912Skevlo		urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
2629264912Skevlo	}
2630251538Srpaulo
2631251538Srpaulo	/* Select BB programming based on board type. */
2632264912Skevlo	if (sc->chip & URTWN_CHIP_88E)
2633264912Skevlo		prog = &rtl8188eu_bb_prog;
2634264912Skevlo	else if (!(sc->chip & URTWN_CHIP_92C)) {
2635251538Srpaulo		if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
2636251538Srpaulo			prog = &rtl8188ce_bb_prog;
2637251538Srpaulo		else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2638251538Srpaulo			prog = &rtl8188ru_bb_prog;
2639251538Srpaulo		else
2640251538Srpaulo			prog = &rtl8188cu_bb_prog;
2641251538Srpaulo	} else {
2642251538Srpaulo		if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
2643251538Srpaulo			prog = &rtl8192ce_bb_prog;
2644251538Srpaulo		else
2645251538Srpaulo			prog = &rtl8192cu_bb_prog;
2646251538Srpaulo	}
2647251538Srpaulo	/* Write BB initialization values. */
2648251538Srpaulo	for (i = 0; i < prog->count; i++) {
2649251538Srpaulo		urtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
2650266472Shselasky		urtwn_ms_delay(sc);
2651251538Srpaulo	}
2652251538Srpaulo
2653251538Srpaulo	if (sc->chip & URTWN_CHIP_92C_1T2R) {
2654251538Srpaulo		/* 8192C 1T only configuration. */
2655251538Srpaulo		reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
2656251538Srpaulo		reg = (reg & ~0x00000003) | 0x2;
2657251538Srpaulo		urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
2658251538Srpaulo
2659251538Srpaulo		reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
2660251538Srpaulo		reg = (reg & ~0x00300033) | 0x00200022;
2661251538Srpaulo		urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
2662251538Srpaulo
2663251538Srpaulo		reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
2664251538Srpaulo		reg = (reg & ~0xff000000) | 0x45 << 24;
2665251538Srpaulo		urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
2666251538Srpaulo
2667251538Srpaulo		reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
2668251538Srpaulo		reg = (reg & ~0x000000ff) | 0x23;
2669251538Srpaulo		urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
2670251538Srpaulo
2671251538Srpaulo		reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
2672251538Srpaulo		reg = (reg & ~0x00000030) | 1 << 4;
2673251538Srpaulo		urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
2674251538Srpaulo
2675251538Srpaulo		reg = urtwn_bb_read(sc, 0xe74);
2676251538Srpaulo		reg = (reg & ~0x0c000000) | 2 << 26;
2677251538Srpaulo		urtwn_bb_write(sc, 0xe74, reg);
2678251538Srpaulo		reg = urtwn_bb_read(sc, 0xe78);
2679251538Srpaulo		reg = (reg & ~0x0c000000) | 2 << 26;
2680251538Srpaulo		urtwn_bb_write(sc, 0xe78, reg);
2681251538Srpaulo		reg = urtwn_bb_read(sc, 0xe7c);
2682251538Srpaulo		reg = (reg & ~0x0c000000) | 2 << 26;
2683251538Srpaulo		urtwn_bb_write(sc, 0xe7c, reg);
2684251538Srpaulo		reg = urtwn_bb_read(sc, 0xe80);
2685251538Srpaulo		reg = (reg & ~0x0c000000) | 2 << 26;
2686251538Srpaulo		urtwn_bb_write(sc, 0xe80, reg);
2687251538Srpaulo		reg = urtwn_bb_read(sc, 0xe88);
2688251538Srpaulo		reg = (reg & ~0x0c000000) | 2 << 26;
2689251538Srpaulo		urtwn_bb_write(sc, 0xe88, reg);
2690251538Srpaulo	}
2691251538Srpaulo
2692251538Srpaulo	/* Write AGC values. */
2693251538Srpaulo	for (i = 0; i < prog->agccount; i++) {
2694251538Srpaulo		urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
2695251538Srpaulo		    prog->agcvals[i]);
2696266472Shselasky		urtwn_ms_delay(sc);
2697251538Srpaulo	}
2698251538Srpaulo
2699264912Skevlo	if (sc->chip & URTWN_CHIP_88E) {
2700264912Skevlo		urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
2701266472Shselasky		urtwn_ms_delay(sc);
2702264912Skevlo		urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420);
2703266472Shselasky		urtwn_ms_delay(sc);
2704264912Skevlo
2705264912Skevlo		crystalcap = sc->r88e_rom[0xb9];
2706264912Skevlo		if (crystalcap == 0xff)
2707264912Skevlo			crystalcap = 0x20;
2708264912Skevlo		crystalcap &= 0x3f;
2709264912Skevlo		reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
2710264912Skevlo		urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
2711264912Skevlo		    RW(reg, R92C_AFE_XTAL_CTRL_ADDR,
2712264912Skevlo		    crystalcap | crystalcap << 6));
2713264912Skevlo	} else {
2714264912Skevlo		if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
2715264912Skevlo		    R92C_HSSI_PARAM2_CCK_HIPWR)
2716264912Skevlo			sc->sc_flags |= URTWN_FLAG_CCK_HIPWR;
2717264912Skevlo	}
2718251538Srpaulo}
2719251538Srpaulo
2720251538Srpaulovoid
2721251538Srpaulourtwn_rf_init(struct urtwn_softc *sc)
2722251538Srpaulo{
2723251538Srpaulo	const struct urtwn_rf_prog *prog;
2724251538Srpaulo	uint32_t reg, type;
2725251538Srpaulo	int i, j, idx, off;
2726251538Srpaulo
2727251538Srpaulo	/* Select RF programming based on board type. */
2728264912Skevlo	if (sc->chip & URTWN_CHIP_88E)
2729264912Skevlo		prog = rtl8188eu_rf_prog;
2730264912Skevlo	else if (!(sc->chip & URTWN_CHIP_92C)) {
2731251538Srpaulo		if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
2732251538Srpaulo			prog = rtl8188ce_rf_prog;
2733251538Srpaulo		else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2734251538Srpaulo			prog = rtl8188ru_rf_prog;
2735251538Srpaulo		else
2736251538Srpaulo			prog = rtl8188cu_rf_prog;
2737251538Srpaulo	} else
2738251538Srpaulo		prog = rtl8192ce_rf_prog;
2739251538Srpaulo
2740251538Srpaulo	for (i = 0; i < sc->nrxchains; i++) {
2741251538Srpaulo		/* Save RF_ENV control type. */
2742251538Srpaulo		idx = i / 2;
2743251538Srpaulo		off = (i % 2) * 16;
2744251538Srpaulo		reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2745251538Srpaulo		type = (reg >> off) & 0x10;
2746251538Srpaulo
2747251538Srpaulo		/* Set RF_ENV enable. */
2748251538Srpaulo		reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
2749251538Srpaulo		reg |= 0x100000;
2750251538Srpaulo		urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
2751266472Shselasky		urtwn_ms_delay(sc);
2752251538Srpaulo		/* Set RF_ENV output high. */
2753251538Srpaulo		reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
2754251538Srpaulo		reg |= 0x10;
2755251538Srpaulo		urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
2756266472Shselasky		urtwn_ms_delay(sc);
2757251538Srpaulo		/* Set address and data lengths of RF registers. */
2758251538Srpaulo		reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
2759251538Srpaulo		reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH;
2760251538Srpaulo		urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
2761266472Shselasky		urtwn_ms_delay(sc);
2762251538Srpaulo		reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
2763251538Srpaulo		reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH;
2764251538Srpaulo		urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
2765266472Shselasky		urtwn_ms_delay(sc);
2766251538Srpaulo
2767251538Srpaulo		/* Write RF initialization values for this chain. */
2768251538Srpaulo		for (j = 0; j < prog[i].count; j++) {
2769251538Srpaulo			if (prog[i].regs[j] >= 0xf9 &&
2770251538Srpaulo			    prog[i].regs[j] <= 0xfe) {
2771251538Srpaulo				/*
2772251538Srpaulo				 * These are fake RF registers offsets that
2773251538Srpaulo				 * indicate a delay is required.
2774251538Srpaulo				 */
2775266472Shselasky				usb_pause_mtx(&sc->sc_mtx, hz / 20);	/* 50ms */
2776251538Srpaulo				continue;
2777251538Srpaulo			}
2778251538Srpaulo			urtwn_rf_write(sc, i, prog[i].regs[j],
2779251538Srpaulo			    prog[i].vals[j]);
2780266472Shselasky			urtwn_ms_delay(sc);
2781251538Srpaulo		}
2782251538Srpaulo
2783251538Srpaulo		/* Restore RF_ENV control type. */
2784251538Srpaulo		reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2785251538Srpaulo		reg &= ~(0x10 << off) | (type << off);
2786251538Srpaulo		urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);
2787251538Srpaulo
2788251538Srpaulo		/* Cache RF register CHNLBW. */
2789251538Srpaulo		sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW);
2790251538Srpaulo	}
2791251538Srpaulo
2792251538Srpaulo	if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
2793251538Srpaulo	    URTWN_CHIP_UMC_A_CUT) {
2794251538Srpaulo		urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255);
2795251538Srpaulo		urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00);
2796251538Srpaulo	}
2797251538Srpaulo}
2798251538Srpaulo
2799251538Srpaulostatic void
2800251538Srpaulourtwn_cam_init(struct urtwn_softc *sc)
2801251538Srpaulo{
2802251538Srpaulo	/* Invalidate all CAM entries. */
2803251538Srpaulo	urtwn_write_4(sc, R92C_CAMCMD,
2804251538Srpaulo	    R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR);
2805251538Srpaulo}
2806251538Srpaulo
2807251538Srpaulostatic void
2808251538Srpaulourtwn_pa_bias_init(struct urtwn_softc *sc)
2809251538Srpaulo{
2810251538Srpaulo	uint8_t reg;
2811251538Srpaulo	int i;
2812251538Srpaulo
2813251538Srpaulo	for (i = 0; i < sc->nrxchains; i++) {
2814251538Srpaulo		if (sc->pa_setting & (1 << i))
2815251538Srpaulo			continue;
2816251538Srpaulo		urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406);
2817251538Srpaulo		urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406);
2818251538Srpaulo		urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406);
2819251538Srpaulo		urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406);
2820251538Srpaulo	}
2821251538Srpaulo	if (!(sc->pa_setting & 0x10)) {
2822251538Srpaulo		reg = urtwn_read_1(sc, 0x16);
2823251538Srpaulo		reg = (reg & ~0xf0) | 0x90;
2824251538Srpaulo		urtwn_write_1(sc, 0x16, reg);
2825251538Srpaulo	}
2826251538Srpaulo}
2827251538Srpaulo
2828251538Srpaulostatic void
2829251538Srpaulourtwn_rxfilter_init(struct urtwn_softc *sc)
2830251538Srpaulo{
2831251538Srpaulo	/* Initialize Rx filter. */
2832251538Srpaulo	/* TODO: use better filter for monitor mode. */
2833251538Srpaulo	urtwn_write_4(sc, R92C_RCR,
2834251538Srpaulo	    R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB |
2835251538Srpaulo	    R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL |
2836251538Srpaulo	    R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS);
2837251538Srpaulo	/* Accept all multicast frames. */
2838251538Srpaulo	urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff);
2839251538Srpaulo	urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff);
2840251538Srpaulo	/* Accept all management frames. */
2841251538Srpaulo	urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff);
2842251538Srpaulo	/* Reject all control frames. */
2843251538Srpaulo	urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000);
2844251538Srpaulo	/* Accept all data frames. */
2845251538Srpaulo	urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
2846251538Srpaulo}
2847251538Srpaulo
2848251538Srpaulostatic void
2849251538Srpaulourtwn_edca_init(struct urtwn_softc *sc)
2850251538Srpaulo{
2851251538Srpaulo	urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a);
2852251538Srpaulo	urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a);
2853251538Srpaulo	urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a);
2854251538Srpaulo	urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a);
2855251538Srpaulo	urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
2856251538Srpaulo	urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
2857251538Srpaulo	urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324);
2858251538Srpaulo	urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226);
2859251538Srpaulo}
2860251538Srpaulo
2861251538Srpaulovoid
2862251538Srpaulourtwn_write_txpower(struct urtwn_softc *sc, int chain,
2863251538Srpaulo    uint16_t power[URTWN_RIDX_COUNT])
2864251538Srpaulo{
2865251538Srpaulo	uint32_t reg;
2866251538Srpaulo
2867251538Srpaulo	/* Write per-CCK rate Tx power. */
2868251538Srpaulo	if (chain == 0) {
2869251538Srpaulo		reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
2870251538Srpaulo		reg = RW(reg, R92C_TXAGC_A_CCK1,  power[0]);
2871251538Srpaulo		urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
2872251538Srpaulo		reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2873251538Srpaulo		reg = RW(reg, R92C_TXAGC_A_CCK2,  power[1]);
2874251538Srpaulo		reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);
2875251538Srpaulo		reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);
2876251538Srpaulo		urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
2877251538Srpaulo	} else {
2878251538Srpaulo		reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
2879251538Srpaulo		reg = RW(reg, R92C_TXAGC_B_CCK1,  power[0]);
2880251538Srpaulo		reg = RW(reg, R92C_TXAGC_B_CCK2,  power[1]);
2881251538Srpaulo		reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);
2882251538Srpaulo		urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
2883251538Srpaulo		reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2884251538Srpaulo		reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);
2885251538Srpaulo		urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
2886251538Srpaulo	}
2887251538Srpaulo	/* Write per-OFDM rate Tx power. */
2888251538Srpaulo	urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
2889251538Srpaulo	    SM(R92C_TXAGC_RATE06, power[ 4]) |
2890251538Srpaulo	    SM(R92C_TXAGC_RATE09, power[ 5]) |
2891251538Srpaulo	    SM(R92C_TXAGC_RATE12, power[ 6]) |
2892251538Srpaulo	    SM(R92C_TXAGC_RATE18, power[ 7]));
2893251538Srpaulo	urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
2894251538Srpaulo	    SM(R92C_TXAGC_RATE24, power[ 8]) |
2895251538Srpaulo	    SM(R92C_TXAGC_RATE36, power[ 9]) |
2896251538Srpaulo	    SM(R92C_TXAGC_RATE48, power[10]) |
2897251538Srpaulo	    SM(R92C_TXAGC_RATE54, power[11]));
2898251538Srpaulo	/* Write per-MCS Tx power. */
2899251538Srpaulo	urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
2900251538Srpaulo	    SM(R92C_TXAGC_MCS00,  power[12]) |
2901251538Srpaulo	    SM(R92C_TXAGC_MCS01,  power[13]) |
2902251538Srpaulo	    SM(R92C_TXAGC_MCS02,  power[14]) |
2903251538Srpaulo	    SM(R92C_TXAGC_MCS03,  power[15]));
2904251538Srpaulo	urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
2905251538Srpaulo	    SM(R92C_TXAGC_MCS04,  power[16]) |
2906251538Srpaulo	    SM(R92C_TXAGC_MCS05,  power[17]) |
2907251538Srpaulo	    SM(R92C_TXAGC_MCS06,  power[18]) |
2908251538Srpaulo	    SM(R92C_TXAGC_MCS07,  power[19]));
2909251538Srpaulo	urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
2910251538Srpaulo	    SM(R92C_TXAGC_MCS08,  power[20]) |
2911261506Skevlo	    SM(R92C_TXAGC_MCS09,  power[21]) |
2912251538Srpaulo	    SM(R92C_TXAGC_MCS10,  power[22]) |
2913251538Srpaulo	    SM(R92C_TXAGC_MCS11,  power[23]));
2914251538Srpaulo	urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
2915251538Srpaulo	    SM(R92C_TXAGC_MCS12,  power[24]) |
2916251538Srpaulo	    SM(R92C_TXAGC_MCS13,  power[25]) |
2917251538Srpaulo	    SM(R92C_TXAGC_MCS14,  power[26]) |
2918251538Srpaulo	    SM(R92C_TXAGC_MCS15,  power[27]));
2919251538Srpaulo}
2920251538Srpaulo
2921251538Srpaulovoid
2922251538Srpaulourtwn_get_txpower(struct urtwn_softc *sc, int chain,
2923251538Srpaulo    struct ieee80211_channel *c, struct ieee80211_channel *extc,
2924251538Srpaulo    uint16_t power[URTWN_RIDX_COUNT])
2925251538Srpaulo{
2926251538Srpaulo	struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2927251538Srpaulo	struct r92c_rom *rom = &sc->rom;
2928251538Srpaulo	uint16_t cckpow, ofdmpow, htpow, diff, max;
2929251538Srpaulo	const struct urtwn_txpwr *base;
2930251538Srpaulo	int ridx, chan, group;
2931251538Srpaulo
2932251538Srpaulo	/* Determine channel group. */
2933251538Srpaulo	chan = ieee80211_chan2ieee(ic, c);	/* XXX center freq! */
2934251538Srpaulo	if (chan <= 3)
2935251538Srpaulo		group = 0;
2936251538Srpaulo	else if (chan <= 9)
2937251538Srpaulo		group = 1;
2938251538Srpaulo	else
2939251538Srpaulo		group = 2;
2940251538Srpaulo
2941251538Srpaulo	/* Get original Tx power based on board type and RF chain. */
2942251538Srpaulo	if (!(sc->chip & URTWN_CHIP_92C)) {
2943251538Srpaulo		if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2944251538Srpaulo			base = &rtl8188ru_txagc[chain];
2945251538Srpaulo		else
2946251538Srpaulo			base = &rtl8192cu_txagc[chain];
2947251538Srpaulo	} else
2948251538Srpaulo		base = &rtl8192cu_txagc[chain];
2949251538Srpaulo
2950251538Srpaulo	memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0]));
2951251538Srpaulo	if (sc->regulatory == 0) {
2952251538Srpaulo		for (ridx = 0; ridx <= 3; ridx++)
2953251538Srpaulo			power[ridx] = base->pwr[0][ridx];
2954251538Srpaulo	}
2955251538Srpaulo	for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) {
2956251538Srpaulo		if (sc->regulatory == 3) {
2957251538Srpaulo			power[ridx] = base->pwr[0][ridx];
2958251538Srpaulo			/* Apply vendor limits. */
2959251538Srpaulo			if (extc != NULL)
2960251538Srpaulo				max = rom->ht40_max_pwr[group];
2961251538Srpaulo			else
2962251538Srpaulo				max = rom->ht20_max_pwr[group];
2963251538Srpaulo			max = (max >> (chain * 4)) & 0xf;
2964251538Srpaulo			if (power[ridx] > max)
2965251538Srpaulo				power[ridx] = max;
2966251538Srpaulo		} else if (sc->regulatory == 1) {
2967251538Srpaulo			if (extc == NULL)
2968251538Srpaulo				power[ridx] = base->pwr[group][ridx];
2969251538Srpaulo		} else if (sc->regulatory != 2)
2970251538Srpaulo			power[ridx] = base->pwr[0][ridx];
2971251538Srpaulo	}
2972251538Srpaulo
2973251538Srpaulo	/* Compute per-CCK rate Tx power. */
2974251538Srpaulo	cckpow = rom->cck_tx_pwr[chain][group];
2975251538Srpaulo	for (ridx = 0; ridx <= 3; ridx++) {
2976251538Srpaulo		power[ridx] += cckpow;
2977251538Srpaulo		if (power[ridx] > R92C_MAX_TX_PWR)
2978251538Srpaulo			power[ridx] = R92C_MAX_TX_PWR;
2979251538Srpaulo	}
2980251538Srpaulo
2981251538Srpaulo	htpow = rom->ht40_1s_tx_pwr[chain][group];
2982251538Srpaulo	if (sc->ntxchains > 1) {
2983251538Srpaulo		/* Apply reduction for 2 spatial streams. */
2984251538Srpaulo		diff = rom->ht40_2s_tx_pwr_diff[group];
2985251538Srpaulo		diff = (diff >> (chain * 4)) & 0xf;
2986251538Srpaulo		htpow = (htpow > diff) ? htpow - diff : 0;
2987251538Srpaulo	}
2988251538Srpaulo
2989251538Srpaulo	/* Compute per-OFDM rate Tx power. */
2990251538Srpaulo	diff = rom->ofdm_tx_pwr_diff[group];
2991251538Srpaulo	diff = (diff >> (chain * 4)) & 0xf;
2992251538Srpaulo	ofdmpow = htpow + diff;	/* HT->OFDM correction. */
2993251538Srpaulo	for (ridx = 4; ridx <= 11; ridx++) {
2994251538Srpaulo		power[ridx] += ofdmpow;
2995251538Srpaulo		if (power[ridx] > R92C_MAX_TX_PWR)
2996251538Srpaulo			power[ridx] = R92C_MAX_TX_PWR;
2997251538Srpaulo	}
2998251538Srpaulo
2999251538Srpaulo	/* Compute per-MCS Tx power. */
3000251538Srpaulo	if (extc == NULL) {
3001251538Srpaulo		diff = rom->ht20_tx_pwr_diff[group];
3002251538Srpaulo		diff = (diff >> (chain * 4)) & 0xf;
3003251538Srpaulo		htpow += diff;	/* HT40->HT20 correction. */
3004251538Srpaulo	}
3005251538Srpaulo	for (ridx = 12; ridx <= 27; ridx++) {
3006251538Srpaulo		power[ridx] += htpow;
3007251538Srpaulo		if (power[ridx] > R92C_MAX_TX_PWR)
3008251538Srpaulo			power[ridx] = R92C_MAX_TX_PWR;
3009251538Srpaulo	}
3010251538Srpaulo#ifdef URTWN_DEBUG
3011251538Srpaulo	if (urtwn_debug >= 4) {
3012251538Srpaulo		/* Dump per-rate Tx power values. */
3013251538Srpaulo		printf("Tx power for chain %d:\n", chain);
3014251538Srpaulo		for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++)
3015251538Srpaulo			printf("Rate %d = %u\n", ridx, power[ridx]);
3016251538Srpaulo	}
3017251538Srpaulo#endif
3018251538Srpaulo}
3019251538Srpaulo
3020251538Srpaulovoid
3021264912Skevlourtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain,
3022264912Skevlo    struct ieee80211_channel *c, struct ieee80211_channel *extc,
3023264912Skevlo    uint16_t power[URTWN_RIDX_COUNT])
3024264912Skevlo{
3025264912Skevlo	struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3026264912Skevlo	uint16_t cckpow, ofdmpow, bw20pow, htpow;
3027264912Skevlo	const struct urtwn_r88e_txpwr *base;
3028264912Skevlo	int ridx, chan, group;
3029264912Skevlo
3030264912Skevlo	/* Determine channel group. */
3031264912Skevlo	chan = ieee80211_chan2ieee(ic, c);	/* XXX center freq! */
3032264912Skevlo	if (chan <= 2)
3033264912Skevlo		group = 0;
3034264912Skevlo	else if (chan <= 5)
3035264912Skevlo		group = 1;
3036264912Skevlo	else if (chan <= 8)
3037264912Skevlo		group = 2;
3038264912Skevlo	else if (chan <= 11)
3039264912Skevlo		group = 3;
3040264912Skevlo	else if (chan <= 13)
3041264912Skevlo		group = 4;
3042264912Skevlo	else
3043264912Skevlo		group = 5;
3044264912Skevlo
3045264912Skevlo	/* Get original Tx power based on board type and RF chain. */
3046264912Skevlo	base = &rtl8188eu_txagc[chain];
3047264912Skevlo
3048264912Skevlo	memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0]));
3049264912Skevlo	if (sc->regulatory == 0) {
3050264912Skevlo		for (ridx = 0; ridx <= 3; ridx++)
3051264912Skevlo			power[ridx] = base->pwr[0][ridx];
3052264912Skevlo	}
3053264912Skevlo	for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) {
3054264912Skevlo		if (sc->regulatory == 3)
3055264912Skevlo			power[ridx] = base->pwr[0][ridx];
3056264912Skevlo		else if (sc->regulatory == 1) {
3057264912Skevlo			if (extc == NULL)
3058264912Skevlo				power[ridx] = base->pwr[group][ridx];
3059264912Skevlo		} else if (sc->regulatory != 2)
3060264912Skevlo			power[ridx] = base->pwr[0][ridx];
3061264912Skevlo	}
3062264912Skevlo
3063264912Skevlo	/* Compute per-CCK rate Tx power. */
3064264912Skevlo	cckpow = sc->cck_tx_pwr[group];
3065264912Skevlo	for (ridx = 0; ridx <= 3; ridx++) {
3066264912Skevlo		power[ridx] += cckpow;
3067264912Skevlo		if (power[ridx] > R92C_MAX_TX_PWR)
3068264912Skevlo			power[ridx] = R92C_MAX_TX_PWR;
3069264912Skevlo	}
3070264912Skevlo
3071264912Skevlo	htpow = sc->ht40_tx_pwr[group];
3072264912Skevlo
3073264912Skevlo	/* Compute per-OFDM rate Tx power. */
3074264912Skevlo	ofdmpow = htpow + sc->ofdm_tx_pwr_diff;
3075264912Skevlo	for (ridx = 4; ridx <= 11; ridx++) {
3076264912Skevlo		power[ridx] += ofdmpow;
3077264912Skevlo		if (power[ridx] > R92C_MAX_TX_PWR)
3078264912Skevlo			power[ridx] = R92C_MAX_TX_PWR;
3079264912Skevlo	}
3080264912Skevlo
3081264912Skevlo	bw20pow = htpow + sc->bw20_tx_pwr_diff;
3082264912Skevlo	for (ridx = 12; ridx <= 27; ridx++) {
3083264912Skevlo		power[ridx] += bw20pow;
3084264912Skevlo		if (power[ridx] > R92C_MAX_TX_PWR)
3085264912Skevlo			power[ridx] = R92C_MAX_TX_PWR;
3086264912Skevlo	}
3087264912Skevlo}
3088264912Skevlo
3089264912Skevlovoid
3090251538Srpaulourtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c,
3091251538Srpaulo    struct ieee80211_channel *extc)
3092251538Srpaulo{
3093251538Srpaulo	uint16_t power[URTWN_RIDX_COUNT];
3094251538Srpaulo	int i;
3095251538Srpaulo
3096251538Srpaulo	for (i = 0; i < sc->ntxchains; i++) {
3097251538Srpaulo		/* Compute per-rate Tx power values. */
3098264912Skevlo		if (sc->chip & URTWN_CHIP_88E)
3099264912Skevlo			urtwn_r88e_get_txpower(sc, i, c, extc, power);
3100264912Skevlo		else
3101264912Skevlo			urtwn_get_txpower(sc, i, c, extc, power);
3102251538Srpaulo		/* Write per-rate Tx power values to hardware. */
3103251538Srpaulo		urtwn_write_txpower(sc, i, power);
3104251538Srpaulo	}
3105251538Srpaulo}
3106251538Srpaulo
3107251538Srpaulostatic void
3108251538Srpaulourtwn_scan_start(struct ieee80211com *ic)
3109251538Srpaulo{
3110251538Srpaulo	/* XXX do nothing?  */
3111251538Srpaulo}
3112251538Srpaulo
3113251538Srpaulostatic void
3114251538Srpaulourtwn_scan_end(struct ieee80211com *ic)
3115251538Srpaulo{
3116251538Srpaulo	/* XXX do nothing?  */
3117251538Srpaulo}
3118251538Srpaulo
3119251538Srpaulostatic void
3120251538Srpaulourtwn_set_channel(struct ieee80211com *ic)
3121251538Srpaulo{
3122251538Srpaulo	struct urtwn_softc *sc = ic->ic_ifp->if_softc;
3123251538Srpaulo
3124251538Srpaulo	URTWN_LOCK(sc);
3125251538Srpaulo	urtwn_set_chan(sc, ic->ic_curchan, NULL);
3126251538Srpaulo	URTWN_UNLOCK(sc);
3127251538Srpaulo}
3128251538Srpaulo
3129251538Srpaulostatic void
3130251538Srpaulourtwn_update_mcast(struct ifnet *ifp)
3131251538Srpaulo{
3132251538Srpaulo	/* XXX do nothing?  */
3133251538Srpaulo}
3134251538Srpaulo
3135251538Srpaulostatic void
3136251538Srpaulourtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c,
3137251538Srpaulo    struct ieee80211_channel *extc)
3138251538Srpaulo{
3139251538Srpaulo	struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3140251538Srpaulo	uint32_t reg;
3141251538Srpaulo	u_int chan;
3142251538Srpaulo	int i;
3143251538Srpaulo
3144251538Srpaulo	chan = ieee80211_chan2ieee(ic, c);	/* XXX center freq! */
3145251538Srpaulo	if (chan == 0 || chan == IEEE80211_CHAN_ANY) {
3146251538Srpaulo		device_printf(sc->sc_dev,
3147251538Srpaulo		    "%s: invalid channel %x\n", __func__, chan);
3148251538Srpaulo		return;
3149251538Srpaulo	}
3150251538Srpaulo
3151251538Srpaulo	/* Set Tx power for this new channel. */
3152251538Srpaulo	urtwn_set_txpower(sc, c, extc);
3153251538Srpaulo
3154251538Srpaulo	for (i = 0; i < sc->nrxchains; i++) {
3155251538Srpaulo		urtwn_rf_write(sc, i, R92C_RF_CHNLBW,
3156251538Srpaulo		    RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));
3157251538Srpaulo	}
3158251538Srpaulo#ifndef IEEE80211_NO_HT
3159251538Srpaulo	if (extc != NULL) {
3160251538Srpaulo		/* Is secondary channel below or above primary? */
3161251538Srpaulo		int prichlo = c->ic_freq < extc->ic_freq;
3162251538Srpaulo
3163251538Srpaulo		urtwn_write_1(sc, R92C_BWOPMODE,
3164251538Srpaulo		    urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ);
3165251538Srpaulo
3166251538Srpaulo		reg = urtwn_read_1(sc, R92C_RRSR + 2);
3167251538Srpaulo		reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5;
3168251538Srpaulo		urtwn_write_1(sc, R92C_RRSR + 2, reg);
3169251538Srpaulo
3170251538Srpaulo		urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
3171251538Srpaulo		    urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
3172251538Srpaulo		urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
3173251538Srpaulo		    urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
3174251538Srpaulo
3175251538Srpaulo		/* Set CCK side band. */
3176251538Srpaulo		reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM);
3177251538Srpaulo		reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;
3178251538Srpaulo		urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
3179251538Srpaulo
3180251538Srpaulo		reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF);
3181251538Srpaulo		reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;
3182251538Srpaulo		urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
3183251538Srpaulo
3184251538Srpaulo		urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
3185251538Srpaulo		    urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
3186251538Srpaulo		    ~R92C_FPGA0_ANAPARAM2_CBW20);
3187251538Srpaulo
3188251538Srpaulo		reg = urtwn_bb_read(sc, 0x818);
3189251538Srpaulo		reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;
3190251538Srpaulo		urtwn_bb_write(sc, 0x818, reg);
3191251538Srpaulo
3192251538Srpaulo		/* Select 40MHz bandwidth. */
3193251538Srpaulo		urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
3194251538Srpaulo		    (sc->rf_chnlbw[0] & ~0xfff) | chan);
3195251538Srpaulo	} else
3196251538Srpaulo#endif
3197251538Srpaulo	{
3198251538Srpaulo		urtwn_write_1(sc, R92C_BWOPMODE,
3199251538Srpaulo		    urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ);
3200251538Srpaulo
3201251538Srpaulo		urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
3202251538Srpaulo		    urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
3203251538Srpaulo		urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
3204251538Srpaulo		    urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
3205251538Srpaulo
3206264912Skevlo		if (!(sc->chip & URTWN_CHIP_88E)) {
3207264912Skevlo			urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
3208264912Skevlo			    urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
3209264912Skevlo			    R92C_FPGA0_ANAPARAM2_CBW20);
3210264912Skevlo		}
3211264912Skevlo
3212251538Srpaulo		/* Select 20MHz bandwidth. */
3213251538Srpaulo		urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
3214264912Skevlo		    (sc->rf_chnlbw[0] & ~0xfff) | chan |
3215264912Skevlo		    ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 :
3216264912Skevlo		    R92C_RF_CHNLBW_BW20));
3217251538Srpaulo	}
3218251538Srpaulo}
3219251538Srpaulo
3220251538Srpaulostatic void
3221251538Srpaulourtwn_iq_calib(struct urtwn_softc *sc)
3222251538Srpaulo{
3223251538Srpaulo	/* TODO */
3224251538Srpaulo}
3225251538Srpaulo
3226251538Srpaulostatic void
3227251538Srpaulourtwn_lc_calib(struct urtwn_softc *sc)
3228251538Srpaulo{
3229251538Srpaulo	uint32_t rf_ac[2];
3230251538Srpaulo	uint8_t txmode;
3231251538Srpaulo	int i;
3232251538Srpaulo
3233251538Srpaulo	txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
3234251538Srpaulo	if ((txmode & 0x70) != 0) {
3235251538Srpaulo		/* Disable all continuous Tx. */
3236251538Srpaulo		urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70);
3237251538Srpaulo
3238251538Srpaulo		/* Set RF mode to standby mode. */
3239251538Srpaulo		for (i = 0; i < sc->nrxchains; i++) {
3240251538Srpaulo			rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC);
3241251538Srpaulo			urtwn_rf_write(sc, i, R92C_RF_AC,
3242251538Srpaulo			    RW(rf_ac[i], R92C_RF_AC_MODE,
3243251538Srpaulo				R92C_RF_AC_MODE_STANDBY));
3244251538Srpaulo		}
3245251538Srpaulo	} else {
3246251538Srpaulo		/* Block all Tx queues. */
3247251538Srpaulo		urtwn_write_1(sc, R92C_TXPAUSE, 0xff);
3248251538Srpaulo	}
3249251538Srpaulo	/* Start calibration. */
3250251538Srpaulo	urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
3251251538Srpaulo	    urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART);
3252251538Srpaulo
3253251538Srpaulo	/* Give calibration the time to complete. */
3254266472Shselasky	usb_pause_mtx(&sc->sc_mtx, hz / 10);		/* 100ms */
3255251538Srpaulo
3256251538Srpaulo	/* Restore configuration. */
3257251538Srpaulo	if ((txmode & 0x70) != 0) {
3258251538Srpaulo		/* Restore Tx mode. */
3259251538Srpaulo		urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode);
3260251538Srpaulo		/* Restore RF mode. */
3261251538Srpaulo		for (i = 0; i < sc->nrxchains; i++)
3262251538Srpaulo			urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]);
3263251538Srpaulo	} else {
3264251538Srpaulo		/* Unblock all Tx queues. */
3265251538Srpaulo		urtwn_write_1(sc, R92C_TXPAUSE, 0x00);
3266251538Srpaulo	}
3267251538Srpaulo}
3268251538Srpaulo
3269251538Srpaulostatic void
3270251538Srpaulourtwn_init_locked(void *arg)
3271251538Srpaulo{
3272251538Srpaulo	struct urtwn_softc *sc = arg;
3273251538Srpaulo	struct ifnet *ifp = sc->sc_ifp;
3274251538Srpaulo	uint32_t reg;
3275251538Srpaulo	int error;
3276251538Srpaulo
3277264864Skevlo	URTWN_ASSERT_LOCKED(sc);
3278264864Skevlo
3279251538Srpaulo	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3280263153Skevlo		urtwn_stop_locked(ifp);
3281251538Srpaulo
3282251538Srpaulo	/* Init firmware commands ring. */
3283251538Srpaulo	sc->fwcur = 0;
3284251538Srpaulo
3285251538Srpaulo	/* Allocate Tx/Rx buffers. */
3286251538Srpaulo	error = urtwn_alloc_rx_list(sc);
3287251538Srpaulo	if (error != 0)
3288251538Srpaulo		goto fail;
3289251538Srpaulo
3290251538Srpaulo	error = urtwn_alloc_tx_list(sc);
3291251538Srpaulo	if (error != 0)
3292251538Srpaulo		goto fail;
3293251538Srpaulo
3294251538Srpaulo	/* Power on adapter. */
3295251538Srpaulo	error = urtwn_power_on(sc);
3296251538Srpaulo	if (error != 0)
3297251538Srpaulo		goto fail;
3298251538Srpaulo
3299251538Srpaulo	/* Initialize DMA. */
3300251538Srpaulo	error = urtwn_dma_init(sc);
3301251538Srpaulo	if (error != 0)
3302251538Srpaulo		goto fail;
3303251538Srpaulo
3304251538Srpaulo	/* Set info size in Rx descriptors (in 64-bit words). */
3305251538Srpaulo	urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4);
3306251538Srpaulo
3307251538Srpaulo	/* Init interrupts. */
3308264912Skevlo	if (sc->chip & URTWN_CHIP_88E) {
3309264912Skevlo		urtwn_write_4(sc, R88E_HISR, 0xffffffff);
3310264912Skevlo		urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 |
3311264912Skevlo		    R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT);
3312264912Skevlo		urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW |
3313264912Skevlo		    R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR);
3314264912Skevlo		urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
3315264912Skevlo		    urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
3316264912Skevlo		    R92C_USB_SPECIAL_OPTION_INT_BULK_SEL);
3317264912Skevlo	} else {
3318264912Skevlo		urtwn_write_4(sc, R92C_HISR, 0xffffffff);
3319264912Skevlo		urtwn_write_4(sc, R92C_HIMR, 0xffffffff);
3320264912Skevlo	}
3321251538Srpaulo
3322251538Srpaulo	/* Set MAC address. */
3323251538Srpaulo	urtwn_write_region_1(sc, R92C_MACID, IF_LLADDR(ifp),
3324251538Srpaulo	    IEEE80211_ADDR_LEN);
3325251538Srpaulo
3326251538Srpaulo	/* Set initial network type. */
3327251538Srpaulo	reg = urtwn_read_4(sc, R92C_CR);
3328251538Srpaulo	reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA);
3329251538Srpaulo	urtwn_write_4(sc, R92C_CR, reg);
3330251538Srpaulo
3331251538Srpaulo	urtwn_rxfilter_init(sc);
3332251538Srpaulo
3333251538Srpaulo	reg = urtwn_read_4(sc, R92C_RRSR);
3334251538Srpaulo	reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M);
3335251538Srpaulo	urtwn_write_4(sc, R92C_RRSR, reg);
3336251538Srpaulo
3337251538Srpaulo	/* Set short/long retry limits. */
3338251538Srpaulo	urtwn_write_2(sc, R92C_RL,
3339251538Srpaulo	    SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30));
3340251538Srpaulo
3341251538Srpaulo	/* Initialize EDCA parameters. */
3342251538Srpaulo	urtwn_edca_init(sc);
3343251538Srpaulo
3344251538Srpaulo	/* Setup rate fallback. */
3345264912Skevlo	if (!(sc->chip & URTWN_CHIP_88E)) {
3346264912Skevlo		urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000);
3347264912Skevlo		urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404);
3348264912Skevlo		urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201);
3349264912Skevlo		urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605);
3350264912Skevlo	}
3351251538Srpaulo
3352251538Srpaulo	urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL,
3353251538Srpaulo	    urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) |
3354251538Srpaulo	    R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW);
3355251538Srpaulo	/* Set ACK timeout. */
3356251538Srpaulo	urtwn_write_1(sc, R92C_ACKTO, 0x40);
3357251538Srpaulo
3358251538Srpaulo	/* Setup USB aggregation. */
3359251538Srpaulo	reg = urtwn_read_4(sc, R92C_TDECTRL);
3360251538Srpaulo	reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6);
3361251538Srpaulo	urtwn_write_4(sc, R92C_TDECTRL, reg);
3362251538Srpaulo	urtwn_write_1(sc, R92C_TRXDMA_CTRL,
3363251538Srpaulo	    urtwn_read_1(sc, R92C_TRXDMA_CTRL) |
3364251538Srpaulo	    R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
3365251538Srpaulo	urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
3366251538Srpaulo	    urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
3367251538Srpaulo	    R92C_USB_SPECIAL_OPTION_AGG_EN);
3368251538Srpaulo	urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
3369264912Skevlo	if (sc->chip & URTWN_CHIP_88E)
3370264912Skevlo		urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4);
3371264912Skevlo	else
3372264912Skevlo		urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4);
3373251538Srpaulo	urtwn_write_1(sc, R92C_USB_AGG_TH, 8);
3374251538Srpaulo	urtwn_write_1(sc, R92C_USB_AGG_TO, 6);
3375251538Srpaulo
3376251538Srpaulo	/* Initialize beacon parameters. */
3377264912Skevlo	urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010);
3378251538Srpaulo	urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404);
3379251538Srpaulo	urtwn_write_1(sc, R92C_DRVERLYINT, 0x05);
3380251538Srpaulo	urtwn_write_1(sc, R92C_BCNDMATIM, 0x02);
3381251538Srpaulo	urtwn_write_2(sc, R92C_BCNTCFG, 0x660f);
3382251538Srpaulo
3383264912Skevlo	if (!(sc->chip & URTWN_CHIP_88E)) {
3384264912Skevlo		/* Setup AMPDU aggregation. */
3385264912Skevlo		urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631);	/* MCS7~0 */
3386264912Skevlo		urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
3387264912Skevlo		urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708);
3388251538Srpaulo
3389264912Skevlo		urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
3390264912Skevlo	}
3391251538Srpaulo
3392251538Srpaulo	/* Load 8051 microcode. */
3393251538Srpaulo	error = urtwn_load_firmware(sc);
3394251538Srpaulo	if (error != 0)
3395251538Srpaulo		goto fail;
3396251538Srpaulo
3397251538Srpaulo	/* Initialize MAC/BB/RF blocks. */
3398251538Srpaulo	urtwn_mac_init(sc);
3399251538Srpaulo	urtwn_bb_init(sc);
3400251538Srpaulo	urtwn_rf_init(sc);
3401251538Srpaulo
3402264912Skevlo	if (sc->chip & URTWN_CHIP_88E) {
3403264912Skevlo		urtwn_write_2(sc, R92C_CR,
3404264912Skevlo		    urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN |
3405264912Skevlo		    R92C_CR_MACRXEN);
3406264912Skevlo	}
3407264912Skevlo
3408251538Srpaulo	/* Turn CCK and OFDM blocks on. */
3409251538Srpaulo	reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
3410251538Srpaulo	reg |= R92C_RFMOD_CCK_EN;
3411251538Srpaulo	urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
3412251538Srpaulo	reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
3413251538Srpaulo	reg |= R92C_RFMOD_OFDM_EN;
3414251538Srpaulo	urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
3415251538Srpaulo
3416251538Srpaulo	/* Clear per-station keys table. */
3417251538Srpaulo	urtwn_cam_init(sc);
3418251538Srpaulo
3419251538Srpaulo	/* Enable hardware sequence numbering. */
3420251538Srpaulo	urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff);
3421251538Srpaulo
3422251538Srpaulo	/* Perform LO and IQ calibrations. */
3423251538Srpaulo	urtwn_iq_calib(sc);
3424251538Srpaulo	/* Perform LC calibration. */
3425251538Srpaulo	urtwn_lc_calib(sc);
3426251538Srpaulo
3427251538Srpaulo	/* Fix USB interference issue. */
3428264912Skevlo	if (!(sc->chip & URTWN_CHIP_88E)) {
3429264912Skevlo		urtwn_write_1(sc, 0xfe40, 0xe0);
3430264912Skevlo		urtwn_write_1(sc, 0xfe41, 0x8d);
3431264912Skevlo		urtwn_write_1(sc, 0xfe42, 0x80);
3432251538Srpaulo
3433264912Skevlo		urtwn_pa_bias_init(sc);
3434264912Skevlo	}
3435251538Srpaulo
3436251538Srpaulo	/* Initialize GPIO setting. */
3437251538Srpaulo	urtwn_write_1(sc, R92C_GPIO_MUXCFG,
3438251538Srpaulo	    urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT);
3439251538Srpaulo
3440251538Srpaulo	/* Fix for lower temperature. */
3441264912Skevlo	if (!(sc->chip & URTWN_CHIP_88E))
3442264912Skevlo		urtwn_write_1(sc, 0x15, 0xe9);
3443251538Srpaulo
3444251538Srpaulo	usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]);
3445251538Srpaulo
3446251538Srpaulo	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3447251538Srpaulo	ifp->if_drv_flags |= IFF_DRV_RUNNING;
3448251538Srpaulo
3449251538Srpaulo	callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
3450251538Srpaulofail:
3451251538Srpaulo	return;
3452251538Srpaulo}
3453251538Srpaulo
3454251538Srpaulostatic void
3455251538Srpaulourtwn_init(void *arg)
3456251538Srpaulo{
3457251538Srpaulo	struct urtwn_softc *sc = arg;
3458251538Srpaulo
3459251538Srpaulo	URTWN_LOCK(sc);
3460251538Srpaulo	urtwn_init_locked(arg);
3461251538Srpaulo	URTWN_UNLOCK(sc);
3462251538Srpaulo}
3463251538Srpaulo
3464251538Srpaulostatic void
3465263153Skevlourtwn_stop_locked(struct ifnet *ifp)
3466251538Srpaulo{
3467251538Srpaulo	struct urtwn_softc *sc = ifp->if_softc;
3468251538Srpaulo
3469264864Skevlo	URTWN_ASSERT_LOCKED(sc);
3470264864Skevlo
3471251538Srpaulo	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3472251538Srpaulo
3473251538Srpaulo	callout_stop(&sc->sc_watchdog_ch);
3474251538Srpaulo	urtwn_abort_xfers(sc);
3475251538Srpaulo}
3476251538Srpaulo
3477251538Srpaulostatic void
3478263153Skevlourtwn_stop(struct ifnet *ifp)
3479251538Srpaulo{
3480251538Srpaulo	struct urtwn_softc *sc = ifp->if_softc;
3481251538Srpaulo
3482251538Srpaulo	URTWN_LOCK(sc);
3483263153Skevlo	urtwn_stop_locked(ifp);
3484251538Srpaulo	URTWN_UNLOCK(sc);
3485251538Srpaulo}
3486251538Srpaulo
3487251538Srpaulostatic void
3488251538Srpaulourtwn_abort_xfers(struct urtwn_softc *sc)
3489251538Srpaulo{
3490251538Srpaulo	int i;
3491251538Srpaulo
3492251538Srpaulo	URTWN_ASSERT_LOCKED(sc);
3493251538Srpaulo
3494251538Srpaulo	/* abort any pending transfers */
3495251538Srpaulo	for (i = 0; i < URTWN_N_TRANSFER; i++)
3496251538Srpaulo		usbd_transfer_stop(sc->sc_xfer[i]);
3497251538Srpaulo}
3498251538Srpaulo
3499251538Srpaulostatic int
3500251538Srpaulourtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
3501251538Srpaulo    const struct ieee80211_bpf_params *params)
3502251538Srpaulo{
3503251538Srpaulo	struct ieee80211com *ic = ni->ni_ic;
3504251538Srpaulo	struct ifnet *ifp = ic->ic_ifp;
3505251538Srpaulo	struct urtwn_softc *sc = ifp->if_softc;
3506251538Srpaulo	struct urtwn_data *bf;
3507251538Srpaulo
3508251538Srpaulo	/* prevent management frames from being sent if we're not ready */
3509251538Srpaulo	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3510251538Srpaulo		m_freem(m);
3511251538Srpaulo		ieee80211_free_node(ni);
3512251538Srpaulo		return (ENETDOWN);
3513251538Srpaulo	}
3514251538Srpaulo	URTWN_LOCK(sc);
3515251538Srpaulo	bf = urtwn_getbuf(sc);
3516251538Srpaulo	if (bf == NULL) {
3517251538Srpaulo		ieee80211_free_node(ni);
3518251538Srpaulo		m_freem(m);
3519251538Srpaulo		URTWN_UNLOCK(sc);
3520251538Srpaulo		return (ENOBUFS);
3521251538Srpaulo	}
3522251538Srpaulo
3523251538Srpaulo	ifp->if_opackets++;
3524251538Srpaulo	if (urtwn_tx_start(sc, ni, m, bf) != 0) {
3525251538Srpaulo		ieee80211_free_node(ni);
3526251538Srpaulo		ifp->if_oerrors++;
3527251538Srpaulo		STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
3528251538Srpaulo		URTWN_UNLOCK(sc);
3529251538Srpaulo		return (EIO);
3530251538Srpaulo	}
3531251538Srpaulo	URTWN_UNLOCK(sc);
3532251538Srpaulo
3533251538Srpaulo	sc->sc_txtimer = 5;
3534251538Srpaulo	return (0);
3535251538Srpaulo}
3536251538Srpaulo
3537266472Shselaskystatic void
3538266472Shselaskyurtwn_ms_delay(struct urtwn_softc *sc)
3539266472Shselasky{
3540266472Shselasky	usb_pause_mtx(&sc->sc_mtx, hz / 1000);
3541266472Shselasky}
3542266472Shselasky
3543251538Srpaulostatic device_method_t urtwn_methods[] = {
3544251538Srpaulo	/* Device interface */
3545251538Srpaulo	DEVMETHOD(device_probe,		urtwn_match),
3546251538Srpaulo	DEVMETHOD(device_attach,	urtwn_attach),
3547251538Srpaulo	DEVMETHOD(device_detach,	urtwn_detach),
3548251538Srpaulo
3549264912Skevlo	DEVMETHOD_END
3550251538Srpaulo};
3551251538Srpaulo
3552251538Srpaulostatic driver_t urtwn_driver = {
3553251538Srpaulo	"urtwn",
3554251538Srpaulo	urtwn_methods,
3555251538Srpaulo	sizeof(struct urtwn_softc)
3556251538Srpaulo};
3557251538Srpaulo
3558251538Srpaulostatic devclass_t urtwn_devclass;
3559251538Srpaulo
3560251538SrpauloDRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL);
3561251538SrpauloMODULE_DEPEND(urtwn, usb, 1, 1, 1);
3562251538SrpauloMODULE_DEPEND(urtwn, wlan, 1, 1, 1);
3563251538SrpauloMODULE_DEPEND(urtwn, firmware, 1, 1, 1);
3564251538SrpauloMODULE_VERSION(urtwn, 1);
3565