if_urtwn.c revision 264982
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 264982 2014-04-26 19:30:04Z andreast $"); 22 23/* 24 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25 */ 26 27#include <sys/param.h> 28#include <sys/sockio.h> 29#include <sys/sysctl.h> 30#include <sys/lock.h> 31#include <sys/mutex.h> 32#include <sys/mbuf.h> 33#include <sys/kernel.h> 34#include <sys/socket.h> 35#include <sys/systm.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/bus.h> 39#include <sys/endian.h> 40#include <sys/linker.h> 41#include <sys/firmware.h> 42#include <sys/kdb.h> 43 44#include <machine/bus.h> 45#include <machine/resource.h> 46#include <sys/rman.h> 47 48#include <net/bpf.h> 49#include <net/if.h> 50#include <net/if_var.h> 51#include <net/if_arp.h> 52#include <net/ethernet.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55#include <net/if_types.h> 56 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/if_ether.h> 61#include <netinet/ip.h> 62 63#include <net80211/ieee80211_var.h> 64#include <net80211/ieee80211_regdomain.h> 65#include <net80211/ieee80211_radiotap.h> 66#include <net80211/ieee80211_ratectl.h> 67 68#include <dev/usb/usb.h> 69#include <dev/usb/usbdi.h> 70#include "usbdevs.h" 71 72#define USB_DEBUG_VAR urtwn_debug 73#include <dev/usb/usb_debug.h> 74 75#include <dev/usb/wlan/if_urtwnreg.h> 76 77#ifdef USB_DEBUG 78static int urtwn_debug = 0; 79 80SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 81SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RW, &urtwn_debug, 0, 82 "Debug level"); 83#endif 84 85#define URTWN_RSSI(r) (r) - 110 86#define IEEE80211_HAS_ADDR4(wh) \ 87 (((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) 88 89/* various supported device vendors/products */ 90static const STRUCT_USB_HOST_ID urtwn_devs[] = { 91#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 92#define URTWN_RTL8188E_DEV(v,p) \ 93 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 94#define URTWN_RTL8188E 1 95 URTWN_DEV(ABOCOM, RTL8188CU_1), 96 URTWN_DEV(ABOCOM, RTL8188CU_2), 97 URTWN_DEV(ABOCOM, RTL8192CU), 98 URTWN_DEV(ASUS, RTL8192CU), 99 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 100 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 101 URTWN_DEV(AZUREWAVE, RTL8188CU), 102 URTWN_DEV(BELKIN, F7D2102), 103 URTWN_DEV(BELKIN, RTL8188CU), 104 URTWN_DEV(BELKIN, RTL8192CU), 105 URTWN_DEV(CHICONY, RTL8188CUS_1), 106 URTWN_DEV(CHICONY, RTL8188CUS_2), 107 URTWN_DEV(CHICONY, RTL8188CUS_3), 108 URTWN_DEV(CHICONY, RTL8188CUS_4), 109 URTWN_DEV(CHICONY, RTL8188CUS_5), 110 URTWN_DEV(COREGA, RTL8192CU), 111 URTWN_DEV(DLINK, RTL8188CU), 112 URTWN_DEV(DLINK, RTL8192CU_1), 113 URTWN_DEV(DLINK, RTL8192CU_2), 114 URTWN_DEV(DLINK, RTL8192CU_3), 115 URTWN_DEV(DLINK, DWA131B), 116 URTWN_DEV(EDIMAX, EW7811UN), 117 URTWN_DEV(EDIMAX, RTL8192CU), 118 URTWN_DEV(FEIXUN, RTL8188CU), 119 URTWN_DEV(FEIXUN, RTL8192CU), 120 URTWN_DEV(GUILLEMOT, HWNUP150), 121 URTWN_DEV(HAWKING, RTL8192CU), 122 URTWN_DEV(HP3, RTL8188CU), 123 URTWN_DEV(NETGEAR, WNA1000M), 124 URTWN_DEV(NETGEAR, RTL8192CU), 125 URTWN_DEV(NETGEAR4, RTL8188CU), 126 URTWN_DEV(NOVATECH, RTL8188CU), 127 URTWN_DEV(PLANEX2, RTL8188CU_1), 128 URTWN_DEV(PLANEX2, RTL8188CU_2), 129 URTWN_DEV(PLANEX2, RTL8188CU_3), 130 URTWN_DEV(PLANEX2, RTL8188CU_4), 131 URTWN_DEV(PLANEX2, RTL8188CUS), 132 URTWN_DEV(PLANEX2, RTL8192CU), 133 URTWN_DEV(REALTEK, RTL8188CE_0), 134 URTWN_DEV(REALTEK, RTL8188CE_1), 135 URTWN_DEV(REALTEK, RTL8188CTV), 136 URTWN_DEV(REALTEK, RTL8188CU_0), 137 URTWN_DEV(REALTEK, RTL8188CU_1), 138 URTWN_DEV(REALTEK, RTL8188CU_2), 139 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 140 URTWN_DEV(REALTEK, RTL8188CUS), 141 URTWN_DEV(REALTEK, RTL8188RU_1), 142 URTWN_DEV(REALTEK, RTL8188RU_2), 143 URTWN_DEV(REALTEK, RTL8191CU), 144 URTWN_DEV(REALTEK, RTL8192CE), 145 URTWN_DEV(REALTEK, RTL8192CU), 146 URTWN_DEV(REALTEK, RTL8188CU_0), 147 URTWN_DEV(SITECOMEU, RTL8188CU_1), 148 URTWN_DEV(SITECOMEU, RTL8188CU_2), 149 URTWN_DEV(SITECOMEU, RTL8192CU), 150 URTWN_DEV(TRENDNET, RTL8188CU), 151 URTWN_DEV(TRENDNET, RTL8192CU), 152 URTWN_DEV(ZYXEL, RTL8192CU), 153 /* URTWN_RTL8188E */ 154 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 155 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 156#undef URTWN_RTL8188E_DEV 157#undef URTWN_DEV 158}; 159 160static device_probe_t urtwn_match; 161static device_attach_t urtwn_attach; 162static device_detach_t urtwn_detach; 163 164static usb_callback_t urtwn_bulk_tx_callback; 165static usb_callback_t urtwn_bulk_rx_callback; 166 167static usb_error_t urtwn_do_request(struct urtwn_softc *sc, 168 struct usb_device_request *req, void *data); 169static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 170 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 171 const uint8_t [IEEE80211_ADDR_LEN], 172 const uint8_t [IEEE80211_ADDR_LEN]); 173static void urtwn_vap_delete(struct ieee80211vap *); 174static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 175 int *); 176static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 177 int *, int8_t *); 178static void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 179static int urtwn_alloc_list(struct urtwn_softc *, 180 struct urtwn_data[], int, int); 181static int urtwn_alloc_rx_list(struct urtwn_softc *); 182static int urtwn_alloc_tx_list(struct urtwn_softc *); 183static void urtwn_free_tx_list(struct urtwn_softc *); 184static void urtwn_free_rx_list(struct urtwn_softc *); 185static void urtwn_free_list(struct urtwn_softc *, 186 struct urtwn_data data[], int); 187static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 188static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 189static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 190 uint8_t *, int); 191static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 192static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 193static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 194static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 195 uint8_t *, int); 196static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 197static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 198static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 199static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 200 const void *, int); 201static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 202 uint8_t, uint32_t); 203static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 204 uint8_t, uint32_t); 205static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 206static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 207 uint32_t); 208static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 209static void urtwn_efuse_read(struct urtwn_softc *); 210static void urtwn_efuse_switch_power(struct urtwn_softc *); 211static int urtwn_read_chipid(struct urtwn_softc *); 212static void urtwn_read_rom(struct urtwn_softc *); 213static void urtwn_r88e_read_rom(struct urtwn_softc *); 214static int urtwn_ra_init(struct urtwn_softc *); 215static void urtwn_tsf_sync_enable(struct urtwn_softc *); 216static void urtwn_set_led(struct urtwn_softc *, int, int); 217static int urtwn_newstate(struct ieee80211vap *, 218 enum ieee80211_state, int); 219static void urtwn_watchdog(void *); 220static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 221static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 222static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 223static int urtwn_tx_start(struct urtwn_softc *, 224 struct ieee80211_node *, struct mbuf *, 225 struct urtwn_data *); 226static void urtwn_start(struct ifnet *); 227static void urtwn_start_locked(struct ifnet *, 228 struct urtwn_softc *); 229static int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 230static int urtwn_r92c_power_on(struct urtwn_softc *); 231static int urtwn_r88e_power_on(struct urtwn_softc *); 232static int urtwn_llt_init(struct urtwn_softc *); 233static void urtwn_fw_reset(struct urtwn_softc *); 234static void urtwn_r88e_fw_reset(struct urtwn_softc *); 235static int urtwn_fw_loadpage(struct urtwn_softc *, int, 236 const uint8_t *, int); 237static int urtwn_load_firmware(struct urtwn_softc *); 238static int urtwn_r92c_dma_init(struct urtwn_softc *); 239static int urtwn_r88e_dma_init(struct urtwn_softc *); 240static void urtwn_mac_init(struct urtwn_softc *); 241static void urtwn_bb_init(struct urtwn_softc *); 242static void urtwn_rf_init(struct urtwn_softc *); 243static void urtwn_cam_init(struct urtwn_softc *); 244static void urtwn_pa_bias_init(struct urtwn_softc *); 245static void urtwn_rxfilter_init(struct urtwn_softc *); 246static void urtwn_edca_init(struct urtwn_softc *); 247static void urtwn_write_txpower(struct urtwn_softc *, int, 248 uint16_t[]); 249static void urtwn_get_txpower(struct urtwn_softc *, int, 250 struct ieee80211_channel *, 251 struct ieee80211_channel *, uint16_t[]); 252static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 253 struct ieee80211_channel *, 254 struct ieee80211_channel *, uint16_t[]); 255static void urtwn_set_txpower(struct urtwn_softc *, 256 struct ieee80211_channel *, 257 struct ieee80211_channel *); 258static void urtwn_scan_start(struct ieee80211com *); 259static void urtwn_scan_end(struct ieee80211com *); 260static void urtwn_set_channel(struct ieee80211com *); 261static void urtwn_set_chan(struct urtwn_softc *, 262 struct ieee80211_channel *, 263 struct ieee80211_channel *); 264static void urtwn_update_mcast(struct ifnet *); 265static void urtwn_iq_calib(struct urtwn_softc *); 266static void urtwn_lc_calib(struct urtwn_softc *); 267static void urtwn_init(void *); 268static void urtwn_init_locked(void *); 269static void urtwn_stop(struct ifnet *); 270static void urtwn_stop_locked(struct ifnet *); 271static void urtwn_abort_xfers(struct urtwn_softc *); 272static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 273 const struct ieee80211_bpf_params *); 274 275/* Aliases. */ 276#define urtwn_bb_write urtwn_write_4 277#define urtwn_bb_read urtwn_read_4 278 279static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 280 [URTWN_BULK_RX] = { 281 .type = UE_BULK, 282 .endpoint = UE_ADDR_ANY, 283 .direction = UE_DIR_IN, 284 .bufsize = URTWN_RXBUFSZ, 285 .flags = { 286 .pipe_bof = 1, 287 .short_xfer_ok = 1 288 }, 289 .callback = urtwn_bulk_rx_callback, 290 }, 291 [URTWN_BULK_TX_BE] = { 292 .type = UE_BULK, 293 .endpoint = 0x03, 294 .direction = UE_DIR_OUT, 295 .bufsize = URTWN_TXBUFSZ, 296 .flags = { 297 .ext_buffer = 1, 298 .pipe_bof = 1, 299 .force_short_xfer = 1 300 }, 301 .callback = urtwn_bulk_tx_callback, 302 .timeout = URTWN_TX_TIMEOUT, /* ms */ 303 }, 304 [URTWN_BULK_TX_BK] = { 305 .type = UE_BULK, 306 .endpoint = 0x03, 307 .direction = UE_DIR_OUT, 308 .bufsize = URTWN_TXBUFSZ, 309 .flags = { 310 .ext_buffer = 1, 311 .pipe_bof = 1, 312 .force_short_xfer = 1, 313 }, 314 .callback = urtwn_bulk_tx_callback, 315 .timeout = URTWN_TX_TIMEOUT, /* ms */ 316 }, 317 [URTWN_BULK_TX_VI] = { 318 .type = UE_BULK, 319 .endpoint = 0x02, 320 .direction = UE_DIR_OUT, 321 .bufsize = URTWN_TXBUFSZ, 322 .flags = { 323 .ext_buffer = 1, 324 .pipe_bof = 1, 325 .force_short_xfer = 1 326 }, 327 .callback = urtwn_bulk_tx_callback, 328 .timeout = URTWN_TX_TIMEOUT, /* ms */ 329 }, 330 [URTWN_BULK_TX_VO] = { 331 .type = UE_BULK, 332 .endpoint = 0x02, 333 .direction = UE_DIR_OUT, 334 .bufsize = URTWN_TXBUFSZ, 335 .flags = { 336 .ext_buffer = 1, 337 .pipe_bof = 1, 338 .force_short_xfer = 1 339 }, 340 .callback = urtwn_bulk_tx_callback, 341 .timeout = URTWN_TX_TIMEOUT, /* ms */ 342 }, 343}; 344 345static int 346urtwn_match(device_t self) 347{ 348 struct usb_attach_arg *uaa = device_get_ivars(self); 349 350 if (uaa->usb_mode != USB_MODE_HOST) 351 return (ENXIO); 352 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 353 return (ENXIO); 354 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 355 return (ENXIO); 356 357 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 358} 359 360static int 361urtwn_attach(device_t self) 362{ 363 struct usb_attach_arg *uaa = device_get_ivars(self); 364 struct urtwn_softc *sc = device_get_softc(self); 365 struct ifnet *ifp; 366 struct ieee80211com *ic; 367 uint8_t iface_index, bands; 368 int error; 369 370 device_set_usb_desc(self); 371 sc->sc_udev = uaa->device; 372 sc->sc_dev = self; 373 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 374 sc->chip |= URTWN_CHIP_88E; 375 376 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 377 MTX_NETWORK_LOCK, MTX_DEF); 378 callout_init(&sc->sc_watchdog_ch, 0); 379 380 iface_index = URTWN_IFACE_INDEX; 381 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 382 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 383 if (error) { 384 device_printf(self, "could not allocate USB transfers, " 385 "err=%s\n", usbd_errstr(error)); 386 goto detach; 387 } 388 389 URTWN_LOCK(sc); 390 391 error = urtwn_read_chipid(sc); 392 if (error) { 393 device_printf(sc->sc_dev, "unsupported test chip\n"); 394 URTWN_UNLOCK(sc); 395 goto detach; 396 } 397 398 /* Determine number of Tx/Rx chains. */ 399 if (sc->chip & URTWN_CHIP_92C) { 400 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 401 sc->nrxchains = 2; 402 } else { 403 sc->ntxchains = 1; 404 sc->nrxchains = 1; 405 } 406 407 if (sc->chip & URTWN_CHIP_88E) 408 urtwn_r88e_read_rom(sc); 409 else 410 urtwn_read_rom(sc); 411 412 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 413 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 414 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 415 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 416 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 417 "8188CUS", sc->ntxchains, sc->nrxchains); 418 419 URTWN_UNLOCK(sc); 420 421 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 422 if (ifp == NULL) { 423 device_printf(sc->sc_dev, "can not if_alloc()\n"); 424 goto detach; 425 } 426 ic = ifp->if_l2com; 427 428 ifp->if_softc = sc; 429 if_initname(ifp, "urtwn", device_get_unit(sc->sc_dev)); 430 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 431 ifp->if_init = urtwn_init; 432 ifp->if_ioctl = urtwn_ioctl; 433 ifp->if_start = urtwn_start; 434 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 435 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 436 IFQ_SET_READY(&ifp->if_snd); 437 438 ic->ic_ifp = ifp; 439 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 440 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 441 442 /* set device capabilities */ 443 ic->ic_caps = 444 IEEE80211_C_STA /* station mode */ 445 | IEEE80211_C_MONITOR /* monitor mode */ 446 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 447 | IEEE80211_C_SHSLOT /* short slot time supported */ 448 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 449 | IEEE80211_C_WPA /* 802.11i */ 450 ; 451 452 bands = 0; 453 setbit(&bands, IEEE80211_MODE_11B); 454 setbit(&bands, IEEE80211_MODE_11G); 455 ieee80211_init_channels(ic, NULL, &bands); 456 457 ieee80211_ifattach(ic, sc->sc_bssid); 458 ic->ic_raw_xmit = urtwn_raw_xmit; 459 ic->ic_scan_start = urtwn_scan_start; 460 ic->ic_scan_end = urtwn_scan_end; 461 ic->ic_set_channel = urtwn_set_channel; 462 463 ic->ic_vap_create = urtwn_vap_create; 464 ic->ic_vap_delete = urtwn_vap_delete; 465 ic->ic_update_mcast = urtwn_update_mcast; 466 467 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 468 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 469 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 470 URTWN_RX_RADIOTAP_PRESENT); 471 472 if (bootverbose) 473 ieee80211_announce(ic); 474 475 return (0); 476 477detach: 478 urtwn_detach(self); 479 return (ENXIO); /* failure */ 480} 481 482static int 483urtwn_detach(device_t self) 484{ 485 struct urtwn_softc *sc = device_get_softc(self); 486 struct ifnet *ifp = sc->sc_ifp; 487 struct ieee80211com *ic = ifp->if_l2com; 488 unsigned int x; 489 490 /* Prevent further ioctls. */ 491 URTWN_LOCK(sc); 492 sc->sc_flags |= URTWN_DETACHED; 493 URTWN_UNLOCK(sc); 494 495 urtwn_stop(ifp); 496 497 callout_drain(&sc->sc_watchdog_ch); 498 499 /* Prevent further allocations from RX/TX data lists. */ 500 URTWN_LOCK(sc); 501 STAILQ_INIT(&sc->sc_tx_active); 502 STAILQ_INIT(&sc->sc_tx_inactive); 503 STAILQ_INIT(&sc->sc_tx_pending); 504 505 STAILQ_INIT(&sc->sc_rx_active); 506 STAILQ_INIT(&sc->sc_rx_inactive); 507 URTWN_UNLOCK(sc); 508 509 /* drain USB transfers */ 510 for (x = 0; x != URTWN_N_TRANSFER; x++) 511 usbd_transfer_drain(sc->sc_xfer[x]); 512 513 /* Free data buffers. */ 514 URTWN_LOCK(sc); 515 urtwn_free_tx_list(sc); 516 urtwn_free_rx_list(sc); 517 URTWN_UNLOCK(sc); 518 519 /* stop all USB transfers */ 520 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 521 ieee80211_ifdetach(ic); 522 523 if_free(ifp); 524 mtx_destroy(&sc->sc_mtx); 525 526 return (0); 527} 528 529static void 530urtwn_free_tx_list(struct urtwn_softc *sc) 531{ 532 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 533} 534 535static void 536urtwn_free_rx_list(struct urtwn_softc *sc) 537{ 538 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 539} 540 541static void 542urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 543{ 544 int i; 545 546 for (i = 0; i < ndata; i++) { 547 struct urtwn_data *dp = &data[i]; 548 549 if (dp->buf != NULL) { 550 free(dp->buf, M_USBDEV); 551 dp->buf = NULL; 552 } 553 if (dp->ni != NULL) { 554 ieee80211_free_node(dp->ni); 555 dp->ni = NULL; 556 } 557 } 558} 559 560static usb_error_t 561urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 562 void *data) 563{ 564 usb_error_t err; 565 int ntries = 10; 566 567 URTWN_ASSERT_LOCKED(sc); 568 569 while (ntries--) { 570 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 571 req, data, 0, NULL, 250 /* ms */); 572 if (err == 0) 573 break; 574 575 DPRINTFN(1, "Control request failed, %s (retrying)\n", 576 usbd_errstr(err)); 577 usb_pause_mtx(&sc->sc_mtx, hz / 100); 578 } 579 return (err); 580} 581 582static struct ieee80211vap * 583urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 584 enum ieee80211_opmode opmode, int flags, 585 const uint8_t bssid[IEEE80211_ADDR_LEN], 586 const uint8_t mac[IEEE80211_ADDR_LEN]) 587{ 588 struct urtwn_vap *uvp; 589 struct ieee80211vap *vap; 590 591 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 592 return (NULL); 593 594 uvp = (struct urtwn_vap *) malloc(sizeof(struct urtwn_vap), 595 M_80211_VAP, M_NOWAIT | M_ZERO); 596 if (uvp == NULL) 597 return (NULL); 598 vap = &uvp->vap; 599 /* enable s/w bmiss handling for sta mode */ 600 601 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 602 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac) != 0) { 603 /* out of memory */ 604 free(uvp, M_80211_VAP); 605 return (NULL); 606 } 607 608 /* override state transition machine */ 609 uvp->newstate = vap->iv_newstate; 610 vap->iv_newstate = urtwn_newstate; 611 612 /* complete setup */ 613 ieee80211_vap_attach(vap, ieee80211_media_change, 614 ieee80211_media_status); 615 ic->ic_opmode = opmode; 616 return (vap); 617} 618 619static void 620urtwn_vap_delete(struct ieee80211vap *vap) 621{ 622 struct urtwn_vap *uvp = URTWN_VAP(vap); 623 624 ieee80211_vap_detach(vap); 625 free(uvp, M_80211_VAP); 626} 627 628static struct mbuf * 629urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 630{ 631 struct ifnet *ifp = sc->sc_ifp; 632 struct ieee80211com *ic = ifp->if_l2com; 633 struct ieee80211_frame *wh; 634 struct mbuf *m; 635 struct r92c_rx_stat *stat; 636 uint32_t rxdw0, rxdw3; 637 uint8_t rate; 638 int8_t rssi = 0; 639 int infosz; 640 641 /* 642 * don't pass packets to the ieee80211 framework if the driver isn't 643 * RUNNING. 644 */ 645 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 646 return (NULL); 647 648 stat = (struct r92c_rx_stat *)buf; 649 rxdw0 = le32toh(stat->rxdw0); 650 rxdw3 = le32toh(stat->rxdw3); 651 652 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 653 /* 654 * This should not happen since we setup our Rx filter 655 * to not receive these frames. 656 */ 657 ifp->if_ierrors++; 658 return (NULL); 659 } 660 661 rate = MS(rxdw3, R92C_RXDW3_RATE); 662 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 663 664 /* Get RSSI from PHY status descriptor if present. */ 665 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 666 if (sc->chip & URTWN_CHIP_88E) 667 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 668 else 669 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 670 /* Update our average RSSI. */ 671 urtwn_update_avgrssi(sc, rate, rssi); 672 /* 673 * Convert the RSSI to a range that will be accepted 674 * by net80211. 675 */ 676 rssi = URTWN_RSSI(rssi); 677 } 678 679 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 680 if (m == NULL) { 681 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 682 return (NULL); 683 } 684 685 /* Finalize mbuf. */ 686 m->m_pkthdr.rcvif = ifp; 687 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 688 memcpy(mtod(m, uint8_t *), wh, pktlen); 689 m->m_pkthdr.len = m->m_len = pktlen; 690 691 if (ieee80211_radiotap_active(ic)) { 692 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 693 694 tap->wr_flags = 0; 695 /* Map HW rate index to 802.11 rate. */ 696 if (!(rxdw3 & R92C_RXDW3_HT)) { 697 switch (rate) { 698 /* CCK. */ 699 case 0: tap->wr_rate = 2; break; 700 case 1: tap->wr_rate = 4; break; 701 case 2: tap->wr_rate = 11; break; 702 case 3: tap->wr_rate = 22; break; 703 /* OFDM. */ 704 case 4: tap->wr_rate = 12; break; 705 case 5: tap->wr_rate = 18; break; 706 case 6: tap->wr_rate = 24; break; 707 case 7: tap->wr_rate = 36; break; 708 case 8: tap->wr_rate = 48; break; 709 case 9: tap->wr_rate = 72; break; 710 case 10: tap->wr_rate = 96; break; 711 case 11: tap->wr_rate = 108; break; 712 } 713 } else if (rate >= 12) { /* MCS0~15. */ 714 /* Bit 7 set means HT MCS instead of rate. */ 715 tap->wr_rate = 0x80 | (rate - 12); 716 } 717 tap->wr_dbm_antsignal = rssi; 718 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 719 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 720 } 721 722 *rssi_p = rssi; 723 724 return (m); 725} 726 727static struct mbuf * 728urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 729 int8_t *nf) 730{ 731 struct urtwn_softc *sc = data->sc; 732 struct ifnet *ifp = sc->sc_ifp; 733 struct r92c_rx_stat *stat; 734 struct mbuf *m, *m0 = NULL, *prevm = NULL; 735 uint32_t rxdw0; 736 uint8_t *buf; 737 int len, totlen, pktlen, infosz, npkts; 738 739 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 740 741 if (len < sizeof(*stat)) { 742 ifp->if_ierrors++; 743 return (NULL); 744 } 745 746 buf = data->buf; 747 /* Get the number of encapsulated frames. */ 748 stat = (struct r92c_rx_stat *)buf; 749 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 750 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 751 752 /* Process all of them. */ 753 while (npkts-- > 0) { 754 if (len < sizeof(*stat)) 755 break; 756 stat = (struct r92c_rx_stat *)buf; 757 rxdw0 = le32toh(stat->rxdw0); 758 759 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 760 if (pktlen == 0) 761 break; 762 763 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 764 765 /* Make sure everything fits in xfer. */ 766 totlen = sizeof(*stat) + infosz + pktlen; 767 if (totlen > len) 768 break; 769 770 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 771 if (m0 == NULL) 772 m0 = m; 773 if (prevm == NULL) 774 prevm = m; 775 else { 776 prevm->m_next = m; 777 prevm = m; 778 } 779 780 /* Next chunk is 128-byte aligned. */ 781 totlen = (totlen + 127) & ~127; 782 buf += totlen; 783 len -= totlen; 784 } 785 786 return (m0); 787} 788 789static void 790urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 791{ 792 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 793 struct ifnet *ifp = sc->sc_ifp; 794 struct ieee80211com *ic = ifp->if_l2com; 795 struct ieee80211_frame *wh; 796 struct ieee80211_node *ni; 797 struct mbuf *m = NULL, *next; 798 struct urtwn_data *data; 799 int8_t nf; 800 int rssi = 1; 801 802 URTWN_ASSERT_LOCKED(sc); 803 804 switch (USB_GET_STATE(xfer)) { 805 case USB_ST_TRANSFERRED: 806 data = STAILQ_FIRST(&sc->sc_rx_active); 807 if (data == NULL) 808 goto tr_setup; 809 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 810 m = urtwn_rxeof(xfer, data, &rssi, &nf); 811 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 812 /* FALLTHROUGH */ 813 case USB_ST_SETUP: 814tr_setup: 815 data = STAILQ_FIRST(&sc->sc_rx_inactive); 816 if (data == NULL) { 817 KASSERT(m == NULL, ("mbuf isn't NULL")); 818 return; 819 } 820 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 821 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 822 usbd_xfer_set_frame_data(xfer, 0, data->buf, 823 usbd_xfer_max_len(xfer)); 824 usbd_transfer_submit(xfer); 825 826 /* 827 * To avoid LOR we should unlock our private mutex here to call 828 * ieee80211_input() because here is at the end of a USB 829 * callback and safe to unlock. 830 */ 831 URTWN_UNLOCK(sc); 832 while (m != NULL) { 833 next = m->m_next; 834 m->m_next = NULL; 835 wh = mtod(m, struct ieee80211_frame *); 836 ni = ieee80211_find_rxnode(ic, 837 (struct ieee80211_frame_min *)wh); 838 nf = URTWN_NOISE_FLOOR; 839 if (ni != NULL) { 840 (void)ieee80211_input(ni, m, rssi, nf); 841 ieee80211_free_node(ni); 842 } else 843 (void)ieee80211_input_all(ic, m, rssi, nf); 844 m = next; 845 } 846 URTWN_LOCK(sc); 847 break; 848 default: 849 /* needs it to the inactive queue due to a error. */ 850 data = STAILQ_FIRST(&sc->sc_rx_active); 851 if (data != NULL) { 852 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 853 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 854 } 855 if (error != USB_ERR_CANCELLED) { 856 usbd_xfer_set_stall(xfer); 857 ifp->if_ierrors++; 858 goto tr_setup; 859 } 860 break; 861 } 862} 863 864static void 865urtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 866{ 867 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 868 struct ifnet *ifp = sc->sc_ifp; 869 struct mbuf *m; 870 871 URTWN_ASSERT_LOCKED(sc); 872 873 /* 874 * Do any tx complete callback. Note this must be done before releasing 875 * the node reference. 876 */ 877 if (data->m) { 878 m = data->m; 879 if (m->m_flags & M_TXCB) { 880 /* XXX status? */ 881 ieee80211_process_callback(data->ni, m, 0); 882 } 883 m_freem(m); 884 data->m = NULL; 885 } 886 if (data->ni) { 887 ieee80211_free_node(data->ni); 888 data->ni = NULL; 889 } 890 sc->sc_txtimer = 0; 891 ifp->if_opackets++; 892 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 893} 894 895static void 896urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 897{ 898 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 899 struct ifnet *ifp = sc->sc_ifp; 900 struct urtwn_data *data; 901 902 URTWN_ASSERT_LOCKED(sc); 903 904 switch (USB_GET_STATE(xfer)){ 905 case USB_ST_TRANSFERRED: 906 data = STAILQ_FIRST(&sc->sc_tx_active); 907 if (data == NULL) 908 goto tr_setup; 909 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 910 urtwn_txeof(xfer, data); 911 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 912 /* FALLTHROUGH */ 913 case USB_ST_SETUP: 914tr_setup: 915 data = STAILQ_FIRST(&sc->sc_tx_pending); 916 if (data == NULL) { 917 DPRINTF("%s: empty pending queue\n", __func__); 918 return; 919 } 920 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 921 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 922 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 923 usbd_transfer_submit(xfer); 924 urtwn_start_locked(ifp, sc); 925 break; 926 default: 927 data = STAILQ_FIRST(&sc->sc_tx_active); 928 if (data == NULL) 929 goto tr_setup; 930 if (data->ni != NULL) { 931 ieee80211_free_node(data->ni); 932 data->ni = NULL; 933 ifp->if_oerrors++; 934 } 935 if (error != USB_ERR_CANCELLED) { 936 usbd_xfer_set_stall(xfer); 937 goto tr_setup; 938 } 939 break; 940 } 941} 942 943static struct urtwn_data * 944_urtwn_getbuf(struct urtwn_softc *sc) 945{ 946 struct urtwn_data *bf; 947 948 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 949 if (bf != NULL) 950 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 951 else 952 bf = NULL; 953 if (bf == NULL) 954 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 955 return (bf); 956} 957 958static struct urtwn_data * 959urtwn_getbuf(struct urtwn_softc *sc) 960{ 961 struct urtwn_data *bf; 962 963 URTWN_ASSERT_LOCKED(sc); 964 965 bf = _urtwn_getbuf(sc); 966 if (bf == NULL) { 967 struct ifnet *ifp = sc->sc_ifp; 968 DPRINTF("%s: stop queue\n", __func__); 969 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 970 } 971 return (bf); 972} 973 974static int 975urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 976 int len) 977{ 978 usb_device_request_t req; 979 980 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 981 req.bRequest = R92C_REQ_REGS; 982 USETW(req.wValue, addr); 983 USETW(req.wIndex, 0); 984 USETW(req.wLength, len); 985 return (urtwn_do_request(sc, &req, buf)); 986} 987 988static void 989urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 990{ 991 urtwn_write_region_1(sc, addr, &val, 1); 992} 993 994 995static void 996urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 997{ 998 val = htole16(val); 999 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1000} 1001 1002static void 1003urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1004{ 1005 val = htole32(val); 1006 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1007} 1008 1009static int 1010urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1011 int len) 1012{ 1013 usb_device_request_t req; 1014 1015 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1016 req.bRequest = R92C_REQ_REGS; 1017 USETW(req.wValue, addr); 1018 USETW(req.wIndex, 0); 1019 USETW(req.wLength, len); 1020 return (urtwn_do_request(sc, &req, buf)); 1021} 1022 1023static uint8_t 1024urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1025{ 1026 uint8_t val; 1027 1028 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1029 return (0xff); 1030 return (val); 1031} 1032 1033static uint16_t 1034urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1035{ 1036 uint16_t val; 1037 1038 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1039 return (0xffff); 1040 return (le16toh(val)); 1041} 1042 1043static uint32_t 1044urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1045{ 1046 uint32_t val; 1047 1048 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1049 return (0xffffffff); 1050 return (le32toh(val)); 1051} 1052 1053static int 1054urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1055{ 1056 struct r92c_fw_cmd cmd; 1057 int ntries; 1058 1059 /* Wait for current FW box to be empty. */ 1060 for (ntries = 0; ntries < 100; ntries++) { 1061 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1062 break; 1063 DELAY(1); 1064 } 1065 if (ntries == 100) { 1066 device_printf(sc->sc_dev, 1067 "could not send firmware command\n"); 1068 return (ETIMEDOUT); 1069 } 1070 memset(&cmd, 0, sizeof(cmd)); 1071 cmd.id = id; 1072 if (len > 3) 1073 cmd.id |= R92C_CMD_FLAG_EXT; 1074 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1075 memcpy(cmd.msg, buf, len); 1076 1077 /* Write the first word last since that will trigger the FW. */ 1078 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1079 (uint8_t *)&cmd + 4, 2); 1080 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1081 (uint8_t *)&cmd + 0, 4); 1082 1083 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1084 return (0); 1085} 1086 1087static __inline void 1088urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1089{ 1090 1091 sc->sc_rf_write(sc, chain, addr, val); 1092} 1093 1094static void 1095urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1096 uint32_t val) 1097{ 1098 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1099 SM(R92C_LSSI_PARAM_ADDR, addr) | 1100 SM(R92C_LSSI_PARAM_DATA, val)); 1101} 1102 1103static void 1104urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1105uint32_t val) 1106{ 1107 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1108 SM(R88E_LSSI_PARAM_ADDR, addr) | 1109 SM(R92C_LSSI_PARAM_DATA, val)); 1110} 1111 1112static uint32_t 1113urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1114{ 1115 uint32_t reg[R92C_MAX_CHAINS], val; 1116 1117 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1118 if (chain != 0) 1119 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1120 1121 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1122 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1123 DELAY(1000); 1124 1125 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1126 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1127 R92C_HSSI_PARAM2_READ_EDGE); 1128 DELAY(1000); 1129 1130 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1131 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1132 DELAY(1000); 1133 1134 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1135 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1136 else 1137 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1138 return (MS(val, R92C_LSSI_READBACK_DATA)); 1139} 1140 1141static int 1142urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1143{ 1144 int ntries; 1145 1146 urtwn_write_4(sc, R92C_LLT_INIT, 1147 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1148 SM(R92C_LLT_INIT_ADDR, addr) | 1149 SM(R92C_LLT_INIT_DATA, data)); 1150 /* Wait for write operation to complete. */ 1151 for (ntries = 0; ntries < 20; ntries++) { 1152 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1153 R92C_LLT_INIT_OP_NO_ACTIVE) 1154 return (0); 1155 DELAY(5); 1156 } 1157 return (ETIMEDOUT); 1158} 1159 1160static uint8_t 1161urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1162{ 1163 uint32_t reg; 1164 int ntries; 1165 1166 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1167 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1168 reg &= ~R92C_EFUSE_CTRL_VALID; 1169 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1170 /* Wait for read operation to complete. */ 1171 for (ntries = 0; ntries < 100; ntries++) { 1172 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1173 if (reg & R92C_EFUSE_CTRL_VALID) 1174 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1175 DELAY(5); 1176 } 1177 device_printf(sc->sc_dev, 1178 "could not read efuse byte at address 0x%x\n", addr); 1179 return (0xff); 1180} 1181 1182static void 1183urtwn_efuse_read(struct urtwn_softc *sc) 1184{ 1185 uint8_t *rom = (uint8_t *)&sc->rom; 1186 uint16_t addr = 0; 1187 uint32_t reg; 1188 uint8_t off, msk; 1189 int i; 1190 1191 urtwn_efuse_switch_power(sc); 1192 1193 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1194 while (addr < 512) { 1195 reg = urtwn_efuse_read_1(sc, addr); 1196 if (reg == 0xff) 1197 break; 1198 addr++; 1199 off = reg >> 4; 1200 msk = reg & 0xf; 1201 for (i = 0; i < 4; i++) { 1202 if (msk & (1 << i)) 1203 continue; 1204 rom[off * 8 + i * 2 + 0] = 1205 urtwn_efuse_read_1(sc, addr); 1206 addr++; 1207 rom[off * 8 + i * 2 + 1] = 1208 urtwn_efuse_read_1(sc, addr); 1209 addr++; 1210 } 1211 } 1212#ifdef URTWN_DEBUG 1213 if (urtwn_debug >= 2) { 1214 /* Dump ROM content. */ 1215 printf("\n"); 1216 for (i = 0; i < sizeof(sc->rom); i++) 1217 printf("%02x:", rom[i]); 1218 printf("\n"); 1219 } 1220#endif 1221} 1222static void 1223urtwn_efuse_switch_power(struct urtwn_softc *sc) 1224{ 1225 uint32_t reg; 1226 1227 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1228 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1229 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1230 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1231 } 1232 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1233 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1234 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1235 reg | R92C_SYS_FUNC_EN_ELDR); 1236 } 1237 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1238 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1239 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1240 urtwn_write_2(sc, R92C_SYS_CLKR, 1241 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1242 } 1243} 1244 1245static int 1246urtwn_read_chipid(struct urtwn_softc *sc) 1247{ 1248 uint32_t reg; 1249 1250 if (sc->chip & URTWN_CHIP_88E) 1251 return (0); 1252 1253 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1254 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1255 return (EIO); 1256 1257 if (reg & R92C_SYS_CFG_TYPE_92C) { 1258 sc->chip |= URTWN_CHIP_92C; 1259 /* Check if it is a castrated 8192C. */ 1260 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1261 R92C_HPON_FSM_CHIP_BONDING_ID) == 1262 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1263 sc->chip |= URTWN_CHIP_92C_1T2R; 1264 } 1265 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1266 sc->chip |= URTWN_CHIP_UMC; 1267 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1268 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1269 } 1270 return (0); 1271} 1272 1273static void 1274urtwn_read_rom(struct urtwn_softc *sc) 1275{ 1276 struct r92c_rom *rom = &sc->rom; 1277 1278 /* Read full ROM image. */ 1279 urtwn_efuse_read(sc); 1280 1281 /* XXX Weird but this is what the vendor driver does. */ 1282 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1283 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1284 1285 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1286 1287 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1288 DPRINTF("regulatory type=%d\n", sc->regulatory); 1289 IEEE80211_ADDR_COPY(sc->sc_bssid, rom->macaddr); 1290 1291 sc->sc_rf_write = urtwn_r92c_rf_write; 1292 sc->sc_power_on = urtwn_r92c_power_on; 1293 sc->sc_dma_init = urtwn_r92c_dma_init; 1294} 1295 1296static void 1297urtwn_r88e_read_rom(struct urtwn_softc *sc) 1298{ 1299 uint8_t *rom = sc->r88e_rom; 1300 uint16_t addr = 0; 1301 uint32_t reg; 1302 uint8_t off, msk, tmp; 1303 int i; 1304 1305 off = 0; 1306 urtwn_efuse_switch_power(sc); 1307 1308 /* Read full ROM image. */ 1309 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1310 while (addr < 1024) { 1311 reg = urtwn_efuse_read_1(sc, addr); 1312 if (reg == 0xff) 1313 break; 1314 addr++; 1315 if ((reg & 0x1f) == 0x0f) { 1316 tmp = (reg & 0xe0) >> 5; 1317 reg = urtwn_efuse_read_1(sc, addr); 1318 if ((reg & 0x0f) != 0x0f) 1319 off = ((reg & 0xf0) >> 1) | tmp; 1320 addr++; 1321 } else 1322 off = reg >> 4; 1323 msk = reg & 0xf; 1324 for (i = 0; i < 4; i++) { 1325 if (msk & (1 << i)) 1326 continue; 1327 rom[off * 8 + i * 2 + 0] = 1328 urtwn_efuse_read_1(sc, addr); 1329 addr++; 1330 rom[off * 8 + i * 2 + 1] = 1331 urtwn_efuse_read_1(sc, addr); 1332 addr++; 1333 } 1334 } 1335 1336 addr = 0x10; 1337 for (i = 0; i < 6; i++) 1338 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1339 for (i = 0; i < 5; i++) 1340 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1341 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1342 if (sc->bw20_tx_pwr_diff & 0x08) 1343 sc->bw20_tx_pwr_diff |= 0xf0; 1344 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1345 if (sc->ofdm_tx_pwr_diff & 0x08) 1346 sc->ofdm_tx_pwr_diff |= 0xf0; 1347 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1348 IEEE80211_ADDR_COPY(sc->sc_bssid, &sc->r88e_rom[0xd7]); 1349 1350 sc->sc_rf_write = urtwn_r88e_rf_write; 1351 sc->sc_power_on = urtwn_r88e_power_on; 1352 sc->sc_dma_init = urtwn_r88e_dma_init; 1353} 1354 1355/* 1356 * Initialize rate adaptation in firmware. 1357 */ 1358static int 1359urtwn_ra_init(struct urtwn_softc *sc) 1360{ 1361 static const uint8_t map[] = 1362 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1363 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1364 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1365 struct ieee80211_node *ni; 1366 struct ieee80211_rateset *rs; 1367 struct r92c_fw_cmd_macid_cfg cmd; 1368 uint32_t rates, basicrates; 1369 uint8_t mode; 1370 int maxrate, maxbasicrate, error, i, j; 1371 1372 ni = ieee80211_ref_node(vap->iv_bss); 1373 rs = &ni->ni_rates; 1374 1375 /* Get normal and basic rates mask. */ 1376 rates = basicrates = 0; 1377 maxrate = maxbasicrate = 0; 1378 for (i = 0; i < rs->rs_nrates; i++) { 1379 /* Convert 802.11 rate to HW rate index. */ 1380 for (j = 0; j < nitems(map); j++) 1381 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1382 break; 1383 if (j == nitems(map)) /* Unknown rate, skip. */ 1384 continue; 1385 rates |= 1 << j; 1386 if (j > maxrate) 1387 maxrate = j; 1388 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1389 basicrates |= 1 << j; 1390 if (j > maxbasicrate) 1391 maxbasicrate = j; 1392 } 1393 } 1394 if (ic->ic_curmode == IEEE80211_MODE_11B) 1395 mode = R92C_RAID_11B; 1396 else 1397 mode = R92C_RAID_11BG; 1398 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1399 mode, rates, basicrates); 1400 1401 /* Set rates mask for group addressed frames. */ 1402 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1403 cmd.mask = htole32(mode << 28 | basicrates); 1404 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1405 if (error != 0) { 1406 ieee80211_free_node(ni); 1407 device_printf(sc->sc_dev, 1408 "could not add broadcast station\n"); 1409 return (error); 1410 } 1411 /* Set initial MRR rate. */ 1412 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1413 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1414 maxbasicrate); 1415 1416 /* Set rates mask for unicast frames. */ 1417 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1418 cmd.mask = htole32(mode << 28 | rates); 1419 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1420 if (error != 0) { 1421 ieee80211_free_node(ni); 1422 device_printf(sc->sc_dev, "could not add BSS station\n"); 1423 return (error); 1424 } 1425 /* Set initial MRR rate. */ 1426 DPRINTF("maxrate=%d\n", maxrate); 1427 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1428 maxrate); 1429 1430 /* Indicate highest supported rate. */ 1431 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1432 ieee80211_free_node(ni); 1433 1434 return (0); 1435} 1436 1437void 1438urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1439{ 1440 struct ifnet *ifp = sc->sc_ifp; 1441 struct ieee80211com *ic = ifp->if_l2com; 1442 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1443 struct ieee80211_node *ni = vap->iv_bss; 1444 1445 uint64_t tsf; 1446 1447 /* Enable TSF synchronization. */ 1448 urtwn_write_1(sc, R92C_BCN_CTRL, 1449 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1450 1451 urtwn_write_1(sc, R92C_BCN_CTRL, 1452 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1453 1454 /* Set initial TSF. */ 1455 memcpy(&tsf, ni->ni_tstamp.data, 8); 1456 tsf = le64toh(tsf); 1457 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1458 tsf -= IEEE80211_DUR_TU; 1459 urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1460 urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1461 1462 urtwn_write_1(sc, R92C_BCN_CTRL, 1463 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1464} 1465 1466static void 1467urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1468{ 1469 uint8_t reg; 1470 1471 if (led == URTWN_LED_LINK) { 1472 if (sc->chip & URTWN_CHIP_88E) { 1473 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1474 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1475 if (!on) { 1476 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1477 urtwn_write_1(sc, R92C_LEDCFG2, 1478 reg | R92C_LEDCFG0_DIS); 1479 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1480 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1481 0xfe); 1482 } 1483 } else { 1484 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1485 if (!on) 1486 reg |= R92C_LEDCFG0_DIS; 1487 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1488 } 1489 sc->ledlink = on; /* Save LED state. */ 1490 } 1491} 1492 1493static int 1494urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1495{ 1496 struct urtwn_vap *uvp = URTWN_VAP(vap); 1497 struct ieee80211com *ic = vap->iv_ic; 1498 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1499 struct ieee80211_node *ni; 1500 enum ieee80211_state ostate; 1501 uint32_t reg; 1502 1503 ostate = vap->iv_state; 1504 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1505 ieee80211_state_name[nstate]); 1506 1507 IEEE80211_UNLOCK(ic); 1508 URTWN_LOCK(sc); 1509 callout_stop(&sc->sc_watchdog_ch); 1510 1511 if (ostate == IEEE80211_S_RUN) { 1512 /* Turn link LED off. */ 1513 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1514 1515 /* Set media status to 'No Link'. */ 1516 reg = urtwn_read_4(sc, R92C_CR); 1517 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1518 urtwn_write_4(sc, R92C_CR, reg); 1519 1520 /* Stop Rx of data frames. */ 1521 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1522 1523 /* Rest TSF. */ 1524 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1525 1526 /* Disable TSF synchronization. */ 1527 urtwn_write_1(sc, R92C_BCN_CTRL, 1528 urtwn_read_1(sc, R92C_BCN_CTRL) | 1529 R92C_BCN_CTRL_DIS_TSF_UDT0); 1530 1531 /* Reset EDCA parameters. */ 1532 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1533 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1534 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1535 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1536 } 1537 1538 switch (nstate) { 1539 case IEEE80211_S_INIT: 1540 /* Turn link LED off. */ 1541 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1542 break; 1543 case IEEE80211_S_SCAN: 1544 if (ostate != IEEE80211_S_SCAN) { 1545 /* Allow Rx from any BSSID. */ 1546 urtwn_write_4(sc, R92C_RCR, 1547 urtwn_read_4(sc, R92C_RCR) & 1548 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1549 1550 /* Set gain for scanning. */ 1551 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1552 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1553 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1554 1555 if (!(sc->chip & URTWN_CHIP_88E)) { 1556 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1557 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1558 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1559 } 1560 } 1561 /* Make link LED blink during scan. */ 1562 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1563 1564 /* Pause AC Tx queues. */ 1565 urtwn_write_1(sc, R92C_TXPAUSE, 1566 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1567 1568 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1569 break; 1570 case IEEE80211_S_AUTH: 1571 /* Set initial gain under link. */ 1572 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1573 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1574 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1575 1576 if (!(sc->chip & URTWN_CHIP_88E)) { 1577 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1578 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1579 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1580 } 1581 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1582 break; 1583 case IEEE80211_S_RUN: 1584 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1585 /* Enable Rx of data frames. */ 1586 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1587 1588 /* Turn link LED on. */ 1589 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1590 break; 1591 } 1592 1593 ni = ieee80211_ref_node(vap->iv_bss); 1594 /* Set media status to 'Associated'. */ 1595 reg = urtwn_read_4(sc, R92C_CR); 1596 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1597 urtwn_write_4(sc, R92C_CR, reg); 1598 1599 /* Set BSSID. */ 1600 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1601 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1602 1603 if (ic->ic_curmode == IEEE80211_MODE_11B) 1604 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1605 else /* 802.11b/g */ 1606 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1607 1608 /* Enable Rx of data frames. */ 1609 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1610 1611 /* Flush all AC queues. */ 1612 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1613 1614 /* Set beacon interval. */ 1615 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1616 1617 /* Allow Rx from our BSSID only. */ 1618 urtwn_write_4(sc, R92C_RCR, 1619 urtwn_read_4(sc, R92C_RCR) | 1620 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1621 1622 /* Enable TSF synchronization. */ 1623 urtwn_tsf_sync_enable(sc); 1624 1625 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1626 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1627 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1628 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1629 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1630 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1631 1632 /* Intialize rate adaptation. */ 1633 if (sc->chip & URTWN_CHIP_88E) 1634 ni->ni_txrate = 1635 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1636 else 1637 urtwn_ra_init(sc); 1638 /* Turn link LED on. */ 1639 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1640 1641 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1642 /* Reset temperature calibration state machine. */ 1643 sc->thcal_state = 0; 1644 sc->thcal_lctemp = 0; 1645 ieee80211_free_node(ni); 1646 break; 1647 default: 1648 break; 1649 } 1650 URTWN_UNLOCK(sc); 1651 IEEE80211_LOCK(ic); 1652 return(uvp->newstate(vap, nstate, arg)); 1653} 1654 1655static void 1656urtwn_watchdog(void *arg) 1657{ 1658 struct urtwn_softc *sc = arg; 1659 struct ifnet *ifp = sc->sc_ifp; 1660 1661 if (sc->sc_txtimer > 0) { 1662 if (--sc->sc_txtimer == 0) { 1663 device_printf(sc->sc_dev, "device timeout\n"); 1664 ifp->if_oerrors++; 1665 return; 1666 } 1667 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1668 } 1669} 1670 1671static void 1672urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1673{ 1674 int pwdb; 1675 1676 /* Convert antenna signal to percentage. */ 1677 if (rssi <= -100 || rssi >= 20) 1678 pwdb = 0; 1679 else if (rssi >= 0) 1680 pwdb = 100; 1681 else 1682 pwdb = 100 + rssi; 1683 if (!(sc->chip & URTWN_CHIP_88E)) { 1684 if (rate <= 3) { 1685 /* CCK gain is smaller than OFDM/MCS gain. */ 1686 pwdb += 6; 1687 if (pwdb > 100) 1688 pwdb = 100; 1689 if (pwdb <= 14) 1690 pwdb -= 4; 1691 else if (pwdb <= 26) 1692 pwdb -= 8; 1693 else if (pwdb <= 34) 1694 pwdb -= 6; 1695 else if (pwdb <= 42) 1696 pwdb -= 2; 1697 } 1698 } 1699 if (sc->avg_pwdb == -1) /* Init. */ 1700 sc->avg_pwdb = pwdb; 1701 else if (sc->avg_pwdb < pwdb) 1702 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1703 else 1704 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1705 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1706} 1707 1708static int8_t 1709urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1710{ 1711 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1712 struct r92c_rx_phystat *phy; 1713 struct r92c_rx_cck *cck; 1714 uint8_t rpt; 1715 int8_t rssi; 1716 1717 if (rate <= 3) { 1718 cck = (struct r92c_rx_cck *)physt; 1719 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1720 rpt = (cck->agc_rpt >> 5) & 0x3; 1721 rssi = (cck->agc_rpt & 0x1f) << 1; 1722 } else { 1723 rpt = (cck->agc_rpt >> 6) & 0x3; 1724 rssi = cck->agc_rpt & 0x3e; 1725 } 1726 rssi = cckoff[rpt] - rssi; 1727 } else { /* OFDM/HT. */ 1728 phy = (struct r92c_rx_phystat *)physt; 1729 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1730 } 1731 return (rssi); 1732} 1733 1734static int8_t 1735urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1736{ 1737 struct r92c_rx_phystat *phy; 1738 struct r88e_rx_cck *cck; 1739 uint8_t cck_agc_rpt, lna_idx, vga_idx; 1740 int8_t rssi; 1741 1742 rssi = 0; 1743 if (rate <= 3) { 1744 cck = (struct r88e_rx_cck *)physt; 1745 cck_agc_rpt = cck->agc_rpt; 1746 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1747 vga_idx = cck_agc_rpt & 0x1f; 1748 switch (lna_idx) { 1749 case 7: 1750 if (vga_idx <= 27) 1751 rssi = -100 + 2* (27 - vga_idx); 1752 else 1753 rssi = -100; 1754 break; 1755 case 6: 1756 rssi = -48 + 2 * (2 - vga_idx); 1757 break; 1758 case 5: 1759 rssi = -42 + 2 * (7 - vga_idx); 1760 break; 1761 case 4: 1762 rssi = -36 + 2 * (7 - vga_idx); 1763 break; 1764 case 3: 1765 rssi = -24 + 2 * (7 - vga_idx); 1766 break; 1767 case 2: 1768 rssi = -12 + 2 * (5 - vga_idx); 1769 break; 1770 case 1: 1771 rssi = 8 - (2 * vga_idx); 1772 break; 1773 case 0: 1774 rssi = 14 - (2 * vga_idx); 1775 break; 1776 } 1777 rssi += 6; 1778 } else { /* OFDM/HT. */ 1779 phy = (struct r92c_rx_phystat *)physt; 1780 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1781 } 1782 return (rssi); 1783} 1784 1785 1786static int 1787urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1788 struct mbuf *m0, struct urtwn_data *data) 1789{ 1790 struct ifnet *ifp = sc->sc_ifp; 1791 struct ieee80211_frame *wh; 1792 struct ieee80211_key *k; 1793 struct ieee80211com *ic = ifp->if_l2com; 1794 struct ieee80211vap *vap = ni->ni_vap; 1795 struct usb_xfer *xfer; 1796 struct r92c_tx_desc *txd; 1797 uint8_t raid, type; 1798 uint16_t sum; 1799 int i, hasqos, xferlen; 1800 struct usb_xfer *urtwn_pipes[4] = { 1801 sc->sc_xfer[URTWN_BULK_TX_BE], 1802 sc->sc_xfer[URTWN_BULK_TX_BK], 1803 sc->sc_xfer[URTWN_BULK_TX_VI], 1804 sc->sc_xfer[URTWN_BULK_TX_VO] 1805 }; 1806 1807 URTWN_ASSERT_LOCKED(sc); 1808 1809 /* 1810 * Software crypto. 1811 */ 1812 wh = mtod(m0, struct ieee80211_frame *); 1813 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1814 1815 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1816 k = ieee80211_crypto_encap(ni, m0); 1817 if (k == NULL) { 1818 device_printf(sc->sc_dev, 1819 "ieee80211_crypto_encap returns NULL.\n"); 1820 /* XXX we don't expect the fragmented frames */ 1821 m_freem(m0); 1822 return (ENOBUFS); 1823 } 1824 1825 /* in case packet header moved, reset pointer */ 1826 wh = mtod(m0, struct ieee80211_frame *); 1827 } 1828 1829 switch (type) { 1830 case IEEE80211_FC0_TYPE_CTL: 1831 case IEEE80211_FC0_TYPE_MGT: 1832 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1833 break; 1834 default: 1835 KASSERT(M_WME_GETAC(m0) < 4, 1836 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1837 xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1838 break; 1839 } 1840 1841 hasqos = 0; 1842 1843 /* Fill Tx descriptor. */ 1844 txd = (struct r92c_tx_desc *)data->buf; 1845 memset(txd, 0, sizeof(*txd)); 1846 1847 txd->txdw0 |= htole32( 1848 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1849 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1850 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1851 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1852 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1853 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1854 type == IEEE80211_FC0_TYPE_DATA) { 1855 if (ic->ic_curmode == IEEE80211_MODE_11B) 1856 raid = R92C_RAID_11B; 1857 else 1858 raid = R92C_RAID_11BG; 1859 if (sc->chip & URTWN_CHIP_88E) { 1860 txd->txdw1 |= htole32( 1861 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1862 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1863 SM(R92C_TXDW1_RAID, raid)); 1864 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1865 } else { 1866 txd->txdw1 |= htole32( 1867 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1868 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1869 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1870 } 1871 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1872 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1873 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1874 R92C_TXDW4_HWRTSEN); 1875 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1876 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1877 R92C_TXDW4_HWRTSEN); 1878 } 1879 } 1880 /* Send RTS at OFDM24. */ 1881 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1882 txd->txdw5 |= htole32(0x0001ff00); 1883 /* Send data at OFDM54. */ 1884 if (sc->chip & URTWN_CHIP_88E) 1885 txd->txdw5 |= htole32(0x13 & 0x3f); 1886 else 1887 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1888 } else { 1889 txd->txdw1 |= htole32( 1890 SM(R92C_TXDW1_MACID, 0) | 1891 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1892 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1893 1894 /* Force CCK1. */ 1895 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1896 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1897 } 1898 /* Set sequence number (already little endian). */ 1899 txd->txdseq |= *(uint16_t *)wh->i_seq; 1900 1901 if (!hasqos) { 1902 /* Use HW sequence numbering for non-QoS frames. */ 1903 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1904 txd->txdseq |= htole16(0x8000); 1905 } else 1906 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1907 1908 /* Compute Tx descriptor checksum. */ 1909 sum = 0; 1910 for (i = 0; i < sizeof(*txd) / 2; i++) 1911 sum ^= ((uint16_t *)txd)[i]; 1912 txd->txdsum = sum; /* NB: already little endian. */ 1913 1914 if (ieee80211_radiotap_active_vap(vap)) { 1915 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1916 1917 tap->wt_flags = 0; 1918 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1919 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1920 ieee80211_radiotap_tx(vap, m0); 1921 } 1922 1923 xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1924 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1925 1926 data->buflen = xferlen; 1927 data->ni = ni; 1928 data->m = m0; 1929 1930 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1931 usbd_transfer_start(xfer); 1932 return (0); 1933} 1934 1935static void 1936urtwn_start(struct ifnet *ifp) 1937{ 1938 struct urtwn_softc *sc = ifp->if_softc; 1939 1940 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1941 return; 1942 URTWN_LOCK(sc); 1943 urtwn_start_locked(ifp, sc); 1944 URTWN_UNLOCK(sc); 1945} 1946 1947static void 1948urtwn_start_locked(struct ifnet *ifp, struct urtwn_softc *sc) 1949{ 1950 struct ieee80211_node *ni; 1951 struct mbuf *m; 1952 struct urtwn_data *bf; 1953 1954 URTWN_ASSERT_LOCKED(sc); 1955 for (;;) { 1956 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1957 if (m == NULL) 1958 break; 1959 bf = urtwn_getbuf(sc); 1960 if (bf == NULL) { 1961 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1962 break; 1963 } 1964 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1965 m->m_pkthdr.rcvif = NULL; 1966 1967 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 1968 ifp->if_oerrors++; 1969 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1970 ieee80211_free_node(ni); 1971 break; 1972 } 1973 1974 sc->sc_txtimer = 5; 1975 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1976 } 1977} 1978 1979static int 1980urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1981{ 1982 struct urtwn_softc *sc = ifp->if_softc; 1983 struct ieee80211com *ic = ifp->if_l2com; 1984 struct ifreq *ifr = (struct ifreq *) data; 1985 int error = 0, startall = 0; 1986 1987 URTWN_LOCK(sc); 1988 error = (sc->sc_flags & URTWN_DETACHED) ? ENXIO : 0; 1989 URTWN_UNLOCK(sc); 1990 if (error != 0) 1991 return (error); 1992 1993 switch (cmd) { 1994 case SIOCSIFFLAGS: 1995 if (ifp->if_flags & IFF_UP) { 1996 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1997 urtwn_init(ifp->if_softc); 1998 startall = 1; 1999 } 2000 } else { 2001 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2002 urtwn_stop(ifp); 2003 } 2004 if (startall) 2005 ieee80211_start_all(ic); 2006 break; 2007 case SIOCGIFMEDIA: 2008 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 2009 break; 2010 case SIOCGIFADDR: 2011 error = ether_ioctl(ifp, cmd, data); 2012 break; 2013 default: 2014 error = EINVAL; 2015 break; 2016 } 2017 return (error); 2018} 2019 2020static int 2021urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 2022 int ndata, int maxsz) 2023{ 2024 int i, error; 2025 2026 for (i = 0; i < ndata; i++) { 2027 struct urtwn_data *dp = &data[i]; 2028 dp->sc = sc; 2029 dp->m = NULL; 2030 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 2031 if (dp->buf == NULL) { 2032 device_printf(sc->sc_dev, 2033 "could not allocate buffer\n"); 2034 error = ENOMEM; 2035 goto fail; 2036 } 2037 dp->ni = NULL; 2038 } 2039 2040 return (0); 2041fail: 2042 urtwn_free_list(sc, data, ndata); 2043 return (error); 2044} 2045 2046static int 2047urtwn_alloc_rx_list(struct urtwn_softc *sc) 2048{ 2049 int error, i; 2050 2051 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 2052 URTWN_RXBUFSZ); 2053 if (error != 0) 2054 return (error); 2055 2056 STAILQ_INIT(&sc->sc_rx_active); 2057 STAILQ_INIT(&sc->sc_rx_inactive); 2058 2059 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 2060 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 2061 2062 return (0); 2063} 2064 2065static int 2066urtwn_alloc_tx_list(struct urtwn_softc *sc) 2067{ 2068 int error, i; 2069 2070 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 2071 URTWN_TXBUFSZ); 2072 if (error != 0) 2073 return (error); 2074 2075 STAILQ_INIT(&sc->sc_tx_active); 2076 STAILQ_INIT(&sc->sc_tx_inactive); 2077 STAILQ_INIT(&sc->sc_tx_pending); 2078 2079 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 2080 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 2081 2082 return (0); 2083} 2084 2085static __inline int 2086urtwn_power_on(struct urtwn_softc *sc) 2087{ 2088 2089 return sc->sc_power_on(sc); 2090} 2091 2092static int 2093urtwn_r92c_power_on(struct urtwn_softc *sc) 2094{ 2095 uint32_t reg; 2096 int ntries; 2097 2098 /* Wait for autoload done bit. */ 2099 for (ntries = 0; ntries < 1000; ntries++) { 2100 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2101 break; 2102 DELAY(5); 2103 } 2104 if (ntries == 1000) { 2105 device_printf(sc->sc_dev, 2106 "timeout waiting for chip autoload\n"); 2107 return (ETIMEDOUT); 2108 } 2109 2110 /* Unlock ISO/CLK/Power control register. */ 2111 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2112 /* Move SPS into PWM mode. */ 2113 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2114 DELAY(100); 2115 2116 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2117 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2118 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2119 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2120 DELAY(100); 2121 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2122 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2123 ~R92C_SYS_ISO_CTRL_MD2PP); 2124 } 2125 2126 /* Auto enable WLAN. */ 2127 urtwn_write_2(sc, R92C_APS_FSMCO, 2128 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2129 for (ntries = 0; ntries < 1000; ntries++) { 2130 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2131 R92C_APS_FSMCO_APFM_ONMAC)) 2132 break; 2133 DELAY(5); 2134 } 2135 if (ntries == 1000) { 2136 device_printf(sc->sc_dev, 2137 "timeout waiting for MAC auto ON\n"); 2138 return (ETIMEDOUT); 2139 } 2140 2141 /* Enable radio, GPIO and LED functions. */ 2142 urtwn_write_2(sc, R92C_APS_FSMCO, 2143 R92C_APS_FSMCO_AFSM_HSUS | 2144 R92C_APS_FSMCO_PDN_EN | 2145 R92C_APS_FSMCO_PFM_ALDN); 2146 /* Release RF digital isolation. */ 2147 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2148 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2149 2150 /* Initialize MAC. */ 2151 urtwn_write_1(sc, R92C_APSD_CTRL, 2152 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2153 for (ntries = 0; ntries < 200; ntries++) { 2154 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2155 R92C_APSD_CTRL_OFF_STATUS)) 2156 break; 2157 DELAY(5); 2158 } 2159 if (ntries == 200) { 2160 device_printf(sc->sc_dev, 2161 "timeout waiting for MAC initialization\n"); 2162 return (ETIMEDOUT); 2163 } 2164 2165 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2166 reg = urtwn_read_2(sc, R92C_CR); 2167 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2168 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2169 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2170 R92C_CR_ENSEC; 2171 urtwn_write_2(sc, R92C_CR, reg); 2172 2173 urtwn_write_1(sc, 0xfe10, 0x19); 2174 return (0); 2175} 2176 2177static int 2178urtwn_r88e_power_on(struct urtwn_softc *sc) 2179{ 2180 uint8_t val; 2181 uint32_t reg; 2182 int ntries; 2183 2184 /* Wait for power ready bit. */ 2185 for (ntries = 0; ntries < 5000; ntries++) { 2186 val = urtwn_read_1(sc, 0x6) & 0x2; 2187 if (val == 0x2) 2188 break; 2189 DELAY(10); 2190 } 2191 if (ntries == 5000) { 2192 device_printf(sc->sc_dev, 2193 "timeout waiting for chip power up\n"); 2194 return (ETIMEDOUT); 2195 } 2196 2197 /* Reset BB. */ 2198 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2199 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2200 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2201 2202 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 2203 2204 /* Disable HWPDN. */ 2205 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 2206 2207 /* Disable WL suspend. */ 2208 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 2209 2210 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 2211 for (ntries = 0; ntries < 5000; ntries++) { 2212 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 2213 break; 2214 DELAY(10); 2215 } 2216 if (ntries == 5000) 2217 return (ETIMEDOUT); 2218 2219 /* Enable LDO normal mode. */ 2220 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 2221 2222 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2223 urtwn_write_2(sc, R92C_CR, 0); 2224 reg = urtwn_read_2(sc, R92C_CR); 2225 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2226 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2227 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2228 urtwn_write_2(sc, R92C_CR, reg); 2229 2230 return (0); 2231} 2232 2233static int 2234urtwn_llt_init(struct urtwn_softc *sc) 2235{ 2236 int i, error, page_count, pktbuf_count; 2237 2238 page_count = (sc->chip & URTWN_CHIP_88E) ? 2239 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2240 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2241 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2242 2243 /* Reserve pages [0; page_count]. */ 2244 for (i = 0; i < page_count; i++) { 2245 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2246 return (error); 2247 } 2248 /* NB: 0xff indicates end-of-list. */ 2249 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2250 return (error); 2251 /* 2252 * Use pages [page_count + 1; pktbuf_count - 1] 2253 * as ring buffer. 2254 */ 2255 for (++i; i < pktbuf_count - 1; i++) { 2256 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2257 return (error); 2258 } 2259 /* Make the last page point to the beginning of the ring buffer. */ 2260 error = urtwn_llt_write(sc, i, page_count + 1); 2261 return (error); 2262} 2263 2264static void 2265urtwn_fw_reset(struct urtwn_softc *sc) 2266{ 2267 uint16_t reg; 2268 int ntries; 2269 2270 /* Tell 8051 to reset itself. */ 2271 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2272 2273 /* Wait until 8051 resets by itself. */ 2274 for (ntries = 0; ntries < 100; ntries++) { 2275 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2276 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2277 return; 2278 DELAY(50); 2279 } 2280 /* Force 8051 reset. */ 2281 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2282 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2283 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2284 R92C_SYS_FUNC_EN_CPUEN); 2285} 2286 2287static void 2288urtwn_r88e_fw_reset(struct urtwn_softc *sc) 2289{ 2290 uint16_t reg; 2291 2292 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2293 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2294 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2295} 2296 2297static int 2298urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2299{ 2300 uint32_t reg; 2301 int off, mlen, error = 0; 2302 2303 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2304 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2305 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2306 2307 off = R92C_FW_START_ADDR; 2308 while (len > 0) { 2309 if (len > 196) 2310 mlen = 196; 2311 else if (len > 4) 2312 mlen = 4; 2313 else 2314 mlen = 1; 2315 /* XXX fix this deconst */ 2316 error = urtwn_write_region_1(sc, off, 2317 __DECONST(uint8_t *, buf), mlen); 2318 if (error != 0) 2319 break; 2320 off += mlen; 2321 buf += mlen; 2322 len -= mlen; 2323 } 2324 return (error); 2325} 2326 2327static int 2328urtwn_load_firmware(struct urtwn_softc *sc) 2329{ 2330 const struct firmware *fw; 2331 const struct r92c_fw_hdr *hdr; 2332 const char *imagename; 2333 const u_char *ptr; 2334 size_t len; 2335 uint32_t reg; 2336 int mlen, ntries, page, error; 2337 2338 URTWN_UNLOCK(sc); 2339 /* Read firmware image from the filesystem. */ 2340 if (sc->chip & URTWN_CHIP_88E) 2341 imagename = "urtwn-rtl8188eufw"; 2342 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2343 URTWN_CHIP_UMC_A_CUT) 2344 imagename = "urtwn-rtl8192cfwU"; 2345 else 2346 imagename = "urtwn-rtl8192cfwT"; 2347 2348 fw = firmware_get(imagename); 2349 URTWN_LOCK(sc); 2350 if (fw == NULL) { 2351 device_printf(sc->sc_dev, 2352 "failed loadfirmware of file %s\n", imagename); 2353 return (ENOENT); 2354 } 2355 2356 len = fw->datasize; 2357 2358 if (len < sizeof(*hdr)) { 2359 device_printf(sc->sc_dev, "firmware too short\n"); 2360 error = EINVAL; 2361 goto fail; 2362 } 2363 ptr = fw->data; 2364 hdr = (const struct r92c_fw_hdr *)ptr; 2365 /* Check if there is a valid FW header and skip it. */ 2366 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2367 (le16toh(hdr->signature) >> 4) == 0x88e || 2368 (le16toh(hdr->signature) >> 4) == 0x92c) { 2369 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2370 le16toh(hdr->version), le16toh(hdr->subversion), 2371 hdr->month, hdr->date, hdr->hour, hdr->minute); 2372 ptr += sizeof(*hdr); 2373 len -= sizeof(*hdr); 2374 } 2375 2376 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2377 if (sc->chip & URTWN_CHIP_88E) 2378 urtwn_r88e_fw_reset(sc); 2379 else 2380 urtwn_fw_reset(sc); 2381 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2382 } 2383 2384 urtwn_write_1(sc, R92C_MCUFWDL, 2385 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2386 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2387 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2388 2389 /* Reset the FWDL checksum. */ 2390 urtwn_write_1(sc, R92C_MCUFWDL, 2391 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2392 2393 for (page = 0; len > 0; page++) { 2394 mlen = min(len, R92C_FW_PAGE_SIZE); 2395 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2396 if (error != 0) { 2397 device_printf(sc->sc_dev, 2398 "could not load firmware page\n"); 2399 goto fail; 2400 } 2401 ptr += mlen; 2402 len -= mlen; 2403 } 2404 urtwn_write_1(sc, R92C_MCUFWDL, 2405 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2406 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2407 2408 /* Wait for checksum report. */ 2409 for (ntries = 0; ntries < 1000; ntries++) { 2410 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2411 break; 2412 DELAY(5); 2413 } 2414 if (ntries == 1000) { 2415 device_printf(sc->sc_dev, 2416 "timeout waiting for checksum report\n"); 2417 error = ETIMEDOUT; 2418 goto fail; 2419 } 2420 2421 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2422 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2423 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2424 if (sc->chip & URTWN_CHIP_88E) 2425 urtwn_r88e_fw_reset(sc); 2426 /* Wait for firmware readiness. */ 2427 for (ntries = 0; ntries < 1000; ntries++) { 2428 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2429 break; 2430 DELAY(5); 2431 } 2432 if (ntries == 1000) { 2433 device_printf(sc->sc_dev, 2434 "timeout waiting for firmware readiness\n"); 2435 error = ETIMEDOUT; 2436 goto fail; 2437 } 2438fail: 2439 firmware_put(fw, FIRMWARE_UNLOAD); 2440 return (error); 2441} 2442 2443static __inline int 2444urtwn_dma_init(struct urtwn_softc *sc) 2445{ 2446 2447 return sc->sc_dma_init(sc); 2448} 2449 2450static int 2451urtwn_r92c_dma_init(struct urtwn_softc *sc) 2452{ 2453 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2454 uint32_t reg; 2455 int error; 2456 2457 /* Initialize LLT table. */ 2458 error = urtwn_llt_init(sc); 2459 if (error != 0) 2460 return (error); 2461 2462 /* Get Tx queues to USB endpoints mapping. */ 2463 hashq = hasnq = haslq = 0; 2464 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2465 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2466 if (MS(reg, R92C_USB_EP_HQ) != 0) 2467 hashq = 1; 2468 if (MS(reg, R92C_USB_EP_NQ) != 0) 2469 hasnq = 1; 2470 if (MS(reg, R92C_USB_EP_LQ) != 0) 2471 haslq = 1; 2472 nqueues = hashq + hasnq + haslq; 2473 if (nqueues == 0) 2474 return (EIO); 2475 /* Get the number of pages for each queue. */ 2476 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2477 /* The remaining pages are assigned to the high priority queue. */ 2478 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2479 2480 /* Set number of pages for normal priority queue. */ 2481 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2482 urtwn_write_4(sc, R92C_RQPN, 2483 /* Set number of pages for public queue. */ 2484 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2485 /* Set number of pages for high priority queue. */ 2486 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2487 /* Set number of pages for low priority queue. */ 2488 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2489 /* Load values. */ 2490 R92C_RQPN_LD); 2491 2492 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2493 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2494 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2495 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2496 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2497 2498 /* Set queue to USB pipe mapping. */ 2499 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2500 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2501 if (nqueues == 1) { 2502 if (hashq) 2503 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2504 else if (hasnq) 2505 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2506 else 2507 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2508 } else if (nqueues == 2) { 2509 /* All 2-endpoints configs have a high priority queue. */ 2510 if (!hashq) 2511 return (EIO); 2512 if (hasnq) 2513 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2514 else 2515 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2516 } else 2517 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2518 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2519 2520 /* Set Tx/Rx transfer page boundary. */ 2521 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2522 2523 /* Set Tx/Rx transfer page size. */ 2524 urtwn_write_1(sc, R92C_PBP, 2525 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2526 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2527 return (0); 2528} 2529 2530static int 2531urtwn_r88e_dma_init(struct urtwn_softc *sc) 2532{ 2533 struct usb_interface *iface; 2534 uint32_t reg; 2535 int nqueues; 2536 int error; 2537 2538 /* Initialize LLT table. */ 2539 error = urtwn_llt_init(sc); 2540 if (error != 0) 2541 return (error); 2542 2543 /* Get Tx queues to USB endpoints mapping. */ 2544 iface = usbd_get_iface(sc->sc_udev, 0); 2545 nqueues = iface->idesc->bNumEndpoints - 1; 2546 if (nqueues == 0) 2547 return (EIO); 2548 2549 /* Set number of pages for normal priority queue. */ 2550 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2551 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2552 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2553 2554 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2555 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2556 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2557 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2558 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2559 2560 /* Set queue to USB pipe mapping. */ 2561 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2562 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2563 if (nqueues == 1) 2564 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2565 else if (nqueues == 2) 2566 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2567 else 2568 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2569 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2570 2571 /* Set Tx/Rx transfer page boundary. */ 2572 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2573 2574 /* Set Tx/Rx transfer page size. */ 2575 urtwn_write_1(sc, R92C_PBP, 2576 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2577 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2578 2579 return (0); 2580} 2581 2582static void 2583urtwn_mac_init(struct urtwn_softc *sc) 2584{ 2585 int i; 2586 2587 /* Write MAC initialization values. */ 2588 if (sc->chip & URTWN_CHIP_88E) { 2589 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2590 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2591 rtl8188eu_mac[i].val); 2592 } 2593 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2594 } else { 2595 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2596 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2597 rtl8192cu_mac[i].val); 2598 } 2599} 2600 2601static void 2602urtwn_bb_init(struct urtwn_softc *sc) 2603{ 2604 const struct urtwn_bb_prog *prog; 2605 uint32_t reg; 2606 uint8_t crystalcap; 2607 int i; 2608 2609 /* Enable BB and RF. */ 2610 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2611 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2612 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2613 R92C_SYS_FUNC_EN_DIO_RF); 2614 2615 if (!(sc->chip & URTWN_CHIP_88E)) 2616 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2617 2618 urtwn_write_1(sc, R92C_RF_CTRL, 2619 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2620 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2621 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2622 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2623 2624 if (!(sc->chip & URTWN_CHIP_88E)) { 2625 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2626 urtwn_write_1(sc, 0x15, 0xe9); 2627 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2628 } 2629 2630 /* Select BB programming based on board type. */ 2631 if (sc->chip & URTWN_CHIP_88E) 2632 prog = &rtl8188eu_bb_prog; 2633 else if (!(sc->chip & URTWN_CHIP_92C)) { 2634 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2635 prog = &rtl8188ce_bb_prog; 2636 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2637 prog = &rtl8188ru_bb_prog; 2638 else 2639 prog = &rtl8188cu_bb_prog; 2640 } else { 2641 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2642 prog = &rtl8192ce_bb_prog; 2643 else 2644 prog = &rtl8192cu_bb_prog; 2645 } 2646 /* Write BB initialization values. */ 2647 for (i = 0; i < prog->count; i++) { 2648 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2649 DELAY(1); 2650 } 2651 2652 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2653 /* 8192C 1T only configuration. */ 2654 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2655 reg = (reg & ~0x00000003) | 0x2; 2656 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2657 2658 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2659 reg = (reg & ~0x00300033) | 0x00200022; 2660 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2661 2662 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2663 reg = (reg & ~0xff000000) | 0x45 << 24; 2664 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2665 2666 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2667 reg = (reg & ~0x000000ff) | 0x23; 2668 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2669 2670 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2671 reg = (reg & ~0x00000030) | 1 << 4; 2672 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2673 2674 reg = urtwn_bb_read(sc, 0xe74); 2675 reg = (reg & ~0x0c000000) | 2 << 26; 2676 urtwn_bb_write(sc, 0xe74, reg); 2677 reg = urtwn_bb_read(sc, 0xe78); 2678 reg = (reg & ~0x0c000000) | 2 << 26; 2679 urtwn_bb_write(sc, 0xe78, reg); 2680 reg = urtwn_bb_read(sc, 0xe7c); 2681 reg = (reg & ~0x0c000000) | 2 << 26; 2682 urtwn_bb_write(sc, 0xe7c, reg); 2683 reg = urtwn_bb_read(sc, 0xe80); 2684 reg = (reg & ~0x0c000000) | 2 << 26; 2685 urtwn_bb_write(sc, 0xe80, reg); 2686 reg = urtwn_bb_read(sc, 0xe88); 2687 reg = (reg & ~0x0c000000) | 2 << 26; 2688 urtwn_bb_write(sc, 0xe88, reg); 2689 } 2690 2691 /* Write AGC values. */ 2692 for (i = 0; i < prog->agccount; i++) { 2693 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2694 prog->agcvals[i]); 2695 DELAY(1); 2696 } 2697 2698 if (sc->chip & URTWN_CHIP_88E) { 2699 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2700 DELAY(1); 2701 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2702 DELAY(1); 2703 2704 crystalcap = sc->r88e_rom[0xb9]; 2705 if (crystalcap == 0xff) 2706 crystalcap = 0x20; 2707 crystalcap &= 0x3f; 2708 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2709 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2710 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2711 crystalcap | crystalcap << 6)); 2712 } else { 2713 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2714 R92C_HSSI_PARAM2_CCK_HIPWR) 2715 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2716 } 2717} 2718 2719void 2720urtwn_rf_init(struct urtwn_softc *sc) 2721{ 2722 const struct urtwn_rf_prog *prog; 2723 uint32_t reg, type; 2724 int i, j, idx, off; 2725 2726 /* Select RF programming based on board type. */ 2727 if (sc->chip & URTWN_CHIP_88E) 2728 prog = rtl8188eu_rf_prog; 2729 else if (!(sc->chip & URTWN_CHIP_92C)) { 2730 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2731 prog = rtl8188ce_rf_prog; 2732 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2733 prog = rtl8188ru_rf_prog; 2734 else 2735 prog = rtl8188cu_rf_prog; 2736 } else 2737 prog = rtl8192ce_rf_prog; 2738 2739 for (i = 0; i < sc->nrxchains; i++) { 2740 /* Save RF_ENV control type. */ 2741 idx = i / 2; 2742 off = (i % 2) * 16; 2743 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2744 type = (reg >> off) & 0x10; 2745 2746 /* Set RF_ENV enable. */ 2747 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2748 reg |= 0x100000; 2749 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2750 DELAY(1); 2751 /* Set RF_ENV output high. */ 2752 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2753 reg |= 0x10; 2754 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2755 DELAY(1); 2756 /* Set address and data lengths of RF registers. */ 2757 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2758 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2759 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2760 DELAY(1); 2761 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2762 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2763 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2764 DELAY(1); 2765 2766 /* Write RF initialization values for this chain. */ 2767 for (j = 0; j < prog[i].count; j++) { 2768 if (prog[i].regs[j] >= 0xf9 && 2769 prog[i].regs[j] <= 0xfe) { 2770 /* 2771 * These are fake RF registers offsets that 2772 * indicate a delay is required. 2773 */ 2774 usb_pause_mtx(&sc->sc_mtx, 50); 2775 continue; 2776 } 2777 urtwn_rf_write(sc, i, prog[i].regs[j], 2778 prog[i].vals[j]); 2779 DELAY(1); 2780 } 2781 2782 /* Restore RF_ENV control type. */ 2783 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2784 reg &= ~(0x10 << off) | (type << off); 2785 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2786 2787 /* Cache RF register CHNLBW. */ 2788 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2789 } 2790 2791 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2792 URTWN_CHIP_UMC_A_CUT) { 2793 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2794 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2795 } 2796} 2797 2798static void 2799urtwn_cam_init(struct urtwn_softc *sc) 2800{ 2801 /* Invalidate all CAM entries. */ 2802 urtwn_write_4(sc, R92C_CAMCMD, 2803 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2804} 2805 2806static void 2807urtwn_pa_bias_init(struct urtwn_softc *sc) 2808{ 2809 uint8_t reg; 2810 int i; 2811 2812 for (i = 0; i < sc->nrxchains; i++) { 2813 if (sc->pa_setting & (1 << i)) 2814 continue; 2815 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2816 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2817 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2818 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2819 } 2820 if (!(sc->pa_setting & 0x10)) { 2821 reg = urtwn_read_1(sc, 0x16); 2822 reg = (reg & ~0xf0) | 0x90; 2823 urtwn_write_1(sc, 0x16, reg); 2824 } 2825} 2826 2827static void 2828urtwn_rxfilter_init(struct urtwn_softc *sc) 2829{ 2830 /* Initialize Rx filter. */ 2831 /* TODO: use better filter for monitor mode. */ 2832 urtwn_write_4(sc, R92C_RCR, 2833 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2834 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2835 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2836 /* Accept all multicast frames. */ 2837 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2838 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2839 /* Accept all management frames. */ 2840 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2841 /* Reject all control frames. */ 2842 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2843 /* Accept all data frames. */ 2844 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2845} 2846 2847static void 2848urtwn_edca_init(struct urtwn_softc *sc) 2849{ 2850 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2851 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2852 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2853 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2854 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2855 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2856 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2857 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2858} 2859 2860void 2861urtwn_write_txpower(struct urtwn_softc *sc, int chain, 2862 uint16_t power[URTWN_RIDX_COUNT]) 2863{ 2864 uint32_t reg; 2865 2866 /* Write per-CCK rate Tx power. */ 2867 if (chain == 0) { 2868 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2869 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2870 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2871 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2872 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2873 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2874 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2875 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2876 } else { 2877 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2878 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2879 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2880 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2881 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2882 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2883 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2884 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2885 } 2886 /* Write per-OFDM rate Tx power. */ 2887 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2888 SM(R92C_TXAGC_RATE06, power[ 4]) | 2889 SM(R92C_TXAGC_RATE09, power[ 5]) | 2890 SM(R92C_TXAGC_RATE12, power[ 6]) | 2891 SM(R92C_TXAGC_RATE18, power[ 7])); 2892 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2893 SM(R92C_TXAGC_RATE24, power[ 8]) | 2894 SM(R92C_TXAGC_RATE36, power[ 9]) | 2895 SM(R92C_TXAGC_RATE48, power[10]) | 2896 SM(R92C_TXAGC_RATE54, power[11])); 2897 /* Write per-MCS Tx power. */ 2898 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2899 SM(R92C_TXAGC_MCS00, power[12]) | 2900 SM(R92C_TXAGC_MCS01, power[13]) | 2901 SM(R92C_TXAGC_MCS02, power[14]) | 2902 SM(R92C_TXAGC_MCS03, power[15])); 2903 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2904 SM(R92C_TXAGC_MCS04, power[16]) | 2905 SM(R92C_TXAGC_MCS05, power[17]) | 2906 SM(R92C_TXAGC_MCS06, power[18]) | 2907 SM(R92C_TXAGC_MCS07, power[19])); 2908 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2909 SM(R92C_TXAGC_MCS08, power[20]) | 2910 SM(R92C_TXAGC_MCS09, power[21]) | 2911 SM(R92C_TXAGC_MCS10, power[22]) | 2912 SM(R92C_TXAGC_MCS11, power[23])); 2913 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2914 SM(R92C_TXAGC_MCS12, power[24]) | 2915 SM(R92C_TXAGC_MCS13, power[25]) | 2916 SM(R92C_TXAGC_MCS14, power[26]) | 2917 SM(R92C_TXAGC_MCS15, power[27])); 2918} 2919 2920void 2921urtwn_get_txpower(struct urtwn_softc *sc, int chain, 2922 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2923 uint16_t power[URTWN_RIDX_COUNT]) 2924{ 2925 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2926 struct r92c_rom *rom = &sc->rom; 2927 uint16_t cckpow, ofdmpow, htpow, diff, max; 2928 const struct urtwn_txpwr *base; 2929 int ridx, chan, group; 2930 2931 /* Determine channel group. */ 2932 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2933 if (chan <= 3) 2934 group = 0; 2935 else if (chan <= 9) 2936 group = 1; 2937 else 2938 group = 2; 2939 2940 /* Get original Tx power based on board type and RF chain. */ 2941 if (!(sc->chip & URTWN_CHIP_92C)) { 2942 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2943 base = &rtl8188ru_txagc[chain]; 2944 else 2945 base = &rtl8192cu_txagc[chain]; 2946 } else 2947 base = &rtl8192cu_txagc[chain]; 2948 2949 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2950 if (sc->regulatory == 0) { 2951 for (ridx = 0; ridx <= 3; ridx++) 2952 power[ridx] = base->pwr[0][ridx]; 2953 } 2954 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 2955 if (sc->regulatory == 3) { 2956 power[ridx] = base->pwr[0][ridx]; 2957 /* Apply vendor limits. */ 2958 if (extc != NULL) 2959 max = rom->ht40_max_pwr[group]; 2960 else 2961 max = rom->ht20_max_pwr[group]; 2962 max = (max >> (chain * 4)) & 0xf; 2963 if (power[ridx] > max) 2964 power[ridx] = max; 2965 } else if (sc->regulatory == 1) { 2966 if (extc == NULL) 2967 power[ridx] = base->pwr[group][ridx]; 2968 } else if (sc->regulatory != 2) 2969 power[ridx] = base->pwr[0][ridx]; 2970 } 2971 2972 /* Compute per-CCK rate Tx power. */ 2973 cckpow = rom->cck_tx_pwr[chain][group]; 2974 for (ridx = 0; ridx <= 3; ridx++) { 2975 power[ridx] += cckpow; 2976 if (power[ridx] > R92C_MAX_TX_PWR) 2977 power[ridx] = R92C_MAX_TX_PWR; 2978 } 2979 2980 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2981 if (sc->ntxchains > 1) { 2982 /* Apply reduction for 2 spatial streams. */ 2983 diff = rom->ht40_2s_tx_pwr_diff[group]; 2984 diff = (diff >> (chain * 4)) & 0xf; 2985 htpow = (htpow > diff) ? htpow - diff : 0; 2986 } 2987 2988 /* Compute per-OFDM rate Tx power. */ 2989 diff = rom->ofdm_tx_pwr_diff[group]; 2990 diff = (diff >> (chain * 4)) & 0xf; 2991 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2992 for (ridx = 4; ridx <= 11; ridx++) { 2993 power[ridx] += ofdmpow; 2994 if (power[ridx] > R92C_MAX_TX_PWR) 2995 power[ridx] = R92C_MAX_TX_PWR; 2996 } 2997 2998 /* Compute per-MCS Tx power. */ 2999 if (extc == NULL) { 3000 diff = rom->ht20_tx_pwr_diff[group]; 3001 diff = (diff >> (chain * 4)) & 0xf; 3002 htpow += diff; /* HT40->HT20 correction. */ 3003 } 3004 for (ridx = 12; ridx <= 27; ridx++) { 3005 power[ridx] += htpow; 3006 if (power[ridx] > R92C_MAX_TX_PWR) 3007 power[ridx] = R92C_MAX_TX_PWR; 3008 } 3009#ifdef URTWN_DEBUG 3010 if (urtwn_debug >= 4) { 3011 /* Dump per-rate Tx power values. */ 3012 printf("Tx power for chain %d:\n", chain); 3013 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 3014 printf("Rate %d = %u\n", ridx, power[ridx]); 3015 } 3016#endif 3017} 3018 3019void 3020urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3021 struct ieee80211_channel *c, struct ieee80211_channel *extc, 3022 uint16_t power[URTWN_RIDX_COUNT]) 3023{ 3024 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3025 uint16_t cckpow, ofdmpow, bw20pow, htpow; 3026 const struct urtwn_r88e_txpwr *base; 3027 int ridx, chan, group; 3028 3029 /* Determine channel group. */ 3030 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3031 if (chan <= 2) 3032 group = 0; 3033 else if (chan <= 5) 3034 group = 1; 3035 else if (chan <= 8) 3036 group = 2; 3037 else if (chan <= 11) 3038 group = 3; 3039 else if (chan <= 13) 3040 group = 4; 3041 else 3042 group = 5; 3043 3044 /* Get original Tx power based on board type and RF chain. */ 3045 base = &rtl8188eu_txagc[chain]; 3046 3047 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3048 if (sc->regulatory == 0) { 3049 for (ridx = 0; ridx <= 3; ridx++) 3050 power[ridx] = base->pwr[0][ridx]; 3051 } 3052 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3053 if (sc->regulatory == 3) 3054 power[ridx] = base->pwr[0][ridx]; 3055 else if (sc->regulatory == 1) { 3056 if (extc == NULL) 3057 power[ridx] = base->pwr[group][ridx]; 3058 } else if (sc->regulatory != 2) 3059 power[ridx] = base->pwr[0][ridx]; 3060 } 3061 3062 /* Compute per-CCK rate Tx power. */ 3063 cckpow = sc->cck_tx_pwr[group]; 3064 for (ridx = 0; ridx <= 3; ridx++) { 3065 power[ridx] += cckpow; 3066 if (power[ridx] > R92C_MAX_TX_PWR) 3067 power[ridx] = R92C_MAX_TX_PWR; 3068 } 3069 3070 htpow = sc->ht40_tx_pwr[group]; 3071 3072 /* Compute per-OFDM rate Tx power. */ 3073 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3074 for (ridx = 4; ridx <= 11; ridx++) { 3075 power[ridx] += ofdmpow; 3076 if (power[ridx] > R92C_MAX_TX_PWR) 3077 power[ridx] = R92C_MAX_TX_PWR; 3078 } 3079 3080 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3081 for (ridx = 12; ridx <= 27; ridx++) { 3082 power[ridx] += bw20pow; 3083 if (power[ridx] > R92C_MAX_TX_PWR) 3084 power[ridx] = R92C_MAX_TX_PWR; 3085 } 3086} 3087 3088void 3089urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3090 struct ieee80211_channel *extc) 3091{ 3092 uint16_t power[URTWN_RIDX_COUNT]; 3093 int i; 3094 3095 for (i = 0; i < sc->ntxchains; i++) { 3096 /* Compute per-rate Tx power values. */ 3097 if (sc->chip & URTWN_CHIP_88E) 3098 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3099 else 3100 urtwn_get_txpower(sc, i, c, extc, power); 3101 /* Write per-rate Tx power values to hardware. */ 3102 urtwn_write_txpower(sc, i, power); 3103 } 3104} 3105 3106static void 3107urtwn_scan_start(struct ieee80211com *ic) 3108{ 3109 /* XXX do nothing? */ 3110} 3111 3112static void 3113urtwn_scan_end(struct ieee80211com *ic) 3114{ 3115 /* XXX do nothing? */ 3116} 3117 3118static void 3119urtwn_set_channel(struct ieee80211com *ic) 3120{ 3121 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 3122 3123 URTWN_LOCK(sc); 3124 urtwn_set_chan(sc, ic->ic_curchan, NULL); 3125 URTWN_UNLOCK(sc); 3126} 3127 3128static void 3129urtwn_update_mcast(struct ifnet *ifp) 3130{ 3131 /* XXX do nothing? */ 3132} 3133 3134static void 3135urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3136 struct ieee80211_channel *extc) 3137{ 3138 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3139 uint32_t reg; 3140 u_int chan; 3141 int i; 3142 3143 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3144 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3145 device_printf(sc->sc_dev, 3146 "%s: invalid channel %x\n", __func__, chan); 3147 return; 3148 } 3149 3150 /* Set Tx power for this new channel. */ 3151 urtwn_set_txpower(sc, c, extc); 3152 3153 for (i = 0; i < sc->nrxchains; i++) { 3154 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3155 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3156 } 3157#ifndef IEEE80211_NO_HT 3158 if (extc != NULL) { 3159 /* Is secondary channel below or above primary? */ 3160 int prichlo = c->ic_freq < extc->ic_freq; 3161 3162 urtwn_write_1(sc, R92C_BWOPMODE, 3163 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3164 3165 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3166 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3167 urtwn_write_1(sc, R92C_RRSR + 2, reg); 3168 3169 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3170 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3171 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3172 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3173 3174 /* Set CCK side band. */ 3175 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3176 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3177 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3178 3179 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3180 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3181 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3182 3183 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3184 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3185 ~R92C_FPGA0_ANAPARAM2_CBW20); 3186 3187 reg = urtwn_bb_read(sc, 0x818); 3188 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3189 urtwn_bb_write(sc, 0x818, reg); 3190 3191 /* Select 40MHz bandwidth. */ 3192 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3193 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3194 } else 3195#endif 3196 { 3197 urtwn_write_1(sc, R92C_BWOPMODE, 3198 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3199 3200 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3201 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3202 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3203 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3204 3205 if (!(sc->chip & URTWN_CHIP_88E)) { 3206 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3207 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3208 R92C_FPGA0_ANAPARAM2_CBW20); 3209 } 3210 3211 /* Select 20MHz bandwidth. */ 3212 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3213 (sc->rf_chnlbw[0] & ~0xfff) | chan | 3214 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3215 R92C_RF_CHNLBW_BW20)); 3216 } 3217} 3218 3219static void 3220urtwn_iq_calib(struct urtwn_softc *sc) 3221{ 3222 /* TODO */ 3223} 3224 3225static void 3226urtwn_lc_calib(struct urtwn_softc *sc) 3227{ 3228 uint32_t rf_ac[2]; 3229 uint8_t txmode; 3230 int i; 3231 3232 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3233 if ((txmode & 0x70) != 0) { 3234 /* Disable all continuous Tx. */ 3235 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3236 3237 /* Set RF mode to standby mode. */ 3238 for (i = 0; i < sc->nrxchains; i++) { 3239 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3240 urtwn_rf_write(sc, i, R92C_RF_AC, 3241 RW(rf_ac[i], R92C_RF_AC_MODE, 3242 R92C_RF_AC_MODE_STANDBY)); 3243 } 3244 } else { 3245 /* Block all Tx queues. */ 3246 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3247 } 3248 /* Start calibration. */ 3249 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3250 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3251 3252 /* Give calibration the time to complete. */ 3253 usb_pause_mtx(&sc->sc_mtx, 100); 3254 3255 /* Restore configuration. */ 3256 if ((txmode & 0x70) != 0) { 3257 /* Restore Tx mode. */ 3258 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3259 /* Restore RF mode. */ 3260 for (i = 0; i < sc->nrxchains; i++) 3261 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3262 } else { 3263 /* Unblock all Tx queues. */ 3264 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3265 } 3266} 3267 3268static void 3269urtwn_init_locked(void *arg) 3270{ 3271 struct urtwn_softc *sc = arg; 3272 struct ifnet *ifp = sc->sc_ifp; 3273 uint32_t reg; 3274 int error; 3275 3276 URTWN_ASSERT_LOCKED(sc); 3277 3278 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3279 urtwn_stop_locked(ifp); 3280 3281 /* Init firmware commands ring. */ 3282 sc->fwcur = 0; 3283 3284 /* Allocate Tx/Rx buffers. */ 3285 error = urtwn_alloc_rx_list(sc); 3286 if (error != 0) 3287 goto fail; 3288 3289 error = urtwn_alloc_tx_list(sc); 3290 if (error != 0) 3291 goto fail; 3292 3293 /* Power on adapter. */ 3294 error = urtwn_power_on(sc); 3295 if (error != 0) 3296 goto fail; 3297 3298 /* Initialize DMA. */ 3299 error = urtwn_dma_init(sc); 3300 if (error != 0) 3301 goto fail; 3302 3303 /* Set info size in Rx descriptors (in 64-bit words). */ 3304 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3305 3306 /* Init interrupts. */ 3307 if (sc->chip & URTWN_CHIP_88E) { 3308 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3309 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3310 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3311 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3312 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3313 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3314 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3315 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3316 } else { 3317 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3318 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3319 } 3320 3321 /* Set MAC address. */ 3322 urtwn_write_region_1(sc, R92C_MACID, IF_LLADDR(ifp), 3323 IEEE80211_ADDR_LEN); 3324 3325 /* Set initial network type. */ 3326 reg = urtwn_read_4(sc, R92C_CR); 3327 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3328 urtwn_write_4(sc, R92C_CR, reg); 3329 3330 urtwn_rxfilter_init(sc); 3331 3332 reg = urtwn_read_4(sc, R92C_RRSR); 3333 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3334 urtwn_write_4(sc, R92C_RRSR, reg); 3335 3336 /* Set short/long retry limits. */ 3337 urtwn_write_2(sc, R92C_RL, 3338 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3339 3340 /* Initialize EDCA parameters. */ 3341 urtwn_edca_init(sc); 3342 3343 /* Setup rate fallback. */ 3344 if (!(sc->chip & URTWN_CHIP_88E)) { 3345 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3346 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3347 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3348 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3349 } 3350 3351 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3352 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3353 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3354 /* Set ACK timeout. */ 3355 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3356 3357 /* Setup USB aggregation. */ 3358 reg = urtwn_read_4(sc, R92C_TDECTRL); 3359 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3360 urtwn_write_4(sc, R92C_TDECTRL, reg); 3361 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3362 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3363 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3364 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3365 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3366 R92C_USB_SPECIAL_OPTION_AGG_EN); 3367 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3368 if (sc->chip & URTWN_CHIP_88E) 3369 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3370 else 3371 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3372 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3373 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3374 3375 /* Initialize beacon parameters. */ 3376 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3377 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3378 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3379 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3380 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3381 3382 if (!(sc->chip & URTWN_CHIP_88E)) { 3383 /* Setup AMPDU aggregation. */ 3384 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3385 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3386 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3387 3388 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3389 } 3390 3391 /* Load 8051 microcode. */ 3392 error = urtwn_load_firmware(sc); 3393 if (error != 0) 3394 goto fail; 3395 3396 /* Initialize MAC/BB/RF blocks. */ 3397 urtwn_mac_init(sc); 3398 urtwn_bb_init(sc); 3399 urtwn_rf_init(sc); 3400 3401 if (sc->chip & URTWN_CHIP_88E) { 3402 urtwn_write_2(sc, R92C_CR, 3403 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3404 R92C_CR_MACRXEN); 3405 } 3406 3407 /* Turn CCK and OFDM blocks on. */ 3408 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3409 reg |= R92C_RFMOD_CCK_EN; 3410 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3411 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3412 reg |= R92C_RFMOD_OFDM_EN; 3413 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3414 3415 /* Clear per-station keys table. */ 3416 urtwn_cam_init(sc); 3417 3418 /* Enable hardware sequence numbering. */ 3419 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3420 3421 /* Perform LO and IQ calibrations. */ 3422 urtwn_iq_calib(sc); 3423 /* Perform LC calibration. */ 3424 urtwn_lc_calib(sc); 3425 3426 /* Fix USB interference issue. */ 3427 if (!(sc->chip & URTWN_CHIP_88E)) { 3428 urtwn_write_1(sc, 0xfe40, 0xe0); 3429 urtwn_write_1(sc, 0xfe41, 0x8d); 3430 urtwn_write_1(sc, 0xfe42, 0x80); 3431 3432 urtwn_pa_bias_init(sc); 3433 } 3434 3435 /* Initialize GPIO setting. */ 3436 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3437 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3438 3439 /* Fix for lower temperature. */ 3440 if (!(sc->chip & URTWN_CHIP_88E)) 3441 urtwn_write_1(sc, 0x15, 0xe9); 3442 3443 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3444 3445 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3446 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3447 3448 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3449fail: 3450 return; 3451} 3452 3453static void 3454urtwn_init(void *arg) 3455{ 3456 struct urtwn_softc *sc = arg; 3457 3458 URTWN_LOCK(sc); 3459 urtwn_init_locked(arg); 3460 URTWN_UNLOCK(sc); 3461} 3462 3463static void 3464urtwn_stop_locked(struct ifnet *ifp) 3465{ 3466 struct urtwn_softc *sc = ifp->if_softc; 3467 3468 URTWN_ASSERT_LOCKED(sc); 3469 3470 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3471 3472 callout_stop(&sc->sc_watchdog_ch); 3473 urtwn_abort_xfers(sc); 3474} 3475 3476static void 3477urtwn_stop(struct ifnet *ifp) 3478{ 3479 struct urtwn_softc *sc = ifp->if_softc; 3480 3481 URTWN_LOCK(sc); 3482 urtwn_stop_locked(ifp); 3483 URTWN_UNLOCK(sc); 3484} 3485 3486static void 3487urtwn_abort_xfers(struct urtwn_softc *sc) 3488{ 3489 int i; 3490 3491 URTWN_ASSERT_LOCKED(sc); 3492 3493 /* abort any pending transfers */ 3494 for (i = 0; i < URTWN_N_TRANSFER; i++) 3495 usbd_transfer_stop(sc->sc_xfer[i]); 3496} 3497 3498static int 3499urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3500 const struct ieee80211_bpf_params *params) 3501{ 3502 struct ieee80211com *ic = ni->ni_ic; 3503 struct ifnet *ifp = ic->ic_ifp; 3504 struct urtwn_softc *sc = ifp->if_softc; 3505 struct urtwn_data *bf; 3506 3507 /* prevent management frames from being sent if we're not ready */ 3508 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3509 m_freem(m); 3510 ieee80211_free_node(ni); 3511 return (ENETDOWN); 3512 } 3513 URTWN_LOCK(sc); 3514 bf = urtwn_getbuf(sc); 3515 if (bf == NULL) { 3516 ieee80211_free_node(ni); 3517 m_freem(m); 3518 URTWN_UNLOCK(sc); 3519 return (ENOBUFS); 3520 } 3521 3522 ifp->if_opackets++; 3523 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3524 ieee80211_free_node(ni); 3525 ifp->if_oerrors++; 3526 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3527 URTWN_UNLOCK(sc); 3528 return (EIO); 3529 } 3530 URTWN_UNLOCK(sc); 3531 3532 sc->sc_txtimer = 5; 3533 return (0); 3534} 3535 3536static device_method_t urtwn_methods[] = { 3537 /* Device interface */ 3538 DEVMETHOD(device_probe, urtwn_match), 3539 DEVMETHOD(device_attach, urtwn_attach), 3540 DEVMETHOD(device_detach, urtwn_detach), 3541 3542 DEVMETHOD_END 3543}; 3544 3545static driver_t urtwn_driver = { 3546 "urtwn", 3547 urtwn_methods, 3548 sizeof(struct urtwn_softc) 3549}; 3550 3551static devclass_t urtwn_devclass; 3552 3553DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3554MODULE_DEPEND(urtwn, usb, 1, 1, 1); 3555MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3556MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3557MODULE_VERSION(urtwn, 1); 3558