if_urtwn.c revision 264972
1251538Srpaulo/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2251538Srpaulo 3251538Srpaulo/*- 4251538Srpaulo * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5264912Skevlo * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6251538Srpaulo * 7251538Srpaulo * Permission to use, copy, modify, and distribute this software for any 8251538Srpaulo * purpose with or without fee is hereby granted, provided that the above 9251538Srpaulo * copyright notice and this permission notice appear in all copies. 10251538Srpaulo * 11251538Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12251538Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13251538Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14251538Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15251538Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16251538Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17251538Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18251538Srpaulo */ 19251538Srpaulo 20251538Srpaulo#include <sys/cdefs.h> 21251538Srpaulo__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 264972 2014-04-26 14:39:58Z kevlo $"); 22251538Srpaulo 23251538Srpaulo/* 24264912Skevlo * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25251538Srpaulo */ 26251538Srpaulo 27251538Srpaulo#include <sys/param.h> 28251538Srpaulo#include <sys/sockio.h> 29251538Srpaulo#include <sys/sysctl.h> 30251538Srpaulo#include <sys/lock.h> 31251538Srpaulo#include <sys/mutex.h> 32251538Srpaulo#include <sys/mbuf.h> 33251538Srpaulo#include <sys/kernel.h> 34251538Srpaulo#include <sys/socket.h> 35251538Srpaulo#include <sys/systm.h> 36251538Srpaulo#include <sys/malloc.h> 37251538Srpaulo#include <sys/module.h> 38251538Srpaulo#include <sys/bus.h> 39251538Srpaulo#include <sys/endian.h> 40251538Srpaulo#include <sys/linker.h> 41251538Srpaulo#include <sys/firmware.h> 42251538Srpaulo#include <sys/kdb.h> 43251538Srpaulo 44251538Srpaulo#include <machine/bus.h> 45251538Srpaulo#include <machine/resource.h> 46251538Srpaulo#include <sys/rman.h> 47251538Srpaulo 48251538Srpaulo#include <net/bpf.h> 49251538Srpaulo#include <net/if.h> 50257176Sglebius#include <net/if_var.h> 51251538Srpaulo#include <net/if_arp.h> 52251538Srpaulo#include <net/ethernet.h> 53251538Srpaulo#include <net/if_dl.h> 54251538Srpaulo#include <net/if_media.h> 55251538Srpaulo#include <net/if_types.h> 56251538Srpaulo 57251538Srpaulo#include <netinet/in.h> 58251538Srpaulo#include <netinet/in_systm.h> 59251538Srpaulo#include <netinet/in_var.h> 60251538Srpaulo#include <netinet/if_ether.h> 61251538Srpaulo#include <netinet/ip.h> 62251538Srpaulo 63251538Srpaulo#include <net80211/ieee80211_var.h> 64251538Srpaulo#include <net80211/ieee80211_regdomain.h> 65251538Srpaulo#include <net80211/ieee80211_radiotap.h> 66251538Srpaulo#include <net80211/ieee80211_ratectl.h> 67251538Srpaulo 68251538Srpaulo#include <dev/usb/usb.h> 69251538Srpaulo#include <dev/usb/usbdi.h> 70251538Srpaulo#include "usbdevs.h" 71251538Srpaulo 72251538Srpaulo#define USB_DEBUG_VAR urtwn_debug 73251538Srpaulo#include <dev/usb/usb_debug.h> 74251538Srpaulo 75251538Srpaulo#include <dev/usb/wlan/if_urtwnreg.h> 76251538Srpaulo 77251538Srpaulo#ifdef USB_DEBUG 78251538Srpaulostatic int urtwn_debug = 0; 79251538Srpaulo 80251538SrpauloSYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 81251538SrpauloSYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RW, &urtwn_debug, 0, 82251538Srpaulo "Debug level"); 83251538Srpaulo#endif 84251538Srpaulo 85252406Srpaulo#define URTWN_RSSI(r) (r) - 110 86251538Srpaulo#define IEEE80211_HAS_ADDR4(wh) \ 87251538Srpaulo (((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) 88251538Srpaulo 89251538Srpaulo/* various supported device vendors/products */ 90251596Srpaulostatic const STRUCT_USB_HOST_ID urtwn_devs[] = { 91251538Srpaulo#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 92264912Skevlo#define URTWN_RTL8188E_DEV(v,p) \ 93264912Skevlo { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 94264912Skevlo#define URTWN_RTL8188E 1 95251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_1), 96251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_2), 97251538Srpaulo URTWN_DEV(ABOCOM, RTL8192CU), 98251538Srpaulo URTWN_DEV(ASUS, RTL8192CU), 99251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_1), 100251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_2), 101251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CU), 102251538Srpaulo URTWN_DEV(BELKIN, F7D2102), 103251538Srpaulo URTWN_DEV(BELKIN, RTL8188CU), 104251538Srpaulo URTWN_DEV(BELKIN, RTL8192CU), 105251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_1), 106251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_2), 107251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_3), 108251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_4), 109251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_5), 110251538Srpaulo URTWN_DEV(COREGA, RTL8192CU), 111251538Srpaulo URTWN_DEV(DLINK, RTL8188CU), 112251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_1), 113251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_2), 114251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_3), 115252196Skevlo URTWN_DEV(DLINK, DWA131B), 116251538Srpaulo URTWN_DEV(EDIMAX, EW7811UN), 117251538Srpaulo URTWN_DEV(EDIMAX, RTL8192CU), 118251538Srpaulo URTWN_DEV(FEIXUN, RTL8188CU), 119251538Srpaulo URTWN_DEV(FEIXUN, RTL8192CU), 120251538Srpaulo URTWN_DEV(GUILLEMOT, HWNUP150), 121251538Srpaulo URTWN_DEV(HAWKING, RTL8192CU), 122251538Srpaulo URTWN_DEV(HP3, RTL8188CU), 123251538Srpaulo URTWN_DEV(NETGEAR, WNA1000M), 124251538Srpaulo URTWN_DEV(NETGEAR, RTL8192CU), 125251538Srpaulo URTWN_DEV(NETGEAR4, RTL8188CU), 126251538Srpaulo URTWN_DEV(NOVATECH, RTL8188CU), 127251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_1), 128251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_2), 129251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_3), 130251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_4), 131251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CUS), 132251538Srpaulo URTWN_DEV(PLANEX2, RTL8192CU), 133251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_0), 134251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_1), 135251538Srpaulo URTWN_DEV(REALTEK, RTL8188CTV), 136251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_0), 137251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_1), 138251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_2), 139251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_COMBO), 140251538Srpaulo URTWN_DEV(REALTEK, RTL8188CUS), 141251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_1), 142251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_2), 143251538Srpaulo URTWN_DEV(REALTEK, RTL8191CU), 144251538Srpaulo URTWN_DEV(REALTEK, RTL8192CE), 145251538Srpaulo URTWN_DEV(REALTEK, RTL8192CU), 146257543Salfred URTWN_DEV(REALTEK, RTL8188CU_0), 147251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_1), 148251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_2), 149251538Srpaulo URTWN_DEV(SITECOMEU, RTL8192CU), 150251538Srpaulo URTWN_DEV(TRENDNET, RTL8188CU), 151251538Srpaulo URTWN_DEV(TRENDNET, RTL8192CU), 152251538Srpaulo URTWN_DEV(ZYXEL, RTL8192CU), 153264912Skevlo /* URTWN_RTL8188E */ 154264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 155264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 156264912Skevlo#undef URTWN_RTL8188E_DEV 157251538Srpaulo#undef URTWN_DEV 158251538Srpaulo}; 159251538Srpaulo 160251538Srpaulostatic device_probe_t urtwn_match; 161251538Srpaulostatic device_attach_t urtwn_attach; 162251538Srpaulostatic device_detach_t urtwn_detach; 163251538Srpaulo 164251538Srpaulostatic usb_callback_t urtwn_bulk_tx_callback; 165251538Srpaulostatic usb_callback_t urtwn_bulk_rx_callback; 166251538Srpaulo 167251538Srpaulostatic usb_error_t urtwn_do_request(struct urtwn_softc *sc, 168251538Srpaulo struct usb_device_request *req, void *data); 169251538Srpaulostatic struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 170251538Srpaulo const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 171251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN], 172251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN]); 173251538Srpaulostatic void urtwn_vap_delete(struct ieee80211vap *); 174251538Srpaulostatic struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 175251538Srpaulo int *); 176251538Srpaulostatic struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 177251538Srpaulo int *, int8_t *); 178251538Srpaulostatic void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 179251538Srpaulostatic int urtwn_alloc_list(struct urtwn_softc *, 180251538Srpaulo struct urtwn_data[], int, int); 181251538Srpaulostatic int urtwn_alloc_rx_list(struct urtwn_softc *); 182251538Srpaulostatic int urtwn_alloc_tx_list(struct urtwn_softc *); 183251538Srpaulostatic void urtwn_free_tx_list(struct urtwn_softc *); 184251538Srpaulostatic void urtwn_free_rx_list(struct urtwn_softc *); 185251538Srpaulostatic void urtwn_free_list(struct urtwn_softc *, 186251538Srpaulo struct urtwn_data data[], int); 187251538Srpaulostatic struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 188251538Srpaulostatic struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 189251538Srpaulostatic int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 190251538Srpaulo uint8_t *, int); 191251538Srpaulostatic void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 192251538Srpaulostatic void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 193251538Srpaulostatic void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 194251538Srpaulostatic int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 195251538Srpaulo uint8_t *, int); 196251538Srpaulostatic uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 197251538Srpaulostatic uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 198251538Srpaulostatic uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 199251538Srpaulostatic int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 200251538Srpaulo const void *, int); 201264912Skevlostatic void urtwn_r92c_rf_write(struct urtwn_softc *, int, 202264912Skevlo uint8_t, uint32_t); 203264912Skevlostatic void urtwn_r88e_rf_write(struct urtwn_softc *, int, 204264912Skevlo uint8_t, uint32_t); 205251538Srpaulostatic uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 206251538Srpaulostatic int urtwn_llt_write(struct urtwn_softc *, uint32_t, 207251538Srpaulo uint32_t); 208251538Srpaulostatic uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 209251538Srpaulostatic void urtwn_efuse_read(struct urtwn_softc *); 210264912Skevlostatic void urtwn_efuse_switch_power(struct urtwn_softc *); 211251538Srpaulostatic int urtwn_read_chipid(struct urtwn_softc *); 212251538Srpaulostatic void urtwn_read_rom(struct urtwn_softc *); 213264912Skevlostatic void urtwn_r88e_read_rom(struct urtwn_softc *); 214251538Srpaulostatic int urtwn_ra_init(struct urtwn_softc *); 215251538Srpaulostatic void urtwn_tsf_sync_enable(struct urtwn_softc *); 216251538Srpaulostatic void urtwn_set_led(struct urtwn_softc *, int, int); 217251538Srpaulostatic int urtwn_newstate(struct ieee80211vap *, 218251538Srpaulo enum ieee80211_state, int); 219251538Srpaulostatic void urtwn_watchdog(void *); 220251538Srpaulostatic void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 221251538Srpaulostatic int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 222264912Skevlostatic int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 223251538Srpaulostatic int urtwn_tx_start(struct urtwn_softc *, 224251538Srpaulo struct ieee80211_node *, struct mbuf *, 225251538Srpaulo struct urtwn_data *); 226251538Srpaulostatic void urtwn_start(struct ifnet *); 227261863Srpaulostatic void urtwn_start_locked(struct ifnet *, 228261863Srpaulo struct urtwn_softc *); 229251538Srpaulostatic int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 230264912Skevlostatic int urtwn_r92c_power_on(struct urtwn_softc *); 231264912Skevlostatic int urtwn_r88e_power_on(struct urtwn_softc *); 232251538Srpaulostatic int urtwn_llt_init(struct urtwn_softc *); 233251538Srpaulostatic void urtwn_fw_reset(struct urtwn_softc *); 234264912Skevlostatic void urtwn_r88e_fw_reset(struct urtwn_softc *); 235251538Srpaulostatic int urtwn_fw_loadpage(struct urtwn_softc *, int, 236251538Srpaulo const uint8_t *, int); 237251538Srpaulostatic int urtwn_load_firmware(struct urtwn_softc *); 238264912Skevlostatic int urtwn_r92c_dma_init(struct urtwn_softc *); 239264912Skevlostatic int urtwn_r88e_dma_init(struct urtwn_softc *); 240251538Srpaulostatic void urtwn_mac_init(struct urtwn_softc *); 241251538Srpaulostatic void urtwn_bb_init(struct urtwn_softc *); 242251538Srpaulostatic void urtwn_rf_init(struct urtwn_softc *); 243251538Srpaulostatic void urtwn_cam_init(struct urtwn_softc *); 244251538Srpaulostatic void urtwn_pa_bias_init(struct urtwn_softc *); 245251538Srpaulostatic void urtwn_rxfilter_init(struct urtwn_softc *); 246251538Srpaulostatic void urtwn_edca_init(struct urtwn_softc *); 247251538Srpaulostatic void urtwn_write_txpower(struct urtwn_softc *, int, 248251538Srpaulo uint16_t[]); 249251538Srpaulostatic void urtwn_get_txpower(struct urtwn_softc *, int, 250251538Srpaulo struct ieee80211_channel *, 251251538Srpaulo struct ieee80211_channel *, uint16_t[]); 252264912Skevlostatic void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 253264912Skevlo struct ieee80211_channel *, 254264912Skevlo struct ieee80211_channel *, uint16_t[]); 255251538Srpaulostatic void urtwn_set_txpower(struct urtwn_softc *, 256251538Srpaulo struct ieee80211_channel *, 257251538Srpaulo struct ieee80211_channel *); 258251538Srpaulostatic void urtwn_scan_start(struct ieee80211com *); 259251538Srpaulostatic void urtwn_scan_end(struct ieee80211com *); 260251538Srpaulostatic void urtwn_set_channel(struct ieee80211com *); 261251538Srpaulostatic void urtwn_set_chan(struct urtwn_softc *, 262251538Srpaulo struct ieee80211_channel *, 263251538Srpaulo struct ieee80211_channel *); 264251538Srpaulostatic void urtwn_update_mcast(struct ifnet *); 265251538Srpaulostatic void urtwn_iq_calib(struct urtwn_softc *); 266251538Srpaulostatic void urtwn_lc_calib(struct urtwn_softc *); 267251538Srpaulostatic void urtwn_init(void *); 268251538Srpaulostatic void urtwn_init_locked(void *); 269263153Skevlostatic void urtwn_stop(struct ifnet *); 270263153Skevlostatic void urtwn_stop_locked(struct ifnet *); 271251538Srpaulostatic void urtwn_abort_xfers(struct urtwn_softc *); 272251538Srpaulostatic int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 273251538Srpaulo const struct ieee80211_bpf_params *); 274251538Srpaulo 275251538Srpaulo/* Aliases. */ 276251538Srpaulo#define urtwn_bb_write urtwn_write_4 277251538Srpaulo#define urtwn_bb_read urtwn_read_4 278251538Srpaulo 279251538Srpaulostatic const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 280251538Srpaulo [URTWN_BULK_RX] = { 281251538Srpaulo .type = UE_BULK, 282251538Srpaulo .endpoint = UE_ADDR_ANY, 283251538Srpaulo .direction = UE_DIR_IN, 284251538Srpaulo .bufsize = URTWN_RXBUFSZ, 285251538Srpaulo .flags = { 286251538Srpaulo .pipe_bof = 1, 287251538Srpaulo .short_xfer_ok = 1 288251538Srpaulo }, 289251538Srpaulo .callback = urtwn_bulk_rx_callback, 290251538Srpaulo }, 291251538Srpaulo [URTWN_BULK_TX_BE] = { 292251538Srpaulo .type = UE_BULK, 293251538Srpaulo .endpoint = 0x03, 294251538Srpaulo .direction = UE_DIR_OUT, 295251538Srpaulo .bufsize = URTWN_TXBUFSZ, 296251538Srpaulo .flags = { 297251538Srpaulo .ext_buffer = 1, 298251538Srpaulo .pipe_bof = 1, 299251538Srpaulo .force_short_xfer = 1 300251538Srpaulo }, 301251538Srpaulo .callback = urtwn_bulk_tx_callback, 302251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 303251538Srpaulo }, 304251538Srpaulo [URTWN_BULK_TX_BK] = { 305251538Srpaulo .type = UE_BULK, 306251538Srpaulo .endpoint = 0x03, 307251538Srpaulo .direction = UE_DIR_OUT, 308251538Srpaulo .bufsize = URTWN_TXBUFSZ, 309251538Srpaulo .flags = { 310251538Srpaulo .ext_buffer = 1, 311251538Srpaulo .pipe_bof = 1, 312251538Srpaulo .force_short_xfer = 1, 313251538Srpaulo }, 314251538Srpaulo .callback = urtwn_bulk_tx_callback, 315251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 316251538Srpaulo }, 317251538Srpaulo [URTWN_BULK_TX_VI] = { 318251538Srpaulo .type = UE_BULK, 319251538Srpaulo .endpoint = 0x02, 320251538Srpaulo .direction = UE_DIR_OUT, 321251538Srpaulo .bufsize = URTWN_TXBUFSZ, 322251538Srpaulo .flags = { 323251538Srpaulo .ext_buffer = 1, 324251538Srpaulo .pipe_bof = 1, 325251538Srpaulo .force_short_xfer = 1 326251538Srpaulo }, 327251538Srpaulo .callback = urtwn_bulk_tx_callback, 328251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 329251538Srpaulo }, 330251538Srpaulo [URTWN_BULK_TX_VO] = { 331251538Srpaulo .type = UE_BULK, 332251538Srpaulo .endpoint = 0x02, 333251538Srpaulo .direction = UE_DIR_OUT, 334251538Srpaulo .bufsize = URTWN_TXBUFSZ, 335251538Srpaulo .flags = { 336251538Srpaulo .ext_buffer = 1, 337251538Srpaulo .pipe_bof = 1, 338251538Srpaulo .force_short_xfer = 1 339251538Srpaulo }, 340251538Srpaulo .callback = urtwn_bulk_tx_callback, 341251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 342251538Srpaulo }, 343251538Srpaulo}; 344251538Srpaulo 345251538Srpaulostatic int 346251538Srpaulourtwn_match(device_t self) 347251538Srpaulo{ 348251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 349251538Srpaulo 350251538Srpaulo if (uaa->usb_mode != USB_MODE_HOST) 351251538Srpaulo return (ENXIO); 352251538Srpaulo if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 353251538Srpaulo return (ENXIO); 354251538Srpaulo if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 355251538Srpaulo return (ENXIO); 356251538Srpaulo 357251538Srpaulo return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 358251538Srpaulo} 359251538Srpaulo 360251538Srpaulostatic int 361251538Srpaulourtwn_attach(device_t self) 362251538Srpaulo{ 363251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 364251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 365251538Srpaulo struct ifnet *ifp; 366251538Srpaulo struct ieee80211com *ic; 367251538Srpaulo uint8_t iface_index, bands; 368251538Srpaulo int error; 369251538Srpaulo 370251538Srpaulo device_set_usb_desc(self); 371251538Srpaulo sc->sc_udev = uaa->device; 372251538Srpaulo sc->sc_dev = self; 373264912Skevlo if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 374264912Skevlo sc->chip |= URTWN_CHIP_88E; 375251538Srpaulo 376251538Srpaulo mtx_init(&sc->sc_mtx, device_get_nameunit(self), 377251538Srpaulo MTX_NETWORK_LOCK, MTX_DEF); 378251538Srpaulo callout_init(&sc->sc_watchdog_ch, 0); 379251538Srpaulo 380251538Srpaulo iface_index = URTWN_IFACE_INDEX; 381251538Srpaulo error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 382251538Srpaulo urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 383251538Srpaulo if (error) { 384251538Srpaulo device_printf(self, "could not allocate USB transfers, " 385251538Srpaulo "err=%s\n", usbd_errstr(error)); 386251538Srpaulo goto detach; 387251538Srpaulo } 388251538Srpaulo 389251538Srpaulo URTWN_LOCK(sc); 390251538Srpaulo 391251538Srpaulo error = urtwn_read_chipid(sc); 392251538Srpaulo if (error) { 393251538Srpaulo device_printf(sc->sc_dev, "unsupported test chip\n"); 394251538Srpaulo URTWN_UNLOCK(sc); 395251538Srpaulo goto detach; 396251538Srpaulo } 397251538Srpaulo 398251538Srpaulo /* Determine number of Tx/Rx chains. */ 399251538Srpaulo if (sc->chip & URTWN_CHIP_92C) { 400251538Srpaulo sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 401251538Srpaulo sc->nrxchains = 2; 402251538Srpaulo } else { 403251538Srpaulo sc->ntxchains = 1; 404251538Srpaulo sc->nrxchains = 1; 405251538Srpaulo } 406251538Srpaulo 407264912Skevlo if (sc->chip & URTWN_CHIP_88E) 408264912Skevlo urtwn_r88e_read_rom(sc); 409264912Skevlo else 410264912Skevlo urtwn_read_rom(sc); 411264912Skevlo 412251538Srpaulo device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 413251538Srpaulo (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 414264912Skevlo (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 415251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 416251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 417251538Srpaulo "8188CUS", sc->ntxchains, sc->nrxchains); 418251538Srpaulo 419251538Srpaulo URTWN_UNLOCK(sc); 420251538Srpaulo 421251538Srpaulo ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 422251538Srpaulo if (ifp == NULL) { 423251538Srpaulo device_printf(sc->sc_dev, "can not if_alloc()\n"); 424251538Srpaulo goto detach; 425251538Srpaulo } 426251538Srpaulo ic = ifp->if_l2com; 427251538Srpaulo 428251538Srpaulo ifp->if_softc = sc; 429251538Srpaulo if_initname(ifp, "urtwn", device_get_unit(sc->sc_dev)); 430251538Srpaulo ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 431251538Srpaulo ifp->if_init = urtwn_init; 432251538Srpaulo ifp->if_ioctl = urtwn_ioctl; 433251538Srpaulo ifp->if_start = urtwn_start; 434251538Srpaulo IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 435251538Srpaulo ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 436251538Srpaulo IFQ_SET_READY(&ifp->if_snd); 437251538Srpaulo 438251538Srpaulo ic->ic_ifp = ifp; 439251538Srpaulo ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 440251538Srpaulo ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 441251538Srpaulo 442251538Srpaulo /* set device capabilities */ 443251538Srpaulo ic->ic_caps = 444251538Srpaulo IEEE80211_C_STA /* station mode */ 445251538Srpaulo | IEEE80211_C_MONITOR /* monitor mode */ 446251538Srpaulo | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 447251538Srpaulo | IEEE80211_C_SHSLOT /* short slot time supported */ 448251538Srpaulo | IEEE80211_C_BGSCAN /* capable of bg scanning */ 449251538Srpaulo | IEEE80211_C_WPA /* 802.11i */ 450251538Srpaulo ; 451251538Srpaulo 452251538Srpaulo bands = 0; 453251538Srpaulo setbit(&bands, IEEE80211_MODE_11B); 454251538Srpaulo setbit(&bands, IEEE80211_MODE_11G); 455251538Srpaulo ieee80211_init_channels(ic, NULL, &bands); 456251538Srpaulo 457251538Srpaulo ieee80211_ifattach(ic, sc->sc_bssid); 458251538Srpaulo ic->ic_raw_xmit = urtwn_raw_xmit; 459251538Srpaulo ic->ic_scan_start = urtwn_scan_start; 460251538Srpaulo ic->ic_scan_end = urtwn_scan_end; 461251538Srpaulo ic->ic_set_channel = urtwn_set_channel; 462251538Srpaulo 463251538Srpaulo ic->ic_vap_create = urtwn_vap_create; 464251538Srpaulo ic->ic_vap_delete = urtwn_vap_delete; 465251538Srpaulo ic->ic_update_mcast = urtwn_update_mcast; 466251538Srpaulo 467251538Srpaulo ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 468251538Srpaulo sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 469251538Srpaulo &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 470251538Srpaulo URTWN_RX_RADIOTAP_PRESENT); 471251538Srpaulo 472251538Srpaulo if (bootverbose) 473251538Srpaulo ieee80211_announce(ic); 474251538Srpaulo 475251538Srpaulo return (0); 476251538Srpaulo 477251538Srpaulodetach: 478251538Srpaulo urtwn_detach(self); 479251538Srpaulo return (ENXIO); /* failure */ 480251538Srpaulo} 481251538Srpaulo 482251538Srpaulostatic int 483251538Srpaulourtwn_detach(device_t self) 484251538Srpaulo{ 485251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 486251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 487251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 488263153Skevlo unsigned int x; 489251538Srpaulo 490263153Skevlo /* Prevent further ioctls. */ 491263153Skevlo URTWN_LOCK(sc); 492263153Skevlo sc->sc_flags |= URTWN_DETACHED; 493263153Skevlo URTWN_UNLOCK(sc); 494251538Srpaulo 495263153Skevlo urtwn_stop(ifp); 496251538Srpaulo 497251538Srpaulo callout_drain(&sc->sc_watchdog_ch); 498251538Srpaulo 499263153Skevlo /* Prevent further allocations from RX/TX data lists. */ 500263153Skevlo URTWN_LOCK(sc); 501263153Skevlo STAILQ_INIT(&sc->sc_tx_active); 502263153Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 503263153Skevlo STAILQ_INIT(&sc->sc_tx_pending); 504263153Skevlo 505263153Skevlo STAILQ_INIT(&sc->sc_rx_active); 506263153Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 507263153Skevlo URTWN_UNLOCK(sc); 508263153Skevlo 509263153Skevlo /* drain USB transfers */ 510263153Skevlo for (x = 0; x != URTWN_N_TRANSFER; x++) 511263153Skevlo usbd_transfer_drain(sc->sc_xfer[x]); 512263153Skevlo 513263153Skevlo /* Free data buffers. */ 514263153Skevlo URTWN_LOCK(sc); 515263153Skevlo urtwn_free_tx_list(sc); 516263153Skevlo urtwn_free_rx_list(sc); 517263153Skevlo URTWN_UNLOCK(sc); 518263153Skevlo 519251538Srpaulo /* stop all USB transfers */ 520251538Srpaulo usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 521251538Srpaulo ieee80211_ifdetach(ic); 522251538Srpaulo 523251538Srpaulo if_free(ifp); 524251538Srpaulo mtx_destroy(&sc->sc_mtx); 525251538Srpaulo 526251538Srpaulo return (0); 527251538Srpaulo} 528251538Srpaulo 529251538Srpaulostatic void 530251538Srpaulourtwn_free_tx_list(struct urtwn_softc *sc) 531251538Srpaulo{ 532251538Srpaulo urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 533251538Srpaulo} 534251538Srpaulo 535251538Srpaulostatic void 536251538Srpaulourtwn_free_rx_list(struct urtwn_softc *sc) 537251538Srpaulo{ 538251538Srpaulo urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 539251538Srpaulo} 540251538Srpaulo 541251538Srpaulostatic void 542251538Srpaulourtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 543251538Srpaulo{ 544251538Srpaulo int i; 545251538Srpaulo 546251538Srpaulo for (i = 0; i < ndata; i++) { 547251538Srpaulo struct urtwn_data *dp = &data[i]; 548251538Srpaulo 549251538Srpaulo if (dp->buf != NULL) { 550251538Srpaulo free(dp->buf, M_USBDEV); 551251538Srpaulo dp->buf = NULL; 552251538Srpaulo } 553251538Srpaulo if (dp->ni != NULL) { 554251538Srpaulo ieee80211_free_node(dp->ni); 555251538Srpaulo dp->ni = NULL; 556251538Srpaulo } 557251538Srpaulo } 558251538Srpaulo} 559251538Srpaulo 560251538Srpaulostatic usb_error_t 561251538Srpaulourtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 562251538Srpaulo void *data) 563251538Srpaulo{ 564251538Srpaulo usb_error_t err; 565251538Srpaulo int ntries = 10; 566251538Srpaulo 567251538Srpaulo URTWN_ASSERT_LOCKED(sc); 568251538Srpaulo 569251538Srpaulo while (ntries--) { 570251538Srpaulo err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 571251538Srpaulo req, data, 0, NULL, 250 /* ms */); 572251538Srpaulo if (err == 0) 573251538Srpaulo break; 574251538Srpaulo 575251538Srpaulo DPRINTFN(1, "Control request failed, %s (retrying)\n", 576251538Srpaulo usbd_errstr(err)); 577251538Srpaulo usb_pause_mtx(&sc->sc_mtx, hz / 100); 578251538Srpaulo } 579251538Srpaulo return (err); 580251538Srpaulo} 581251538Srpaulo 582251538Srpaulostatic struct ieee80211vap * 583251538Srpaulourtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 584251538Srpaulo enum ieee80211_opmode opmode, int flags, 585251538Srpaulo const uint8_t bssid[IEEE80211_ADDR_LEN], 586251538Srpaulo const uint8_t mac[IEEE80211_ADDR_LEN]) 587251538Srpaulo{ 588251538Srpaulo struct urtwn_vap *uvp; 589251538Srpaulo struct ieee80211vap *vap; 590251538Srpaulo 591251538Srpaulo if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 592251538Srpaulo return (NULL); 593251538Srpaulo 594251538Srpaulo uvp = (struct urtwn_vap *) malloc(sizeof(struct urtwn_vap), 595251538Srpaulo M_80211_VAP, M_NOWAIT | M_ZERO); 596251538Srpaulo if (uvp == NULL) 597251538Srpaulo return (NULL); 598251538Srpaulo vap = &uvp->vap; 599251538Srpaulo /* enable s/w bmiss handling for sta mode */ 600251538Srpaulo 601257743Shselasky if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 602257743Shselasky flags | IEEE80211_CLONE_NOBEACONS, bssid, mac) != 0) { 603257743Shselasky /* out of memory */ 604257743Shselasky free(uvp, M_80211_VAP); 605257743Shselasky return (NULL); 606257743Shselasky } 607257743Shselasky 608251538Srpaulo /* override state transition machine */ 609251538Srpaulo uvp->newstate = vap->iv_newstate; 610251538Srpaulo vap->iv_newstate = urtwn_newstate; 611251538Srpaulo 612251538Srpaulo /* complete setup */ 613251538Srpaulo ieee80211_vap_attach(vap, ieee80211_media_change, 614251538Srpaulo ieee80211_media_status); 615251538Srpaulo ic->ic_opmode = opmode; 616251538Srpaulo return (vap); 617251538Srpaulo} 618251538Srpaulo 619251538Srpaulostatic void 620251538Srpaulourtwn_vap_delete(struct ieee80211vap *vap) 621251538Srpaulo{ 622251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 623251538Srpaulo 624251538Srpaulo ieee80211_vap_detach(vap); 625251538Srpaulo free(uvp, M_80211_VAP); 626251538Srpaulo} 627251538Srpaulo 628251538Srpaulostatic struct mbuf * 629251538Srpaulourtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 630251538Srpaulo{ 631251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 632251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 633251538Srpaulo struct ieee80211_frame *wh; 634251538Srpaulo struct mbuf *m; 635251538Srpaulo struct r92c_rx_stat *stat; 636251538Srpaulo uint32_t rxdw0, rxdw3; 637251538Srpaulo uint8_t rate; 638251538Srpaulo int8_t rssi = 0; 639251538Srpaulo int infosz; 640251538Srpaulo 641251538Srpaulo /* 642251538Srpaulo * don't pass packets to the ieee80211 framework if the driver isn't 643251538Srpaulo * RUNNING. 644251538Srpaulo */ 645251538Srpaulo if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 646251538Srpaulo return (NULL); 647251538Srpaulo 648251538Srpaulo stat = (struct r92c_rx_stat *)buf; 649251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 650251538Srpaulo rxdw3 = le32toh(stat->rxdw3); 651251538Srpaulo 652251538Srpaulo if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 653251538Srpaulo /* 654251538Srpaulo * This should not happen since we setup our Rx filter 655251538Srpaulo * to not receive these frames. 656251538Srpaulo */ 657251538Srpaulo ifp->if_ierrors++; 658251538Srpaulo return (NULL); 659251538Srpaulo } 660251538Srpaulo 661251538Srpaulo rate = MS(rxdw3, R92C_RXDW3_RATE); 662251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 663251538Srpaulo 664251538Srpaulo /* Get RSSI from PHY status descriptor if present. */ 665251538Srpaulo if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 666264912Skevlo if (sc->chip & URTWN_CHIP_88E) 667264912Skevlo rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 668264912Skevlo else 669264912Skevlo rssi = urtwn_get_rssi(sc, rate, &stat[1]); 670251538Srpaulo /* Update our average RSSI. */ 671251538Srpaulo urtwn_update_avgrssi(sc, rate, rssi); 672252405Srpaulo /* 673252405Srpaulo * Convert the RSSI to a range that will be accepted 674252405Srpaulo * by net80211. 675252405Srpaulo */ 676252405Srpaulo rssi = URTWN_RSSI(rssi); 677251538Srpaulo } 678251538Srpaulo 679260463Skevlo m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 680251538Srpaulo if (m == NULL) { 681251538Srpaulo device_printf(sc->sc_dev, "could not create RX mbuf\n"); 682251538Srpaulo return (NULL); 683251538Srpaulo } 684251538Srpaulo 685251538Srpaulo /* Finalize mbuf. */ 686251538Srpaulo m->m_pkthdr.rcvif = ifp; 687251538Srpaulo wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 688251538Srpaulo memcpy(mtod(m, uint8_t *), wh, pktlen); 689251538Srpaulo m->m_pkthdr.len = m->m_len = pktlen; 690251538Srpaulo 691251538Srpaulo if (ieee80211_radiotap_active(ic)) { 692251538Srpaulo struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 693251538Srpaulo 694251538Srpaulo tap->wr_flags = 0; 695251538Srpaulo /* Map HW rate index to 802.11 rate. */ 696251538Srpaulo if (!(rxdw3 & R92C_RXDW3_HT)) { 697251538Srpaulo switch (rate) { 698251538Srpaulo /* CCK. */ 699251538Srpaulo case 0: tap->wr_rate = 2; break; 700251538Srpaulo case 1: tap->wr_rate = 4; break; 701251538Srpaulo case 2: tap->wr_rate = 11; break; 702251538Srpaulo case 3: tap->wr_rate = 22; break; 703251538Srpaulo /* OFDM. */ 704251538Srpaulo case 4: tap->wr_rate = 12; break; 705251538Srpaulo case 5: tap->wr_rate = 18; break; 706251538Srpaulo case 6: tap->wr_rate = 24; break; 707251538Srpaulo case 7: tap->wr_rate = 36; break; 708251538Srpaulo case 8: tap->wr_rate = 48; break; 709251538Srpaulo case 9: tap->wr_rate = 72; break; 710251538Srpaulo case 10: tap->wr_rate = 96; break; 711251538Srpaulo case 11: tap->wr_rate = 108; break; 712251538Srpaulo } 713251538Srpaulo } else if (rate >= 12) { /* MCS0~15. */ 714251538Srpaulo /* Bit 7 set means HT MCS instead of rate. */ 715251538Srpaulo tap->wr_rate = 0x80 | (rate - 12); 716251538Srpaulo } 717251538Srpaulo tap->wr_dbm_antsignal = rssi; 718251538Srpaulo tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 719251538Srpaulo tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 720251538Srpaulo } 721251538Srpaulo 722251538Srpaulo *rssi_p = rssi; 723251538Srpaulo 724251538Srpaulo return (m); 725251538Srpaulo} 726251538Srpaulo 727251538Srpaulostatic struct mbuf * 728251538Srpaulourtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 729251538Srpaulo int8_t *nf) 730251538Srpaulo{ 731251538Srpaulo struct urtwn_softc *sc = data->sc; 732251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 733251538Srpaulo struct r92c_rx_stat *stat; 734251538Srpaulo struct mbuf *m, *m0 = NULL, *prevm = NULL; 735251538Srpaulo uint32_t rxdw0; 736251538Srpaulo uint8_t *buf; 737251538Srpaulo int len, totlen, pktlen, infosz, npkts; 738251538Srpaulo 739251538Srpaulo usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 740251538Srpaulo 741251538Srpaulo if (len < sizeof(*stat)) { 742251538Srpaulo ifp->if_ierrors++; 743251538Srpaulo return (NULL); 744251538Srpaulo } 745251538Srpaulo 746251538Srpaulo buf = data->buf; 747251538Srpaulo /* Get the number of encapsulated frames. */ 748251538Srpaulo stat = (struct r92c_rx_stat *)buf; 749251538Srpaulo npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 750251538Srpaulo DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 751251538Srpaulo 752251538Srpaulo /* Process all of them. */ 753251538Srpaulo while (npkts-- > 0) { 754251538Srpaulo if (len < sizeof(*stat)) 755251538Srpaulo break; 756251538Srpaulo stat = (struct r92c_rx_stat *)buf; 757251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 758251538Srpaulo 759251538Srpaulo pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 760251538Srpaulo if (pktlen == 0) 761251538Srpaulo break; 762251538Srpaulo 763251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 764251538Srpaulo 765251538Srpaulo /* Make sure everything fits in xfer. */ 766251538Srpaulo totlen = sizeof(*stat) + infosz + pktlen; 767251538Srpaulo if (totlen > len) 768251538Srpaulo break; 769251538Srpaulo 770251538Srpaulo m = urtwn_rx_frame(sc, buf, pktlen, rssi); 771251538Srpaulo if (m0 == NULL) 772251538Srpaulo m0 = m; 773251538Srpaulo if (prevm == NULL) 774251538Srpaulo prevm = m; 775251538Srpaulo else { 776251538Srpaulo prevm->m_next = m; 777251538Srpaulo prevm = m; 778251538Srpaulo } 779251538Srpaulo 780251538Srpaulo /* Next chunk is 128-byte aligned. */ 781251538Srpaulo totlen = (totlen + 127) & ~127; 782251538Srpaulo buf += totlen; 783251538Srpaulo len -= totlen; 784251538Srpaulo } 785251538Srpaulo 786251538Srpaulo return (m0); 787251538Srpaulo} 788251538Srpaulo 789251538Srpaulostatic void 790251538Srpaulourtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 791251538Srpaulo{ 792251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 793251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 794251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 795251538Srpaulo struct ieee80211_frame *wh; 796251538Srpaulo struct ieee80211_node *ni; 797251538Srpaulo struct mbuf *m = NULL, *next; 798251538Srpaulo struct urtwn_data *data; 799251538Srpaulo int8_t nf; 800251538Srpaulo int rssi = 1; 801251538Srpaulo 802251538Srpaulo URTWN_ASSERT_LOCKED(sc); 803251538Srpaulo 804251538Srpaulo switch (USB_GET_STATE(xfer)) { 805251538Srpaulo case USB_ST_TRANSFERRED: 806251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 807251538Srpaulo if (data == NULL) 808251538Srpaulo goto tr_setup; 809251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 810251538Srpaulo m = urtwn_rxeof(xfer, data, &rssi, &nf); 811251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 812251538Srpaulo /* FALLTHROUGH */ 813251538Srpaulo case USB_ST_SETUP: 814251538Srpaulotr_setup: 815251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_inactive); 816251538Srpaulo if (data == NULL) { 817251538Srpaulo KASSERT(m == NULL, ("mbuf isn't NULL")); 818251538Srpaulo return; 819251538Srpaulo } 820251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 821251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 822251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, 823251538Srpaulo usbd_xfer_max_len(xfer)); 824251538Srpaulo usbd_transfer_submit(xfer); 825251538Srpaulo 826251538Srpaulo /* 827251538Srpaulo * To avoid LOR we should unlock our private mutex here to call 828251538Srpaulo * ieee80211_input() because here is at the end of a USB 829251538Srpaulo * callback and safe to unlock. 830251538Srpaulo */ 831251538Srpaulo URTWN_UNLOCK(sc); 832251538Srpaulo while (m != NULL) { 833251538Srpaulo next = m->m_next; 834251538Srpaulo m->m_next = NULL; 835251538Srpaulo wh = mtod(m, struct ieee80211_frame *); 836251538Srpaulo ni = ieee80211_find_rxnode(ic, 837251538Srpaulo (struct ieee80211_frame_min *)wh); 838251538Srpaulo nf = URTWN_NOISE_FLOOR; 839251538Srpaulo if (ni != NULL) { 840251538Srpaulo (void)ieee80211_input(ni, m, rssi, nf); 841251538Srpaulo ieee80211_free_node(ni); 842251538Srpaulo } else 843251538Srpaulo (void)ieee80211_input_all(ic, m, rssi, nf); 844251538Srpaulo m = next; 845251538Srpaulo } 846251538Srpaulo URTWN_LOCK(sc); 847251538Srpaulo break; 848251538Srpaulo default: 849251538Srpaulo /* needs it to the inactive queue due to a error. */ 850251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 851251538Srpaulo if (data != NULL) { 852251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 853251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 854251538Srpaulo } 855251538Srpaulo if (error != USB_ERR_CANCELLED) { 856251538Srpaulo usbd_xfer_set_stall(xfer); 857251538Srpaulo ifp->if_ierrors++; 858251538Srpaulo goto tr_setup; 859251538Srpaulo } 860251538Srpaulo break; 861251538Srpaulo } 862251538Srpaulo} 863251538Srpaulo 864251538Srpaulostatic void 865251538Srpaulourtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 866251538Srpaulo{ 867251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 868251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 869251538Srpaulo struct mbuf *m; 870251538Srpaulo 871251538Srpaulo URTWN_ASSERT_LOCKED(sc); 872251538Srpaulo 873251538Srpaulo /* 874251538Srpaulo * Do any tx complete callback. Note this must be done before releasing 875251538Srpaulo * the node reference. 876251538Srpaulo */ 877251538Srpaulo if (data->m) { 878251538Srpaulo m = data->m; 879251538Srpaulo if (m->m_flags & M_TXCB) { 880251538Srpaulo /* XXX status? */ 881251538Srpaulo ieee80211_process_callback(data->ni, m, 0); 882251538Srpaulo } 883251538Srpaulo m_freem(m); 884251538Srpaulo data->m = NULL; 885251538Srpaulo } 886251538Srpaulo if (data->ni) { 887251538Srpaulo ieee80211_free_node(data->ni); 888251538Srpaulo data->ni = NULL; 889251538Srpaulo } 890251538Srpaulo sc->sc_txtimer = 0; 891251538Srpaulo ifp->if_opackets++; 892251538Srpaulo ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 893251538Srpaulo} 894251538Srpaulo 895251538Srpaulostatic void 896251538Srpaulourtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 897251538Srpaulo{ 898251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 899251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 900251538Srpaulo struct urtwn_data *data; 901251538Srpaulo 902251538Srpaulo URTWN_ASSERT_LOCKED(sc); 903251538Srpaulo 904251538Srpaulo switch (USB_GET_STATE(xfer)){ 905251538Srpaulo case USB_ST_TRANSFERRED: 906251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 907251538Srpaulo if (data == NULL) 908251538Srpaulo goto tr_setup; 909251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 910251538Srpaulo urtwn_txeof(xfer, data); 911251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 912251538Srpaulo /* FALLTHROUGH */ 913251538Srpaulo case USB_ST_SETUP: 914251538Srpaulotr_setup: 915251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_pending); 916251538Srpaulo if (data == NULL) { 917251538Srpaulo DPRINTF("%s: empty pending queue\n", __func__); 918251538Srpaulo return; 919251538Srpaulo } 920251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 921251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 922251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 923251538Srpaulo usbd_transfer_submit(xfer); 924261863Srpaulo urtwn_start_locked(ifp, sc); 925251538Srpaulo break; 926251538Srpaulo default: 927251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 928251538Srpaulo if (data == NULL) 929251538Srpaulo goto tr_setup; 930251538Srpaulo if (data->ni != NULL) { 931251538Srpaulo ieee80211_free_node(data->ni); 932251538Srpaulo data->ni = NULL; 933251538Srpaulo ifp->if_oerrors++; 934251538Srpaulo } 935251538Srpaulo if (error != USB_ERR_CANCELLED) { 936251538Srpaulo usbd_xfer_set_stall(xfer); 937251538Srpaulo goto tr_setup; 938251538Srpaulo } 939251538Srpaulo break; 940251538Srpaulo } 941251538Srpaulo} 942251538Srpaulo 943251538Srpaulostatic struct urtwn_data * 944251538Srpaulo_urtwn_getbuf(struct urtwn_softc *sc) 945251538Srpaulo{ 946251538Srpaulo struct urtwn_data *bf; 947251538Srpaulo 948251538Srpaulo bf = STAILQ_FIRST(&sc->sc_tx_inactive); 949251538Srpaulo if (bf != NULL) 950251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 951251538Srpaulo else 952251538Srpaulo bf = NULL; 953251538Srpaulo if (bf == NULL) 954251538Srpaulo DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 955251538Srpaulo return (bf); 956251538Srpaulo} 957251538Srpaulo 958251538Srpaulostatic struct urtwn_data * 959251538Srpaulourtwn_getbuf(struct urtwn_softc *sc) 960251538Srpaulo{ 961251538Srpaulo struct urtwn_data *bf; 962251538Srpaulo 963251538Srpaulo URTWN_ASSERT_LOCKED(sc); 964251538Srpaulo 965251538Srpaulo bf = _urtwn_getbuf(sc); 966251538Srpaulo if (bf == NULL) { 967251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 968251538Srpaulo DPRINTF("%s: stop queue\n", __func__); 969251538Srpaulo ifp->if_drv_flags |= IFF_DRV_OACTIVE; 970251538Srpaulo } 971251538Srpaulo return (bf); 972251538Srpaulo} 973251538Srpaulo 974251538Srpaulostatic int 975251538Srpaulourtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 976251538Srpaulo int len) 977251538Srpaulo{ 978251538Srpaulo usb_device_request_t req; 979251538Srpaulo 980251538Srpaulo req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 981251538Srpaulo req.bRequest = R92C_REQ_REGS; 982251538Srpaulo USETW(req.wValue, addr); 983251538Srpaulo USETW(req.wIndex, 0); 984251538Srpaulo USETW(req.wLength, len); 985251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 986251538Srpaulo} 987251538Srpaulo 988251538Srpaulostatic void 989251538Srpaulourtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 990251538Srpaulo{ 991251538Srpaulo urtwn_write_region_1(sc, addr, &val, 1); 992251538Srpaulo} 993251538Srpaulo 994251538Srpaulo 995251538Srpaulostatic void 996251538Srpaulourtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 997251538Srpaulo{ 998251538Srpaulo val = htole16(val); 999251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1000251538Srpaulo} 1001251538Srpaulo 1002251538Srpaulostatic void 1003251538Srpaulourtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1004251538Srpaulo{ 1005251538Srpaulo val = htole32(val); 1006251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1007251538Srpaulo} 1008251538Srpaulo 1009251538Srpaulostatic int 1010251538Srpaulourtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1011251538Srpaulo int len) 1012251538Srpaulo{ 1013251538Srpaulo usb_device_request_t req; 1014251538Srpaulo 1015251538Srpaulo req.bmRequestType = UT_READ_VENDOR_DEVICE; 1016251538Srpaulo req.bRequest = R92C_REQ_REGS; 1017251538Srpaulo USETW(req.wValue, addr); 1018251538Srpaulo USETW(req.wIndex, 0); 1019251538Srpaulo USETW(req.wLength, len); 1020251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 1021251538Srpaulo} 1022251538Srpaulo 1023251538Srpaulostatic uint8_t 1024251538Srpaulourtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1025251538Srpaulo{ 1026251538Srpaulo uint8_t val; 1027251538Srpaulo 1028251538Srpaulo if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1029251538Srpaulo return (0xff); 1030251538Srpaulo return (val); 1031251538Srpaulo} 1032251538Srpaulo 1033251538Srpaulostatic uint16_t 1034251538Srpaulourtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1035251538Srpaulo{ 1036251538Srpaulo uint16_t val; 1037251538Srpaulo 1038251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1039251538Srpaulo return (0xffff); 1040251538Srpaulo return (le16toh(val)); 1041251538Srpaulo} 1042251538Srpaulo 1043251538Srpaulostatic uint32_t 1044251538Srpaulourtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1045251538Srpaulo{ 1046251538Srpaulo uint32_t val; 1047251538Srpaulo 1048251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1049251538Srpaulo return (0xffffffff); 1050251538Srpaulo return (le32toh(val)); 1051251538Srpaulo} 1052251538Srpaulo 1053251538Srpaulostatic int 1054251538Srpaulourtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1055251538Srpaulo{ 1056251538Srpaulo struct r92c_fw_cmd cmd; 1057251538Srpaulo int ntries; 1058251538Srpaulo 1059251538Srpaulo /* Wait for current FW box to be empty. */ 1060251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1061251538Srpaulo if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1062251538Srpaulo break; 1063251538Srpaulo DELAY(1); 1064251538Srpaulo } 1065251538Srpaulo if (ntries == 100) { 1066251538Srpaulo device_printf(sc->sc_dev, 1067251538Srpaulo "could not send firmware command\n"); 1068251538Srpaulo return (ETIMEDOUT); 1069251538Srpaulo } 1070251538Srpaulo memset(&cmd, 0, sizeof(cmd)); 1071251538Srpaulo cmd.id = id; 1072251538Srpaulo if (len > 3) 1073251538Srpaulo cmd.id |= R92C_CMD_FLAG_EXT; 1074251538Srpaulo KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1075251538Srpaulo memcpy(cmd.msg, buf, len); 1076251538Srpaulo 1077251538Srpaulo /* Write the first word last since that will trigger the FW. */ 1078251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1079251538Srpaulo (uint8_t *)&cmd + 4, 2); 1080251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1081251538Srpaulo (uint8_t *)&cmd + 0, 4); 1082251538Srpaulo 1083251538Srpaulo sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1084251538Srpaulo return (0); 1085251538Srpaulo} 1086251538Srpaulo 1087264912Skevlostatic __inline void 1088251538Srpaulourtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1089251538Srpaulo{ 1090264912Skevlo 1091264912Skevlo sc->sc_rf_write(sc, chain, addr, val); 1092264912Skevlo} 1093264912Skevlo 1094264912Skevlostatic void 1095264912Skevlourtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1096264912Skevlo uint32_t val) 1097264912Skevlo{ 1098251538Srpaulo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1099251538Srpaulo SM(R92C_LSSI_PARAM_ADDR, addr) | 1100251538Srpaulo SM(R92C_LSSI_PARAM_DATA, val)); 1101251538Srpaulo} 1102251538Srpaulo 1103264912Skevlostatic void 1104264912Skevlourtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1105264912Skevlouint32_t val) 1106264912Skevlo{ 1107264912Skevlo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1108264912Skevlo SM(R88E_LSSI_PARAM_ADDR, addr) | 1109264912Skevlo SM(R92C_LSSI_PARAM_DATA, val)); 1110264912Skevlo} 1111264912Skevlo 1112251538Srpaulostatic uint32_t 1113251538Srpaulourtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1114251538Srpaulo{ 1115251538Srpaulo uint32_t reg[R92C_MAX_CHAINS], val; 1116251538Srpaulo 1117251538Srpaulo reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1118251538Srpaulo if (chain != 0) 1119251538Srpaulo reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1120251538Srpaulo 1121251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1122251538Srpaulo reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1123251538Srpaulo DELAY(1000); 1124251538Srpaulo 1125251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1126251538Srpaulo RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1127251538Srpaulo R92C_HSSI_PARAM2_READ_EDGE); 1128251538Srpaulo DELAY(1000); 1129251538Srpaulo 1130251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1131251538Srpaulo reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1132251538Srpaulo DELAY(1000); 1133251538Srpaulo 1134251538Srpaulo if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1135251538Srpaulo val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1136251538Srpaulo else 1137251538Srpaulo val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1138251538Srpaulo return (MS(val, R92C_LSSI_READBACK_DATA)); 1139251538Srpaulo} 1140251538Srpaulo 1141251538Srpaulostatic int 1142251538Srpaulourtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1143251538Srpaulo{ 1144251538Srpaulo int ntries; 1145251538Srpaulo 1146251538Srpaulo urtwn_write_4(sc, R92C_LLT_INIT, 1147251538Srpaulo SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1148251538Srpaulo SM(R92C_LLT_INIT_ADDR, addr) | 1149251538Srpaulo SM(R92C_LLT_INIT_DATA, data)); 1150251538Srpaulo /* Wait for write operation to complete. */ 1151251538Srpaulo for (ntries = 0; ntries < 20; ntries++) { 1152251538Srpaulo if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1153251538Srpaulo R92C_LLT_INIT_OP_NO_ACTIVE) 1154251538Srpaulo return (0); 1155251538Srpaulo DELAY(5); 1156251538Srpaulo } 1157251538Srpaulo return (ETIMEDOUT); 1158251538Srpaulo} 1159251538Srpaulo 1160251538Srpaulostatic uint8_t 1161251538Srpaulourtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1162251538Srpaulo{ 1163251538Srpaulo uint32_t reg; 1164251538Srpaulo int ntries; 1165251538Srpaulo 1166251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1167251538Srpaulo reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1168251538Srpaulo reg &= ~R92C_EFUSE_CTRL_VALID; 1169251538Srpaulo urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1170251538Srpaulo /* Wait for read operation to complete. */ 1171251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1172251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1173251538Srpaulo if (reg & R92C_EFUSE_CTRL_VALID) 1174251538Srpaulo return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1175251538Srpaulo DELAY(5); 1176251538Srpaulo } 1177251538Srpaulo device_printf(sc->sc_dev, 1178251538Srpaulo "could not read efuse byte at address 0x%x\n", addr); 1179251538Srpaulo return (0xff); 1180251538Srpaulo} 1181251538Srpaulo 1182251538Srpaulostatic void 1183251538Srpaulourtwn_efuse_read(struct urtwn_softc *sc) 1184251538Srpaulo{ 1185251538Srpaulo uint8_t *rom = (uint8_t *)&sc->rom; 1186251538Srpaulo uint16_t addr = 0; 1187251538Srpaulo uint32_t reg; 1188251538Srpaulo uint8_t off, msk; 1189251538Srpaulo int i; 1190251538Srpaulo 1191264912Skevlo urtwn_efuse_switch_power(sc); 1192264912Skevlo 1193251538Srpaulo memset(&sc->rom, 0xff, sizeof(sc->rom)); 1194251538Srpaulo while (addr < 512) { 1195251538Srpaulo reg = urtwn_efuse_read_1(sc, addr); 1196251538Srpaulo if (reg == 0xff) 1197251538Srpaulo break; 1198251538Srpaulo addr++; 1199251538Srpaulo off = reg >> 4; 1200251538Srpaulo msk = reg & 0xf; 1201251538Srpaulo for (i = 0; i < 4; i++) { 1202251538Srpaulo if (msk & (1 << i)) 1203251538Srpaulo continue; 1204251538Srpaulo rom[off * 8 + i * 2 + 0] = 1205251538Srpaulo urtwn_efuse_read_1(sc, addr); 1206251538Srpaulo addr++; 1207251538Srpaulo rom[off * 8 + i * 2 + 1] = 1208251538Srpaulo urtwn_efuse_read_1(sc, addr); 1209251538Srpaulo addr++; 1210251538Srpaulo } 1211251538Srpaulo } 1212251538Srpaulo#ifdef URTWN_DEBUG 1213251538Srpaulo if (urtwn_debug >= 2) { 1214251538Srpaulo /* Dump ROM content. */ 1215251538Srpaulo printf("\n"); 1216251538Srpaulo for (i = 0; i < sizeof(sc->rom); i++) 1217251538Srpaulo printf("%02x:", rom[i]); 1218251538Srpaulo printf("\n"); 1219251538Srpaulo } 1220251538Srpaulo#endif 1221251538Srpaulo} 1222264912Skevlostatic void 1223264912Skevlourtwn_efuse_switch_power(struct urtwn_softc *sc) 1224264912Skevlo{ 1225264912Skevlo uint32_t reg; 1226251538Srpaulo 1227264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1228264912Skevlo if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1229264912Skevlo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1230264912Skevlo reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1231264912Skevlo } 1232264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1233264912Skevlo if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1234264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1235264912Skevlo reg | R92C_SYS_FUNC_EN_ELDR); 1236264912Skevlo } 1237264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1238264912Skevlo if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1239264912Skevlo (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1240264912Skevlo urtwn_write_2(sc, R92C_SYS_CLKR, 1241264912Skevlo reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1242264912Skevlo } 1243264912Skevlo} 1244264912Skevlo 1245251538Srpaulostatic int 1246251538Srpaulourtwn_read_chipid(struct urtwn_softc *sc) 1247251538Srpaulo{ 1248251538Srpaulo uint32_t reg; 1249251538Srpaulo 1250264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1251264912Skevlo return (0); 1252264912Skevlo 1253251538Srpaulo reg = urtwn_read_4(sc, R92C_SYS_CFG); 1254251538Srpaulo if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1255251538Srpaulo return (EIO); 1256251538Srpaulo 1257251538Srpaulo if (reg & R92C_SYS_CFG_TYPE_92C) { 1258251538Srpaulo sc->chip |= URTWN_CHIP_92C; 1259251538Srpaulo /* Check if it is a castrated 8192C. */ 1260251538Srpaulo if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1261251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID) == 1262251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1263251538Srpaulo sc->chip |= URTWN_CHIP_92C_1T2R; 1264251538Srpaulo } 1265251538Srpaulo if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1266251538Srpaulo sc->chip |= URTWN_CHIP_UMC; 1267251538Srpaulo if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1268251538Srpaulo sc->chip |= URTWN_CHIP_UMC_A_CUT; 1269251538Srpaulo } 1270251538Srpaulo return (0); 1271251538Srpaulo} 1272251538Srpaulo 1273251538Srpaulostatic void 1274251538Srpaulourtwn_read_rom(struct urtwn_softc *sc) 1275251538Srpaulo{ 1276251538Srpaulo struct r92c_rom *rom = &sc->rom; 1277251538Srpaulo 1278251538Srpaulo /* Read full ROM image. */ 1279251538Srpaulo urtwn_efuse_read(sc); 1280251538Srpaulo 1281251538Srpaulo /* XXX Weird but this is what the vendor driver does. */ 1282251538Srpaulo sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1283251538Srpaulo DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1284251538Srpaulo 1285251538Srpaulo sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1286251538Srpaulo 1287251538Srpaulo sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1288251538Srpaulo DPRINTF("regulatory type=%d\n", sc->regulatory); 1289264912Skevlo IEEE80211_ADDR_COPY(sc->sc_bssid, rom->macaddr); 1290251538Srpaulo 1291264912Skevlo sc->sc_rf_write = urtwn_r92c_rf_write; 1292264912Skevlo sc->sc_power_on = urtwn_r92c_power_on; 1293264912Skevlo sc->sc_dma_init = urtwn_r92c_dma_init; 1294251538Srpaulo} 1295251538Srpaulo 1296264912Skevlostatic void 1297264912Skevlourtwn_r88e_read_rom(struct urtwn_softc *sc) 1298264912Skevlo{ 1299264912Skevlo uint8_t *rom = sc->r88e_rom; 1300264912Skevlo uint16_t addr = 0; 1301264912Skevlo uint32_t reg; 1302264912Skevlo uint8_t off, msk, tmp; 1303264912Skevlo int i; 1304264912Skevlo 1305264912Skevlo urtwn_efuse_switch_power(sc); 1306264912Skevlo 1307264912Skevlo /* Read full ROM image. */ 1308264912Skevlo memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1309264912Skevlo while (addr < 1024) { 1310264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1311264912Skevlo if (reg == 0xff) 1312264912Skevlo break; 1313264912Skevlo addr++; 1314264912Skevlo if ((reg & 0x1f) == 0x0f) { 1315264912Skevlo tmp = (reg & 0xe0) >> 5; 1316264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1317264912Skevlo if ((reg & 0x0f) != 0x0f) 1318264912Skevlo off = ((reg & 0xf0) >> 1) | tmp; 1319264912Skevlo addr++; 1320264912Skevlo } else 1321264912Skevlo off = reg >> 4; 1322264912Skevlo msk = reg & 0xf; 1323264912Skevlo for (i = 0; i < 4; i++) { 1324264912Skevlo if (msk & (1 << i)) 1325264912Skevlo continue; 1326264912Skevlo rom[off * 8 + i * 2 + 0] = 1327264912Skevlo urtwn_efuse_read_1(sc, addr); 1328264912Skevlo addr++; 1329264912Skevlo rom[off * 8 + i * 2 + 1] = 1330264912Skevlo urtwn_efuse_read_1(sc, addr); 1331264912Skevlo addr++; 1332264912Skevlo } 1333264912Skevlo } 1334264912Skevlo 1335264912Skevlo addr = 0x10; 1336264912Skevlo for (i = 0; i < 6; i++) 1337264912Skevlo sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1338264912Skevlo for (i = 0; i < 5; i++) 1339264912Skevlo sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1340264912Skevlo sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1341264912Skevlo if (sc->bw20_tx_pwr_diff & 0x08) 1342264912Skevlo sc->bw20_tx_pwr_diff |= 0xf0; 1343264912Skevlo sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1344264912Skevlo if (sc->ofdm_tx_pwr_diff & 0x08) 1345264912Skevlo sc->ofdm_tx_pwr_diff |= 0xf0; 1346264912Skevlo sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1347264912Skevlo IEEE80211_ADDR_COPY(sc->sc_bssid, &sc->r88e_rom[0xd7]); 1348264912Skevlo 1349264912Skevlo sc->sc_rf_write = urtwn_r88e_rf_write; 1350264912Skevlo sc->sc_power_on = urtwn_r88e_power_on; 1351264912Skevlo sc->sc_dma_init = urtwn_r88e_dma_init; 1352264912Skevlo} 1353264912Skevlo 1354251538Srpaulo/* 1355251538Srpaulo * Initialize rate adaptation in firmware. 1356251538Srpaulo */ 1357251538Srpaulostatic int 1358251538Srpaulourtwn_ra_init(struct urtwn_softc *sc) 1359251538Srpaulo{ 1360251538Srpaulo static const uint8_t map[] = 1361251538Srpaulo { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1362251538Srpaulo struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1363251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1364251538Srpaulo struct ieee80211_node *ni; 1365251538Srpaulo struct ieee80211_rateset *rs; 1366251538Srpaulo struct r92c_fw_cmd_macid_cfg cmd; 1367251538Srpaulo uint32_t rates, basicrates; 1368251538Srpaulo uint8_t mode; 1369251538Srpaulo int maxrate, maxbasicrate, error, i, j; 1370251538Srpaulo 1371251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1372251538Srpaulo rs = &ni->ni_rates; 1373251538Srpaulo 1374251538Srpaulo /* Get normal and basic rates mask. */ 1375251538Srpaulo rates = basicrates = 0; 1376251538Srpaulo maxrate = maxbasicrate = 0; 1377251538Srpaulo for (i = 0; i < rs->rs_nrates; i++) { 1378251538Srpaulo /* Convert 802.11 rate to HW rate index. */ 1379251538Srpaulo for (j = 0; j < nitems(map); j++) 1380251538Srpaulo if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1381251538Srpaulo break; 1382251538Srpaulo if (j == nitems(map)) /* Unknown rate, skip. */ 1383251538Srpaulo continue; 1384251538Srpaulo rates |= 1 << j; 1385251538Srpaulo if (j > maxrate) 1386251538Srpaulo maxrate = j; 1387251538Srpaulo if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1388251538Srpaulo basicrates |= 1 << j; 1389251538Srpaulo if (j > maxbasicrate) 1390251538Srpaulo maxbasicrate = j; 1391251538Srpaulo } 1392251538Srpaulo } 1393251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1394251538Srpaulo mode = R92C_RAID_11B; 1395251538Srpaulo else 1396251538Srpaulo mode = R92C_RAID_11BG; 1397251538Srpaulo DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1398251538Srpaulo mode, rates, basicrates); 1399251538Srpaulo 1400251538Srpaulo /* Set rates mask for group addressed frames. */ 1401251538Srpaulo cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1402251538Srpaulo cmd.mask = htole32(mode << 28 | basicrates); 1403251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1404251538Srpaulo if (error != 0) { 1405252401Srpaulo ieee80211_free_node(ni); 1406251538Srpaulo device_printf(sc->sc_dev, 1407251538Srpaulo "could not add broadcast station\n"); 1408251538Srpaulo return (error); 1409251538Srpaulo } 1410251538Srpaulo /* Set initial MRR rate. */ 1411251538Srpaulo DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1412251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1413251538Srpaulo maxbasicrate); 1414251538Srpaulo 1415251538Srpaulo /* Set rates mask for unicast frames. */ 1416251538Srpaulo cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1417251538Srpaulo cmd.mask = htole32(mode << 28 | rates); 1418251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1419251538Srpaulo if (error != 0) { 1420252401Srpaulo ieee80211_free_node(ni); 1421251538Srpaulo device_printf(sc->sc_dev, "could not add BSS station\n"); 1422251538Srpaulo return (error); 1423251538Srpaulo } 1424251538Srpaulo /* Set initial MRR rate. */ 1425251538Srpaulo DPRINTF("maxrate=%d\n", maxrate); 1426251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1427251538Srpaulo maxrate); 1428251538Srpaulo 1429251538Srpaulo /* Indicate highest supported rate. */ 1430252403Srpaulo ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1431252401Srpaulo ieee80211_free_node(ni); 1432252401Srpaulo 1433251538Srpaulo return (0); 1434251538Srpaulo} 1435251538Srpaulo 1436251538Srpaulovoid 1437251538Srpaulourtwn_tsf_sync_enable(struct urtwn_softc *sc) 1438251538Srpaulo{ 1439251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 1440251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 1441251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1442251538Srpaulo struct ieee80211_node *ni = vap->iv_bss; 1443251538Srpaulo 1444251538Srpaulo uint64_t tsf; 1445251538Srpaulo 1446251538Srpaulo /* Enable TSF synchronization. */ 1447251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1448251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1449251538Srpaulo 1450251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1451251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1452251538Srpaulo 1453251538Srpaulo /* Set initial TSF. */ 1454251538Srpaulo memcpy(&tsf, ni->ni_tstamp.data, 8); 1455251538Srpaulo tsf = le64toh(tsf); 1456251538Srpaulo tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1457251538Srpaulo tsf -= IEEE80211_DUR_TU; 1458251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1459251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1460251538Srpaulo 1461251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1462251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1463251538Srpaulo} 1464251538Srpaulo 1465251538Srpaulostatic void 1466251538Srpaulourtwn_set_led(struct urtwn_softc *sc, int led, int on) 1467251538Srpaulo{ 1468251538Srpaulo uint8_t reg; 1469264912Skevlo 1470251538Srpaulo if (led == URTWN_LED_LINK) { 1471264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 1472264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1473264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1474264912Skevlo if (!on) { 1475264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1476264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, 1477264912Skevlo reg | R92C_LEDCFG0_DIS); 1478264912Skevlo urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1479264912Skevlo urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1480264912Skevlo 0xfe); 1481264912Skevlo } 1482264912Skevlo } else { 1483264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1484264912Skevlo if (!on) 1485264912Skevlo reg |= R92C_LEDCFG0_DIS; 1486264912Skevlo urtwn_write_1(sc, R92C_LEDCFG0, reg); 1487264912Skevlo } 1488264912Skevlo sc->ledlink = on; /* Save LED state. */ 1489251538Srpaulo } 1490251538Srpaulo} 1491251538Srpaulo 1492251538Srpaulostatic int 1493251538Srpaulourtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1494251538Srpaulo{ 1495251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 1496251538Srpaulo struct ieee80211com *ic = vap->iv_ic; 1497251538Srpaulo struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1498251538Srpaulo struct ieee80211_node *ni; 1499251538Srpaulo enum ieee80211_state ostate; 1500251538Srpaulo uint32_t reg; 1501251538Srpaulo 1502251538Srpaulo ostate = vap->iv_state; 1503251538Srpaulo DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1504251538Srpaulo ieee80211_state_name[nstate]); 1505251538Srpaulo 1506251538Srpaulo IEEE80211_UNLOCK(ic); 1507251538Srpaulo URTWN_LOCK(sc); 1508251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 1509251538Srpaulo 1510251538Srpaulo if (ostate == IEEE80211_S_RUN) { 1511251538Srpaulo /* Turn link LED off. */ 1512251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1513251538Srpaulo 1514251538Srpaulo /* Set media status to 'No Link'. */ 1515251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 1516251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1517251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 1518251538Srpaulo 1519251538Srpaulo /* Stop Rx of data frames. */ 1520251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1521251538Srpaulo 1522251538Srpaulo /* Rest TSF. */ 1523251538Srpaulo urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1524251538Srpaulo 1525251538Srpaulo /* Disable TSF synchronization. */ 1526251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1527251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | 1528251538Srpaulo R92C_BCN_CTRL_DIS_TSF_UDT0); 1529251538Srpaulo 1530251538Srpaulo /* Reset EDCA parameters. */ 1531251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1532251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1533251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1534251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1535251538Srpaulo } 1536251538Srpaulo 1537251538Srpaulo switch (nstate) { 1538251538Srpaulo case IEEE80211_S_INIT: 1539251538Srpaulo /* Turn link LED off. */ 1540251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1541251538Srpaulo break; 1542251538Srpaulo case IEEE80211_S_SCAN: 1543251538Srpaulo if (ostate != IEEE80211_S_SCAN) { 1544251538Srpaulo /* Allow Rx from any BSSID. */ 1545251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1546251538Srpaulo urtwn_read_4(sc, R92C_RCR) & 1547251538Srpaulo ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1548251538Srpaulo 1549251538Srpaulo /* Set gain for scanning. */ 1550251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1551251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1552251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1553251538Srpaulo 1554264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1555264912Skevlo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1556264912Skevlo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1557264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1558264912Skevlo } 1559251538Srpaulo } 1560251538Srpaulo /* Make link LED blink during scan. */ 1561251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1562251538Srpaulo 1563251538Srpaulo /* Pause AC Tx queues. */ 1564251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 1565251538Srpaulo urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1566251538Srpaulo 1567251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 1568251538Srpaulo break; 1569251538Srpaulo case IEEE80211_S_AUTH: 1570251538Srpaulo /* Set initial gain under link. */ 1571251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1572251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1573251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1574251538Srpaulo 1575264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1576264912Skevlo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1577264912Skevlo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1578264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1579264912Skevlo } 1580251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 1581251538Srpaulo break; 1582251538Srpaulo case IEEE80211_S_RUN: 1583251538Srpaulo if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1584251538Srpaulo /* Enable Rx of data frames. */ 1585251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1586251538Srpaulo 1587251538Srpaulo /* Turn link LED on. */ 1588251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1589251538Srpaulo break; 1590251538Srpaulo } 1591251538Srpaulo 1592251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1593251538Srpaulo /* Set media status to 'Associated'. */ 1594251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 1595251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1596251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 1597251538Srpaulo 1598251538Srpaulo /* Set BSSID. */ 1599251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1600251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1601251538Srpaulo 1602251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1603251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1604251538Srpaulo else /* 802.11b/g */ 1605251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1606251538Srpaulo 1607251538Srpaulo /* Enable Rx of data frames. */ 1608251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1609251538Srpaulo 1610251538Srpaulo /* Flush all AC queues. */ 1611251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0); 1612251538Srpaulo 1613251538Srpaulo /* Set beacon interval. */ 1614251538Srpaulo urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1615251538Srpaulo 1616251538Srpaulo /* Allow Rx from our BSSID only. */ 1617251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1618251538Srpaulo urtwn_read_4(sc, R92C_RCR) | 1619251538Srpaulo R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1620251538Srpaulo 1621251538Srpaulo /* Enable TSF synchronization. */ 1622251538Srpaulo urtwn_tsf_sync_enable(sc); 1623251538Srpaulo 1624251538Srpaulo urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1625251538Srpaulo urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1626251538Srpaulo urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1627251538Srpaulo urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1628251538Srpaulo urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1629251538Srpaulo urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1630251538Srpaulo 1631251538Srpaulo /* Intialize rate adaptation. */ 1632264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1633264912Skevlo ni->ni_txrate = 1634264912Skevlo ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1635264912Skevlo else 1636264912Skevlo urtwn_ra_init(sc); 1637251538Srpaulo /* Turn link LED on. */ 1638251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1639251538Srpaulo 1640251538Srpaulo sc->avg_pwdb = -1; /* Reset average RSSI. */ 1641251538Srpaulo /* Reset temperature calibration state machine. */ 1642251538Srpaulo sc->thcal_state = 0; 1643251538Srpaulo sc->thcal_lctemp = 0; 1644251538Srpaulo ieee80211_free_node(ni); 1645251538Srpaulo break; 1646251538Srpaulo default: 1647251538Srpaulo break; 1648251538Srpaulo } 1649251538Srpaulo URTWN_UNLOCK(sc); 1650251538Srpaulo IEEE80211_LOCK(ic); 1651251538Srpaulo return(uvp->newstate(vap, nstate, arg)); 1652251538Srpaulo} 1653251538Srpaulo 1654251538Srpaulostatic void 1655251538Srpaulourtwn_watchdog(void *arg) 1656251538Srpaulo{ 1657251538Srpaulo struct urtwn_softc *sc = arg; 1658251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 1659251538Srpaulo 1660251538Srpaulo if (sc->sc_txtimer > 0) { 1661251538Srpaulo if (--sc->sc_txtimer == 0) { 1662251538Srpaulo device_printf(sc->sc_dev, "device timeout\n"); 1663251538Srpaulo ifp->if_oerrors++; 1664251538Srpaulo return; 1665251538Srpaulo } 1666251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1667251538Srpaulo } 1668251538Srpaulo} 1669251538Srpaulo 1670251538Srpaulostatic void 1671251538Srpaulourtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1672251538Srpaulo{ 1673251538Srpaulo int pwdb; 1674251538Srpaulo 1675251538Srpaulo /* Convert antenna signal to percentage. */ 1676251538Srpaulo if (rssi <= -100 || rssi >= 20) 1677251538Srpaulo pwdb = 0; 1678251538Srpaulo else if (rssi >= 0) 1679251538Srpaulo pwdb = 100; 1680251538Srpaulo else 1681251538Srpaulo pwdb = 100 + rssi; 1682264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1683264912Skevlo if (rate <= 3) { 1684264912Skevlo /* CCK gain is smaller than OFDM/MCS gain. */ 1685264912Skevlo pwdb += 6; 1686264912Skevlo if (pwdb > 100) 1687264912Skevlo pwdb = 100; 1688264912Skevlo if (pwdb <= 14) 1689264912Skevlo pwdb -= 4; 1690264912Skevlo else if (pwdb <= 26) 1691264912Skevlo pwdb -= 8; 1692264912Skevlo else if (pwdb <= 34) 1693264912Skevlo pwdb -= 6; 1694264912Skevlo else if (pwdb <= 42) 1695264912Skevlo pwdb -= 2; 1696264912Skevlo } 1697251538Srpaulo } 1698251538Srpaulo if (sc->avg_pwdb == -1) /* Init. */ 1699251538Srpaulo sc->avg_pwdb = pwdb; 1700251538Srpaulo else if (sc->avg_pwdb < pwdb) 1701251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1702251538Srpaulo else 1703251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1704251538Srpaulo DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1705251538Srpaulo} 1706251538Srpaulo 1707251538Srpaulostatic int8_t 1708251538Srpaulourtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1709251538Srpaulo{ 1710251538Srpaulo static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1711251538Srpaulo struct r92c_rx_phystat *phy; 1712251538Srpaulo struct r92c_rx_cck *cck; 1713251538Srpaulo uint8_t rpt; 1714251538Srpaulo int8_t rssi; 1715251538Srpaulo 1716251538Srpaulo if (rate <= 3) { 1717251538Srpaulo cck = (struct r92c_rx_cck *)physt; 1718251538Srpaulo if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1719251538Srpaulo rpt = (cck->agc_rpt >> 5) & 0x3; 1720251538Srpaulo rssi = (cck->agc_rpt & 0x1f) << 1; 1721251538Srpaulo } else { 1722251538Srpaulo rpt = (cck->agc_rpt >> 6) & 0x3; 1723251538Srpaulo rssi = cck->agc_rpt & 0x3e; 1724251538Srpaulo } 1725251538Srpaulo rssi = cckoff[rpt] - rssi; 1726251538Srpaulo } else { /* OFDM/HT. */ 1727251538Srpaulo phy = (struct r92c_rx_phystat *)physt; 1728251538Srpaulo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1729251538Srpaulo } 1730251538Srpaulo return (rssi); 1731251538Srpaulo} 1732251538Srpaulo 1733264912Skevlostatic int8_t 1734264912Skevlourtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1735264912Skevlo{ 1736264912Skevlo struct r92c_rx_phystat *phy; 1737264912Skevlo struct r88e_rx_cck *cck; 1738264912Skevlo uint8_t cck_agc_rpt, lna_idx, vga_idx; 1739264912Skevlo int8_t rssi; 1740264912Skevlo 1741264972Skevlo rssi = 0; 1742264912Skevlo if (rate <= 3) { 1743264912Skevlo cck = (struct r88e_rx_cck *)physt; 1744264912Skevlo cck_agc_rpt = cck->agc_rpt; 1745264912Skevlo lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1746264912Skevlo vga_idx = cck_agc_rpt & 0x1f; 1747264912Skevlo switch (lna_idx) { 1748264912Skevlo case 7: 1749264912Skevlo if (vga_idx <= 27) 1750264912Skevlo rssi = -100 + 2* (27 - vga_idx); 1751264912Skevlo else 1752264912Skevlo rssi = -100; 1753264912Skevlo break; 1754264912Skevlo case 6: 1755264912Skevlo rssi = -48 + 2 * (2 - vga_idx); 1756264912Skevlo break; 1757264912Skevlo case 5: 1758264912Skevlo rssi = -42 + 2 * (7 - vga_idx); 1759264912Skevlo break; 1760264912Skevlo case 4: 1761264912Skevlo rssi = -36 + 2 * (7 - vga_idx); 1762264912Skevlo break; 1763264912Skevlo case 3: 1764264912Skevlo rssi = -24 + 2 * (7 - vga_idx); 1765264912Skevlo break; 1766264912Skevlo case 2: 1767264912Skevlo rssi = -12 + 2 * (5 - vga_idx); 1768264912Skevlo break; 1769264912Skevlo case 1: 1770264912Skevlo rssi = 8 - (2 * vga_idx); 1771264912Skevlo break; 1772264912Skevlo case 0: 1773264912Skevlo rssi = 14 - (2 * vga_idx); 1774264912Skevlo break; 1775264912Skevlo } 1776264912Skevlo rssi += 6; 1777264912Skevlo } else { /* OFDM/HT. */ 1778264912Skevlo phy = (struct r92c_rx_phystat *)physt; 1779264912Skevlo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1780264912Skevlo } 1781264912Skevlo return (rssi); 1782264912Skevlo} 1783264912Skevlo 1784264912Skevlo 1785251538Srpaulostatic int 1786251538Srpaulourtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1787251538Srpaulo struct mbuf *m0, struct urtwn_data *data) 1788251538Srpaulo{ 1789251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 1790251538Srpaulo struct ieee80211_frame *wh; 1791251538Srpaulo struct ieee80211_key *k; 1792251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 1793251538Srpaulo struct ieee80211vap *vap = ni->ni_vap; 1794251538Srpaulo struct usb_xfer *xfer; 1795251538Srpaulo struct r92c_tx_desc *txd; 1796251538Srpaulo uint8_t raid, type; 1797251538Srpaulo uint16_t sum; 1798251538Srpaulo int i, hasqos, xferlen; 1799251538Srpaulo struct usb_xfer *urtwn_pipes[4] = { 1800251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BE], 1801251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BK], 1802251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VI], 1803251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VO] 1804251538Srpaulo }; 1805251538Srpaulo 1806251538Srpaulo URTWN_ASSERT_LOCKED(sc); 1807251538Srpaulo 1808251538Srpaulo /* 1809251538Srpaulo * Software crypto. 1810251538Srpaulo */ 1811251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1812264912Skevlo type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1813264912Skevlo 1814260444Skevlo if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1815251538Srpaulo k = ieee80211_crypto_encap(ni, m0); 1816251538Srpaulo if (k == NULL) { 1817251538Srpaulo device_printf(sc->sc_dev, 1818251538Srpaulo "ieee80211_crypto_encap returns NULL.\n"); 1819251538Srpaulo /* XXX we don't expect the fragmented frames */ 1820251538Srpaulo m_freem(m0); 1821251538Srpaulo return (ENOBUFS); 1822251538Srpaulo } 1823251538Srpaulo 1824251538Srpaulo /* in case packet header moved, reset pointer */ 1825251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1826251538Srpaulo } 1827251538Srpaulo 1828264912Skevlo switch (type) { 1829251538Srpaulo case IEEE80211_FC0_TYPE_CTL: 1830251538Srpaulo case IEEE80211_FC0_TYPE_MGT: 1831251538Srpaulo xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1832251538Srpaulo break; 1833251538Srpaulo default: 1834251538Srpaulo KASSERT(M_WME_GETAC(m0) < 4, 1835251538Srpaulo ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1836251538Srpaulo xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1837251538Srpaulo break; 1838251538Srpaulo } 1839251538Srpaulo 1840251538Srpaulo hasqos = 0; 1841251538Srpaulo 1842251538Srpaulo /* Fill Tx descriptor. */ 1843251538Srpaulo txd = (struct r92c_tx_desc *)data->buf; 1844251538Srpaulo memset(txd, 0, sizeof(*txd)); 1845251538Srpaulo 1846251538Srpaulo txd->txdw0 |= htole32( 1847251538Srpaulo SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1848251538Srpaulo SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1849251538Srpaulo R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1850251538Srpaulo if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1851251538Srpaulo txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1852251538Srpaulo if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1853251538Srpaulo type == IEEE80211_FC0_TYPE_DATA) { 1854251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1855251538Srpaulo raid = R92C_RAID_11B; 1856251538Srpaulo else 1857251538Srpaulo raid = R92C_RAID_11BG; 1858264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 1859264912Skevlo txd->txdw1 |= htole32( 1860264912Skevlo SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1861264912Skevlo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1862264912Skevlo SM(R92C_TXDW1_RAID, raid)); 1863264912Skevlo txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1864264912Skevlo } else { 1865264912Skevlo txd->txdw1 |= htole32( 1866264912Skevlo SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1867264912Skevlo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1868264912Skevlo SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1869264912Skevlo } 1870251538Srpaulo if (ic->ic_flags & IEEE80211_F_USEPROT) { 1871251538Srpaulo if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1872251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1873251538Srpaulo R92C_TXDW4_HWRTSEN); 1874251538Srpaulo } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1875251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1876251538Srpaulo R92C_TXDW4_HWRTSEN); 1877251538Srpaulo } 1878251538Srpaulo } 1879251538Srpaulo /* Send RTS at OFDM24. */ 1880251538Srpaulo txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1881251538Srpaulo txd->txdw5 |= htole32(0x0001ff00); 1882251538Srpaulo /* Send data at OFDM54. */ 1883264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1884264912Skevlo txd->txdw5 |= htole32(0x13 & 0x3f); 1885264912Skevlo else 1886264912Skevlo txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1887251538Srpaulo } else { 1888251538Srpaulo txd->txdw1 |= htole32( 1889251538Srpaulo SM(R92C_TXDW1_MACID, 0) | 1890251538Srpaulo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1891251538Srpaulo SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1892251538Srpaulo 1893251538Srpaulo /* Force CCK1. */ 1894251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1895251538Srpaulo txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1896251538Srpaulo } 1897251538Srpaulo /* Set sequence number (already little endian). */ 1898251538Srpaulo txd->txdseq |= *(uint16_t *)wh->i_seq; 1899251538Srpaulo 1900251538Srpaulo if (!hasqos) { 1901251538Srpaulo /* Use HW sequence numbering for non-QoS frames. */ 1902251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1903251538Srpaulo txd->txdseq |= htole16(0x8000); 1904251538Srpaulo } else 1905251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1906251538Srpaulo 1907251538Srpaulo /* Compute Tx descriptor checksum. */ 1908251538Srpaulo sum = 0; 1909251538Srpaulo for (i = 0; i < sizeof(*txd) / 2; i++) 1910251538Srpaulo sum ^= ((uint16_t *)txd)[i]; 1911251538Srpaulo txd->txdsum = sum; /* NB: already little endian. */ 1912251538Srpaulo 1913251538Srpaulo if (ieee80211_radiotap_active_vap(vap)) { 1914251538Srpaulo struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1915251538Srpaulo 1916251538Srpaulo tap->wt_flags = 0; 1917251538Srpaulo tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1918251538Srpaulo tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1919251538Srpaulo ieee80211_radiotap_tx(vap, m0); 1920251538Srpaulo } 1921251538Srpaulo 1922251538Srpaulo xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1923251538Srpaulo m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1924251538Srpaulo 1925251538Srpaulo data->buflen = xferlen; 1926251538Srpaulo data->ni = ni; 1927251538Srpaulo data->m = m0; 1928251538Srpaulo 1929251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1930251538Srpaulo usbd_transfer_start(xfer); 1931251538Srpaulo return (0); 1932251538Srpaulo} 1933251538Srpaulo 1934251538Srpaulostatic void 1935251538Srpaulourtwn_start(struct ifnet *ifp) 1936251538Srpaulo{ 1937251538Srpaulo struct urtwn_softc *sc = ifp->if_softc; 1938261863Srpaulo 1939261863Srpaulo if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1940261863Srpaulo return; 1941261863Srpaulo URTWN_LOCK(sc); 1942261863Srpaulo urtwn_start_locked(ifp, sc); 1943261863Srpaulo URTWN_UNLOCK(sc); 1944261863Srpaulo} 1945261863Srpaulo 1946261863Srpaulostatic void 1947261863Srpaulourtwn_start_locked(struct ifnet *ifp, struct urtwn_softc *sc) 1948261863Srpaulo{ 1949251538Srpaulo struct ieee80211_node *ni; 1950251538Srpaulo struct mbuf *m; 1951251538Srpaulo struct urtwn_data *bf; 1952251538Srpaulo 1953261863Srpaulo URTWN_ASSERT_LOCKED(sc); 1954251538Srpaulo for (;;) { 1955251538Srpaulo IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1956251538Srpaulo if (m == NULL) 1957251538Srpaulo break; 1958251538Srpaulo bf = urtwn_getbuf(sc); 1959251538Srpaulo if (bf == NULL) { 1960251538Srpaulo IFQ_DRV_PREPEND(&ifp->if_snd, m); 1961251538Srpaulo break; 1962251538Srpaulo } 1963251538Srpaulo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1964251538Srpaulo m->m_pkthdr.rcvif = NULL; 1965251538Srpaulo 1966251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 1967251538Srpaulo ifp->if_oerrors++; 1968251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1969251538Srpaulo ieee80211_free_node(ni); 1970251538Srpaulo break; 1971251538Srpaulo } 1972251538Srpaulo 1973251538Srpaulo sc->sc_txtimer = 5; 1974251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1975251538Srpaulo } 1976251538Srpaulo} 1977251538Srpaulo 1978251538Srpaulostatic int 1979251538Srpaulourtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1980251538Srpaulo{ 1981263153Skevlo struct urtwn_softc *sc = ifp->if_softc; 1982251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 1983251538Srpaulo struct ifreq *ifr = (struct ifreq *) data; 1984251538Srpaulo int error = 0, startall = 0; 1985251538Srpaulo 1986263153Skevlo URTWN_LOCK(sc); 1987263153Skevlo error = (sc->sc_flags & URTWN_DETACHED) ? ENXIO : 0; 1988263153Skevlo URTWN_UNLOCK(sc); 1989263153Skevlo if (error != 0) 1990263153Skevlo return (error); 1991263153Skevlo 1992251538Srpaulo switch (cmd) { 1993251538Srpaulo case SIOCSIFFLAGS: 1994251538Srpaulo if (ifp->if_flags & IFF_UP) { 1995251538Srpaulo if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1996251538Srpaulo urtwn_init(ifp->if_softc); 1997251538Srpaulo startall = 1; 1998251538Srpaulo } 1999251538Srpaulo } else { 2000251538Srpaulo if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2001263153Skevlo urtwn_stop(ifp); 2002251538Srpaulo } 2003251538Srpaulo if (startall) 2004251538Srpaulo ieee80211_start_all(ic); 2005251538Srpaulo break; 2006251538Srpaulo case SIOCGIFMEDIA: 2007251538Srpaulo error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 2008251538Srpaulo break; 2009251538Srpaulo case SIOCGIFADDR: 2010251538Srpaulo error = ether_ioctl(ifp, cmd, data); 2011251538Srpaulo break; 2012251538Srpaulo default: 2013251538Srpaulo error = EINVAL; 2014251538Srpaulo break; 2015251538Srpaulo } 2016251538Srpaulo return (error); 2017251538Srpaulo} 2018251538Srpaulo 2019251538Srpaulostatic int 2020251538Srpaulourtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 2021251538Srpaulo int ndata, int maxsz) 2022251538Srpaulo{ 2023251538Srpaulo int i, error; 2024251538Srpaulo 2025251538Srpaulo for (i = 0; i < ndata; i++) { 2026251538Srpaulo struct urtwn_data *dp = &data[i]; 2027251538Srpaulo dp->sc = sc; 2028251538Srpaulo dp->m = NULL; 2029251538Srpaulo dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 2030251538Srpaulo if (dp->buf == NULL) { 2031251538Srpaulo device_printf(sc->sc_dev, 2032251538Srpaulo "could not allocate buffer\n"); 2033251538Srpaulo error = ENOMEM; 2034251538Srpaulo goto fail; 2035251538Srpaulo } 2036251538Srpaulo dp->ni = NULL; 2037251538Srpaulo } 2038251538Srpaulo 2039251538Srpaulo return (0); 2040251538Srpaulofail: 2041251538Srpaulo urtwn_free_list(sc, data, ndata); 2042251538Srpaulo return (error); 2043251538Srpaulo} 2044251538Srpaulo 2045251538Srpaulostatic int 2046251538Srpaulourtwn_alloc_rx_list(struct urtwn_softc *sc) 2047251538Srpaulo{ 2048251538Srpaulo int error, i; 2049251538Srpaulo 2050251538Srpaulo error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 2051251538Srpaulo URTWN_RXBUFSZ); 2052251538Srpaulo if (error != 0) 2053251538Srpaulo return (error); 2054251538Srpaulo 2055251538Srpaulo STAILQ_INIT(&sc->sc_rx_active); 2056251538Srpaulo STAILQ_INIT(&sc->sc_rx_inactive); 2057251538Srpaulo 2058251538Srpaulo for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 2059251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 2060251538Srpaulo 2061251538Srpaulo return (0); 2062251538Srpaulo} 2063251538Srpaulo 2064251538Srpaulostatic int 2065251538Srpaulourtwn_alloc_tx_list(struct urtwn_softc *sc) 2066251538Srpaulo{ 2067251538Srpaulo int error, i; 2068251538Srpaulo 2069251538Srpaulo error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 2070251538Srpaulo URTWN_TXBUFSZ); 2071251538Srpaulo if (error != 0) 2072251538Srpaulo return (error); 2073251538Srpaulo 2074251538Srpaulo STAILQ_INIT(&sc->sc_tx_active); 2075251538Srpaulo STAILQ_INIT(&sc->sc_tx_inactive); 2076251538Srpaulo STAILQ_INIT(&sc->sc_tx_pending); 2077251538Srpaulo 2078251538Srpaulo for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 2079251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 2080251538Srpaulo 2081251538Srpaulo return (0); 2082251538Srpaulo} 2083251538Srpaulo 2084264912Skevlostatic __inline int 2085251538Srpaulourtwn_power_on(struct urtwn_softc *sc) 2086251538Srpaulo{ 2087264912Skevlo 2088264912Skevlo return sc->sc_power_on(sc); 2089264912Skevlo} 2090264912Skevlo 2091264912Skevlostatic int 2092264912Skevlourtwn_r92c_power_on(struct urtwn_softc *sc) 2093264912Skevlo{ 2094251538Srpaulo uint32_t reg; 2095251538Srpaulo int ntries; 2096251538Srpaulo 2097251538Srpaulo /* Wait for autoload done bit. */ 2098251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2099251538Srpaulo if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2100251538Srpaulo break; 2101251538Srpaulo DELAY(5); 2102251538Srpaulo } 2103251538Srpaulo if (ntries == 1000) { 2104251538Srpaulo device_printf(sc->sc_dev, 2105251538Srpaulo "timeout waiting for chip autoload\n"); 2106251538Srpaulo return (ETIMEDOUT); 2107251538Srpaulo } 2108251538Srpaulo 2109251538Srpaulo /* Unlock ISO/CLK/Power control register. */ 2110251538Srpaulo urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2111251538Srpaulo /* Move SPS into PWM mode. */ 2112251538Srpaulo urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2113251538Srpaulo DELAY(100); 2114251538Srpaulo 2115251538Srpaulo reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2116251538Srpaulo if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2117251538Srpaulo urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2118251538Srpaulo reg | R92C_LDOV12D_CTRL_LDV12_EN); 2119251538Srpaulo DELAY(100); 2120251538Srpaulo urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2121251538Srpaulo urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2122251538Srpaulo ~R92C_SYS_ISO_CTRL_MD2PP); 2123251538Srpaulo } 2124251538Srpaulo 2125251538Srpaulo /* Auto enable WLAN. */ 2126251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2127251538Srpaulo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2128251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2129262822Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2130262822Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2131251538Srpaulo break; 2132251538Srpaulo DELAY(5); 2133251538Srpaulo } 2134251538Srpaulo if (ntries == 1000) { 2135251538Srpaulo device_printf(sc->sc_dev, 2136251538Srpaulo "timeout waiting for MAC auto ON\n"); 2137251538Srpaulo return (ETIMEDOUT); 2138251538Srpaulo } 2139251538Srpaulo 2140251538Srpaulo /* Enable radio, GPIO and LED functions. */ 2141251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2142251538Srpaulo R92C_APS_FSMCO_AFSM_HSUS | 2143251538Srpaulo R92C_APS_FSMCO_PDN_EN | 2144251538Srpaulo R92C_APS_FSMCO_PFM_ALDN); 2145251538Srpaulo /* Release RF digital isolation. */ 2146251538Srpaulo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2147251538Srpaulo urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2148251538Srpaulo 2149251538Srpaulo /* Initialize MAC. */ 2150251538Srpaulo urtwn_write_1(sc, R92C_APSD_CTRL, 2151251538Srpaulo urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2152251538Srpaulo for (ntries = 0; ntries < 200; ntries++) { 2153251538Srpaulo if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2154251538Srpaulo R92C_APSD_CTRL_OFF_STATUS)) 2155251538Srpaulo break; 2156251538Srpaulo DELAY(5); 2157251538Srpaulo } 2158251538Srpaulo if (ntries == 200) { 2159251538Srpaulo device_printf(sc->sc_dev, 2160251538Srpaulo "timeout waiting for MAC initialization\n"); 2161251538Srpaulo return (ETIMEDOUT); 2162251538Srpaulo } 2163251538Srpaulo 2164251538Srpaulo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2165251538Srpaulo reg = urtwn_read_2(sc, R92C_CR); 2166251538Srpaulo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2167251538Srpaulo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2168251538Srpaulo R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2169251538Srpaulo R92C_CR_ENSEC; 2170251538Srpaulo urtwn_write_2(sc, R92C_CR, reg); 2171251538Srpaulo 2172251538Srpaulo urtwn_write_1(sc, 0xfe10, 0x19); 2173251538Srpaulo return (0); 2174251538Srpaulo} 2175251538Srpaulo 2176251538Srpaulostatic int 2177264912Skevlourtwn_r88e_power_on(struct urtwn_softc *sc) 2178264912Skevlo{ 2179264912Skevlo uint8_t val; 2180264912Skevlo uint32_t reg; 2181264912Skevlo int ntries; 2182264912Skevlo 2183264912Skevlo /* Wait for power ready bit. */ 2184264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2185264912Skevlo val = urtwn_read_1(sc, 0x6) & 0x2; 2186264912Skevlo if (val == 0x2) 2187264912Skevlo break; 2188264912Skevlo DELAY(10); 2189264912Skevlo } 2190264912Skevlo if (ntries == 5000) { 2191264912Skevlo device_printf(sc->sc_dev, 2192264912Skevlo "timeout waiting for chip power up\n"); 2193264912Skevlo return (ETIMEDOUT); 2194264912Skevlo } 2195264912Skevlo 2196264912Skevlo /* Reset BB. */ 2197264912Skevlo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2198264912Skevlo urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2199264912Skevlo R92C_SYS_FUNC_EN_BB_GLB_RST)); 2200264912Skevlo 2201264912Skevlo urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 2202264912Skevlo 2203264912Skevlo /* Disable HWPDN. */ 2204264912Skevlo urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 2205264912Skevlo 2206264912Skevlo /* Disable WL suspend. */ 2207264912Skevlo urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 2208264912Skevlo 2209264912Skevlo urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 2210264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2211264912Skevlo if (!(urtwn_read_1(sc, 0x5) & 0x1)) 2212264912Skevlo break; 2213264912Skevlo DELAY(10); 2214264912Skevlo } 2215264912Skevlo if (ntries == 5000) 2216264912Skevlo return (ETIMEDOUT); 2217264912Skevlo 2218264912Skevlo /* Enable LDO normal mode. */ 2219264912Skevlo urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 2220264912Skevlo 2221264912Skevlo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2222264912Skevlo urtwn_write_2(sc, R92C_CR, 0); 2223264912Skevlo reg = urtwn_read_2(sc, R92C_CR); 2224264912Skevlo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2225264912Skevlo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2226264912Skevlo R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2227264912Skevlo urtwn_write_2(sc, R92C_CR, reg); 2228264912Skevlo 2229264912Skevlo return (0); 2230264912Skevlo} 2231264912Skevlo 2232264912Skevlostatic int 2233251538Srpaulourtwn_llt_init(struct urtwn_softc *sc) 2234251538Srpaulo{ 2235264912Skevlo int i, error, page_count, pktbuf_count; 2236251538Srpaulo 2237264912Skevlo page_count = (sc->chip & URTWN_CHIP_88E) ? 2238264912Skevlo R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2239264912Skevlo pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2240264912Skevlo R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2241264912Skevlo 2242264912Skevlo /* Reserve pages [0; page_count]. */ 2243264912Skevlo for (i = 0; i < page_count; i++) { 2244251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2245251538Srpaulo return (error); 2246251538Srpaulo } 2247251538Srpaulo /* NB: 0xff indicates end-of-list. */ 2248251538Srpaulo if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2249251538Srpaulo return (error); 2250251538Srpaulo /* 2251264912Skevlo * Use pages [page_count + 1; pktbuf_count - 1] 2252251538Srpaulo * as ring buffer. 2253251538Srpaulo */ 2254264912Skevlo for (++i; i < pktbuf_count - 1; i++) { 2255251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2256251538Srpaulo return (error); 2257251538Srpaulo } 2258251538Srpaulo /* Make the last page point to the beginning of the ring buffer. */ 2259264912Skevlo error = urtwn_llt_write(sc, i, page_count + 1); 2260251538Srpaulo return (error); 2261251538Srpaulo} 2262251538Srpaulo 2263251538Srpaulostatic void 2264251538Srpaulourtwn_fw_reset(struct urtwn_softc *sc) 2265251538Srpaulo{ 2266251538Srpaulo uint16_t reg; 2267251538Srpaulo int ntries; 2268251538Srpaulo 2269251538Srpaulo /* Tell 8051 to reset itself. */ 2270251538Srpaulo urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2271251538Srpaulo 2272251538Srpaulo /* Wait until 8051 resets by itself. */ 2273251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 2274251538Srpaulo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2275251538Srpaulo if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2276251538Srpaulo return; 2277251538Srpaulo DELAY(50); 2278251538Srpaulo } 2279251538Srpaulo /* Force 8051 reset. */ 2280251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2281264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2282264912Skevlo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2283264912Skevlo R92C_SYS_FUNC_EN_CPUEN); 2284251538Srpaulo} 2285251538Srpaulo 2286264912Skevlostatic void 2287264912Skevlourtwn_r88e_fw_reset(struct urtwn_softc *sc) 2288264912Skevlo{ 2289264912Skevlo uint16_t reg; 2290264912Skevlo 2291264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2292264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2293264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2294264912Skevlo} 2295264912Skevlo 2296251538Srpaulostatic int 2297251538Srpaulourtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2298251538Srpaulo{ 2299251538Srpaulo uint32_t reg; 2300251538Srpaulo int off, mlen, error = 0; 2301251538Srpaulo 2302251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2303251538Srpaulo reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2304251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2305251538Srpaulo 2306251538Srpaulo off = R92C_FW_START_ADDR; 2307251538Srpaulo while (len > 0) { 2308251538Srpaulo if (len > 196) 2309251538Srpaulo mlen = 196; 2310251538Srpaulo else if (len > 4) 2311251538Srpaulo mlen = 4; 2312251538Srpaulo else 2313251538Srpaulo mlen = 1; 2314251538Srpaulo /* XXX fix this deconst */ 2315251538Srpaulo error = urtwn_write_region_1(sc, off, 2316251538Srpaulo __DECONST(uint8_t *, buf), mlen); 2317251538Srpaulo if (error != 0) 2318251538Srpaulo break; 2319251538Srpaulo off += mlen; 2320251538Srpaulo buf += mlen; 2321251538Srpaulo len -= mlen; 2322251538Srpaulo } 2323251538Srpaulo return (error); 2324251538Srpaulo} 2325251538Srpaulo 2326251538Srpaulostatic int 2327251538Srpaulourtwn_load_firmware(struct urtwn_softc *sc) 2328251538Srpaulo{ 2329251538Srpaulo const struct firmware *fw; 2330251538Srpaulo const struct r92c_fw_hdr *hdr; 2331251538Srpaulo const char *imagename; 2332251538Srpaulo const u_char *ptr; 2333251538Srpaulo size_t len; 2334251538Srpaulo uint32_t reg; 2335251538Srpaulo int mlen, ntries, page, error; 2336251538Srpaulo 2337264864Skevlo URTWN_UNLOCK(sc); 2338251538Srpaulo /* Read firmware image from the filesystem. */ 2339264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2340264912Skevlo imagename = "urtwn-rtl8188eufw"; 2341264912Skevlo else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2342264912Skevlo URTWN_CHIP_UMC_A_CUT) 2343251538Srpaulo imagename = "urtwn-rtl8192cfwU"; 2344251538Srpaulo else 2345251538Srpaulo imagename = "urtwn-rtl8192cfwT"; 2346251538Srpaulo 2347251538Srpaulo fw = firmware_get(imagename); 2348264864Skevlo URTWN_LOCK(sc); 2349251538Srpaulo if (fw == NULL) { 2350251538Srpaulo device_printf(sc->sc_dev, 2351251538Srpaulo "failed loadfirmware of file %s\n", imagename); 2352251538Srpaulo return (ENOENT); 2353251538Srpaulo } 2354251538Srpaulo 2355251538Srpaulo len = fw->datasize; 2356251538Srpaulo 2357251538Srpaulo if (len < sizeof(*hdr)) { 2358251538Srpaulo device_printf(sc->sc_dev, "firmware too short\n"); 2359251538Srpaulo error = EINVAL; 2360251538Srpaulo goto fail; 2361251538Srpaulo } 2362251538Srpaulo ptr = fw->data; 2363251538Srpaulo hdr = (const struct r92c_fw_hdr *)ptr; 2364251538Srpaulo /* Check if there is a valid FW header and skip it. */ 2365251538Srpaulo if ((le16toh(hdr->signature) >> 4) == 0x88c || 2366264912Skevlo (le16toh(hdr->signature) >> 4) == 0x88e || 2367251538Srpaulo (le16toh(hdr->signature) >> 4) == 0x92c) { 2368251538Srpaulo DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2369251538Srpaulo le16toh(hdr->version), le16toh(hdr->subversion), 2370251538Srpaulo hdr->month, hdr->date, hdr->hour, hdr->minute); 2371251538Srpaulo ptr += sizeof(*hdr); 2372251538Srpaulo len -= sizeof(*hdr); 2373251538Srpaulo } 2374251538Srpaulo 2375264912Skevlo if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2376264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2377264912Skevlo urtwn_r88e_fw_reset(sc); 2378264912Skevlo else 2379264912Skevlo urtwn_fw_reset(sc); 2380251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 0); 2381251538Srpaulo } 2382264912Skevlo 2383251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2384251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2385251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 2, 2386251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2387251538Srpaulo 2388263154Skevlo /* Reset the FWDL checksum. */ 2389263154Skevlo urtwn_write_1(sc, R92C_MCUFWDL, 2390263154Skevlo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2391263154Skevlo 2392251538Srpaulo for (page = 0; len > 0; page++) { 2393251538Srpaulo mlen = min(len, R92C_FW_PAGE_SIZE); 2394251538Srpaulo error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2395251538Srpaulo if (error != 0) { 2396251538Srpaulo device_printf(sc->sc_dev, 2397251538Srpaulo "could not load firmware page\n"); 2398251538Srpaulo goto fail; 2399251538Srpaulo } 2400251538Srpaulo ptr += mlen; 2401251538Srpaulo len -= mlen; 2402251538Srpaulo } 2403251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2404251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2405251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2406251538Srpaulo 2407251538Srpaulo /* Wait for checksum report. */ 2408251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2409251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2410251538Srpaulo break; 2411251538Srpaulo DELAY(5); 2412251538Srpaulo } 2413251538Srpaulo if (ntries == 1000) { 2414251538Srpaulo device_printf(sc->sc_dev, 2415251538Srpaulo "timeout waiting for checksum report\n"); 2416251538Srpaulo error = ETIMEDOUT; 2417251538Srpaulo goto fail; 2418251538Srpaulo } 2419251538Srpaulo 2420251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2421251538Srpaulo reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2422251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2423264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2424264912Skevlo urtwn_r88e_fw_reset(sc); 2425251538Srpaulo /* Wait for firmware readiness. */ 2426251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2427251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2428251538Srpaulo break; 2429251538Srpaulo DELAY(5); 2430251538Srpaulo } 2431251538Srpaulo if (ntries == 1000) { 2432251538Srpaulo device_printf(sc->sc_dev, 2433251538Srpaulo "timeout waiting for firmware readiness\n"); 2434251538Srpaulo error = ETIMEDOUT; 2435251538Srpaulo goto fail; 2436251538Srpaulo } 2437251538Srpaulofail: 2438251538Srpaulo firmware_put(fw, FIRMWARE_UNLOAD); 2439251538Srpaulo return (error); 2440251538Srpaulo} 2441251538Srpaulo 2442264912Skevlostatic __inline int 2443251538Srpaulourtwn_dma_init(struct urtwn_softc *sc) 2444251538Srpaulo{ 2445264912Skevlo 2446264912Skevlo return sc->sc_dma_init(sc); 2447264912Skevlo} 2448264912Skevlo 2449264912Skevlostatic int 2450264912Skevlourtwn_r92c_dma_init(struct urtwn_softc *sc) 2451264912Skevlo{ 2452251538Srpaulo int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2453251538Srpaulo uint32_t reg; 2454251538Srpaulo int error; 2455251538Srpaulo 2456251538Srpaulo /* Initialize LLT table. */ 2457251538Srpaulo error = urtwn_llt_init(sc); 2458251538Srpaulo if (error != 0) 2459251538Srpaulo return (error); 2460251538Srpaulo 2461251538Srpaulo /* Get Tx queues to USB endpoints mapping. */ 2462251538Srpaulo hashq = hasnq = haslq = 0; 2463251538Srpaulo reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2464251538Srpaulo DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2465251538Srpaulo if (MS(reg, R92C_USB_EP_HQ) != 0) 2466251538Srpaulo hashq = 1; 2467251538Srpaulo if (MS(reg, R92C_USB_EP_NQ) != 0) 2468251538Srpaulo hasnq = 1; 2469251538Srpaulo if (MS(reg, R92C_USB_EP_LQ) != 0) 2470251538Srpaulo haslq = 1; 2471251538Srpaulo nqueues = hashq + hasnq + haslq; 2472251538Srpaulo if (nqueues == 0) 2473251538Srpaulo return (EIO); 2474251538Srpaulo /* Get the number of pages for each queue. */ 2475251538Srpaulo nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2476251538Srpaulo /* The remaining pages are assigned to the high priority queue. */ 2477251538Srpaulo nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2478251538Srpaulo 2479251538Srpaulo /* Set number of pages for normal priority queue. */ 2480251538Srpaulo urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2481251538Srpaulo urtwn_write_4(sc, R92C_RQPN, 2482251538Srpaulo /* Set number of pages for public queue. */ 2483251538Srpaulo SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2484251538Srpaulo /* Set number of pages for high priority queue. */ 2485251538Srpaulo SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2486251538Srpaulo /* Set number of pages for low priority queue. */ 2487251538Srpaulo SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2488251538Srpaulo /* Load values. */ 2489251538Srpaulo R92C_RQPN_LD); 2490251538Srpaulo 2491251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2492251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2493251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2494251538Srpaulo urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2495251538Srpaulo urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2496251538Srpaulo 2497251538Srpaulo /* Set queue to USB pipe mapping. */ 2498251538Srpaulo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2499251538Srpaulo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2500251538Srpaulo if (nqueues == 1) { 2501251538Srpaulo if (hashq) 2502251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2503251538Srpaulo else if (hasnq) 2504251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2505251538Srpaulo else 2506251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2507251538Srpaulo } else if (nqueues == 2) { 2508251538Srpaulo /* All 2-endpoints configs have a high priority queue. */ 2509251538Srpaulo if (!hashq) 2510251538Srpaulo return (EIO); 2511251538Srpaulo if (hasnq) 2512251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2513251538Srpaulo else 2514251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2515251538Srpaulo } else 2516251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2517251538Srpaulo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2518251538Srpaulo 2519251538Srpaulo /* Set Tx/Rx transfer page boundary. */ 2520251538Srpaulo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2521251538Srpaulo 2522251538Srpaulo /* Set Tx/Rx transfer page size. */ 2523251538Srpaulo urtwn_write_1(sc, R92C_PBP, 2524251538Srpaulo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2525251538Srpaulo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2526251538Srpaulo return (0); 2527251538Srpaulo} 2528251538Srpaulo 2529264912Skevlostatic int 2530264912Skevlourtwn_r88e_dma_init(struct urtwn_softc *sc) 2531264912Skevlo{ 2532264912Skevlo struct usb_interface *iface; 2533264912Skevlo uint32_t reg; 2534264912Skevlo int nqueues; 2535264912Skevlo int error; 2536264912Skevlo 2537264912Skevlo /* Initialize LLT table. */ 2538264912Skevlo error = urtwn_llt_init(sc); 2539264912Skevlo if (error != 0) 2540264912Skevlo return (error); 2541264912Skevlo 2542264912Skevlo /* Get Tx queues to USB endpoints mapping. */ 2543264912Skevlo iface = usbd_get_iface(sc->sc_udev, 0); 2544264912Skevlo nqueues = iface->idesc->bNumEndpoints - 1; 2545264912Skevlo if (nqueues == 0) 2546264912Skevlo return (EIO); 2547264912Skevlo 2548264912Skevlo /* Set number of pages for normal priority queue. */ 2549264912Skevlo urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2550264912Skevlo urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2551264912Skevlo urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2552264912Skevlo 2553264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2554264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2555264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2556264912Skevlo urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2557264912Skevlo urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2558264912Skevlo 2559264912Skevlo /* Set queue to USB pipe mapping. */ 2560264912Skevlo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2561264912Skevlo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2562264912Skevlo if (nqueues == 1) 2563264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2564264912Skevlo else if (nqueues == 2) 2565264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2566264912Skevlo else 2567264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2568264912Skevlo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2569264912Skevlo 2570264912Skevlo /* Set Tx/Rx transfer page boundary. */ 2571264912Skevlo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2572264912Skevlo 2573264912Skevlo /* Set Tx/Rx transfer page size. */ 2574264912Skevlo urtwn_write_1(sc, R92C_PBP, 2575264912Skevlo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2576264912Skevlo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2577264912Skevlo 2578264912Skevlo return (0); 2579264912Skevlo} 2580264912Skevlo 2581251538Srpaulostatic void 2582251538Srpaulourtwn_mac_init(struct urtwn_softc *sc) 2583251538Srpaulo{ 2584251538Srpaulo int i; 2585251538Srpaulo 2586251538Srpaulo /* Write MAC initialization values. */ 2587264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2588264912Skevlo for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2589264912Skevlo urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2590264912Skevlo rtl8188eu_mac[i].val); 2591264912Skevlo } 2592264912Skevlo urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2593264912Skevlo } else { 2594264912Skevlo for (i = 0; i < nitems(rtl8192cu_mac); i++) 2595264912Skevlo urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2596264912Skevlo rtl8192cu_mac[i].val); 2597264912Skevlo } 2598251538Srpaulo} 2599251538Srpaulo 2600251538Srpaulostatic void 2601251538Srpaulourtwn_bb_init(struct urtwn_softc *sc) 2602251538Srpaulo{ 2603251538Srpaulo const struct urtwn_bb_prog *prog; 2604251538Srpaulo uint32_t reg; 2605264912Skevlo uint8_t crystalcap; 2606251538Srpaulo int i; 2607251538Srpaulo 2608251538Srpaulo /* Enable BB and RF. */ 2609251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2610251538Srpaulo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2611251538Srpaulo R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2612251538Srpaulo R92C_SYS_FUNC_EN_DIO_RF); 2613251538Srpaulo 2614264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 2615264912Skevlo urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2616251538Srpaulo 2617251538Srpaulo urtwn_write_1(sc, R92C_RF_CTRL, 2618251538Srpaulo R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2619251538Srpaulo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2620251538Srpaulo R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2621251538Srpaulo R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2622251538Srpaulo 2623264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2624264912Skevlo urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2625264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 2626264912Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2627264912Skevlo } 2628251538Srpaulo 2629251538Srpaulo /* Select BB programming based on board type. */ 2630264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2631264912Skevlo prog = &rtl8188eu_bb_prog; 2632264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2633251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2634251538Srpaulo prog = &rtl8188ce_bb_prog; 2635251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2636251538Srpaulo prog = &rtl8188ru_bb_prog; 2637251538Srpaulo else 2638251538Srpaulo prog = &rtl8188cu_bb_prog; 2639251538Srpaulo } else { 2640251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2641251538Srpaulo prog = &rtl8192ce_bb_prog; 2642251538Srpaulo else 2643251538Srpaulo prog = &rtl8192cu_bb_prog; 2644251538Srpaulo } 2645251538Srpaulo /* Write BB initialization values. */ 2646251538Srpaulo for (i = 0; i < prog->count; i++) { 2647251538Srpaulo urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2648251538Srpaulo DELAY(1); 2649251538Srpaulo } 2650251538Srpaulo 2651251538Srpaulo if (sc->chip & URTWN_CHIP_92C_1T2R) { 2652251538Srpaulo /* 8192C 1T only configuration. */ 2653251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2654251538Srpaulo reg = (reg & ~0x00000003) | 0x2; 2655251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2656251538Srpaulo 2657251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2658251538Srpaulo reg = (reg & ~0x00300033) | 0x00200022; 2659251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2660251538Srpaulo 2661251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2662251538Srpaulo reg = (reg & ~0xff000000) | 0x45 << 24; 2663251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2664251538Srpaulo 2665251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2666251538Srpaulo reg = (reg & ~0x000000ff) | 0x23; 2667251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2668251538Srpaulo 2669251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2670251538Srpaulo reg = (reg & ~0x00000030) | 1 << 4; 2671251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2672251538Srpaulo 2673251538Srpaulo reg = urtwn_bb_read(sc, 0xe74); 2674251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2675251538Srpaulo urtwn_bb_write(sc, 0xe74, reg); 2676251538Srpaulo reg = urtwn_bb_read(sc, 0xe78); 2677251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2678251538Srpaulo urtwn_bb_write(sc, 0xe78, reg); 2679251538Srpaulo reg = urtwn_bb_read(sc, 0xe7c); 2680251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2681251538Srpaulo urtwn_bb_write(sc, 0xe7c, reg); 2682251538Srpaulo reg = urtwn_bb_read(sc, 0xe80); 2683251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2684251538Srpaulo urtwn_bb_write(sc, 0xe80, reg); 2685251538Srpaulo reg = urtwn_bb_read(sc, 0xe88); 2686251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2687251538Srpaulo urtwn_bb_write(sc, 0xe88, reg); 2688251538Srpaulo } 2689251538Srpaulo 2690251538Srpaulo /* Write AGC values. */ 2691251538Srpaulo for (i = 0; i < prog->agccount; i++) { 2692251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2693251538Srpaulo prog->agcvals[i]); 2694251538Srpaulo DELAY(1); 2695251538Srpaulo } 2696251538Srpaulo 2697264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2698264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2699264912Skevlo DELAY(1); 2700264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2701264912Skevlo DELAY(1); 2702264912Skevlo 2703264912Skevlo crystalcap = sc->r88e_rom[0xb9]; 2704264912Skevlo if (crystalcap == 0xff) 2705264912Skevlo crystalcap = 0x20; 2706264912Skevlo crystalcap &= 0x3f; 2707264912Skevlo reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2708264912Skevlo urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2709264912Skevlo RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2710264912Skevlo crystalcap | crystalcap << 6)); 2711264912Skevlo } else { 2712264912Skevlo if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2713264912Skevlo R92C_HSSI_PARAM2_CCK_HIPWR) 2714264912Skevlo sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2715264912Skevlo } 2716251538Srpaulo} 2717251538Srpaulo 2718251538Srpaulovoid 2719251538Srpaulourtwn_rf_init(struct urtwn_softc *sc) 2720251538Srpaulo{ 2721251538Srpaulo const struct urtwn_rf_prog *prog; 2722251538Srpaulo uint32_t reg, type; 2723251538Srpaulo int i, j, idx, off; 2724251538Srpaulo 2725251538Srpaulo /* Select RF programming based on board type. */ 2726264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2727264912Skevlo prog = rtl8188eu_rf_prog; 2728264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2729251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2730251538Srpaulo prog = rtl8188ce_rf_prog; 2731251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2732251538Srpaulo prog = rtl8188ru_rf_prog; 2733251538Srpaulo else 2734251538Srpaulo prog = rtl8188cu_rf_prog; 2735251538Srpaulo } else 2736251538Srpaulo prog = rtl8192ce_rf_prog; 2737251538Srpaulo 2738251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2739251538Srpaulo /* Save RF_ENV control type. */ 2740251538Srpaulo idx = i / 2; 2741251538Srpaulo off = (i % 2) * 16; 2742251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2743251538Srpaulo type = (reg >> off) & 0x10; 2744251538Srpaulo 2745251538Srpaulo /* Set RF_ENV enable. */ 2746251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2747251538Srpaulo reg |= 0x100000; 2748251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2749251538Srpaulo DELAY(1); 2750251538Srpaulo /* Set RF_ENV output high. */ 2751251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2752251538Srpaulo reg |= 0x10; 2753251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2754251538Srpaulo DELAY(1); 2755251538Srpaulo /* Set address and data lengths of RF registers. */ 2756251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2757251538Srpaulo reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2758251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2759251538Srpaulo DELAY(1); 2760251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2761251538Srpaulo reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2762251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2763251538Srpaulo DELAY(1); 2764251538Srpaulo 2765251538Srpaulo /* Write RF initialization values for this chain. */ 2766251538Srpaulo for (j = 0; j < prog[i].count; j++) { 2767251538Srpaulo if (prog[i].regs[j] >= 0xf9 && 2768251538Srpaulo prog[i].regs[j] <= 0xfe) { 2769251538Srpaulo /* 2770251538Srpaulo * These are fake RF registers offsets that 2771251538Srpaulo * indicate a delay is required. 2772251538Srpaulo */ 2773251538Srpaulo usb_pause_mtx(&sc->sc_mtx, 50); 2774251538Srpaulo continue; 2775251538Srpaulo } 2776251538Srpaulo urtwn_rf_write(sc, i, prog[i].regs[j], 2777251538Srpaulo prog[i].vals[j]); 2778251538Srpaulo DELAY(1); 2779251538Srpaulo } 2780251538Srpaulo 2781251538Srpaulo /* Restore RF_ENV control type. */ 2782251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2783251538Srpaulo reg &= ~(0x10 << off) | (type << off); 2784251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2785251538Srpaulo 2786251538Srpaulo /* Cache RF register CHNLBW. */ 2787251538Srpaulo sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2788251538Srpaulo } 2789251538Srpaulo 2790251538Srpaulo if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2791251538Srpaulo URTWN_CHIP_UMC_A_CUT) { 2792251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2793251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2794251538Srpaulo } 2795251538Srpaulo} 2796251538Srpaulo 2797251538Srpaulostatic void 2798251538Srpaulourtwn_cam_init(struct urtwn_softc *sc) 2799251538Srpaulo{ 2800251538Srpaulo /* Invalidate all CAM entries. */ 2801251538Srpaulo urtwn_write_4(sc, R92C_CAMCMD, 2802251538Srpaulo R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2803251538Srpaulo} 2804251538Srpaulo 2805251538Srpaulostatic void 2806251538Srpaulourtwn_pa_bias_init(struct urtwn_softc *sc) 2807251538Srpaulo{ 2808251538Srpaulo uint8_t reg; 2809251538Srpaulo int i; 2810251538Srpaulo 2811251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2812251538Srpaulo if (sc->pa_setting & (1 << i)) 2813251538Srpaulo continue; 2814251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2815251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2816251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2817251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2818251538Srpaulo } 2819251538Srpaulo if (!(sc->pa_setting & 0x10)) { 2820251538Srpaulo reg = urtwn_read_1(sc, 0x16); 2821251538Srpaulo reg = (reg & ~0xf0) | 0x90; 2822251538Srpaulo urtwn_write_1(sc, 0x16, reg); 2823251538Srpaulo } 2824251538Srpaulo} 2825251538Srpaulo 2826251538Srpaulostatic void 2827251538Srpaulourtwn_rxfilter_init(struct urtwn_softc *sc) 2828251538Srpaulo{ 2829251538Srpaulo /* Initialize Rx filter. */ 2830251538Srpaulo /* TODO: use better filter for monitor mode. */ 2831251538Srpaulo urtwn_write_4(sc, R92C_RCR, 2832251538Srpaulo R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2833251538Srpaulo R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2834251538Srpaulo R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2835251538Srpaulo /* Accept all multicast frames. */ 2836251538Srpaulo urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2837251538Srpaulo urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2838251538Srpaulo /* Accept all management frames. */ 2839251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2840251538Srpaulo /* Reject all control frames. */ 2841251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2842251538Srpaulo /* Accept all data frames. */ 2843251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2844251538Srpaulo} 2845251538Srpaulo 2846251538Srpaulostatic void 2847251538Srpaulourtwn_edca_init(struct urtwn_softc *sc) 2848251538Srpaulo{ 2849251538Srpaulo urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2850251538Srpaulo urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2851251538Srpaulo urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2852251538Srpaulo urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2853251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2854251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2855251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2856251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2857251538Srpaulo} 2858251538Srpaulo 2859251538Srpaulovoid 2860251538Srpaulourtwn_write_txpower(struct urtwn_softc *sc, int chain, 2861251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2862251538Srpaulo{ 2863251538Srpaulo uint32_t reg; 2864251538Srpaulo 2865251538Srpaulo /* Write per-CCK rate Tx power. */ 2866251538Srpaulo if (chain == 0) { 2867251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2868251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2869251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2870251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2871251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2872251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2873251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2874251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2875251538Srpaulo } else { 2876251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2877251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2878251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2879251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2880251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2881251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2882251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2883251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2884251538Srpaulo } 2885251538Srpaulo /* Write per-OFDM rate Tx power. */ 2886251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2887251538Srpaulo SM(R92C_TXAGC_RATE06, power[ 4]) | 2888251538Srpaulo SM(R92C_TXAGC_RATE09, power[ 5]) | 2889251538Srpaulo SM(R92C_TXAGC_RATE12, power[ 6]) | 2890251538Srpaulo SM(R92C_TXAGC_RATE18, power[ 7])); 2891251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2892251538Srpaulo SM(R92C_TXAGC_RATE24, power[ 8]) | 2893251538Srpaulo SM(R92C_TXAGC_RATE36, power[ 9]) | 2894251538Srpaulo SM(R92C_TXAGC_RATE48, power[10]) | 2895251538Srpaulo SM(R92C_TXAGC_RATE54, power[11])); 2896251538Srpaulo /* Write per-MCS Tx power. */ 2897251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2898251538Srpaulo SM(R92C_TXAGC_MCS00, power[12]) | 2899251538Srpaulo SM(R92C_TXAGC_MCS01, power[13]) | 2900251538Srpaulo SM(R92C_TXAGC_MCS02, power[14]) | 2901251538Srpaulo SM(R92C_TXAGC_MCS03, power[15])); 2902251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2903251538Srpaulo SM(R92C_TXAGC_MCS04, power[16]) | 2904251538Srpaulo SM(R92C_TXAGC_MCS05, power[17]) | 2905251538Srpaulo SM(R92C_TXAGC_MCS06, power[18]) | 2906251538Srpaulo SM(R92C_TXAGC_MCS07, power[19])); 2907251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2908251538Srpaulo SM(R92C_TXAGC_MCS08, power[20]) | 2909261506Skevlo SM(R92C_TXAGC_MCS09, power[21]) | 2910251538Srpaulo SM(R92C_TXAGC_MCS10, power[22]) | 2911251538Srpaulo SM(R92C_TXAGC_MCS11, power[23])); 2912251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2913251538Srpaulo SM(R92C_TXAGC_MCS12, power[24]) | 2914251538Srpaulo SM(R92C_TXAGC_MCS13, power[25]) | 2915251538Srpaulo SM(R92C_TXAGC_MCS14, power[26]) | 2916251538Srpaulo SM(R92C_TXAGC_MCS15, power[27])); 2917251538Srpaulo} 2918251538Srpaulo 2919251538Srpaulovoid 2920251538Srpaulourtwn_get_txpower(struct urtwn_softc *sc, int chain, 2921251538Srpaulo struct ieee80211_channel *c, struct ieee80211_channel *extc, 2922251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2923251538Srpaulo{ 2924251538Srpaulo struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2925251538Srpaulo struct r92c_rom *rom = &sc->rom; 2926251538Srpaulo uint16_t cckpow, ofdmpow, htpow, diff, max; 2927251538Srpaulo const struct urtwn_txpwr *base; 2928251538Srpaulo int ridx, chan, group; 2929251538Srpaulo 2930251538Srpaulo /* Determine channel group. */ 2931251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2932251538Srpaulo if (chan <= 3) 2933251538Srpaulo group = 0; 2934251538Srpaulo else if (chan <= 9) 2935251538Srpaulo group = 1; 2936251538Srpaulo else 2937251538Srpaulo group = 2; 2938251538Srpaulo 2939251538Srpaulo /* Get original Tx power based on board type and RF chain. */ 2940251538Srpaulo if (!(sc->chip & URTWN_CHIP_92C)) { 2941251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2942251538Srpaulo base = &rtl8188ru_txagc[chain]; 2943251538Srpaulo else 2944251538Srpaulo base = &rtl8192cu_txagc[chain]; 2945251538Srpaulo } else 2946251538Srpaulo base = &rtl8192cu_txagc[chain]; 2947251538Srpaulo 2948251538Srpaulo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2949251538Srpaulo if (sc->regulatory == 0) { 2950251538Srpaulo for (ridx = 0; ridx <= 3; ridx++) 2951251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2952251538Srpaulo } 2953251538Srpaulo for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 2954251538Srpaulo if (sc->regulatory == 3) { 2955251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2956251538Srpaulo /* Apply vendor limits. */ 2957251538Srpaulo if (extc != NULL) 2958251538Srpaulo max = rom->ht40_max_pwr[group]; 2959251538Srpaulo else 2960251538Srpaulo max = rom->ht20_max_pwr[group]; 2961251538Srpaulo max = (max >> (chain * 4)) & 0xf; 2962251538Srpaulo if (power[ridx] > max) 2963251538Srpaulo power[ridx] = max; 2964251538Srpaulo } else if (sc->regulatory == 1) { 2965251538Srpaulo if (extc == NULL) 2966251538Srpaulo power[ridx] = base->pwr[group][ridx]; 2967251538Srpaulo } else if (sc->regulatory != 2) 2968251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2969251538Srpaulo } 2970251538Srpaulo 2971251538Srpaulo /* Compute per-CCK rate Tx power. */ 2972251538Srpaulo cckpow = rom->cck_tx_pwr[chain][group]; 2973251538Srpaulo for (ridx = 0; ridx <= 3; ridx++) { 2974251538Srpaulo power[ridx] += cckpow; 2975251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2976251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2977251538Srpaulo } 2978251538Srpaulo 2979251538Srpaulo htpow = rom->ht40_1s_tx_pwr[chain][group]; 2980251538Srpaulo if (sc->ntxchains > 1) { 2981251538Srpaulo /* Apply reduction for 2 spatial streams. */ 2982251538Srpaulo diff = rom->ht40_2s_tx_pwr_diff[group]; 2983251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2984251538Srpaulo htpow = (htpow > diff) ? htpow - diff : 0; 2985251538Srpaulo } 2986251538Srpaulo 2987251538Srpaulo /* Compute per-OFDM rate Tx power. */ 2988251538Srpaulo diff = rom->ofdm_tx_pwr_diff[group]; 2989251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2990251538Srpaulo ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2991251538Srpaulo for (ridx = 4; ridx <= 11; ridx++) { 2992251538Srpaulo power[ridx] += ofdmpow; 2993251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2994251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2995251538Srpaulo } 2996251538Srpaulo 2997251538Srpaulo /* Compute per-MCS Tx power. */ 2998251538Srpaulo if (extc == NULL) { 2999251538Srpaulo diff = rom->ht20_tx_pwr_diff[group]; 3000251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 3001251538Srpaulo htpow += diff; /* HT40->HT20 correction. */ 3002251538Srpaulo } 3003251538Srpaulo for (ridx = 12; ridx <= 27; ridx++) { 3004251538Srpaulo power[ridx] += htpow; 3005251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 3006251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 3007251538Srpaulo } 3008251538Srpaulo#ifdef URTWN_DEBUG 3009251538Srpaulo if (urtwn_debug >= 4) { 3010251538Srpaulo /* Dump per-rate Tx power values. */ 3011251538Srpaulo printf("Tx power for chain %d:\n", chain); 3012251538Srpaulo for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 3013251538Srpaulo printf("Rate %d = %u\n", ridx, power[ridx]); 3014251538Srpaulo } 3015251538Srpaulo#endif 3016251538Srpaulo} 3017251538Srpaulo 3018251538Srpaulovoid 3019264912Skevlourtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3020264912Skevlo struct ieee80211_channel *c, struct ieee80211_channel *extc, 3021264912Skevlo uint16_t power[URTWN_RIDX_COUNT]) 3022264912Skevlo{ 3023264912Skevlo struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3024264912Skevlo uint16_t cckpow, ofdmpow, bw20pow, htpow; 3025264912Skevlo const struct urtwn_r88e_txpwr *base; 3026264912Skevlo int ridx, chan, group; 3027264912Skevlo 3028264912Skevlo /* Determine channel group. */ 3029264912Skevlo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3030264912Skevlo if (chan <= 2) 3031264912Skevlo group = 0; 3032264912Skevlo else if (chan <= 5) 3033264912Skevlo group = 1; 3034264912Skevlo else if (chan <= 8) 3035264912Skevlo group = 2; 3036264912Skevlo else if (chan <= 11) 3037264912Skevlo group = 3; 3038264912Skevlo else if (chan <= 13) 3039264912Skevlo group = 4; 3040264912Skevlo else 3041264912Skevlo group = 5; 3042264912Skevlo 3043264912Skevlo /* Get original Tx power based on board type and RF chain. */ 3044264912Skevlo base = &rtl8188eu_txagc[chain]; 3045264912Skevlo 3046264912Skevlo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3047264912Skevlo if (sc->regulatory == 0) { 3048264912Skevlo for (ridx = 0; ridx <= 3; ridx++) 3049264912Skevlo power[ridx] = base->pwr[0][ridx]; 3050264912Skevlo } 3051264912Skevlo for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3052264912Skevlo if (sc->regulatory == 3) 3053264912Skevlo power[ridx] = base->pwr[0][ridx]; 3054264912Skevlo else if (sc->regulatory == 1) { 3055264912Skevlo if (extc == NULL) 3056264912Skevlo power[ridx] = base->pwr[group][ridx]; 3057264912Skevlo } else if (sc->regulatory != 2) 3058264912Skevlo power[ridx] = base->pwr[0][ridx]; 3059264912Skevlo } 3060264912Skevlo 3061264912Skevlo /* Compute per-CCK rate Tx power. */ 3062264912Skevlo cckpow = sc->cck_tx_pwr[group]; 3063264912Skevlo for (ridx = 0; ridx <= 3; ridx++) { 3064264912Skevlo power[ridx] += cckpow; 3065264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3066264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3067264912Skevlo } 3068264912Skevlo 3069264912Skevlo htpow = sc->ht40_tx_pwr[group]; 3070264912Skevlo 3071264912Skevlo /* Compute per-OFDM rate Tx power. */ 3072264912Skevlo ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3073264912Skevlo for (ridx = 4; ridx <= 11; ridx++) { 3074264912Skevlo power[ridx] += ofdmpow; 3075264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3076264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3077264912Skevlo } 3078264912Skevlo 3079264912Skevlo bw20pow = htpow + sc->bw20_tx_pwr_diff; 3080264912Skevlo for (ridx = 12; ridx <= 27; ridx++) { 3081264912Skevlo power[ridx] += bw20pow; 3082264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3083264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3084264912Skevlo } 3085264912Skevlo} 3086264912Skevlo 3087264912Skevlovoid 3088251538Srpaulourtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3089251538Srpaulo struct ieee80211_channel *extc) 3090251538Srpaulo{ 3091251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]; 3092251538Srpaulo int i; 3093251538Srpaulo 3094251538Srpaulo for (i = 0; i < sc->ntxchains; i++) { 3095251538Srpaulo /* Compute per-rate Tx power values. */ 3096264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3097264912Skevlo urtwn_r88e_get_txpower(sc, i, c, extc, power); 3098264912Skevlo else 3099264912Skevlo urtwn_get_txpower(sc, i, c, extc, power); 3100251538Srpaulo /* Write per-rate Tx power values to hardware. */ 3101251538Srpaulo urtwn_write_txpower(sc, i, power); 3102251538Srpaulo } 3103251538Srpaulo} 3104251538Srpaulo 3105251538Srpaulostatic void 3106251538Srpaulourtwn_scan_start(struct ieee80211com *ic) 3107251538Srpaulo{ 3108251538Srpaulo /* XXX do nothing? */ 3109251538Srpaulo} 3110251538Srpaulo 3111251538Srpaulostatic void 3112251538Srpaulourtwn_scan_end(struct ieee80211com *ic) 3113251538Srpaulo{ 3114251538Srpaulo /* XXX do nothing? */ 3115251538Srpaulo} 3116251538Srpaulo 3117251538Srpaulostatic void 3118251538Srpaulourtwn_set_channel(struct ieee80211com *ic) 3119251538Srpaulo{ 3120251538Srpaulo struct urtwn_softc *sc = ic->ic_ifp->if_softc; 3121251538Srpaulo 3122251538Srpaulo URTWN_LOCK(sc); 3123251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 3124251538Srpaulo URTWN_UNLOCK(sc); 3125251538Srpaulo} 3126251538Srpaulo 3127251538Srpaulostatic void 3128251538Srpaulourtwn_update_mcast(struct ifnet *ifp) 3129251538Srpaulo{ 3130251538Srpaulo /* XXX do nothing? */ 3131251538Srpaulo} 3132251538Srpaulo 3133251538Srpaulostatic void 3134251538Srpaulourtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3135251538Srpaulo struct ieee80211_channel *extc) 3136251538Srpaulo{ 3137251538Srpaulo struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3138251538Srpaulo uint32_t reg; 3139251538Srpaulo u_int chan; 3140251538Srpaulo int i; 3141251538Srpaulo 3142251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3143251538Srpaulo if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3144251538Srpaulo device_printf(sc->sc_dev, 3145251538Srpaulo "%s: invalid channel %x\n", __func__, chan); 3146251538Srpaulo return; 3147251538Srpaulo } 3148251538Srpaulo 3149251538Srpaulo /* Set Tx power for this new channel. */ 3150251538Srpaulo urtwn_set_txpower(sc, c, extc); 3151251538Srpaulo 3152251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3153251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3154251538Srpaulo RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3155251538Srpaulo } 3156251538Srpaulo#ifndef IEEE80211_NO_HT 3157251538Srpaulo if (extc != NULL) { 3158251538Srpaulo /* Is secondary channel below or above primary? */ 3159251538Srpaulo int prichlo = c->ic_freq < extc->ic_freq; 3160251538Srpaulo 3161251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3162251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3163251538Srpaulo 3164251538Srpaulo reg = urtwn_read_1(sc, R92C_RRSR + 2); 3165251538Srpaulo reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3166251538Srpaulo urtwn_write_1(sc, R92C_RRSR + 2, reg); 3167251538Srpaulo 3168251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3169251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3170251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3171251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3172251538Srpaulo 3173251538Srpaulo /* Set CCK side band. */ 3174251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3175251538Srpaulo reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3176251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3177251538Srpaulo 3178251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3179251538Srpaulo reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3180251538Srpaulo urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3181251538Srpaulo 3182251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3183251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3184251538Srpaulo ~R92C_FPGA0_ANAPARAM2_CBW20); 3185251538Srpaulo 3186251538Srpaulo reg = urtwn_bb_read(sc, 0x818); 3187251538Srpaulo reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3188251538Srpaulo urtwn_bb_write(sc, 0x818, reg); 3189251538Srpaulo 3190251538Srpaulo /* Select 40MHz bandwidth. */ 3191251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3192251538Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan); 3193251538Srpaulo } else 3194251538Srpaulo#endif 3195251538Srpaulo { 3196251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3197251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3198251538Srpaulo 3199251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3200251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3201251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3202251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3203251538Srpaulo 3204264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3205264912Skevlo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3206264912Skevlo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3207264912Skevlo R92C_FPGA0_ANAPARAM2_CBW20); 3208264912Skevlo } 3209264912Skevlo 3210251538Srpaulo /* Select 20MHz bandwidth. */ 3211251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3212264912Skevlo (sc->rf_chnlbw[0] & ~0xfff) | chan | 3213264912Skevlo ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3214264912Skevlo R92C_RF_CHNLBW_BW20)); 3215251538Srpaulo } 3216251538Srpaulo} 3217251538Srpaulo 3218251538Srpaulostatic void 3219251538Srpaulourtwn_iq_calib(struct urtwn_softc *sc) 3220251538Srpaulo{ 3221251538Srpaulo /* TODO */ 3222251538Srpaulo} 3223251538Srpaulo 3224251538Srpaulostatic void 3225251538Srpaulourtwn_lc_calib(struct urtwn_softc *sc) 3226251538Srpaulo{ 3227251538Srpaulo uint32_t rf_ac[2]; 3228251538Srpaulo uint8_t txmode; 3229251538Srpaulo int i; 3230251538Srpaulo 3231251538Srpaulo txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3232251538Srpaulo if ((txmode & 0x70) != 0) { 3233251538Srpaulo /* Disable all continuous Tx. */ 3234251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3235251538Srpaulo 3236251538Srpaulo /* Set RF mode to standby mode. */ 3237251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3238251538Srpaulo rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3239251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, 3240251538Srpaulo RW(rf_ac[i], R92C_RF_AC_MODE, 3241251538Srpaulo R92C_RF_AC_MODE_STANDBY)); 3242251538Srpaulo } 3243251538Srpaulo } else { 3244251538Srpaulo /* Block all Tx queues. */ 3245251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3246251538Srpaulo } 3247251538Srpaulo /* Start calibration. */ 3248251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3249251538Srpaulo urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3250251538Srpaulo 3251251538Srpaulo /* Give calibration the time to complete. */ 3252251538Srpaulo usb_pause_mtx(&sc->sc_mtx, 100); 3253251538Srpaulo 3254251538Srpaulo /* Restore configuration. */ 3255251538Srpaulo if ((txmode & 0x70) != 0) { 3256251538Srpaulo /* Restore Tx mode. */ 3257251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3258251538Srpaulo /* Restore RF mode. */ 3259251538Srpaulo for (i = 0; i < sc->nrxchains; i++) 3260251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3261251538Srpaulo } else { 3262251538Srpaulo /* Unblock all Tx queues. */ 3263251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3264251538Srpaulo } 3265251538Srpaulo} 3266251538Srpaulo 3267251538Srpaulostatic void 3268251538Srpaulourtwn_init_locked(void *arg) 3269251538Srpaulo{ 3270251538Srpaulo struct urtwn_softc *sc = arg; 3271251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 3272251538Srpaulo uint32_t reg; 3273251538Srpaulo int error; 3274251538Srpaulo 3275264864Skevlo URTWN_ASSERT_LOCKED(sc); 3276264864Skevlo 3277251538Srpaulo if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3278263153Skevlo urtwn_stop_locked(ifp); 3279251538Srpaulo 3280251538Srpaulo /* Init firmware commands ring. */ 3281251538Srpaulo sc->fwcur = 0; 3282251538Srpaulo 3283251538Srpaulo /* Allocate Tx/Rx buffers. */ 3284251538Srpaulo error = urtwn_alloc_rx_list(sc); 3285251538Srpaulo if (error != 0) 3286251538Srpaulo goto fail; 3287251538Srpaulo 3288251538Srpaulo error = urtwn_alloc_tx_list(sc); 3289251538Srpaulo if (error != 0) 3290251538Srpaulo goto fail; 3291251538Srpaulo 3292251538Srpaulo /* Power on adapter. */ 3293251538Srpaulo error = urtwn_power_on(sc); 3294251538Srpaulo if (error != 0) 3295251538Srpaulo goto fail; 3296251538Srpaulo 3297251538Srpaulo /* Initialize DMA. */ 3298251538Srpaulo error = urtwn_dma_init(sc); 3299251538Srpaulo if (error != 0) 3300251538Srpaulo goto fail; 3301251538Srpaulo 3302251538Srpaulo /* Set info size in Rx descriptors (in 64-bit words). */ 3303251538Srpaulo urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3304251538Srpaulo 3305251538Srpaulo /* Init interrupts. */ 3306264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3307264912Skevlo urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3308264912Skevlo urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3309264912Skevlo R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3310264912Skevlo urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3311264912Skevlo R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3312264912Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3313264912Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3314264912Skevlo R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3315264912Skevlo } else { 3316264912Skevlo urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3317264912Skevlo urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3318264912Skevlo } 3319251538Srpaulo 3320251538Srpaulo /* Set MAC address. */ 3321251538Srpaulo urtwn_write_region_1(sc, R92C_MACID, IF_LLADDR(ifp), 3322251538Srpaulo IEEE80211_ADDR_LEN); 3323251538Srpaulo 3324251538Srpaulo /* Set initial network type. */ 3325251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 3326251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3327251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 3328251538Srpaulo 3329251538Srpaulo urtwn_rxfilter_init(sc); 3330251538Srpaulo 3331251538Srpaulo reg = urtwn_read_4(sc, R92C_RRSR); 3332251538Srpaulo reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3333251538Srpaulo urtwn_write_4(sc, R92C_RRSR, reg); 3334251538Srpaulo 3335251538Srpaulo /* Set short/long retry limits. */ 3336251538Srpaulo urtwn_write_2(sc, R92C_RL, 3337251538Srpaulo SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3338251538Srpaulo 3339251538Srpaulo /* Initialize EDCA parameters. */ 3340251538Srpaulo urtwn_edca_init(sc); 3341251538Srpaulo 3342251538Srpaulo /* Setup rate fallback. */ 3343264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3344264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3345264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3346264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3347264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3348264912Skevlo } 3349251538Srpaulo 3350251538Srpaulo urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3351251538Srpaulo urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3352251538Srpaulo R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3353251538Srpaulo /* Set ACK timeout. */ 3354251538Srpaulo urtwn_write_1(sc, R92C_ACKTO, 0x40); 3355251538Srpaulo 3356251538Srpaulo /* Setup USB aggregation. */ 3357251538Srpaulo reg = urtwn_read_4(sc, R92C_TDECTRL); 3358251538Srpaulo reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3359251538Srpaulo urtwn_write_4(sc, R92C_TDECTRL, reg); 3360251538Srpaulo urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3361251538Srpaulo urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3362251538Srpaulo R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3363251538Srpaulo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3364251538Srpaulo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3365251538Srpaulo R92C_USB_SPECIAL_OPTION_AGG_EN); 3366251538Srpaulo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3367264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3368264912Skevlo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3369264912Skevlo else 3370264912Skevlo urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3371251538Srpaulo urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3372251538Srpaulo urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3373251538Srpaulo 3374251538Srpaulo /* Initialize beacon parameters. */ 3375264912Skevlo urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3376251538Srpaulo urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3377251538Srpaulo urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3378251538Srpaulo urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3379251538Srpaulo urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3380251538Srpaulo 3381264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3382264912Skevlo /* Setup AMPDU aggregation. */ 3383264912Skevlo urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3384264912Skevlo urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3385264912Skevlo urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3386251538Srpaulo 3387264912Skevlo urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3388264912Skevlo } 3389251538Srpaulo 3390251538Srpaulo /* Load 8051 microcode. */ 3391251538Srpaulo error = urtwn_load_firmware(sc); 3392251538Srpaulo if (error != 0) 3393251538Srpaulo goto fail; 3394251538Srpaulo 3395251538Srpaulo /* Initialize MAC/BB/RF blocks. */ 3396251538Srpaulo urtwn_mac_init(sc); 3397251538Srpaulo urtwn_bb_init(sc); 3398251538Srpaulo urtwn_rf_init(sc); 3399251538Srpaulo 3400264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3401264912Skevlo urtwn_write_2(sc, R92C_CR, 3402264912Skevlo urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3403264912Skevlo R92C_CR_MACRXEN); 3404264912Skevlo } 3405264912Skevlo 3406251538Srpaulo /* Turn CCK and OFDM blocks on. */ 3407251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3408251538Srpaulo reg |= R92C_RFMOD_CCK_EN; 3409251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3410251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3411251538Srpaulo reg |= R92C_RFMOD_OFDM_EN; 3412251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3413251538Srpaulo 3414251538Srpaulo /* Clear per-station keys table. */ 3415251538Srpaulo urtwn_cam_init(sc); 3416251538Srpaulo 3417251538Srpaulo /* Enable hardware sequence numbering. */ 3418251538Srpaulo urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3419251538Srpaulo 3420251538Srpaulo /* Perform LO and IQ calibrations. */ 3421251538Srpaulo urtwn_iq_calib(sc); 3422251538Srpaulo /* Perform LC calibration. */ 3423251538Srpaulo urtwn_lc_calib(sc); 3424251538Srpaulo 3425251538Srpaulo /* Fix USB interference issue. */ 3426264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3427264912Skevlo urtwn_write_1(sc, 0xfe40, 0xe0); 3428264912Skevlo urtwn_write_1(sc, 0xfe41, 0x8d); 3429264912Skevlo urtwn_write_1(sc, 0xfe42, 0x80); 3430251538Srpaulo 3431264912Skevlo urtwn_pa_bias_init(sc); 3432264912Skevlo } 3433251538Srpaulo 3434251538Srpaulo /* Initialize GPIO setting. */ 3435251538Srpaulo urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3436251538Srpaulo urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3437251538Srpaulo 3438251538Srpaulo /* Fix for lower temperature. */ 3439264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 3440264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 3441251538Srpaulo 3442251538Srpaulo usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3443251538Srpaulo 3444251538Srpaulo ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3445251538Srpaulo ifp->if_drv_flags |= IFF_DRV_RUNNING; 3446251538Srpaulo 3447251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3448251538Srpaulofail: 3449251538Srpaulo return; 3450251538Srpaulo} 3451251538Srpaulo 3452251538Srpaulostatic void 3453251538Srpaulourtwn_init(void *arg) 3454251538Srpaulo{ 3455251538Srpaulo struct urtwn_softc *sc = arg; 3456251538Srpaulo 3457251538Srpaulo URTWN_LOCK(sc); 3458251538Srpaulo urtwn_init_locked(arg); 3459251538Srpaulo URTWN_UNLOCK(sc); 3460251538Srpaulo} 3461251538Srpaulo 3462251538Srpaulostatic void 3463263153Skevlourtwn_stop_locked(struct ifnet *ifp) 3464251538Srpaulo{ 3465251538Srpaulo struct urtwn_softc *sc = ifp->if_softc; 3466251538Srpaulo 3467264864Skevlo URTWN_ASSERT_LOCKED(sc); 3468264864Skevlo 3469251538Srpaulo ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3470251538Srpaulo 3471251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 3472251538Srpaulo urtwn_abort_xfers(sc); 3473251538Srpaulo} 3474251538Srpaulo 3475251538Srpaulostatic void 3476263153Skevlourtwn_stop(struct ifnet *ifp) 3477251538Srpaulo{ 3478251538Srpaulo struct urtwn_softc *sc = ifp->if_softc; 3479251538Srpaulo 3480251538Srpaulo URTWN_LOCK(sc); 3481263153Skevlo urtwn_stop_locked(ifp); 3482251538Srpaulo URTWN_UNLOCK(sc); 3483251538Srpaulo} 3484251538Srpaulo 3485251538Srpaulostatic void 3486251538Srpaulourtwn_abort_xfers(struct urtwn_softc *sc) 3487251538Srpaulo{ 3488251538Srpaulo int i; 3489251538Srpaulo 3490251538Srpaulo URTWN_ASSERT_LOCKED(sc); 3491251538Srpaulo 3492251538Srpaulo /* abort any pending transfers */ 3493251538Srpaulo for (i = 0; i < URTWN_N_TRANSFER; i++) 3494251538Srpaulo usbd_transfer_stop(sc->sc_xfer[i]); 3495251538Srpaulo} 3496251538Srpaulo 3497251538Srpaulostatic int 3498251538Srpaulourtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3499251538Srpaulo const struct ieee80211_bpf_params *params) 3500251538Srpaulo{ 3501251538Srpaulo struct ieee80211com *ic = ni->ni_ic; 3502251538Srpaulo struct ifnet *ifp = ic->ic_ifp; 3503251538Srpaulo struct urtwn_softc *sc = ifp->if_softc; 3504251538Srpaulo struct urtwn_data *bf; 3505251538Srpaulo 3506251538Srpaulo /* prevent management frames from being sent if we're not ready */ 3507251538Srpaulo if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3508251538Srpaulo m_freem(m); 3509251538Srpaulo ieee80211_free_node(ni); 3510251538Srpaulo return (ENETDOWN); 3511251538Srpaulo } 3512251538Srpaulo URTWN_LOCK(sc); 3513251538Srpaulo bf = urtwn_getbuf(sc); 3514251538Srpaulo if (bf == NULL) { 3515251538Srpaulo ieee80211_free_node(ni); 3516251538Srpaulo m_freem(m); 3517251538Srpaulo URTWN_UNLOCK(sc); 3518251538Srpaulo return (ENOBUFS); 3519251538Srpaulo } 3520251538Srpaulo 3521251538Srpaulo ifp->if_opackets++; 3522251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3523251538Srpaulo ieee80211_free_node(ni); 3524251538Srpaulo ifp->if_oerrors++; 3525251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3526251538Srpaulo URTWN_UNLOCK(sc); 3527251538Srpaulo return (EIO); 3528251538Srpaulo } 3529251538Srpaulo URTWN_UNLOCK(sc); 3530251538Srpaulo 3531251538Srpaulo sc->sc_txtimer = 5; 3532251538Srpaulo return (0); 3533251538Srpaulo} 3534251538Srpaulo 3535251538Srpaulostatic device_method_t urtwn_methods[] = { 3536251538Srpaulo /* Device interface */ 3537251538Srpaulo DEVMETHOD(device_probe, urtwn_match), 3538251538Srpaulo DEVMETHOD(device_attach, urtwn_attach), 3539251538Srpaulo DEVMETHOD(device_detach, urtwn_detach), 3540251538Srpaulo 3541264912Skevlo DEVMETHOD_END 3542251538Srpaulo}; 3543251538Srpaulo 3544251538Srpaulostatic driver_t urtwn_driver = { 3545251538Srpaulo "urtwn", 3546251538Srpaulo urtwn_methods, 3547251538Srpaulo sizeof(struct urtwn_softc) 3548251538Srpaulo}; 3549251538Srpaulo 3550251538Srpaulostatic devclass_t urtwn_devclass; 3551251538Srpaulo 3552251538SrpauloDRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3553251538SrpauloMODULE_DEPEND(urtwn, usb, 1, 1, 1); 3554251538SrpauloMODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3555251538SrpauloMODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3556251538SrpauloMODULE_VERSION(urtwn, 1); 3557