ubsec.c revision 163648
1/* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */ 2 3/*- 4 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 5 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 6 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Jason L. Wright 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Effort sponsored in part by the Defense Advanced Research Projects 37 * Agency (DARPA) and Air Force Research Laboratory, Air Force 38 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/dev/ubsec/ubsec.c 163648 2006-10-24 11:17:46Z ru $"); 43 44/* 45 * uBsec 5[56]01, 58xx hardware crypto accelerator 46 */ 47 48#include "opt_ubsec.h" 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/proc.h> 53#include <sys/errno.h> 54#include <sys/malloc.h> 55#include <sys/kernel.h> 56#include <sys/module.h> 57#include <sys/mbuf.h> 58#include <sys/lock.h> 59#include <sys/mutex.h> 60#include <sys/sysctl.h> 61#include <sys/endian.h> 62 63#include <vm/vm.h> 64#include <vm/pmap.h> 65 66#include <machine/bus.h> 67#include <machine/resource.h> 68#include <sys/bus.h> 69#include <sys/rman.h> 70 71#include <crypto/sha1.h> 72#include <opencrypto/cryptodev.h> 73#include <opencrypto/cryptosoft.h> 74#include <sys/md5.h> 75#include <sys/random.h> 76 77#include <dev/pci/pcivar.h> 78#include <dev/pci/pcireg.h> 79 80/* grr, #defines for gratuitous incompatibility in queue.h */ 81#define SIMPLEQ_HEAD STAILQ_HEAD 82#define SIMPLEQ_ENTRY STAILQ_ENTRY 83#define SIMPLEQ_INIT STAILQ_INIT 84#define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL 85#define SIMPLEQ_EMPTY STAILQ_EMPTY 86#define SIMPLEQ_FIRST STAILQ_FIRST 87#define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD 88#define SIMPLEQ_FOREACH STAILQ_FOREACH 89/* ditto for endian.h */ 90#define letoh16(x) le16toh(x) 91#define letoh32(x) le32toh(x) 92 93#ifdef UBSEC_RNDTEST 94#include <dev/rndtest/rndtest.h> 95#endif 96#include <dev/ubsec/ubsecreg.h> 97#include <dev/ubsec/ubsecvar.h> 98 99/* 100 * Prototypes and count for the pci_device structure 101 */ 102static int ubsec_probe(device_t); 103static int ubsec_attach(device_t); 104static int ubsec_detach(device_t); 105static int ubsec_suspend(device_t); 106static int ubsec_resume(device_t); 107static void ubsec_shutdown(device_t); 108 109static device_method_t ubsec_methods[] = { 110 /* Device interface */ 111 DEVMETHOD(device_probe, ubsec_probe), 112 DEVMETHOD(device_attach, ubsec_attach), 113 DEVMETHOD(device_detach, ubsec_detach), 114 DEVMETHOD(device_suspend, ubsec_suspend), 115 DEVMETHOD(device_resume, ubsec_resume), 116 DEVMETHOD(device_shutdown, ubsec_shutdown), 117 118 /* bus interface */ 119 DEVMETHOD(bus_print_child, bus_generic_print_child), 120 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 121 122 { 0, 0 } 123}; 124static driver_t ubsec_driver = { 125 "ubsec", 126 ubsec_methods, 127 sizeof (struct ubsec_softc) 128}; 129static devclass_t ubsec_devclass; 130 131DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0); 132MODULE_DEPEND(ubsec, crypto, 1, 1, 1); 133#ifdef UBSEC_RNDTEST 134MODULE_DEPEND(ubsec, rndtest, 1, 1, 1); 135#endif 136 137static void ubsec_intr(void *); 138static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *); 139static int ubsec_freesession(void *, u_int64_t); 140static int ubsec_process(void *, struct cryptop *, int); 141static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 142static void ubsec_feed(struct ubsec_softc *); 143static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 144static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 145static int ubsec_feed2(struct ubsec_softc *); 146static void ubsec_rng(void *); 147static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 148 struct ubsec_dma_alloc *, int); 149#define ubsec_dma_sync(_dma, _flags) \ 150 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 151static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 152static int ubsec_dmamap_aligned(struct ubsec_operand *op); 153 154static void ubsec_reset_board(struct ubsec_softc *sc); 155static void ubsec_init_board(struct ubsec_softc *sc); 156static void ubsec_init_pciregs(device_t dev); 157static void ubsec_totalreset(struct ubsec_softc *sc); 158 159static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q); 160 161static int ubsec_kprocess(void*, struct cryptkop *, int); 162static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int); 163static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int); 164static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int); 165static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 166static int ubsec_ksigbits(struct crparam *); 167static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 168static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 169 170SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters"); 171 172#ifdef UBSEC_DEBUG 173static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 174static void ubsec_dump_mcr(struct ubsec_mcr *); 175static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *); 176 177static int ubsec_debug = 0; 178SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug, 179 0, "control debugging msgs"); 180#endif 181 182#define READ_REG(sc,r) \ 183 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 184 185#define WRITE_REG(sc,reg,val) \ 186 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 187 188#define SWAP32(x) (x) = htole32(ntohl((x))) 189#define HTOLE32(x) (x) = htole32(x) 190 191struct ubsec_stats ubsecstats; 192SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats, 193 ubsec_stats, "driver statistics"); 194 195static int 196ubsec_probe(device_t dev) 197{ 198 if (pci_get_vendor(dev) == PCI_VENDOR_SUN && 199 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 || 200 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K)) 201 return (BUS_PROBE_DEFAULT); 202 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 203 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 || 204 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)) 205 return (BUS_PROBE_DEFAULT); 206 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 207 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 || 208 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 209 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 || 210 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 || 211 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 212 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 213 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 214 )) 215 return (BUS_PROBE_DEFAULT); 216 return (ENXIO); 217} 218 219static const char* 220ubsec_partname(struct ubsec_softc *sc) 221{ 222 /* XXX sprintf numbers when not decoded */ 223 switch (pci_get_vendor(sc->sc_dev)) { 224 case PCI_VENDOR_BROADCOM: 225 switch (pci_get_device(sc->sc_dev)) { 226 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801"; 227 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802"; 228 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805"; 229 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820"; 230 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821"; 231 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822"; 232 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823"; 233 } 234 return "Broadcom unknown-part"; 235 case PCI_VENDOR_BLUESTEEL: 236 switch (pci_get_device(sc->sc_dev)) { 237 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601"; 238 } 239 return "Bluesteel unknown-part"; 240 case PCI_VENDOR_SUN: 241 switch (pci_get_device(sc->sc_dev)) { 242 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821"; 243 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K"; 244 } 245 return "Sun unknown-part"; 246 } 247 return "Unknown-vendor unknown-part"; 248} 249 250static void 251default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 252{ 253 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 254} 255 256static int 257ubsec_attach(device_t dev) 258{ 259 struct ubsec_softc *sc = device_get_softc(dev); 260 struct ubsec_dma *dmap; 261 u_int32_t cmd, i; 262 int rid; 263 264 bzero(sc, sizeof (*sc)); 265 sc->sc_dev = dev; 266 267 SIMPLEQ_INIT(&sc->sc_queue); 268 SIMPLEQ_INIT(&sc->sc_qchip); 269 SIMPLEQ_INIT(&sc->sc_queue2); 270 SIMPLEQ_INIT(&sc->sc_qchip2); 271 SIMPLEQ_INIT(&sc->sc_q2free); 272 273 /* XXX handle power management */ 274 275 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; 276 277 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 278 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601) 279 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 280 281 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 282 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 283 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805)) 284 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 285 286 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 287 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820) 288 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 289 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 290 291 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 292 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 293 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 294 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) || 295 (pci_get_vendor(dev) == PCI_VENDOR_SUN && 296 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K || 297 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) { 298 /* NB: the 5821/5822 defines some additional status bits */ 299 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY | 300 BS_STAT_MCR2_ALLEMPTY; 301 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 302 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 303 } 304 305 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 306 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 307 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 308 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 309 310 if (!(cmd & PCIM_CMD_MEMEN)) { 311 device_printf(dev, "failed to enable memory mapping\n"); 312 goto bad; 313 } 314 315 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 316 device_printf(dev, "failed to enable bus mastering\n"); 317 goto bad; 318 } 319 320 /* 321 * Setup memory-mapping of PCI registers. 322 */ 323 rid = BS_BAR; 324 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 325 RF_ACTIVE); 326 if (sc->sc_sr == NULL) { 327 device_printf(dev, "cannot map register space\n"); 328 goto bad; 329 } 330 sc->sc_st = rman_get_bustag(sc->sc_sr); 331 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 332 333 /* 334 * Arrange interrupt line. 335 */ 336 rid = 0; 337 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 338 RF_SHAREABLE|RF_ACTIVE); 339 if (sc->sc_irq == NULL) { 340 device_printf(dev, "could not map interrupt\n"); 341 goto bad1; 342 } 343 /* 344 * NB: Network code assumes we are blocked with splimp() 345 * so make sure the IRQ is mapped appropriately. 346 */ 347 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 348 ubsec_intr, sc, &sc->sc_ih)) { 349 device_printf(dev, "could not establish interrupt\n"); 350 goto bad2; 351 } 352 353 sc->sc_cid = crypto_get_driverid(0); 354 if (sc->sc_cid < 0) { 355 device_printf(dev, "could not get crypto driver id\n"); 356 goto bad3; 357 } 358 359 /* 360 * Setup DMA descriptor area. 361 */ 362 if (bus_dma_tag_create(NULL, /* parent */ 363 1, 0, /* alignment, bounds */ 364 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 365 BUS_SPACE_MAXADDR, /* highaddr */ 366 NULL, NULL, /* filter, filterarg */ 367 0x3ffff, /* maxsize */ 368 UBS_MAX_SCATTER, /* nsegments */ 369 0xffff, /* maxsegsize */ 370 BUS_DMA_ALLOCNOW, /* flags */ 371 NULL, NULL, /* lockfunc, lockarg */ 372 &sc->sc_dmat)) { 373 device_printf(dev, "cannot allocate DMA tag\n"); 374 goto bad4; 375 } 376 SIMPLEQ_INIT(&sc->sc_freequeue); 377 dmap = sc->sc_dmaa; 378 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 379 struct ubsec_q *q; 380 381 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 382 M_DEVBUF, M_NOWAIT); 383 if (q == NULL) { 384 device_printf(dev, "cannot allocate queue buffers\n"); 385 break; 386 } 387 388 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 389 &dmap->d_alloc, 0)) { 390 device_printf(dev, "cannot allocate dma buffers\n"); 391 free(q, M_DEVBUF); 392 break; 393 } 394 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 395 396 q->q_dma = dmap; 397 sc->sc_queuea[i] = q; 398 399 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 400 } 401 mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev), 402 "mcr1 operations", MTX_DEF); 403 mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev), 404 "mcr1 free q", MTX_DEF); 405 406 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc)); 407 408 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 409 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 410 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 411 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 412 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 413 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 414 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 415 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 416 417 /* 418 * Reset Broadcom chip 419 */ 420 ubsec_reset_board(sc); 421 422 /* 423 * Init Broadcom specific PCI settings 424 */ 425 ubsec_init_pciregs(dev); 426 427 /* 428 * Init Broadcom chip 429 */ 430 ubsec_init_board(sc); 431 432#ifndef UBSEC_NO_RNG 433 if (sc->sc_flags & UBS_FLAGS_RNG) { 434 sc->sc_statmask |= BS_STAT_MCR2_DONE; 435#ifdef UBSEC_RNDTEST 436 sc->sc_rndtest = rndtest_attach(dev); 437 if (sc->sc_rndtest) 438 sc->sc_harvest = rndtest_harvest; 439 else 440 sc->sc_harvest = default_harvest; 441#else 442 sc->sc_harvest = default_harvest; 443#endif 444 445 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 446 &sc->sc_rng.rng_q.q_mcr, 0)) 447 goto skip_rng; 448 449 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 450 &sc->sc_rng.rng_q.q_ctx, 0)) { 451 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 452 goto skip_rng; 453 } 454 455 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 456 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 457 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 458 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 459 goto skip_rng; 460 } 461 462 if (hz >= 100) 463 sc->sc_rnghz = hz / 100; 464 else 465 sc->sc_rnghz = 1; 466 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 467 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 468skip_rng: 469 ; 470 } 471#endif /* UBSEC_NO_RNG */ 472 mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev), 473 "mcr2 operations", MTX_DEF); 474 475 if (sc->sc_flags & UBS_FLAGS_KEY) { 476 sc->sc_statmask |= BS_STAT_MCR2_DONE; 477 478 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 479 ubsec_kprocess, sc); 480#if 0 481 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 482 ubsec_kprocess, sc); 483#endif 484 } 485 return (0); 486bad4: 487 crypto_unregister_all(sc->sc_cid); 488bad3: 489 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 490bad2: 491 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 492bad1: 493 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 494bad: 495 return (ENXIO); 496} 497 498/* 499 * Detach a device that successfully probed. 500 */ 501static int 502ubsec_detach(device_t dev) 503{ 504 struct ubsec_softc *sc = device_get_softc(dev); 505 506 /* XXX wait/abort active ops */ 507 508 /* disable interrupts */ 509 WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~ 510 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR)); 511 512 callout_stop(&sc->sc_rngto); 513 514 crypto_unregister_all(sc->sc_cid); 515 516#ifdef UBSEC_RNDTEST 517 if (sc->sc_rndtest) 518 rndtest_detach(sc->sc_rndtest); 519#endif 520 521 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 522 struct ubsec_q *q; 523 524 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 525 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next); 526 ubsec_dma_free(sc, &q->q_dma->d_alloc); 527 free(q, M_DEVBUF); 528 } 529 mtx_destroy(&sc->sc_mcr1lock); 530 mtx_destroy(&sc->sc_freeqlock); 531#ifndef UBSEC_NO_RNG 532 if (sc->sc_flags & UBS_FLAGS_RNG) { 533 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 534 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 535 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 536 } 537#endif /* UBSEC_NO_RNG */ 538 mtx_destroy(&sc->sc_mcr2lock); 539 540 bus_generic_detach(dev); 541 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 542 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 543 544 bus_dma_tag_destroy(sc->sc_dmat); 545 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 546 547 return (0); 548} 549 550/* 551 * Stop all chip i/o so that the kernel's probe routines don't 552 * get confused by errant DMAs when rebooting. 553 */ 554static void 555ubsec_shutdown(device_t dev) 556{ 557#ifdef notyet 558 ubsec_stop(device_get_softc(dev)); 559#endif 560} 561 562/* 563 * Device suspend routine. 564 */ 565static int 566ubsec_suspend(device_t dev) 567{ 568 struct ubsec_softc *sc = device_get_softc(dev); 569 570#ifdef notyet 571 /* XXX stop the device and save PCI settings */ 572#endif 573 sc->sc_suspended = 1; 574 575 return (0); 576} 577 578static int 579ubsec_resume(device_t dev) 580{ 581 struct ubsec_softc *sc = device_get_softc(dev); 582 583#ifdef notyet 584 /* XXX retore PCI settings and start the device */ 585#endif 586 sc->sc_suspended = 0; 587 return (0); 588} 589 590/* 591 * UBSEC Interrupt routine 592 */ 593static void 594ubsec_intr(void *arg) 595{ 596 struct ubsec_softc *sc = arg; 597 volatile u_int32_t stat; 598 struct ubsec_q *q; 599 struct ubsec_dma *dmap; 600 int npkts = 0, i; 601 602 stat = READ_REG(sc, BS_STAT); 603 stat &= sc->sc_statmask; 604 if (stat == 0) 605 return; 606 607 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 608 609 /* 610 * Check to see if we have any packets waiting for us 611 */ 612 if ((stat & BS_STAT_MCR1_DONE)) { 613 mtx_lock(&sc->sc_mcr1lock); 614 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 615 q = SIMPLEQ_FIRST(&sc->sc_qchip); 616 dmap = q->q_dma; 617 618 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 619 break; 620 621 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); 622 623 npkts = q->q_nstacked_mcrs; 624 sc->sc_nqchip -= 1+npkts; 625 /* 626 * search for further sc_qchip ubsec_q's that share 627 * the same MCR, and complete them too, they must be 628 * at the top. 629 */ 630 for (i = 0; i < npkts; i++) { 631 if(q->q_stacked_mcr[i]) { 632 ubsec_callback(sc, q->q_stacked_mcr[i]); 633 } else { 634 break; 635 } 636 } 637 ubsec_callback(sc, q); 638 } 639 /* 640 * Don't send any more packet to chip if there has been 641 * a DMAERR. 642 */ 643 if (!(stat & BS_STAT_DMAERR)) 644 ubsec_feed(sc); 645 mtx_unlock(&sc->sc_mcr1lock); 646 } 647 648 /* 649 * Check to see if we have any key setups/rng's waiting for us 650 */ 651 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 652 (stat & BS_STAT_MCR2_DONE)) { 653 struct ubsec_q2 *q2; 654 struct ubsec_mcr *mcr; 655 656 mtx_lock(&sc->sc_mcr2lock); 657 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 658 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 659 660 ubsec_dma_sync(&q2->q_mcr, 661 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 662 663 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 664 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 665 ubsec_dma_sync(&q2->q_mcr, 666 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 667 break; 668 } 669 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q_next); 670 ubsec_callback2(sc, q2); 671 /* 672 * Don't send any more packet to chip if there has been 673 * a DMAERR. 674 */ 675 if (!(stat & BS_STAT_DMAERR)) 676 ubsec_feed2(sc); 677 } 678 mtx_unlock(&sc->sc_mcr2lock); 679 } 680 681 /* 682 * Check to see if we got any DMA Error 683 */ 684 if (stat & BS_STAT_DMAERR) { 685#ifdef UBSEC_DEBUG 686 if (ubsec_debug) { 687 volatile u_int32_t a = READ_REG(sc, BS_ERR); 688 689 printf("dmaerr %s@%08x\n", 690 (a & BS_ERR_READ) ? "read" : "write", 691 a & BS_ERR_ADDR); 692 } 693#endif /* UBSEC_DEBUG */ 694 ubsecstats.hst_dmaerr++; 695 mtx_lock(&sc->sc_mcr1lock); 696 ubsec_totalreset(sc); 697 ubsec_feed(sc); 698 mtx_unlock(&sc->sc_mcr1lock); 699 } 700 701 if (sc->sc_needwakeup) { /* XXX check high watermark */ 702 int wakeup; 703 704 mtx_lock(&sc->sc_freeqlock); 705 wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 706#ifdef UBSEC_DEBUG 707 if (ubsec_debug) 708 device_printf(sc->sc_dev, "wakeup crypto (%x)\n", 709 sc->sc_needwakeup); 710#endif /* UBSEC_DEBUG */ 711 sc->sc_needwakeup &= ~wakeup; 712 mtx_unlock(&sc->sc_freeqlock); 713 crypto_unblock(sc->sc_cid, wakeup); 714 } 715} 716 717/* 718 * ubsec_feed() - aggregate and post requests to chip 719 */ 720static void 721ubsec_feed(struct ubsec_softc *sc) 722{ 723 struct ubsec_q *q, *q2; 724 int npkts, i; 725 void *v; 726 u_int32_t stat; 727 728 /* 729 * Decide how many ops to combine in a single MCR. We cannot 730 * aggregate more than UBS_MAX_AGGR because this is the number 731 * of slots defined in the data structure. Note that 732 * aggregation only happens if ops are marked batch'able. 733 * Aggregating ops reduces the number of interrupts to the host 734 * but also (potentially) increases the latency for processing 735 * completed ops as we only get an interrupt when all aggregated 736 * ops have completed. 737 */ 738 if (sc->sc_nqueue == 0) 739 return; 740 if (sc->sc_nqueue > 1) { 741 npkts = 0; 742 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) { 743 npkts++; 744 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0) 745 break; 746 } 747 } else 748 npkts = 1; 749 /* 750 * Check device status before going any further. 751 */ 752 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 753 if (stat & BS_STAT_DMAERR) { 754 ubsec_totalreset(sc); 755 ubsecstats.hst_dmaerr++; 756 } else 757 ubsecstats.hst_mcr1full++; 758 return; 759 } 760 if (sc->sc_nqueue > ubsecstats.hst_maxqueue) 761 ubsecstats.hst_maxqueue = sc->sc_nqueue; 762 if (npkts > UBS_MAX_AGGR) 763 npkts = UBS_MAX_AGGR; 764 if (npkts < 2) /* special case 1 op */ 765 goto feed1; 766 767 ubsecstats.hst_totbatch += npkts-1; 768#ifdef UBSEC_DEBUG 769 if (ubsec_debug) 770 printf("merging %d records\n", npkts); 771#endif /* UBSEC_DEBUG */ 772 773 q = SIMPLEQ_FIRST(&sc->sc_queue); 774 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); 775 --sc->sc_nqueue; 776 777 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 778 if (q->q_dst_map != NULL) 779 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 780 781 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 782 783 for (i = 0; i < q->q_nstacked_mcrs; i++) { 784 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 785 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 786 BUS_DMASYNC_PREWRITE); 787 if (q2->q_dst_map != NULL) 788 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 789 BUS_DMASYNC_PREREAD); 790 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); 791 --sc->sc_nqueue; 792 793 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - 794 sizeof(struct ubsec_mcr_add)); 795 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 796 q->q_stacked_mcr[i] = q2; 797 } 798 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 799 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 800 sc->sc_nqchip += npkts; 801 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 802 ubsecstats.hst_maxqchip = sc->sc_nqchip; 803 ubsec_dma_sync(&q->q_dma->d_alloc, 804 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 805 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 806 offsetof(struct ubsec_dmachunk, d_mcr)); 807 return; 808feed1: 809 q = SIMPLEQ_FIRST(&sc->sc_queue); 810 811 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 812 if (q->q_dst_map != NULL) 813 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 814 ubsec_dma_sync(&q->q_dma->d_alloc, 815 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 816 817 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 818 offsetof(struct ubsec_dmachunk, d_mcr)); 819#ifdef UBSEC_DEBUG 820 if (ubsec_debug) 821 printf("feed1: q->chip %p %08x stat %08x\n", 822 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr), 823 stat); 824#endif /* UBSEC_DEBUG */ 825 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); 826 --sc->sc_nqueue; 827 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 828 sc->sc_nqchip++; 829 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 830 ubsecstats.hst_maxqchip = sc->sc_nqchip; 831 return; 832} 833 834static void 835ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key) 836{ 837 838 /* Go ahead and compute key in ubsec's byte order */ 839 if (algo == CRYPTO_DES_CBC) { 840 bcopy(key, &ses->ses_deskey[0], 8); 841 bcopy(key, &ses->ses_deskey[2], 8); 842 bcopy(key, &ses->ses_deskey[4], 8); 843 } else 844 bcopy(key, ses->ses_deskey, 24); 845 846 SWAP32(ses->ses_deskey[0]); 847 SWAP32(ses->ses_deskey[1]); 848 SWAP32(ses->ses_deskey[2]); 849 SWAP32(ses->ses_deskey[3]); 850 SWAP32(ses->ses_deskey[4]); 851 SWAP32(ses->ses_deskey[5]); 852} 853 854static void 855ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen) 856{ 857 MD5_CTX md5ctx; 858 SHA1_CTX sha1ctx; 859 int i; 860 861 for (i = 0; i < klen; i++) 862 key[i] ^= HMAC_IPAD_VAL; 863 864 if (algo == CRYPTO_MD5_HMAC) { 865 MD5Init(&md5ctx); 866 MD5Update(&md5ctx, key, klen); 867 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); 868 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state)); 869 } else { 870 SHA1Init(&sha1ctx); 871 SHA1Update(&sha1ctx, key, klen); 872 SHA1Update(&sha1ctx, hmac_ipad_buffer, 873 SHA1_HMAC_BLOCK_LEN - klen); 874 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); 875 } 876 877 for (i = 0; i < klen; i++) 878 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 879 880 if (algo == CRYPTO_MD5_HMAC) { 881 MD5Init(&md5ctx); 882 MD5Update(&md5ctx, key, klen); 883 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); 884 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state)); 885 } else { 886 SHA1Init(&sha1ctx); 887 SHA1Update(&sha1ctx, key, klen); 888 SHA1Update(&sha1ctx, hmac_opad_buffer, 889 SHA1_HMAC_BLOCK_LEN - klen); 890 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); 891 } 892 893 for (i = 0; i < klen; i++) 894 key[i] ^= HMAC_OPAD_VAL; 895} 896 897/* 898 * Allocate a new 'session' and return an encoded session id. 'sidp' 899 * contains our registration id, and should contain an encoded session 900 * id on successful allocation. 901 */ 902static int 903ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 904{ 905 struct cryptoini *c, *encini = NULL, *macini = NULL; 906 struct ubsec_softc *sc = arg; 907 struct ubsec_session *ses = NULL; 908 int sesn; 909 910 if (sidp == NULL || cri == NULL || sc == NULL) 911 return (EINVAL); 912 913 for (c = cri; c != NULL; c = c->cri_next) { 914 if (c->cri_alg == CRYPTO_MD5_HMAC || 915 c->cri_alg == CRYPTO_SHA1_HMAC) { 916 if (macini) 917 return (EINVAL); 918 macini = c; 919 } else if (c->cri_alg == CRYPTO_DES_CBC || 920 c->cri_alg == CRYPTO_3DES_CBC) { 921 if (encini) 922 return (EINVAL); 923 encini = c; 924 } else 925 return (EINVAL); 926 } 927 if (encini == NULL && macini == NULL) 928 return (EINVAL); 929 930 if (sc->sc_sessions == NULL) { 931 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 932 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 933 if (ses == NULL) 934 return (ENOMEM); 935 sesn = 0; 936 sc->sc_nsessions = 1; 937 } else { 938 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 939 if (sc->sc_sessions[sesn].ses_used == 0) { 940 ses = &sc->sc_sessions[sesn]; 941 break; 942 } 943 } 944 945 if (ses == NULL) { 946 sesn = sc->sc_nsessions; 947 ses = (struct ubsec_session *)malloc((sesn + 1) * 948 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 949 if (ses == NULL) 950 return (ENOMEM); 951 bcopy(sc->sc_sessions, ses, sesn * 952 sizeof(struct ubsec_session)); 953 bzero(sc->sc_sessions, sesn * 954 sizeof(struct ubsec_session)); 955 free(sc->sc_sessions, M_DEVBUF); 956 sc->sc_sessions = ses; 957 ses = &sc->sc_sessions[sesn]; 958 sc->sc_nsessions++; 959 } 960 } 961 bzero(ses, sizeof(struct ubsec_session)); 962 ses->ses_used = 1; 963 964 if (encini) { 965 /* get an IV, network byte order */ 966 /* XXX may read fewer than requested */ 967 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 968 969 if (encini->cri_key != NULL) { 970 ubsec_setup_enckey(ses, encini->cri_alg, 971 encini->cri_key); 972 } 973 } 974 975 if (macini) { 976 ses->ses_mlen = macini->cri_mlen; 977 if (ses->ses_mlen == 0) { 978 if (macini->cri_alg == CRYPTO_MD5_HMAC) 979 ses->ses_mlen = MD5_HASH_LEN; 980 else 981 ses->ses_mlen = SHA1_HASH_LEN; 982 } 983 984 if (macini->cri_key != NULL) { 985 ubsec_setup_mackey(ses, macini->cri_alg, 986 macini->cri_key, macini->cri_klen / 8); 987 } 988 } 989 990 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); 991 return (0); 992} 993 994/* 995 * Deallocate a session. 996 */ 997static int 998ubsec_freesession(void *arg, u_int64_t tid) 999{ 1000 struct ubsec_softc *sc = arg; 1001 int session, ret; 1002 u_int32_t sid = CRYPTO_SESID2LID(tid); 1003 1004 if (sc == NULL) 1005 return (EINVAL); 1006 1007 session = UBSEC_SESSION(sid); 1008 if (session < sc->sc_nsessions) { 1009 bzero(&sc->sc_sessions[session], 1010 sizeof(sc->sc_sessions[session])); 1011 ret = 0; 1012 } else 1013 ret = EINVAL; 1014 1015 return (ret); 1016} 1017 1018static void 1019ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1020{ 1021 struct ubsec_operand *op = arg; 1022 1023 KASSERT(nsegs <= UBS_MAX_SCATTER, 1024 ("Too many DMA segments returned when mapping operand")); 1025#ifdef UBSEC_DEBUG 1026 if (ubsec_debug) 1027 printf("ubsec_op_cb: mapsize %u nsegs %d error %d\n", 1028 (u_int) mapsize, nsegs, error); 1029#endif 1030 if (error != 0) 1031 return; 1032 op->mapsize = mapsize; 1033 op->nsegs = nsegs; 1034 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1035} 1036 1037static int 1038ubsec_process(void *arg, struct cryptop *crp, int hint) 1039{ 1040 struct ubsec_q *q = NULL; 1041 int err = 0, i, j, nicealign; 1042 struct ubsec_softc *sc = arg; 1043 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1044 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1045 int sskip, dskip, stheend, dtheend; 1046 int16_t coffset; 1047 struct ubsec_session *ses; 1048 struct ubsec_pktctx ctx; 1049 struct ubsec_dma *dmap = NULL; 1050 1051 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1052 ubsecstats.hst_invalid++; 1053 return (EINVAL); 1054 } 1055 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1056 ubsecstats.hst_badsession++; 1057 return (EINVAL); 1058 } 1059 1060 mtx_lock(&sc->sc_freeqlock); 1061 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1062 ubsecstats.hst_queuefull++; 1063 sc->sc_needwakeup |= CRYPTO_SYMQ; 1064 mtx_unlock(&sc->sc_freeqlock); 1065 return (ERESTART); 1066 } 1067 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1068 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next); 1069 mtx_unlock(&sc->sc_freeqlock); 1070 1071 dmap = q->q_dma; /* Save dma pointer */ 1072 bzero(q, sizeof(struct ubsec_q)); 1073 bzero(&ctx, sizeof(ctx)); 1074 1075 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1076 q->q_dma = dmap; 1077 ses = &sc->sc_sessions[q->q_sesn]; 1078 1079 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1080 q->q_src_m = (struct mbuf *)crp->crp_buf; 1081 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1082 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1083 q->q_src_io = (struct uio *)crp->crp_buf; 1084 q->q_dst_io = (struct uio *)crp->crp_buf; 1085 } else { 1086 ubsecstats.hst_badflags++; 1087 err = EINVAL; 1088 goto errout; /* XXX we don't handle contiguous blocks! */ 1089 } 1090 1091 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 1092 1093 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1094 dmap->d_dma->d_mcr.mcr_flags = 0; 1095 q->q_crp = crp; 1096 1097 crd1 = crp->crp_desc; 1098 if (crd1 == NULL) { 1099 ubsecstats.hst_nodesc++; 1100 err = EINVAL; 1101 goto errout; 1102 } 1103 crd2 = crd1->crd_next; 1104 1105 if (crd2 == NULL) { 1106 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 1107 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 1108 maccrd = crd1; 1109 enccrd = NULL; 1110 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1111 crd1->crd_alg == CRYPTO_3DES_CBC) { 1112 maccrd = NULL; 1113 enccrd = crd1; 1114 } else { 1115 ubsecstats.hst_badalg++; 1116 err = EINVAL; 1117 goto errout; 1118 } 1119 } else { 1120 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1121 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1122 (crd2->crd_alg == CRYPTO_DES_CBC || 1123 crd2->crd_alg == CRYPTO_3DES_CBC) && 1124 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1125 maccrd = crd1; 1126 enccrd = crd2; 1127 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1128 crd1->crd_alg == CRYPTO_3DES_CBC) && 1129 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1130 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1131 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1132 enccrd = crd1; 1133 maccrd = crd2; 1134 } else { 1135 /* 1136 * We cannot order the ubsec as requested 1137 */ 1138 ubsecstats.hst_badalg++; 1139 err = EINVAL; 1140 goto errout; 1141 } 1142 } 1143 1144 if (enccrd) { 1145 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1146 ubsec_setup_enckey(ses, enccrd->crd_alg, 1147 enccrd->crd_key); 1148 } 1149 1150 encoffset = enccrd->crd_skip; 1151 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1152 1153 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1154 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1155 1156 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1157 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1158 else { 1159 ctx.pc_iv[0] = ses->ses_iv[0]; 1160 ctx.pc_iv[1] = ses->ses_iv[1]; 1161 } 1162 1163 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1164 crypto_copyback(crp->crp_flags, crp->crp_buf, 1165 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv); 1166 } 1167 } else { 1168 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1169 1170 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1171 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1172 else { 1173 crypto_copydata(crp->crp_flags, crp->crp_buf, 1174 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv); 1175 } 1176 } 1177 1178 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1179 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1180 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1181 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1182 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1183 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1184 SWAP32(ctx.pc_iv[0]); 1185 SWAP32(ctx.pc_iv[1]); 1186 } 1187 1188 if (maccrd) { 1189 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1190 ubsec_setup_mackey(ses, maccrd->crd_alg, 1191 maccrd->crd_key, maccrd->crd_klen / 8); 1192 } 1193 1194 macoffset = maccrd->crd_skip; 1195 1196 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1197 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1198 else 1199 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1200 1201 for (i = 0; i < 5; i++) { 1202 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1203 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1204 1205 HTOLE32(ctx.pc_hminner[i]); 1206 HTOLE32(ctx.pc_hmouter[i]); 1207 } 1208 } 1209 1210 if (enccrd && maccrd) { 1211 /* 1212 * ubsec cannot handle packets where the end of encryption 1213 * and authentication are not the same, or where the 1214 * encrypted part begins before the authenticated part. 1215 */ 1216 if ((encoffset + enccrd->crd_len) != 1217 (macoffset + maccrd->crd_len)) { 1218 ubsecstats.hst_lenmismatch++; 1219 err = EINVAL; 1220 goto errout; 1221 } 1222 if (enccrd->crd_skip < maccrd->crd_skip) { 1223 ubsecstats.hst_skipmismatch++; 1224 err = EINVAL; 1225 goto errout; 1226 } 1227 sskip = maccrd->crd_skip; 1228 cpskip = dskip = enccrd->crd_skip; 1229 stheend = maccrd->crd_len; 1230 dtheend = enccrd->crd_len; 1231 coffset = enccrd->crd_skip - maccrd->crd_skip; 1232 cpoffset = cpskip + dtheend; 1233#ifdef UBSEC_DEBUG 1234 if (ubsec_debug) { 1235 printf("mac: skip %d, len %d, inject %d\n", 1236 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1237 printf("enc: skip %d, len %d, inject %d\n", 1238 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1239 printf("src: skip %d, len %d\n", sskip, stheend); 1240 printf("dst: skip %d, len %d\n", dskip, dtheend); 1241 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1242 coffset, stheend, cpskip, cpoffset); 1243 } 1244#endif 1245 } else { 1246 cpskip = dskip = sskip = macoffset + encoffset; 1247 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1248 cpoffset = cpskip + dtheend; 1249 coffset = 0; 1250 } 1251 ctx.pc_offset = htole16(coffset >> 2); 1252 1253 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) { 1254 ubsecstats.hst_nomap++; 1255 err = ENOMEM; 1256 goto errout; 1257 } 1258 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1259 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1260 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1261 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1262 q->q_src_map = NULL; 1263 ubsecstats.hst_noload++; 1264 err = ENOMEM; 1265 goto errout; 1266 } 1267 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1268 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1269 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1270 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1271 q->q_src_map = NULL; 1272 ubsecstats.hst_noload++; 1273 err = ENOMEM; 1274 goto errout; 1275 } 1276 } 1277 nicealign = ubsec_dmamap_aligned(&q->q_src); 1278 1279 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1280 1281#ifdef UBSEC_DEBUG 1282 if (ubsec_debug) 1283 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1284#endif 1285 for (i = j = 0; i < q->q_src_nsegs; i++) { 1286 struct ubsec_pktbuf *pb; 1287 bus_size_t packl = q->q_src_segs[i].ds_len; 1288 bus_addr_t packp = q->q_src_segs[i].ds_addr; 1289 1290 if (sskip >= packl) { 1291 sskip -= packl; 1292 continue; 1293 } 1294 1295 packl -= sskip; 1296 packp += sskip; 1297 sskip = 0; 1298 1299 if (packl > 0xfffc) { 1300 err = EIO; 1301 goto errout; 1302 } 1303 1304 if (j == 0) 1305 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1306 else 1307 pb = &dmap->d_dma->d_sbuf[j - 1]; 1308 1309 pb->pb_addr = htole32(packp); 1310 1311 if (stheend) { 1312 if (packl > stheend) { 1313 pb->pb_len = htole32(stheend); 1314 stheend = 0; 1315 } else { 1316 pb->pb_len = htole32(packl); 1317 stheend -= packl; 1318 } 1319 } else 1320 pb->pb_len = htole32(packl); 1321 1322 if ((i + 1) == q->q_src_nsegs) 1323 pb->pb_next = 0; 1324 else 1325 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1326 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1327 j++; 1328 } 1329 1330 if (enccrd == NULL && maccrd != NULL) { 1331 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1332 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1333 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1334 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1335#ifdef UBSEC_DEBUG 1336 if (ubsec_debug) 1337 printf("opkt: %x %x %x\n", 1338 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1339 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1340 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1341#endif 1342 } else { 1343 if (crp->crp_flags & CRYPTO_F_IOV) { 1344 if (!nicealign) { 1345 ubsecstats.hst_iovmisaligned++; 1346 err = EINVAL; 1347 goto errout; 1348 } 1349 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1350 &q->q_dst_map)) { 1351 ubsecstats.hst_nomap++; 1352 err = ENOMEM; 1353 goto errout; 1354 } 1355 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1356 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) { 1357 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1358 q->q_dst_map = NULL; 1359 ubsecstats.hst_noload++; 1360 err = ENOMEM; 1361 goto errout; 1362 } 1363 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1364 if (nicealign) { 1365 q->q_dst = q->q_src; 1366 } else { 1367 int totlen, len; 1368 struct mbuf *m, *top, **mp; 1369 1370 ubsecstats.hst_unaligned++; 1371 totlen = q->q_src_mapsize; 1372 if (totlen >= MINCLSIZE) { 1373 m = m_getcl(M_DONTWAIT, MT_DATA, 1374 q->q_src_m->m_flags & M_PKTHDR); 1375 len = MCLBYTES; 1376 } else if (q->q_src_m->m_flags & M_PKTHDR) { 1377 m = m_gethdr(M_DONTWAIT, MT_DATA); 1378 len = MHLEN; 1379 } else { 1380 m = m_get(M_DONTWAIT, MT_DATA); 1381 len = MLEN; 1382 } 1383 if (m && q->q_src_m->m_flags & M_PKTHDR && 1384 !m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)) { 1385 m_free(m); 1386 m = NULL; 1387 } 1388 if (m == NULL) { 1389 ubsecstats.hst_nombuf++; 1390 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1391 goto errout; 1392 } 1393 m->m_len = len = min(totlen, len); 1394 totlen -= len; 1395 top = m; 1396 mp = ⊤ 1397 1398 while (totlen > 0) { 1399 if (totlen >= MINCLSIZE) { 1400 m = m_getcl(M_DONTWAIT, 1401 MT_DATA, 0); 1402 len = MCLBYTES; 1403 } else { 1404 m = m_get(M_DONTWAIT, MT_DATA); 1405 len = MLEN; 1406 } 1407 if (m == NULL) { 1408 m_freem(top); 1409 ubsecstats.hst_nombuf++; 1410 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1411 goto errout; 1412 } 1413 m->m_len = len = min(totlen, len); 1414 totlen -= len; 1415 *mp = m; 1416 mp = &m->m_next; 1417 } 1418 q->q_dst_m = top; 1419 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1420 cpskip, cpoffset); 1421 if (bus_dmamap_create(sc->sc_dmat, 1422 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) { 1423 ubsecstats.hst_nomap++; 1424 err = ENOMEM; 1425 goto errout; 1426 } 1427 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1428 q->q_dst_map, q->q_dst_m, 1429 ubsec_op_cb, &q->q_dst, 1430 BUS_DMA_NOWAIT) != 0) { 1431 bus_dmamap_destroy(sc->sc_dmat, 1432 q->q_dst_map); 1433 q->q_dst_map = NULL; 1434 ubsecstats.hst_noload++; 1435 err = ENOMEM; 1436 goto errout; 1437 } 1438 } 1439 } else { 1440 ubsecstats.hst_badflags++; 1441 err = EINVAL; 1442 goto errout; 1443 } 1444 1445#ifdef UBSEC_DEBUG 1446 if (ubsec_debug) 1447 printf("dst skip: %d\n", dskip); 1448#endif 1449 for (i = j = 0; i < q->q_dst_nsegs; i++) { 1450 struct ubsec_pktbuf *pb; 1451 bus_size_t packl = q->q_dst_segs[i].ds_len; 1452 bus_addr_t packp = q->q_dst_segs[i].ds_addr; 1453 1454 if (dskip >= packl) { 1455 dskip -= packl; 1456 continue; 1457 } 1458 1459 packl -= dskip; 1460 packp += dskip; 1461 dskip = 0; 1462 1463 if (packl > 0xfffc) { 1464 err = EIO; 1465 goto errout; 1466 } 1467 1468 if (j == 0) 1469 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1470 else 1471 pb = &dmap->d_dma->d_dbuf[j - 1]; 1472 1473 pb->pb_addr = htole32(packp); 1474 1475 if (dtheend) { 1476 if (packl > dtheend) { 1477 pb->pb_len = htole32(dtheend); 1478 dtheend = 0; 1479 } else { 1480 pb->pb_len = htole32(packl); 1481 dtheend -= packl; 1482 } 1483 } else 1484 pb->pb_len = htole32(packl); 1485 1486 if ((i + 1) == q->q_dst_nsegs) { 1487 if (maccrd) 1488 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1489 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1490 else 1491 pb->pb_next = 0; 1492 } else 1493 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1494 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1495 j++; 1496 } 1497 } 1498 1499 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1500 offsetof(struct ubsec_dmachunk, d_ctx)); 1501 1502 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1503 struct ubsec_pktctx_long *ctxl; 1504 1505 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr + 1506 offsetof(struct ubsec_dmachunk, d_ctx)); 1507 1508 /* transform small context into long context */ 1509 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1510 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1511 ctxl->pc_flags = ctx.pc_flags; 1512 ctxl->pc_offset = ctx.pc_offset; 1513 for (i = 0; i < 6; i++) 1514 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1515 for (i = 0; i < 5; i++) 1516 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1517 for (i = 0; i < 5; i++) 1518 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1519 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1520 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1521 } else 1522 bcopy(&ctx, dmap->d_alloc.dma_vaddr + 1523 offsetof(struct ubsec_dmachunk, d_ctx), 1524 sizeof(struct ubsec_pktctx)); 1525 1526 mtx_lock(&sc->sc_mcr1lock); 1527 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1528 sc->sc_nqueue++; 1529 ubsecstats.hst_ipackets++; 1530 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size; 1531 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR) 1532 ubsec_feed(sc); 1533 mtx_unlock(&sc->sc_mcr1lock); 1534 return (0); 1535 1536errout: 1537 if (q != NULL) { 1538 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1539 m_freem(q->q_dst_m); 1540 1541 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1542 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1543 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1544 } 1545 if (q->q_src_map != NULL) { 1546 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1547 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1548 } 1549 } 1550 if (q != NULL || err == ERESTART) { 1551 mtx_lock(&sc->sc_freeqlock); 1552 if (q != NULL) 1553 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1554 if (err == ERESTART) 1555 sc->sc_needwakeup |= CRYPTO_SYMQ; 1556 mtx_unlock(&sc->sc_freeqlock); 1557 } 1558 if (err != ERESTART) { 1559 crp->crp_etype = err; 1560 crypto_done(crp); 1561 } 1562 return (err); 1563} 1564 1565static void 1566ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1567{ 1568 struct cryptop *crp = (struct cryptop *)q->q_crp; 1569 struct cryptodesc *crd; 1570 struct ubsec_dma *dmap = q->q_dma; 1571 1572 ubsecstats.hst_opackets++; 1573 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1574 1575 ubsec_dma_sync(&dmap->d_alloc, 1576 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1577 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1578 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1579 BUS_DMASYNC_POSTREAD); 1580 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1581 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1582 } 1583 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE); 1584 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1585 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1586 1587 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1588 m_freem(q->q_src_m); 1589 crp->crp_buf = (caddr_t)q->q_dst_m; 1590 } 1591 1592 /* copy out IV for future use */ 1593 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1594 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1595 if (crd->crd_alg != CRYPTO_DES_CBC && 1596 crd->crd_alg != CRYPTO_3DES_CBC) 1597 continue; 1598 crypto_copydata(crp->crp_flags, crp->crp_buf, 1599 crd->crd_skip + crd->crd_len - 8, 8, 1600 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1601 break; 1602 } 1603 } 1604 1605 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1606 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1607 crd->crd_alg != CRYPTO_SHA1_HMAC) 1608 continue; 1609 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, 1610 sc->sc_sessions[q->q_sesn].ses_mlen, 1611 (caddr_t)dmap->d_dma->d_macbuf); 1612 break; 1613 } 1614 mtx_lock(&sc->sc_freeqlock); 1615 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1616 mtx_unlock(&sc->sc_freeqlock); 1617 crypto_done(crp); 1618} 1619 1620static void 1621ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1622{ 1623 int i, j, dlen, slen; 1624 caddr_t dptr, sptr; 1625 1626 j = 0; 1627 sptr = srcm->m_data; 1628 slen = srcm->m_len; 1629 dptr = dstm->m_data; 1630 dlen = dstm->m_len; 1631 1632 while (1) { 1633 for (i = 0; i < min(slen, dlen); i++) { 1634 if (j < hoffset || j >= toffset) 1635 *dptr++ = *sptr++; 1636 slen--; 1637 dlen--; 1638 j++; 1639 } 1640 if (slen == 0) { 1641 srcm = srcm->m_next; 1642 if (srcm == NULL) 1643 return; 1644 sptr = srcm->m_data; 1645 slen = srcm->m_len; 1646 } 1647 if (dlen == 0) { 1648 dstm = dstm->m_next; 1649 if (dstm == NULL) 1650 return; 1651 dptr = dstm->m_data; 1652 dlen = dstm->m_len; 1653 } 1654 } 1655} 1656 1657/* 1658 * feed the key generator, must be called at splimp() or higher. 1659 */ 1660static int 1661ubsec_feed2(struct ubsec_softc *sc) 1662{ 1663 struct ubsec_q2 *q; 1664 1665 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1666 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1667 break; 1668 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1669 1670 ubsec_dma_sync(&q->q_mcr, 1671 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1672 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE); 1673 1674 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1675 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q_next); 1676 --sc->sc_nqueue2; 1677 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1678 } 1679 return (0); 1680} 1681 1682/* 1683 * Callback for handling random numbers 1684 */ 1685static void 1686ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1687{ 1688 struct cryptkop *krp; 1689 struct ubsec_ctx_keyop *ctx; 1690 1691 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1692 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE); 1693 1694 switch (q->q_type) { 1695#ifndef UBSEC_NO_RNG 1696 case UBS_CTXOP_RNGBYPASS: { 1697 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1698 1699 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD); 1700 (*sc->sc_harvest)(sc->sc_rndtest, 1701 rng->rng_buf.dma_vaddr, 1702 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t)); 1703 rng->rng_used = 0; 1704 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1705 break; 1706 } 1707#endif 1708 case UBS_CTXOP_MODEXP: { 1709 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1710 u_int rlen, clen; 1711 1712 krp = me->me_krp; 1713 rlen = (me->me_modbits + 7) / 8; 1714 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1715 1716 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE); 1717 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE); 1718 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD); 1719 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE); 1720 1721 if (clen < rlen) 1722 krp->krp_status = E2BIG; 1723 else { 1724 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1725 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1726 (krp->krp_param[krp->krp_iparams].crp_nbits 1727 + 7) / 8); 1728 bcopy(me->me_C.dma_vaddr, 1729 krp->krp_param[krp->krp_iparams].crp_p, 1730 (me->me_modbits + 7) / 8); 1731 } else 1732 ubsec_kshift_l(me->me_shiftbits, 1733 me->me_C.dma_vaddr, me->me_normbits, 1734 krp->krp_param[krp->krp_iparams].crp_p, 1735 krp->krp_param[krp->krp_iparams].crp_nbits); 1736 } 1737 1738 crypto_kdone(krp); 1739 1740 /* bzero all potentially sensitive data */ 1741 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1742 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1743 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1744 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1745 1746 /* Can't free here, so put us on the free list. */ 1747 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1748 break; 1749 } 1750 case UBS_CTXOP_RSAPRIV: { 1751 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1752 u_int len; 1753 1754 krp = rp->rpr_krp; 1755 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE); 1756 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD); 1757 1758 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1759 bcopy(rp->rpr_msgout.dma_vaddr, 1760 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1761 1762 crypto_kdone(krp); 1763 1764 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1765 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1766 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1767 1768 /* Can't free here, so put us on the free list. */ 1769 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1770 break; 1771 } 1772 default: 1773 device_printf(sc->sc_dev, "unknown ctx op: %x\n", 1774 letoh16(ctx->ctx_op)); 1775 break; 1776 } 1777} 1778 1779#ifndef UBSEC_NO_RNG 1780static void 1781ubsec_rng(void *vsc) 1782{ 1783 struct ubsec_softc *sc = vsc; 1784 struct ubsec_q2_rng *rng = &sc->sc_rng; 1785 struct ubsec_mcr *mcr; 1786 struct ubsec_ctx_rngbypass *ctx; 1787 1788 mtx_lock(&sc->sc_mcr2lock); 1789 if (rng->rng_used) { 1790 mtx_unlock(&sc->sc_mcr2lock); 1791 return; 1792 } 1793 sc->sc_nqueue2++; 1794 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1795 goto out; 1796 1797 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1798 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1799 1800 mcr->mcr_pkts = htole16(1); 1801 mcr->mcr_flags = 0; 1802 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1803 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1804 mcr->mcr_ipktbuf.pb_len = 0; 1805 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1806 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1807 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1808 UBS_PKTBUF_LEN); 1809 mcr->mcr_opktbuf.pb_next = 0; 1810 1811 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1812 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS); 1813 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS; 1814 1815 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD); 1816 1817 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1818 rng->rng_used = 1; 1819 ubsec_feed2(sc); 1820 ubsecstats.hst_rng++; 1821 mtx_unlock(&sc->sc_mcr2lock); 1822 1823 return; 1824 1825out: 1826 /* 1827 * Something weird happened, generate our own call back. 1828 */ 1829 sc->sc_nqueue2--; 1830 mtx_unlock(&sc->sc_mcr2lock); 1831 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1832} 1833#endif /* UBSEC_NO_RNG */ 1834 1835static void 1836ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1837{ 1838 bus_addr_t *paddr = (bus_addr_t*) arg; 1839 *paddr = segs->ds_addr; 1840} 1841 1842static int 1843ubsec_dma_malloc( 1844 struct ubsec_softc *sc, 1845 bus_size_t size, 1846 struct ubsec_dma_alloc *dma, 1847 int mapflags 1848) 1849{ 1850 int r; 1851 1852 /* XXX could specify sc_dmat as parent but that just adds overhead */ 1853 r = bus_dma_tag_create(NULL, /* parent */ 1854 1, 0, /* alignment, bounds */ 1855 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1856 BUS_SPACE_MAXADDR, /* highaddr */ 1857 NULL, NULL, /* filter, filterarg */ 1858 size, /* maxsize */ 1859 1, /* nsegments */ 1860 size, /* maxsegsize */ 1861 BUS_DMA_ALLOCNOW, /* flags */ 1862 NULL, NULL, /* lockfunc, lockarg */ 1863 &dma->dma_tag); 1864 if (r != 0) { 1865 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1866 "bus_dma_tag_create failed; error %u\n", r); 1867 goto fail_0; 1868 } 1869 1870 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1871 if (r != 0) { 1872 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1873 "bus_dmamap_create failed; error %u\n", r); 1874 goto fail_1; 1875 } 1876 1877 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1878 BUS_DMA_NOWAIT, &dma->dma_map); 1879 if (r != 0) { 1880 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1881 "bus_dmammem_alloc failed; size %zu, error %u\n", 1882 size, r); 1883 goto fail_2; 1884 } 1885 1886 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1887 size, 1888 ubsec_dmamap_cb, 1889 &dma->dma_paddr, 1890 mapflags | BUS_DMA_NOWAIT); 1891 if (r != 0) { 1892 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1893 "bus_dmamap_load failed; error %u\n", r); 1894 goto fail_3; 1895 } 1896 1897 dma->dma_size = size; 1898 return (0); 1899 1900fail_3: 1901 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1902fail_2: 1903 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1904fail_1: 1905 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1906 bus_dma_tag_destroy(dma->dma_tag); 1907fail_0: 1908 dma->dma_map = NULL; 1909 dma->dma_tag = NULL; 1910 return (r); 1911} 1912 1913static void 1914ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1915{ 1916 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1917 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1918 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1919 bus_dma_tag_destroy(dma->dma_tag); 1920} 1921 1922/* 1923 * Resets the board. Values in the regesters are left as is 1924 * from the reset (i.e. initial values are assigned elsewhere). 1925 */ 1926static void 1927ubsec_reset_board(struct ubsec_softc *sc) 1928{ 1929 volatile u_int32_t ctrl; 1930 1931 ctrl = READ_REG(sc, BS_CTRL); 1932 ctrl |= BS_CTRL_RESET; 1933 WRITE_REG(sc, BS_CTRL, ctrl); 1934 1935 /* 1936 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1937 */ 1938 DELAY(10); 1939} 1940 1941/* 1942 * Init Broadcom registers 1943 */ 1944static void 1945ubsec_init_board(struct ubsec_softc *sc) 1946{ 1947 u_int32_t ctrl; 1948 1949 ctrl = READ_REG(sc, BS_CTRL); 1950 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1951 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1952 1953 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) 1954 ctrl |= BS_CTRL_MCR2INT; 1955 else 1956 ctrl &= ~BS_CTRL_MCR2INT; 1957 1958 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1959 ctrl &= ~BS_CTRL_SWNORM; 1960 1961 WRITE_REG(sc, BS_CTRL, ctrl); 1962} 1963 1964/* 1965 * Init Broadcom PCI registers 1966 */ 1967static void 1968ubsec_init_pciregs(device_t dev) 1969{ 1970#if 0 1971 u_int32_t misc; 1972 1973 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT); 1974 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT)) 1975 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT); 1976 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT)) 1977 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT); 1978 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc); 1979#endif 1980 1981 /* 1982 * This will set the cache line size to 1, this will 1983 * force the BCM58xx chip just to do burst read/writes. 1984 * Cache line read/writes are to slow 1985 */ 1986 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1); 1987} 1988 1989/* 1990 * Clean up after a chip crash. 1991 * It is assumed that the caller in splimp() 1992 */ 1993static void 1994ubsec_cleanchip(struct ubsec_softc *sc) 1995{ 1996 struct ubsec_q *q; 1997 1998 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 1999 q = SIMPLEQ_FIRST(&sc->sc_qchip); 2000 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); 2001 ubsec_free_q(sc, q); 2002 } 2003 sc->sc_nqchip = 0; 2004} 2005 2006/* 2007 * free a ubsec_q 2008 * It is assumed that the caller is within splimp(). 2009 */ 2010static int 2011ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2012{ 2013 struct ubsec_q *q2; 2014 struct cryptop *crp; 2015 int npkts; 2016 int i; 2017 2018 npkts = q->q_nstacked_mcrs; 2019 2020 for (i = 0; i < npkts; i++) { 2021 if(q->q_stacked_mcr[i]) { 2022 q2 = q->q_stacked_mcr[i]; 2023 2024 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 2025 m_freem(q2->q_dst_m); 2026 2027 crp = (struct cryptop *)q2->q_crp; 2028 2029 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2030 2031 crp->crp_etype = EFAULT; 2032 crypto_done(crp); 2033 } else { 2034 break; 2035 } 2036 } 2037 2038 /* 2039 * Free header MCR 2040 */ 2041 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2042 m_freem(q->q_dst_m); 2043 2044 crp = (struct cryptop *)q->q_crp; 2045 2046 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2047 2048 crp->crp_etype = EFAULT; 2049 crypto_done(crp); 2050 return(0); 2051} 2052 2053/* 2054 * Routine to reset the chip and clean up. 2055 * It is assumed that the caller is in splimp() 2056 */ 2057static void 2058ubsec_totalreset(struct ubsec_softc *sc) 2059{ 2060 ubsec_reset_board(sc); 2061 ubsec_init_board(sc); 2062 ubsec_cleanchip(sc); 2063} 2064 2065static int 2066ubsec_dmamap_aligned(struct ubsec_operand *op) 2067{ 2068 int i; 2069 2070 for (i = 0; i < op->nsegs; i++) { 2071 if (op->segs[i].ds_addr & 3) 2072 return (0); 2073 if ((i != (op->nsegs - 1)) && 2074 (op->segs[i].ds_len & 3)) 2075 return (0); 2076 } 2077 return (1); 2078} 2079 2080static void 2081ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2082{ 2083 switch (q->q_type) { 2084 case UBS_CTXOP_MODEXP: { 2085 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2086 2087 ubsec_dma_free(sc, &me->me_q.q_mcr); 2088 ubsec_dma_free(sc, &me->me_q.q_ctx); 2089 ubsec_dma_free(sc, &me->me_M); 2090 ubsec_dma_free(sc, &me->me_E); 2091 ubsec_dma_free(sc, &me->me_C); 2092 ubsec_dma_free(sc, &me->me_epb); 2093 free(me, M_DEVBUF); 2094 break; 2095 } 2096 case UBS_CTXOP_RSAPRIV: { 2097 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2098 2099 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2100 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2101 ubsec_dma_free(sc, &rp->rpr_msgin); 2102 ubsec_dma_free(sc, &rp->rpr_msgout); 2103 free(rp, M_DEVBUF); 2104 break; 2105 } 2106 default: 2107 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type); 2108 break; 2109 } 2110} 2111 2112static int 2113ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2114{ 2115 struct ubsec_softc *sc = arg; 2116 int r; 2117 2118 if (krp == NULL || krp->krp_callback == NULL) 2119 return (EINVAL); 2120 2121 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2122 struct ubsec_q2 *q; 2123 2124 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2125 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q_next); 2126 ubsec_kfree(sc, q); 2127 } 2128 2129 switch (krp->krp_op) { 2130 case CRK_MOD_EXP: 2131 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2132 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2133 else 2134 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2135 break; 2136 case CRK_MOD_EXP_CRT: 2137 return (ubsec_kprocess_rsapriv(sc, krp, hint)); 2138 default: 2139 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n", 2140 krp->krp_op); 2141 krp->krp_status = EOPNOTSUPP; 2142 crypto_kdone(krp); 2143 return (0); 2144 } 2145 return (0); /* silence compiler */ 2146} 2147 2148/* 2149 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2150 */ 2151static int 2152ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2153{ 2154 struct ubsec_q2_modexp *me; 2155 struct ubsec_mcr *mcr; 2156 struct ubsec_ctx_modexp *ctx; 2157 struct ubsec_pktbuf *epb; 2158 int err = 0; 2159 u_int nbits, normbits, mbits, shiftbits, ebits; 2160 2161 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2162 if (me == NULL) { 2163 err = ENOMEM; 2164 goto errout; 2165 } 2166 bzero(me, sizeof *me); 2167 me->me_krp = krp; 2168 me->me_q.q_type = UBS_CTXOP_MODEXP; 2169 2170 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2171 if (nbits <= 512) 2172 normbits = 512; 2173 else if (nbits <= 768) 2174 normbits = 768; 2175 else if (nbits <= 1024) 2176 normbits = 1024; 2177 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2178 normbits = 1536; 2179 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2180 normbits = 2048; 2181 else { 2182 err = E2BIG; 2183 goto errout; 2184 } 2185 2186 shiftbits = normbits - nbits; 2187 2188 me->me_modbits = nbits; 2189 me->me_shiftbits = shiftbits; 2190 me->me_normbits = normbits; 2191 2192 /* Sanity check: result bits must be >= true modulus bits. */ 2193 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2194 err = ERANGE; 2195 goto errout; 2196 } 2197 2198 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2199 &me->me_q.q_mcr, 0)) { 2200 err = ENOMEM; 2201 goto errout; 2202 } 2203 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2204 2205 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2206 &me->me_q.q_ctx, 0)) { 2207 err = ENOMEM; 2208 goto errout; 2209 } 2210 2211 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2212 if (mbits > nbits) { 2213 err = E2BIG; 2214 goto errout; 2215 } 2216 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2217 err = ENOMEM; 2218 goto errout; 2219 } 2220 ubsec_kshift_r(shiftbits, 2221 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2222 me->me_M.dma_vaddr, normbits); 2223 2224 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2225 err = ENOMEM; 2226 goto errout; 2227 } 2228 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2229 2230 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2231 if (ebits > nbits) { 2232 err = E2BIG; 2233 goto errout; 2234 } 2235 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2236 err = ENOMEM; 2237 goto errout; 2238 } 2239 ubsec_kshift_r(shiftbits, 2240 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2241 me->me_E.dma_vaddr, normbits); 2242 2243 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2244 &me->me_epb, 0)) { 2245 err = ENOMEM; 2246 goto errout; 2247 } 2248 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2249 epb->pb_addr = htole32(me->me_E.dma_paddr); 2250 epb->pb_next = 0; 2251 epb->pb_len = htole32(normbits / 8); 2252 2253#ifdef UBSEC_DEBUG 2254 if (ubsec_debug) { 2255 printf("Epb "); 2256 ubsec_dump_pb(epb); 2257 } 2258#endif 2259 2260 mcr->mcr_pkts = htole16(1); 2261 mcr->mcr_flags = 0; 2262 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2263 mcr->mcr_reserved = 0; 2264 mcr->mcr_pktlen = 0; 2265 2266 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2267 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2268 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2269 2270 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2271 mcr->mcr_opktbuf.pb_next = 0; 2272 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2273 2274#ifdef DIAGNOSTIC 2275 /* Misaligned output buffer will hang the chip. */ 2276 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2277 panic("%s: modexp invalid addr 0x%x\n", 2278 device_get_nameunit(sc->sc_dev), 2279 letoh32(mcr->mcr_opktbuf.pb_addr)); 2280 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2281 panic("%s: modexp invalid len 0x%x\n", 2282 device_get_nameunit(sc->sc_dev), 2283 letoh32(mcr->mcr_opktbuf.pb_len)); 2284#endif 2285 2286 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2287 bzero(ctx, sizeof(*ctx)); 2288 ubsec_kshift_r(shiftbits, 2289 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2290 ctx->me_N, normbits); 2291 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2292 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2293 ctx->me_E_len = htole16(nbits); 2294 ctx->me_N_len = htole16(nbits); 2295 2296#ifdef UBSEC_DEBUG 2297 if (ubsec_debug) { 2298 ubsec_dump_mcr(mcr); 2299 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2300 } 2301#endif 2302 2303 /* 2304 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2305 * everything else. 2306 */ 2307 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2308 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2309 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2310 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2311 2312 /* Enqueue and we're done... */ 2313 mtx_lock(&sc->sc_mcr2lock); 2314 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2315 ubsec_feed2(sc); 2316 ubsecstats.hst_modexp++; 2317 mtx_unlock(&sc->sc_mcr2lock); 2318 2319 return (0); 2320 2321errout: 2322 if (me != NULL) { 2323 if (me->me_q.q_mcr.dma_map != NULL) 2324 ubsec_dma_free(sc, &me->me_q.q_mcr); 2325 if (me->me_q.q_ctx.dma_map != NULL) { 2326 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2327 ubsec_dma_free(sc, &me->me_q.q_ctx); 2328 } 2329 if (me->me_M.dma_map != NULL) { 2330 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2331 ubsec_dma_free(sc, &me->me_M); 2332 } 2333 if (me->me_E.dma_map != NULL) { 2334 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2335 ubsec_dma_free(sc, &me->me_E); 2336 } 2337 if (me->me_C.dma_map != NULL) { 2338 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2339 ubsec_dma_free(sc, &me->me_C); 2340 } 2341 if (me->me_epb.dma_map != NULL) 2342 ubsec_dma_free(sc, &me->me_epb); 2343 free(me, M_DEVBUF); 2344 } 2345 krp->krp_status = err; 2346 crypto_kdone(krp); 2347 return (0); 2348} 2349 2350/* 2351 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2352 */ 2353static int 2354ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2355{ 2356 struct ubsec_q2_modexp *me; 2357 struct ubsec_mcr *mcr; 2358 struct ubsec_ctx_modexp *ctx; 2359 struct ubsec_pktbuf *epb; 2360 int err = 0; 2361 u_int nbits, normbits, mbits, shiftbits, ebits; 2362 2363 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2364 if (me == NULL) { 2365 err = ENOMEM; 2366 goto errout; 2367 } 2368 bzero(me, sizeof *me); 2369 me->me_krp = krp; 2370 me->me_q.q_type = UBS_CTXOP_MODEXP; 2371 2372 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2373 if (nbits <= 512) 2374 normbits = 512; 2375 else if (nbits <= 768) 2376 normbits = 768; 2377 else if (nbits <= 1024) 2378 normbits = 1024; 2379 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2380 normbits = 1536; 2381 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2382 normbits = 2048; 2383 else { 2384 err = E2BIG; 2385 goto errout; 2386 } 2387 2388 shiftbits = normbits - nbits; 2389 2390 /* XXX ??? */ 2391 me->me_modbits = nbits; 2392 me->me_shiftbits = shiftbits; 2393 me->me_normbits = normbits; 2394 2395 /* Sanity check: result bits must be >= true modulus bits. */ 2396 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2397 err = ERANGE; 2398 goto errout; 2399 } 2400 2401 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2402 &me->me_q.q_mcr, 0)) { 2403 err = ENOMEM; 2404 goto errout; 2405 } 2406 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2407 2408 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2409 &me->me_q.q_ctx, 0)) { 2410 err = ENOMEM; 2411 goto errout; 2412 } 2413 2414 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2415 if (mbits > nbits) { 2416 err = E2BIG; 2417 goto errout; 2418 } 2419 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2420 err = ENOMEM; 2421 goto errout; 2422 } 2423 bzero(me->me_M.dma_vaddr, normbits / 8); 2424 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2425 me->me_M.dma_vaddr, (mbits + 7) / 8); 2426 2427 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2428 err = ENOMEM; 2429 goto errout; 2430 } 2431 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2432 2433 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2434 if (ebits > nbits) { 2435 err = E2BIG; 2436 goto errout; 2437 } 2438 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2439 err = ENOMEM; 2440 goto errout; 2441 } 2442 bzero(me->me_E.dma_vaddr, normbits / 8); 2443 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2444 me->me_E.dma_vaddr, (ebits + 7) / 8); 2445 2446 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2447 &me->me_epb, 0)) { 2448 err = ENOMEM; 2449 goto errout; 2450 } 2451 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2452 epb->pb_addr = htole32(me->me_E.dma_paddr); 2453 epb->pb_next = 0; 2454 epb->pb_len = htole32((ebits + 7) / 8); 2455 2456#ifdef UBSEC_DEBUG 2457 if (ubsec_debug) { 2458 printf("Epb "); 2459 ubsec_dump_pb(epb); 2460 } 2461#endif 2462 2463 mcr->mcr_pkts = htole16(1); 2464 mcr->mcr_flags = 0; 2465 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2466 mcr->mcr_reserved = 0; 2467 mcr->mcr_pktlen = 0; 2468 2469 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2470 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2471 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2472 2473 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2474 mcr->mcr_opktbuf.pb_next = 0; 2475 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2476 2477#ifdef DIAGNOSTIC 2478 /* Misaligned output buffer will hang the chip. */ 2479 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2480 panic("%s: modexp invalid addr 0x%x\n", 2481 device_get_nameunit(sc->sc_dev), 2482 letoh32(mcr->mcr_opktbuf.pb_addr)); 2483 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2484 panic("%s: modexp invalid len 0x%x\n", 2485 device_get_nameunit(sc->sc_dev), 2486 letoh32(mcr->mcr_opktbuf.pb_len)); 2487#endif 2488 2489 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2490 bzero(ctx, sizeof(*ctx)); 2491 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2492 (nbits + 7) / 8); 2493 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2494 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2495 ctx->me_E_len = htole16(ebits); 2496 ctx->me_N_len = htole16(nbits); 2497 2498#ifdef UBSEC_DEBUG 2499 if (ubsec_debug) { 2500 ubsec_dump_mcr(mcr); 2501 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2502 } 2503#endif 2504 2505 /* 2506 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2507 * everything else. 2508 */ 2509 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2510 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2511 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2512 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2513 2514 /* Enqueue and we're done... */ 2515 mtx_lock(&sc->sc_mcr2lock); 2516 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2517 ubsec_feed2(sc); 2518 mtx_unlock(&sc->sc_mcr2lock); 2519 2520 return (0); 2521 2522errout: 2523 if (me != NULL) { 2524 if (me->me_q.q_mcr.dma_map != NULL) 2525 ubsec_dma_free(sc, &me->me_q.q_mcr); 2526 if (me->me_q.q_ctx.dma_map != NULL) { 2527 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2528 ubsec_dma_free(sc, &me->me_q.q_ctx); 2529 } 2530 if (me->me_M.dma_map != NULL) { 2531 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2532 ubsec_dma_free(sc, &me->me_M); 2533 } 2534 if (me->me_E.dma_map != NULL) { 2535 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2536 ubsec_dma_free(sc, &me->me_E); 2537 } 2538 if (me->me_C.dma_map != NULL) { 2539 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2540 ubsec_dma_free(sc, &me->me_C); 2541 } 2542 if (me->me_epb.dma_map != NULL) 2543 ubsec_dma_free(sc, &me->me_epb); 2544 free(me, M_DEVBUF); 2545 } 2546 krp->krp_status = err; 2547 crypto_kdone(krp); 2548 return (0); 2549} 2550 2551static int 2552ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2553{ 2554 struct ubsec_q2_rsapriv *rp = NULL; 2555 struct ubsec_mcr *mcr; 2556 struct ubsec_ctx_rsapriv *ctx; 2557 int err = 0; 2558 u_int padlen, msglen; 2559 2560 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2561 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2562 if (msglen > padlen) 2563 padlen = msglen; 2564 2565 if (padlen <= 256) 2566 padlen = 256; 2567 else if (padlen <= 384) 2568 padlen = 384; 2569 else if (padlen <= 512) 2570 padlen = 512; 2571 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2572 padlen = 768; 2573 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2574 padlen = 1024; 2575 else { 2576 err = E2BIG; 2577 goto errout; 2578 } 2579 2580 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2581 err = E2BIG; 2582 goto errout; 2583 } 2584 2585 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2586 err = E2BIG; 2587 goto errout; 2588 } 2589 2590 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2591 err = E2BIG; 2592 goto errout; 2593 } 2594 2595 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT); 2596 if (rp == NULL) 2597 return (ENOMEM); 2598 bzero(rp, sizeof *rp); 2599 rp->rpr_krp = krp; 2600 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2601 2602 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2603 &rp->rpr_q.q_mcr, 0)) { 2604 err = ENOMEM; 2605 goto errout; 2606 } 2607 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2608 2609 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2610 &rp->rpr_q.q_ctx, 0)) { 2611 err = ENOMEM; 2612 goto errout; 2613 } 2614 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2615 bzero(ctx, sizeof *ctx); 2616 2617 /* Copy in p */ 2618 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2619 &ctx->rpr_buf[0 * (padlen / 8)], 2620 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2621 2622 /* Copy in q */ 2623 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2624 &ctx->rpr_buf[1 * (padlen / 8)], 2625 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2626 2627 /* Copy in dp */ 2628 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2629 &ctx->rpr_buf[2 * (padlen / 8)], 2630 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2631 2632 /* Copy in dq */ 2633 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2634 &ctx->rpr_buf[3 * (padlen / 8)], 2635 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2636 2637 /* Copy in pinv */ 2638 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2639 &ctx->rpr_buf[4 * (padlen / 8)], 2640 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2641 2642 msglen = padlen * 2; 2643 2644 /* Copy in input message (aligned buffer/length). */ 2645 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2646 /* Is this likely? */ 2647 err = E2BIG; 2648 goto errout; 2649 } 2650 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2651 err = ENOMEM; 2652 goto errout; 2653 } 2654 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2655 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2656 rp->rpr_msgin.dma_vaddr, 2657 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2658 2659 /* Prepare space for output message (aligned buffer/length). */ 2660 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2661 /* Is this likely? */ 2662 err = E2BIG; 2663 goto errout; 2664 } 2665 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2666 err = ENOMEM; 2667 goto errout; 2668 } 2669 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2670 2671 mcr->mcr_pkts = htole16(1); 2672 mcr->mcr_flags = 0; 2673 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2674 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2675 mcr->mcr_ipktbuf.pb_next = 0; 2676 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2677 mcr->mcr_reserved = 0; 2678 mcr->mcr_pktlen = htole16(msglen); 2679 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2680 mcr->mcr_opktbuf.pb_next = 0; 2681 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2682 2683#ifdef DIAGNOSTIC 2684 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2685 panic("%s: rsapriv: invalid msgin %x(0x%jx)", 2686 device_get_nameunit(sc->sc_dev), 2687 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size); 2688 } 2689 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2690 panic("%s: rsapriv: invalid msgout %x(0x%jx)", 2691 device_get_nameunit(sc->sc_dev), 2692 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size); 2693 } 2694#endif 2695 2696 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2697 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2698 ctx->rpr_q_len = htole16(padlen); 2699 ctx->rpr_p_len = htole16(padlen); 2700 2701 /* 2702 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2703 * everything else. 2704 */ 2705 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE); 2706 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD); 2707 2708 /* Enqueue and we're done... */ 2709 mtx_lock(&sc->sc_mcr2lock); 2710 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2711 ubsec_feed2(sc); 2712 ubsecstats.hst_modexpcrt++; 2713 mtx_unlock(&sc->sc_mcr2lock); 2714 return (0); 2715 2716errout: 2717 if (rp != NULL) { 2718 if (rp->rpr_q.q_mcr.dma_map != NULL) 2719 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2720 if (rp->rpr_msgin.dma_map != NULL) { 2721 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2722 ubsec_dma_free(sc, &rp->rpr_msgin); 2723 } 2724 if (rp->rpr_msgout.dma_map != NULL) { 2725 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2726 ubsec_dma_free(sc, &rp->rpr_msgout); 2727 } 2728 free(rp, M_DEVBUF); 2729 } 2730 krp->krp_status = err; 2731 crypto_kdone(krp); 2732 return (0); 2733} 2734 2735#ifdef UBSEC_DEBUG 2736static void 2737ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2738{ 2739 printf("addr 0x%x (0x%x) next 0x%x\n", 2740 pb->pb_addr, pb->pb_len, pb->pb_next); 2741} 2742 2743static void 2744ubsec_dump_ctx2(struct ubsec_ctx_keyop *c) 2745{ 2746 printf("CTX (0x%x):\n", c->ctx_len); 2747 switch (letoh16(c->ctx_op)) { 2748 case UBS_CTXOP_RNGBYPASS: 2749 case UBS_CTXOP_RNGSHA1: 2750 break; 2751 case UBS_CTXOP_MODEXP: 2752 { 2753 struct ubsec_ctx_modexp *cx = (void *)c; 2754 int i, len; 2755 2756 printf(" Elen %u, Nlen %u\n", 2757 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2758 len = (cx->me_N_len + 7)/8; 2759 for (i = 0; i < len; i++) 2760 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2761 printf("\n"); 2762 break; 2763 } 2764 default: 2765 printf("unknown context: %x\n", c->ctx_op); 2766 } 2767 printf("END CTX\n"); 2768} 2769 2770static void 2771ubsec_dump_mcr(struct ubsec_mcr *mcr) 2772{ 2773 volatile struct ubsec_mcr_add *ma; 2774 int i; 2775 2776 printf("MCR:\n"); 2777 printf(" pkts: %u, flags 0x%x\n", 2778 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2779 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2780 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2781 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2782 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2783 letoh16(ma->mcr_reserved)); 2784 printf(" %d: ipkt ", i); 2785 ubsec_dump_pb(&ma->mcr_ipktbuf); 2786 printf(" %d: opkt ", i); 2787 ubsec_dump_pb(&ma->mcr_opktbuf); 2788 ma++; 2789 } 2790 printf("END MCR\n"); 2791} 2792#endif /* UBSEC_DEBUG */ 2793 2794/* 2795 * Return the number of significant bits of a big number. 2796 */ 2797static int 2798ubsec_ksigbits(struct crparam *cr) 2799{ 2800 u_int plen = (cr->crp_nbits + 7) / 8; 2801 int i, sig = plen * 8; 2802 u_int8_t c, *p = cr->crp_p; 2803 2804 for (i = plen - 1; i >= 0; i--) { 2805 c = p[i]; 2806 if (c != 0) { 2807 while ((c & 0x80) == 0) { 2808 sig--; 2809 c <<= 1; 2810 } 2811 break; 2812 } 2813 sig -= 8; 2814 } 2815 return (sig); 2816} 2817 2818static void 2819ubsec_kshift_r( 2820 u_int shiftbits, 2821 u_int8_t *src, u_int srcbits, 2822 u_int8_t *dst, u_int dstbits) 2823{ 2824 u_int slen, dlen; 2825 int i, si, di, n; 2826 2827 slen = (srcbits + 7) / 8; 2828 dlen = (dstbits + 7) / 8; 2829 2830 for (i = 0; i < slen; i++) 2831 dst[i] = src[i]; 2832 for (i = 0; i < dlen - slen; i++) 2833 dst[slen + i] = 0; 2834 2835 n = shiftbits / 8; 2836 if (n != 0) { 2837 si = dlen - n - 1; 2838 di = dlen - 1; 2839 while (si >= 0) 2840 dst[di--] = dst[si--]; 2841 while (di >= 0) 2842 dst[di--] = 0; 2843 } 2844 2845 n = shiftbits % 8; 2846 if (n != 0) { 2847 for (i = dlen - 1; i > 0; i--) 2848 dst[i] = (dst[i] << n) | 2849 (dst[i - 1] >> (8 - n)); 2850 dst[0] = dst[0] << n; 2851 } 2852} 2853 2854static void 2855ubsec_kshift_l( 2856 u_int shiftbits, 2857 u_int8_t *src, u_int srcbits, 2858 u_int8_t *dst, u_int dstbits) 2859{ 2860 int slen, dlen, i, n; 2861 2862 slen = (srcbits + 7) / 8; 2863 dlen = (dstbits + 7) / 8; 2864 2865 n = shiftbits / 8; 2866 for (i = 0; i < slen; i++) 2867 dst[i] = src[i + n]; 2868 for (i = 0; i < dlen - slen; i++) 2869 dst[slen + i] = 0; 2870 2871 n = shiftbits % 8; 2872 if (n != 0) { 2873 for (i = 0; i < (dlen - 1); i++) 2874 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2875 dst[dlen - 1] = dst[dlen - 1] >> n; 2876 } 2877} 2878