ubsec.c revision 159340
1/* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */ 2 3/*- 4 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 5 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 6 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Jason L. Wright 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Effort sponsored in part by the Defense Advanced Research Projects 37 * Agency (DARPA) and Air Force Research Laboratory, Air Force 38 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/dev/ubsec/ubsec.c 159340 2006-06-06 13:32:26Z pjd $"); 43 44/* 45 * uBsec 5[56]01, 58xx hardware crypto accelerator 46 */ 47 48#include "opt_ubsec.h" 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/proc.h> 53#include <sys/errno.h> 54#include <sys/malloc.h> 55#include <sys/kernel.h> 56#include <sys/module.h> 57#include <sys/mbuf.h> 58#include <sys/lock.h> 59#include <sys/mutex.h> 60#include <sys/sysctl.h> 61#include <sys/endian.h> 62 63#include <vm/vm.h> 64#include <vm/pmap.h> 65 66#include <machine/bus.h> 67#include <machine/resource.h> 68#include <sys/bus.h> 69#include <sys/rman.h> 70 71#include <crypto/sha1.h> 72#include <opencrypto/cryptodev.h> 73#include <opencrypto/cryptosoft.h> 74#include <sys/md5.h> 75#include <sys/random.h> 76 77#include <dev/pci/pcivar.h> 78#include <dev/pci/pcireg.h> 79 80/* grr, #defines for gratuitous incompatibility in queue.h */ 81#define SIMPLEQ_HEAD STAILQ_HEAD 82#define SIMPLEQ_ENTRY STAILQ_ENTRY 83#define SIMPLEQ_INIT STAILQ_INIT 84#define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL 85#define SIMPLEQ_EMPTY STAILQ_EMPTY 86#define SIMPLEQ_FIRST STAILQ_FIRST 87#define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD_UNTIL 88#define SIMPLEQ_FOREACH STAILQ_FOREACH 89/* ditto for endian.h */ 90#define letoh16(x) le16toh(x) 91#define letoh32(x) le32toh(x) 92 93#ifdef UBSEC_RNDTEST 94#include <dev/rndtest/rndtest.h> 95#endif 96#include <dev/ubsec/ubsecreg.h> 97#include <dev/ubsec/ubsecvar.h> 98 99/* 100 * Prototypes and count for the pci_device structure 101 */ 102static int ubsec_probe(device_t); 103static int ubsec_attach(device_t); 104static int ubsec_detach(device_t); 105static int ubsec_suspend(device_t); 106static int ubsec_resume(device_t); 107static void ubsec_shutdown(device_t); 108 109static device_method_t ubsec_methods[] = { 110 /* Device interface */ 111 DEVMETHOD(device_probe, ubsec_probe), 112 DEVMETHOD(device_attach, ubsec_attach), 113 DEVMETHOD(device_detach, ubsec_detach), 114 DEVMETHOD(device_suspend, ubsec_suspend), 115 DEVMETHOD(device_resume, ubsec_resume), 116 DEVMETHOD(device_shutdown, ubsec_shutdown), 117 118 /* bus interface */ 119 DEVMETHOD(bus_print_child, bus_generic_print_child), 120 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 121 122 { 0, 0 } 123}; 124static driver_t ubsec_driver = { 125 "ubsec", 126 ubsec_methods, 127 sizeof (struct ubsec_softc) 128}; 129static devclass_t ubsec_devclass; 130 131DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0); 132MODULE_DEPEND(ubsec, crypto, 1, 1, 1); 133#ifdef UBSEC_RNDTEST 134MODULE_DEPEND(ubsec, rndtest, 1, 1, 1); 135#endif 136 137static void ubsec_intr(void *); 138static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *); 139static int ubsec_freesession(void *, u_int64_t); 140static int ubsec_process(void *, struct cryptop *, int); 141static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 142static void ubsec_feed(struct ubsec_softc *); 143static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 144static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 145static int ubsec_feed2(struct ubsec_softc *); 146static void ubsec_rng(void *); 147static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 148 struct ubsec_dma_alloc *, int); 149#define ubsec_dma_sync(_dma, _flags) \ 150 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 151static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 152static int ubsec_dmamap_aligned(struct ubsec_operand *op); 153 154static void ubsec_reset_board(struct ubsec_softc *sc); 155static void ubsec_init_board(struct ubsec_softc *sc); 156static void ubsec_init_pciregs(device_t dev); 157static void ubsec_totalreset(struct ubsec_softc *sc); 158 159static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q); 160 161static int ubsec_kprocess(void*, struct cryptkop *, int); 162static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int); 163static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int); 164static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int); 165static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 166static int ubsec_ksigbits(struct crparam *); 167static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 168static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 169 170SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters"); 171 172#ifdef UBSEC_DEBUG 173static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 174static void ubsec_dump_mcr(struct ubsec_mcr *); 175static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *); 176 177static int ubsec_debug = 0; 178SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug, 179 0, "control debugging msgs"); 180#endif 181 182#define READ_REG(sc,r) \ 183 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 184 185#define WRITE_REG(sc,reg,val) \ 186 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 187 188#define SWAP32(x) (x) = htole32(ntohl((x))) 189#define HTOLE32(x) (x) = htole32(x) 190 191struct ubsec_stats ubsecstats; 192SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats, 193 ubsec_stats, "driver statistics"); 194 195static int 196ubsec_probe(device_t dev) 197{ 198 if (pci_get_vendor(dev) == PCI_VENDOR_SUN && 199 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 || 200 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K)) 201 return (BUS_PROBE_DEFAULT); 202 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 203 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 || 204 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)) 205 return (BUS_PROBE_DEFAULT); 206 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 207 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 || 208 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 209 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 || 210 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 || 211 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 212 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 213 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 214 )) 215 return (BUS_PROBE_DEFAULT); 216 return (ENXIO); 217} 218 219static const char* 220ubsec_partname(struct ubsec_softc *sc) 221{ 222 /* XXX sprintf numbers when not decoded */ 223 switch (pci_get_vendor(sc->sc_dev)) { 224 case PCI_VENDOR_BROADCOM: 225 switch (pci_get_device(sc->sc_dev)) { 226 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801"; 227 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802"; 228 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805"; 229 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820"; 230 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821"; 231 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822"; 232 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823"; 233 } 234 return "Broadcom unknown-part"; 235 case PCI_VENDOR_BLUESTEEL: 236 switch (pci_get_device(sc->sc_dev)) { 237 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601"; 238 } 239 return "Bluesteel unknown-part"; 240 case PCI_VENDOR_SUN: 241 switch (pci_get_device(sc->sc_dev)) { 242 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821"; 243 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K"; 244 } 245 return "Sun unknown-part"; 246 } 247 return "Unknown-vendor unknown-part"; 248} 249 250static void 251default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 252{ 253 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 254} 255 256static int 257ubsec_attach(device_t dev) 258{ 259 struct ubsec_softc *sc = device_get_softc(dev); 260 struct ubsec_dma *dmap; 261 u_int32_t cmd, i; 262 int rid; 263 264 bzero(sc, sizeof (*sc)); 265 sc->sc_dev = dev; 266 267 SIMPLEQ_INIT(&sc->sc_queue); 268 SIMPLEQ_INIT(&sc->sc_qchip); 269 SIMPLEQ_INIT(&sc->sc_queue2); 270 SIMPLEQ_INIT(&sc->sc_qchip2); 271 SIMPLEQ_INIT(&sc->sc_q2free); 272 273 /* XXX handle power management */ 274 275 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; 276 277 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 278 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601) 279 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 280 281 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 282 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 283 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805)) 284 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 285 286 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 287 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820) 288 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 289 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 290 291 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 292 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 293 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 294 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) || 295 (pci_get_vendor(dev) == PCI_VENDOR_SUN && 296 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K || 297 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) { 298 /* NB: the 5821/5822 defines some additional status bits */ 299 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY | 300 BS_STAT_MCR2_ALLEMPTY; 301 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 302 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 303 } 304 305 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 306 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 307 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 308 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 309 310 if (!(cmd & PCIM_CMD_MEMEN)) { 311 device_printf(dev, "failed to enable memory mapping\n"); 312 goto bad; 313 } 314 315 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 316 device_printf(dev, "failed to enable bus mastering\n"); 317 goto bad; 318 } 319 320 /* 321 * Setup memory-mapping of PCI registers. 322 */ 323 rid = BS_BAR; 324 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 325 RF_ACTIVE); 326 if (sc->sc_sr == NULL) { 327 device_printf(dev, "cannot map register space\n"); 328 goto bad; 329 } 330 sc->sc_st = rman_get_bustag(sc->sc_sr); 331 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 332 333 /* 334 * Arrange interrupt line. 335 */ 336 rid = 0; 337 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 338 RF_SHAREABLE|RF_ACTIVE); 339 if (sc->sc_irq == NULL) { 340 device_printf(dev, "could not map interrupt\n"); 341 goto bad1; 342 } 343 /* 344 * NB: Network code assumes we are blocked with splimp() 345 * so make sure the IRQ is mapped appropriately. 346 */ 347 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 348 ubsec_intr, sc, &sc->sc_ih)) { 349 device_printf(dev, "could not establish interrupt\n"); 350 goto bad2; 351 } 352 353 sc->sc_cid = crypto_get_driverid(0); 354 if (sc->sc_cid < 0) { 355 device_printf(dev, "could not get crypto driver id\n"); 356 goto bad3; 357 } 358 359 /* 360 * Setup DMA descriptor area. 361 */ 362 if (bus_dma_tag_create(NULL, /* parent */ 363 1, 0, /* alignment, bounds */ 364 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 365 BUS_SPACE_MAXADDR, /* highaddr */ 366 NULL, NULL, /* filter, filterarg */ 367 0x3ffff, /* maxsize */ 368 UBS_MAX_SCATTER, /* nsegments */ 369 0xffff, /* maxsegsize */ 370 BUS_DMA_ALLOCNOW, /* flags */ 371 NULL, NULL, /* lockfunc, lockarg */ 372 &sc->sc_dmat)) { 373 device_printf(dev, "cannot allocate DMA tag\n"); 374 goto bad4; 375 } 376 SIMPLEQ_INIT(&sc->sc_freequeue); 377 dmap = sc->sc_dmaa; 378 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 379 struct ubsec_q *q; 380 381 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 382 M_DEVBUF, M_NOWAIT); 383 if (q == NULL) { 384 device_printf(dev, "cannot allocate queue buffers\n"); 385 break; 386 } 387 388 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 389 &dmap->d_alloc, 0)) { 390 device_printf(dev, "cannot allocate dma buffers\n"); 391 free(q, M_DEVBUF); 392 break; 393 } 394 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 395 396 q->q_dma = dmap; 397 sc->sc_queuea[i] = q; 398 399 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 400 } 401 mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev), 402 "mcr1 operations", MTX_DEF); 403 mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev), 404 "mcr1 free q", MTX_DEF); 405 406 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc)); 407 408 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 409 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 410 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 411 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 412 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 413 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 414 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 415 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 416 417 /* 418 * Reset Broadcom chip 419 */ 420 ubsec_reset_board(sc); 421 422 /* 423 * Init Broadcom specific PCI settings 424 */ 425 ubsec_init_pciregs(dev); 426 427 /* 428 * Init Broadcom chip 429 */ 430 ubsec_init_board(sc); 431 432#ifndef UBSEC_NO_RNG 433 if (sc->sc_flags & UBS_FLAGS_RNG) { 434 sc->sc_statmask |= BS_STAT_MCR2_DONE; 435#ifdef UBSEC_RNDTEST 436 sc->sc_rndtest = rndtest_attach(dev); 437 if (sc->sc_rndtest) 438 sc->sc_harvest = rndtest_harvest; 439 else 440 sc->sc_harvest = default_harvest; 441#else 442 sc->sc_harvest = default_harvest; 443#endif 444 445 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 446 &sc->sc_rng.rng_q.q_mcr, 0)) 447 goto skip_rng; 448 449 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 450 &sc->sc_rng.rng_q.q_ctx, 0)) { 451 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 452 goto skip_rng; 453 } 454 455 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 456 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 457 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 458 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 459 goto skip_rng; 460 } 461 462 if (hz >= 100) 463 sc->sc_rnghz = hz / 100; 464 else 465 sc->sc_rnghz = 1; 466 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 467 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 468skip_rng: 469 ; 470 } 471#endif /* UBSEC_NO_RNG */ 472 mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev), 473 "mcr2 operations", MTX_DEF); 474 475 if (sc->sc_flags & UBS_FLAGS_KEY) { 476 sc->sc_statmask |= BS_STAT_MCR2_DONE; 477 478 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 479 ubsec_kprocess, sc); 480#if 0 481 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 482 ubsec_kprocess, sc); 483#endif 484 } 485 return (0); 486bad4: 487 crypto_unregister_all(sc->sc_cid); 488bad3: 489 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 490bad2: 491 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 492bad1: 493 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 494bad: 495 return (ENXIO); 496} 497 498/* 499 * Detach a device that successfully probed. 500 */ 501static int 502ubsec_detach(device_t dev) 503{ 504 struct ubsec_softc *sc = device_get_softc(dev); 505 506 /* XXX wait/abort active ops */ 507 508 /* disable interrupts */ 509 WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~ 510 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR)); 511 512 callout_stop(&sc->sc_rngto); 513 514 crypto_unregister_all(sc->sc_cid); 515 516#ifdef UBSEC_RNDTEST 517 if (sc->sc_rndtest) 518 rndtest_detach(sc->sc_rndtest); 519#endif 520 521 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 522 struct ubsec_q *q; 523 524 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 525 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 526 ubsec_dma_free(sc, &q->q_dma->d_alloc); 527 free(q, M_DEVBUF); 528 } 529 mtx_destroy(&sc->sc_mcr1lock); 530 mtx_destroy(&sc->sc_freeqlock); 531#ifndef UBSEC_NO_RNG 532 if (sc->sc_flags & UBS_FLAGS_RNG) { 533 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 534 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 535 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 536 } 537#endif /* UBSEC_NO_RNG */ 538 mtx_destroy(&sc->sc_mcr2lock); 539 540 bus_generic_detach(dev); 541 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 542 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 543 544 bus_dma_tag_destroy(sc->sc_dmat); 545 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 546 547 return (0); 548} 549 550/* 551 * Stop all chip i/o so that the kernel's probe routines don't 552 * get confused by errant DMAs when rebooting. 553 */ 554static void 555ubsec_shutdown(device_t dev) 556{ 557#ifdef notyet 558 ubsec_stop(device_get_softc(dev)); 559#endif 560} 561 562/* 563 * Device suspend routine. 564 */ 565static int 566ubsec_suspend(device_t dev) 567{ 568 struct ubsec_softc *sc = device_get_softc(dev); 569 570#ifdef notyet 571 /* XXX stop the device and save PCI settings */ 572#endif 573 sc->sc_suspended = 1; 574 575 return (0); 576} 577 578static int 579ubsec_resume(device_t dev) 580{ 581 struct ubsec_softc *sc = device_get_softc(dev); 582 583#ifdef notyet 584 /* XXX retore PCI settings and start the device */ 585#endif 586 sc->sc_suspended = 0; 587 return (0); 588} 589 590/* 591 * UBSEC Interrupt routine 592 */ 593static void 594ubsec_intr(void *arg) 595{ 596 struct ubsec_softc *sc = arg; 597 volatile u_int32_t stat; 598 struct ubsec_q *q; 599 struct ubsec_dma *dmap; 600 int npkts = 0, i; 601 602 stat = READ_REG(sc, BS_STAT); 603 stat &= sc->sc_statmask; 604 if (stat == 0) 605 return; 606 607 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 608 609 /* 610 * Check to see if we have any packets waiting for us 611 */ 612 if ((stat & BS_STAT_MCR1_DONE)) { 613 mtx_lock(&sc->sc_mcr1lock); 614 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 615 q = SIMPLEQ_FIRST(&sc->sc_qchip); 616 dmap = q->q_dma; 617 618 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 619 break; 620 621 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 622 623 npkts = q->q_nstacked_mcrs; 624 sc->sc_nqchip -= 1+npkts; 625 /* 626 * search for further sc_qchip ubsec_q's that share 627 * the same MCR, and complete them too, they must be 628 * at the top. 629 */ 630 for (i = 0; i < npkts; i++) { 631 if(q->q_stacked_mcr[i]) { 632 ubsec_callback(sc, q->q_stacked_mcr[i]); 633 } else { 634 break; 635 } 636 } 637 ubsec_callback(sc, q); 638 } 639 /* 640 * Don't send any more packet to chip if there has been 641 * a DMAERR. 642 */ 643 if (!(stat & BS_STAT_DMAERR)) 644 ubsec_feed(sc); 645 mtx_unlock(&sc->sc_mcr1lock); 646 } 647 648 /* 649 * Check to see if we have any key setups/rng's waiting for us 650 */ 651 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 652 (stat & BS_STAT_MCR2_DONE)) { 653 struct ubsec_q2 *q2; 654 struct ubsec_mcr *mcr; 655 656 mtx_lock(&sc->sc_mcr2lock); 657 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 658 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 659 660 ubsec_dma_sync(&q2->q_mcr, 661 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 662 663 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 664 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 665 ubsec_dma_sync(&q2->q_mcr, 666 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 667 break; 668 } 669 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next); 670 ubsec_callback2(sc, q2); 671 /* 672 * Don't send any more packet to chip if there has been 673 * a DMAERR. 674 */ 675 if (!(stat & BS_STAT_DMAERR)) 676 ubsec_feed2(sc); 677 } 678 mtx_unlock(&sc->sc_mcr2lock); 679 } 680 681 /* 682 * Check to see if we got any DMA Error 683 */ 684 if (stat & BS_STAT_DMAERR) { 685#ifdef UBSEC_DEBUG 686 if (ubsec_debug) { 687 volatile u_int32_t a = READ_REG(sc, BS_ERR); 688 689 printf("dmaerr %s@%08x\n", 690 (a & BS_ERR_READ) ? "read" : "write", 691 a & BS_ERR_ADDR); 692 } 693#endif /* UBSEC_DEBUG */ 694 ubsecstats.hst_dmaerr++; 695 mtx_lock(&sc->sc_mcr1lock); 696 ubsec_totalreset(sc); 697 ubsec_feed(sc); 698 mtx_unlock(&sc->sc_mcr1lock); 699 } 700 701 if (sc->sc_needwakeup) { /* XXX check high watermark */ 702 int wakeup; 703 704 mtx_lock(&sc->sc_freeqlock); 705 wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 706#ifdef UBSEC_DEBUG 707 if (ubsec_debug) 708 device_printf(sc->sc_dev, "wakeup crypto (%x)\n", 709 sc->sc_needwakeup); 710#endif /* UBSEC_DEBUG */ 711 sc->sc_needwakeup &= ~wakeup; 712 mtx_unlock(&sc->sc_freeqlock); 713 crypto_unblock(sc->sc_cid, wakeup); 714 } 715} 716 717/* 718 * ubsec_feed() - aggregate and post requests to chip 719 */ 720static void 721ubsec_feed(struct ubsec_softc *sc) 722{ 723 struct ubsec_q *q, *q2; 724 int npkts, i; 725 void *v; 726 u_int32_t stat; 727 728 /* 729 * Decide how many ops to combine in a single MCR. We cannot 730 * aggregate more than UBS_MAX_AGGR because this is the number 731 * of slots defined in the data structure. Note that 732 * aggregation only happens if ops are marked batch'able. 733 * Aggregating ops reduces the number of interrupts to the host 734 * but also (potentially) increases the latency for processing 735 * completed ops as we only get an interrupt when all aggregated 736 * ops have completed. 737 */ 738 if (sc->sc_nqueue == 0) 739 return; 740 if (sc->sc_nqueue > 1) { 741 npkts = 0; 742 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) { 743 npkts++; 744 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0) 745 break; 746 } 747 } else 748 npkts = 1; 749 /* 750 * Check device status before going any further. 751 */ 752 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 753 if (stat & BS_STAT_DMAERR) { 754 ubsec_totalreset(sc); 755 ubsecstats.hst_dmaerr++; 756 } else 757 ubsecstats.hst_mcr1full++; 758 return; 759 } 760 if (sc->sc_nqueue > ubsecstats.hst_maxqueue) 761 ubsecstats.hst_maxqueue = sc->sc_nqueue; 762 if (npkts > UBS_MAX_AGGR) 763 npkts = UBS_MAX_AGGR; 764 if (npkts < 2) /* special case 1 op */ 765 goto feed1; 766 767 ubsecstats.hst_totbatch += npkts-1; 768#ifdef UBSEC_DEBUG 769 if (ubsec_debug) 770 printf("merging %d records\n", npkts); 771#endif /* UBSEC_DEBUG */ 772 773 q = SIMPLEQ_FIRST(&sc->sc_queue); 774 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 775 --sc->sc_nqueue; 776 777 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 778 if (q->q_dst_map != NULL) 779 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 780 781 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 782 783 for (i = 0; i < q->q_nstacked_mcrs; i++) { 784 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 785 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 786 BUS_DMASYNC_PREWRITE); 787 if (q2->q_dst_map != NULL) 788 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 789 BUS_DMASYNC_PREREAD); 790 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next); 791 --sc->sc_nqueue; 792 793 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - 794 sizeof(struct ubsec_mcr_add)); 795 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 796 q->q_stacked_mcr[i] = q2; 797 } 798 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 799 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 800 sc->sc_nqchip += npkts; 801 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 802 ubsecstats.hst_maxqchip = sc->sc_nqchip; 803 ubsec_dma_sync(&q->q_dma->d_alloc, 804 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 805 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 806 offsetof(struct ubsec_dmachunk, d_mcr)); 807 return; 808feed1: 809 q = SIMPLEQ_FIRST(&sc->sc_queue); 810 811 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 812 if (q->q_dst_map != NULL) 813 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 814 ubsec_dma_sync(&q->q_dma->d_alloc, 815 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 816 817 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 818 offsetof(struct ubsec_dmachunk, d_mcr)); 819#ifdef UBSEC_DEBUG 820 if (ubsec_debug) 821 printf("feed1: q->chip %p %08x stat %08x\n", 822 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr), 823 stat); 824#endif /* UBSEC_DEBUG */ 825 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 826 --sc->sc_nqueue; 827 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 828 sc->sc_nqchip++; 829 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 830 ubsecstats.hst_maxqchip = sc->sc_nqchip; 831 return; 832} 833 834static void 835ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key) 836{ 837 838 /* Go ahead and compute key in ubsec's byte order */ 839 if (algo == CRYPTO_DES_CBC) { 840 bcopy(key, &ses->ses_deskey[0], 8); 841 bcopy(key, &ses->ses_deskey[2], 8); 842 bcopy(key, &ses->ses_deskey[4], 8); 843 } else 844 bcopy(key, ses->ses_deskey, 24); 845 846 SWAP32(ses->ses_deskey[0]); 847 SWAP32(ses->ses_deskey[1]); 848 SWAP32(ses->ses_deskey[2]); 849 SWAP32(ses->ses_deskey[3]); 850 SWAP32(ses->ses_deskey[4]); 851 SWAP32(ses->ses_deskey[5]); 852} 853 854static void 855ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen) 856{ 857 MD5_CTX md5ctx; 858 SHA1_CTX sha1ctx; 859 int i; 860 861 for (i = 0; i < klen; i++) 862 key[i] ^= HMAC_IPAD_VAL; 863 864 if (algo == CRYPTO_MD5_HMAC) { 865 MD5Init(&md5ctx); 866 MD5Update(&md5ctx, key, klen); 867 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); 868 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state)); 869 } else { 870 SHA1Init(&sha1ctx); 871 SHA1Update(&sha1ctx, key, klen); 872 SHA1Update(&sha1ctx, hmac_ipad_buffer, 873 SHA1_HMAC_BLOCK_LEN - klen); 874 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); 875 } 876 877 for (i = 0; i < klen; i++) 878 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 879 880 if (algo == CRYPTO_MD5_HMAC) { 881 MD5Init(&md5ctx); 882 MD5Update(&md5ctx, key, klen); 883 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); 884 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state)); 885 } else { 886 SHA1Init(&sha1ctx); 887 SHA1Update(&sha1ctx, key, klen); 888 SHA1Update(&sha1ctx, hmac_opad_buffer, 889 SHA1_HMAC_BLOCK_LEN - klen); 890 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); 891 } 892 893 for (i = 0; i < klen; i++) 894 key[i] ^= HMAC_OPAD_VAL; 895} 896 897/* 898 * Allocate a new 'session' and return an encoded session id. 'sidp' 899 * contains our registration id, and should contain an encoded session 900 * id on successful allocation. 901 */ 902static int 903ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 904{ 905 struct cryptoini *c, *encini = NULL, *macini = NULL; 906 struct ubsec_softc *sc = arg; 907 struct ubsec_session *ses = NULL; 908 int sesn; 909 910 if (sidp == NULL || cri == NULL || sc == NULL) 911 return (EINVAL); 912 913 for (c = cri; c != NULL; c = c->cri_next) { 914 if (c->cri_alg == CRYPTO_MD5_HMAC || 915 c->cri_alg == CRYPTO_SHA1_HMAC) { 916 if (macini) 917 return (EINVAL); 918 macini = c; 919 } else if (c->cri_alg == CRYPTO_DES_CBC || 920 c->cri_alg == CRYPTO_3DES_CBC) { 921 if (encini) 922 return (EINVAL); 923 encini = c; 924 } else 925 return (EINVAL); 926 } 927 if (encini == NULL && macini == NULL) 928 return (EINVAL); 929 930 if (sc->sc_sessions == NULL) { 931 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 932 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 933 if (ses == NULL) 934 return (ENOMEM); 935 sesn = 0; 936 sc->sc_nsessions = 1; 937 } else { 938 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 939 if (sc->sc_sessions[sesn].ses_used == 0) { 940 ses = &sc->sc_sessions[sesn]; 941 break; 942 } 943 } 944 945 if (ses == NULL) { 946 sesn = sc->sc_nsessions; 947 ses = (struct ubsec_session *)malloc((sesn + 1) * 948 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 949 if (ses == NULL) 950 return (ENOMEM); 951 bcopy(sc->sc_sessions, ses, sesn * 952 sizeof(struct ubsec_session)); 953 bzero(sc->sc_sessions, sesn * 954 sizeof(struct ubsec_session)); 955 free(sc->sc_sessions, M_DEVBUF); 956 sc->sc_sessions = ses; 957 ses = &sc->sc_sessions[sesn]; 958 sc->sc_nsessions++; 959 } 960 } 961 bzero(ses, sizeof(struct ubsec_session)); 962 ses->ses_used = 1; 963 964 if (encini) { 965 /* get an IV, network byte order */ 966 /* XXX may read fewer than requested */ 967 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 968 969 if (encini->cri_key != NULL) { 970 ubsec_setup_enckey(ses, encini->cri_alg, 971 encini->cri_key); 972 } 973 } 974 975 if (macini) { 976 ses->ses_mlen = macini->cri_mlen; 977 if (ses->ses_mlen == 0) { 978 if (macini->cri_alg == CRYPTO_MD5_HMAC) 979 ses->ses_mlen = MD5_HASH_LEN; 980 else 981 ses->ses_mlen = SHA1_HASH_LEN; 982 } 983 984 if (macini->cri_key != NULL) { 985 ubsec_setup_mackey(ses, macini->cri_alg, 986 macini->cri_key, macini->cri_klen / 8); 987 } 988 } 989 990 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); 991 return (0); 992} 993 994/* 995 * Deallocate a session. 996 */ 997static int 998ubsec_freesession(void *arg, u_int64_t tid) 999{ 1000 struct ubsec_softc *sc = arg; 1001 int session, ret; 1002 u_int32_t sid = CRYPTO_SESID2LID(tid); 1003 1004 if (sc == NULL) 1005 return (EINVAL); 1006 1007 session = UBSEC_SESSION(sid); 1008 if (session < sc->sc_nsessions) { 1009 bzero(&sc->sc_sessions[session], 1010 sizeof(sc->sc_sessions[session])); 1011 ret = 0; 1012 } else 1013 ret = EINVAL; 1014 1015 return (ret); 1016} 1017 1018static void 1019ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1020{ 1021 struct ubsec_operand *op = arg; 1022 1023 KASSERT(nsegs <= UBS_MAX_SCATTER, 1024 ("Too many DMA segments returned when mapping operand")); 1025#ifdef UBSEC_DEBUG 1026 if (ubsec_debug) 1027 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 1028 (u_int) mapsize, nsegs); 1029#endif 1030 op->mapsize = mapsize; 1031 op->nsegs = nsegs; 1032 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1033} 1034 1035static int 1036ubsec_process(void *arg, struct cryptop *crp, int hint) 1037{ 1038 struct ubsec_q *q = NULL; 1039 int err = 0, i, j, nicealign; 1040 struct ubsec_softc *sc = arg; 1041 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1042 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1043 int sskip, dskip, stheend, dtheend; 1044 int16_t coffset; 1045 struct ubsec_session *ses; 1046 struct ubsec_pktctx ctx; 1047 struct ubsec_dma *dmap = NULL; 1048 1049 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1050 ubsecstats.hst_invalid++; 1051 return (EINVAL); 1052 } 1053 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1054 ubsecstats.hst_badsession++; 1055 return (EINVAL); 1056 } 1057 1058 mtx_lock(&sc->sc_freeqlock); 1059 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1060 ubsecstats.hst_queuefull++; 1061 sc->sc_needwakeup |= CRYPTO_SYMQ; 1062 mtx_unlock(&sc->sc_freeqlock); 1063 return (ERESTART); 1064 } 1065 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1066 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 1067 mtx_unlock(&sc->sc_freeqlock); 1068 1069 dmap = q->q_dma; /* Save dma pointer */ 1070 bzero(q, sizeof(struct ubsec_q)); 1071 bzero(&ctx, sizeof(ctx)); 1072 1073 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1074 q->q_dma = dmap; 1075 ses = &sc->sc_sessions[q->q_sesn]; 1076 1077 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1078 q->q_src_m = (struct mbuf *)crp->crp_buf; 1079 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1080 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1081 q->q_src_io = (struct uio *)crp->crp_buf; 1082 q->q_dst_io = (struct uio *)crp->crp_buf; 1083 } else { 1084 ubsecstats.hst_badflags++; 1085 err = EINVAL; 1086 goto errout; /* XXX we don't handle contiguous blocks! */ 1087 } 1088 1089 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 1090 1091 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1092 dmap->d_dma->d_mcr.mcr_flags = 0; 1093 q->q_crp = crp; 1094 1095 crd1 = crp->crp_desc; 1096 if (crd1 == NULL) { 1097 ubsecstats.hst_nodesc++; 1098 err = EINVAL; 1099 goto errout; 1100 } 1101 crd2 = crd1->crd_next; 1102 1103 if (crd2 == NULL) { 1104 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 1105 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 1106 maccrd = crd1; 1107 enccrd = NULL; 1108 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1109 crd1->crd_alg == CRYPTO_3DES_CBC) { 1110 maccrd = NULL; 1111 enccrd = crd1; 1112 } else { 1113 ubsecstats.hst_badalg++; 1114 err = EINVAL; 1115 goto errout; 1116 } 1117 } else { 1118 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1119 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1120 (crd2->crd_alg == CRYPTO_DES_CBC || 1121 crd2->crd_alg == CRYPTO_3DES_CBC) && 1122 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1123 maccrd = crd1; 1124 enccrd = crd2; 1125 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1126 crd1->crd_alg == CRYPTO_3DES_CBC) && 1127 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1128 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1129 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1130 enccrd = crd1; 1131 maccrd = crd2; 1132 } else { 1133 /* 1134 * We cannot order the ubsec as requested 1135 */ 1136 ubsecstats.hst_badalg++; 1137 err = EINVAL; 1138 goto errout; 1139 } 1140 } 1141 1142 if (enccrd) { 1143 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1144 ubsec_setup_enckey(ses, enccrd->crd_alg, 1145 enccrd->crd_key); 1146 } 1147 1148 encoffset = enccrd->crd_skip; 1149 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1150 1151 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1152 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1153 1154 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1155 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1156 else { 1157 ctx.pc_iv[0] = ses->ses_iv[0]; 1158 ctx.pc_iv[1] = ses->ses_iv[1]; 1159 } 1160 1161 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1162 crypto_copyback(crp->crp_flags, crp->crp_buf, 1163 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv); 1164 } 1165 } else { 1166 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1167 1168 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1169 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1170 else { 1171 crypto_copydata(crp->crp_flags, crp->crp_buf, 1172 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv); 1173 } 1174 } 1175 1176 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1177 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1178 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1179 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1180 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1181 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1182 SWAP32(ctx.pc_iv[0]); 1183 SWAP32(ctx.pc_iv[1]); 1184 } 1185 1186 if (maccrd) { 1187 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1188 ubsec_setup_mackey(ses, maccrd->crd_alg, 1189 maccrd->crd_key, maccrd->crd_klen / 8); 1190 } 1191 1192 macoffset = maccrd->crd_skip; 1193 1194 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1195 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1196 else 1197 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1198 1199 for (i = 0; i < 5; i++) { 1200 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1201 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1202 1203 HTOLE32(ctx.pc_hminner[i]); 1204 HTOLE32(ctx.pc_hmouter[i]); 1205 } 1206 } 1207 1208 if (enccrd && maccrd) { 1209 /* 1210 * ubsec cannot handle packets where the end of encryption 1211 * and authentication are not the same, or where the 1212 * encrypted part begins before the authenticated part. 1213 */ 1214 if ((encoffset + enccrd->crd_len) != 1215 (macoffset + maccrd->crd_len)) { 1216 ubsecstats.hst_lenmismatch++; 1217 err = EINVAL; 1218 goto errout; 1219 } 1220 if (enccrd->crd_skip < maccrd->crd_skip) { 1221 ubsecstats.hst_skipmismatch++; 1222 err = EINVAL; 1223 goto errout; 1224 } 1225 sskip = maccrd->crd_skip; 1226 cpskip = dskip = enccrd->crd_skip; 1227 stheend = maccrd->crd_len; 1228 dtheend = enccrd->crd_len; 1229 coffset = enccrd->crd_skip - maccrd->crd_skip; 1230 cpoffset = cpskip + dtheend; 1231#ifdef UBSEC_DEBUG 1232 if (ubsec_debug) { 1233 printf("mac: skip %d, len %d, inject %d\n", 1234 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1235 printf("enc: skip %d, len %d, inject %d\n", 1236 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1237 printf("src: skip %d, len %d\n", sskip, stheend); 1238 printf("dst: skip %d, len %d\n", dskip, dtheend); 1239 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1240 coffset, stheend, cpskip, cpoffset); 1241 } 1242#endif 1243 } else { 1244 cpskip = dskip = sskip = macoffset + encoffset; 1245 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1246 cpoffset = cpskip + dtheend; 1247 coffset = 0; 1248 } 1249 ctx.pc_offset = htole16(coffset >> 2); 1250 1251 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) { 1252 ubsecstats.hst_nomap++; 1253 err = ENOMEM; 1254 goto errout; 1255 } 1256 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1257 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1258 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1259 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1260 q->q_src_map = NULL; 1261 ubsecstats.hst_noload++; 1262 err = ENOMEM; 1263 goto errout; 1264 } 1265 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1266 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1267 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1268 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1269 q->q_src_map = NULL; 1270 ubsecstats.hst_noload++; 1271 err = ENOMEM; 1272 goto errout; 1273 } 1274 } 1275 nicealign = ubsec_dmamap_aligned(&q->q_src); 1276 1277 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1278 1279#ifdef UBSEC_DEBUG 1280 if (ubsec_debug) 1281 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1282#endif 1283 for (i = j = 0; i < q->q_src_nsegs; i++) { 1284 struct ubsec_pktbuf *pb; 1285 bus_size_t packl = q->q_src_segs[i].ds_len; 1286 bus_addr_t packp = q->q_src_segs[i].ds_addr; 1287 1288 if (sskip >= packl) { 1289 sskip -= packl; 1290 continue; 1291 } 1292 1293 packl -= sskip; 1294 packp += sskip; 1295 sskip = 0; 1296 1297 if (packl > 0xfffc) { 1298 err = EIO; 1299 goto errout; 1300 } 1301 1302 if (j == 0) 1303 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1304 else 1305 pb = &dmap->d_dma->d_sbuf[j - 1]; 1306 1307 pb->pb_addr = htole32(packp); 1308 1309 if (stheend) { 1310 if (packl > stheend) { 1311 pb->pb_len = htole32(stheend); 1312 stheend = 0; 1313 } else { 1314 pb->pb_len = htole32(packl); 1315 stheend -= packl; 1316 } 1317 } else 1318 pb->pb_len = htole32(packl); 1319 1320 if ((i + 1) == q->q_src_nsegs) 1321 pb->pb_next = 0; 1322 else 1323 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1324 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1325 j++; 1326 } 1327 1328 if (enccrd == NULL && maccrd != NULL) { 1329 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1330 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1331 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1332 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1333#ifdef UBSEC_DEBUG 1334 if (ubsec_debug) 1335 printf("opkt: %x %x %x\n", 1336 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1337 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1338 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1339#endif 1340 } else { 1341 if (crp->crp_flags & CRYPTO_F_IOV) { 1342 if (!nicealign) { 1343 ubsecstats.hst_iovmisaligned++; 1344 err = EINVAL; 1345 goto errout; 1346 } 1347 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1348 &q->q_dst_map)) { 1349 ubsecstats.hst_nomap++; 1350 err = ENOMEM; 1351 goto errout; 1352 } 1353 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1354 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) { 1355 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1356 q->q_dst_map = NULL; 1357 ubsecstats.hst_noload++; 1358 err = ENOMEM; 1359 goto errout; 1360 } 1361 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1362 if (nicealign) { 1363 q->q_dst = q->q_src; 1364 } else { 1365 int totlen, len; 1366 struct mbuf *m, *top, **mp; 1367 1368 ubsecstats.hst_unaligned++; 1369 totlen = q->q_src_mapsize; 1370 if (q->q_src_m->m_flags & M_PKTHDR) { 1371 len = MHLEN; 1372 MGETHDR(m, M_DONTWAIT, MT_DATA); 1373 if (m && !m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)) { 1374 m_free(m); 1375 m = NULL; 1376 } 1377 } else { 1378 len = MLEN; 1379 MGET(m, M_DONTWAIT, MT_DATA); 1380 } 1381 if (m == NULL) { 1382 ubsecstats.hst_nombuf++; 1383 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1384 goto errout; 1385 } 1386 if (totlen >= MINCLSIZE) { 1387 MCLGET(m, M_DONTWAIT); 1388 if ((m->m_flags & M_EXT) == 0) { 1389 m_free(m); 1390 ubsecstats.hst_nomcl++; 1391 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1392 goto errout; 1393 } 1394 len = MCLBYTES; 1395 } 1396 m->m_len = len; 1397 top = NULL; 1398 mp = ⊤ 1399 1400 while (totlen > 0) { 1401 if (top) { 1402 MGET(m, M_DONTWAIT, MT_DATA); 1403 if (m == NULL) { 1404 m_freem(top); 1405 ubsecstats.hst_nombuf++; 1406 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1407 goto errout; 1408 } 1409 len = MLEN; 1410 } 1411 if (top && totlen >= MINCLSIZE) { 1412 MCLGET(m, M_DONTWAIT); 1413 if ((m->m_flags & M_EXT) == 0) { 1414 *mp = m; 1415 m_freem(top); 1416 ubsecstats.hst_nomcl++; 1417 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1418 goto errout; 1419 } 1420 len = MCLBYTES; 1421 } 1422 m->m_len = len = min(totlen, len); 1423 totlen -= len; 1424 *mp = m; 1425 mp = &m->m_next; 1426 } 1427 q->q_dst_m = top; 1428 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1429 cpskip, cpoffset); 1430 if (bus_dmamap_create(sc->sc_dmat, 1431 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) { 1432 ubsecstats.hst_nomap++; 1433 err = ENOMEM; 1434 goto errout; 1435 } 1436 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1437 q->q_dst_map, q->q_dst_m, 1438 ubsec_op_cb, &q->q_dst, 1439 BUS_DMA_NOWAIT) != 0) { 1440 bus_dmamap_destroy(sc->sc_dmat, 1441 q->q_dst_map); 1442 q->q_dst_map = NULL; 1443 ubsecstats.hst_noload++; 1444 err = ENOMEM; 1445 goto errout; 1446 } 1447 } 1448 } else { 1449 ubsecstats.hst_badflags++; 1450 err = EINVAL; 1451 goto errout; 1452 } 1453 1454#ifdef UBSEC_DEBUG 1455 if (ubsec_debug) 1456 printf("dst skip: %d\n", dskip); 1457#endif 1458 for (i = j = 0; i < q->q_dst_nsegs; i++) { 1459 struct ubsec_pktbuf *pb; 1460 bus_size_t packl = q->q_dst_segs[i].ds_len; 1461 bus_addr_t packp = q->q_dst_segs[i].ds_addr; 1462 1463 if (dskip >= packl) { 1464 dskip -= packl; 1465 continue; 1466 } 1467 1468 packl -= dskip; 1469 packp += dskip; 1470 dskip = 0; 1471 1472 if (packl > 0xfffc) { 1473 err = EIO; 1474 goto errout; 1475 } 1476 1477 if (j == 0) 1478 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1479 else 1480 pb = &dmap->d_dma->d_dbuf[j - 1]; 1481 1482 pb->pb_addr = htole32(packp); 1483 1484 if (dtheend) { 1485 if (packl > dtheend) { 1486 pb->pb_len = htole32(dtheend); 1487 dtheend = 0; 1488 } else { 1489 pb->pb_len = htole32(packl); 1490 dtheend -= packl; 1491 } 1492 } else 1493 pb->pb_len = htole32(packl); 1494 1495 if ((i + 1) == q->q_dst_nsegs) { 1496 if (maccrd) 1497 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1498 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1499 else 1500 pb->pb_next = 0; 1501 } else 1502 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1503 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1504 j++; 1505 } 1506 } 1507 1508 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1509 offsetof(struct ubsec_dmachunk, d_ctx)); 1510 1511 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1512 struct ubsec_pktctx_long *ctxl; 1513 1514 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr + 1515 offsetof(struct ubsec_dmachunk, d_ctx)); 1516 1517 /* transform small context into long context */ 1518 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1519 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1520 ctxl->pc_flags = ctx.pc_flags; 1521 ctxl->pc_offset = ctx.pc_offset; 1522 for (i = 0; i < 6; i++) 1523 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1524 for (i = 0; i < 5; i++) 1525 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1526 for (i = 0; i < 5; i++) 1527 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1528 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1529 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1530 } else 1531 bcopy(&ctx, dmap->d_alloc.dma_vaddr + 1532 offsetof(struct ubsec_dmachunk, d_ctx), 1533 sizeof(struct ubsec_pktctx)); 1534 1535 mtx_lock(&sc->sc_mcr1lock); 1536 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1537 sc->sc_nqueue++; 1538 ubsecstats.hst_ipackets++; 1539 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size; 1540 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR) 1541 ubsec_feed(sc); 1542 mtx_unlock(&sc->sc_mcr1lock); 1543 return (0); 1544 1545errout: 1546 if (q != NULL) { 1547 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1548 m_freem(q->q_dst_m); 1549 1550 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1551 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1552 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1553 } 1554 if (q->q_src_map != NULL) { 1555 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1556 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1557 } 1558 } 1559 if (q != NULL || err == ERESTART) { 1560 mtx_lock(&sc->sc_freeqlock); 1561 if (q != NULL) 1562 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1563 if (err == ERESTART) 1564 sc->sc_needwakeup |= CRYPTO_SYMQ; 1565 mtx_unlock(&sc->sc_freeqlock); 1566 } 1567 if (err != ERESTART) { 1568 crp->crp_etype = err; 1569 crypto_done(crp); 1570 } 1571 return (err); 1572} 1573 1574static void 1575ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1576{ 1577 struct cryptop *crp = (struct cryptop *)q->q_crp; 1578 struct cryptodesc *crd; 1579 struct ubsec_dma *dmap = q->q_dma; 1580 1581 ubsecstats.hst_opackets++; 1582 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1583 1584 ubsec_dma_sync(&dmap->d_alloc, 1585 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1586 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1587 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1588 BUS_DMASYNC_POSTREAD); 1589 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1590 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1591 } 1592 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE); 1593 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1594 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1595 1596 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1597 m_freem(q->q_src_m); 1598 crp->crp_buf = (caddr_t)q->q_dst_m; 1599 } 1600 1601 /* copy out IV for future use */ 1602 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1603 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1604 if (crd->crd_alg != CRYPTO_DES_CBC && 1605 crd->crd_alg != CRYPTO_3DES_CBC) 1606 continue; 1607 crypto_copydata(crp->crp_flags, crp->crp_buf, 1608 crd->crd_skip + crd->crd_len - 8, 8, 1609 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1610 break; 1611 } 1612 } 1613 1614 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1615 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1616 crd->crd_alg != CRYPTO_SHA1_HMAC) 1617 continue; 1618 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, 1619 sc->sc_sessions[q->q_sesn].ses_mlen, 1620 (caddr_t)dmap->d_dma->d_macbuf); 1621 break; 1622 } 1623 mtx_lock(&sc->sc_freeqlock); 1624 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1625 mtx_unlock(&sc->sc_freeqlock); 1626 crypto_done(crp); 1627} 1628 1629static void 1630ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1631{ 1632 int i, j, dlen, slen; 1633 caddr_t dptr, sptr; 1634 1635 j = 0; 1636 sptr = srcm->m_data; 1637 slen = srcm->m_len; 1638 dptr = dstm->m_data; 1639 dlen = dstm->m_len; 1640 1641 while (1) { 1642 for (i = 0; i < min(slen, dlen); i++) { 1643 if (j < hoffset || j >= toffset) 1644 *dptr++ = *sptr++; 1645 slen--; 1646 dlen--; 1647 j++; 1648 } 1649 if (slen == 0) { 1650 srcm = srcm->m_next; 1651 if (srcm == NULL) 1652 return; 1653 sptr = srcm->m_data; 1654 slen = srcm->m_len; 1655 } 1656 if (dlen == 0) { 1657 dstm = dstm->m_next; 1658 if (dstm == NULL) 1659 return; 1660 dptr = dstm->m_data; 1661 dlen = dstm->m_len; 1662 } 1663 } 1664} 1665 1666/* 1667 * feed the key generator, must be called at splimp() or higher. 1668 */ 1669static int 1670ubsec_feed2(struct ubsec_softc *sc) 1671{ 1672 struct ubsec_q2 *q; 1673 1674 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1675 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1676 break; 1677 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1678 1679 ubsec_dma_sync(&q->q_mcr, 1680 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1681 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE); 1682 1683 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1684 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next); 1685 --sc->sc_nqueue2; 1686 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1687 } 1688 return (0); 1689} 1690 1691/* 1692 * Callback for handling random numbers 1693 */ 1694static void 1695ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1696{ 1697 struct cryptkop *krp; 1698 struct ubsec_ctx_keyop *ctx; 1699 1700 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1701 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE); 1702 1703 switch (q->q_type) { 1704#ifndef UBSEC_NO_RNG 1705 case UBS_CTXOP_RNGBYPASS: { 1706 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1707 1708 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD); 1709 (*sc->sc_harvest)(sc->sc_rndtest, 1710 rng->rng_buf.dma_vaddr, 1711 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t)); 1712 rng->rng_used = 0; 1713 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1714 break; 1715 } 1716#endif 1717 case UBS_CTXOP_MODEXP: { 1718 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1719 u_int rlen, clen; 1720 1721 krp = me->me_krp; 1722 rlen = (me->me_modbits + 7) / 8; 1723 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1724 1725 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE); 1726 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE); 1727 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD); 1728 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE); 1729 1730 if (clen < rlen) 1731 krp->krp_status = E2BIG; 1732 else { 1733 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1734 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1735 (krp->krp_param[krp->krp_iparams].crp_nbits 1736 + 7) / 8); 1737 bcopy(me->me_C.dma_vaddr, 1738 krp->krp_param[krp->krp_iparams].crp_p, 1739 (me->me_modbits + 7) / 8); 1740 } else 1741 ubsec_kshift_l(me->me_shiftbits, 1742 me->me_C.dma_vaddr, me->me_normbits, 1743 krp->krp_param[krp->krp_iparams].crp_p, 1744 krp->krp_param[krp->krp_iparams].crp_nbits); 1745 } 1746 1747 crypto_kdone(krp); 1748 1749 /* bzero all potentially sensitive data */ 1750 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1751 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1752 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1753 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1754 1755 /* Can't free here, so put us on the free list. */ 1756 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1757 break; 1758 } 1759 case UBS_CTXOP_RSAPRIV: { 1760 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1761 u_int len; 1762 1763 krp = rp->rpr_krp; 1764 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE); 1765 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD); 1766 1767 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1768 bcopy(rp->rpr_msgout.dma_vaddr, 1769 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1770 1771 crypto_kdone(krp); 1772 1773 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1774 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1775 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1776 1777 /* Can't free here, so put us on the free list. */ 1778 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1779 break; 1780 } 1781 default: 1782 device_printf(sc->sc_dev, "unknown ctx op: %x\n", 1783 letoh16(ctx->ctx_op)); 1784 break; 1785 } 1786} 1787 1788#ifndef UBSEC_NO_RNG 1789static void 1790ubsec_rng(void *vsc) 1791{ 1792 struct ubsec_softc *sc = vsc; 1793 struct ubsec_q2_rng *rng = &sc->sc_rng; 1794 struct ubsec_mcr *mcr; 1795 struct ubsec_ctx_rngbypass *ctx; 1796 1797 mtx_lock(&sc->sc_mcr2lock); 1798 if (rng->rng_used) { 1799 mtx_unlock(&sc->sc_mcr2lock); 1800 return; 1801 } 1802 sc->sc_nqueue2++; 1803 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1804 goto out; 1805 1806 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1807 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1808 1809 mcr->mcr_pkts = htole16(1); 1810 mcr->mcr_flags = 0; 1811 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1812 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1813 mcr->mcr_ipktbuf.pb_len = 0; 1814 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1815 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1816 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1817 UBS_PKTBUF_LEN); 1818 mcr->mcr_opktbuf.pb_next = 0; 1819 1820 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1821 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS); 1822 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS; 1823 1824 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD); 1825 1826 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1827 rng->rng_used = 1; 1828 ubsec_feed2(sc); 1829 ubsecstats.hst_rng++; 1830 mtx_unlock(&sc->sc_mcr2lock); 1831 1832 return; 1833 1834out: 1835 /* 1836 * Something weird happened, generate our own call back. 1837 */ 1838 sc->sc_nqueue2--; 1839 mtx_unlock(&sc->sc_mcr2lock); 1840 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1841} 1842#endif /* UBSEC_NO_RNG */ 1843 1844static void 1845ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1846{ 1847 bus_addr_t *paddr = (bus_addr_t*) arg; 1848 *paddr = segs->ds_addr; 1849} 1850 1851static int 1852ubsec_dma_malloc( 1853 struct ubsec_softc *sc, 1854 bus_size_t size, 1855 struct ubsec_dma_alloc *dma, 1856 int mapflags 1857) 1858{ 1859 int r; 1860 1861 /* XXX could specify sc_dmat as parent but that just adds overhead */ 1862 r = bus_dma_tag_create(NULL, /* parent */ 1863 1, 0, /* alignment, bounds */ 1864 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1865 BUS_SPACE_MAXADDR, /* highaddr */ 1866 NULL, NULL, /* filter, filterarg */ 1867 size, /* maxsize */ 1868 1, /* nsegments */ 1869 size, /* maxsegsize */ 1870 BUS_DMA_ALLOCNOW, /* flags */ 1871 NULL, NULL, /* lockfunc, lockarg */ 1872 &dma->dma_tag); 1873 if (r != 0) { 1874 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1875 "bus_dma_tag_create failed; error %u\n", r); 1876 goto fail_0; 1877 } 1878 1879 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1880 if (r != 0) { 1881 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1882 "bus_dmamap_create failed; error %u\n", r); 1883 goto fail_1; 1884 } 1885 1886 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1887 BUS_DMA_NOWAIT, &dma->dma_map); 1888 if (r != 0) { 1889 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1890 "bus_dmammem_alloc failed; size %zu, error %u\n", 1891 size, r); 1892 goto fail_2; 1893 } 1894 1895 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1896 size, 1897 ubsec_dmamap_cb, 1898 &dma->dma_paddr, 1899 mapflags | BUS_DMA_NOWAIT); 1900 if (r != 0) { 1901 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1902 "bus_dmamap_load failed; error %u\n", r); 1903 goto fail_3; 1904 } 1905 1906 dma->dma_size = size; 1907 return (0); 1908 1909fail_3: 1910 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1911fail_2: 1912 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1913fail_1: 1914 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1915 bus_dma_tag_destroy(dma->dma_tag); 1916fail_0: 1917 dma->dma_map = NULL; 1918 dma->dma_tag = NULL; 1919 return (r); 1920} 1921 1922static void 1923ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1924{ 1925 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1926 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1927 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1928 bus_dma_tag_destroy(dma->dma_tag); 1929} 1930 1931/* 1932 * Resets the board. Values in the regesters are left as is 1933 * from the reset (i.e. initial values are assigned elsewhere). 1934 */ 1935static void 1936ubsec_reset_board(struct ubsec_softc *sc) 1937{ 1938 volatile u_int32_t ctrl; 1939 1940 ctrl = READ_REG(sc, BS_CTRL); 1941 ctrl |= BS_CTRL_RESET; 1942 WRITE_REG(sc, BS_CTRL, ctrl); 1943 1944 /* 1945 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1946 */ 1947 DELAY(10); 1948} 1949 1950/* 1951 * Init Broadcom registers 1952 */ 1953static void 1954ubsec_init_board(struct ubsec_softc *sc) 1955{ 1956 u_int32_t ctrl; 1957 1958 ctrl = READ_REG(sc, BS_CTRL); 1959 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1960 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1961 1962 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) 1963 ctrl |= BS_CTRL_MCR2INT; 1964 else 1965 ctrl &= ~BS_CTRL_MCR2INT; 1966 1967 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1968 ctrl &= ~BS_CTRL_SWNORM; 1969 1970 WRITE_REG(sc, BS_CTRL, ctrl); 1971} 1972 1973/* 1974 * Init Broadcom PCI registers 1975 */ 1976static void 1977ubsec_init_pciregs(device_t dev) 1978{ 1979#if 0 1980 u_int32_t misc; 1981 1982 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT); 1983 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT)) 1984 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT); 1985 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT)) 1986 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT); 1987 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc); 1988#endif 1989 1990 /* 1991 * This will set the cache line size to 1, this will 1992 * force the BCM58xx chip just to do burst read/writes. 1993 * Cache line read/writes are to slow 1994 */ 1995 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1); 1996} 1997 1998/* 1999 * Clean up after a chip crash. 2000 * It is assumed that the caller in splimp() 2001 */ 2002static void 2003ubsec_cleanchip(struct ubsec_softc *sc) 2004{ 2005 struct ubsec_q *q; 2006 2007 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 2008 q = SIMPLEQ_FIRST(&sc->sc_qchip); 2009 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 2010 ubsec_free_q(sc, q); 2011 } 2012 sc->sc_nqchip = 0; 2013} 2014 2015/* 2016 * free a ubsec_q 2017 * It is assumed that the caller is within splimp(). 2018 */ 2019static int 2020ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2021{ 2022 struct ubsec_q *q2; 2023 struct cryptop *crp; 2024 int npkts; 2025 int i; 2026 2027 npkts = q->q_nstacked_mcrs; 2028 2029 for (i = 0; i < npkts; i++) { 2030 if(q->q_stacked_mcr[i]) { 2031 q2 = q->q_stacked_mcr[i]; 2032 2033 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 2034 m_freem(q2->q_dst_m); 2035 2036 crp = (struct cryptop *)q2->q_crp; 2037 2038 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2039 2040 crp->crp_etype = EFAULT; 2041 crypto_done(crp); 2042 } else { 2043 break; 2044 } 2045 } 2046 2047 /* 2048 * Free header MCR 2049 */ 2050 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2051 m_freem(q->q_dst_m); 2052 2053 crp = (struct cryptop *)q->q_crp; 2054 2055 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2056 2057 crp->crp_etype = EFAULT; 2058 crypto_done(crp); 2059 return(0); 2060} 2061 2062/* 2063 * Routine to reset the chip and clean up. 2064 * It is assumed that the caller is in splimp() 2065 */ 2066static void 2067ubsec_totalreset(struct ubsec_softc *sc) 2068{ 2069 ubsec_reset_board(sc); 2070 ubsec_init_board(sc); 2071 ubsec_cleanchip(sc); 2072} 2073 2074static int 2075ubsec_dmamap_aligned(struct ubsec_operand *op) 2076{ 2077 int i; 2078 2079 for (i = 0; i < op->nsegs; i++) { 2080 if (op->segs[i].ds_addr & 3) 2081 return (0); 2082 if ((i != (op->nsegs - 1)) && 2083 (op->segs[i].ds_len & 3)) 2084 return (0); 2085 } 2086 return (1); 2087} 2088 2089static void 2090ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2091{ 2092 switch (q->q_type) { 2093 case UBS_CTXOP_MODEXP: { 2094 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2095 2096 ubsec_dma_free(sc, &me->me_q.q_mcr); 2097 ubsec_dma_free(sc, &me->me_q.q_ctx); 2098 ubsec_dma_free(sc, &me->me_M); 2099 ubsec_dma_free(sc, &me->me_E); 2100 ubsec_dma_free(sc, &me->me_C); 2101 ubsec_dma_free(sc, &me->me_epb); 2102 free(me, M_DEVBUF); 2103 break; 2104 } 2105 case UBS_CTXOP_RSAPRIV: { 2106 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2107 2108 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2109 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2110 ubsec_dma_free(sc, &rp->rpr_msgin); 2111 ubsec_dma_free(sc, &rp->rpr_msgout); 2112 free(rp, M_DEVBUF); 2113 break; 2114 } 2115 default: 2116 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type); 2117 break; 2118 } 2119} 2120 2121static int 2122ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2123{ 2124 struct ubsec_softc *sc = arg; 2125 int r; 2126 2127 if (krp == NULL || krp->krp_callback == NULL) 2128 return (EINVAL); 2129 2130 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2131 struct ubsec_q2 *q; 2132 2133 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2134 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next); 2135 ubsec_kfree(sc, q); 2136 } 2137 2138 switch (krp->krp_op) { 2139 case CRK_MOD_EXP: 2140 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2141 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2142 else 2143 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2144 break; 2145 case CRK_MOD_EXP_CRT: 2146 return (ubsec_kprocess_rsapriv(sc, krp, hint)); 2147 default: 2148 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n", 2149 krp->krp_op); 2150 krp->krp_status = EOPNOTSUPP; 2151 crypto_kdone(krp); 2152 return (0); 2153 } 2154 return (0); /* silence compiler */ 2155} 2156 2157/* 2158 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2159 */ 2160static int 2161ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2162{ 2163 struct ubsec_q2_modexp *me; 2164 struct ubsec_mcr *mcr; 2165 struct ubsec_ctx_modexp *ctx; 2166 struct ubsec_pktbuf *epb; 2167 int err = 0; 2168 u_int nbits, normbits, mbits, shiftbits, ebits; 2169 2170 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2171 if (me == NULL) { 2172 err = ENOMEM; 2173 goto errout; 2174 } 2175 bzero(me, sizeof *me); 2176 me->me_krp = krp; 2177 me->me_q.q_type = UBS_CTXOP_MODEXP; 2178 2179 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2180 if (nbits <= 512) 2181 normbits = 512; 2182 else if (nbits <= 768) 2183 normbits = 768; 2184 else if (nbits <= 1024) 2185 normbits = 1024; 2186 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2187 normbits = 1536; 2188 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2189 normbits = 2048; 2190 else { 2191 err = E2BIG; 2192 goto errout; 2193 } 2194 2195 shiftbits = normbits - nbits; 2196 2197 me->me_modbits = nbits; 2198 me->me_shiftbits = shiftbits; 2199 me->me_normbits = normbits; 2200 2201 /* Sanity check: result bits must be >= true modulus bits. */ 2202 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2203 err = ERANGE; 2204 goto errout; 2205 } 2206 2207 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2208 &me->me_q.q_mcr, 0)) { 2209 err = ENOMEM; 2210 goto errout; 2211 } 2212 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2213 2214 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2215 &me->me_q.q_ctx, 0)) { 2216 err = ENOMEM; 2217 goto errout; 2218 } 2219 2220 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2221 if (mbits > nbits) { 2222 err = E2BIG; 2223 goto errout; 2224 } 2225 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2226 err = ENOMEM; 2227 goto errout; 2228 } 2229 ubsec_kshift_r(shiftbits, 2230 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2231 me->me_M.dma_vaddr, normbits); 2232 2233 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2234 err = ENOMEM; 2235 goto errout; 2236 } 2237 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2238 2239 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2240 if (ebits > nbits) { 2241 err = E2BIG; 2242 goto errout; 2243 } 2244 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2245 err = ENOMEM; 2246 goto errout; 2247 } 2248 ubsec_kshift_r(shiftbits, 2249 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2250 me->me_E.dma_vaddr, normbits); 2251 2252 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2253 &me->me_epb, 0)) { 2254 err = ENOMEM; 2255 goto errout; 2256 } 2257 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2258 epb->pb_addr = htole32(me->me_E.dma_paddr); 2259 epb->pb_next = 0; 2260 epb->pb_len = htole32(normbits / 8); 2261 2262#ifdef UBSEC_DEBUG 2263 if (ubsec_debug) { 2264 printf("Epb "); 2265 ubsec_dump_pb(epb); 2266 } 2267#endif 2268 2269 mcr->mcr_pkts = htole16(1); 2270 mcr->mcr_flags = 0; 2271 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2272 mcr->mcr_reserved = 0; 2273 mcr->mcr_pktlen = 0; 2274 2275 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2276 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2277 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2278 2279 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2280 mcr->mcr_opktbuf.pb_next = 0; 2281 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2282 2283#ifdef DIAGNOSTIC 2284 /* Misaligned output buffer will hang the chip. */ 2285 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2286 panic("%s: modexp invalid addr 0x%x\n", 2287 device_get_nameunit(sc->sc_dev), 2288 letoh32(mcr->mcr_opktbuf.pb_addr)); 2289 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2290 panic("%s: modexp invalid len 0x%x\n", 2291 device_get_nameunit(sc->sc_dev), 2292 letoh32(mcr->mcr_opktbuf.pb_len)); 2293#endif 2294 2295 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2296 bzero(ctx, sizeof(*ctx)); 2297 ubsec_kshift_r(shiftbits, 2298 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2299 ctx->me_N, normbits); 2300 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2301 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2302 ctx->me_E_len = htole16(nbits); 2303 ctx->me_N_len = htole16(nbits); 2304 2305#ifdef UBSEC_DEBUG 2306 if (ubsec_debug) { 2307 ubsec_dump_mcr(mcr); 2308 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2309 } 2310#endif 2311 2312 /* 2313 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2314 * everything else. 2315 */ 2316 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2317 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2318 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2319 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2320 2321 /* Enqueue and we're done... */ 2322 mtx_lock(&sc->sc_mcr2lock); 2323 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2324 ubsec_feed2(sc); 2325 ubsecstats.hst_modexp++; 2326 mtx_unlock(&sc->sc_mcr2lock); 2327 2328 return (0); 2329 2330errout: 2331 if (me != NULL) { 2332 if (me->me_q.q_mcr.dma_map != NULL) 2333 ubsec_dma_free(sc, &me->me_q.q_mcr); 2334 if (me->me_q.q_ctx.dma_map != NULL) { 2335 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2336 ubsec_dma_free(sc, &me->me_q.q_ctx); 2337 } 2338 if (me->me_M.dma_map != NULL) { 2339 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2340 ubsec_dma_free(sc, &me->me_M); 2341 } 2342 if (me->me_E.dma_map != NULL) { 2343 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2344 ubsec_dma_free(sc, &me->me_E); 2345 } 2346 if (me->me_C.dma_map != NULL) { 2347 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2348 ubsec_dma_free(sc, &me->me_C); 2349 } 2350 if (me->me_epb.dma_map != NULL) 2351 ubsec_dma_free(sc, &me->me_epb); 2352 free(me, M_DEVBUF); 2353 } 2354 krp->krp_status = err; 2355 crypto_kdone(krp); 2356 return (0); 2357} 2358 2359/* 2360 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2361 */ 2362static int 2363ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2364{ 2365 struct ubsec_q2_modexp *me; 2366 struct ubsec_mcr *mcr; 2367 struct ubsec_ctx_modexp *ctx; 2368 struct ubsec_pktbuf *epb; 2369 int err = 0; 2370 u_int nbits, normbits, mbits, shiftbits, ebits; 2371 2372 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2373 if (me == NULL) { 2374 err = ENOMEM; 2375 goto errout; 2376 } 2377 bzero(me, sizeof *me); 2378 me->me_krp = krp; 2379 me->me_q.q_type = UBS_CTXOP_MODEXP; 2380 2381 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2382 if (nbits <= 512) 2383 normbits = 512; 2384 else if (nbits <= 768) 2385 normbits = 768; 2386 else if (nbits <= 1024) 2387 normbits = 1024; 2388 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2389 normbits = 1536; 2390 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2391 normbits = 2048; 2392 else { 2393 err = E2BIG; 2394 goto errout; 2395 } 2396 2397 shiftbits = normbits - nbits; 2398 2399 /* XXX ??? */ 2400 me->me_modbits = nbits; 2401 me->me_shiftbits = shiftbits; 2402 me->me_normbits = normbits; 2403 2404 /* Sanity check: result bits must be >= true modulus bits. */ 2405 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2406 err = ERANGE; 2407 goto errout; 2408 } 2409 2410 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2411 &me->me_q.q_mcr, 0)) { 2412 err = ENOMEM; 2413 goto errout; 2414 } 2415 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2416 2417 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2418 &me->me_q.q_ctx, 0)) { 2419 err = ENOMEM; 2420 goto errout; 2421 } 2422 2423 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2424 if (mbits > nbits) { 2425 err = E2BIG; 2426 goto errout; 2427 } 2428 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2429 err = ENOMEM; 2430 goto errout; 2431 } 2432 bzero(me->me_M.dma_vaddr, normbits / 8); 2433 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2434 me->me_M.dma_vaddr, (mbits + 7) / 8); 2435 2436 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2437 err = ENOMEM; 2438 goto errout; 2439 } 2440 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2441 2442 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2443 if (ebits > nbits) { 2444 err = E2BIG; 2445 goto errout; 2446 } 2447 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2448 err = ENOMEM; 2449 goto errout; 2450 } 2451 bzero(me->me_E.dma_vaddr, normbits / 8); 2452 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2453 me->me_E.dma_vaddr, (ebits + 7) / 8); 2454 2455 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2456 &me->me_epb, 0)) { 2457 err = ENOMEM; 2458 goto errout; 2459 } 2460 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2461 epb->pb_addr = htole32(me->me_E.dma_paddr); 2462 epb->pb_next = 0; 2463 epb->pb_len = htole32((ebits + 7) / 8); 2464 2465#ifdef UBSEC_DEBUG 2466 if (ubsec_debug) { 2467 printf("Epb "); 2468 ubsec_dump_pb(epb); 2469 } 2470#endif 2471 2472 mcr->mcr_pkts = htole16(1); 2473 mcr->mcr_flags = 0; 2474 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2475 mcr->mcr_reserved = 0; 2476 mcr->mcr_pktlen = 0; 2477 2478 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2479 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2480 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2481 2482 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2483 mcr->mcr_opktbuf.pb_next = 0; 2484 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2485 2486#ifdef DIAGNOSTIC 2487 /* Misaligned output buffer will hang the chip. */ 2488 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2489 panic("%s: modexp invalid addr 0x%x\n", 2490 device_get_nameunit(sc->sc_dev), 2491 letoh32(mcr->mcr_opktbuf.pb_addr)); 2492 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2493 panic("%s: modexp invalid len 0x%x\n", 2494 device_get_nameunit(sc->sc_dev), 2495 letoh32(mcr->mcr_opktbuf.pb_len)); 2496#endif 2497 2498 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2499 bzero(ctx, sizeof(*ctx)); 2500 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2501 (nbits + 7) / 8); 2502 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2503 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2504 ctx->me_E_len = htole16(ebits); 2505 ctx->me_N_len = htole16(nbits); 2506 2507#ifdef UBSEC_DEBUG 2508 if (ubsec_debug) { 2509 ubsec_dump_mcr(mcr); 2510 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2511 } 2512#endif 2513 2514 /* 2515 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2516 * everything else. 2517 */ 2518 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2519 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2520 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2521 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2522 2523 /* Enqueue and we're done... */ 2524 mtx_lock(&sc->sc_mcr2lock); 2525 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2526 ubsec_feed2(sc); 2527 mtx_unlock(&sc->sc_mcr2lock); 2528 2529 return (0); 2530 2531errout: 2532 if (me != NULL) { 2533 if (me->me_q.q_mcr.dma_map != NULL) 2534 ubsec_dma_free(sc, &me->me_q.q_mcr); 2535 if (me->me_q.q_ctx.dma_map != NULL) { 2536 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2537 ubsec_dma_free(sc, &me->me_q.q_ctx); 2538 } 2539 if (me->me_M.dma_map != NULL) { 2540 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2541 ubsec_dma_free(sc, &me->me_M); 2542 } 2543 if (me->me_E.dma_map != NULL) { 2544 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2545 ubsec_dma_free(sc, &me->me_E); 2546 } 2547 if (me->me_C.dma_map != NULL) { 2548 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2549 ubsec_dma_free(sc, &me->me_C); 2550 } 2551 if (me->me_epb.dma_map != NULL) 2552 ubsec_dma_free(sc, &me->me_epb); 2553 free(me, M_DEVBUF); 2554 } 2555 krp->krp_status = err; 2556 crypto_kdone(krp); 2557 return (0); 2558} 2559 2560static int 2561ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2562{ 2563 struct ubsec_q2_rsapriv *rp = NULL; 2564 struct ubsec_mcr *mcr; 2565 struct ubsec_ctx_rsapriv *ctx; 2566 int err = 0; 2567 u_int padlen, msglen; 2568 2569 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2570 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2571 if (msglen > padlen) 2572 padlen = msglen; 2573 2574 if (padlen <= 256) 2575 padlen = 256; 2576 else if (padlen <= 384) 2577 padlen = 384; 2578 else if (padlen <= 512) 2579 padlen = 512; 2580 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2581 padlen = 768; 2582 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2583 padlen = 1024; 2584 else { 2585 err = E2BIG; 2586 goto errout; 2587 } 2588 2589 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2590 err = E2BIG; 2591 goto errout; 2592 } 2593 2594 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2595 err = E2BIG; 2596 goto errout; 2597 } 2598 2599 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2600 err = E2BIG; 2601 goto errout; 2602 } 2603 2604 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT); 2605 if (rp == NULL) 2606 return (ENOMEM); 2607 bzero(rp, sizeof *rp); 2608 rp->rpr_krp = krp; 2609 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2610 2611 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2612 &rp->rpr_q.q_mcr, 0)) { 2613 err = ENOMEM; 2614 goto errout; 2615 } 2616 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2617 2618 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2619 &rp->rpr_q.q_ctx, 0)) { 2620 err = ENOMEM; 2621 goto errout; 2622 } 2623 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2624 bzero(ctx, sizeof *ctx); 2625 2626 /* Copy in p */ 2627 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2628 &ctx->rpr_buf[0 * (padlen / 8)], 2629 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2630 2631 /* Copy in q */ 2632 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2633 &ctx->rpr_buf[1 * (padlen / 8)], 2634 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2635 2636 /* Copy in dp */ 2637 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2638 &ctx->rpr_buf[2 * (padlen / 8)], 2639 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2640 2641 /* Copy in dq */ 2642 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2643 &ctx->rpr_buf[3 * (padlen / 8)], 2644 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2645 2646 /* Copy in pinv */ 2647 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2648 &ctx->rpr_buf[4 * (padlen / 8)], 2649 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2650 2651 msglen = padlen * 2; 2652 2653 /* Copy in input message (aligned buffer/length). */ 2654 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2655 /* Is this likely? */ 2656 err = E2BIG; 2657 goto errout; 2658 } 2659 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2660 err = ENOMEM; 2661 goto errout; 2662 } 2663 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2664 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2665 rp->rpr_msgin.dma_vaddr, 2666 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2667 2668 /* Prepare space for output message (aligned buffer/length). */ 2669 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2670 /* Is this likely? */ 2671 err = E2BIG; 2672 goto errout; 2673 } 2674 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2675 err = ENOMEM; 2676 goto errout; 2677 } 2678 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2679 2680 mcr->mcr_pkts = htole16(1); 2681 mcr->mcr_flags = 0; 2682 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2683 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2684 mcr->mcr_ipktbuf.pb_next = 0; 2685 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2686 mcr->mcr_reserved = 0; 2687 mcr->mcr_pktlen = htole16(msglen); 2688 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2689 mcr->mcr_opktbuf.pb_next = 0; 2690 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2691 2692#ifdef DIAGNOSTIC 2693 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2694 panic("%s: rsapriv: invalid msgin %x(0x%jx)", 2695 device_get_nameunit(sc->sc_dev), 2696 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size); 2697 } 2698 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2699 panic("%s: rsapriv: invalid msgout %x(0x%jx)", 2700 device_get_nameunit(sc->sc_dev), 2701 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size); 2702 } 2703#endif 2704 2705 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2706 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2707 ctx->rpr_q_len = htole16(padlen); 2708 ctx->rpr_p_len = htole16(padlen); 2709 2710 /* 2711 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2712 * everything else. 2713 */ 2714 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE); 2715 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD); 2716 2717 /* Enqueue and we're done... */ 2718 mtx_lock(&sc->sc_mcr2lock); 2719 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2720 ubsec_feed2(sc); 2721 ubsecstats.hst_modexpcrt++; 2722 mtx_unlock(&sc->sc_mcr2lock); 2723 return (0); 2724 2725errout: 2726 if (rp != NULL) { 2727 if (rp->rpr_q.q_mcr.dma_map != NULL) 2728 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2729 if (rp->rpr_msgin.dma_map != NULL) { 2730 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2731 ubsec_dma_free(sc, &rp->rpr_msgin); 2732 } 2733 if (rp->rpr_msgout.dma_map != NULL) { 2734 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2735 ubsec_dma_free(sc, &rp->rpr_msgout); 2736 } 2737 free(rp, M_DEVBUF); 2738 } 2739 krp->krp_status = err; 2740 crypto_kdone(krp); 2741 return (0); 2742} 2743 2744#ifdef UBSEC_DEBUG 2745static void 2746ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2747{ 2748 printf("addr 0x%x (0x%x) next 0x%x\n", 2749 pb->pb_addr, pb->pb_len, pb->pb_next); 2750} 2751 2752static void 2753ubsec_dump_ctx2(struct ubsec_ctx_keyop *c) 2754{ 2755 printf("CTX (0x%x):\n", c->ctx_len); 2756 switch (letoh16(c->ctx_op)) { 2757 case UBS_CTXOP_RNGBYPASS: 2758 case UBS_CTXOP_RNGSHA1: 2759 break; 2760 case UBS_CTXOP_MODEXP: 2761 { 2762 struct ubsec_ctx_modexp *cx = (void *)c; 2763 int i, len; 2764 2765 printf(" Elen %u, Nlen %u\n", 2766 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2767 len = (cx->me_N_len + 7)/8; 2768 for (i = 0; i < len; i++) 2769 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2770 printf("\n"); 2771 break; 2772 } 2773 default: 2774 printf("unknown context: %x\n", c->ctx_op); 2775 } 2776 printf("END CTX\n"); 2777} 2778 2779static void 2780ubsec_dump_mcr(struct ubsec_mcr *mcr) 2781{ 2782 volatile struct ubsec_mcr_add *ma; 2783 int i; 2784 2785 printf("MCR:\n"); 2786 printf(" pkts: %u, flags 0x%x\n", 2787 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2788 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2789 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2790 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2791 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2792 letoh16(ma->mcr_reserved)); 2793 printf(" %d: ipkt ", i); 2794 ubsec_dump_pb(&ma->mcr_ipktbuf); 2795 printf(" %d: opkt ", i); 2796 ubsec_dump_pb(&ma->mcr_opktbuf); 2797 ma++; 2798 } 2799 printf("END MCR\n"); 2800} 2801#endif /* UBSEC_DEBUG */ 2802 2803/* 2804 * Return the number of significant bits of a big number. 2805 */ 2806static int 2807ubsec_ksigbits(struct crparam *cr) 2808{ 2809 u_int plen = (cr->crp_nbits + 7) / 8; 2810 int i, sig = plen * 8; 2811 u_int8_t c, *p = cr->crp_p; 2812 2813 for (i = plen - 1; i >= 0; i--) { 2814 c = p[i]; 2815 if (c != 0) { 2816 while ((c & 0x80) == 0) { 2817 sig--; 2818 c <<= 1; 2819 } 2820 break; 2821 } 2822 sig -= 8; 2823 } 2824 return (sig); 2825} 2826 2827static void 2828ubsec_kshift_r( 2829 u_int shiftbits, 2830 u_int8_t *src, u_int srcbits, 2831 u_int8_t *dst, u_int dstbits) 2832{ 2833 u_int slen, dlen; 2834 int i, si, di, n; 2835 2836 slen = (srcbits + 7) / 8; 2837 dlen = (dstbits + 7) / 8; 2838 2839 for (i = 0; i < slen; i++) 2840 dst[i] = src[i]; 2841 for (i = 0; i < dlen - slen; i++) 2842 dst[slen + i] = 0; 2843 2844 n = shiftbits / 8; 2845 if (n != 0) { 2846 si = dlen - n - 1; 2847 di = dlen - 1; 2848 while (si >= 0) 2849 dst[di--] = dst[si--]; 2850 while (di >= 0) 2851 dst[di--] = 0; 2852 } 2853 2854 n = shiftbits % 8; 2855 if (n != 0) { 2856 for (i = dlen - 1; i > 0; i--) 2857 dst[i] = (dst[i] << n) | 2858 (dst[i - 1] >> (8 - n)); 2859 dst[0] = dst[0] << n; 2860 } 2861} 2862 2863static void 2864ubsec_kshift_l( 2865 u_int shiftbits, 2866 u_int8_t *src, u_int srcbits, 2867 u_int8_t *dst, u_int dstbits) 2868{ 2869 int slen, dlen, i, n; 2870 2871 slen = (srcbits + 7) / 8; 2872 dlen = (dstbits + 7) / 8; 2873 2874 n = shiftbits / 8; 2875 for (i = 0; i < slen; i++) 2876 dst[i] = src[i + n]; 2877 for (i = 0; i < dlen - slen; i++) 2878 dst[slen + i] = 0; 2879 2880 n = shiftbits % 8; 2881 if (n != 0) { 2882 for (i = 0; i < (dlen - 1); i++) 2883 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2884 dst[dlen - 1] = dst[dlen - 1] >> n; 2885 } 2886} 2887