ubsec.c revision 119137
1/* $FreeBSD: head/sys/dev/ubsec/ubsec.c 119137 2003-08-19 17:51:11Z sam $ */ 2/* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */ 3 4/* 5 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 6 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 7 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 8 * 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Jason L. Wright 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 34 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Effort sponsored in part by the Defense Advanced Research Projects 38 * Agency (DARPA) and Air Force Research Laboratory, Air Force 39 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 40 * 41 */ 42 43/* 44 * uBsec 5[56]01, 58xx hardware crypto accelerator 45 */ 46 47#include "opt_ubsec.h" 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/proc.h> 52#include <sys/errno.h> 53#include <sys/malloc.h> 54#include <sys/kernel.h> 55#include <sys/mbuf.h> 56#include <sys/lock.h> 57#include <sys/mutex.h> 58#include <sys/sysctl.h> 59#include <sys/endian.h> 60 61#include <vm/vm.h> 62#include <vm/pmap.h> 63 64#include <machine/clock.h> 65#include <machine/bus.h> 66#include <machine/resource.h> 67#include <sys/bus.h> 68#include <sys/rman.h> 69 70#include <crypto/sha1.h> 71#include <opencrypto/cryptodev.h> 72#include <opencrypto/cryptosoft.h> 73#include <sys/md5.h> 74#include <sys/random.h> 75 76#include <pci/pcivar.h> 77#include <pci/pcireg.h> 78 79/* grr, #defines for gratuitous incompatibility in queue.h */ 80#define SIMPLEQ_HEAD STAILQ_HEAD 81#define SIMPLEQ_ENTRY STAILQ_ENTRY 82#define SIMPLEQ_INIT STAILQ_INIT 83#define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL 84#define SIMPLEQ_EMPTY STAILQ_EMPTY 85#define SIMPLEQ_FIRST STAILQ_FIRST 86#define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD_UNTIL 87#define SIMPLEQ_FOREACH STAILQ_FOREACH 88/* ditto for endian.h */ 89#define letoh16(x) le16toh(x) 90#define letoh32(x) le32toh(x) 91 92#ifdef UBSEC_RNDTEST 93#include <dev/rndtest/rndtest.h> 94#endif 95#include <dev/ubsec/ubsecreg.h> 96#include <dev/ubsec/ubsecvar.h> 97 98/* 99 * Prototypes and count for the pci_device structure 100 */ 101static int ubsec_probe(device_t); 102static int ubsec_attach(device_t); 103static int ubsec_detach(device_t); 104static int ubsec_suspend(device_t); 105static int ubsec_resume(device_t); 106static void ubsec_shutdown(device_t); 107 108static device_method_t ubsec_methods[] = { 109 /* Device interface */ 110 DEVMETHOD(device_probe, ubsec_probe), 111 DEVMETHOD(device_attach, ubsec_attach), 112 DEVMETHOD(device_detach, ubsec_detach), 113 DEVMETHOD(device_suspend, ubsec_suspend), 114 DEVMETHOD(device_resume, ubsec_resume), 115 DEVMETHOD(device_shutdown, ubsec_shutdown), 116 117 /* bus interface */ 118 DEVMETHOD(bus_print_child, bus_generic_print_child), 119 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 120 121 { 0, 0 } 122}; 123static driver_t ubsec_driver = { 124 "ubsec", 125 ubsec_methods, 126 sizeof (struct ubsec_softc) 127}; 128static devclass_t ubsec_devclass; 129 130DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0); 131MODULE_DEPEND(ubsec, crypto, 1, 1, 1); 132#ifdef UBSEC_RNDTEST 133MODULE_DEPEND(ubsec, rndtest, 1, 1, 1); 134#endif 135 136static void ubsec_intr(void *); 137static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *); 138static int ubsec_freesession(void *, u_int64_t); 139static int ubsec_process(void *, struct cryptop *, int); 140static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 141static void ubsec_feed(struct ubsec_softc *); 142static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 143static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 144static int ubsec_feed2(struct ubsec_softc *); 145static void ubsec_rng(void *); 146static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 147 struct ubsec_dma_alloc *, int); 148#define ubsec_dma_sync(_dma, _flags) \ 149 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 150static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 151static int ubsec_dmamap_aligned(struct ubsec_operand *op); 152 153static void ubsec_reset_board(struct ubsec_softc *sc); 154static void ubsec_init_board(struct ubsec_softc *sc); 155static void ubsec_init_pciregs(device_t dev); 156static void ubsec_totalreset(struct ubsec_softc *sc); 157 158static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q); 159 160static int ubsec_kprocess(void*, struct cryptkop *, int); 161static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int); 162static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int); 163static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int); 164static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 165static int ubsec_ksigbits(struct crparam *); 166static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 167static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 168 169SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters"); 170 171#ifdef UBSEC_DEBUG 172static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 173static void ubsec_dump_mcr(struct ubsec_mcr *); 174static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *); 175 176static int ubsec_debug = 0; 177SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug, 178 0, "control debugging msgs"); 179#endif 180 181#define READ_REG(sc,r) \ 182 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 183 184#define WRITE_REG(sc,reg,val) \ 185 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 186 187#define SWAP32(x) (x) = htole32(ntohl((x))) 188#define HTOLE32(x) (x) = htole32(x) 189 190struct ubsec_stats ubsecstats; 191SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats, 192 ubsec_stats, "driver statistics"); 193 194static int 195ubsec_probe(device_t dev) 196{ 197 if (pci_get_vendor(dev) == PCI_VENDOR_SUN && 198 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 || 199 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K)) 200 return (0); 201 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 202 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 || 203 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)) 204 return (0); 205 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 206 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 || 207 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 208 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 || 209 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 || 210 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 211 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 212 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 213 )) 214 return (0); 215 return (ENXIO); 216} 217 218static const char* 219ubsec_partname(struct ubsec_softc *sc) 220{ 221 /* XXX sprintf numbers when not decoded */ 222 switch (pci_get_vendor(sc->sc_dev)) { 223 case PCI_VENDOR_BROADCOM: 224 switch (pci_get_device(sc->sc_dev)) { 225 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801"; 226 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802"; 227 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805"; 228 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820"; 229 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821"; 230 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822"; 231 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823"; 232 } 233 return "Broadcom unknown-part"; 234 case PCI_VENDOR_BLUESTEEL: 235 switch (pci_get_device(sc->sc_dev)) { 236 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601"; 237 } 238 return "Bluesteel unknown-part"; 239 case PCI_VENDOR_SUN: 240 switch (pci_get_device(sc->sc_dev)) { 241 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821"; 242 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K"; 243 } 244 return "Sun unknown-part"; 245 } 246 return "Unknown-vendor unknown-part"; 247} 248 249static void 250default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 251{ 252 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 253} 254 255static int 256ubsec_attach(device_t dev) 257{ 258 struct ubsec_softc *sc = device_get_softc(dev); 259 struct ubsec_dma *dmap; 260 u_int32_t cmd, i; 261 int rid; 262 263 bzero(sc, sizeof (*sc)); 264 sc->sc_dev = dev; 265 266 SIMPLEQ_INIT(&sc->sc_queue); 267 SIMPLEQ_INIT(&sc->sc_qchip); 268 SIMPLEQ_INIT(&sc->sc_queue2); 269 SIMPLEQ_INIT(&sc->sc_qchip2); 270 SIMPLEQ_INIT(&sc->sc_q2free); 271 272 /* XXX handle power management */ 273 274 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; 275 276 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 277 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601) 278 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 279 280 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 281 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 282 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805)) 283 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 284 285 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 286 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820) 287 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 288 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 289 290 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 291 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 292 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 293 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) || 294 (pci_get_vendor(dev) == PCI_VENDOR_SUN && 295 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K || 296 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) { 297 /* NB: the 5821/5822 defines some additional status bits */ 298 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY | 299 BS_STAT_MCR2_ALLEMPTY; 300 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 301 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 302 } 303 304 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 305 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 306 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 307 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 308 309 if (!(cmd & PCIM_CMD_MEMEN)) { 310 device_printf(dev, "failed to enable memory mapping\n"); 311 goto bad; 312 } 313 314 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 315 device_printf(dev, "failed to enable bus mastering\n"); 316 goto bad; 317 } 318 319 /* 320 * Setup memory-mapping of PCI registers. 321 */ 322 rid = BS_BAR; 323 sc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 324 0, ~0, 1, RF_ACTIVE); 325 if (sc->sc_sr == NULL) { 326 device_printf(dev, "cannot map register space\n"); 327 goto bad; 328 } 329 sc->sc_st = rman_get_bustag(sc->sc_sr); 330 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 331 332 /* 333 * Arrange interrupt line. 334 */ 335 rid = 0; 336 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 337 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 338 if (sc->sc_irq == NULL) { 339 device_printf(dev, "could not map interrupt\n"); 340 goto bad1; 341 } 342 /* 343 * NB: Network code assumes we are blocked with splimp() 344 * so make sure the IRQ is mapped appropriately. 345 */ 346 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 347 ubsec_intr, sc, &sc->sc_ih)) { 348 device_printf(dev, "could not establish interrupt\n"); 349 goto bad2; 350 } 351 352 sc->sc_cid = crypto_get_driverid(0); 353 if (sc->sc_cid < 0) { 354 device_printf(dev, "could not get crypto driver id\n"); 355 goto bad3; 356 } 357 358 /* 359 * Setup DMA descriptor area. 360 */ 361 if (bus_dma_tag_create(NULL, /* parent */ 362 1, 0, /* alignment, bounds */ 363 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 364 BUS_SPACE_MAXADDR, /* highaddr */ 365 NULL, NULL, /* filter, filterarg */ 366 0x3ffff, /* maxsize */ 367 UBS_MAX_SCATTER, /* nsegments */ 368 0xffff, /* maxsegsize */ 369 BUS_DMA_ALLOCNOW, /* flags */ 370 NULL, NULL, /* lockfunc, lockarg */ 371 &sc->sc_dmat)) { 372 device_printf(dev, "cannot allocate DMA tag\n"); 373 goto bad4; 374 } 375 SIMPLEQ_INIT(&sc->sc_freequeue); 376 dmap = sc->sc_dmaa; 377 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 378 struct ubsec_q *q; 379 380 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 381 M_DEVBUF, M_NOWAIT); 382 if (q == NULL) { 383 device_printf(dev, "cannot allocate queue buffers\n"); 384 break; 385 } 386 387 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 388 &dmap->d_alloc, 0)) { 389 device_printf(dev, "cannot allocate dma buffers\n"); 390 free(q, M_DEVBUF); 391 break; 392 } 393 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 394 395 q->q_dma = dmap; 396 sc->sc_queuea[i] = q; 397 398 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 399 } 400 mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev), 401 "mcr1 operations", MTX_DEF); 402 mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev), 403 "mcr1 free q", MTX_DEF); 404 405 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc)); 406 407 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 408 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 409 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 410 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 411 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 412 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 413 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 414 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 415 416 /* 417 * Reset Broadcom chip 418 */ 419 ubsec_reset_board(sc); 420 421 /* 422 * Init Broadcom specific PCI settings 423 */ 424 ubsec_init_pciregs(dev); 425 426 /* 427 * Init Broadcom chip 428 */ 429 ubsec_init_board(sc); 430 431#ifndef UBSEC_NO_RNG 432 if (sc->sc_flags & UBS_FLAGS_RNG) { 433 sc->sc_statmask |= BS_STAT_MCR2_DONE; 434#ifdef UBSEC_RNDTEST 435 sc->sc_rndtest = rndtest_attach(dev); 436 if (sc->sc_rndtest) 437 sc->sc_harvest = rndtest_harvest; 438 else 439 sc->sc_harvest = default_harvest; 440#else 441 sc->sc_harvest = default_harvest; 442#endif 443 444 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 445 &sc->sc_rng.rng_q.q_mcr, 0)) 446 goto skip_rng; 447 448 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 449 &sc->sc_rng.rng_q.q_ctx, 0)) { 450 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 451 goto skip_rng; 452 } 453 454 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 455 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 456 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 457 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 458 goto skip_rng; 459 } 460 461 if (hz >= 100) 462 sc->sc_rnghz = hz / 100; 463 else 464 sc->sc_rnghz = 1; 465 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 466 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 467skip_rng: 468 ; 469 } 470#endif /* UBSEC_NO_RNG */ 471 mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev), 472 "mcr2 operations", MTX_DEF); 473 474 if (sc->sc_flags & UBS_FLAGS_KEY) { 475 sc->sc_statmask |= BS_STAT_MCR2_DONE; 476 477 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 478 ubsec_kprocess, sc); 479#if 0 480 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 481 ubsec_kprocess, sc); 482#endif 483 } 484 return (0); 485bad4: 486 crypto_unregister_all(sc->sc_cid); 487bad3: 488 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 489bad2: 490 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 491bad1: 492 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 493bad: 494 return (ENXIO); 495} 496 497/* 498 * Detach a device that successfully probed. 499 */ 500static int 501ubsec_detach(device_t dev) 502{ 503 struct ubsec_softc *sc = device_get_softc(dev); 504 505 /* XXX wait/abort active ops */ 506 507 /* disable interrupts */ 508 WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~ 509 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR)); 510 511 callout_stop(&sc->sc_rngto); 512 513 crypto_unregister_all(sc->sc_cid); 514 515#ifdef UBSEC_RNDTEST 516 if (sc->sc_rndtest) 517 rndtest_detach(sc->sc_rndtest); 518#endif 519 520 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 521 struct ubsec_q *q; 522 523 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 524 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 525 ubsec_dma_free(sc, &q->q_dma->d_alloc); 526 free(q, M_DEVBUF); 527 } 528 mtx_destroy(&sc->sc_mcr1lock); 529#ifndef UBSEC_NO_RNG 530 if (sc->sc_flags & UBS_FLAGS_RNG) { 531 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 532 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 533 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 534 } 535#endif /* UBSEC_NO_RNG */ 536 mtx_destroy(&sc->sc_mcr2lock); 537 538 bus_generic_detach(dev); 539 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 540 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 541 542 bus_dma_tag_destroy(sc->sc_dmat); 543 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 544 545 return (0); 546} 547 548/* 549 * Stop all chip i/o so that the kernel's probe routines don't 550 * get confused by errant DMAs when rebooting. 551 */ 552static void 553ubsec_shutdown(device_t dev) 554{ 555#ifdef notyet 556 ubsec_stop(device_get_softc(dev)); 557#endif 558} 559 560/* 561 * Device suspend routine. 562 */ 563static int 564ubsec_suspend(device_t dev) 565{ 566 struct ubsec_softc *sc = device_get_softc(dev); 567 568#ifdef notyet 569 /* XXX stop the device and save PCI settings */ 570#endif 571 sc->sc_suspended = 1; 572 573 return (0); 574} 575 576static int 577ubsec_resume(device_t dev) 578{ 579 struct ubsec_softc *sc = device_get_softc(dev); 580 581#ifdef notyet 582 /* XXX retore PCI settings and start the device */ 583#endif 584 sc->sc_suspended = 0; 585 return (0); 586} 587 588/* 589 * UBSEC Interrupt routine 590 */ 591static void 592ubsec_intr(void *arg) 593{ 594 struct ubsec_softc *sc = arg; 595 volatile u_int32_t stat; 596 struct ubsec_q *q; 597 struct ubsec_dma *dmap; 598 int npkts = 0, i; 599 600 stat = READ_REG(sc, BS_STAT); 601 stat &= sc->sc_statmask; 602 if (stat == 0) 603 return; 604 605 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 606 607 /* 608 * Check to see if we have any packets waiting for us 609 */ 610 if ((stat & BS_STAT_MCR1_DONE)) { 611 mtx_lock(&sc->sc_mcr1lock); 612 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 613 q = SIMPLEQ_FIRST(&sc->sc_qchip); 614 dmap = q->q_dma; 615 616 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 617 break; 618 619 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 620 621 npkts = q->q_nstacked_mcrs; 622 sc->sc_nqchip -= 1+npkts; 623 /* 624 * search for further sc_qchip ubsec_q's that share 625 * the same MCR, and complete them too, they must be 626 * at the top. 627 */ 628 for (i = 0; i < npkts; i++) { 629 if(q->q_stacked_mcr[i]) { 630 ubsec_callback(sc, q->q_stacked_mcr[i]); 631 } else { 632 break; 633 } 634 } 635 ubsec_callback(sc, q); 636 } 637 /* 638 * Don't send any more packet to chip if there has been 639 * a DMAERR. 640 */ 641 if (!(stat & BS_STAT_DMAERR)) 642 ubsec_feed(sc); 643 mtx_unlock(&sc->sc_mcr1lock); 644 } 645 646 /* 647 * Check to see if we have any key setups/rng's waiting for us 648 */ 649 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 650 (stat & BS_STAT_MCR2_DONE)) { 651 struct ubsec_q2 *q2; 652 struct ubsec_mcr *mcr; 653 654 mtx_lock(&sc->sc_mcr2lock); 655 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 656 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 657 658 ubsec_dma_sync(&q2->q_mcr, 659 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 660 661 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 662 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 663 ubsec_dma_sync(&q2->q_mcr, 664 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 665 break; 666 } 667 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next); 668 ubsec_callback2(sc, q2); 669 /* 670 * Don't send any more packet to chip if there has been 671 * a DMAERR. 672 */ 673 if (!(stat & BS_STAT_DMAERR)) 674 ubsec_feed2(sc); 675 } 676 mtx_unlock(&sc->sc_mcr2lock); 677 } 678 679 /* 680 * Check to see if we got any DMA Error 681 */ 682 if (stat & BS_STAT_DMAERR) { 683#ifdef UBSEC_DEBUG 684 if (ubsec_debug) { 685 volatile u_int32_t a = READ_REG(sc, BS_ERR); 686 687 printf("dmaerr %s@%08x\n", 688 (a & BS_ERR_READ) ? "read" : "write", 689 a & BS_ERR_ADDR); 690 } 691#endif /* UBSEC_DEBUG */ 692 ubsecstats.hst_dmaerr++; 693 mtx_lock(&sc->sc_mcr1lock); 694 ubsec_totalreset(sc); 695 ubsec_feed(sc); 696 mtx_unlock(&sc->sc_mcr1lock); 697 } 698 699 if (sc->sc_needwakeup) { /* XXX check high watermark */ 700 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 701#ifdef UBSEC_DEBUG 702 if (ubsec_debug) 703 device_printf(sc->sc_dev, "wakeup crypto (%x)\n", 704 sc->sc_needwakeup); 705#endif /* UBSEC_DEBUG */ 706 sc->sc_needwakeup &= ~wakeup; 707 crypto_unblock(sc->sc_cid, wakeup); 708 } 709} 710 711/* 712 * ubsec_feed() - aggregate and post requests to chip 713 */ 714static void 715ubsec_feed(struct ubsec_softc *sc) 716{ 717 struct ubsec_q *q, *q2; 718 int npkts, i; 719 void *v; 720 u_int32_t stat; 721 722 /* 723 * Decide how many ops to combine in a single MCR. We cannot 724 * aggregate more than UBS_MAX_AGGR because this is the number 725 * of slots defined in the data structure. Note that 726 * aggregation only happens if ops are marked batch'able. 727 * Aggregating ops reduces the number of interrupts to the host 728 * but also (potentially) increases the latency for processing 729 * completed ops as we only get an interrupt when all aggregated 730 * ops have completed. 731 */ 732 if (sc->sc_nqueue == 0) 733 return; 734 if (sc->sc_nqueue > 1) { 735 npkts = 0; 736 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) { 737 npkts++; 738 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0) 739 break; 740 } 741 } else 742 npkts = 1; 743 /* 744 * Check device status before going any further. 745 */ 746 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 747 if (stat & BS_STAT_DMAERR) { 748 ubsec_totalreset(sc); 749 ubsecstats.hst_dmaerr++; 750 } else 751 ubsecstats.hst_mcr1full++; 752 return; 753 } 754 if (sc->sc_nqueue > ubsecstats.hst_maxqueue) 755 ubsecstats.hst_maxqueue = sc->sc_nqueue; 756 if (npkts > UBS_MAX_AGGR) 757 npkts = UBS_MAX_AGGR; 758 if (npkts < 2) /* special case 1 op */ 759 goto feed1; 760 761 ubsecstats.hst_totbatch += npkts-1; 762#ifdef UBSEC_DEBUG 763 if (ubsec_debug) 764 printf("merging %d records\n", npkts); 765#endif /* UBSEC_DEBUG */ 766 767 q = SIMPLEQ_FIRST(&sc->sc_queue); 768 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 769 --sc->sc_nqueue; 770 771 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 772 if (q->q_dst_map != NULL) 773 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 774 775 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 776 777 for (i = 0; i < q->q_nstacked_mcrs; i++) { 778 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 779 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 780 BUS_DMASYNC_PREWRITE); 781 if (q2->q_dst_map != NULL) 782 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 783 BUS_DMASYNC_PREREAD); 784 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next); 785 --sc->sc_nqueue; 786 787 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - 788 sizeof(struct ubsec_mcr_add)); 789 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 790 q->q_stacked_mcr[i] = q2; 791 } 792 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 793 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 794 sc->sc_nqchip += npkts; 795 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 796 ubsecstats.hst_maxqchip = sc->sc_nqchip; 797 ubsec_dma_sync(&q->q_dma->d_alloc, 798 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 799 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 800 offsetof(struct ubsec_dmachunk, d_mcr)); 801 return; 802feed1: 803 q = SIMPLEQ_FIRST(&sc->sc_queue); 804 805 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 806 if (q->q_dst_map != NULL) 807 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 808 ubsec_dma_sync(&q->q_dma->d_alloc, 809 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 810 811 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 812 offsetof(struct ubsec_dmachunk, d_mcr)); 813#ifdef UBSEC_DEBUG 814 if (ubsec_debug) 815 printf("feed1: q->chip %p %08x stat %08x\n", 816 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr), 817 stat); 818#endif /* UBSEC_DEBUG */ 819 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 820 --sc->sc_nqueue; 821 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 822 sc->sc_nqchip++; 823 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 824 ubsecstats.hst_maxqchip = sc->sc_nqchip; 825 return; 826} 827 828/* 829 * Allocate a new 'session' and return an encoded session id. 'sidp' 830 * contains our registration id, and should contain an encoded session 831 * id on successful allocation. 832 */ 833static int 834ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 835{ 836 struct cryptoini *c, *encini = NULL, *macini = NULL; 837 struct ubsec_softc *sc = arg; 838 struct ubsec_session *ses = NULL; 839 MD5_CTX md5ctx; 840 SHA1_CTX sha1ctx; 841 int i, sesn; 842 843 if (sidp == NULL || cri == NULL || sc == NULL) 844 return (EINVAL); 845 846 for (c = cri; c != NULL; c = c->cri_next) { 847 if (c->cri_alg == CRYPTO_MD5_HMAC || 848 c->cri_alg == CRYPTO_SHA1_HMAC) { 849 if (macini) 850 return (EINVAL); 851 macini = c; 852 } else if (c->cri_alg == CRYPTO_DES_CBC || 853 c->cri_alg == CRYPTO_3DES_CBC) { 854 if (encini) 855 return (EINVAL); 856 encini = c; 857 } else 858 return (EINVAL); 859 } 860 if (encini == NULL && macini == NULL) 861 return (EINVAL); 862 863 if (sc->sc_sessions == NULL) { 864 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 865 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 866 if (ses == NULL) 867 return (ENOMEM); 868 sesn = 0; 869 sc->sc_nsessions = 1; 870 } else { 871 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 872 if (sc->sc_sessions[sesn].ses_used == 0) { 873 ses = &sc->sc_sessions[sesn]; 874 break; 875 } 876 } 877 878 if (ses == NULL) { 879 sesn = sc->sc_nsessions; 880 ses = (struct ubsec_session *)malloc((sesn + 1) * 881 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 882 if (ses == NULL) 883 return (ENOMEM); 884 bcopy(sc->sc_sessions, ses, sesn * 885 sizeof(struct ubsec_session)); 886 bzero(sc->sc_sessions, sesn * 887 sizeof(struct ubsec_session)); 888 free(sc->sc_sessions, M_DEVBUF); 889 sc->sc_sessions = ses; 890 ses = &sc->sc_sessions[sesn]; 891 sc->sc_nsessions++; 892 } 893 } 894 bzero(ses, sizeof(struct ubsec_session)); 895 ses->ses_used = 1; 896 897 if (encini) { 898 /* get an IV, network byte order */ 899 /* XXX may read fewer than requested */ 900 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 901 902 /* Go ahead and compute key in ubsec's byte order */ 903 if (encini->cri_alg == CRYPTO_DES_CBC) { 904 bcopy(encini->cri_key, &ses->ses_deskey[0], 8); 905 bcopy(encini->cri_key, &ses->ses_deskey[2], 8); 906 bcopy(encini->cri_key, &ses->ses_deskey[4], 8); 907 } else 908 bcopy(encini->cri_key, ses->ses_deskey, 24); 909 910 SWAP32(ses->ses_deskey[0]); 911 SWAP32(ses->ses_deskey[1]); 912 SWAP32(ses->ses_deskey[2]); 913 SWAP32(ses->ses_deskey[3]); 914 SWAP32(ses->ses_deskey[4]); 915 SWAP32(ses->ses_deskey[5]); 916 } 917 918 if (macini) { 919 for (i = 0; i < macini->cri_klen / 8; i++) 920 macini->cri_key[i] ^= HMAC_IPAD_VAL; 921 922 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 923 MD5Init(&md5ctx); 924 MD5Update(&md5ctx, macini->cri_key, 925 macini->cri_klen / 8); 926 MD5Update(&md5ctx, hmac_ipad_buffer, 927 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 928 bcopy(md5ctx.state, ses->ses_hminner, 929 sizeof(md5ctx.state)); 930 } else { 931 SHA1Init(&sha1ctx); 932 SHA1Update(&sha1ctx, macini->cri_key, 933 macini->cri_klen / 8); 934 SHA1Update(&sha1ctx, hmac_ipad_buffer, 935 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 936 bcopy(sha1ctx.h.b32, ses->ses_hminner, 937 sizeof(sha1ctx.h.b32)); 938 } 939 940 for (i = 0; i < macini->cri_klen / 8; i++) 941 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 942 943 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 944 MD5Init(&md5ctx); 945 MD5Update(&md5ctx, macini->cri_key, 946 macini->cri_klen / 8); 947 MD5Update(&md5ctx, hmac_opad_buffer, 948 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 949 bcopy(md5ctx.state, ses->ses_hmouter, 950 sizeof(md5ctx.state)); 951 } else { 952 SHA1Init(&sha1ctx); 953 SHA1Update(&sha1ctx, macini->cri_key, 954 macini->cri_klen / 8); 955 SHA1Update(&sha1ctx, hmac_opad_buffer, 956 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 957 bcopy(sha1ctx.h.b32, ses->ses_hmouter, 958 sizeof(sha1ctx.h.b32)); 959 } 960 961 for (i = 0; i < macini->cri_klen / 8; i++) 962 macini->cri_key[i] ^= HMAC_OPAD_VAL; 963 } 964 965 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); 966 return (0); 967} 968 969/* 970 * Deallocate a session. 971 */ 972static int 973ubsec_freesession(void *arg, u_int64_t tid) 974{ 975 struct ubsec_softc *sc = arg; 976 int session, ret; 977 u_int32_t sid = CRYPTO_SESID2LID(tid); 978 979 if (sc == NULL) 980 return (EINVAL); 981 982 session = UBSEC_SESSION(sid); 983 if (session < sc->sc_nsessions) { 984 bzero(&sc->sc_sessions[session], 985 sizeof(sc->sc_sessions[session])); 986 ret = 0; 987 } else 988 ret = EINVAL; 989 990 return (ret); 991} 992 993static void 994ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 995{ 996 struct ubsec_operand *op = arg; 997 998 KASSERT(nsegs <= UBS_MAX_SCATTER, 999 ("Too many DMA segments returned when mapping operand")); 1000#ifdef UBSEC_DEBUG 1001 if (ubsec_debug) 1002 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 1003 (u_int) mapsize, nsegs); 1004#endif 1005 op->mapsize = mapsize; 1006 op->nsegs = nsegs; 1007 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1008} 1009 1010static int 1011ubsec_process(void *arg, struct cryptop *crp, int hint) 1012{ 1013 struct ubsec_q *q = NULL; 1014 int err = 0, i, j, nicealign; 1015 struct ubsec_softc *sc = arg; 1016 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1017 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1018 int sskip, dskip, stheend, dtheend; 1019 int16_t coffset; 1020 struct ubsec_session *ses; 1021 struct ubsec_pktctx ctx; 1022 struct ubsec_dma *dmap = NULL; 1023 1024 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1025 ubsecstats.hst_invalid++; 1026 return (EINVAL); 1027 } 1028 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1029 ubsecstats.hst_badsession++; 1030 return (EINVAL); 1031 } 1032 1033 mtx_lock(&sc->sc_freeqlock); 1034 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1035 ubsecstats.hst_queuefull++; 1036 sc->sc_needwakeup |= CRYPTO_SYMQ; 1037 mtx_unlock(&sc->sc_freeqlock); 1038 return (ERESTART); 1039 } 1040 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1041 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 1042 mtx_unlock(&sc->sc_freeqlock); 1043 1044 dmap = q->q_dma; /* Save dma pointer */ 1045 bzero(q, sizeof(struct ubsec_q)); 1046 bzero(&ctx, sizeof(ctx)); 1047 1048 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1049 q->q_dma = dmap; 1050 ses = &sc->sc_sessions[q->q_sesn]; 1051 1052 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1053 q->q_src_m = (struct mbuf *)crp->crp_buf; 1054 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1055 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1056 q->q_src_io = (struct uio *)crp->crp_buf; 1057 q->q_dst_io = (struct uio *)crp->crp_buf; 1058 } else { 1059 ubsecstats.hst_badflags++; 1060 err = EINVAL; 1061 goto errout; /* XXX we don't handle contiguous blocks! */ 1062 } 1063 1064 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 1065 1066 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1067 dmap->d_dma->d_mcr.mcr_flags = 0; 1068 q->q_crp = crp; 1069 1070 crd1 = crp->crp_desc; 1071 if (crd1 == NULL) { 1072 ubsecstats.hst_nodesc++; 1073 err = EINVAL; 1074 goto errout; 1075 } 1076 crd2 = crd1->crd_next; 1077 1078 if (crd2 == NULL) { 1079 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 1080 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 1081 maccrd = crd1; 1082 enccrd = NULL; 1083 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1084 crd1->crd_alg == CRYPTO_3DES_CBC) { 1085 maccrd = NULL; 1086 enccrd = crd1; 1087 } else { 1088 ubsecstats.hst_badalg++; 1089 err = EINVAL; 1090 goto errout; 1091 } 1092 } else { 1093 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1094 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1095 (crd2->crd_alg == CRYPTO_DES_CBC || 1096 crd2->crd_alg == CRYPTO_3DES_CBC) && 1097 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1098 maccrd = crd1; 1099 enccrd = crd2; 1100 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1101 crd1->crd_alg == CRYPTO_3DES_CBC) && 1102 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1103 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1104 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1105 enccrd = crd1; 1106 maccrd = crd2; 1107 } else { 1108 /* 1109 * We cannot order the ubsec as requested 1110 */ 1111 ubsecstats.hst_badalg++; 1112 err = EINVAL; 1113 goto errout; 1114 } 1115 } 1116 1117 if (enccrd) { 1118 encoffset = enccrd->crd_skip; 1119 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1120 1121 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1122 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1123 1124 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1125 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1126 else { 1127 ctx.pc_iv[0] = ses->ses_iv[0]; 1128 ctx.pc_iv[1] = ses->ses_iv[1]; 1129 } 1130 1131 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1132 if (crp->crp_flags & CRYPTO_F_IMBUF) 1133 m_copyback(q->q_src_m, 1134 enccrd->crd_inject, 1135 8, (caddr_t)ctx.pc_iv); 1136 else if (crp->crp_flags & CRYPTO_F_IOV) 1137 cuio_copyback(q->q_src_io, 1138 enccrd->crd_inject, 1139 8, (caddr_t)ctx.pc_iv); 1140 } 1141 } else { 1142 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1143 1144 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1145 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1146 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1147 m_copydata(q->q_src_m, enccrd->crd_inject, 1148 8, (caddr_t)ctx.pc_iv); 1149 else if (crp->crp_flags & CRYPTO_F_IOV) 1150 cuio_copydata(q->q_src_io, 1151 enccrd->crd_inject, 8, 1152 (caddr_t)ctx.pc_iv); 1153 } 1154 1155 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1156 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1157 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1158 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1159 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1160 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1161 SWAP32(ctx.pc_iv[0]); 1162 SWAP32(ctx.pc_iv[1]); 1163 } 1164 1165 if (maccrd) { 1166 macoffset = maccrd->crd_skip; 1167 1168 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1169 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1170 else 1171 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1172 1173 for (i = 0; i < 5; i++) { 1174 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1175 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1176 1177 HTOLE32(ctx.pc_hminner[i]); 1178 HTOLE32(ctx.pc_hmouter[i]); 1179 } 1180 } 1181 1182 if (enccrd && maccrd) { 1183 /* 1184 * ubsec cannot handle packets where the end of encryption 1185 * and authentication are not the same, or where the 1186 * encrypted part begins before the authenticated part. 1187 */ 1188 if ((encoffset + enccrd->crd_len) != 1189 (macoffset + maccrd->crd_len)) { 1190 ubsecstats.hst_lenmismatch++; 1191 err = EINVAL; 1192 goto errout; 1193 } 1194 if (enccrd->crd_skip < maccrd->crd_skip) { 1195 ubsecstats.hst_skipmismatch++; 1196 err = EINVAL; 1197 goto errout; 1198 } 1199 sskip = maccrd->crd_skip; 1200 cpskip = dskip = enccrd->crd_skip; 1201 stheend = maccrd->crd_len; 1202 dtheend = enccrd->crd_len; 1203 coffset = enccrd->crd_skip - maccrd->crd_skip; 1204 cpoffset = cpskip + dtheend; 1205#ifdef UBSEC_DEBUG 1206 if (ubsec_debug) { 1207 printf("mac: skip %d, len %d, inject %d\n", 1208 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1209 printf("enc: skip %d, len %d, inject %d\n", 1210 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1211 printf("src: skip %d, len %d\n", sskip, stheend); 1212 printf("dst: skip %d, len %d\n", dskip, dtheend); 1213 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1214 coffset, stheend, cpskip, cpoffset); 1215 } 1216#endif 1217 } else { 1218 cpskip = dskip = sskip = macoffset + encoffset; 1219 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1220 cpoffset = cpskip + dtheend; 1221 coffset = 0; 1222 } 1223 ctx.pc_offset = htole16(coffset >> 2); 1224 1225 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) { 1226 ubsecstats.hst_nomap++; 1227 err = ENOMEM; 1228 goto errout; 1229 } 1230 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1231 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1232 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1233 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1234 q->q_src_map = NULL; 1235 ubsecstats.hst_noload++; 1236 err = ENOMEM; 1237 goto errout; 1238 } 1239 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1240 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1241 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1242 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1243 q->q_src_map = NULL; 1244 ubsecstats.hst_noload++; 1245 err = ENOMEM; 1246 goto errout; 1247 } 1248 } 1249 nicealign = ubsec_dmamap_aligned(&q->q_src); 1250 1251 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1252 1253#ifdef UBSEC_DEBUG 1254 if (ubsec_debug) 1255 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1256#endif 1257 for (i = j = 0; i < q->q_src_nsegs; i++) { 1258 struct ubsec_pktbuf *pb; 1259 bus_size_t packl = q->q_src_segs[i].ds_len; 1260 bus_addr_t packp = q->q_src_segs[i].ds_addr; 1261 1262 if (sskip >= packl) { 1263 sskip -= packl; 1264 continue; 1265 } 1266 1267 packl -= sskip; 1268 packp += sskip; 1269 sskip = 0; 1270 1271 if (packl > 0xfffc) { 1272 err = EIO; 1273 goto errout; 1274 } 1275 1276 if (j == 0) 1277 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1278 else 1279 pb = &dmap->d_dma->d_sbuf[j - 1]; 1280 1281 pb->pb_addr = htole32(packp); 1282 1283 if (stheend) { 1284 if (packl > stheend) { 1285 pb->pb_len = htole32(stheend); 1286 stheend = 0; 1287 } else { 1288 pb->pb_len = htole32(packl); 1289 stheend -= packl; 1290 } 1291 } else 1292 pb->pb_len = htole32(packl); 1293 1294 if ((i + 1) == q->q_src_nsegs) 1295 pb->pb_next = 0; 1296 else 1297 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1298 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1299 j++; 1300 } 1301 1302 if (enccrd == NULL && maccrd != NULL) { 1303 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1304 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1305 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1306 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1307#ifdef UBSEC_DEBUG 1308 if (ubsec_debug) 1309 printf("opkt: %x %x %x\n", 1310 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1311 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1312 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1313#endif 1314 } else { 1315 if (crp->crp_flags & CRYPTO_F_IOV) { 1316 if (!nicealign) { 1317 ubsecstats.hst_iovmisaligned++; 1318 err = EINVAL; 1319 goto errout; 1320 } 1321 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1322 &q->q_dst_map)) { 1323 ubsecstats.hst_nomap++; 1324 err = ENOMEM; 1325 goto errout; 1326 } 1327 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1328 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) { 1329 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1330 q->q_dst_map = NULL; 1331 ubsecstats.hst_noload++; 1332 err = ENOMEM; 1333 goto errout; 1334 } 1335 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1336 if (nicealign) { 1337 q->q_dst = q->q_src; 1338 } else { 1339 int totlen, len; 1340 struct mbuf *m, *top, **mp; 1341 1342 ubsecstats.hst_unaligned++; 1343 totlen = q->q_src_mapsize; 1344 if (q->q_src_m->m_flags & M_PKTHDR) { 1345 len = MHLEN; 1346 MGETHDR(m, M_DONTWAIT, MT_DATA); 1347 if (m && !m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)) { 1348 m_free(m); 1349 m = NULL; 1350 } 1351 } else { 1352 len = MLEN; 1353 MGET(m, M_DONTWAIT, MT_DATA); 1354 } 1355 if (m == NULL) { 1356 ubsecstats.hst_nombuf++; 1357 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1358 goto errout; 1359 } 1360 if (totlen >= MINCLSIZE) { 1361 MCLGET(m, M_DONTWAIT); 1362 if ((m->m_flags & M_EXT) == 0) { 1363 m_free(m); 1364 ubsecstats.hst_nomcl++; 1365 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1366 goto errout; 1367 } 1368 len = MCLBYTES; 1369 } 1370 m->m_len = len; 1371 top = NULL; 1372 mp = ⊤ 1373 1374 while (totlen > 0) { 1375 if (top) { 1376 MGET(m, M_DONTWAIT, MT_DATA); 1377 if (m == NULL) { 1378 m_freem(top); 1379 ubsecstats.hst_nombuf++; 1380 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1381 goto errout; 1382 } 1383 len = MLEN; 1384 } 1385 if (top && totlen >= MINCLSIZE) { 1386 MCLGET(m, M_DONTWAIT); 1387 if ((m->m_flags & M_EXT) == 0) { 1388 *mp = m; 1389 m_freem(top); 1390 ubsecstats.hst_nomcl++; 1391 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1392 goto errout; 1393 } 1394 len = MCLBYTES; 1395 } 1396 m->m_len = len = min(totlen, len); 1397 totlen -= len; 1398 *mp = m; 1399 mp = &m->m_next; 1400 } 1401 q->q_dst_m = top; 1402 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1403 cpskip, cpoffset); 1404 if (bus_dmamap_create(sc->sc_dmat, 1405 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) { 1406 ubsecstats.hst_nomap++; 1407 err = ENOMEM; 1408 goto errout; 1409 } 1410 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1411 q->q_dst_map, q->q_dst_m, 1412 ubsec_op_cb, &q->q_dst, 1413 BUS_DMA_NOWAIT) != 0) { 1414 bus_dmamap_destroy(sc->sc_dmat, 1415 q->q_dst_map); 1416 q->q_dst_map = NULL; 1417 ubsecstats.hst_noload++; 1418 err = ENOMEM; 1419 goto errout; 1420 } 1421 } 1422 } else { 1423 ubsecstats.hst_badflags++; 1424 err = EINVAL; 1425 goto errout; 1426 } 1427 1428#ifdef UBSEC_DEBUG 1429 if (ubsec_debug) 1430 printf("dst skip: %d\n", dskip); 1431#endif 1432 for (i = j = 0; i < q->q_dst_nsegs; i++) { 1433 struct ubsec_pktbuf *pb; 1434 bus_size_t packl = q->q_dst_segs[i].ds_len; 1435 bus_addr_t packp = q->q_dst_segs[i].ds_addr; 1436 1437 if (dskip >= packl) { 1438 dskip -= packl; 1439 continue; 1440 } 1441 1442 packl -= dskip; 1443 packp += dskip; 1444 dskip = 0; 1445 1446 if (packl > 0xfffc) { 1447 err = EIO; 1448 goto errout; 1449 } 1450 1451 if (j == 0) 1452 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1453 else 1454 pb = &dmap->d_dma->d_dbuf[j - 1]; 1455 1456 pb->pb_addr = htole32(packp); 1457 1458 if (dtheend) { 1459 if (packl > dtheend) { 1460 pb->pb_len = htole32(dtheend); 1461 dtheend = 0; 1462 } else { 1463 pb->pb_len = htole32(packl); 1464 dtheend -= packl; 1465 } 1466 } else 1467 pb->pb_len = htole32(packl); 1468 1469 if ((i + 1) == q->q_dst_nsegs) { 1470 if (maccrd) 1471 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1472 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1473 else 1474 pb->pb_next = 0; 1475 } else 1476 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1477 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1478 j++; 1479 } 1480 } 1481 1482 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1483 offsetof(struct ubsec_dmachunk, d_ctx)); 1484 1485 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1486 struct ubsec_pktctx_long *ctxl; 1487 1488 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr + 1489 offsetof(struct ubsec_dmachunk, d_ctx)); 1490 1491 /* transform small context into long context */ 1492 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1493 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1494 ctxl->pc_flags = ctx.pc_flags; 1495 ctxl->pc_offset = ctx.pc_offset; 1496 for (i = 0; i < 6; i++) 1497 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1498 for (i = 0; i < 5; i++) 1499 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1500 for (i = 0; i < 5; i++) 1501 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1502 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1503 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1504 } else 1505 bcopy(&ctx, dmap->d_alloc.dma_vaddr + 1506 offsetof(struct ubsec_dmachunk, d_ctx), 1507 sizeof(struct ubsec_pktctx)); 1508 1509 mtx_lock(&sc->sc_mcr1lock); 1510 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1511 sc->sc_nqueue++; 1512 ubsecstats.hst_ipackets++; 1513 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size; 1514 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR) 1515 ubsec_feed(sc); 1516 mtx_unlock(&sc->sc_mcr1lock); 1517 return (0); 1518 1519errout: 1520 if (q != NULL) { 1521 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1522 m_freem(q->q_dst_m); 1523 1524 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1525 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1526 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1527 } 1528 if (q->q_src_map != NULL) { 1529 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1530 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1531 } 1532 1533 mtx_lock(&sc->sc_freeqlock); 1534 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1535 mtx_unlock(&sc->sc_freeqlock); 1536 } 1537 if (err != ERESTART) { 1538 crp->crp_etype = err; 1539 crypto_done(crp); 1540 } else { 1541 sc->sc_needwakeup |= CRYPTO_SYMQ; 1542 } 1543 return (err); 1544} 1545 1546static void 1547ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1548{ 1549 struct cryptop *crp = (struct cryptop *)q->q_crp; 1550 struct cryptodesc *crd; 1551 struct ubsec_dma *dmap = q->q_dma; 1552 1553 ubsecstats.hst_opackets++; 1554 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1555 1556 ubsec_dma_sync(&dmap->d_alloc, 1557 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1558 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1559 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1560 BUS_DMASYNC_POSTREAD); 1561 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1562 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1563 } 1564 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE); 1565 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1566 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1567 1568 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1569 m_freem(q->q_src_m); 1570 crp->crp_buf = (caddr_t)q->q_dst_m; 1571 } 1572 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len; 1573 1574 /* copy out IV for future use */ 1575 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1576 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1577 if (crd->crd_alg != CRYPTO_DES_CBC && 1578 crd->crd_alg != CRYPTO_3DES_CBC) 1579 continue; 1580 if (crp->crp_flags & CRYPTO_F_IMBUF) 1581 m_copydata((struct mbuf *)crp->crp_buf, 1582 crd->crd_skip + crd->crd_len - 8, 8, 1583 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1584 else if (crp->crp_flags & CRYPTO_F_IOV) { 1585 cuio_copydata((struct uio *)crp->crp_buf, 1586 crd->crd_skip + crd->crd_len - 8, 8, 1587 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1588 } 1589 break; 1590 } 1591 } 1592 1593 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1594 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1595 crd->crd_alg != CRYPTO_SHA1_HMAC) 1596 continue; 1597 if (crp->crp_flags & CRYPTO_F_IMBUF) 1598 m_copyback((struct mbuf *)crp->crp_buf, 1599 crd->crd_inject, 12, 1600 (caddr_t)dmap->d_dma->d_macbuf); 1601 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1602 bcopy((caddr_t)dmap->d_dma->d_macbuf, 1603 crp->crp_mac, 12); 1604 break; 1605 } 1606 mtx_lock(&sc->sc_freeqlock); 1607 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1608 mtx_unlock(&sc->sc_freeqlock); 1609 crypto_done(crp); 1610} 1611 1612static void 1613ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1614{ 1615 int i, j, dlen, slen; 1616 caddr_t dptr, sptr; 1617 1618 j = 0; 1619 sptr = srcm->m_data; 1620 slen = srcm->m_len; 1621 dptr = dstm->m_data; 1622 dlen = dstm->m_len; 1623 1624 while (1) { 1625 for (i = 0; i < min(slen, dlen); i++) { 1626 if (j < hoffset || j >= toffset) 1627 *dptr++ = *sptr++; 1628 slen--; 1629 dlen--; 1630 j++; 1631 } 1632 if (slen == 0) { 1633 srcm = srcm->m_next; 1634 if (srcm == NULL) 1635 return; 1636 sptr = srcm->m_data; 1637 slen = srcm->m_len; 1638 } 1639 if (dlen == 0) { 1640 dstm = dstm->m_next; 1641 if (dstm == NULL) 1642 return; 1643 dptr = dstm->m_data; 1644 dlen = dstm->m_len; 1645 } 1646 } 1647} 1648 1649/* 1650 * feed the key generator, must be called at splimp() or higher. 1651 */ 1652static int 1653ubsec_feed2(struct ubsec_softc *sc) 1654{ 1655 struct ubsec_q2 *q; 1656 1657 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1658 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1659 break; 1660 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1661 1662 ubsec_dma_sync(&q->q_mcr, 1663 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1664 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE); 1665 1666 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1667 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next); 1668 --sc->sc_nqueue2; 1669 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1670 } 1671 return (0); 1672} 1673 1674/* 1675 * Callback for handling random numbers 1676 */ 1677static void 1678ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1679{ 1680 struct cryptkop *krp; 1681 struct ubsec_ctx_keyop *ctx; 1682 1683 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1684 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE); 1685 1686 switch (q->q_type) { 1687#ifndef UBSEC_NO_RNG 1688 case UBS_CTXOP_RNGBYPASS: { 1689 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1690 1691 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD); 1692 (*sc->sc_harvest)(sc->sc_rndtest, 1693 rng->rng_buf.dma_vaddr, 1694 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t)); 1695 rng->rng_used = 0; 1696 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1697 break; 1698 } 1699#endif 1700 case UBS_CTXOP_MODEXP: { 1701 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1702 u_int rlen, clen; 1703 1704 krp = me->me_krp; 1705 rlen = (me->me_modbits + 7) / 8; 1706 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1707 1708 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE); 1709 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE); 1710 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD); 1711 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE); 1712 1713 if (clen < rlen) 1714 krp->krp_status = E2BIG; 1715 else { 1716 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1717 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1718 (krp->krp_param[krp->krp_iparams].crp_nbits 1719 + 7) / 8); 1720 bcopy(me->me_C.dma_vaddr, 1721 krp->krp_param[krp->krp_iparams].crp_p, 1722 (me->me_modbits + 7) / 8); 1723 } else 1724 ubsec_kshift_l(me->me_shiftbits, 1725 me->me_C.dma_vaddr, me->me_normbits, 1726 krp->krp_param[krp->krp_iparams].crp_p, 1727 krp->krp_param[krp->krp_iparams].crp_nbits); 1728 } 1729 1730 crypto_kdone(krp); 1731 1732 /* bzero all potentially sensitive data */ 1733 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1734 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1735 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1736 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1737 1738 /* Can't free here, so put us on the free list. */ 1739 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1740 break; 1741 } 1742 case UBS_CTXOP_RSAPRIV: { 1743 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1744 u_int len; 1745 1746 krp = rp->rpr_krp; 1747 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE); 1748 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD); 1749 1750 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1751 bcopy(rp->rpr_msgout.dma_vaddr, 1752 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1753 1754 crypto_kdone(krp); 1755 1756 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1757 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1758 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1759 1760 /* Can't free here, so put us on the free list. */ 1761 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1762 break; 1763 } 1764 default: 1765 device_printf(sc->sc_dev, "unknown ctx op: %x\n", 1766 letoh16(ctx->ctx_op)); 1767 break; 1768 } 1769} 1770 1771#ifndef UBSEC_NO_RNG 1772static void 1773ubsec_rng(void *vsc) 1774{ 1775 struct ubsec_softc *sc = vsc; 1776 struct ubsec_q2_rng *rng = &sc->sc_rng; 1777 struct ubsec_mcr *mcr; 1778 struct ubsec_ctx_rngbypass *ctx; 1779 1780 mtx_lock(&sc->sc_mcr2lock); 1781 if (rng->rng_used) { 1782 mtx_unlock(&sc->sc_mcr2lock); 1783 return; 1784 } 1785 sc->sc_nqueue2++; 1786 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1787 goto out; 1788 1789 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1790 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1791 1792 mcr->mcr_pkts = htole16(1); 1793 mcr->mcr_flags = 0; 1794 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1795 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1796 mcr->mcr_ipktbuf.pb_len = 0; 1797 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1798 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1799 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1800 UBS_PKTBUF_LEN); 1801 mcr->mcr_opktbuf.pb_next = 0; 1802 1803 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1804 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS); 1805 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS; 1806 1807 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD); 1808 1809 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1810 rng->rng_used = 1; 1811 ubsec_feed2(sc); 1812 ubsecstats.hst_rng++; 1813 mtx_unlock(&sc->sc_mcr2lock); 1814 1815 return; 1816 1817out: 1818 /* 1819 * Something weird happened, generate our own call back. 1820 */ 1821 sc->sc_nqueue2--; 1822 mtx_unlock(&sc->sc_mcr2lock); 1823 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1824} 1825#endif /* UBSEC_NO_RNG */ 1826 1827static void 1828ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1829{ 1830 bus_addr_t *paddr = (bus_addr_t*) arg; 1831 *paddr = segs->ds_addr; 1832} 1833 1834static int 1835ubsec_dma_malloc( 1836 struct ubsec_softc *sc, 1837 bus_size_t size, 1838 struct ubsec_dma_alloc *dma, 1839 int mapflags 1840) 1841{ 1842 int r; 1843 1844 /* XXX could specify sc_dmat as parent but that just adds overhead */ 1845 r = bus_dma_tag_create(NULL, /* parent */ 1846 1, 0, /* alignment, bounds */ 1847 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1848 BUS_SPACE_MAXADDR, /* highaddr */ 1849 NULL, NULL, /* filter, filterarg */ 1850 size, /* maxsize */ 1851 1, /* nsegments */ 1852 size, /* maxsegsize */ 1853 BUS_DMA_ALLOCNOW, /* flags */ 1854 NULL, NULL, /* lockfunc, lockarg */ 1855 &dma->dma_tag); 1856 if (r != 0) { 1857 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1858 "bus_dma_tag_create failed; error %u\n", r); 1859 goto fail_0; 1860 } 1861 1862 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1863 if (r != 0) { 1864 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1865 "bus_dmamap_create failed; error %u\n", r); 1866 goto fail_1; 1867 } 1868 1869 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1870 BUS_DMA_NOWAIT, &dma->dma_map); 1871 if (r != 0) { 1872 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1873 "bus_dmammem_alloc failed; size %zu, error %u\n", 1874 size, r); 1875 goto fail_2; 1876 } 1877 1878 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1879 size, 1880 ubsec_dmamap_cb, 1881 &dma->dma_paddr, 1882 mapflags | BUS_DMA_NOWAIT); 1883 if (r != 0) { 1884 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1885 "bus_dmamap_load failed; error %u\n", r); 1886 goto fail_3; 1887 } 1888 1889 dma->dma_size = size; 1890 return (0); 1891 1892fail_3: 1893 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1894fail_2: 1895 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1896fail_1: 1897 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1898 bus_dma_tag_destroy(dma->dma_tag); 1899fail_0: 1900 dma->dma_map = NULL; 1901 dma->dma_tag = NULL; 1902 return (r); 1903} 1904 1905static void 1906ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1907{ 1908 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1909 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1910 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1911 bus_dma_tag_destroy(dma->dma_tag); 1912} 1913 1914/* 1915 * Resets the board. Values in the regesters are left as is 1916 * from the reset (i.e. initial values are assigned elsewhere). 1917 */ 1918static void 1919ubsec_reset_board(struct ubsec_softc *sc) 1920{ 1921 volatile u_int32_t ctrl; 1922 1923 ctrl = READ_REG(sc, BS_CTRL); 1924 ctrl |= BS_CTRL_RESET; 1925 WRITE_REG(sc, BS_CTRL, ctrl); 1926 1927 /* 1928 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1929 */ 1930 DELAY(10); 1931} 1932 1933/* 1934 * Init Broadcom registers 1935 */ 1936static void 1937ubsec_init_board(struct ubsec_softc *sc) 1938{ 1939 u_int32_t ctrl; 1940 1941 ctrl = READ_REG(sc, BS_CTRL); 1942 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1943 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1944 1945 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) 1946 ctrl |= BS_CTRL_MCR2INT; 1947 else 1948 ctrl &= ~BS_CTRL_MCR2INT; 1949 1950 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1951 ctrl &= ~BS_CTRL_SWNORM; 1952 1953 WRITE_REG(sc, BS_CTRL, ctrl); 1954} 1955 1956/* 1957 * Init Broadcom PCI registers 1958 */ 1959static void 1960ubsec_init_pciregs(device_t dev) 1961{ 1962#if 0 1963 u_int32_t misc; 1964 1965 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT); 1966 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT)) 1967 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT); 1968 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT)) 1969 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT); 1970 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc); 1971#endif 1972 1973 /* 1974 * This will set the cache line size to 1, this will 1975 * force the BCM58xx chip just to do burst read/writes. 1976 * Cache line read/writes are to slow 1977 */ 1978 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1); 1979} 1980 1981/* 1982 * Clean up after a chip crash. 1983 * It is assumed that the caller in splimp() 1984 */ 1985static void 1986ubsec_cleanchip(struct ubsec_softc *sc) 1987{ 1988 struct ubsec_q *q; 1989 1990 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 1991 q = SIMPLEQ_FIRST(&sc->sc_qchip); 1992 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 1993 ubsec_free_q(sc, q); 1994 } 1995 sc->sc_nqchip = 0; 1996} 1997 1998/* 1999 * free a ubsec_q 2000 * It is assumed that the caller is within splimp(). 2001 */ 2002static int 2003ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2004{ 2005 struct ubsec_q *q2; 2006 struct cryptop *crp; 2007 int npkts; 2008 int i; 2009 2010 npkts = q->q_nstacked_mcrs; 2011 2012 for (i = 0; i < npkts; i++) { 2013 if(q->q_stacked_mcr[i]) { 2014 q2 = q->q_stacked_mcr[i]; 2015 2016 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 2017 m_freem(q2->q_dst_m); 2018 2019 crp = (struct cryptop *)q2->q_crp; 2020 2021 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2022 2023 crp->crp_etype = EFAULT; 2024 crypto_done(crp); 2025 } else { 2026 break; 2027 } 2028 } 2029 2030 /* 2031 * Free header MCR 2032 */ 2033 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2034 m_freem(q->q_dst_m); 2035 2036 crp = (struct cryptop *)q->q_crp; 2037 2038 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2039 2040 crp->crp_etype = EFAULT; 2041 crypto_done(crp); 2042 return(0); 2043} 2044 2045/* 2046 * Routine to reset the chip and clean up. 2047 * It is assumed that the caller is in splimp() 2048 */ 2049static void 2050ubsec_totalreset(struct ubsec_softc *sc) 2051{ 2052 ubsec_reset_board(sc); 2053 ubsec_init_board(sc); 2054 ubsec_cleanchip(sc); 2055} 2056 2057static int 2058ubsec_dmamap_aligned(struct ubsec_operand *op) 2059{ 2060 int i; 2061 2062 for (i = 0; i < op->nsegs; i++) { 2063 if (op->segs[i].ds_addr & 3) 2064 return (0); 2065 if ((i != (op->nsegs - 1)) && 2066 (op->segs[i].ds_len & 3)) 2067 return (0); 2068 } 2069 return (1); 2070} 2071 2072static void 2073ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2074{ 2075 switch (q->q_type) { 2076 case UBS_CTXOP_MODEXP: { 2077 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2078 2079 ubsec_dma_free(sc, &me->me_q.q_mcr); 2080 ubsec_dma_free(sc, &me->me_q.q_ctx); 2081 ubsec_dma_free(sc, &me->me_M); 2082 ubsec_dma_free(sc, &me->me_E); 2083 ubsec_dma_free(sc, &me->me_C); 2084 ubsec_dma_free(sc, &me->me_epb); 2085 free(me, M_DEVBUF); 2086 break; 2087 } 2088 case UBS_CTXOP_RSAPRIV: { 2089 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2090 2091 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2092 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2093 ubsec_dma_free(sc, &rp->rpr_msgin); 2094 ubsec_dma_free(sc, &rp->rpr_msgout); 2095 free(rp, M_DEVBUF); 2096 break; 2097 } 2098 default: 2099 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type); 2100 break; 2101 } 2102} 2103 2104static int 2105ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2106{ 2107 struct ubsec_softc *sc = arg; 2108 int r; 2109 2110 if (krp == NULL || krp->krp_callback == NULL) 2111 return (EINVAL); 2112 2113 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2114 struct ubsec_q2 *q; 2115 2116 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2117 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next); 2118 ubsec_kfree(sc, q); 2119 } 2120 2121 switch (krp->krp_op) { 2122 case CRK_MOD_EXP: 2123 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2124 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2125 else 2126 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2127 break; 2128 case CRK_MOD_EXP_CRT: 2129 return (ubsec_kprocess_rsapriv(sc, krp, hint)); 2130 default: 2131 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n", 2132 krp->krp_op); 2133 krp->krp_status = EOPNOTSUPP; 2134 crypto_kdone(krp); 2135 return (0); 2136 } 2137 return (0); /* silence compiler */ 2138} 2139 2140/* 2141 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2142 */ 2143static int 2144ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2145{ 2146 struct ubsec_q2_modexp *me; 2147 struct ubsec_mcr *mcr; 2148 struct ubsec_ctx_modexp *ctx; 2149 struct ubsec_pktbuf *epb; 2150 int err = 0; 2151 u_int nbits, normbits, mbits, shiftbits, ebits; 2152 2153 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2154 if (me == NULL) { 2155 err = ENOMEM; 2156 goto errout; 2157 } 2158 bzero(me, sizeof *me); 2159 me->me_krp = krp; 2160 me->me_q.q_type = UBS_CTXOP_MODEXP; 2161 2162 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2163 if (nbits <= 512) 2164 normbits = 512; 2165 else if (nbits <= 768) 2166 normbits = 768; 2167 else if (nbits <= 1024) 2168 normbits = 1024; 2169 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2170 normbits = 1536; 2171 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2172 normbits = 2048; 2173 else { 2174 err = E2BIG; 2175 goto errout; 2176 } 2177 2178 shiftbits = normbits - nbits; 2179 2180 me->me_modbits = nbits; 2181 me->me_shiftbits = shiftbits; 2182 me->me_normbits = normbits; 2183 2184 /* Sanity check: result bits must be >= true modulus bits. */ 2185 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2186 err = ERANGE; 2187 goto errout; 2188 } 2189 2190 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2191 &me->me_q.q_mcr, 0)) { 2192 err = ENOMEM; 2193 goto errout; 2194 } 2195 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2196 2197 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2198 &me->me_q.q_ctx, 0)) { 2199 err = ENOMEM; 2200 goto errout; 2201 } 2202 2203 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2204 if (mbits > nbits) { 2205 err = E2BIG; 2206 goto errout; 2207 } 2208 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2209 err = ENOMEM; 2210 goto errout; 2211 } 2212 ubsec_kshift_r(shiftbits, 2213 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2214 me->me_M.dma_vaddr, normbits); 2215 2216 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2217 err = ENOMEM; 2218 goto errout; 2219 } 2220 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2221 2222 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2223 if (ebits > nbits) { 2224 err = E2BIG; 2225 goto errout; 2226 } 2227 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2228 err = ENOMEM; 2229 goto errout; 2230 } 2231 ubsec_kshift_r(shiftbits, 2232 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2233 me->me_E.dma_vaddr, normbits); 2234 2235 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2236 &me->me_epb, 0)) { 2237 err = ENOMEM; 2238 goto errout; 2239 } 2240 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2241 epb->pb_addr = htole32(me->me_E.dma_paddr); 2242 epb->pb_next = 0; 2243 epb->pb_len = htole32(normbits / 8); 2244 2245#ifdef UBSEC_DEBUG 2246 if (ubsec_debug) { 2247 printf("Epb "); 2248 ubsec_dump_pb(epb); 2249 } 2250#endif 2251 2252 mcr->mcr_pkts = htole16(1); 2253 mcr->mcr_flags = 0; 2254 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2255 mcr->mcr_reserved = 0; 2256 mcr->mcr_pktlen = 0; 2257 2258 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2259 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2260 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2261 2262 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2263 mcr->mcr_opktbuf.pb_next = 0; 2264 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2265 2266#ifdef DIAGNOSTIC 2267 /* Misaligned output buffer will hang the chip. */ 2268 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2269 panic("%s: modexp invalid addr 0x%x\n", 2270 device_get_nameunit(sc->sc_dev), 2271 letoh32(mcr->mcr_opktbuf.pb_addr)); 2272 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2273 panic("%s: modexp invalid len 0x%x\n", 2274 device_get_nameunit(sc->sc_dev), 2275 letoh32(mcr->mcr_opktbuf.pb_len)); 2276#endif 2277 2278 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2279 bzero(ctx, sizeof(*ctx)); 2280 ubsec_kshift_r(shiftbits, 2281 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2282 ctx->me_N, normbits); 2283 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2284 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2285 ctx->me_E_len = htole16(nbits); 2286 ctx->me_N_len = htole16(nbits); 2287 2288#ifdef UBSEC_DEBUG 2289 if (ubsec_debug) { 2290 ubsec_dump_mcr(mcr); 2291 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2292 } 2293#endif 2294 2295 /* 2296 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2297 * everything else. 2298 */ 2299 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2300 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2301 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2302 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2303 2304 /* Enqueue and we're done... */ 2305 mtx_lock(&sc->sc_mcr2lock); 2306 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2307 ubsec_feed2(sc); 2308 ubsecstats.hst_modexp++; 2309 mtx_unlock(&sc->sc_mcr2lock); 2310 2311 return (0); 2312 2313errout: 2314 if (me != NULL) { 2315 if (me->me_q.q_mcr.dma_map != NULL) 2316 ubsec_dma_free(sc, &me->me_q.q_mcr); 2317 if (me->me_q.q_ctx.dma_map != NULL) { 2318 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2319 ubsec_dma_free(sc, &me->me_q.q_ctx); 2320 } 2321 if (me->me_M.dma_map != NULL) { 2322 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2323 ubsec_dma_free(sc, &me->me_M); 2324 } 2325 if (me->me_E.dma_map != NULL) { 2326 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2327 ubsec_dma_free(sc, &me->me_E); 2328 } 2329 if (me->me_C.dma_map != NULL) { 2330 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2331 ubsec_dma_free(sc, &me->me_C); 2332 } 2333 if (me->me_epb.dma_map != NULL) 2334 ubsec_dma_free(sc, &me->me_epb); 2335 free(me, M_DEVBUF); 2336 } 2337 krp->krp_status = err; 2338 crypto_kdone(krp); 2339 return (0); 2340} 2341 2342/* 2343 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2344 */ 2345static int 2346ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2347{ 2348 struct ubsec_q2_modexp *me; 2349 struct ubsec_mcr *mcr; 2350 struct ubsec_ctx_modexp *ctx; 2351 struct ubsec_pktbuf *epb; 2352 int err = 0; 2353 u_int nbits, normbits, mbits, shiftbits, ebits; 2354 2355 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2356 if (me == NULL) { 2357 err = ENOMEM; 2358 goto errout; 2359 } 2360 bzero(me, sizeof *me); 2361 me->me_krp = krp; 2362 me->me_q.q_type = UBS_CTXOP_MODEXP; 2363 2364 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2365 if (nbits <= 512) 2366 normbits = 512; 2367 else if (nbits <= 768) 2368 normbits = 768; 2369 else if (nbits <= 1024) 2370 normbits = 1024; 2371 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2372 normbits = 1536; 2373 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2374 normbits = 2048; 2375 else { 2376 err = E2BIG; 2377 goto errout; 2378 } 2379 2380 shiftbits = normbits - nbits; 2381 2382 /* XXX ??? */ 2383 me->me_modbits = nbits; 2384 me->me_shiftbits = shiftbits; 2385 me->me_normbits = normbits; 2386 2387 /* Sanity check: result bits must be >= true modulus bits. */ 2388 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2389 err = ERANGE; 2390 goto errout; 2391 } 2392 2393 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2394 &me->me_q.q_mcr, 0)) { 2395 err = ENOMEM; 2396 goto errout; 2397 } 2398 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2399 2400 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2401 &me->me_q.q_ctx, 0)) { 2402 err = ENOMEM; 2403 goto errout; 2404 } 2405 2406 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2407 if (mbits > nbits) { 2408 err = E2BIG; 2409 goto errout; 2410 } 2411 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2412 err = ENOMEM; 2413 goto errout; 2414 } 2415 bzero(me->me_M.dma_vaddr, normbits / 8); 2416 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2417 me->me_M.dma_vaddr, (mbits + 7) / 8); 2418 2419 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2420 err = ENOMEM; 2421 goto errout; 2422 } 2423 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2424 2425 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2426 if (ebits > nbits) { 2427 err = E2BIG; 2428 goto errout; 2429 } 2430 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2431 err = ENOMEM; 2432 goto errout; 2433 } 2434 bzero(me->me_E.dma_vaddr, normbits / 8); 2435 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2436 me->me_E.dma_vaddr, (ebits + 7) / 8); 2437 2438 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2439 &me->me_epb, 0)) { 2440 err = ENOMEM; 2441 goto errout; 2442 } 2443 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2444 epb->pb_addr = htole32(me->me_E.dma_paddr); 2445 epb->pb_next = 0; 2446 epb->pb_len = htole32((ebits + 7) / 8); 2447 2448#ifdef UBSEC_DEBUG 2449 if (ubsec_debug) { 2450 printf("Epb "); 2451 ubsec_dump_pb(epb); 2452 } 2453#endif 2454 2455 mcr->mcr_pkts = htole16(1); 2456 mcr->mcr_flags = 0; 2457 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2458 mcr->mcr_reserved = 0; 2459 mcr->mcr_pktlen = 0; 2460 2461 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2462 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2463 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2464 2465 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2466 mcr->mcr_opktbuf.pb_next = 0; 2467 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2468 2469#ifdef DIAGNOSTIC 2470 /* Misaligned output buffer will hang the chip. */ 2471 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2472 panic("%s: modexp invalid addr 0x%x\n", 2473 device_get_nameunit(sc->sc_dev), 2474 letoh32(mcr->mcr_opktbuf.pb_addr)); 2475 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2476 panic("%s: modexp invalid len 0x%x\n", 2477 device_get_nameunit(sc->sc_dev), 2478 letoh32(mcr->mcr_opktbuf.pb_len)); 2479#endif 2480 2481 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2482 bzero(ctx, sizeof(*ctx)); 2483 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2484 (nbits + 7) / 8); 2485 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2486 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2487 ctx->me_E_len = htole16(ebits); 2488 ctx->me_N_len = htole16(nbits); 2489 2490#ifdef UBSEC_DEBUG 2491 if (ubsec_debug) { 2492 ubsec_dump_mcr(mcr); 2493 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2494 } 2495#endif 2496 2497 /* 2498 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2499 * everything else. 2500 */ 2501 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2502 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2503 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2504 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2505 2506 /* Enqueue and we're done... */ 2507 mtx_lock(&sc->sc_mcr2lock); 2508 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2509 ubsec_feed2(sc); 2510 mtx_unlock(&sc->sc_mcr2lock); 2511 2512 return (0); 2513 2514errout: 2515 if (me != NULL) { 2516 if (me->me_q.q_mcr.dma_map != NULL) 2517 ubsec_dma_free(sc, &me->me_q.q_mcr); 2518 if (me->me_q.q_ctx.dma_map != NULL) { 2519 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2520 ubsec_dma_free(sc, &me->me_q.q_ctx); 2521 } 2522 if (me->me_M.dma_map != NULL) { 2523 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2524 ubsec_dma_free(sc, &me->me_M); 2525 } 2526 if (me->me_E.dma_map != NULL) { 2527 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2528 ubsec_dma_free(sc, &me->me_E); 2529 } 2530 if (me->me_C.dma_map != NULL) { 2531 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2532 ubsec_dma_free(sc, &me->me_C); 2533 } 2534 if (me->me_epb.dma_map != NULL) 2535 ubsec_dma_free(sc, &me->me_epb); 2536 free(me, M_DEVBUF); 2537 } 2538 krp->krp_status = err; 2539 crypto_kdone(krp); 2540 return (0); 2541} 2542 2543static int 2544ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2545{ 2546 struct ubsec_q2_rsapriv *rp = NULL; 2547 struct ubsec_mcr *mcr; 2548 struct ubsec_ctx_rsapriv *ctx; 2549 int err = 0; 2550 u_int padlen, msglen; 2551 2552 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2553 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2554 if (msglen > padlen) 2555 padlen = msglen; 2556 2557 if (padlen <= 256) 2558 padlen = 256; 2559 else if (padlen <= 384) 2560 padlen = 384; 2561 else if (padlen <= 512) 2562 padlen = 512; 2563 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2564 padlen = 768; 2565 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2566 padlen = 1024; 2567 else { 2568 err = E2BIG; 2569 goto errout; 2570 } 2571 2572 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2573 err = E2BIG; 2574 goto errout; 2575 } 2576 2577 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2578 err = E2BIG; 2579 goto errout; 2580 } 2581 2582 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2583 err = E2BIG; 2584 goto errout; 2585 } 2586 2587 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT); 2588 if (rp == NULL) 2589 return (ENOMEM); 2590 bzero(rp, sizeof *rp); 2591 rp->rpr_krp = krp; 2592 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2593 2594 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2595 &rp->rpr_q.q_mcr, 0)) { 2596 err = ENOMEM; 2597 goto errout; 2598 } 2599 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2600 2601 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2602 &rp->rpr_q.q_ctx, 0)) { 2603 err = ENOMEM; 2604 goto errout; 2605 } 2606 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2607 bzero(ctx, sizeof *ctx); 2608 2609 /* Copy in p */ 2610 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2611 &ctx->rpr_buf[0 * (padlen / 8)], 2612 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2613 2614 /* Copy in q */ 2615 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2616 &ctx->rpr_buf[1 * (padlen / 8)], 2617 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2618 2619 /* Copy in dp */ 2620 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2621 &ctx->rpr_buf[2 * (padlen / 8)], 2622 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2623 2624 /* Copy in dq */ 2625 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2626 &ctx->rpr_buf[3 * (padlen / 8)], 2627 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2628 2629 /* Copy in pinv */ 2630 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2631 &ctx->rpr_buf[4 * (padlen / 8)], 2632 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2633 2634 msglen = padlen * 2; 2635 2636 /* Copy in input message (aligned buffer/length). */ 2637 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2638 /* Is this likely? */ 2639 err = E2BIG; 2640 goto errout; 2641 } 2642 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2643 err = ENOMEM; 2644 goto errout; 2645 } 2646 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2647 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2648 rp->rpr_msgin.dma_vaddr, 2649 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2650 2651 /* Prepare space for output message (aligned buffer/length). */ 2652 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2653 /* Is this likely? */ 2654 err = E2BIG; 2655 goto errout; 2656 } 2657 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2658 err = ENOMEM; 2659 goto errout; 2660 } 2661 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2662 2663 mcr->mcr_pkts = htole16(1); 2664 mcr->mcr_flags = 0; 2665 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2666 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2667 mcr->mcr_ipktbuf.pb_next = 0; 2668 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2669 mcr->mcr_reserved = 0; 2670 mcr->mcr_pktlen = htole16(msglen); 2671 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2672 mcr->mcr_opktbuf.pb_next = 0; 2673 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2674 2675#ifdef DIAGNOSTIC 2676 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2677 panic("%s: rsapriv: invalid msgin %x(0x%jx)", 2678 device_get_nameunit(sc->sc_dev), 2679 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size); 2680 } 2681 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2682 panic("%s: rsapriv: invalid msgout %x(0x%jx)", 2683 device_get_nameunit(sc->sc_dev), 2684 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size); 2685 } 2686#endif 2687 2688 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2689 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2690 ctx->rpr_q_len = htole16(padlen); 2691 ctx->rpr_p_len = htole16(padlen); 2692 2693 /* 2694 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2695 * everything else. 2696 */ 2697 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE); 2698 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD); 2699 2700 /* Enqueue and we're done... */ 2701 mtx_lock(&sc->sc_mcr2lock); 2702 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2703 ubsec_feed2(sc); 2704 ubsecstats.hst_modexpcrt++; 2705 mtx_unlock(&sc->sc_mcr2lock); 2706 return (0); 2707 2708errout: 2709 if (rp != NULL) { 2710 if (rp->rpr_q.q_mcr.dma_map != NULL) 2711 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2712 if (rp->rpr_msgin.dma_map != NULL) { 2713 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2714 ubsec_dma_free(sc, &rp->rpr_msgin); 2715 } 2716 if (rp->rpr_msgout.dma_map != NULL) { 2717 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2718 ubsec_dma_free(sc, &rp->rpr_msgout); 2719 } 2720 free(rp, M_DEVBUF); 2721 } 2722 krp->krp_status = err; 2723 crypto_kdone(krp); 2724 return (0); 2725} 2726 2727#ifdef UBSEC_DEBUG 2728static void 2729ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2730{ 2731 printf("addr 0x%x (0x%x) next 0x%x\n", 2732 pb->pb_addr, pb->pb_len, pb->pb_next); 2733} 2734 2735static void 2736ubsec_dump_ctx2(struct ubsec_ctx_keyop *c) 2737{ 2738 printf("CTX (0x%x):\n", c->ctx_len); 2739 switch (letoh16(c->ctx_op)) { 2740 case UBS_CTXOP_RNGBYPASS: 2741 case UBS_CTXOP_RNGSHA1: 2742 break; 2743 case UBS_CTXOP_MODEXP: 2744 { 2745 struct ubsec_ctx_modexp *cx = (void *)c; 2746 int i, len; 2747 2748 printf(" Elen %u, Nlen %u\n", 2749 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2750 len = (cx->me_N_len + 7)/8; 2751 for (i = 0; i < len; i++) 2752 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2753 printf("\n"); 2754 break; 2755 } 2756 default: 2757 printf("unknown context: %x\n", c->ctx_op); 2758 } 2759 printf("END CTX\n"); 2760} 2761 2762static void 2763ubsec_dump_mcr(struct ubsec_mcr *mcr) 2764{ 2765 volatile struct ubsec_mcr_add *ma; 2766 int i; 2767 2768 printf("MCR:\n"); 2769 printf(" pkts: %u, flags 0x%x\n", 2770 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2771 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2772 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2773 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2774 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2775 letoh16(ma->mcr_reserved)); 2776 printf(" %d: ipkt ", i); 2777 ubsec_dump_pb(&ma->mcr_ipktbuf); 2778 printf(" %d: opkt ", i); 2779 ubsec_dump_pb(&ma->mcr_opktbuf); 2780 ma++; 2781 } 2782 printf("END MCR\n"); 2783} 2784#endif /* UBSEC_DEBUG */ 2785 2786/* 2787 * Return the number of significant bits of a big number. 2788 */ 2789static int 2790ubsec_ksigbits(struct crparam *cr) 2791{ 2792 u_int plen = (cr->crp_nbits + 7) / 8; 2793 int i, sig = plen * 8; 2794 u_int8_t c, *p = cr->crp_p; 2795 2796 for (i = plen - 1; i >= 0; i--) { 2797 c = p[i]; 2798 if (c != 0) { 2799 while ((c & 0x80) == 0) { 2800 sig--; 2801 c <<= 1; 2802 } 2803 break; 2804 } 2805 sig -= 8; 2806 } 2807 return (sig); 2808} 2809 2810static void 2811ubsec_kshift_r( 2812 u_int shiftbits, 2813 u_int8_t *src, u_int srcbits, 2814 u_int8_t *dst, u_int dstbits) 2815{ 2816 u_int slen, dlen; 2817 int i, si, di, n; 2818 2819 slen = (srcbits + 7) / 8; 2820 dlen = (dstbits + 7) / 8; 2821 2822 for (i = 0; i < slen; i++) 2823 dst[i] = src[i]; 2824 for (i = 0; i < dlen - slen; i++) 2825 dst[slen + i] = 0; 2826 2827 n = shiftbits / 8; 2828 if (n != 0) { 2829 si = dlen - n - 1; 2830 di = dlen - 1; 2831 while (si >= 0) 2832 dst[di--] = dst[si--]; 2833 while (di >= 0) 2834 dst[di--] = 0; 2835 } 2836 2837 n = shiftbits % 8; 2838 if (n != 0) { 2839 for (i = dlen - 1; i > 0; i--) 2840 dst[i] = (dst[i] << n) | 2841 (dst[i - 1] >> (8 - n)); 2842 dst[0] = dst[0] << n; 2843 } 2844} 2845 2846static void 2847ubsec_kshift_l( 2848 u_int shiftbits, 2849 u_int8_t *src, u_int srcbits, 2850 u_int8_t *dst, u_int dstbits) 2851{ 2852 int slen, dlen, i, n; 2853 2854 slen = (srcbits + 7) / 8; 2855 dlen = (dstbits + 7) / 8; 2856 2857 n = shiftbits / 8; 2858 for (i = 0; i < slen; i++) 2859 dst[i] = src[i + n]; 2860 for (i = 0; i < dlen - slen; i++) 2861 dst[slen + i] = 0; 2862 2863 n = shiftbits % 8; 2864 if (n != 0) { 2865 for (i = 0; i < (dlen - 1); i++) 2866 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2867 dst[dlen - 1] = dst[dlen - 1] >> n; 2868 } 2869} 2870