ubsec.c revision 115747
1/* $FreeBSD: head/sys/dev/ubsec/ubsec.c 115747 2003-06-02 23:32:03Z sam $ */ 2/* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */ 3 4/* 5 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 6 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 7 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 8 * 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Jason L. Wright 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 34 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Effort sponsored in part by the Defense Advanced Research Projects 38 * Agency (DARPA) and Air Force Research Laboratory, Air Force 39 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 40 * 41 */ 42 43/* 44 * uBsec 5[56]01, 58xx hardware crypto accelerator 45 */ 46 47#include "opt_ubsec.h" 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/proc.h> 52#include <sys/errno.h> 53#include <sys/malloc.h> 54#include <sys/kernel.h> 55#include <sys/mbuf.h> 56#include <sys/lock.h> 57#include <sys/mutex.h> 58#include <sys/sysctl.h> 59#include <sys/endian.h> 60 61#include <vm/vm.h> 62#include <vm/pmap.h> 63 64#include <machine/clock.h> 65#include <machine/bus.h> 66#include <machine/resource.h> 67#include <sys/bus.h> 68#include <sys/rman.h> 69 70#include <crypto/sha1.h> 71#include <opencrypto/cryptodev.h> 72#include <opencrypto/cryptosoft.h> 73#include <sys/md5.h> 74#include <sys/random.h> 75 76#include <pci/pcivar.h> 77#include <pci/pcireg.h> 78 79/* grr, #defines for gratuitous incompatibility in queue.h */ 80#define SIMPLEQ_HEAD STAILQ_HEAD 81#define SIMPLEQ_ENTRY STAILQ_ENTRY 82#define SIMPLEQ_INIT STAILQ_INIT 83#define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL 84#define SIMPLEQ_EMPTY STAILQ_EMPTY 85#define SIMPLEQ_FIRST STAILQ_FIRST 86#define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD_UNTIL 87#define SIMPLEQ_FOREACH STAILQ_FOREACH 88/* ditto for endian.h */ 89#define letoh16(x) le16toh(x) 90#define letoh32(x) le32toh(x) 91 92#ifdef UBSEC_RNDTEST 93#include <dev/rndtest/rndtest.h> 94#endif 95#include <dev/ubsec/ubsecreg.h> 96#include <dev/ubsec/ubsecvar.h> 97 98/* 99 * Prototypes and count for the pci_device structure 100 */ 101static int ubsec_probe(device_t); 102static int ubsec_attach(device_t); 103static int ubsec_detach(device_t); 104static int ubsec_suspend(device_t); 105static int ubsec_resume(device_t); 106static void ubsec_shutdown(device_t); 107 108static device_method_t ubsec_methods[] = { 109 /* Device interface */ 110 DEVMETHOD(device_probe, ubsec_probe), 111 DEVMETHOD(device_attach, ubsec_attach), 112 DEVMETHOD(device_detach, ubsec_detach), 113 DEVMETHOD(device_suspend, ubsec_suspend), 114 DEVMETHOD(device_resume, ubsec_resume), 115 DEVMETHOD(device_shutdown, ubsec_shutdown), 116 117 /* bus interface */ 118 DEVMETHOD(bus_print_child, bus_generic_print_child), 119 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 120 121 { 0, 0 } 122}; 123static driver_t ubsec_driver = { 124 "ubsec", 125 ubsec_methods, 126 sizeof (struct ubsec_softc) 127}; 128static devclass_t ubsec_devclass; 129 130DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0); 131MODULE_DEPEND(ubsec, crypto, 1, 1, 1); 132#ifdef UBSEC_RNDTEST 133MODULE_DEPEND(ubsec, rndtest, 1, 1, 1); 134#endif 135 136static void ubsec_intr(void *); 137static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *); 138static int ubsec_freesession(void *, u_int64_t); 139static int ubsec_process(void *, struct cryptop *, int); 140static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 141static void ubsec_feed(struct ubsec_softc *); 142static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 143static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 144static int ubsec_feed2(struct ubsec_softc *); 145static void ubsec_rng(void *); 146static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 147 struct ubsec_dma_alloc *, int); 148#define ubsec_dma_sync(_dma, _flags) \ 149 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 150static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 151static int ubsec_dmamap_aligned(struct ubsec_operand *op); 152 153static void ubsec_reset_board(struct ubsec_softc *sc); 154static void ubsec_init_board(struct ubsec_softc *sc); 155static void ubsec_init_pciregs(device_t dev); 156static void ubsec_totalreset(struct ubsec_softc *sc); 157 158static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q); 159 160static int ubsec_kprocess(void*, struct cryptkop *, int); 161static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int); 162static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int); 163static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int); 164static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 165static int ubsec_ksigbits(struct crparam *); 166static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 167static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 168 169SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters"); 170 171#ifdef UBSEC_DEBUG 172static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 173static void ubsec_dump_mcr(struct ubsec_mcr *); 174static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *); 175 176static int ubsec_debug = 0; 177SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug, 178 0, "control debugging msgs"); 179#endif 180 181#define READ_REG(sc,r) \ 182 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 183 184#define WRITE_REG(sc,reg,val) \ 185 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 186 187#define SWAP32(x) (x) = htole32(ntohl((x))) 188#define HTOLE32(x) (x) = htole32(x) 189 190struct ubsec_stats ubsecstats; 191SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats, 192 ubsec_stats, "driver statistics"); 193 194static int 195ubsec_probe(device_t dev) 196{ 197 if (pci_get_vendor(dev) == PCI_VENDOR_SUN && 198 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 || 199 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K)) 200 return (0); 201 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 202 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 || 203 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)) 204 return (0); 205 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 206 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 || 207 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 208 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 || 209 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 || 210 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 211 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 212 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 213 )) 214 return (0); 215 return (ENXIO); 216} 217 218static const char* 219ubsec_partname(struct ubsec_softc *sc) 220{ 221 /* XXX sprintf numbers when not decoded */ 222 switch (pci_get_vendor(sc->sc_dev)) { 223 case PCI_VENDOR_BROADCOM: 224 switch (pci_get_device(sc->sc_dev)) { 225 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801"; 226 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802"; 227 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805"; 228 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820"; 229 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821"; 230 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822"; 231 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823"; 232 } 233 return "Broadcom unknown-part"; 234 case PCI_VENDOR_BLUESTEEL: 235 switch (pci_get_device(sc->sc_dev)) { 236 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601"; 237 } 238 return "Bluesteel unknown-part"; 239 case PCI_VENDOR_SUN: 240 switch (pci_get_device(sc->sc_dev)) { 241 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821"; 242 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K"; 243 } 244 return "Sun unknown-part"; 245 } 246 return "Unknown-vendor unknown-part"; 247} 248 249static void 250default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 251{ 252 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 253} 254 255static int 256ubsec_attach(device_t dev) 257{ 258 struct ubsec_softc *sc = device_get_softc(dev); 259 struct ubsec_dma *dmap; 260 u_int32_t cmd, i; 261 int rid; 262 263 bzero(sc, sizeof (*sc)); 264 sc->sc_dev = dev; 265 266 SIMPLEQ_INIT(&sc->sc_queue); 267 SIMPLEQ_INIT(&sc->sc_qchip); 268 SIMPLEQ_INIT(&sc->sc_queue2); 269 SIMPLEQ_INIT(&sc->sc_qchip2); 270 SIMPLEQ_INIT(&sc->sc_q2free); 271 272 /* XXX handle power management */ 273 274 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; 275 276 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 277 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601) 278 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 279 280 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 281 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 282 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805)) 283 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 284 285 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 286 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820) 287 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 288 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 289 290 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 291 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 292 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 293 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) || 294 (pci_get_vendor(dev) == PCI_VENDOR_SUN && 295 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K || 296 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) { 297 /* NB: the 5821/5822 defines some additional status bits */ 298 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY | 299 BS_STAT_MCR2_ALLEMPTY; 300 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 301 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 302 } 303 304 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 305 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 306 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 307 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 308 309 if (!(cmd & PCIM_CMD_MEMEN)) { 310 device_printf(dev, "failed to enable memory mapping\n"); 311 goto bad; 312 } 313 314 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 315 device_printf(dev, "failed to enable bus mastering\n"); 316 goto bad; 317 } 318 319 /* 320 * Setup memory-mapping of PCI registers. 321 */ 322 rid = BS_BAR; 323 sc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 324 0, ~0, 1, RF_ACTIVE); 325 if (sc->sc_sr == NULL) { 326 device_printf(dev, "cannot map register space\n"); 327 goto bad; 328 } 329 sc->sc_st = rman_get_bustag(sc->sc_sr); 330 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 331 332 /* 333 * Arrange interrupt line. 334 */ 335 rid = 0; 336 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 337 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 338 if (sc->sc_irq == NULL) { 339 device_printf(dev, "could not map interrupt\n"); 340 goto bad1; 341 } 342 /* 343 * NB: Network code assumes we are blocked with splimp() 344 * so make sure the IRQ is mapped appropriately. 345 */ 346 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 347 ubsec_intr, sc, &sc->sc_ih)) { 348 device_printf(dev, "could not establish interrupt\n"); 349 goto bad2; 350 } 351 352 sc->sc_cid = crypto_get_driverid(0); 353 if (sc->sc_cid < 0) { 354 device_printf(dev, "could not get crypto driver id\n"); 355 goto bad3; 356 } 357 358 /* 359 * Setup DMA descriptor area. 360 */ 361 if (bus_dma_tag_create(NULL, /* parent */ 362 1, 0, /* alignment, bounds */ 363 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 364 BUS_SPACE_MAXADDR, /* highaddr */ 365 NULL, NULL, /* filter, filterarg */ 366 0x3ffff, /* maxsize */ 367 UBS_MAX_SCATTER, /* nsegments */ 368 0xffff, /* maxsegsize */ 369 BUS_DMA_ALLOCNOW, /* flags */ 370 &sc->sc_dmat)) { 371 device_printf(dev, "cannot allocate DMA tag\n"); 372 goto bad4; 373 } 374 SIMPLEQ_INIT(&sc->sc_freequeue); 375 dmap = sc->sc_dmaa; 376 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 377 struct ubsec_q *q; 378 379 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 380 M_DEVBUF, M_NOWAIT); 381 if (q == NULL) { 382 device_printf(dev, "cannot allocate queue buffers\n"); 383 break; 384 } 385 386 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 387 &dmap->d_alloc, 0)) { 388 device_printf(dev, "cannot allocate dma buffers\n"); 389 free(q, M_DEVBUF); 390 break; 391 } 392 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 393 394 q->q_dma = dmap; 395 sc->sc_queuea[i] = q; 396 397 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 398 } 399 mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev), 400 "mcr1 operations", MTX_DEF); 401 mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev), 402 "mcr1 free q", MTX_DEF); 403 404 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc)); 405 406 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 407 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 408 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 409 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 410 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 411 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 412 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 413 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 414 415 /* 416 * Reset Broadcom chip 417 */ 418 ubsec_reset_board(sc); 419 420 /* 421 * Init Broadcom specific PCI settings 422 */ 423 ubsec_init_pciregs(dev); 424 425 /* 426 * Init Broadcom chip 427 */ 428 ubsec_init_board(sc); 429 430#ifndef UBSEC_NO_RNG 431 if (sc->sc_flags & UBS_FLAGS_RNG) { 432 sc->sc_statmask |= BS_STAT_MCR2_DONE; 433#ifdef UBSEC_RNDTEST 434 sc->sc_rndtest = rndtest_attach(dev); 435 if (sc->sc_rndtest) 436 sc->sc_harvest = rndtest_harvest; 437 else 438 sc->sc_harvest = default_harvest; 439#else 440 sc->sc_harvest = default_harvest; 441#endif 442 443 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 444 &sc->sc_rng.rng_q.q_mcr, 0)) 445 goto skip_rng; 446 447 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 448 &sc->sc_rng.rng_q.q_ctx, 0)) { 449 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 450 goto skip_rng; 451 } 452 453 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 454 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 455 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 456 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 457 goto skip_rng; 458 } 459 460 if (hz >= 100) 461 sc->sc_rnghz = hz / 100; 462 else 463 sc->sc_rnghz = 1; 464 /* NB: 1 means the callout runs w/o Giant locked */ 465 callout_init(&sc->sc_rngto, 1); 466 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 467skip_rng: 468 ; 469 } 470#endif /* UBSEC_NO_RNG */ 471 mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev), 472 "mcr2 operations", MTX_DEF); 473 474 if (sc->sc_flags & UBS_FLAGS_KEY) { 475 sc->sc_statmask |= BS_STAT_MCR2_DONE; 476 477 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 478 ubsec_kprocess, sc); 479#if 0 480 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 481 ubsec_kprocess, sc); 482#endif 483 } 484 return (0); 485bad4: 486 crypto_unregister_all(sc->sc_cid); 487bad3: 488 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 489bad2: 490 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 491bad1: 492 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 493bad: 494 return (ENXIO); 495} 496 497/* 498 * Detach a device that successfully probed. 499 */ 500static int 501ubsec_detach(device_t dev) 502{ 503 struct ubsec_softc *sc = device_get_softc(dev); 504 505 /* XXX wait/abort active ops */ 506 507 /* disable interrupts */ 508 WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~ 509 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR)); 510 511 callout_stop(&sc->sc_rngto); 512 513 crypto_unregister_all(sc->sc_cid); 514 515#ifdef UBSEC_RNDTEST 516 if (sc->sc_rndtest) 517 rndtest_detach(sc->sc_rndtest); 518#endif 519 520 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 521 struct ubsec_q *q; 522 523 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 524 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 525 ubsec_dma_free(sc, &q->q_dma->d_alloc); 526 free(q, M_DEVBUF); 527 } 528 mtx_destroy(&sc->sc_mcr1lock); 529#ifndef UBSEC_NO_RNG 530 if (sc->sc_flags & UBS_FLAGS_RNG) { 531 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 532 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 533 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 534 } 535#endif /* UBSEC_NO_RNG */ 536 mtx_destroy(&sc->sc_mcr2lock); 537 538 bus_generic_detach(dev); 539 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 540 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 541 542 bus_dma_tag_destroy(sc->sc_dmat); 543 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 544 545 return (0); 546} 547 548/* 549 * Stop all chip i/o so that the kernel's probe routines don't 550 * get confused by errant DMAs when rebooting. 551 */ 552static void 553ubsec_shutdown(device_t dev) 554{ 555#ifdef notyet 556 ubsec_stop(device_get_softc(dev)); 557#endif 558} 559 560/* 561 * Device suspend routine. 562 */ 563static int 564ubsec_suspend(device_t dev) 565{ 566 struct ubsec_softc *sc = device_get_softc(dev); 567 568#ifdef notyet 569 /* XXX stop the device and save PCI settings */ 570#endif 571 sc->sc_suspended = 1; 572 573 return (0); 574} 575 576static int 577ubsec_resume(device_t dev) 578{ 579 struct ubsec_softc *sc = device_get_softc(dev); 580 581#ifdef notyet 582 /* XXX retore PCI settings and start the device */ 583#endif 584 sc->sc_suspended = 0; 585 return (0); 586} 587 588/* 589 * UBSEC Interrupt routine 590 */ 591static void 592ubsec_intr(void *arg) 593{ 594 struct ubsec_softc *sc = arg; 595 volatile u_int32_t stat; 596 struct ubsec_q *q; 597 struct ubsec_dma *dmap; 598 int npkts = 0, i; 599 600 stat = READ_REG(sc, BS_STAT); 601 stat &= sc->sc_statmask; 602 if (stat == 0) 603 return; 604 605 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 606 607 /* 608 * Check to see if we have any packets waiting for us 609 */ 610 if ((stat & BS_STAT_MCR1_DONE)) { 611 mtx_lock(&sc->sc_mcr1lock); 612 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 613 q = SIMPLEQ_FIRST(&sc->sc_qchip); 614 dmap = q->q_dma; 615 616 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 617 break; 618 619 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 620 621 npkts = q->q_nstacked_mcrs; 622 sc->sc_nqchip -= 1+npkts; 623 /* 624 * search for further sc_qchip ubsec_q's that share 625 * the same MCR, and complete them too, they must be 626 * at the top. 627 */ 628 for (i = 0; i < npkts; i++) { 629 if(q->q_stacked_mcr[i]) { 630 ubsec_callback(sc, q->q_stacked_mcr[i]); 631 } else { 632 break; 633 } 634 } 635 ubsec_callback(sc, q); 636 } 637 /* 638 * Don't send any more packet to chip if there has been 639 * a DMAERR. 640 */ 641 if (!(stat & BS_STAT_DMAERR)) 642 ubsec_feed(sc); 643 mtx_unlock(&sc->sc_mcr1lock); 644 } 645 646 /* 647 * Check to see if we have any key setups/rng's waiting for us 648 */ 649 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 650 (stat & BS_STAT_MCR2_DONE)) { 651 struct ubsec_q2 *q2; 652 struct ubsec_mcr *mcr; 653 654 mtx_lock(&sc->sc_mcr2lock); 655 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 656 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 657 658 ubsec_dma_sync(&q2->q_mcr, 659 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 660 661 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 662 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 663 ubsec_dma_sync(&q2->q_mcr, 664 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 665 break; 666 } 667 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next); 668 ubsec_callback2(sc, q2); 669 /* 670 * Don't send any more packet to chip if there has been 671 * a DMAERR. 672 */ 673 if (!(stat & BS_STAT_DMAERR)) 674 ubsec_feed2(sc); 675 } 676 mtx_unlock(&sc->sc_mcr2lock); 677 } 678 679 /* 680 * Check to see if we got any DMA Error 681 */ 682 if (stat & BS_STAT_DMAERR) { 683#ifdef UBSEC_DEBUG 684 if (ubsec_debug) { 685 volatile u_int32_t a = READ_REG(sc, BS_ERR); 686 687 printf("dmaerr %s@%08x\n", 688 (a & BS_ERR_READ) ? "read" : "write", 689 a & BS_ERR_ADDR); 690 } 691#endif /* UBSEC_DEBUG */ 692 ubsecstats.hst_dmaerr++; 693 mtx_lock(&sc->sc_mcr1lock); 694 ubsec_totalreset(sc); 695 ubsec_feed(sc); 696 mtx_unlock(&sc->sc_mcr1lock); 697 } 698 699 if (sc->sc_needwakeup) { /* XXX check high watermark */ 700 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 701#ifdef UBSEC_DEBUG 702 if (ubsec_debug) 703 device_printf(sc->sc_dev, "wakeup crypto (%x)\n", 704 sc->sc_needwakeup); 705#endif /* UBSEC_DEBUG */ 706 sc->sc_needwakeup &= ~wakeup; 707 crypto_unblock(sc->sc_cid, wakeup); 708 } 709} 710 711/* 712 * ubsec_feed() - aggregate and post requests to chip 713 */ 714static void 715ubsec_feed(struct ubsec_softc *sc) 716{ 717 struct ubsec_q *q, *q2; 718 int npkts, i; 719 void *v; 720 u_int32_t stat; 721 722 /* 723 * Decide how many ops to combine in a single MCR. We cannot 724 * aggregate more than UBS_MAX_AGGR because this is the number 725 * of slots defined in the data structure. Note that 726 * aggregation only happens if ops are marked batch'able. 727 * Aggregating ops reduces the number of interrupts to the host 728 * but also (potentially) increases the latency for processing 729 * completed ops as we only get an interrupt when all aggregated 730 * ops have completed. 731 */ 732 if (sc->sc_nqueue == 0) 733 return; 734 if (sc->sc_nqueue > 1) { 735 npkts = 0; 736 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) { 737 npkts++; 738 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0) 739 break; 740 } 741 } else 742 npkts = 1; 743 /* 744 * Check device status before going any further. 745 */ 746 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 747 if (stat & BS_STAT_DMAERR) { 748 ubsec_totalreset(sc); 749 ubsecstats.hst_dmaerr++; 750 } else 751 ubsecstats.hst_mcr1full++; 752 return; 753 } 754 if (sc->sc_nqueue > ubsecstats.hst_maxqueue) 755 ubsecstats.hst_maxqueue = sc->sc_nqueue; 756 if (npkts > UBS_MAX_AGGR) 757 npkts = UBS_MAX_AGGR; 758 if (npkts < 2) /* special case 1 op */ 759 goto feed1; 760 761 ubsecstats.hst_totbatch += npkts-1; 762#ifdef UBSEC_DEBUG 763 if (ubsec_debug) 764 printf("merging %d records\n", npkts); 765#endif /* UBSEC_DEBUG */ 766 767 q = SIMPLEQ_FIRST(&sc->sc_queue); 768 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 769 --sc->sc_nqueue; 770 771 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 772 if (q->q_dst_map != NULL) 773 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 774 775 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 776 777 for (i = 0; i < q->q_nstacked_mcrs; i++) { 778 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 779 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 780 BUS_DMASYNC_PREWRITE); 781 if (q2->q_dst_map != NULL) 782 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 783 BUS_DMASYNC_PREREAD); 784 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next); 785 --sc->sc_nqueue; 786 787 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - 788 sizeof(struct ubsec_mcr_add)); 789 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 790 q->q_stacked_mcr[i] = q2; 791 } 792 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 793 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 794 sc->sc_nqchip += npkts; 795 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 796 ubsecstats.hst_maxqchip = sc->sc_nqchip; 797 ubsec_dma_sync(&q->q_dma->d_alloc, 798 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 799 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 800 offsetof(struct ubsec_dmachunk, d_mcr)); 801 return; 802feed1: 803 q = SIMPLEQ_FIRST(&sc->sc_queue); 804 805 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 806 if (q->q_dst_map != NULL) 807 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 808 ubsec_dma_sync(&q->q_dma->d_alloc, 809 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 810 811 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 812 offsetof(struct ubsec_dmachunk, d_mcr)); 813#ifdef UBSEC_DEBUG 814 if (ubsec_debug) 815 printf("feed1: q->chip %p %08x stat %08x\n", 816 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr), 817 stat); 818#endif /* UBSEC_DEBUG */ 819 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 820 --sc->sc_nqueue; 821 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 822 sc->sc_nqchip++; 823 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 824 ubsecstats.hst_maxqchip = sc->sc_nqchip; 825 return; 826} 827 828/* 829 * Allocate a new 'session' and return an encoded session id. 'sidp' 830 * contains our registration id, and should contain an encoded session 831 * id on successful allocation. 832 */ 833static int 834ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 835{ 836 struct cryptoini *c, *encini = NULL, *macini = NULL; 837 struct ubsec_softc *sc = arg; 838 struct ubsec_session *ses = NULL; 839 MD5_CTX md5ctx; 840 SHA1_CTX sha1ctx; 841 int i, sesn; 842 843 if (sidp == NULL || cri == NULL || sc == NULL) 844 return (EINVAL); 845 846 for (c = cri; c != NULL; c = c->cri_next) { 847 if (c->cri_alg == CRYPTO_MD5_HMAC || 848 c->cri_alg == CRYPTO_SHA1_HMAC) { 849 if (macini) 850 return (EINVAL); 851 macini = c; 852 } else if (c->cri_alg == CRYPTO_DES_CBC || 853 c->cri_alg == CRYPTO_3DES_CBC) { 854 if (encini) 855 return (EINVAL); 856 encini = c; 857 } else 858 return (EINVAL); 859 } 860 if (encini == NULL && macini == NULL) 861 return (EINVAL); 862 863 if (sc->sc_sessions == NULL) { 864 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 865 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 866 if (ses == NULL) 867 return (ENOMEM); 868 sesn = 0; 869 sc->sc_nsessions = 1; 870 } else { 871 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 872 if (sc->sc_sessions[sesn].ses_used == 0) { 873 ses = &sc->sc_sessions[sesn]; 874 break; 875 } 876 } 877 878 if (ses == NULL) { 879 sesn = sc->sc_nsessions; 880 ses = (struct ubsec_session *)malloc((sesn + 1) * 881 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 882 if (ses == NULL) 883 return (ENOMEM); 884 bcopy(sc->sc_sessions, ses, sesn * 885 sizeof(struct ubsec_session)); 886 bzero(sc->sc_sessions, sesn * 887 sizeof(struct ubsec_session)); 888 free(sc->sc_sessions, M_DEVBUF); 889 sc->sc_sessions = ses; 890 ses = &sc->sc_sessions[sesn]; 891 sc->sc_nsessions++; 892 } 893 } 894 bzero(ses, sizeof(struct ubsec_session)); 895 ses->ses_used = 1; 896 897 if (encini) { 898 /* get an IV, network byte order */ 899 /* XXX may read fewer than requested */ 900 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 901 902 /* Go ahead and compute key in ubsec's byte order */ 903 if (encini->cri_alg == CRYPTO_DES_CBC) { 904 bcopy(encini->cri_key, &ses->ses_deskey[0], 8); 905 bcopy(encini->cri_key, &ses->ses_deskey[2], 8); 906 bcopy(encini->cri_key, &ses->ses_deskey[4], 8); 907 } else 908 bcopy(encini->cri_key, ses->ses_deskey, 24); 909 910 SWAP32(ses->ses_deskey[0]); 911 SWAP32(ses->ses_deskey[1]); 912 SWAP32(ses->ses_deskey[2]); 913 SWAP32(ses->ses_deskey[3]); 914 SWAP32(ses->ses_deskey[4]); 915 SWAP32(ses->ses_deskey[5]); 916 } 917 918 if (macini) { 919 for (i = 0; i < macini->cri_klen / 8; i++) 920 macini->cri_key[i] ^= HMAC_IPAD_VAL; 921 922 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 923 MD5Init(&md5ctx); 924 MD5Update(&md5ctx, macini->cri_key, 925 macini->cri_klen / 8); 926 MD5Update(&md5ctx, hmac_ipad_buffer, 927 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 928 bcopy(md5ctx.state, ses->ses_hminner, 929 sizeof(md5ctx.state)); 930 } else { 931 SHA1Init(&sha1ctx); 932 SHA1Update(&sha1ctx, macini->cri_key, 933 macini->cri_klen / 8); 934 SHA1Update(&sha1ctx, hmac_ipad_buffer, 935 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 936 bcopy(sha1ctx.h.b32, ses->ses_hminner, 937 sizeof(sha1ctx.h.b32)); 938 } 939 940 for (i = 0; i < macini->cri_klen / 8; i++) 941 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 942 943 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 944 MD5Init(&md5ctx); 945 MD5Update(&md5ctx, macini->cri_key, 946 macini->cri_klen / 8); 947 MD5Update(&md5ctx, hmac_opad_buffer, 948 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 949 bcopy(md5ctx.state, ses->ses_hmouter, 950 sizeof(md5ctx.state)); 951 } else { 952 SHA1Init(&sha1ctx); 953 SHA1Update(&sha1ctx, macini->cri_key, 954 macini->cri_klen / 8); 955 SHA1Update(&sha1ctx, hmac_opad_buffer, 956 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 957 bcopy(sha1ctx.h.b32, ses->ses_hmouter, 958 sizeof(sha1ctx.h.b32)); 959 } 960 961 for (i = 0; i < macini->cri_klen / 8; i++) 962 macini->cri_key[i] ^= HMAC_OPAD_VAL; 963 } 964 965 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); 966 return (0); 967} 968 969/* 970 * Deallocate a session. 971 */ 972static int 973ubsec_freesession(void *arg, u_int64_t tid) 974{ 975 struct ubsec_softc *sc = arg; 976 int session, ret; 977 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 978 979 if (sc == NULL) 980 return (EINVAL); 981 982 session = UBSEC_SESSION(sid); 983 if (session < sc->sc_nsessions) { 984 bzero(&sc->sc_sessions[session], 985 sizeof(sc->sc_sessions[session])); 986 ret = 0; 987 } else 988 ret = EINVAL; 989 990 return (ret); 991} 992 993static void 994ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 995{ 996 struct ubsec_operand *op = arg; 997 998 KASSERT(nsegs <= UBS_MAX_SCATTER, 999 ("Too many DMA segments returned when mapping operand")); 1000#ifdef UBSEC_DEBUG 1001 if (ubsec_debug) 1002 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 1003 (u_int) mapsize, nsegs); 1004#endif 1005 op->mapsize = mapsize; 1006 op->nsegs = nsegs; 1007 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1008} 1009 1010static int 1011ubsec_process(void *arg, struct cryptop *crp, int hint) 1012{ 1013 struct ubsec_q *q = NULL; 1014 int err = 0, i, j, nicealign; 1015 struct ubsec_softc *sc = arg; 1016 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1017 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1018 int sskip, dskip, stheend, dtheend; 1019 int16_t coffset; 1020 struct ubsec_session *ses; 1021 struct ubsec_pktctx ctx; 1022 struct ubsec_dma *dmap = NULL; 1023 1024 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1025 ubsecstats.hst_invalid++; 1026 return (EINVAL); 1027 } 1028 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1029 ubsecstats.hst_badsession++; 1030 return (EINVAL); 1031 } 1032 1033 mtx_lock(&sc->sc_freeqlock); 1034 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1035 ubsecstats.hst_queuefull++; 1036 sc->sc_needwakeup |= CRYPTO_SYMQ; 1037 mtx_unlock(&sc->sc_freeqlock); 1038 return (ERESTART); 1039 } 1040 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1041 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 1042 mtx_unlock(&sc->sc_freeqlock); 1043 1044 dmap = q->q_dma; /* Save dma pointer */ 1045 bzero(q, sizeof(struct ubsec_q)); 1046 bzero(&ctx, sizeof(ctx)); 1047 1048 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1049 q->q_dma = dmap; 1050 ses = &sc->sc_sessions[q->q_sesn]; 1051 1052 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1053 q->q_src_m = (struct mbuf *)crp->crp_buf; 1054 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1055 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1056 q->q_src_io = (struct uio *)crp->crp_buf; 1057 q->q_dst_io = (struct uio *)crp->crp_buf; 1058 } else { 1059 ubsecstats.hst_badflags++; 1060 err = EINVAL; 1061 goto errout; /* XXX we don't handle contiguous blocks! */ 1062 } 1063 1064 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 1065 1066 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1067 dmap->d_dma->d_mcr.mcr_flags = 0; 1068 q->q_crp = crp; 1069 1070 crd1 = crp->crp_desc; 1071 if (crd1 == NULL) { 1072 ubsecstats.hst_nodesc++; 1073 err = EINVAL; 1074 goto errout; 1075 } 1076 crd2 = crd1->crd_next; 1077 1078 if (crd2 == NULL) { 1079 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 1080 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 1081 maccrd = crd1; 1082 enccrd = NULL; 1083 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1084 crd1->crd_alg == CRYPTO_3DES_CBC) { 1085 maccrd = NULL; 1086 enccrd = crd1; 1087 } else { 1088 ubsecstats.hst_badalg++; 1089 err = EINVAL; 1090 goto errout; 1091 } 1092 } else { 1093 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1094 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1095 (crd2->crd_alg == CRYPTO_DES_CBC || 1096 crd2->crd_alg == CRYPTO_3DES_CBC) && 1097 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1098 maccrd = crd1; 1099 enccrd = crd2; 1100 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1101 crd1->crd_alg == CRYPTO_3DES_CBC) && 1102 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1103 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1104 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1105 enccrd = crd1; 1106 maccrd = crd2; 1107 } else { 1108 /* 1109 * We cannot order the ubsec as requested 1110 */ 1111 ubsecstats.hst_badalg++; 1112 err = EINVAL; 1113 goto errout; 1114 } 1115 } 1116 1117 if (enccrd) { 1118 encoffset = enccrd->crd_skip; 1119 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1120 1121 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1122 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1123 1124 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1125 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1126 else { 1127 ctx.pc_iv[0] = ses->ses_iv[0]; 1128 ctx.pc_iv[1] = ses->ses_iv[1]; 1129 } 1130 1131 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1132 if (crp->crp_flags & CRYPTO_F_IMBUF) 1133 m_copyback(q->q_src_m, 1134 enccrd->crd_inject, 1135 8, (caddr_t)ctx.pc_iv); 1136 else if (crp->crp_flags & CRYPTO_F_IOV) 1137 cuio_copyback(q->q_src_io, 1138 enccrd->crd_inject, 1139 8, (caddr_t)ctx.pc_iv); 1140 } 1141 } else { 1142 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1143 1144 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1145 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1146 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1147 m_copydata(q->q_src_m, enccrd->crd_inject, 1148 8, (caddr_t)ctx.pc_iv); 1149 else if (crp->crp_flags & CRYPTO_F_IOV) 1150 cuio_copydata(q->q_src_io, 1151 enccrd->crd_inject, 8, 1152 (caddr_t)ctx.pc_iv); 1153 } 1154 1155 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1156 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1157 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1158 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1159 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1160 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1161 SWAP32(ctx.pc_iv[0]); 1162 SWAP32(ctx.pc_iv[1]); 1163 } 1164 1165 if (maccrd) { 1166 macoffset = maccrd->crd_skip; 1167 1168 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1169 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1170 else 1171 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1172 1173 for (i = 0; i < 5; i++) { 1174 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1175 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1176 1177 HTOLE32(ctx.pc_hminner[i]); 1178 HTOLE32(ctx.pc_hmouter[i]); 1179 } 1180 } 1181 1182 if (enccrd && maccrd) { 1183 /* 1184 * ubsec cannot handle packets where the end of encryption 1185 * and authentication are not the same, or where the 1186 * encrypted part begins before the authenticated part. 1187 */ 1188 if ((encoffset + enccrd->crd_len) != 1189 (macoffset + maccrd->crd_len)) { 1190 ubsecstats.hst_lenmismatch++; 1191 err = EINVAL; 1192 goto errout; 1193 } 1194 if (enccrd->crd_skip < maccrd->crd_skip) { 1195 ubsecstats.hst_skipmismatch++; 1196 err = EINVAL; 1197 goto errout; 1198 } 1199 sskip = maccrd->crd_skip; 1200 cpskip = dskip = enccrd->crd_skip; 1201 stheend = maccrd->crd_len; 1202 dtheend = enccrd->crd_len; 1203 coffset = enccrd->crd_skip - maccrd->crd_skip; 1204 cpoffset = cpskip + dtheend; 1205#ifdef UBSEC_DEBUG 1206 if (ubsec_debug) { 1207 printf("mac: skip %d, len %d, inject %d\n", 1208 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1209 printf("enc: skip %d, len %d, inject %d\n", 1210 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1211 printf("src: skip %d, len %d\n", sskip, stheend); 1212 printf("dst: skip %d, len %d\n", dskip, dtheend); 1213 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1214 coffset, stheend, cpskip, cpoffset); 1215 } 1216#endif 1217 } else { 1218 cpskip = dskip = sskip = macoffset + encoffset; 1219 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1220 cpoffset = cpskip + dtheend; 1221 coffset = 0; 1222 } 1223 ctx.pc_offset = htole16(coffset >> 2); 1224 1225 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) { 1226 ubsecstats.hst_nomap++; 1227 err = ENOMEM; 1228 goto errout; 1229 } 1230 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1231 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1232 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1233 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1234 q->q_src_map = NULL; 1235 ubsecstats.hst_noload++; 1236 err = ENOMEM; 1237 goto errout; 1238 } 1239 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1240 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1241 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1242 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1243 q->q_src_map = NULL; 1244 ubsecstats.hst_noload++; 1245 err = ENOMEM; 1246 goto errout; 1247 } 1248 } 1249 nicealign = ubsec_dmamap_aligned(&q->q_src); 1250 1251 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1252 1253#ifdef UBSEC_DEBUG 1254 if (ubsec_debug) 1255 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1256#endif 1257 for (i = j = 0; i < q->q_src_nsegs; i++) { 1258 struct ubsec_pktbuf *pb; 1259 bus_size_t packl = q->q_src_segs[i].ds_len; 1260 bus_addr_t packp = q->q_src_segs[i].ds_addr; 1261 1262 if (sskip >= packl) { 1263 sskip -= packl; 1264 continue; 1265 } 1266 1267 packl -= sskip; 1268 packp += sskip; 1269 sskip = 0; 1270 1271 if (packl > 0xfffc) { 1272 err = EIO; 1273 goto errout; 1274 } 1275 1276 if (j == 0) 1277 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1278 else 1279 pb = &dmap->d_dma->d_sbuf[j - 1]; 1280 1281 pb->pb_addr = htole32(packp); 1282 1283 if (stheend) { 1284 if (packl > stheend) { 1285 pb->pb_len = htole32(stheend); 1286 stheend = 0; 1287 } else { 1288 pb->pb_len = htole32(packl); 1289 stheend -= packl; 1290 } 1291 } else 1292 pb->pb_len = htole32(packl); 1293 1294 if ((i + 1) == q->q_src_nsegs) 1295 pb->pb_next = 0; 1296 else 1297 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1298 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1299 j++; 1300 } 1301 1302 if (enccrd == NULL && maccrd != NULL) { 1303 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1304 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1305 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1306 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1307#ifdef UBSEC_DEBUG 1308 if (ubsec_debug) 1309 printf("opkt: %x %x %x\n", 1310 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1311 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1312 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1313#endif 1314 } else { 1315 if (crp->crp_flags & CRYPTO_F_IOV) { 1316 if (!nicealign) { 1317 ubsecstats.hst_iovmisaligned++; 1318 err = EINVAL; 1319 goto errout; 1320 } 1321 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1322 &q->q_dst_map)) { 1323 ubsecstats.hst_nomap++; 1324 err = ENOMEM; 1325 goto errout; 1326 } 1327 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1328 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) { 1329 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1330 q->q_dst_map = NULL; 1331 ubsecstats.hst_noload++; 1332 err = ENOMEM; 1333 goto errout; 1334 } 1335 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1336 if (nicealign) { 1337 q->q_dst = q->q_src; 1338 } else { 1339 int totlen, len; 1340 struct mbuf *m, *top, **mp; 1341 1342 ubsecstats.hst_unaligned++; 1343 totlen = q->q_src_mapsize; 1344 if (q->q_src_m->m_flags & M_PKTHDR) { 1345 len = MHLEN; 1346 MGETHDR(m, M_DONTWAIT, MT_DATA); 1347 if (m && !m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)) { 1348 m_free(m); 1349 m = NULL; 1350 } 1351 } else { 1352 len = MLEN; 1353 MGET(m, M_DONTWAIT, MT_DATA); 1354 } 1355 if (m == NULL) { 1356 ubsecstats.hst_nombuf++; 1357 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1358 goto errout; 1359 } 1360 if (totlen >= MINCLSIZE) { 1361 MCLGET(m, M_DONTWAIT); 1362 if ((m->m_flags & M_EXT) == 0) { 1363 m_free(m); 1364 ubsecstats.hst_nomcl++; 1365 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1366 goto errout; 1367 } 1368 len = MCLBYTES; 1369 } 1370 m->m_len = len; 1371 top = NULL; 1372 mp = ⊤ 1373 1374 while (totlen > 0) { 1375 if (top) { 1376 MGET(m, M_DONTWAIT, MT_DATA); 1377 if (m == NULL) { 1378 m_freem(top); 1379 ubsecstats.hst_nombuf++; 1380 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1381 goto errout; 1382 } 1383 len = MLEN; 1384 } 1385 if (top && totlen >= MINCLSIZE) { 1386 MCLGET(m, M_DONTWAIT); 1387 if ((m->m_flags & M_EXT) == 0) { 1388 *mp = m; 1389 m_freem(top); 1390 ubsecstats.hst_nomcl++; 1391 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1392 goto errout; 1393 } 1394 len = MCLBYTES; 1395 } 1396 m->m_len = len = min(totlen, len); 1397 totlen -= len; 1398 *mp = m; 1399 mp = &m->m_next; 1400 } 1401 q->q_dst_m = top; 1402 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1403 cpskip, cpoffset); 1404 if (bus_dmamap_create(sc->sc_dmat, 1405 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) { 1406 ubsecstats.hst_nomap++; 1407 err = ENOMEM; 1408 goto errout; 1409 } 1410 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1411 q->q_dst_map, q->q_dst_m, 1412 ubsec_op_cb, &q->q_dst, 1413 BUS_DMA_NOWAIT) != 0) { 1414 bus_dmamap_destroy(sc->sc_dmat, 1415 q->q_dst_map); 1416 q->q_dst_map = NULL; 1417 ubsecstats.hst_noload++; 1418 err = ENOMEM; 1419 goto errout; 1420 } 1421 } 1422 } else { 1423 ubsecstats.hst_badflags++; 1424 err = EINVAL; 1425 goto errout; 1426 } 1427 1428#ifdef UBSEC_DEBUG 1429 if (ubsec_debug) 1430 printf("dst skip: %d\n", dskip); 1431#endif 1432 for (i = j = 0; i < q->q_dst_nsegs; i++) { 1433 struct ubsec_pktbuf *pb; 1434 bus_size_t packl = q->q_dst_segs[i].ds_len; 1435 bus_addr_t packp = q->q_dst_segs[i].ds_addr; 1436 1437 if (dskip >= packl) { 1438 dskip -= packl; 1439 continue; 1440 } 1441 1442 packl -= dskip; 1443 packp += dskip; 1444 dskip = 0; 1445 1446 if (packl > 0xfffc) { 1447 err = EIO; 1448 goto errout; 1449 } 1450 1451 if (j == 0) 1452 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1453 else 1454 pb = &dmap->d_dma->d_dbuf[j - 1]; 1455 1456 pb->pb_addr = htole32(packp); 1457 1458 if (dtheend) { 1459 if (packl > dtheend) { 1460 pb->pb_len = htole32(dtheend); 1461 dtheend = 0; 1462 } else { 1463 pb->pb_len = htole32(packl); 1464 dtheend -= packl; 1465 } 1466 } else 1467 pb->pb_len = htole32(packl); 1468 1469 if ((i + 1) == q->q_dst_nsegs) { 1470 if (maccrd) 1471 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1472 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1473 else 1474 pb->pb_next = 0; 1475 } else 1476 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1477 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1478 j++; 1479 } 1480 } 1481 1482 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1483 offsetof(struct ubsec_dmachunk, d_ctx)); 1484 1485 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1486 struct ubsec_pktctx_long *ctxl; 1487 1488 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr + 1489 offsetof(struct ubsec_dmachunk, d_ctx)); 1490 1491 /* transform small context into long context */ 1492 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1493 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1494 ctxl->pc_flags = ctx.pc_flags; 1495 ctxl->pc_offset = ctx.pc_offset; 1496 for (i = 0; i < 6; i++) 1497 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1498 for (i = 0; i < 5; i++) 1499 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1500 for (i = 0; i < 5; i++) 1501 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1502 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1503 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1504 } else 1505 bcopy(&ctx, dmap->d_alloc.dma_vaddr + 1506 offsetof(struct ubsec_dmachunk, d_ctx), 1507 sizeof(struct ubsec_pktctx)); 1508 1509 mtx_lock(&sc->sc_mcr1lock); 1510 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1511 sc->sc_nqueue++; 1512 ubsecstats.hst_ipackets++; 1513 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size; 1514 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR) 1515 ubsec_feed(sc); 1516 mtx_unlock(&sc->sc_mcr1lock); 1517 return (0); 1518 1519errout: 1520 if (q != NULL) { 1521 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1522 m_freem(q->q_dst_m); 1523 1524 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1525 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1526 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1527 } 1528 if (q->q_src_map != NULL) { 1529 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1530 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1531 } 1532 1533 mtx_lock(&sc->sc_freeqlock); 1534 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1535 mtx_unlock(&sc->sc_freeqlock); 1536 } 1537 if (err != ERESTART) { 1538 crp->crp_etype = err; 1539 crypto_done(crp); 1540 } else { 1541 sc->sc_needwakeup |= CRYPTO_SYMQ; 1542 } 1543 return (err); 1544} 1545 1546static void 1547ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1548{ 1549 struct cryptop *crp = (struct cryptop *)q->q_crp; 1550 struct cryptodesc *crd; 1551 struct ubsec_dma *dmap = q->q_dma; 1552 1553 ubsecstats.hst_opackets++; 1554 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1555 1556 ubsec_dma_sync(&dmap->d_alloc, 1557 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1558 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1559 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1560 BUS_DMASYNC_POSTREAD); 1561 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1562 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1563 } 1564 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE); 1565 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1566 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1567 1568 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1569 m_freem(q->q_src_m); 1570 crp->crp_buf = (caddr_t)q->q_dst_m; 1571 } 1572 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len; 1573 1574 /* copy out IV for future use */ 1575 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1576 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1577 if (crd->crd_alg != CRYPTO_DES_CBC && 1578 crd->crd_alg != CRYPTO_3DES_CBC) 1579 continue; 1580 if (crp->crp_flags & CRYPTO_F_IMBUF) 1581 m_copydata((struct mbuf *)crp->crp_buf, 1582 crd->crd_skip + crd->crd_len - 8, 8, 1583 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1584 else if (crp->crp_flags & CRYPTO_F_IOV) { 1585 cuio_copydata((struct uio *)crp->crp_buf, 1586 crd->crd_skip + crd->crd_len - 8, 8, 1587 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1588 } 1589 break; 1590 } 1591 } 1592 1593 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1594 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1595 crd->crd_alg != CRYPTO_SHA1_HMAC) 1596 continue; 1597 if (crp->crp_flags & CRYPTO_F_IMBUF) 1598 m_copyback((struct mbuf *)crp->crp_buf, 1599 crd->crd_inject, 12, 1600 (caddr_t)dmap->d_dma->d_macbuf); 1601 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1602 bcopy((caddr_t)dmap->d_dma->d_macbuf, 1603 crp->crp_mac, 12); 1604 break; 1605 } 1606 mtx_lock(&sc->sc_freeqlock); 1607 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1608 mtx_unlock(&sc->sc_freeqlock); 1609 crypto_done(crp); 1610} 1611 1612static void 1613ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1614{ 1615 int i, j, dlen, slen; 1616 caddr_t dptr, sptr; 1617 1618 j = 0; 1619 sptr = srcm->m_data; 1620 slen = srcm->m_len; 1621 dptr = dstm->m_data; 1622 dlen = dstm->m_len; 1623 1624 while (1) { 1625 for (i = 0; i < min(slen, dlen); i++) { 1626 if (j < hoffset || j >= toffset) 1627 *dptr++ = *sptr++; 1628 slen--; 1629 dlen--; 1630 j++; 1631 } 1632 if (slen == 0) { 1633 srcm = srcm->m_next; 1634 if (srcm == NULL) 1635 return; 1636 sptr = srcm->m_data; 1637 slen = srcm->m_len; 1638 } 1639 if (dlen == 0) { 1640 dstm = dstm->m_next; 1641 if (dstm == NULL) 1642 return; 1643 dptr = dstm->m_data; 1644 dlen = dstm->m_len; 1645 } 1646 } 1647} 1648 1649/* 1650 * feed the key generator, must be called at splimp() or higher. 1651 */ 1652static int 1653ubsec_feed2(struct ubsec_softc *sc) 1654{ 1655 struct ubsec_q2 *q; 1656 1657 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1658 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1659 break; 1660 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1661 1662 ubsec_dma_sync(&q->q_mcr, 1663 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1664 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE); 1665 1666 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1667 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next); 1668 --sc->sc_nqueue2; 1669 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1670 } 1671 return (0); 1672} 1673 1674/* 1675 * Callback for handling random numbers 1676 */ 1677static void 1678ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1679{ 1680 struct cryptkop *krp; 1681 struct ubsec_ctx_keyop *ctx; 1682 1683 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1684 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE); 1685 1686 switch (q->q_type) { 1687#ifndef UBSEC_NO_RNG 1688 case UBS_CTXOP_RNGBYPASS: { 1689 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1690 1691 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD); 1692 (*sc->sc_harvest)(sc->sc_rndtest, 1693 rng->rng_buf.dma_vaddr, 1694 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t)); 1695 rng->rng_used = 0; 1696 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1697 break; 1698 } 1699#endif 1700 case UBS_CTXOP_MODEXP: { 1701 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1702 u_int rlen, clen; 1703 1704 krp = me->me_krp; 1705 rlen = (me->me_modbits + 7) / 8; 1706 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1707 1708 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE); 1709 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE); 1710 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD); 1711 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE); 1712 1713 if (clen < rlen) 1714 krp->krp_status = E2BIG; 1715 else { 1716 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1717 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1718 (krp->krp_param[krp->krp_iparams].crp_nbits 1719 + 7) / 8); 1720 bcopy(me->me_C.dma_vaddr, 1721 krp->krp_param[krp->krp_iparams].crp_p, 1722 (me->me_modbits + 7) / 8); 1723 } else 1724 ubsec_kshift_l(me->me_shiftbits, 1725 me->me_C.dma_vaddr, me->me_normbits, 1726 krp->krp_param[krp->krp_iparams].crp_p, 1727 krp->krp_param[krp->krp_iparams].crp_nbits); 1728 } 1729 1730 crypto_kdone(krp); 1731 1732 /* bzero all potentially sensitive data */ 1733 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1734 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1735 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1736 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1737 1738 /* Can't free here, so put us on the free list. */ 1739 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1740 break; 1741 } 1742 case UBS_CTXOP_RSAPRIV: { 1743 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1744 u_int len; 1745 1746 krp = rp->rpr_krp; 1747 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE); 1748 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD); 1749 1750 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1751 bcopy(rp->rpr_msgout.dma_vaddr, 1752 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1753 1754 crypto_kdone(krp); 1755 1756 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1757 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1758 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1759 1760 /* Can't free here, so put us on the free list. */ 1761 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1762 break; 1763 } 1764 default: 1765 device_printf(sc->sc_dev, "unknown ctx op: %x\n", 1766 letoh16(ctx->ctx_op)); 1767 break; 1768 } 1769} 1770 1771#ifndef UBSEC_NO_RNG 1772static void 1773ubsec_rng(void *vsc) 1774{ 1775 struct ubsec_softc *sc = vsc; 1776 struct ubsec_q2_rng *rng = &sc->sc_rng; 1777 struct ubsec_mcr *mcr; 1778 struct ubsec_ctx_rngbypass *ctx; 1779 1780 mtx_lock(&sc->sc_mcr2lock); 1781 if (rng->rng_used) { 1782 mtx_unlock(&sc->sc_mcr2lock); 1783 return; 1784 } 1785 sc->sc_nqueue2++; 1786 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1787 goto out; 1788 1789 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1790 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1791 1792 mcr->mcr_pkts = htole16(1); 1793 mcr->mcr_flags = 0; 1794 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1795 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1796 mcr->mcr_ipktbuf.pb_len = 0; 1797 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1798 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1799 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1800 UBS_PKTBUF_LEN); 1801 mcr->mcr_opktbuf.pb_next = 0; 1802 1803 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1804 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS); 1805 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS; 1806 1807 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD); 1808 1809 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1810 rng->rng_used = 1; 1811 ubsec_feed2(sc); 1812 ubsecstats.hst_rng++; 1813 mtx_unlock(&sc->sc_mcr2lock); 1814 1815 return; 1816 1817out: 1818 /* 1819 * Something weird happened, generate our own call back. 1820 */ 1821 sc->sc_nqueue2--; 1822 mtx_unlock(&sc->sc_mcr2lock); 1823 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1824} 1825#endif /* UBSEC_NO_RNG */ 1826 1827static void 1828ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1829{ 1830 bus_addr_t *paddr = (bus_addr_t*) arg; 1831 *paddr = segs->ds_addr; 1832} 1833 1834static int 1835ubsec_dma_malloc( 1836 struct ubsec_softc *sc, 1837 bus_size_t size, 1838 struct ubsec_dma_alloc *dma, 1839 int mapflags 1840) 1841{ 1842 int r; 1843 1844 /* XXX could specify sc_dmat as parent but that just adds overhead */ 1845 r = bus_dma_tag_create(NULL, /* parent */ 1846 1, 0, /* alignment, bounds */ 1847 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1848 BUS_SPACE_MAXADDR, /* highaddr */ 1849 NULL, NULL, /* filter, filterarg */ 1850 size, /* maxsize */ 1851 1, /* nsegments */ 1852 size, /* maxsegsize */ 1853 BUS_DMA_ALLOCNOW, /* flags */ 1854 &dma->dma_tag); 1855 if (r != 0) { 1856 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1857 "bus_dma_tag_create failed; error %u\n", r); 1858 goto fail_0; 1859 } 1860 1861 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1862 if (r != 0) { 1863 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1864 "bus_dmamap_create failed; error %u\n", r); 1865 goto fail_1; 1866 } 1867 1868 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1869 BUS_DMA_NOWAIT, &dma->dma_map); 1870 if (r != 0) { 1871 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1872 "bus_dmammem_alloc failed; size %zu, error %u\n", 1873 size, r); 1874 goto fail_2; 1875 } 1876 1877 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1878 size, 1879 ubsec_dmamap_cb, 1880 &dma->dma_paddr, 1881 mapflags | BUS_DMA_NOWAIT); 1882 if (r != 0) { 1883 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1884 "bus_dmamap_load failed; error %u\n", r); 1885 goto fail_3; 1886 } 1887 1888 dma->dma_size = size; 1889 return (0); 1890 1891fail_3: 1892 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1893fail_2: 1894 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1895fail_1: 1896 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1897 bus_dma_tag_destroy(dma->dma_tag); 1898fail_0: 1899 dma->dma_map = NULL; 1900 dma->dma_tag = NULL; 1901 return (r); 1902} 1903 1904static void 1905ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1906{ 1907 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1908 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1909 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1910 bus_dma_tag_destroy(dma->dma_tag); 1911} 1912 1913/* 1914 * Resets the board. Values in the regesters are left as is 1915 * from the reset (i.e. initial values are assigned elsewhere). 1916 */ 1917static void 1918ubsec_reset_board(struct ubsec_softc *sc) 1919{ 1920 volatile u_int32_t ctrl; 1921 1922 ctrl = READ_REG(sc, BS_CTRL); 1923 ctrl |= BS_CTRL_RESET; 1924 WRITE_REG(sc, BS_CTRL, ctrl); 1925 1926 /* 1927 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1928 */ 1929 DELAY(10); 1930} 1931 1932/* 1933 * Init Broadcom registers 1934 */ 1935static void 1936ubsec_init_board(struct ubsec_softc *sc) 1937{ 1938 u_int32_t ctrl; 1939 1940 ctrl = READ_REG(sc, BS_CTRL); 1941 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1942 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1943 1944 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) 1945 ctrl |= BS_CTRL_MCR2INT; 1946 else 1947 ctrl &= ~BS_CTRL_MCR2INT; 1948 1949 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1950 ctrl &= ~BS_CTRL_SWNORM; 1951 1952 WRITE_REG(sc, BS_CTRL, ctrl); 1953} 1954 1955/* 1956 * Init Broadcom PCI registers 1957 */ 1958static void 1959ubsec_init_pciregs(device_t dev) 1960{ 1961#if 0 1962 u_int32_t misc; 1963 1964 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT); 1965 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT)) 1966 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT); 1967 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT)) 1968 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT); 1969 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc); 1970#endif 1971 1972 /* 1973 * This will set the cache line size to 1, this will 1974 * force the BCM58xx chip just to do burst read/writes. 1975 * Cache line read/writes are to slow 1976 */ 1977 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1); 1978} 1979 1980/* 1981 * Clean up after a chip crash. 1982 * It is assumed that the caller in splimp() 1983 */ 1984static void 1985ubsec_cleanchip(struct ubsec_softc *sc) 1986{ 1987 struct ubsec_q *q; 1988 1989 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 1990 q = SIMPLEQ_FIRST(&sc->sc_qchip); 1991 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 1992 ubsec_free_q(sc, q); 1993 } 1994 sc->sc_nqchip = 0; 1995} 1996 1997/* 1998 * free a ubsec_q 1999 * It is assumed that the caller is within splimp(). 2000 */ 2001static int 2002ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2003{ 2004 struct ubsec_q *q2; 2005 struct cryptop *crp; 2006 int npkts; 2007 int i; 2008 2009 npkts = q->q_nstacked_mcrs; 2010 2011 for (i = 0; i < npkts; i++) { 2012 if(q->q_stacked_mcr[i]) { 2013 q2 = q->q_stacked_mcr[i]; 2014 2015 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 2016 m_freem(q2->q_dst_m); 2017 2018 crp = (struct cryptop *)q2->q_crp; 2019 2020 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2021 2022 crp->crp_etype = EFAULT; 2023 crypto_done(crp); 2024 } else { 2025 break; 2026 } 2027 } 2028 2029 /* 2030 * Free header MCR 2031 */ 2032 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2033 m_freem(q->q_dst_m); 2034 2035 crp = (struct cryptop *)q->q_crp; 2036 2037 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2038 2039 crp->crp_etype = EFAULT; 2040 crypto_done(crp); 2041 return(0); 2042} 2043 2044/* 2045 * Routine to reset the chip and clean up. 2046 * It is assumed that the caller is in splimp() 2047 */ 2048static void 2049ubsec_totalreset(struct ubsec_softc *sc) 2050{ 2051 ubsec_reset_board(sc); 2052 ubsec_init_board(sc); 2053 ubsec_cleanchip(sc); 2054} 2055 2056static int 2057ubsec_dmamap_aligned(struct ubsec_operand *op) 2058{ 2059 int i; 2060 2061 for (i = 0; i < op->nsegs; i++) { 2062 if (op->segs[i].ds_addr & 3) 2063 return (0); 2064 if ((i != (op->nsegs - 1)) && 2065 (op->segs[i].ds_len & 3)) 2066 return (0); 2067 } 2068 return (1); 2069} 2070 2071static void 2072ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2073{ 2074 switch (q->q_type) { 2075 case UBS_CTXOP_MODEXP: { 2076 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2077 2078 ubsec_dma_free(sc, &me->me_q.q_mcr); 2079 ubsec_dma_free(sc, &me->me_q.q_ctx); 2080 ubsec_dma_free(sc, &me->me_M); 2081 ubsec_dma_free(sc, &me->me_E); 2082 ubsec_dma_free(sc, &me->me_C); 2083 ubsec_dma_free(sc, &me->me_epb); 2084 free(me, M_DEVBUF); 2085 break; 2086 } 2087 case UBS_CTXOP_RSAPRIV: { 2088 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2089 2090 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2091 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2092 ubsec_dma_free(sc, &rp->rpr_msgin); 2093 ubsec_dma_free(sc, &rp->rpr_msgout); 2094 free(rp, M_DEVBUF); 2095 break; 2096 } 2097 default: 2098 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type); 2099 break; 2100 } 2101} 2102 2103static int 2104ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2105{ 2106 struct ubsec_softc *sc = arg; 2107 int r; 2108 2109 if (krp == NULL || krp->krp_callback == NULL) 2110 return (EINVAL); 2111 2112 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2113 struct ubsec_q2 *q; 2114 2115 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2116 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next); 2117 ubsec_kfree(sc, q); 2118 } 2119 2120 switch (krp->krp_op) { 2121 case CRK_MOD_EXP: 2122 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2123 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2124 else 2125 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2126 break; 2127 case CRK_MOD_EXP_CRT: 2128 return (ubsec_kprocess_rsapriv(sc, krp, hint)); 2129 default: 2130 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n", 2131 krp->krp_op); 2132 krp->krp_status = EOPNOTSUPP; 2133 crypto_kdone(krp); 2134 return (0); 2135 } 2136 return (0); /* silence compiler */ 2137} 2138 2139/* 2140 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2141 */ 2142static int 2143ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2144{ 2145 struct ubsec_q2_modexp *me; 2146 struct ubsec_mcr *mcr; 2147 struct ubsec_ctx_modexp *ctx; 2148 struct ubsec_pktbuf *epb; 2149 int err = 0; 2150 u_int nbits, normbits, mbits, shiftbits, ebits; 2151 2152 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2153 if (me == NULL) { 2154 err = ENOMEM; 2155 goto errout; 2156 } 2157 bzero(me, sizeof *me); 2158 me->me_krp = krp; 2159 me->me_q.q_type = UBS_CTXOP_MODEXP; 2160 2161 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2162 if (nbits <= 512) 2163 normbits = 512; 2164 else if (nbits <= 768) 2165 normbits = 768; 2166 else if (nbits <= 1024) 2167 normbits = 1024; 2168 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2169 normbits = 1536; 2170 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2171 normbits = 2048; 2172 else { 2173 err = E2BIG; 2174 goto errout; 2175 } 2176 2177 shiftbits = normbits - nbits; 2178 2179 me->me_modbits = nbits; 2180 me->me_shiftbits = shiftbits; 2181 me->me_normbits = normbits; 2182 2183 /* Sanity check: result bits must be >= true modulus bits. */ 2184 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2185 err = ERANGE; 2186 goto errout; 2187 } 2188 2189 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2190 &me->me_q.q_mcr, 0)) { 2191 err = ENOMEM; 2192 goto errout; 2193 } 2194 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2195 2196 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2197 &me->me_q.q_ctx, 0)) { 2198 err = ENOMEM; 2199 goto errout; 2200 } 2201 2202 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2203 if (mbits > nbits) { 2204 err = E2BIG; 2205 goto errout; 2206 } 2207 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2208 err = ENOMEM; 2209 goto errout; 2210 } 2211 ubsec_kshift_r(shiftbits, 2212 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2213 me->me_M.dma_vaddr, normbits); 2214 2215 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2216 err = ENOMEM; 2217 goto errout; 2218 } 2219 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2220 2221 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2222 if (ebits > nbits) { 2223 err = E2BIG; 2224 goto errout; 2225 } 2226 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2227 err = ENOMEM; 2228 goto errout; 2229 } 2230 ubsec_kshift_r(shiftbits, 2231 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2232 me->me_E.dma_vaddr, normbits); 2233 2234 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2235 &me->me_epb, 0)) { 2236 err = ENOMEM; 2237 goto errout; 2238 } 2239 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2240 epb->pb_addr = htole32(me->me_E.dma_paddr); 2241 epb->pb_next = 0; 2242 epb->pb_len = htole32(normbits / 8); 2243 2244#ifdef UBSEC_DEBUG 2245 if (ubsec_debug) { 2246 printf("Epb "); 2247 ubsec_dump_pb(epb); 2248 } 2249#endif 2250 2251 mcr->mcr_pkts = htole16(1); 2252 mcr->mcr_flags = 0; 2253 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2254 mcr->mcr_reserved = 0; 2255 mcr->mcr_pktlen = 0; 2256 2257 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2258 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2259 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2260 2261 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2262 mcr->mcr_opktbuf.pb_next = 0; 2263 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2264 2265#ifdef DIAGNOSTIC 2266 /* Misaligned output buffer will hang the chip. */ 2267 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2268 panic("%s: modexp invalid addr 0x%x\n", 2269 device_get_nameunit(sc->sc_dev), 2270 letoh32(mcr->mcr_opktbuf.pb_addr)); 2271 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2272 panic("%s: modexp invalid len 0x%x\n", 2273 device_get_nameunit(sc->sc_dev), 2274 letoh32(mcr->mcr_opktbuf.pb_len)); 2275#endif 2276 2277 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2278 bzero(ctx, sizeof(*ctx)); 2279 ubsec_kshift_r(shiftbits, 2280 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2281 ctx->me_N, normbits); 2282 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2283 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2284 ctx->me_E_len = htole16(nbits); 2285 ctx->me_N_len = htole16(nbits); 2286 2287#ifdef UBSEC_DEBUG 2288 if (ubsec_debug) { 2289 ubsec_dump_mcr(mcr); 2290 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2291 } 2292#endif 2293 2294 /* 2295 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2296 * everything else. 2297 */ 2298 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2299 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2300 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2301 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2302 2303 /* Enqueue and we're done... */ 2304 mtx_lock(&sc->sc_mcr2lock); 2305 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2306 ubsec_feed2(sc); 2307 ubsecstats.hst_modexp++; 2308 mtx_unlock(&sc->sc_mcr2lock); 2309 2310 return (0); 2311 2312errout: 2313 if (me != NULL) { 2314 if (me->me_q.q_mcr.dma_map != NULL) 2315 ubsec_dma_free(sc, &me->me_q.q_mcr); 2316 if (me->me_q.q_ctx.dma_map != NULL) { 2317 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2318 ubsec_dma_free(sc, &me->me_q.q_ctx); 2319 } 2320 if (me->me_M.dma_map != NULL) { 2321 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2322 ubsec_dma_free(sc, &me->me_M); 2323 } 2324 if (me->me_E.dma_map != NULL) { 2325 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2326 ubsec_dma_free(sc, &me->me_E); 2327 } 2328 if (me->me_C.dma_map != NULL) { 2329 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2330 ubsec_dma_free(sc, &me->me_C); 2331 } 2332 if (me->me_epb.dma_map != NULL) 2333 ubsec_dma_free(sc, &me->me_epb); 2334 free(me, M_DEVBUF); 2335 } 2336 krp->krp_status = err; 2337 crypto_kdone(krp); 2338 return (0); 2339} 2340 2341/* 2342 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2343 */ 2344static int 2345ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2346{ 2347 struct ubsec_q2_modexp *me; 2348 struct ubsec_mcr *mcr; 2349 struct ubsec_ctx_modexp *ctx; 2350 struct ubsec_pktbuf *epb; 2351 int err = 0; 2352 u_int nbits, normbits, mbits, shiftbits, ebits; 2353 2354 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2355 if (me == NULL) { 2356 err = ENOMEM; 2357 goto errout; 2358 } 2359 bzero(me, sizeof *me); 2360 me->me_krp = krp; 2361 me->me_q.q_type = UBS_CTXOP_MODEXP; 2362 2363 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2364 if (nbits <= 512) 2365 normbits = 512; 2366 else if (nbits <= 768) 2367 normbits = 768; 2368 else if (nbits <= 1024) 2369 normbits = 1024; 2370 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2371 normbits = 1536; 2372 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2373 normbits = 2048; 2374 else { 2375 err = E2BIG; 2376 goto errout; 2377 } 2378 2379 shiftbits = normbits - nbits; 2380 2381 /* XXX ??? */ 2382 me->me_modbits = nbits; 2383 me->me_shiftbits = shiftbits; 2384 me->me_normbits = normbits; 2385 2386 /* Sanity check: result bits must be >= true modulus bits. */ 2387 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2388 err = ERANGE; 2389 goto errout; 2390 } 2391 2392 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2393 &me->me_q.q_mcr, 0)) { 2394 err = ENOMEM; 2395 goto errout; 2396 } 2397 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2398 2399 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2400 &me->me_q.q_ctx, 0)) { 2401 err = ENOMEM; 2402 goto errout; 2403 } 2404 2405 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2406 if (mbits > nbits) { 2407 err = E2BIG; 2408 goto errout; 2409 } 2410 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2411 err = ENOMEM; 2412 goto errout; 2413 } 2414 bzero(me->me_M.dma_vaddr, normbits / 8); 2415 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2416 me->me_M.dma_vaddr, (mbits + 7) / 8); 2417 2418 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2419 err = ENOMEM; 2420 goto errout; 2421 } 2422 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2423 2424 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2425 if (ebits > nbits) { 2426 err = E2BIG; 2427 goto errout; 2428 } 2429 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2430 err = ENOMEM; 2431 goto errout; 2432 } 2433 bzero(me->me_E.dma_vaddr, normbits / 8); 2434 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2435 me->me_E.dma_vaddr, (ebits + 7) / 8); 2436 2437 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2438 &me->me_epb, 0)) { 2439 err = ENOMEM; 2440 goto errout; 2441 } 2442 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2443 epb->pb_addr = htole32(me->me_E.dma_paddr); 2444 epb->pb_next = 0; 2445 epb->pb_len = htole32((ebits + 7) / 8); 2446 2447#ifdef UBSEC_DEBUG 2448 if (ubsec_debug) { 2449 printf("Epb "); 2450 ubsec_dump_pb(epb); 2451 } 2452#endif 2453 2454 mcr->mcr_pkts = htole16(1); 2455 mcr->mcr_flags = 0; 2456 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2457 mcr->mcr_reserved = 0; 2458 mcr->mcr_pktlen = 0; 2459 2460 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2461 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2462 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2463 2464 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2465 mcr->mcr_opktbuf.pb_next = 0; 2466 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2467 2468#ifdef DIAGNOSTIC 2469 /* Misaligned output buffer will hang the chip. */ 2470 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2471 panic("%s: modexp invalid addr 0x%x\n", 2472 device_get_nameunit(sc->sc_dev), 2473 letoh32(mcr->mcr_opktbuf.pb_addr)); 2474 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2475 panic("%s: modexp invalid len 0x%x\n", 2476 device_get_nameunit(sc->sc_dev), 2477 letoh32(mcr->mcr_opktbuf.pb_len)); 2478#endif 2479 2480 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2481 bzero(ctx, sizeof(*ctx)); 2482 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2483 (nbits + 7) / 8); 2484 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2485 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2486 ctx->me_E_len = htole16(ebits); 2487 ctx->me_N_len = htole16(nbits); 2488 2489#ifdef UBSEC_DEBUG 2490 if (ubsec_debug) { 2491 ubsec_dump_mcr(mcr); 2492 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2493 } 2494#endif 2495 2496 /* 2497 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2498 * everything else. 2499 */ 2500 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2501 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2502 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2503 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2504 2505 /* Enqueue and we're done... */ 2506 mtx_lock(&sc->sc_mcr2lock); 2507 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2508 ubsec_feed2(sc); 2509 mtx_unlock(&sc->sc_mcr2lock); 2510 2511 return (0); 2512 2513errout: 2514 if (me != NULL) { 2515 if (me->me_q.q_mcr.dma_map != NULL) 2516 ubsec_dma_free(sc, &me->me_q.q_mcr); 2517 if (me->me_q.q_ctx.dma_map != NULL) { 2518 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2519 ubsec_dma_free(sc, &me->me_q.q_ctx); 2520 } 2521 if (me->me_M.dma_map != NULL) { 2522 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2523 ubsec_dma_free(sc, &me->me_M); 2524 } 2525 if (me->me_E.dma_map != NULL) { 2526 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2527 ubsec_dma_free(sc, &me->me_E); 2528 } 2529 if (me->me_C.dma_map != NULL) { 2530 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2531 ubsec_dma_free(sc, &me->me_C); 2532 } 2533 if (me->me_epb.dma_map != NULL) 2534 ubsec_dma_free(sc, &me->me_epb); 2535 free(me, M_DEVBUF); 2536 } 2537 krp->krp_status = err; 2538 crypto_kdone(krp); 2539 return (0); 2540} 2541 2542static int 2543ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2544{ 2545 struct ubsec_q2_rsapriv *rp = NULL; 2546 struct ubsec_mcr *mcr; 2547 struct ubsec_ctx_rsapriv *ctx; 2548 int err = 0; 2549 u_int padlen, msglen; 2550 2551 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2552 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2553 if (msglen > padlen) 2554 padlen = msglen; 2555 2556 if (padlen <= 256) 2557 padlen = 256; 2558 else if (padlen <= 384) 2559 padlen = 384; 2560 else if (padlen <= 512) 2561 padlen = 512; 2562 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2563 padlen = 768; 2564 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2565 padlen = 1024; 2566 else { 2567 err = E2BIG; 2568 goto errout; 2569 } 2570 2571 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2572 err = E2BIG; 2573 goto errout; 2574 } 2575 2576 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2577 err = E2BIG; 2578 goto errout; 2579 } 2580 2581 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2582 err = E2BIG; 2583 goto errout; 2584 } 2585 2586 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT); 2587 if (rp == NULL) 2588 return (ENOMEM); 2589 bzero(rp, sizeof *rp); 2590 rp->rpr_krp = krp; 2591 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2592 2593 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2594 &rp->rpr_q.q_mcr, 0)) { 2595 err = ENOMEM; 2596 goto errout; 2597 } 2598 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2599 2600 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2601 &rp->rpr_q.q_ctx, 0)) { 2602 err = ENOMEM; 2603 goto errout; 2604 } 2605 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2606 bzero(ctx, sizeof *ctx); 2607 2608 /* Copy in p */ 2609 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2610 &ctx->rpr_buf[0 * (padlen / 8)], 2611 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2612 2613 /* Copy in q */ 2614 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2615 &ctx->rpr_buf[1 * (padlen / 8)], 2616 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2617 2618 /* Copy in dp */ 2619 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2620 &ctx->rpr_buf[2 * (padlen / 8)], 2621 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2622 2623 /* Copy in dq */ 2624 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2625 &ctx->rpr_buf[3 * (padlen / 8)], 2626 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2627 2628 /* Copy in pinv */ 2629 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2630 &ctx->rpr_buf[4 * (padlen / 8)], 2631 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2632 2633 msglen = padlen * 2; 2634 2635 /* Copy in input message (aligned buffer/length). */ 2636 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2637 /* Is this likely? */ 2638 err = E2BIG; 2639 goto errout; 2640 } 2641 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2642 err = ENOMEM; 2643 goto errout; 2644 } 2645 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2646 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2647 rp->rpr_msgin.dma_vaddr, 2648 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2649 2650 /* Prepare space for output message (aligned buffer/length). */ 2651 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2652 /* Is this likely? */ 2653 err = E2BIG; 2654 goto errout; 2655 } 2656 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2657 err = ENOMEM; 2658 goto errout; 2659 } 2660 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2661 2662 mcr->mcr_pkts = htole16(1); 2663 mcr->mcr_flags = 0; 2664 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2665 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2666 mcr->mcr_ipktbuf.pb_next = 0; 2667 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2668 mcr->mcr_reserved = 0; 2669 mcr->mcr_pktlen = htole16(msglen); 2670 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2671 mcr->mcr_opktbuf.pb_next = 0; 2672 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2673 2674#ifdef DIAGNOSTIC 2675 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2676 panic("%s: rsapriv: invalid msgin %x(0x%jx)", 2677 device_get_nameunit(sc->sc_dev), 2678 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size); 2679 } 2680 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2681 panic("%s: rsapriv: invalid msgout %x(0x%jx)", 2682 device_get_nameunit(sc->sc_dev), 2683 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size); 2684 } 2685#endif 2686 2687 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2688 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2689 ctx->rpr_q_len = htole16(padlen); 2690 ctx->rpr_p_len = htole16(padlen); 2691 2692 /* 2693 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2694 * everything else. 2695 */ 2696 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE); 2697 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD); 2698 2699 /* Enqueue and we're done... */ 2700 mtx_lock(&sc->sc_mcr2lock); 2701 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2702 ubsec_feed2(sc); 2703 ubsecstats.hst_modexpcrt++; 2704 mtx_unlock(&sc->sc_mcr2lock); 2705 return (0); 2706 2707errout: 2708 if (rp != NULL) { 2709 if (rp->rpr_q.q_mcr.dma_map != NULL) 2710 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2711 if (rp->rpr_msgin.dma_map != NULL) { 2712 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2713 ubsec_dma_free(sc, &rp->rpr_msgin); 2714 } 2715 if (rp->rpr_msgout.dma_map != NULL) { 2716 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2717 ubsec_dma_free(sc, &rp->rpr_msgout); 2718 } 2719 free(rp, M_DEVBUF); 2720 } 2721 krp->krp_status = err; 2722 crypto_kdone(krp); 2723 return (0); 2724} 2725 2726#ifdef UBSEC_DEBUG 2727static void 2728ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2729{ 2730 printf("addr 0x%x (0x%x) next 0x%x\n", 2731 pb->pb_addr, pb->pb_len, pb->pb_next); 2732} 2733 2734static void 2735ubsec_dump_ctx2(struct ubsec_ctx_keyop *c) 2736{ 2737 printf("CTX (0x%x):\n", c->ctx_len); 2738 switch (letoh16(c->ctx_op)) { 2739 case UBS_CTXOP_RNGBYPASS: 2740 case UBS_CTXOP_RNGSHA1: 2741 break; 2742 case UBS_CTXOP_MODEXP: 2743 { 2744 struct ubsec_ctx_modexp *cx = (void *)c; 2745 int i, len; 2746 2747 printf(" Elen %u, Nlen %u\n", 2748 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2749 len = (cx->me_N_len + 7)/8; 2750 for (i = 0; i < len; i++) 2751 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2752 printf("\n"); 2753 break; 2754 } 2755 default: 2756 printf("unknown context: %x\n", c->ctx_op); 2757 } 2758 printf("END CTX\n"); 2759} 2760 2761static void 2762ubsec_dump_mcr(struct ubsec_mcr *mcr) 2763{ 2764 volatile struct ubsec_mcr_add *ma; 2765 int i; 2766 2767 printf("MCR:\n"); 2768 printf(" pkts: %u, flags 0x%x\n", 2769 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2770 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2771 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2772 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2773 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2774 letoh16(ma->mcr_reserved)); 2775 printf(" %d: ipkt ", i); 2776 ubsec_dump_pb(&ma->mcr_ipktbuf); 2777 printf(" %d: opkt ", i); 2778 ubsec_dump_pb(&ma->mcr_opktbuf); 2779 ma++; 2780 } 2781 printf("END MCR\n"); 2782} 2783#endif /* UBSEC_DEBUG */ 2784 2785/* 2786 * Return the number of significant bits of a big number. 2787 */ 2788static int 2789ubsec_ksigbits(struct crparam *cr) 2790{ 2791 u_int plen = (cr->crp_nbits + 7) / 8; 2792 int i, sig = plen * 8; 2793 u_int8_t c, *p = cr->crp_p; 2794 2795 for (i = plen - 1; i >= 0; i--) { 2796 c = p[i]; 2797 if (c != 0) { 2798 while ((c & 0x80) == 0) { 2799 sig--; 2800 c <<= 1; 2801 } 2802 break; 2803 } 2804 sig -= 8; 2805 } 2806 return (sig); 2807} 2808 2809static void 2810ubsec_kshift_r( 2811 u_int shiftbits, 2812 u_int8_t *src, u_int srcbits, 2813 u_int8_t *dst, u_int dstbits) 2814{ 2815 u_int slen, dlen; 2816 int i, si, di, n; 2817 2818 slen = (srcbits + 7) / 8; 2819 dlen = (dstbits + 7) / 8; 2820 2821 for (i = 0; i < slen; i++) 2822 dst[i] = src[i]; 2823 for (i = 0; i < dlen - slen; i++) 2824 dst[slen + i] = 0; 2825 2826 n = shiftbits / 8; 2827 if (n != 0) { 2828 si = dlen - n - 1; 2829 di = dlen - 1; 2830 while (si >= 0) 2831 dst[di--] = dst[si--]; 2832 while (di >= 0) 2833 dst[di--] = 0; 2834 } 2835 2836 n = shiftbits % 8; 2837 if (n != 0) { 2838 for (i = dlen - 1; i > 0; i--) 2839 dst[i] = (dst[i] << n) | 2840 (dst[i - 1] >> (8 - n)); 2841 dst[0] = dst[0] << n; 2842 } 2843} 2844 2845static void 2846ubsec_kshift_l( 2847 u_int shiftbits, 2848 u_int8_t *src, u_int srcbits, 2849 u_int8_t *dst, u_int dstbits) 2850{ 2851 int slen, dlen, i, n; 2852 2853 slen = (srcbits + 7) / 8; 2854 dlen = (dstbits + 7) / 8; 2855 2856 n = shiftbits / 8; 2857 for (i = 0; i < slen; i++) 2858 dst[i] = src[i + n]; 2859 for (i = 0; i < dlen - slen; i++) 2860 dst[slen + i] = 0; 2861 2862 n = shiftbits % 8; 2863 if (n != 0) { 2864 for (i = 0; i < (dlen - 1); i++) 2865 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2866 dst[dlen - 1] = dst[dlen - 1] >> n; 2867 } 2868} 2869