ubsec.c revision 109623
1/* $FreeBSD: head/sys/dev/ubsec/ubsec.c 109623 2003-01-21 08:56:16Z alfred $ */ 2/* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */ 3 4/* 5 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 6 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 7 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 8 * 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Jason L. Wright 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 34 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Effort sponsored in part by the Defense Advanced Research Projects 38 * Agency (DARPA) and Air Force Research Laboratory, Air Force 39 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 40 * 41 */ 42 43#define UBSEC_DEBUG 44 45/* 46 * uBsec 5[56]01, 58xx hardware crypto accelerator 47 */ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/proc.h> 52#include <sys/errno.h> 53#include <sys/malloc.h> 54#include <sys/kernel.h> 55#include <sys/mbuf.h> 56#include <sys/lock.h> 57#include <sys/mutex.h> 58#include <sys/stdint.h> 59#include <sys/sysctl.h> 60#include <sys/endian.h> 61 62#include <vm/vm.h> 63#include <vm/pmap.h> 64 65#include <machine/clock.h> 66#include <machine/bus.h> 67#include <machine/resource.h> 68#include <sys/bus.h> 69#include <sys/rman.h> 70 71#include <crypto/sha1.h> 72#include <opencrypto/cryptodev.h> 73#include <opencrypto/cryptosoft.h> 74#include <sys/md5.h> 75#include <sys/random.h> 76 77#include <pci/pcivar.h> 78#include <pci/pcireg.h> 79 80/* grr, #defines for gratuitous incompatibility in queue.h */ 81#define SIMPLEQ_HEAD STAILQ_HEAD 82#define SIMPLEQ_ENTRY STAILQ_ENTRY 83#define SIMPLEQ_INIT STAILQ_INIT 84#define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL 85#define SIMPLEQ_EMPTY STAILQ_EMPTY 86#define SIMPLEQ_FIRST STAILQ_FIRST 87#define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD_UNTIL 88/* ditto for endian.h */ 89#define letoh16(x) le16toh(x) 90#define letoh32(x) le32toh(x) 91 92#include <dev/ubsec/ubsecreg.h> 93#include <dev/ubsec/ubsecvar.h> 94 95/* 96 * Prototypes and count for the pci_device structure 97 */ 98static int ubsec_probe(device_t); 99static int ubsec_attach(device_t); 100static int ubsec_detach(device_t); 101static int ubsec_suspend(device_t); 102static int ubsec_resume(device_t); 103static void ubsec_shutdown(device_t); 104 105static device_method_t ubsec_methods[] = { 106 /* Device interface */ 107 DEVMETHOD(device_probe, ubsec_probe), 108 DEVMETHOD(device_attach, ubsec_attach), 109 DEVMETHOD(device_detach, ubsec_detach), 110 DEVMETHOD(device_suspend, ubsec_suspend), 111 DEVMETHOD(device_resume, ubsec_resume), 112 DEVMETHOD(device_shutdown, ubsec_shutdown), 113 114 /* bus interface */ 115 DEVMETHOD(bus_print_child, bus_generic_print_child), 116 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 117 118 { 0, 0 } 119}; 120static driver_t ubsec_driver = { 121 "ubsec", 122 ubsec_methods, 123 sizeof (struct ubsec_softc) 124}; 125static devclass_t ubsec_devclass; 126 127DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0); 128MODULE_DEPEND(ubsec, crypto, 1, 1, 1); 129 130static void ubsec_intr(void *); 131static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *); 132static int ubsec_freesession(void *, u_int64_t); 133static int ubsec_process(void *, struct cryptop *, int); 134static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 135static int ubsec_feed(struct ubsec_softc *); 136static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 137static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 138static int ubsec_feed2(struct ubsec_softc *); 139static void ubsec_rng(void *); 140static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 141 struct ubsec_dma_alloc *, int); 142#define ubsec_dma_sync(_dma, _flags) \ 143 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 144static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 145static int ubsec_dmamap_aligned(struct ubsec_operand *op); 146 147static void ubsec_reset_board(struct ubsec_softc *sc); 148static void ubsec_init_board(struct ubsec_softc *sc); 149static void ubsec_init_pciregs(device_t dev); 150static void ubsec_totalreset(struct ubsec_softc *sc); 151 152static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q); 153 154static int ubsec_kprocess(void*, struct cryptkop *, int); 155static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int); 156static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int); 157static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int); 158static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 159static int ubsec_ksigbits(struct crparam *); 160static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 161static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 162 163SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters"); 164 165#ifdef UBSEC_DEBUG 166static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 167static void ubsec_dump_mcr(struct ubsec_mcr *); 168static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *); 169 170static int ubsec_debug = 0; 171SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug, 172 0, "control debugging msgs"); 173#endif 174 175#define READ_REG(sc,r) \ 176 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 177 178#define WRITE_REG(sc,reg,val) \ 179 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 180 181#define SWAP32(x) (x) = htole32(ntohl((x))) 182#define HTOLE32(x) (x) = htole32(x) 183 184struct ubsec_stats ubsecstats; 185SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats, 186 ubsec_stats, "driver statistics"); 187/* 188 * ubsec_maxbatch controls the number of crypto ops to voluntarily 189 * collect into one submission to the hardware. This batching happens 190 * when ops are dispatched from the crypto subsystem with a hint that 191 * more are to follow immediately. These ops must also not be marked 192 * with a ``no delay'' flag. 193 */ 194static int ubsec_maxbatch = 1; 195SYSCTL_INT(_hw_ubsec, OID_AUTO, maxbatch, CTLFLAG_RW, &ubsec_maxbatch, 196 0, "max ops to batch w/o interrupt"); 197/* 198 * ubsec_maxaggr controls the number of crypto ops to submit to the 199 * hardware as a unit. This aggregation reduces the number of interrupts 200 * to the host at the expense of increased latency (for all but the last 201 * operation). For network traffic setting this to one yields the highest 202 * performance but at the expense of more interrupt processing. 203 */ 204static int ubsec_maxaggr = 1; 205SYSCTL_INT(_hw_ubsec, OID_AUTO, maxaggr, CTLFLAG_RW, &ubsec_maxaggr, 206 0, "max ops to aggregate under one interrupt"); 207 208static int 209ubsec_probe(device_t dev) 210{ 211 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 212 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 || 213 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)) 214 return (0); 215 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 216 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 || 217 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 || 218 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 219 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822)) 220 return (0); 221 return (ENXIO); 222} 223 224static const char* 225ubsec_partname(struct ubsec_softc *sc) 226{ 227 /* XXX sprintf numbers when not decoded */ 228 switch (pci_get_vendor(sc->sc_dev)) { 229 case PCI_VENDOR_BROADCOM: 230 switch (pci_get_device(sc->sc_dev)) { 231 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805"; 232 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820"; 233 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821"; 234 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822"; 235 } 236 return "Broadcom unknown-part"; 237 case PCI_VENDOR_BLUESTEEL: 238 switch (pci_get_device(sc->sc_dev)) { 239 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601"; 240 } 241 return "Bluesteel unknown-part"; 242 } 243 return "Unknown-vendor unknown-part"; 244} 245 246static int 247ubsec_attach(device_t dev) 248{ 249 struct ubsec_softc *sc = device_get_softc(dev); 250 struct ubsec_dma *dmap; 251 u_int32_t cmd, i; 252 int rid; 253 254 KASSERT(sc != NULL, ("ubsec_attach: null software carrier!")); 255 bzero(sc, sizeof (*sc)); 256 sc->sc_dev = dev; 257 258 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "crypto driver", MTX_DEF); 259 260 SIMPLEQ_INIT(&sc->sc_queue); 261 SIMPLEQ_INIT(&sc->sc_qchip); 262 SIMPLEQ_INIT(&sc->sc_queue2); 263 SIMPLEQ_INIT(&sc->sc_qchip2); 264 SIMPLEQ_INIT(&sc->sc_q2free); 265 266 /* XXX handle power management */ 267 268 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; 269 270 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 271 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601) 272 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 273 274 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 275 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805) 276 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 277 278 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 279 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820) 280 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 281 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 282 283 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 284 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 285 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822)) { 286 /* NB: the 5821/5822 defines some additional status bits */ 287 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY | 288 BS_STAT_MCR2_ALLEMPTY; 289 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 290 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 291 } 292 293 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 294 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 295 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 296 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 297 298 if (!(cmd & PCIM_CMD_MEMEN)) { 299 device_printf(dev, "failed to enable memory mapping\n"); 300 goto bad; 301 } 302 303 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 304 device_printf(dev, "failed to enable bus mastering\n"); 305 goto bad; 306 } 307 308 /* 309 * Setup memory-mapping of PCI registers. 310 */ 311 rid = BS_BAR; 312 sc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 313 0, ~0, 1, RF_ACTIVE); 314 if (sc->sc_sr == NULL) { 315 device_printf(dev, "cannot map register space\n"); 316 goto bad; 317 } 318 sc->sc_st = rman_get_bustag(sc->sc_sr); 319 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 320 321 /* 322 * Arrange interrupt line. 323 */ 324 rid = 0; 325 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 326 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 327 if (sc->sc_irq == NULL) { 328 device_printf(dev, "could not map interrupt\n"); 329 goto bad1; 330 } 331 /* 332 * NB: Network code assumes we are blocked with splimp() 333 * so make sure the IRQ is mapped appropriately. 334 */ 335 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 336 ubsec_intr, sc, &sc->sc_ih)) { 337 device_printf(dev, "could not establish interrupt\n"); 338 goto bad2; 339 } 340 341 sc->sc_cid = crypto_get_driverid(0); 342 if (sc->sc_cid < 0) { 343 device_printf(dev, "could not get crypto driver id\n"); 344 goto bad3; 345 } 346 347 /* 348 * Setup DMA descriptor area. 349 */ 350 if (bus_dma_tag_create(NULL, /* parent */ 351 1, 0, /* alignment, bounds */ 352 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 353 BUS_SPACE_MAXADDR, /* highaddr */ 354 NULL, NULL, /* filter, filterarg */ 355 0x3ffff, /* maxsize */ 356 UBS_MAX_SCATTER, /* nsegments */ 357 0xffff, /* maxsegsize */ 358 BUS_DMA_ALLOCNOW, /* flags */ 359 &sc->sc_dmat)) { 360 device_printf(dev, "cannot allocate DMA tag\n"); 361 goto bad4; 362 } 363 SIMPLEQ_INIT(&sc->sc_freequeue); 364 dmap = sc->sc_dmaa; 365 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 366 struct ubsec_q *q; 367 368 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 369 M_DEVBUF, M_NOWAIT); 370 if (q == NULL) { 371 device_printf(dev, "cannot allocate queue buffers\n"); 372 break; 373 } 374 375 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 376 &dmap->d_alloc, 0)) { 377 device_printf(dev, "cannot allocate dma buffers\n"); 378 free(q, M_DEVBUF); 379 break; 380 } 381 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 382 383 q->q_dma = dmap; 384 sc->sc_queuea[i] = q; 385 386 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 387 } 388 389 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc)); 390 391 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 392 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 393 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 394 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 395 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 396 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 397 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 398 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 399 400 /* 401 * Reset Broadcom chip 402 */ 403 ubsec_reset_board(sc); 404 405 /* 406 * Init Broadcom specific PCI settings 407 */ 408 ubsec_init_pciregs(dev); 409 410 /* 411 * Init Broadcom chip 412 */ 413 ubsec_init_board(sc); 414 415#ifndef UBSEC_NO_RNG 416 if (sc->sc_flags & UBS_FLAGS_RNG) { 417 sc->sc_statmask |= BS_STAT_MCR2_DONE; 418 419 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 420 &sc->sc_rng.rng_q.q_mcr, 0)) 421 goto skip_rng; 422 423 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 424 &sc->sc_rng.rng_q.q_ctx, 0)) { 425 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 426 goto skip_rng; 427 } 428 429 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 430 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 431 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 432 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 433 goto skip_rng; 434 } 435 436 if (hz >= 100) 437 sc->sc_rnghz = hz / 100; 438 else 439 sc->sc_rnghz = 1; 440 /* NB: 1 means the callout runs w/o Giant locked */ 441 callout_init(&sc->sc_rngto, 1); 442 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 443skip_rng: 444 ; 445 } 446#endif /* UBSEC_NO_RNG */ 447 448 if (sc->sc_flags & UBS_FLAGS_KEY) { 449 sc->sc_statmask |= BS_STAT_MCR2_DONE; 450 451 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 452 ubsec_kprocess, sc); 453#if 0 454 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 455 ubsec_kprocess, sc); 456#endif 457 } 458 return (0); 459bad4: 460 crypto_unregister_all(sc->sc_cid); 461bad3: 462 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 463bad2: 464 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 465bad1: 466 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 467bad: 468 mtx_destroy(&sc->sc_mtx); 469 return (ENXIO); 470} 471 472/* 473 * Detach a device that successfully probed. 474 */ 475static int 476ubsec_detach(device_t dev) 477{ 478 struct ubsec_softc *sc = device_get_softc(dev); 479 480 KASSERT(sc != NULL, ("ubsec_detach: null software carrier")); 481 482 /* XXX wait/abort active ops */ 483 484 UBSEC_LOCK(sc); 485 486 callout_stop(&sc->sc_rngto); 487 488 crypto_unregister_all(sc->sc_cid); 489 490 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 491 struct ubsec_q *q; 492 493 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 494 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 495 ubsec_dma_free(sc, &q->q_dma->d_alloc); 496 free(q, M_DEVBUF); 497 } 498#ifndef UBSEC_NO_RNG 499 if (sc->sc_flags & UBS_FLAGS_RNG) { 500 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 501 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 502 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 503 } 504#endif /* UBSEC_NO_RNG */ 505 506 bus_generic_detach(dev); 507 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 508 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 509 510 bus_dma_tag_destroy(sc->sc_dmat); 511 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 512 513 UBSEC_UNLOCK(sc); 514 515 mtx_destroy(&sc->sc_mtx); 516 517 return (0); 518} 519 520/* 521 * Stop all chip i/o so that the kernel's probe routines don't 522 * get confused by errant DMAs when rebooting. 523 */ 524static void 525ubsec_shutdown(device_t dev) 526{ 527#ifdef notyet 528 ubsec_stop(device_get_softc(dev)); 529#endif 530} 531 532/* 533 * Device suspend routine. 534 */ 535static int 536ubsec_suspend(device_t dev) 537{ 538 struct ubsec_softc *sc = device_get_softc(dev); 539 540 KASSERT(sc != NULL, ("ubsec_suspend: null software carrier")); 541#ifdef notyet 542 /* XXX stop the device and save PCI settings */ 543#endif 544 sc->sc_suspended = 1; 545 546 return (0); 547} 548 549static int 550ubsec_resume(device_t dev) 551{ 552 struct ubsec_softc *sc = device_get_softc(dev); 553 554 KASSERT(sc != NULL, ("ubsec_resume: null software carrier")); 555#ifdef notyet 556 /* XXX retore PCI settings and start the device */ 557#endif 558 sc->sc_suspended = 0; 559 return (0); 560} 561 562/* 563 * UBSEC Interrupt routine 564 */ 565static void 566ubsec_intr(void *arg) 567{ 568 struct ubsec_softc *sc = arg; 569 volatile u_int32_t stat; 570 struct ubsec_q *q; 571 struct ubsec_dma *dmap; 572 int npkts = 0, i; 573 574 UBSEC_LOCK(sc); 575 576 stat = READ_REG(sc, BS_STAT); 577 stat &= sc->sc_statmask; 578 if (stat == 0) { 579 UBSEC_UNLOCK(sc); 580 return; 581 } 582 583 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 584 585 /* 586 * Check to see if we have any packets waiting for us 587 */ 588 if ((stat & BS_STAT_MCR1_DONE)) { 589 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 590 q = SIMPLEQ_FIRST(&sc->sc_qchip); 591 dmap = q->q_dma; 592 593 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 594 break; 595 596 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 597 598 npkts = q->q_nstacked_mcrs; 599 sc->sc_nqchip -= 1+npkts; 600 /* 601 * search for further sc_qchip ubsec_q's that share 602 * the same MCR, and complete them too, they must be 603 * at the top. 604 */ 605 for (i = 0; i < npkts; i++) { 606 if(q->q_stacked_mcr[i]) { 607 ubsec_callback(sc, q->q_stacked_mcr[i]); 608 ubsecstats.hst_opackets++; 609 } else { 610 break; 611 } 612 } 613 ubsec_callback(sc, q); 614 ubsecstats.hst_opackets++; 615 } 616 617 /* 618 * Don't send any more packet to chip if there has been 619 * a DMAERR. 620 */ 621 if (!(stat & BS_STAT_DMAERR)) 622 ubsec_feed(sc); 623 } 624 625 /* 626 * Check to see if we have any key setups/rng's waiting for us 627 */ 628 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 629 (stat & BS_STAT_MCR2_DONE)) { 630 struct ubsec_q2 *q2; 631 struct ubsec_mcr *mcr; 632 633 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 634 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 635 636 ubsec_dma_sync(&q2->q_mcr, 637 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 638 639 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 640 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 641 ubsec_dma_sync(&q2->q_mcr, 642 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 643 break; 644 } 645 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next); 646 ubsec_callback2(sc, q2); 647 /* 648 * Don't send any more packet to chip if there has been 649 * a DMAERR. 650 */ 651 if (!(stat & BS_STAT_DMAERR)) 652 ubsec_feed2(sc); 653 } 654 } 655 656 /* 657 * Check to see if we got any DMA Error 658 */ 659 if (stat & BS_STAT_DMAERR) { 660#ifdef UBSEC_DEBUG 661 if (ubsec_debug) { 662 volatile u_int32_t a = READ_REG(sc, BS_ERR); 663 664 printf("dmaerr %s@%08x\n", 665 (a & BS_ERR_READ) ? "read" : "write", 666 a & BS_ERR_ADDR); 667 } 668#endif /* UBSEC_DEBUG */ 669 ubsecstats.hst_dmaerr++; 670 ubsec_totalreset(sc); 671 ubsec_feed(sc); 672 } 673 674 if (sc->sc_needwakeup) { /* XXX check high watermark */ 675 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 676#ifdef UBSEC_DEBUG 677 if (ubsec_debug) 678 device_printf(sc->sc_dev, "wakeup crypto (%x)\n", 679 sc->sc_needwakeup); 680#endif /* UBSEC_DEBUG */ 681 sc->sc_needwakeup &= ~wakeup; 682 crypto_unblock(sc->sc_cid, wakeup); 683 } 684 685 UBSEC_UNLOCK(sc); 686} 687 688/* 689 * ubsec_feed() - aggregate and post requests to chip 690 */ 691static int 692ubsec_feed(struct ubsec_softc *sc) 693{ 694 struct ubsec_q *q, *q2; 695 int npkts, i; 696 void *v; 697 u_int32_t stat; 698 699 npkts = sc->sc_nqueue; 700 if (npkts > ubsecstats.hst_maxqueue) 701 ubsecstats.hst_maxqueue = npkts; 702 /* 703 * Decide how many ops to combine in a single MCR. We cannot 704 * aggregate more than UBS_MAX_AGGR because this is the number 705 * of slots defined in the data structure. Otherwise we clamp 706 * based on the tunable parameter ubsec_maxaggr. Note that 707 * aggregation can happen in two ways: either by batching ops 708 * from above or because the h/w backs up and throttles us. 709 * Aggregating ops reduces the number of interrupts to the host 710 * but also (potentially) increases the latency for processing 711 * completed ops as we only get an interrupt when all aggregated 712 * ops have completed. 713 */ 714 if (npkts > UBS_MAX_AGGR) 715 npkts = UBS_MAX_AGGR; 716 if (npkts > ubsec_maxaggr) 717 npkts = ubsec_maxaggr; 718 if (npkts > ubsecstats.hst_maxbatch) 719 ubsecstats.hst_maxbatch = npkts; 720 if (npkts < 2) 721 goto feed1; 722 ubsecstats.hst_totbatch += npkts-1; 723 724 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 725 if (stat & BS_STAT_DMAERR) { 726 ubsec_totalreset(sc); 727 ubsecstats.hst_dmaerr++; 728 } else 729 ubsecstats.hst_mcr1full++; 730 return (0); 731 } 732 733#ifdef UBSEC_DEBUG 734 if (ubsec_debug) 735 printf("merging %d records\n", npkts); 736#endif /* UBSEC_DEBUG */ 737 738 q = SIMPLEQ_FIRST(&sc->sc_queue); 739 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 740 --sc->sc_nqueue; 741 742 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 743 if (q->q_dst_map != NULL) 744 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 745 746 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 747 748 for (i = 0; i < q->q_nstacked_mcrs; i++) { 749 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 750 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 751 BUS_DMASYNC_PREWRITE); 752 if (q2->q_dst_map != NULL) 753 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 754 BUS_DMASYNC_PREREAD); 755 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next); 756 --sc->sc_nqueue; 757 758 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - 759 sizeof(struct ubsec_mcr_add)); 760 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 761 q->q_stacked_mcr[i] = q2; 762 } 763 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 764 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 765 sc->sc_nqchip += npkts; 766 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 767 ubsecstats.hst_maxqchip = sc->sc_nqchip; 768 ubsec_dma_sync(&q->q_dma->d_alloc, 769 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 770 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 771 offsetof(struct ubsec_dmachunk, d_mcr)); 772 return (0); 773 774feed1: 775 while (!SIMPLEQ_EMPTY(&sc->sc_queue)) { 776 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 777 if (stat & BS_STAT_DMAERR) { 778 ubsec_totalreset(sc); 779 ubsecstats.hst_dmaerr++; 780 } else 781 ubsecstats.hst_mcr1full++; 782 break; 783 } 784 785 q = SIMPLEQ_FIRST(&sc->sc_queue); 786 787 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 788 BUS_DMASYNC_PREWRITE); 789 if (q->q_dst_map != NULL) 790 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 791 BUS_DMASYNC_PREREAD); 792 ubsec_dma_sync(&q->q_dma->d_alloc, 793 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 794 795 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 796 offsetof(struct ubsec_dmachunk, d_mcr)); 797#ifdef UBSEC_DEBUG 798 if (ubsec_debug) 799 printf("feed: q->chip %p %08x stat %08x\n", 800 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr), 801 stat); 802#endif /* UBSEC_DEBUG */ 803 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 804 --sc->sc_nqueue; 805 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 806 sc->sc_nqchip++; 807 } 808 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 809 ubsecstats.hst_maxqchip = sc->sc_nqchip; 810 return (0); 811} 812 813/* 814 * Allocate a new 'session' and return an encoded session id. 'sidp' 815 * contains our registration id, and should contain an encoded session 816 * id on successful allocation. 817 */ 818static int 819ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 820{ 821 struct cryptoini *c, *encini = NULL, *macini = NULL; 822 struct ubsec_softc *sc = arg; 823 struct ubsec_session *ses = NULL; 824 MD5_CTX md5ctx; 825 SHA1_CTX sha1ctx; 826 int i, sesn; 827 828 KASSERT(sc != NULL, ("ubsec_newsession: null softc")); 829 if (sidp == NULL || cri == NULL || sc == NULL) 830 return (EINVAL); 831 832 for (c = cri; c != NULL; c = c->cri_next) { 833 if (c->cri_alg == CRYPTO_MD5_HMAC || 834 c->cri_alg == CRYPTO_SHA1_HMAC) { 835 if (macini) 836 return (EINVAL); 837 macini = c; 838 } else if (c->cri_alg == CRYPTO_DES_CBC || 839 c->cri_alg == CRYPTO_3DES_CBC) { 840 if (encini) 841 return (EINVAL); 842 encini = c; 843 } else 844 return (EINVAL); 845 } 846 if (encini == NULL && macini == NULL) 847 return (EINVAL); 848 849 if (sc->sc_sessions == NULL) { 850 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 851 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 852 if (ses == NULL) 853 return (ENOMEM); 854 sesn = 0; 855 sc->sc_nsessions = 1; 856 } else { 857 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 858 if (sc->sc_sessions[sesn].ses_used == 0) { 859 ses = &sc->sc_sessions[sesn]; 860 break; 861 } 862 } 863 864 if (ses == NULL) { 865 sesn = sc->sc_nsessions; 866 ses = (struct ubsec_session *)malloc((sesn + 1) * 867 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 868 if (ses == NULL) 869 return (ENOMEM); 870 bcopy(sc->sc_sessions, ses, sesn * 871 sizeof(struct ubsec_session)); 872 bzero(sc->sc_sessions, sesn * 873 sizeof(struct ubsec_session)); 874 free(sc->sc_sessions, M_DEVBUF); 875 sc->sc_sessions = ses; 876 ses = &sc->sc_sessions[sesn]; 877 sc->sc_nsessions++; 878 } 879 } 880 881 bzero(ses, sizeof(struct ubsec_session)); 882 ses->ses_used = 1; 883 if (encini) { 884 /* get an IV, network byte order */ 885 /* XXX may read fewer than requested */ 886 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 887 888 /* Go ahead and compute key in ubsec's byte order */ 889 if (encini->cri_alg == CRYPTO_DES_CBC) { 890 bcopy(encini->cri_key, &ses->ses_deskey[0], 8); 891 bcopy(encini->cri_key, &ses->ses_deskey[2], 8); 892 bcopy(encini->cri_key, &ses->ses_deskey[4], 8); 893 } else 894 bcopy(encini->cri_key, ses->ses_deskey, 24); 895 896 SWAP32(ses->ses_deskey[0]); 897 SWAP32(ses->ses_deskey[1]); 898 SWAP32(ses->ses_deskey[2]); 899 SWAP32(ses->ses_deskey[3]); 900 SWAP32(ses->ses_deskey[4]); 901 SWAP32(ses->ses_deskey[5]); 902 } 903 904 if (macini) { 905 for (i = 0; i < macini->cri_klen / 8; i++) 906 macini->cri_key[i] ^= HMAC_IPAD_VAL; 907 908 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 909 MD5Init(&md5ctx); 910 MD5Update(&md5ctx, macini->cri_key, 911 macini->cri_klen / 8); 912 MD5Update(&md5ctx, hmac_ipad_buffer, 913 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 914 bcopy(md5ctx.state, ses->ses_hminner, 915 sizeof(md5ctx.state)); 916 } else { 917 SHA1Init(&sha1ctx); 918 SHA1Update(&sha1ctx, macini->cri_key, 919 macini->cri_klen / 8); 920 SHA1Update(&sha1ctx, hmac_ipad_buffer, 921 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 922 bcopy(sha1ctx.h.b32, ses->ses_hminner, 923 sizeof(sha1ctx.h.b32)); 924 } 925 926 for (i = 0; i < macini->cri_klen / 8; i++) 927 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 928 929 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 930 MD5Init(&md5ctx); 931 MD5Update(&md5ctx, macini->cri_key, 932 macini->cri_klen / 8); 933 MD5Update(&md5ctx, hmac_opad_buffer, 934 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 935 bcopy(md5ctx.state, ses->ses_hmouter, 936 sizeof(md5ctx.state)); 937 } else { 938 SHA1Init(&sha1ctx); 939 SHA1Update(&sha1ctx, macini->cri_key, 940 macini->cri_klen / 8); 941 SHA1Update(&sha1ctx, hmac_opad_buffer, 942 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 943 bcopy(sha1ctx.h.b32, ses->ses_hmouter, 944 sizeof(sha1ctx.h.b32)); 945 } 946 947 for (i = 0; i < macini->cri_klen / 8; i++) 948 macini->cri_key[i] ^= HMAC_OPAD_VAL; 949 } 950 951 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); 952 return (0); 953} 954 955/* 956 * Deallocate a session. 957 */ 958static int 959ubsec_freesession(void *arg, u_int64_t tid) 960{ 961 struct ubsec_softc *sc = arg; 962 int session; 963 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 964 965 KASSERT(sc != NULL, ("ubsec_freesession: null softc")); 966 if (sc == NULL) 967 return (EINVAL); 968 969 session = UBSEC_SESSION(sid); 970 if (session >= sc->sc_nsessions) 971 return (EINVAL); 972 973 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 974 return (0); 975} 976 977static void 978ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 979{ 980 struct ubsec_operand *op = arg; 981 982 KASSERT(nsegs <= UBS_MAX_SCATTER, 983 ("Too many DMA segments returned when mapping operand")); 984#ifdef UBSEC_DEBUG 985 if (ubsec_debug) 986 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 987 (u_int) mapsize, nsegs); 988#endif 989 op->mapsize = mapsize; 990 op->nsegs = nsegs; 991 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 992} 993 994static int 995ubsec_process(void *arg, struct cryptop *crp, int hint) 996{ 997 struct ubsec_q *q = NULL; 998 int err = 0, i, j, nicealign; 999 struct ubsec_softc *sc = arg; 1000 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1001 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1002 int sskip, dskip, stheend, dtheend; 1003 int16_t coffset; 1004 struct ubsec_session *ses; 1005 struct ubsec_pktctx ctx; 1006 struct ubsec_dma *dmap = NULL; 1007 1008 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1009 ubsecstats.hst_invalid++; 1010 return (EINVAL); 1011 } 1012 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1013 ubsecstats.hst_badsession++; 1014 return (EINVAL); 1015 } 1016 1017 UBSEC_LOCK(sc); 1018 1019 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1020 ubsecstats.hst_queuefull++; 1021 sc->sc_needwakeup |= CRYPTO_SYMQ; 1022 UBSEC_UNLOCK(sc); 1023 return (ERESTART); 1024 } 1025 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1026 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 1027 UBSEC_UNLOCK(sc); 1028 1029 dmap = q->q_dma; /* Save dma pointer */ 1030 bzero(q, sizeof(struct ubsec_q)); 1031 bzero(&ctx, sizeof(ctx)); 1032 1033 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1034 q->q_dma = dmap; 1035 ses = &sc->sc_sessions[q->q_sesn]; 1036 1037 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1038 q->q_src_m = (struct mbuf *)crp->crp_buf; 1039 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1040 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1041 q->q_src_io = (struct uio *)crp->crp_buf; 1042 q->q_dst_io = (struct uio *)crp->crp_buf; 1043 } else { 1044 ubsecstats.hst_badflags++; 1045 err = EINVAL; 1046 goto errout; /* XXX we don't handle contiguous blocks! */ 1047 } 1048 1049 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 1050 1051 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1052 dmap->d_dma->d_mcr.mcr_flags = 0; 1053 q->q_crp = crp; 1054 1055 crd1 = crp->crp_desc; 1056 if (crd1 == NULL) { 1057 ubsecstats.hst_nodesc++; 1058 err = EINVAL; 1059 goto errout; 1060 } 1061 crd2 = crd1->crd_next; 1062 1063 if (crd2 == NULL) { 1064 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 1065 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 1066 maccrd = crd1; 1067 enccrd = NULL; 1068 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1069 crd1->crd_alg == CRYPTO_3DES_CBC) { 1070 maccrd = NULL; 1071 enccrd = crd1; 1072 } else { 1073 ubsecstats.hst_badalg++; 1074 err = EINVAL; 1075 goto errout; 1076 } 1077 } else { 1078 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1079 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1080 (crd2->crd_alg == CRYPTO_DES_CBC || 1081 crd2->crd_alg == CRYPTO_3DES_CBC) && 1082 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1083 maccrd = crd1; 1084 enccrd = crd2; 1085 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1086 crd1->crd_alg == CRYPTO_3DES_CBC) && 1087 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1088 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1089 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1090 enccrd = crd1; 1091 maccrd = crd2; 1092 } else { 1093 /* 1094 * We cannot order the ubsec as requested 1095 */ 1096 ubsecstats.hst_badalg++; 1097 err = EINVAL; 1098 goto errout; 1099 } 1100 } 1101 1102 if (enccrd) { 1103 encoffset = enccrd->crd_skip; 1104 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1105 1106 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1107 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1108 1109 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1110 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1111 else { 1112 ctx.pc_iv[0] = ses->ses_iv[0]; 1113 ctx.pc_iv[1] = ses->ses_iv[1]; 1114 } 1115 1116 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1117 if (crp->crp_flags & CRYPTO_F_IMBUF) 1118 m_copyback(q->q_src_m, 1119 enccrd->crd_inject, 1120 8, (caddr_t)ctx.pc_iv); 1121 else if (crp->crp_flags & CRYPTO_F_IOV) 1122 cuio_copyback(q->q_src_io, 1123 enccrd->crd_inject, 1124 8, (caddr_t)ctx.pc_iv); 1125 } 1126 } else { 1127 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1128 1129 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1130 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1131 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1132 m_copydata(q->q_src_m, enccrd->crd_inject, 1133 8, (caddr_t)ctx.pc_iv); 1134 else if (crp->crp_flags & CRYPTO_F_IOV) 1135 cuio_copydata(q->q_src_io, 1136 enccrd->crd_inject, 8, 1137 (caddr_t)ctx.pc_iv); 1138 } 1139 1140 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1141 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1142 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1143 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1144 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1145 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1146 SWAP32(ctx.pc_iv[0]); 1147 SWAP32(ctx.pc_iv[1]); 1148 } 1149 1150 if (maccrd) { 1151 macoffset = maccrd->crd_skip; 1152 1153 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1154 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1155 else 1156 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1157 1158 for (i = 0; i < 5; i++) { 1159 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1160 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1161 1162 HTOLE32(ctx.pc_hminner[i]); 1163 HTOLE32(ctx.pc_hmouter[i]); 1164 } 1165 } 1166 1167 if (enccrd && maccrd) { 1168 /* 1169 * ubsec cannot handle packets where the end of encryption 1170 * and authentication are not the same, or where the 1171 * encrypted part begins before the authenticated part. 1172 */ 1173 if ((encoffset + enccrd->crd_len) != 1174 (macoffset + maccrd->crd_len)) { 1175 ubsecstats.hst_lenmismatch++; 1176 err = EINVAL; 1177 goto errout; 1178 } 1179 if (enccrd->crd_skip < maccrd->crd_skip) { 1180 ubsecstats.hst_skipmismatch++; 1181 err = EINVAL; 1182 goto errout; 1183 } 1184 sskip = maccrd->crd_skip; 1185 cpskip = dskip = enccrd->crd_skip; 1186 stheend = maccrd->crd_len; 1187 dtheend = enccrd->crd_len; 1188 coffset = enccrd->crd_skip - maccrd->crd_skip; 1189 cpoffset = cpskip + dtheend; 1190#ifdef UBSEC_DEBUG 1191 if (ubsec_debug) { 1192 printf("mac: skip %d, len %d, inject %d\n", 1193 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1194 printf("enc: skip %d, len %d, inject %d\n", 1195 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1196 printf("src: skip %d, len %d\n", sskip, stheend); 1197 printf("dst: skip %d, len %d\n", dskip, dtheend); 1198 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1199 coffset, stheend, cpskip, cpoffset); 1200 } 1201#endif 1202 } else { 1203 cpskip = dskip = sskip = macoffset + encoffset; 1204 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1205 cpoffset = cpskip + dtheend; 1206 coffset = 0; 1207 } 1208 ctx.pc_offset = htole16(coffset >> 2); 1209 1210 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) { 1211 ubsecstats.hst_nomap++; 1212 err = ENOMEM; 1213 goto errout; 1214 } 1215 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1216 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1217 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1218 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1219 q->q_src_map = NULL; 1220 ubsecstats.hst_noload++; 1221 err = ENOMEM; 1222 goto errout; 1223 } 1224 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1225 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1226 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1227 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1228 q->q_src_map = NULL; 1229 ubsecstats.hst_noload++; 1230 err = ENOMEM; 1231 goto errout; 1232 } 1233 } 1234 nicealign = ubsec_dmamap_aligned(&q->q_src); 1235 1236 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1237 1238#ifdef UBSEC_DEBUG 1239 if (ubsec_debug) 1240 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1241#endif 1242 for (i = j = 0; i < q->q_src_nsegs; i++) { 1243 struct ubsec_pktbuf *pb; 1244 bus_size_t packl = q->q_src_segs[i].ds_len; 1245 bus_addr_t packp = q->q_src_segs[i].ds_addr; 1246 1247 if (sskip >= packl) { 1248 sskip -= packl; 1249 continue; 1250 } 1251 1252 packl -= sskip; 1253 packp += sskip; 1254 sskip = 0; 1255 1256 if (packl > 0xfffc) { 1257 err = EIO; 1258 goto errout; 1259 } 1260 1261 if (j == 0) 1262 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1263 else 1264 pb = &dmap->d_dma->d_sbuf[j - 1]; 1265 1266 pb->pb_addr = htole32(packp); 1267 1268 if (stheend) { 1269 if (packl > stheend) { 1270 pb->pb_len = htole32(stheend); 1271 stheend = 0; 1272 } else { 1273 pb->pb_len = htole32(packl); 1274 stheend -= packl; 1275 } 1276 } else 1277 pb->pb_len = htole32(packl); 1278 1279 if ((i + 1) == q->q_src_nsegs) 1280 pb->pb_next = 0; 1281 else 1282 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1283 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1284 j++; 1285 } 1286 1287 if (enccrd == NULL && maccrd != NULL) { 1288 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1289 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1290 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1291 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1292#ifdef UBSEC_DEBUG 1293 if (ubsec_debug) 1294 printf("opkt: %x %x %x\n", 1295 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1296 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1297 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1298#endif 1299 } else { 1300 if (crp->crp_flags & CRYPTO_F_IOV) { 1301 if (!nicealign) { 1302 ubsecstats.hst_iovmisaligned++; 1303 err = EINVAL; 1304 goto errout; 1305 } 1306 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1307 &q->q_dst_map)) { 1308 ubsecstats.hst_nomap++; 1309 err = ENOMEM; 1310 goto errout; 1311 } 1312 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1313 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) { 1314 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1315 q->q_dst_map = NULL; 1316 ubsecstats.hst_noload++; 1317 err = ENOMEM; 1318 goto errout; 1319 } 1320 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1321 if (nicealign) { 1322 q->q_dst = q->q_src; 1323 } else { 1324 int totlen, len; 1325 struct mbuf *m, *top, **mp; 1326 1327 ubsecstats.hst_unaligned++; 1328 totlen = q->q_src_mapsize; 1329 if (q->q_src_m->m_flags & M_PKTHDR) { 1330 len = MHLEN; 1331 MGETHDR(m, M_NOWAIT, MT_DATA); 1332 if (m && !m_dup_pkthdr(m, q->q_src_m, M_NOWAIT)) { 1333 m_free(m); 1334 m = NULL; 1335 } 1336 } else { 1337 len = MLEN; 1338 MGET(m, M_NOWAIT, MT_DATA); 1339 } 1340 if (m == NULL) { 1341 ubsecstats.hst_nombuf++; 1342 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1343 goto errout; 1344 } 1345 if (totlen >= MINCLSIZE) { 1346 MCLGET(m, M_NOWAIT); 1347 if ((m->m_flags & M_EXT) == 0) { 1348 m_free(m); 1349 ubsecstats.hst_nomcl++; 1350 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1351 goto errout; 1352 } 1353 len = MCLBYTES; 1354 } 1355 m->m_len = len; 1356 top = NULL; 1357 mp = ⊤ 1358 1359 while (totlen > 0) { 1360 if (top) { 1361 MGET(m, M_NOWAIT, MT_DATA); 1362 if (m == NULL) { 1363 m_freem(top); 1364 ubsecstats.hst_nombuf++; 1365 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1366 goto errout; 1367 } 1368 len = MLEN; 1369 } 1370 if (top && totlen >= MINCLSIZE) { 1371 MCLGET(m, M_NOWAIT); 1372 if ((m->m_flags & M_EXT) == 0) { 1373 *mp = m; 1374 m_freem(top); 1375 ubsecstats.hst_nomcl++; 1376 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1377 goto errout; 1378 } 1379 len = MCLBYTES; 1380 } 1381 m->m_len = len = min(totlen, len); 1382 totlen -= len; 1383 *mp = m; 1384 mp = &m->m_next; 1385 } 1386 q->q_dst_m = top; 1387 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1388 cpskip, cpoffset); 1389 if (bus_dmamap_create(sc->sc_dmat, 1390 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) { 1391 ubsecstats.hst_nomap++; 1392 err = ENOMEM; 1393 goto errout; 1394 } 1395 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1396 q->q_dst_map, q->q_dst_m, 1397 ubsec_op_cb, &q->q_dst, 1398 BUS_DMA_NOWAIT) != 0) { 1399 bus_dmamap_destroy(sc->sc_dmat, 1400 q->q_dst_map); 1401 q->q_dst_map = NULL; 1402 ubsecstats.hst_noload++; 1403 err = ENOMEM; 1404 goto errout; 1405 } 1406 } 1407 } else { 1408 ubsecstats.hst_badflags++; 1409 err = EINVAL; 1410 goto errout; 1411 } 1412 1413#ifdef UBSEC_DEBUG 1414 if (ubsec_debug) 1415 printf("dst skip: %d\n", dskip); 1416#endif 1417 for (i = j = 0; i < q->q_dst_nsegs; i++) { 1418 struct ubsec_pktbuf *pb; 1419 bus_size_t packl = q->q_dst_segs[i].ds_len; 1420 bus_addr_t packp = q->q_dst_segs[i].ds_addr; 1421 1422 if (dskip >= packl) { 1423 dskip -= packl; 1424 continue; 1425 } 1426 1427 packl -= dskip; 1428 packp += dskip; 1429 dskip = 0; 1430 1431 if (packl > 0xfffc) { 1432 err = EIO; 1433 goto errout; 1434 } 1435 1436 if (j == 0) 1437 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1438 else 1439 pb = &dmap->d_dma->d_dbuf[j - 1]; 1440 1441 pb->pb_addr = htole32(packp); 1442 1443 if (dtheend) { 1444 if (packl > dtheend) { 1445 pb->pb_len = htole32(dtheend); 1446 dtheend = 0; 1447 } else { 1448 pb->pb_len = htole32(packl); 1449 dtheend -= packl; 1450 } 1451 } else 1452 pb->pb_len = htole32(packl); 1453 1454 if ((i + 1) == q->q_dst_nsegs) { 1455 if (maccrd) 1456 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1457 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1458 else 1459 pb->pb_next = 0; 1460 } else 1461 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1462 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1463 j++; 1464 } 1465 } 1466 1467 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1468 offsetof(struct ubsec_dmachunk, d_ctx)); 1469 1470 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1471 struct ubsec_pktctx_long *ctxl; 1472 1473 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr + 1474 offsetof(struct ubsec_dmachunk, d_ctx)); 1475 1476 /* transform small context into long context */ 1477 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1478 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1479 ctxl->pc_flags = ctx.pc_flags; 1480 ctxl->pc_offset = ctx.pc_offset; 1481 for (i = 0; i < 6; i++) 1482 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1483 for (i = 0; i < 5; i++) 1484 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1485 for (i = 0; i < 5; i++) 1486 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1487 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1488 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1489 } else 1490 bcopy(&ctx, dmap->d_alloc.dma_vaddr + 1491 offsetof(struct ubsec_dmachunk, d_ctx), 1492 sizeof(struct ubsec_pktctx)); 1493 1494 UBSEC_LOCK(sc); 1495 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1496 sc->sc_nqueue++; 1497 ubsecstats.hst_ipackets++; 1498 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size; 1499 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= ubsec_maxbatch) 1500 ubsec_feed(sc); 1501 UBSEC_UNLOCK(sc); 1502 return (0); 1503 1504errout: 1505 if (q != NULL) { 1506 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1507 m_freem(q->q_dst_m); 1508 1509 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1510 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1511 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1512 } 1513 if (q->q_src_map != NULL) { 1514 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1515 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1516 } 1517 1518 UBSEC_LOCK(sc); 1519 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1520 UBSEC_UNLOCK(sc); 1521 } 1522 if (err != ERESTART) { 1523 crp->crp_etype = err; 1524 crypto_done(crp); 1525 } else { 1526 sc->sc_needwakeup |= CRYPTO_SYMQ; 1527 } 1528 return (err); 1529} 1530 1531static void 1532ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1533{ 1534 struct cryptop *crp = (struct cryptop *)q->q_crp; 1535 struct cryptodesc *crd; 1536 struct ubsec_dma *dmap = q->q_dma; 1537 1538 ubsec_dma_sync(&dmap->d_alloc, 1539 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1540 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1541 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1542 BUS_DMASYNC_POSTREAD); 1543 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1544 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1545 } 1546 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE); 1547 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1548 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1549 1550 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1551 m_freem(q->q_src_m); 1552 crp->crp_buf = (caddr_t)q->q_dst_m; 1553 } 1554 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len; 1555 1556 /* copy out IV for future use */ 1557 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1558 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1559 if (crd->crd_alg != CRYPTO_DES_CBC && 1560 crd->crd_alg != CRYPTO_3DES_CBC) 1561 continue; 1562 if (crp->crp_flags & CRYPTO_F_IMBUF) 1563 m_copydata((struct mbuf *)crp->crp_buf, 1564 crd->crd_skip + crd->crd_len - 8, 8, 1565 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1566 else if (crp->crp_flags & CRYPTO_F_IOV) { 1567 cuio_copydata((struct uio *)crp->crp_buf, 1568 crd->crd_skip + crd->crd_len - 8, 8, 1569 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1570 } 1571 break; 1572 } 1573 } 1574 1575 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1576 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1577 crd->crd_alg != CRYPTO_SHA1_HMAC) 1578 continue; 1579 if (crp->crp_flags & CRYPTO_F_IMBUF) 1580 m_copyback((struct mbuf *)crp->crp_buf, 1581 crd->crd_inject, 12, 1582 (caddr_t)dmap->d_dma->d_macbuf); 1583 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1584 bcopy((caddr_t)dmap->d_dma->d_macbuf, 1585 crp->crp_mac, 12); 1586 break; 1587 } 1588 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1589 crypto_done(crp); 1590} 1591 1592static void 1593ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1594{ 1595 int i, j, dlen, slen; 1596 caddr_t dptr, sptr; 1597 1598 j = 0; 1599 sptr = srcm->m_data; 1600 slen = srcm->m_len; 1601 dptr = dstm->m_data; 1602 dlen = dstm->m_len; 1603 1604 while (1) { 1605 for (i = 0; i < min(slen, dlen); i++) { 1606 if (j < hoffset || j >= toffset) 1607 *dptr++ = *sptr++; 1608 slen--; 1609 dlen--; 1610 j++; 1611 } 1612 if (slen == 0) { 1613 srcm = srcm->m_next; 1614 if (srcm == NULL) 1615 return; 1616 sptr = srcm->m_data; 1617 slen = srcm->m_len; 1618 } 1619 if (dlen == 0) { 1620 dstm = dstm->m_next; 1621 if (dstm == NULL) 1622 return; 1623 dptr = dstm->m_data; 1624 dlen = dstm->m_len; 1625 } 1626 } 1627} 1628 1629/* 1630 * feed the key generator, must be called at splimp() or higher. 1631 */ 1632static int 1633ubsec_feed2(struct ubsec_softc *sc) 1634{ 1635 struct ubsec_q2 *q; 1636 1637 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1638 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1639 break; 1640 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1641 1642 ubsec_dma_sync(&q->q_mcr, 1643 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1644 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE); 1645 1646 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1647 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next); 1648 --sc->sc_nqueue2; 1649 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1650 } 1651 return (0); 1652} 1653 1654/* 1655 * Callback for handling random numbers 1656 */ 1657static void 1658ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1659{ 1660 struct cryptkop *krp; 1661 struct ubsec_ctx_keyop *ctx; 1662 1663 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1664 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE); 1665 1666 switch (q->q_type) { 1667#ifndef UBSEC_NO_RNG 1668 case UBS_CTXOP_RNGBYPASS: { 1669 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1670 1671 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD); 1672 random_harvest(rng->rng_buf.dma_vaddr, 1673 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t), 1674 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t)*NBBY, 0, 1675 RANDOM_PURE); 1676 rng->rng_used = 0; 1677 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1678 break; 1679 } 1680#endif 1681 case UBS_CTXOP_MODEXP: { 1682 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1683 u_int rlen, clen; 1684 1685 krp = me->me_krp; 1686 rlen = (me->me_modbits + 7) / 8; 1687 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1688 1689 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE); 1690 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE); 1691 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD); 1692 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE); 1693 1694 if (clen < rlen) 1695 krp->krp_status = E2BIG; 1696 else { 1697 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1698 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1699 (krp->krp_param[krp->krp_iparams].crp_nbits 1700 + 7) / 8); 1701 bcopy(me->me_C.dma_vaddr, 1702 krp->krp_param[krp->krp_iparams].crp_p, 1703 (me->me_modbits + 7) / 8); 1704 } else 1705 ubsec_kshift_l(me->me_shiftbits, 1706 me->me_C.dma_vaddr, me->me_normbits, 1707 krp->krp_param[krp->krp_iparams].crp_p, 1708 krp->krp_param[krp->krp_iparams].crp_nbits); 1709 } 1710 1711 crypto_kdone(krp); 1712 1713 /* bzero all potentially sensitive data */ 1714 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1715 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1716 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1717 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1718 1719 /* Can't free here, so put us on the free list. */ 1720 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1721 break; 1722 } 1723 case UBS_CTXOP_RSAPRIV: { 1724 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1725 u_int len; 1726 1727 krp = rp->rpr_krp; 1728 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE); 1729 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD); 1730 1731 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1732 bcopy(rp->rpr_msgout.dma_vaddr, 1733 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1734 1735 crypto_kdone(krp); 1736 1737 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1738 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1739 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1740 1741 /* Can't free here, so put us on the free list. */ 1742 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1743 break; 1744 } 1745 default: 1746 device_printf(sc->sc_dev, "unknown ctx op: %x\n", 1747 letoh16(ctx->ctx_op)); 1748 break; 1749 } 1750} 1751 1752#ifndef UBSEC_NO_RNG 1753static void 1754ubsec_rng(void *vsc) 1755{ 1756 struct ubsec_softc *sc = vsc; 1757 struct ubsec_q2_rng *rng = &sc->sc_rng; 1758 struct ubsec_mcr *mcr; 1759 struct ubsec_ctx_rngbypass *ctx; 1760 1761 UBSEC_LOCK(sc); 1762 if (rng->rng_used) { 1763 UBSEC_UNLOCK(sc); 1764 return; 1765 } 1766 sc->sc_nqueue2++; 1767 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1768 goto out; 1769 1770 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1771 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1772 1773 mcr->mcr_pkts = htole16(1); 1774 mcr->mcr_flags = 0; 1775 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1776 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1777 mcr->mcr_ipktbuf.pb_len = 0; 1778 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1779 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1780 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1781 UBS_PKTBUF_LEN); 1782 mcr->mcr_opktbuf.pb_next = 0; 1783 1784 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1785 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS); 1786 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS; 1787 1788 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD); 1789 1790 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1791 rng->rng_used = 1; 1792 ubsec_feed2(sc); 1793 ubsecstats.hst_rng++; 1794 UBSEC_UNLOCK(sc); 1795 1796 return; 1797 1798out: 1799 /* 1800 * Something weird happened, generate our own call back. 1801 */ 1802 sc->sc_nqueue2--; 1803 UBSEC_UNLOCK(sc); 1804 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1805} 1806#endif /* UBSEC_NO_RNG */ 1807 1808static void 1809ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1810{ 1811 bus_addr_t *paddr = (bus_addr_t*) arg; 1812 *paddr = segs->ds_addr; 1813} 1814 1815static int 1816ubsec_dma_malloc( 1817 struct ubsec_softc *sc, 1818 bus_size_t size, 1819 struct ubsec_dma_alloc *dma, 1820 int mapflags 1821) 1822{ 1823 int r; 1824 1825 /* XXX could specify sc_dmat as parent but that just adds overhead */ 1826 r = bus_dma_tag_create(NULL, /* parent */ 1827 1, 0, /* alignment, bounds */ 1828 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1829 BUS_SPACE_MAXADDR, /* highaddr */ 1830 NULL, NULL, /* filter, filterarg */ 1831 size, /* maxsize */ 1832 1, /* nsegments */ 1833 size, /* maxsegsize */ 1834 BUS_DMA_ALLOCNOW, /* flags */ 1835 &dma->dma_tag); 1836 if (r != 0) { 1837 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1838 "bus_dma_tag_create failed; error %u\n", r); 1839 goto fail_0; 1840 } 1841 1842 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1843 if (r != 0) { 1844 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1845 "bus_dmamap_create failed; error %u\n", r); 1846 goto fail_1; 1847 } 1848 1849 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1850 BUS_DMA_NOWAIT, &dma->dma_map); 1851 if (r != 0) { 1852 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1853 "bus_dmammem_alloc failed; size %zu, error %u\n", 1854 size, r); 1855 goto fail_2; 1856 } 1857 1858 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1859 size, 1860 ubsec_dmamap_cb, 1861 &dma->dma_paddr, 1862 mapflags | BUS_DMA_NOWAIT); 1863 if (r != 0) { 1864 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1865 "bus_dmamap_load failed; error %u\n", r); 1866 goto fail_3; 1867 } 1868 1869 dma->dma_size = size; 1870 return (0); 1871 1872fail_3: 1873 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1874fail_2: 1875 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1876fail_1: 1877 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1878 bus_dma_tag_destroy(dma->dma_tag); 1879fail_0: 1880 dma->dma_map = NULL; 1881 dma->dma_tag = NULL; 1882 return (r); 1883} 1884 1885static void 1886ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1887{ 1888 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1889 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1890 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1891 bus_dma_tag_destroy(dma->dma_tag); 1892} 1893 1894/* 1895 * Resets the board. Values in the regesters are left as is 1896 * from the reset (i.e. initial values are assigned elsewhere). 1897 */ 1898static void 1899ubsec_reset_board(struct ubsec_softc *sc) 1900{ 1901 volatile u_int32_t ctrl; 1902 1903 ctrl = READ_REG(sc, BS_CTRL); 1904 ctrl |= BS_CTRL_RESET; 1905 WRITE_REG(sc, BS_CTRL, ctrl); 1906 1907 /* 1908 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1909 */ 1910 DELAY(10); 1911} 1912 1913/* 1914 * Init Broadcom registers 1915 */ 1916static void 1917ubsec_init_board(struct ubsec_softc *sc) 1918{ 1919 u_int32_t ctrl; 1920 1921 ctrl = READ_REG(sc, BS_CTRL); 1922 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1923 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1924 1925 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) 1926 ctrl |= BS_CTRL_MCR2INT; 1927 else 1928 ctrl &= ~BS_CTRL_MCR2INT; 1929 1930 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1931 ctrl &= ~BS_CTRL_SWNORM; 1932 1933 WRITE_REG(sc, BS_CTRL, ctrl); 1934} 1935 1936/* 1937 * Init Broadcom PCI registers 1938 */ 1939static void 1940ubsec_init_pciregs(device_t dev) 1941{ 1942#if 0 1943 u_int32_t misc; 1944 1945 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT); 1946 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT)) 1947 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT); 1948 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT)) 1949 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT); 1950 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc); 1951#endif 1952 1953 /* 1954 * This will set the cache line size to 1, this will 1955 * force the BCM58xx chip just to do burst read/writes. 1956 * Cache line read/writes are to slow 1957 */ 1958 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1); 1959} 1960 1961/* 1962 * Clean up after a chip crash. 1963 * It is assumed that the caller in splimp() 1964 */ 1965static void 1966ubsec_cleanchip(struct ubsec_softc *sc) 1967{ 1968 struct ubsec_q *q; 1969 1970 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 1971 q = SIMPLEQ_FIRST(&sc->sc_qchip); 1972 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 1973 ubsec_free_q(sc, q); 1974 } 1975 sc->sc_nqchip = 0; 1976} 1977 1978/* 1979 * free a ubsec_q 1980 * It is assumed that the caller is within splimp(). 1981 */ 1982static int 1983ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 1984{ 1985 struct ubsec_q *q2; 1986 struct cryptop *crp; 1987 int npkts; 1988 int i; 1989 1990 npkts = q->q_nstacked_mcrs; 1991 1992 for (i = 0; i < npkts; i++) { 1993 if(q->q_stacked_mcr[i]) { 1994 q2 = q->q_stacked_mcr[i]; 1995 1996 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 1997 m_freem(q2->q_dst_m); 1998 1999 crp = (struct cryptop *)q2->q_crp; 2000 2001 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2002 2003 crp->crp_etype = EFAULT; 2004 crypto_done(crp); 2005 } else { 2006 break; 2007 } 2008 } 2009 2010 /* 2011 * Free header MCR 2012 */ 2013 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2014 m_freem(q->q_dst_m); 2015 2016 crp = (struct cryptop *)q->q_crp; 2017 2018 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2019 2020 crp->crp_etype = EFAULT; 2021 crypto_done(crp); 2022 return(0); 2023} 2024 2025/* 2026 * Routine to reset the chip and clean up. 2027 * It is assumed that the caller is in splimp() 2028 */ 2029static void 2030ubsec_totalreset(struct ubsec_softc *sc) 2031{ 2032 ubsec_reset_board(sc); 2033 ubsec_init_board(sc); 2034 ubsec_cleanchip(sc); 2035} 2036 2037static int 2038ubsec_dmamap_aligned(struct ubsec_operand *op) 2039{ 2040 int i; 2041 2042 for (i = 0; i < op->nsegs; i++) { 2043 if (op->segs[i].ds_addr & 3) 2044 return (0); 2045 if ((i != (op->nsegs - 1)) && 2046 (op->segs[i].ds_len & 3)) 2047 return (0); 2048 } 2049 return (1); 2050} 2051 2052static void 2053ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2054{ 2055 switch (q->q_type) { 2056 case UBS_CTXOP_MODEXP: { 2057 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2058 2059 ubsec_dma_free(sc, &me->me_q.q_mcr); 2060 ubsec_dma_free(sc, &me->me_q.q_ctx); 2061 ubsec_dma_free(sc, &me->me_M); 2062 ubsec_dma_free(sc, &me->me_E); 2063 ubsec_dma_free(sc, &me->me_C); 2064 ubsec_dma_free(sc, &me->me_epb); 2065 free(me, M_DEVBUF); 2066 break; 2067 } 2068 case UBS_CTXOP_RSAPRIV: { 2069 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2070 2071 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2072 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2073 ubsec_dma_free(sc, &rp->rpr_msgin); 2074 ubsec_dma_free(sc, &rp->rpr_msgout); 2075 free(rp, M_DEVBUF); 2076 break; 2077 } 2078 default: 2079 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type); 2080 break; 2081 } 2082} 2083 2084static int 2085ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2086{ 2087 struct ubsec_softc *sc = arg; 2088 int r; 2089 2090 if (krp == NULL || krp->krp_callback == NULL) 2091 return (EINVAL); 2092 2093 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2094 struct ubsec_q2 *q; 2095 2096 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2097 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next); 2098 ubsec_kfree(sc, q); 2099 } 2100 2101 switch (krp->krp_op) { 2102 case CRK_MOD_EXP: 2103 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2104 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2105 else 2106 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2107 break; 2108 case CRK_MOD_EXP_CRT: 2109 return (ubsec_kprocess_rsapriv(sc, krp, hint)); 2110 default: 2111 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n", 2112 krp->krp_op); 2113 krp->krp_status = EOPNOTSUPP; 2114 crypto_kdone(krp); 2115 return (0); 2116 } 2117 return (0); /* silence compiler */ 2118} 2119 2120/* 2121 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2122 */ 2123static int 2124ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2125{ 2126 struct ubsec_q2_modexp *me; 2127 struct ubsec_mcr *mcr; 2128 struct ubsec_ctx_modexp *ctx; 2129 struct ubsec_pktbuf *epb; 2130 int err = 0; 2131 u_int nbits, normbits, mbits, shiftbits, ebits; 2132 2133 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2134 if (me == NULL) { 2135 err = ENOMEM; 2136 goto errout; 2137 } 2138 bzero(me, sizeof *me); 2139 me->me_krp = krp; 2140 me->me_q.q_type = UBS_CTXOP_MODEXP; 2141 2142 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2143 if (nbits <= 512) 2144 normbits = 512; 2145 else if (nbits <= 768) 2146 normbits = 768; 2147 else if (nbits <= 1024) 2148 normbits = 1024; 2149 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2150 normbits = 1536; 2151 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2152 normbits = 2048; 2153 else { 2154 err = E2BIG; 2155 goto errout; 2156 } 2157 2158 shiftbits = normbits - nbits; 2159 2160 me->me_modbits = nbits; 2161 me->me_shiftbits = shiftbits; 2162 me->me_normbits = normbits; 2163 2164 /* Sanity check: result bits must be >= true modulus bits. */ 2165 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2166 err = ERANGE; 2167 goto errout; 2168 } 2169 2170 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2171 &me->me_q.q_mcr, 0)) { 2172 err = ENOMEM; 2173 goto errout; 2174 } 2175 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2176 2177 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2178 &me->me_q.q_ctx, 0)) { 2179 err = ENOMEM; 2180 goto errout; 2181 } 2182 2183 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2184 if (mbits > nbits) { 2185 err = E2BIG; 2186 goto errout; 2187 } 2188 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2189 err = ENOMEM; 2190 goto errout; 2191 } 2192 ubsec_kshift_r(shiftbits, 2193 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2194 me->me_M.dma_vaddr, normbits); 2195 2196 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2197 err = ENOMEM; 2198 goto errout; 2199 } 2200 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2201 2202 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2203 if (ebits > nbits) { 2204 err = E2BIG; 2205 goto errout; 2206 } 2207 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2208 err = ENOMEM; 2209 goto errout; 2210 } 2211 ubsec_kshift_r(shiftbits, 2212 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2213 me->me_E.dma_vaddr, normbits); 2214 2215 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2216 &me->me_epb, 0)) { 2217 err = ENOMEM; 2218 goto errout; 2219 } 2220 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2221 epb->pb_addr = htole32(me->me_E.dma_paddr); 2222 epb->pb_next = 0; 2223 epb->pb_len = htole32(normbits / 8); 2224 2225#ifdef UBSEC_DEBUG 2226 if (ubsec_debug) { 2227 printf("Epb "); 2228 ubsec_dump_pb(epb); 2229 } 2230#endif 2231 2232 mcr->mcr_pkts = htole16(1); 2233 mcr->mcr_flags = 0; 2234 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2235 mcr->mcr_reserved = 0; 2236 mcr->mcr_pktlen = 0; 2237 2238 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2239 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2240 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2241 2242 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2243 mcr->mcr_opktbuf.pb_next = 0; 2244 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2245 2246#ifdef DIAGNOSTIC 2247 /* Misaligned output buffer will hang the chip. */ 2248 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2249 panic("%s: modexp invalid addr 0x%x\n", 2250 device_get_nameunit(sc->sc_dev), 2251 letoh32(mcr->mcr_opktbuf.pb_addr)); 2252 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2253 panic("%s: modexp invalid len 0x%x\n", 2254 device_get_nameunit(sc->sc_dev), 2255 letoh32(mcr->mcr_opktbuf.pb_len)); 2256#endif 2257 2258 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2259 bzero(ctx, sizeof(*ctx)); 2260 ubsec_kshift_r(shiftbits, 2261 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2262 ctx->me_N, normbits); 2263 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2264 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2265 ctx->me_E_len = htole16(nbits); 2266 ctx->me_N_len = htole16(nbits); 2267 2268#ifdef UBSEC_DEBUG 2269 if (ubsec_debug) { 2270 ubsec_dump_mcr(mcr); 2271 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2272 } 2273#endif 2274 2275 /* 2276 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2277 * everything else. 2278 */ 2279 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2280 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2281 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2282 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2283 2284 /* Enqueue and we're done... */ 2285 UBSEC_LOCK(sc); 2286 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2287 ubsec_feed2(sc); 2288 ubsecstats.hst_modexp++; 2289 UBSEC_UNLOCK(sc); 2290 2291 return (0); 2292 2293errout: 2294 if (me != NULL) { 2295 if (me->me_q.q_mcr.dma_map != NULL) 2296 ubsec_dma_free(sc, &me->me_q.q_mcr); 2297 if (me->me_q.q_ctx.dma_map != NULL) { 2298 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2299 ubsec_dma_free(sc, &me->me_q.q_ctx); 2300 } 2301 if (me->me_M.dma_map != NULL) { 2302 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2303 ubsec_dma_free(sc, &me->me_M); 2304 } 2305 if (me->me_E.dma_map != NULL) { 2306 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2307 ubsec_dma_free(sc, &me->me_E); 2308 } 2309 if (me->me_C.dma_map != NULL) { 2310 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2311 ubsec_dma_free(sc, &me->me_C); 2312 } 2313 if (me->me_epb.dma_map != NULL) 2314 ubsec_dma_free(sc, &me->me_epb); 2315 free(me, M_DEVBUF); 2316 } 2317 krp->krp_status = err; 2318 crypto_kdone(krp); 2319 return (0); 2320} 2321 2322/* 2323 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2324 */ 2325static int 2326ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2327{ 2328 struct ubsec_q2_modexp *me; 2329 struct ubsec_mcr *mcr; 2330 struct ubsec_ctx_modexp *ctx; 2331 struct ubsec_pktbuf *epb; 2332 int err = 0; 2333 u_int nbits, normbits, mbits, shiftbits, ebits; 2334 2335 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2336 if (me == NULL) { 2337 err = ENOMEM; 2338 goto errout; 2339 } 2340 bzero(me, sizeof *me); 2341 me->me_krp = krp; 2342 me->me_q.q_type = UBS_CTXOP_MODEXP; 2343 2344 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2345 if (nbits <= 512) 2346 normbits = 512; 2347 else if (nbits <= 768) 2348 normbits = 768; 2349 else if (nbits <= 1024) 2350 normbits = 1024; 2351 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2352 normbits = 1536; 2353 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2354 normbits = 2048; 2355 else { 2356 err = E2BIG; 2357 goto errout; 2358 } 2359 2360 shiftbits = normbits - nbits; 2361 2362 /* XXX ??? */ 2363 me->me_modbits = nbits; 2364 me->me_shiftbits = shiftbits; 2365 me->me_normbits = normbits; 2366 2367 /* Sanity check: result bits must be >= true modulus bits. */ 2368 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2369 err = ERANGE; 2370 goto errout; 2371 } 2372 2373 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2374 &me->me_q.q_mcr, 0)) { 2375 err = ENOMEM; 2376 goto errout; 2377 } 2378 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2379 2380 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2381 &me->me_q.q_ctx, 0)) { 2382 err = ENOMEM; 2383 goto errout; 2384 } 2385 2386 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2387 if (mbits > nbits) { 2388 err = E2BIG; 2389 goto errout; 2390 } 2391 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2392 err = ENOMEM; 2393 goto errout; 2394 } 2395 bzero(me->me_M.dma_vaddr, normbits / 8); 2396 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2397 me->me_M.dma_vaddr, (mbits + 7) / 8); 2398 2399 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2400 err = ENOMEM; 2401 goto errout; 2402 } 2403 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2404 2405 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2406 if (ebits > nbits) { 2407 err = E2BIG; 2408 goto errout; 2409 } 2410 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2411 err = ENOMEM; 2412 goto errout; 2413 } 2414 bzero(me->me_E.dma_vaddr, normbits / 8); 2415 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2416 me->me_E.dma_vaddr, (ebits + 7) / 8); 2417 2418 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2419 &me->me_epb, 0)) { 2420 err = ENOMEM; 2421 goto errout; 2422 } 2423 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2424 epb->pb_addr = htole32(me->me_E.dma_paddr); 2425 epb->pb_next = 0; 2426 epb->pb_len = htole32((ebits + 7) / 8); 2427 2428#ifdef UBSEC_DEBUG 2429 if (ubsec_debug) { 2430 printf("Epb "); 2431 ubsec_dump_pb(epb); 2432 } 2433#endif 2434 2435 mcr->mcr_pkts = htole16(1); 2436 mcr->mcr_flags = 0; 2437 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2438 mcr->mcr_reserved = 0; 2439 mcr->mcr_pktlen = 0; 2440 2441 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2442 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2443 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2444 2445 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2446 mcr->mcr_opktbuf.pb_next = 0; 2447 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2448 2449#ifdef DIAGNOSTIC 2450 /* Misaligned output buffer will hang the chip. */ 2451 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2452 panic("%s: modexp invalid addr 0x%x\n", 2453 device_get_nameunit(sc->sc_dev), 2454 letoh32(mcr->mcr_opktbuf.pb_addr)); 2455 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2456 panic("%s: modexp invalid len 0x%x\n", 2457 device_get_nameunit(sc->sc_dev), 2458 letoh32(mcr->mcr_opktbuf.pb_len)); 2459#endif 2460 2461 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2462 bzero(ctx, sizeof(*ctx)); 2463 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2464 (nbits + 7) / 8); 2465 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2466 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2467 ctx->me_E_len = htole16(ebits); 2468 ctx->me_N_len = htole16(nbits); 2469 2470#ifdef UBSEC_DEBUG 2471 if (ubsec_debug) { 2472 ubsec_dump_mcr(mcr); 2473 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2474 } 2475#endif 2476 2477 /* 2478 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2479 * everything else. 2480 */ 2481 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2482 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2483 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2484 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2485 2486 /* Enqueue and we're done... */ 2487 UBSEC_LOCK(sc); 2488 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2489 ubsec_feed2(sc); 2490 UBSEC_UNLOCK(sc); 2491 2492 return (0); 2493 2494errout: 2495 if (me != NULL) { 2496 if (me->me_q.q_mcr.dma_map != NULL) 2497 ubsec_dma_free(sc, &me->me_q.q_mcr); 2498 if (me->me_q.q_ctx.dma_map != NULL) { 2499 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2500 ubsec_dma_free(sc, &me->me_q.q_ctx); 2501 } 2502 if (me->me_M.dma_map != NULL) { 2503 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2504 ubsec_dma_free(sc, &me->me_M); 2505 } 2506 if (me->me_E.dma_map != NULL) { 2507 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2508 ubsec_dma_free(sc, &me->me_E); 2509 } 2510 if (me->me_C.dma_map != NULL) { 2511 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2512 ubsec_dma_free(sc, &me->me_C); 2513 } 2514 if (me->me_epb.dma_map != NULL) 2515 ubsec_dma_free(sc, &me->me_epb); 2516 free(me, M_DEVBUF); 2517 } 2518 krp->krp_status = err; 2519 crypto_kdone(krp); 2520 return (0); 2521} 2522 2523static int 2524ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2525{ 2526 struct ubsec_q2_rsapriv *rp = NULL; 2527 struct ubsec_mcr *mcr; 2528 struct ubsec_ctx_rsapriv *ctx; 2529 int err = 0; 2530 u_int padlen, msglen; 2531 2532 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2533 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2534 if (msglen > padlen) 2535 padlen = msglen; 2536 2537 if (padlen <= 256) 2538 padlen = 256; 2539 else if (padlen <= 384) 2540 padlen = 384; 2541 else if (padlen <= 512) 2542 padlen = 512; 2543 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2544 padlen = 768; 2545 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2546 padlen = 1024; 2547 else { 2548 err = E2BIG; 2549 goto errout; 2550 } 2551 2552 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2553 err = E2BIG; 2554 goto errout; 2555 } 2556 2557 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2558 err = E2BIG; 2559 goto errout; 2560 } 2561 2562 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2563 err = E2BIG; 2564 goto errout; 2565 } 2566 2567 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT); 2568 if (rp == NULL) 2569 return (ENOMEM); 2570 bzero(rp, sizeof *rp); 2571 rp->rpr_krp = krp; 2572 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2573 2574 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2575 &rp->rpr_q.q_mcr, 0)) { 2576 err = ENOMEM; 2577 goto errout; 2578 } 2579 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2580 2581 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2582 &rp->rpr_q.q_ctx, 0)) { 2583 err = ENOMEM; 2584 goto errout; 2585 } 2586 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2587 bzero(ctx, sizeof *ctx); 2588 2589 /* Copy in p */ 2590 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2591 &ctx->rpr_buf[0 * (padlen / 8)], 2592 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2593 2594 /* Copy in q */ 2595 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2596 &ctx->rpr_buf[1 * (padlen / 8)], 2597 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2598 2599 /* Copy in dp */ 2600 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2601 &ctx->rpr_buf[2 * (padlen / 8)], 2602 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2603 2604 /* Copy in dq */ 2605 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2606 &ctx->rpr_buf[3 * (padlen / 8)], 2607 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2608 2609 /* Copy in pinv */ 2610 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2611 &ctx->rpr_buf[4 * (padlen / 8)], 2612 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2613 2614 msglen = padlen * 2; 2615 2616 /* Copy in input message (aligned buffer/length). */ 2617 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2618 /* Is this likely? */ 2619 err = E2BIG; 2620 goto errout; 2621 } 2622 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2623 err = ENOMEM; 2624 goto errout; 2625 } 2626 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2627 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2628 rp->rpr_msgin.dma_vaddr, 2629 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2630 2631 /* Prepare space for output message (aligned buffer/length). */ 2632 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2633 /* Is this likely? */ 2634 err = E2BIG; 2635 goto errout; 2636 } 2637 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2638 err = ENOMEM; 2639 goto errout; 2640 } 2641 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2642 2643 mcr->mcr_pkts = htole16(1); 2644 mcr->mcr_flags = 0; 2645 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2646 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2647 mcr->mcr_ipktbuf.pb_next = 0; 2648 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2649 mcr->mcr_reserved = 0; 2650 mcr->mcr_pktlen = htole16(msglen); 2651 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2652 mcr->mcr_opktbuf.pb_next = 0; 2653 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2654 2655#ifdef DIAGNOSTIC 2656 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2657 panic("%s: rsapriv: invalid msgin %x(0x%jx)", 2658 device_get_nameunit(sc->sc_dev), 2659 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size); 2660 } 2661 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2662 panic("%s: rsapriv: invalid msgout %x(0x%jx)", 2663 device_get_nameunit(sc->sc_dev), 2664 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size); 2665 } 2666#endif 2667 2668 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2669 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2670 ctx->rpr_q_len = htole16(padlen); 2671 ctx->rpr_p_len = htole16(padlen); 2672 2673 /* 2674 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2675 * everything else. 2676 */ 2677 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE); 2678 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD); 2679 2680 /* Enqueue and we're done... */ 2681 UBSEC_LOCK(sc); 2682 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2683 ubsec_feed2(sc); 2684 ubsecstats.hst_modexpcrt++; 2685 UBSEC_UNLOCK(sc); 2686 return (0); 2687 2688errout: 2689 if (rp != NULL) { 2690 if (rp->rpr_q.q_mcr.dma_map != NULL) 2691 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2692 if (rp->rpr_msgin.dma_map != NULL) { 2693 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2694 ubsec_dma_free(sc, &rp->rpr_msgin); 2695 } 2696 if (rp->rpr_msgout.dma_map != NULL) { 2697 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2698 ubsec_dma_free(sc, &rp->rpr_msgout); 2699 } 2700 free(rp, M_DEVBUF); 2701 } 2702 krp->krp_status = err; 2703 crypto_kdone(krp); 2704 return (0); 2705} 2706 2707#ifdef UBSEC_DEBUG 2708static void 2709ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2710{ 2711 printf("addr 0x%x (0x%x) next 0x%x\n", 2712 pb->pb_addr, pb->pb_len, pb->pb_next); 2713} 2714 2715static void 2716ubsec_dump_ctx2(struct ubsec_ctx_keyop *c) 2717{ 2718 printf("CTX (0x%x):\n", c->ctx_len); 2719 switch (letoh16(c->ctx_op)) { 2720 case UBS_CTXOP_RNGBYPASS: 2721 case UBS_CTXOP_RNGSHA1: 2722 break; 2723 case UBS_CTXOP_MODEXP: 2724 { 2725 struct ubsec_ctx_modexp *cx = (void *)c; 2726 int i, len; 2727 2728 printf(" Elen %u, Nlen %u\n", 2729 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2730 len = (cx->me_N_len + 7)/8; 2731 for (i = 0; i < len; i++) 2732 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2733 printf("\n"); 2734 break; 2735 } 2736 default: 2737 printf("unknown context: %x\n", c->ctx_op); 2738 } 2739 printf("END CTX\n"); 2740} 2741 2742static void 2743ubsec_dump_mcr(struct ubsec_mcr *mcr) 2744{ 2745 volatile struct ubsec_mcr_add *ma; 2746 int i; 2747 2748 printf("MCR:\n"); 2749 printf(" pkts: %u, flags 0x%x\n", 2750 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2751 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2752 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2753 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2754 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2755 letoh16(ma->mcr_reserved)); 2756 printf(" %d: ipkt ", i); 2757 ubsec_dump_pb(&ma->mcr_ipktbuf); 2758 printf(" %d: opkt ", i); 2759 ubsec_dump_pb(&ma->mcr_opktbuf); 2760 ma++; 2761 } 2762 printf("END MCR\n"); 2763} 2764#endif /* UBSEC_DEBUG */ 2765 2766/* 2767 * Return the number of significant bits of a big number. 2768 */ 2769static int 2770ubsec_ksigbits(struct crparam *cr) 2771{ 2772 u_int plen = (cr->crp_nbits + 7) / 8; 2773 int i, sig = plen * 8; 2774 u_int8_t c, *p = cr->crp_p; 2775 2776 for (i = plen - 1; i >= 0; i--) { 2777 c = p[i]; 2778 if (c != 0) { 2779 while ((c & 0x80) == 0) { 2780 sig--; 2781 c <<= 1; 2782 } 2783 break; 2784 } 2785 sig -= 8; 2786 } 2787 return (sig); 2788} 2789 2790static void 2791ubsec_kshift_r( 2792 u_int shiftbits, 2793 u_int8_t *src, u_int srcbits, 2794 u_int8_t *dst, u_int dstbits) 2795{ 2796 u_int slen, dlen; 2797 int i, si, di, n; 2798 2799 slen = (srcbits + 7) / 8; 2800 dlen = (dstbits + 7) / 8; 2801 2802 for (i = 0; i < slen; i++) 2803 dst[i] = src[i]; 2804 for (i = 0; i < dlen - slen; i++) 2805 dst[slen + i] = 0; 2806 2807 n = shiftbits / 8; 2808 if (n != 0) { 2809 si = dlen - n - 1; 2810 di = dlen - 1; 2811 while (si >= 0) 2812 dst[di--] = dst[si--]; 2813 while (di >= 0) 2814 dst[di--] = 0; 2815 } 2816 2817 n = shiftbits % 8; 2818 if (n != 0) { 2819 for (i = dlen - 1; i > 0; i--) 2820 dst[i] = (dst[i] << n) | 2821 (dst[i - 1] >> (8 - n)); 2822 dst[0] = dst[0] << n; 2823 } 2824} 2825 2826static void 2827ubsec_kshift_l( 2828 u_int shiftbits, 2829 u_int8_t *src, u_int srcbits, 2830 u_int8_t *dst, u_int dstbits) 2831{ 2832 int slen, dlen, i, n; 2833 2834 slen = (srcbits + 7) / 8; 2835 dlen = (dstbits + 7) / 8; 2836 2837 n = shiftbits / 8; 2838 for (i = 0; i < slen; i++) 2839 dst[i] = src[i + n]; 2840 for (i = 0; i < dlen - slen; i++) 2841 dst[slen + i] = 0; 2842 2843 n = shiftbits % 8; 2844 if (n != 0) { 2845 for (i = 0; i < (dlen - 1); i++) 2846 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2847 dst[dlen - 1] = dst[dlen - 1] >> n; 2848 } 2849} 2850