ubsec.c revision 109094
1/* $FreeBSD: head/sys/dev/ubsec/ubsec.c 109094 2003-01-11 04:55:52Z sam $ */ 2/* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */ 3 4/* 5 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 6 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 7 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 8 * 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Jason L. Wright 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 34 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Effort sponsored in part by the Defense Advanced Research Projects 38 * Agency (DARPA) and Air Force Research Laboratory, Air Force 39 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 40 * 41 */ 42 43#define UBSEC_DEBUG 44 45/* 46 * uBsec 5[56]01, 58xx hardware crypto accelerator 47 */ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/proc.h> 52#include <sys/errno.h> 53#include <sys/malloc.h> 54#include <sys/kernel.h> 55#include <sys/mbuf.h> 56#include <sys/lock.h> 57#include <sys/mutex.h> 58#include <sys/stdint.h> 59#include <sys/sysctl.h> 60#include <sys/endian.h> 61 62#include <vm/vm.h> 63#include <vm/pmap.h> 64 65#include <machine/clock.h> 66#include <machine/bus.h> 67#include <machine/resource.h> 68#include <sys/bus.h> 69#include <sys/rman.h> 70 71#include <crypto/sha1.h> 72#include <opencrypto/cryptodev.h> 73#include <opencrypto/cryptosoft.h> 74#include <sys/md5.h> 75#include <sys/random.h> 76 77#include <pci/pcivar.h> 78#include <pci/pcireg.h> 79 80/* grr, #defines for gratuitous incompatibility in queue.h */ 81#define SIMPLEQ_HEAD STAILQ_HEAD 82#define SIMPLEQ_ENTRY STAILQ_ENTRY 83#define SIMPLEQ_INIT STAILQ_INIT 84#define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL 85#define SIMPLEQ_EMPTY STAILQ_EMPTY 86#define SIMPLEQ_FIRST STAILQ_FIRST 87#define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD_UNTIL 88/* ditto for endian.h */ 89#define letoh16(x) le16toh(x) 90#define letoh32(x) le32toh(x) 91 92#include <dev/ubsec/ubsecreg.h> 93#include <dev/ubsec/ubsecvar.h> 94 95/* 96 * Prototypes and count for the pci_device structure 97 */ 98static int ubsec_probe(device_t); 99static int ubsec_attach(device_t); 100static int ubsec_detach(device_t); 101static int ubsec_suspend(device_t); 102static int ubsec_resume(device_t); 103static void ubsec_shutdown(device_t); 104 105static device_method_t ubsec_methods[] = { 106 /* Device interface */ 107 DEVMETHOD(device_probe, ubsec_probe), 108 DEVMETHOD(device_attach, ubsec_attach), 109 DEVMETHOD(device_detach, ubsec_detach), 110 DEVMETHOD(device_suspend, ubsec_suspend), 111 DEVMETHOD(device_resume, ubsec_resume), 112 DEVMETHOD(device_shutdown, ubsec_shutdown), 113 114 /* bus interface */ 115 DEVMETHOD(bus_print_child, bus_generic_print_child), 116 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 117 118 { 0, 0 } 119}; 120static driver_t ubsec_driver = { 121 "ubsec", 122 ubsec_methods, 123 sizeof (struct ubsec_softc) 124}; 125static devclass_t ubsec_devclass; 126 127DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0); 128MODULE_DEPEND(ubsec, crypto, 1, 1, 1); 129 130static void ubsec_intr(void *); 131static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *); 132static int ubsec_freesession(void *, u_int64_t); 133static int ubsec_process(void *, struct cryptop *, int); 134static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 135static int ubsec_feed(struct ubsec_softc *); 136static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 137static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 138static int ubsec_feed2(struct ubsec_softc *); 139static void ubsec_rng(void *); 140static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 141 struct ubsec_dma_alloc *, int); 142#define ubsec_dma_sync(_dma, _flags) \ 143 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 144static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 145static int ubsec_dmamap_aligned(struct ubsec_operand *op); 146 147static void ubsec_reset_board(struct ubsec_softc *sc); 148static void ubsec_init_board(struct ubsec_softc *sc); 149static void ubsec_init_pciregs(device_t dev); 150static void ubsec_totalreset(struct ubsec_softc *sc); 151 152static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q); 153 154static int ubsec_kprocess(void*, struct cryptkop *, int); 155static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int); 156static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int); 157static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int); 158static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 159static int ubsec_ksigbits(struct crparam *); 160static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 161static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 162 163#ifdef UBSEC_DEBUG 164static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 165static void ubsec_dump_mcr(struct ubsec_mcr *); 166static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *); 167 168static int ubsec_debug = 0; 169SYSCTL_INT(_debug, OID_AUTO, ubsec, CTLFLAG_RW, &ubsec_debug, 170 0, "UBSEC driver debugging printfs"); 171#endif 172 173#define READ_REG(sc,r) \ 174 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 175 176#define WRITE_REG(sc,reg,val) \ 177 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 178 179#define SWAP32(x) (x) = htole32(ntohl((x))) 180#define HTOLE32(x) (x) = htole32(x) 181 182 183struct ubsec_stats ubsecstats; 184SYSCTL_STRUCT(_kern, OID_AUTO, ubsec_stats, CTLFLAG_RD, &ubsecstats, 185 ubsec_stats, "Broadcom driver statistics"); 186/* 187 * ubsec_maxbatch controls the number of crypto ops to voluntarily 188 * collect into one submission to the hardware. This batching happens 189 * when ops are dispatched from the crypto subsystem with a hint that 190 * more are to follow immediately. These ops must also not be marked 191 * with a ``no delay'' flag. 192 */ 193static int ubsec_maxbatch = 1; 194SYSCTL_INT(_kern, OID_AUTO, ubsec_maxbatch, CTLFLAG_RW, &ubsec_maxbatch, 195 0, "Broadcom driver: max ops to batch w/o interrupt"); 196/* 197 * ubsec_maxaggr controls the number of crypto ops to submit to the 198 * hardware as a unit. This aggregation reduces the number of interrupts 199 * to the host at the expense of increased latency (for all but the last 200 * operation). For network traffic setting this to one yields the highest 201 * performance but at the expense of more interrupt processing. 202 */ 203static int ubsec_maxaggr = 1; 204SYSCTL_INT(_kern, OID_AUTO, ubsec_maxaggr, CTLFLAG_RW, &ubsec_maxaggr, 205 0, "Broadcom driver: max ops to aggregate under one interrupt"); 206 207static int 208ubsec_probe(device_t dev) 209{ 210 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 211 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 || 212 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)) 213 return (0); 214 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 215 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 || 216 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 || 217 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 218 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822)) 219 return (0); 220 return (ENXIO); 221} 222 223static const char* 224ubsec_partname(struct ubsec_softc *sc) 225{ 226 /* XXX sprintf numbers when not decoded */ 227 switch (pci_get_vendor(sc->sc_dev)) { 228 case PCI_VENDOR_BROADCOM: 229 switch (pci_get_device(sc->sc_dev)) { 230 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805"; 231 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820"; 232 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821"; 233 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822"; 234 } 235 return "Broadcom unknown-part"; 236 case PCI_VENDOR_BLUESTEEL: 237 switch (pci_get_device(sc->sc_dev)) { 238 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601"; 239 } 240 return "Bluesteel unknown-part"; 241 } 242 return "Unknown-vendor unknown-part"; 243} 244 245static int 246ubsec_attach(device_t dev) 247{ 248 struct ubsec_softc *sc = device_get_softc(dev); 249 struct ubsec_dma *dmap; 250 u_int32_t cmd, i; 251 int rid; 252 253 KASSERT(sc != NULL, ("ubsec_attach: null software carrier!")); 254 bzero(sc, sizeof (*sc)); 255 sc->sc_dev = dev; 256 257 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "crypto driver", MTX_DEF); 258 259 SIMPLEQ_INIT(&sc->sc_queue); 260 SIMPLEQ_INIT(&sc->sc_qchip); 261 SIMPLEQ_INIT(&sc->sc_queue2); 262 SIMPLEQ_INIT(&sc->sc_qchip2); 263 SIMPLEQ_INIT(&sc->sc_q2free); 264 265 /* XXX handle power management */ 266 267 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; 268 269 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 270 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601) 271 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 272 273 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 274 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805) 275 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 276 277 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 278 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820) 279 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 280 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 281 282 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 283 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 284 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822)) { 285 /* NB: the 5821/5822 defines some additional status bits */ 286 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY | 287 BS_STAT_MCR2_ALLEMPTY; 288 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 289 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 290 } 291 292 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 293 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 294 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 295 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 296 297 if (!(cmd & PCIM_CMD_MEMEN)) { 298 device_printf(dev, "failed to enable memory mapping\n"); 299 goto bad; 300 } 301 302 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 303 device_printf(dev, "failed to enable bus mastering\n"); 304 goto bad; 305 } 306 307 /* 308 * Setup memory-mapping of PCI registers. 309 */ 310 rid = BS_BAR; 311 sc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 312 0, ~0, 1, RF_ACTIVE); 313 if (sc->sc_sr == NULL) { 314 device_printf(dev, "cannot map register space\n"); 315 goto bad; 316 } 317 sc->sc_st = rman_get_bustag(sc->sc_sr); 318 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 319 320 /* 321 * Arrange interrupt line. 322 */ 323 rid = 0; 324 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 325 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 326 if (sc->sc_irq == NULL) { 327 device_printf(dev, "could not map interrupt\n"); 328 goto bad1; 329 } 330 /* 331 * NB: Network code assumes we are blocked with splimp() 332 * so make sure the IRQ is mapped appropriately. 333 */ 334 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 335 ubsec_intr, sc, &sc->sc_ih)) { 336 device_printf(dev, "could not establish interrupt\n"); 337 goto bad2; 338 } 339 340 sc->sc_cid = crypto_get_driverid(0); 341 if (sc->sc_cid < 0) { 342 device_printf(dev, "could not get crypto driver id\n"); 343 goto bad3; 344 } 345 346 /* 347 * Setup DMA descriptor area. 348 */ 349 if (bus_dma_tag_create(NULL, /* parent */ 350 1, 0, /* alignment, bounds */ 351 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 352 BUS_SPACE_MAXADDR, /* highaddr */ 353 NULL, NULL, /* filter, filterarg */ 354 0x3ffff, /* maxsize */ 355 UBS_MAX_SCATTER, /* nsegments */ 356 0xffff, /* maxsegsize */ 357 BUS_DMA_ALLOCNOW, /* flags */ 358 &sc->sc_dmat)) { 359 device_printf(dev, "cannot allocate DMA tag\n"); 360 goto bad4; 361 } 362 SIMPLEQ_INIT(&sc->sc_freequeue); 363 dmap = sc->sc_dmaa; 364 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 365 struct ubsec_q *q; 366 367 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 368 M_DEVBUF, M_NOWAIT); 369 if (q == NULL) { 370 device_printf(dev, "cannot allocate queue buffers\n"); 371 break; 372 } 373 374 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 375 &dmap->d_alloc, 0)) { 376 device_printf(dev, "cannot allocate dma buffers\n"); 377 free(q, M_DEVBUF); 378 break; 379 } 380 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 381 382 q->q_dma = dmap; 383 sc->sc_queuea[i] = q; 384 385 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 386 } 387 388 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc)); 389 390 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 391 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 392 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 393 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 394 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 395 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 396 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 397 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 398 399 /* 400 * Reset Broadcom chip 401 */ 402 ubsec_reset_board(sc); 403 404 /* 405 * Init Broadcom specific PCI settings 406 */ 407 ubsec_init_pciregs(dev); 408 409 /* 410 * Init Broadcom chip 411 */ 412 ubsec_init_board(sc); 413 414#ifndef UBSEC_NO_RNG 415 if (sc->sc_flags & UBS_FLAGS_RNG) { 416 sc->sc_statmask |= BS_STAT_MCR2_DONE; 417 418 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 419 &sc->sc_rng.rng_q.q_mcr, 0)) 420 goto skip_rng; 421 422 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 423 &sc->sc_rng.rng_q.q_ctx, 0)) { 424 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 425 goto skip_rng; 426 } 427 428 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 429 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 430 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 431 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 432 goto skip_rng; 433 } 434 435 if (hz >= 100) 436 sc->sc_rnghz = hz / 100; 437 else 438 sc->sc_rnghz = 1; 439 /* NB: 1 means the callout runs w/o Giant locked */ 440 callout_init(&sc->sc_rngto, 1); 441 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 442skip_rng: 443 ; 444 } 445#endif /* UBSEC_NO_RNG */ 446 447 if (sc->sc_flags & UBS_FLAGS_KEY) { 448 sc->sc_statmask |= BS_STAT_MCR2_DONE; 449 450 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 451 ubsec_kprocess, sc); 452#if 0 453 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 454 ubsec_kprocess, sc); 455#endif 456 } 457 return (0); 458bad4: 459 crypto_unregister_all(sc->sc_cid); 460bad3: 461 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 462bad2: 463 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 464bad1: 465 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 466bad: 467 mtx_destroy(&sc->sc_mtx); 468 return (ENXIO); 469} 470 471/* 472 * Detach a device that successfully probed. 473 */ 474static int 475ubsec_detach(device_t dev) 476{ 477 struct ubsec_softc *sc = device_get_softc(dev); 478 479 KASSERT(sc != NULL, ("ubsec_detach: null software carrier")); 480 481 /* XXX wait/abort active ops */ 482 483 UBSEC_LOCK(sc); 484 485 callout_stop(&sc->sc_rngto); 486 487 crypto_unregister_all(sc->sc_cid); 488 489 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 490 struct ubsec_q *q; 491 492 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 493 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 494 ubsec_dma_free(sc, &q->q_dma->d_alloc); 495 free(q, M_DEVBUF); 496 } 497#ifndef UBSEC_NO_RNG 498 if (sc->sc_flags & UBS_FLAGS_RNG) { 499 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 500 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 501 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 502 } 503#endif /* UBSEC_NO_RNG */ 504 505 bus_generic_detach(dev); 506 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 507 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 508 509 bus_dma_tag_destroy(sc->sc_dmat); 510 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 511 512 UBSEC_UNLOCK(sc); 513 514 mtx_destroy(&sc->sc_mtx); 515 516 return (0); 517} 518 519/* 520 * Stop all chip i/o so that the kernel's probe routines don't 521 * get confused by errant DMAs when rebooting. 522 */ 523static void 524ubsec_shutdown(device_t dev) 525{ 526#ifdef notyet 527 ubsec_stop(device_get_softc(dev)); 528#endif 529} 530 531/* 532 * Device suspend routine. 533 */ 534static int 535ubsec_suspend(device_t dev) 536{ 537 struct ubsec_softc *sc = device_get_softc(dev); 538 539 KASSERT(sc != NULL, ("ubsec_suspend: null software carrier")); 540#ifdef notyet 541 /* XXX stop the device and save PCI settings */ 542#endif 543 sc->sc_suspended = 1; 544 545 return (0); 546} 547 548static int 549ubsec_resume(device_t dev) 550{ 551 struct ubsec_softc *sc = device_get_softc(dev); 552 553 KASSERT(sc != NULL, ("ubsec_resume: null software carrier")); 554#ifdef notyet 555 /* XXX retore PCI settings and start the device */ 556#endif 557 sc->sc_suspended = 0; 558 return (0); 559} 560 561/* 562 * UBSEC Interrupt routine 563 */ 564static void 565ubsec_intr(void *arg) 566{ 567 struct ubsec_softc *sc = arg; 568 volatile u_int32_t stat; 569 struct ubsec_q *q; 570 struct ubsec_dma *dmap; 571 int npkts = 0, i; 572 573 UBSEC_LOCK(sc); 574 575 stat = READ_REG(sc, BS_STAT); 576 stat &= sc->sc_statmask; 577 if (stat == 0) { 578 UBSEC_UNLOCK(sc); 579 return; 580 } 581 582 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 583 584 /* 585 * Check to see if we have any packets waiting for us 586 */ 587 if ((stat & BS_STAT_MCR1_DONE)) { 588 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 589 q = SIMPLEQ_FIRST(&sc->sc_qchip); 590 dmap = q->q_dma; 591 592 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 593 break; 594 595 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 596 597 npkts = q->q_nstacked_mcrs; 598 sc->sc_nqchip -= 1+npkts; 599 /* 600 * search for further sc_qchip ubsec_q's that share 601 * the same MCR, and complete them too, they must be 602 * at the top. 603 */ 604 for (i = 0; i < npkts; i++) { 605 if(q->q_stacked_mcr[i]) { 606 ubsec_callback(sc, q->q_stacked_mcr[i]); 607 ubsecstats.hst_opackets++; 608 } else { 609 break; 610 } 611 } 612 ubsec_callback(sc, q); 613 ubsecstats.hst_opackets++; 614 } 615 616 /* 617 * Don't send any more packet to chip if there has been 618 * a DMAERR. 619 */ 620 if (!(stat & BS_STAT_DMAERR)) 621 ubsec_feed(sc); 622 } 623 624 /* 625 * Check to see if we have any key setups/rng's waiting for us 626 */ 627 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 628 (stat & BS_STAT_MCR2_DONE)) { 629 struct ubsec_q2 *q2; 630 struct ubsec_mcr *mcr; 631 632 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 633 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 634 635 ubsec_dma_sync(&q2->q_mcr, 636 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 637 638 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 639 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 640 ubsec_dma_sync(&q2->q_mcr, 641 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 642 break; 643 } 644 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next); 645 ubsec_callback2(sc, q2); 646 /* 647 * Don't send any more packet to chip if there has been 648 * a DMAERR. 649 */ 650 if (!(stat & BS_STAT_DMAERR)) 651 ubsec_feed2(sc); 652 } 653 } 654 655 /* 656 * Check to see if we got any DMA Error 657 */ 658 if (stat & BS_STAT_DMAERR) { 659#ifdef UBSEC_DEBUG 660 if (ubsec_debug) { 661 volatile u_int32_t a = READ_REG(sc, BS_ERR); 662 663 printf("dmaerr %s@%08x\n", 664 (a & BS_ERR_READ) ? "read" : "write", 665 a & BS_ERR_ADDR); 666 } 667#endif /* UBSEC_DEBUG */ 668 ubsecstats.hst_dmaerr++; 669 ubsec_totalreset(sc); 670 ubsec_feed(sc); 671 } 672 673 if (sc->sc_needwakeup) { /* XXX check high watermark */ 674 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 675#ifdef UBSEC_DEBUG 676 if (ubsec_debug) 677 device_printf(sc->sc_dev, "wakeup crypto (%x)\n", 678 sc->sc_needwakeup); 679#endif /* UBSEC_DEBUG */ 680 sc->sc_needwakeup &= ~wakeup; 681 crypto_unblock(sc->sc_cid, wakeup); 682 } 683 684 UBSEC_UNLOCK(sc); 685} 686 687/* 688 * ubsec_feed() - aggregate and post requests to chip 689 */ 690static int 691ubsec_feed(struct ubsec_softc *sc) 692{ 693 struct ubsec_q *q, *q2; 694 int npkts, i; 695 void *v; 696 u_int32_t stat; 697 698 npkts = sc->sc_nqueue; 699 if (npkts > ubsecstats.hst_maxqueue) 700 ubsecstats.hst_maxqueue = npkts; 701 /* 702 * Decide how many ops to combine in a single MCR. We cannot 703 * aggregate more than UBS_MAX_AGGR because this is the number 704 * of slots defined in the data structure. Otherwise we clamp 705 * based on the tunable parameter ubsec_maxaggr. Note that 706 * aggregation can happen in two ways: either by batching ops 707 * from above or because the h/w backs up and throttles us. 708 * Aggregating ops reduces the number of interrupts to the host 709 * but also (potentially) increases the latency for processing 710 * completed ops as we only get an interrupt when all aggregated 711 * ops have completed. 712 */ 713 if (npkts > UBS_MAX_AGGR) 714 npkts = UBS_MAX_AGGR; 715 if (npkts > ubsec_maxaggr) 716 npkts = ubsec_maxaggr; 717 if (npkts > ubsecstats.hst_maxbatch) 718 ubsecstats.hst_maxbatch = npkts; 719 if (npkts < 2) 720 goto feed1; 721 ubsecstats.hst_totbatch += npkts-1; 722 723 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 724 if (stat & BS_STAT_DMAERR) { 725 ubsec_totalreset(sc); 726 ubsecstats.hst_dmaerr++; 727 } else 728 ubsecstats.hst_mcr1full++; 729 return (0); 730 } 731 732#ifdef UBSEC_DEBUG 733 if (ubsec_debug) 734 printf("merging %d records\n", npkts); 735#endif /* UBSEC_DEBUG */ 736 737 q = SIMPLEQ_FIRST(&sc->sc_queue); 738 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 739 --sc->sc_nqueue; 740 741 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 742 if (q->q_dst_map != NULL) 743 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 744 745 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 746 747 for (i = 0; i < q->q_nstacked_mcrs; i++) { 748 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 749 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 750 BUS_DMASYNC_PREWRITE); 751 if (q2->q_dst_map != NULL) 752 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 753 BUS_DMASYNC_PREREAD); 754 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next); 755 --sc->sc_nqueue; 756 757 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - 758 sizeof(struct ubsec_mcr_add)); 759 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 760 q->q_stacked_mcr[i] = q2; 761 } 762 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 763 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 764 sc->sc_nqchip += npkts; 765 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 766 ubsecstats.hst_maxqchip = sc->sc_nqchip; 767 ubsec_dma_sync(&q->q_dma->d_alloc, 768 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 769 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 770 offsetof(struct ubsec_dmachunk, d_mcr)); 771 return (0); 772 773feed1: 774 while (!SIMPLEQ_EMPTY(&sc->sc_queue)) { 775 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 776 if (stat & BS_STAT_DMAERR) { 777 ubsec_totalreset(sc); 778 ubsecstats.hst_dmaerr++; 779 } else 780 ubsecstats.hst_mcr1full++; 781 break; 782 } 783 784 q = SIMPLEQ_FIRST(&sc->sc_queue); 785 786 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 787 BUS_DMASYNC_PREWRITE); 788 if (q->q_dst_map != NULL) 789 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 790 BUS_DMASYNC_PREREAD); 791 ubsec_dma_sync(&q->q_dma->d_alloc, 792 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 793 794 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 795 offsetof(struct ubsec_dmachunk, d_mcr)); 796#ifdef UBSEC_DEBUG 797 if (ubsec_debug) 798 printf("feed: q->chip %p %08x stat %08x\n", 799 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr), 800 stat); 801#endif /* UBSEC_DEBUG */ 802 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 803 --sc->sc_nqueue; 804 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 805 sc->sc_nqchip++; 806 } 807 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 808 ubsecstats.hst_maxqchip = sc->sc_nqchip; 809 return (0); 810} 811 812/* 813 * Allocate a new 'session' and return an encoded session id. 'sidp' 814 * contains our registration id, and should contain an encoded session 815 * id on successful allocation. 816 */ 817static int 818ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 819{ 820 struct cryptoini *c, *encini = NULL, *macini = NULL; 821 struct ubsec_softc *sc = arg; 822 struct ubsec_session *ses = NULL; 823 MD5_CTX md5ctx; 824 SHA1_CTX sha1ctx; 825 int i, sesn; 826 827 KASSERT(sc != NULL, ("ubsec_newsession: null softc")); 828 if (sidp == NULL || cri == NULL || sc == NULL) 829 return (EINVAL); 830 831 for (c = cri; c != NULL; c = c->cri_next) { 832 if (c->cri_alg == CRYPTO_MD5_HMAC || 833 c->cri_alg == CRYPTO_SHA1_HMAC) { 834 if (macini) 835 return (EINVAL); 836 macini = c; 837 } else if (c->cri_alg == CRYPTO_DES_CBC || 838 c->cri_alg == CRYPTO_3DES_CBC) { 839 if (encini) 840 return (EINVAL); 841 encini = c; 842 } else 843 return (EINVAL); 844 } 845 if (encini == NULL && macini == NULL) 846 return (EINVAL); 847 848 if (sc->sc_sessions == NULL) { 849 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 850 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 851 if (ses == NULL) 852 return (ENOMEM); 853 sesn = 0; 854 sc->sc_nsessions = 1; 855 } else { 856 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 857 if (sc->sc_sessions[sesn].ses_used == 0) { 858 ses = &sc->sc_sessions[sesn]; 859 break; 860 } 861 } 862 863 if (ses == NULL) { 864 sesn = sc->sc_nsessions; 865 ses = (struct ubsec_session *)malloc((sesn + 1) * 866 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 867 if (ses == NULL) 868 return (ENOMEM); 869 bcopy(sc->sc_sessions, ses, sesn * 870 sizeof(struct ubsec_session)); 871 bzero(sc->sc_sessions, sesn * 872 sizeof(struct ubsec_session)); 873 free(sc->sc_sessions, M_DEVBUF); 874 sc->sc_sessions = ses; 875 ses = &sc->sc_sessions[sesn]; 876 sc->sc_nsessions++; 877 } 878 } 879 880 bzero(ses, sizeof(struct ubsec_session)); 881 ses->ses_used = 1; 882 if (encini) { 883 /* get an IV, network byte order */ 884 /* XXX may read fewer than requested */ 885 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 886 887 /* Go ahead and compute key in ubsec's byte order */ 888 if (encini->cri_alg == CRYPTO_DES_CBC) { 889 bcopy(encini->cri_key, &ses->ses_deskey[0], 8); 890 bcopy(encini->cri_key, &ses->ses_deskey[2], 8); 891 bcopy(encini->cri_key, &ses->ses_deskey[4], 8); 892 } else 893 bcopy(encini->cri_key, ses->ses_deskey, 24); 894 895 SWAP32(ses->ses_deskey[0]); 896 SWAP32(ses->ses_deskey[1]); 897 SWAP32(ses->ses_deskey[2]); 898 SWAP32(ses->ses_deskey[3]); 899 SWAP32(ses->ses_deskey[4]); 900 SWAP32(ses->ses_deskey[5]); 901 } 902 903 if (macini) { 904 for (i = 0; i < macini->cri_klen / 8; i++) 905 macini->cri_key[i] ^= HMAC_IPAD_VAL; 906 907 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 908 MD5Init(&md5ctx); 909 MD5Update(&md5ctx, macini->cri_key, 910 macini->cri_klen / 8); 911 MD5Update(&md5ctx, hmac_ipad_buffer, 912 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 913 bcopy(md5ctx.state, ses->ses_hminner, 914 sizeof(md5ctx.state)); 915 } else { 916 SHA1Init(&sha1ctx); 917 SHA1Update(&sha1ctx, macini->cri_key, 918 macini->cri_klen / 8); 919 SHA1Update(&sha1ctx, hmac_ipad_buffer, 920 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 921 bcopy(sha1ctx.h.b32, ses->ses_hminner, 922 sizeof(sha1ctx.h.b32)); 923 } 924 925 for (i = 0; i < macini->cri_klen / 8; i++) 926 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 927 928 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 929 MD5Init(&md5ctx); 930 MD5Update(&md5ctx, macini->cri_key, 931 macini->cri_klen / 8); 932 MD5Update(&md5ctx, hmac_opad_buffer, 933 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 934 bcopy(md5ctx.state, ses->ses_hmouter, 935 sizeof(md5ctx.state)); 936 } else { 937 SHA1Init(&sha1ctx); 938 SHA1Update(&sha1ctx, macini->cri_key, 939 macini->cri_klen / 8); 940 SHA1Update(&sha1ctx, hmac_opad_buffer, 941 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 942 bcopy(sha1ctx.h.b32, ses->ses_hmouter, 943 sizeof(sha1ctx.h.b32)); 944 } 945 946 for (i = 0; i < macini->cri_klen / 8; i++) 947 macini->cri_key[i] ^= HMAC_OPAD_VAL; 948 } 949 950 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); 951 return (0); 952} 953 954/* 955 * Deallocate a session. 956 */ 957static int 958ubsec_freesession(void *arg, u_int64_t tid) 959{ 960 struct ubsec_softc *sc = arg; 961 int session; 962 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 963 964 KASSERT(sc != NULL, ("ubsec_freesession: null softc")); 965 if (sc == NULL) 966 return (EINVAL); 967 968 session = UBSEC_SESSION(sid); 969 if (session >= sc->sc_nsessions) 970 return (EINVAL); 971 972 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 973 return (0); 974} 975 976static void 977ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 978{ 979 struct ubsec_operand *op = arg; 980 981 KASSERT(nsegs <= UBS_MAX_SCATTER, 982 ("Too many DMA segments returned when mapping operand")); 983#ifdef UBSEC_DEBUG 984 if (ubsec_debug) 985 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 986 (u_int) mapsize, nsegs); 987#endif 988 op->mapsize = mapsize; 989 op->nsegs = nsegs; 990 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 991} 992 993static int 994ubsec_process(void *arg, struct cryptop *crp, int hint) 995{ 996 struct ubsec_q *q = NULL; 997 int err = 0, i, j, nicealign; 998 struct ubsec_softc *sc = arg; 999 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1000 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1001 int sskip, dskip, stheend, dtheend; 1002 int16_t coffset; 1003 struct ubsec_session *ses; 1004 struct ubsec_pktctx ctx; 1005 struct ubsec_dma *dmap = NULL; 1006 1007 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1008 ubsecstats.hst_invalid++; 1009 return (EINVAL); 1010 } 1011 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1012 ubsecstats.hst_badsession++; 1013 return (EINVAL); 1014 } 1015 1016 UBSEC_LOCK(sc); 1017 1018 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1019 ubsecstats.hst_queuefull++; 1020 sc->sc_needwakeup |= CRYPTO_SYMQ; 1021 UBSEC_UNLOCK(sc); 1022 return (ERESTART); 1023 } 1024 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1025 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 1026 UBSEC_UNLOCK(sc); 1027 1028 dmap = q->q_dma; /* Save dma pointer */ 1029 bzero(q, sizeof(struct ubsec_q)); 1030 bzero(&ctx, sizeof(ctx)); 1031 1032 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1033 q->q_dma = dmap; 1034 ses = &sc->sc_sessions[q->q_sesn]; 1035 1036 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1037 q->q_src_m = (struct mbuf *)crp->crp_buf; 1038 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1039 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1040 q->q_src_io = (struct uio *)crp->crp_buf; 1041 q->q_dst_io = (struct uio *)crp->crp_buf; 1042 } else { 1043 ubsecstats.hst_badflags++; 1044 err = EINVAL; 1045 goto errout; /* XXX we don't handle contiguous blocks! */ 1046 } 1047 1048 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 1049 1050 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1051 dmap->d_dma->d_mcr.mcr_flags = 0; 1052 q->q_crp = crp; 1053 1054 crd1 = crp->crp_desc; 1055 if (crd1 == NULL) { 1056 ubsecstats.hst_nodesc++; 1057 err = EINVAL; 1058 goto errout; 1059 } 1060 crd2 = crd1->crd_next; 1061 1062 if (crd2 == NULL) { 1063 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 1064 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 1065 maccrd = crd1; 1066 enccrd = NULL; 1067 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1068 crd1->crd_alg == CRYPTO_3DES_CBC) { 1069 maccrd = NULL; 1070 enccrd = crd1; 1071 } else { 1072 ubsecstats.hst_badalg++; 1073 err = EINVAL; 1074 goto errout; 1075 } 1076 } else { 1077 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1078 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1079 (crd2->crd_alg == CRYPTO_DES_CBC || 1080 crd2->crd_alg == CRYPTO_3DES_CBC) && 1081 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1082 maccrd = crd1; 1083 enccrd = crd2; 1084 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1085 crd1->crd_alg == CRYPTO_3DES_CBC) && 1086 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1087 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1088 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1089 enccrd = crd1; 1090 maccrd = crd2; 1091 } else { 1092 /* 1093 * We cannot order the ubsec as requested 1094 */ 1095 ubsecstats.hst_badalg++; 1096 err = EINVAL; 1097 goto errout; 1098 } 1099 } 1100 1101 if (enccrd) { 1102 encoffset = enccrd->crd_skip; 1103 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1104 1105 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1106 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1107 1108 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1109 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1110 else { 1111 ctx.pc_iv[0] = ses->ses_iv[0]; 1112 ctx.pc_iv[1] = ses->ses_iv[1]; 1113 } 1114 1115 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1116 if (crp->crp_flags & CRYPTO_F_IMBUF) 1117 m_copyback(q->q_src_m, 1118 enccrd->crd_inject, 1119 8, (caddr_t)ctx.pc_iv); 1120 else if (crp->crp_flags & CRYPTO_F_IOV) 1121 cuio_copyback(q->q_src_io, 1122 enccrd->crd_inject, 1123 8, (caddr_t)ctx.pc_iv); 1124 } 1125 } else { 1126 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1127 1128 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1129 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1130 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1131 m_copydata(q->q_src_m, enccrd->crd_inject, 1132 8, (caddr_t)ctx.pc_iv); 1133 else if (crp->crp_flags & CRYPTO_F_IOV) 1134 cuio_copydata(q->q_src_io, 1135 enccrd->crd_inject, 8, 1136 (caddr_t)ctx.pc_iv); 1137 } 1138 1139 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1140 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1141 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1142 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1143 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1144 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1145 SWAP32(ctx.pc_iv[0]); 1146 SWAP32(ctx.pc_iv[1]); 1147 } 1148 1149 if (maccrd) { 1150 macoffset = maccrd->crd_skip; 1151 1152 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1153 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1154 else 1155 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1156 1157 for (i = 0; i < 5; i++) { 1158 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1159 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1160 1161 HTOLE32(ctx.pc_hminner[i]); 1162 HTOLE32(ctx.pc_hmouter[i]); 1163 } 1164 } 1165 1166 if (enccrd && maccrd) { 1167 /* 1168 * ubsec cannot handle packets where the end of encryption 1169 * and authentication are not the same, or where the 1170 * encrypted part begins before the authenticated part. 1171 */ 1172 if ((encoffset + enccrd->crd_len) != 1173 (macoffset + maccrd->crd_len)) { 1174 ubsecstats.hst_lenmismatch++; 1175 err = EINVAL; 1176 goto errout; 1177 } 1178 if (enccrd->crd_skip < maccrd->crd_skip) { 1179 ubsecstats.hst_skipmismatch++; 1180 err = EINVAL; 1181 goto errout; 1182 } 1183 sskip = maccrd->crd_skip; 1184 cpskip = dskip = enccrd->crd_skip; 1185 stheend = maccrd->crd_len; 1186 dtheend = enccrd->crd_len; 1187 coffset = enccrd->crd_skip - maccrd->crd_skip; 1188 cpoffset = cpskip + dtheend; 1189#ifdef UBSEC_DEBUG 1190 if (ubsec_debug) { 1191 printf("mac: skip %d, len %d, inject %d\n", 1192 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1193 printf("enc: skip %d, len %d, inject %d\n", 1194 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1195 printf("src: skip %d, len %d\n", sskip, stheend); 1196 printf("dst: skip %d, len %d\n", dskip, dtheend); 1197 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1198 coffset, stheend, cpskip, cpoffset); 1199 } 1200#endif 1201 } else { 1202 cpskip = dskip = sskip = macoffset + encoffset; 1203 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1204 cpoffset = cpskip + dtheend; 1205 coffset = 0; 1206 } 1207 ctx.pc_offset = htole16(coffset >> 2); 1208 1209 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) { 1210 ubsecstats.hst_nomap++; 1211 err = ENOMEM; 1212 goto errout; 1213 } 1214 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1215 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1216 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1217 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1218 q->q_src_map = NULL; 1219 ubsecstats.hst_noload++; 1220 err = ENOMEM; 1221 goto errout; 1222 } 1223 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1224 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1225 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1226 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1227 q->q_src_map = NULL; 1228 ubsecstats.hst_noload++; 1229 err = ENOMEM; 1230 goto errout; 1231 } 1232 } 1233 nicealign = ubsec_dmamap_aligned(&q->q_src); 1234 1235 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1236 1237#ifdef UBSEC_DEBUG 1238 if (ubsec_debug) 1239 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1240#endif 1241 for (i = j = 0; i < q->q_src_nsegs; i++) { 1242 struct ubsec_pktbuf *pb; 1243 bus_size_t packl = q->q_src_segs[i].ds_len; 1244 bus_addr_t packp = q->q_src_segs[i].ds_addr; 1245 1246 if (sskip >= packl) { 1247 sskip -= packl; 1248 continue; 1249 } 1250 1251 packl -= sskip; 1252 packp += sskip; 1253 sskip = 0; 1254 1255 if (packl > 0xfffc) { 1256 err = EIO; 1257 goto errout; 1258 } 1259 1260 if (j == 0) 1261 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1262 else 1263 pb = &dmap->d_dma->d_sbuf[j - 1]; 1264 1265 pb->pb_addr = htole32(packp); 1266 1267 if (stheend) { 1268 if (packl > stheend) { 1269 pb->pb_len = htole32(stheend); 1270 stheend = 0; 1271 } else { 1272 pb->pb_len = htole32(packl); 1273 stheend -= packl; 1274 } 1275 } else 1276 pb->pb_len = htole32(packl); 1277 1278 if ((i + 1) == q->q_src_nsegs) 1279 pb->pb_next = 0; 1280 else 1281 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1282 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1283 j++; 1284 } 1285 1286 if (enccrd == NULL && maccrd != NULL) { 1287 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1288 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1289 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1290 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1291#ifdef UBSEC_DEBUG 1292 if (ubsec_debug) 1293 printf("opkt: %x %x %x\n", 1294 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1295 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1296 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1297#endif 1298 } else { 1299 if (crp->crp_flags & CRYPTO_F_IOV) { 1300 if (!nicealign) { 1301 ubsecstats.hst_iovmisaligned++; 1302 err = EINVAL; 1303 goto errout; 1304 } 1305 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1306 &q->q_dst_map)) { 1307 ubsecstats.hst_nomap++; 1308 err = ENOMEM; 1309 goto errout; 1310 } 1311 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1312 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) { 1313 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1314 q->q_dst_map = NULL; 1315 ubsecstats.hst_noload++; 1316 err = ENOMEM; 1317 goto errout; 1318 } 1319 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1320 if (nicealign) { 1321 q->q_dst = q->q_src; 1322 } else { 1323 int totlen, len; 1324 struct mbuf *m, *top, **mp; 1325 1326 ubsecstats.hst_unaligned++; 1327 totlen = q->q_src_mapsize; 1328 if (q->q_src_m->m_flags & M_PKTHDR) { 1329 len = MHLEN; 1330 MGETHDR(m, M_DONTWAIT, MT_DATA); 1331 if (m && !m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)) { 1332 m_free(m); 1333 m = NULL; 1334 } 1335 } else { 1336 len = MLEN; 1337 MGET(m, M_DONTWAIT, MT_DATA); 1338 } 1339 if (m == NULL) { 1340 ubsecstats.hst_nombuf++; 1341 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1342 goto errout; 1343 } 1344 if (totlen >= MINCLSIZE) { 1345 MCLGET(m, M_DONTWAIT); 1346 if ((m->m_flags & M_EXT) == 0) { 1347 m_free(m); 1348 ubsecstats.hst_nomcl++; 1349 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1350 goto errout; 1351 } 1352 len = MCLBYTES; 1353 } 1354 m->m_len = len; 1355 top = NULL; 1356 mp = ⊤ 1357 1358 while (totlen > 0) { 1359 if (top) { 1360 MGET(m, M_DONTWAIT, MT_DATA); 1361 if (m == NULL) { 1362 m_freem(top); 1363 ubsecstats.hst_nombuf++; 1364 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1365 goto errout; 1366 } 1367 len = MLEN; 1368 } 1369 if (top && totlen >= MINCLSIZE) { 1370 MCLGET(m, M_DONTWAIT); 1371 if ((m->m_flags & M_EXT) == 0) { 1372 *mp = m; 1373 m_freem(top); 1374 ubsecstats.hst_nomcl++; 1375 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1376 goto errout; 1377 } 1378 len = MCLBYTES; 1379 } 1380 m->m_len = len = min(totlen, len); 1381 totlen -= len; 1382 *mp = m; 1383 mp = &m->m_next; 1384 } 1385 q->q_dst_m = top; 1386 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1387 cpskip, cpoffset); 1388 if (bus_dmamap_create(sc->sc_dmat, 1389 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) { 1390 ubsecstats.hst_nomap++; 1391 err = ENOMEM; 1392 goto errout; 1393 } 1394 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1395 q->q_dst_map, q->q_dst_m, 1396 ubsec_op_cb, &q->q_dst, 1397 BUS_DMA_NOWAIT) != 0) { 1398 bus_dmamap_destroy(sc->sc_dmat, 1399 q->q_dst_map); 1400 q->q_dst_map = NULL; 1401 ubsecstats.hst_noload++; 1402 err = ENOMEM; 1403 goto errout; 1404 } 1405 } 1406 } else { 1407 ubsecstats.hst_badflags++; 1408 err = EINVAL; 1409 goto errout; 1410 } 1411 1412#ifdef UBSEC_DEBUG 1413 if (ubsec_debug) 1414 printf("dst skip: %d\n", dskip); 1415#endif 1416 for (i = j = 0; i < q->q_dst_nsegs; i++) { 1417 struct ubsec_pktbuf *pb; 1418 bus_size_t packl = q->q_dst_segs[i].ds_len; 1419 bus_addr_t packp = q->q_dst_segs[i].ds_addr; 1420 1421 if (dskip >= packl) { 1422 dskip -= packl; 1423 continue; 1424 } 1425 1426 packl -= dskip; 1427 packp += dskip; 1428 dskip = 0; 1429 1430 if (packl > 0xfffc) { 1431 err = EIO; 1432 goto errout; 1433 } 1434 1435 if (j == 0) 1436 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1437 else 1438 pb = &dmap->d_dma->d_dbuf[j - 1]; 1439 1440 pb->pb_addr = htole32(packp); 1441 1442 if (dtheend) { 1443 if (packl > dtheend) { 1444 pb->pb_len = htole32(dtheend); 1445 dtheend = 0; 1446 } else { 1447 pb->pb_len = htole32(packl); 1448 dtheend -= packl; 1449 } 1450 } else 1451 pb->pb_len = htole32(packl); 1452 1453 if ((i + 1) == q->q_dst_nsegs) { 1454 if (maccrd) 1455 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1456 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1457 else 1458 pb->pb_next = 0; 1459 } else 1460 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1461 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1462 j++; 1463 } 1464 } 1465 1466 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1467 offsetof(struct ubsec_dmachunk, d_ctx)); 1468 1469 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1470 struct ubsec_pktctx_long *ctxl; 1471 1472 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr + 1473 offsetof(struct ubsec_dmachunk, d_ctx)); 1474 1475 /* transform small context into long context */ 1476 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1477 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1478 ctxl->pc_flags = ctx.pc_flags; 1479 ctxl->pc_offset = ctx.pc_offset; 1480 for (i = 0; i < 6; i++) 1481 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1482 for (i = 0; i < 5; i++) 1483 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1484 for (i = 0; i < 5; i++) 1485 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1486 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1487 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1488 } else 1489 bcopy(&ctx, dmap->d_alloc.dma_vaddr + 1490 offsetof(struct ubsec_dmachunk, d_ctx), 1491 sizeof(struct ubsec_pktctx)); 1492 1493 UBSEC_LOCK(sc); 1494 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1495 sc->sc_nqueue++; 1496 ubsecstats.hst_ipackets++; 1497 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size; 1498 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= ubsec_maxbatch) 1499 ubsec_feed(sc); 1500 UBSEC_UNLOCK(sc); 1501 return (0); 1502 1503errout: 1504 if (q != NULL) { 1505 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1506 m_freem(q->q_dst_m); 1507 1508 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1509 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1510 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1511 } 1512 if (q->q_src_map != NULL) { 1513 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1514 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1515 } 1516 1517 UBSEC_LOCK(sc); 1518 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1519 UBSEC_UNLOCK(sc); 1520 } 1521 if (err != ERESTART) { 1522 crp->crp_etype = err; 1523 crypto_done(crp); 1524 } else { 1525 sc->sc_needwakeup |= CRYPTO_SYMQ; 1526 } 1527 return (err); 1528} 1529 1530static void 1531ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1532{ 1533 struct cryptop *crp = (struct cryptop *)q->q_crp; 1534 struct cryptodesc *crd; 1535 struct ubsec_dma *dmap = q->q_dma; 1536 1537 ubsec_dma_sync(&dmap->d_alloc, 1538 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1539 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1540 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1541 BUS_DMASYNC_POSTREAD); 1542 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1543 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1544 } 1545 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE); 1546 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1547 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1548 1549 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1550 m_freem(q->q_src_m); 1551 crp->crp_buf = (caddr_t)q->q_dst_m; 1552 } 1553 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len; 1554 1555 /* copy out IV for future use */ 1556 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1557 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1558 if (crd->crd_alg != CRYPTO_DES_CBC && 1559 crd->crd_alg != CRYPTO_3DES_CBC) 1560 continue; 1561 if (crp->crp_flags & CRYPTO_F_IMBUF) 1562 m_copydata((struct mbuf *)crp->crp_buf, 1563 crd->crd_skip + crd->crd_len - 8, 8, 1564 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1565 else if (crp->crp_flags & CRYPTO_F_IOV) { 1566 cuio_copydata((struct uio *)crp->crp_buf, 1567 crd->crd_skip + crd->crd_len - 8, 8, 1568 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1569 } 1570 break; 1571 } 1572 } 1573 1574 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1575 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1576 crd->crd_alg != CRYPTO_SHA1_HMAC) 1577 continue; 1578 if (crp->crp_flags & CRYPTO_F_IMBUF) 1579 m_copyback((struct mbuf *)crp->crp_buf, 1580 crd->crd_inject, 12, 1581 (caddr_t)dmap->d_dma->d_macbuf); 1582 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1583 bcopy((caddr_t)dmap->d_dma->d_macbuf, 1584 crp->crp_mac, 12); 1585 break; 1586 } 1587 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1588 crypto_done(crp); 1589} 1590 1591static void 1592ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1593{ 1594 int i, j, dlen, slen; 1595 caddr_t dptr, sptr; 1596 1597 j = 0; 1598 sptr = srcm->m_data; 1599 slen = srcm->m_len; 1600 dptr = dstm->m_data; 1601 dlen = dstm->m_len; 1602 1603 while (1) { 1604 for (i = 0; i < min(slen, dlen); i++) { 1605 if (j < hoffset || j >= toffset) 1606 *dptr++ = *sptr++; 1607 slen--; 1608 dlen--; 1609 j++; 1610 } 1611 if (slen == 0) { 1612 srcm = srcm->m_next; 1613 if (srcm == NULL) 1614 return; 1615 sptr = srcm->m_data; 1616 slen = srcm->m_len; 1617 } 1618 if (dlen == 0) { 1619 dstm = dstm->m_next; 1620 if (dstm == NULL) 1621 return; 1622 dptr = dstm->m_data; 1623 dlen = dstm->m_len; 1624 } 1625 } 1626} 1627 1628/* 1629 * feed the key generator, must be called at splimp() or higher. 1630 */ 1631static int 1632ubsec_feed2(struct ubsec_softc *sc) 1633{ 1634 struct ubsec_q2 *q; 1635 1636 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1637 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1638 break; 1639 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1640 1641 ubsec_dma_sync(&q->q_mcr, 1642 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1643 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE); 1644 1645 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1646 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next); 1647 --sc->sc_nqueue2; 1648 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1649 } 1650 return (0); 1651} 1652 1653/* 1654 * Callback for handling random numbers 1655 */ 1656static void 1657ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1658{ 1659 struct cryptkop *krp; 1660 struct ubsec_ctx_keyop *ctx; 1661 1662 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1663 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE); 1664 1665 switch (q->q_type) { 1666#ifndef UBSEC_NO_RNG 1667 case UBS_CTXOP_RNGBYPASS: { 1668 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1669 1670 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD); 1671 random_harvest(rng->rng_buf.dma_vaddr, 1672 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t), 1673 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t)*NBBY, 0, 1674 RANDOM_PURE); 1675 rng->rng_used = 0; 1676 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1677 break; 1678 } 1679#endif 1680 case UBS_CTXOP_MODEXP: { 1681 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1682 u_int rlen, clen; 1683 1684 krp = me->me_krp; 1685 rlen = (me->me_modbits + 7) / 8; 1686 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1687 1688 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE); 1689 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE); 1690 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD); 1691 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE); 1692 1693 if (clen < rlen) 1694 krp->krp_status = E2BIG; 1695 else { 1696 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1697 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1698 (krp->krp_param[krp->krp_iparams].crp_nbits 1699 + 7) / 8); 1700 bcopy(me->me_C.dma_vaddr, 1701 krp->krp_param[krp->krp_iparams].crp_p, 1702 (me->me_modbits + 7) / 8); 1703 } else 1704 ubsec_kshift_l(me->me_shiftbits, 1705 me->me_C.dma_vaddr, me->me_normbits, 1706 krp->krp_param[krp->krp_iparams].crp_p, 1707 krp->krp_param[krp->krp_iparams].crp_nbits); 1708 } 1709 1710 crypto_kdone(krp); 1711 1712 /* bzero all potentially sensitive data */ 1713 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1714 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1715 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1716 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1717 1718 /* Can't free here, so put us on the free list. */ 1719 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1720 break; 1721 } 1722 case UBS_CTXOP_RSAPRIV: { 1723 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1724 u_int len; 1725 1726 krp = rp->rpr_krp; 1727 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE); 1728 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD); 1729 1730 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1731 bcopy(rp->rpr_msgout.dma_vaddr, 1732 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1733 1734 crypto_kdone(krp); 1735 1736 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1737 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1738 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1739 1740 /* Can't free here, so put us on the free list. */ 1741 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1742 break; 1743 } 1744 default: 1745 device_printf(sc->sc_dev, "unknown ctx op: %x\n", 1746 letoh16(ctx->ctx_op)); 1747 break; 1748 } 1749} 1750 1751#ifndef UBSEC_NO_RNG 1752static void 1753ubsec_rng(void *vsc) 1754{ 1755 struct ubsec_softc *sc = vsc; 1756 struct ubsec_q2_rng *rng = &sc->sc_rng; 1757 struct ubsec_mcr *mcr; 1758 struct ubsec_ctx_rngbypass *ctx; 1759 1760 UBSEC_LOCK(sc); 1761 if (rng->rng_used) { 1762 UBSEC_UNLOCK(sc); 1763 return; 1764 } 1765 sc->sc_nqueue2++; 1766 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1767 goto out; 1768 1769 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1770 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1771 1772 mcr->mcr_pkts = htole16(1); 1773 mcr->mcr_flags = 0; 1774 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1775 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1776 mcr->mcr_ipktbuf.pb_len = 0; 1777 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1778 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1779 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1780 UBS_PKTBUF_LEN); 1781 mcr->mcr_opktbuf.pb_next = 0; 1782 1783 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1784 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS); 1785 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS; 1786 1787 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD); 1788 1789 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1790 rng->rng_used = 1; 1791 ubsec_feed2(sc); 1792 ubsecstats.hst_rng++; 1793 UBSEC_UNLOCK(sc); 1794 1795 return; 1796 1797out: 1798 /* 1799 * Something weird happened, generate our own call back. 1800 */ 1801 sc->sc_nqueue2--; 1802 UBSEC_UNLOCK(sc); 1803 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1804} 1805#endif /* UBSEC_NO_RNG */ 1806 1807static void 1808ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1809{ 1810 bus_addr_t *paddr = (bus_addr_t*) arg; 1811 *paddr = segs->ds_addr; 1812} 1813 1814static int 1815ubsec_dma_malloc( 1816 struct ubsec_softc *sc, 1817 bus_size_t size, 1818 struct ubsec_dma_alloc *dma, 1819 int mapflags 1820) 1821{ 1822 int r; 1823 1824 /* XXX could specify sc_dmat as parent but that just adds overhead */ 1825 r = bus_dma_tag_create(NULL, /* parent */ 1826 1, 0, /* alignment, bounds */ 1827 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1828 BUS_SPACE_MAXADDR, /* highaddr */ 1829 NULL, NULL, /* filter, filterarg */ 1830 size, /* maxsize */ 1831 1, /* nsegments */ 1832 size, /* maxsegsize */ 1833 BUS_DMA_ALLOCNOW, /* flags */ 1834 &dma->dma_tag); 1835 if (r != 0) { 1836 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1837 "bus_dma_tag_create failed; error %u\n", r); 1838 goto fail_0; 1839 } 1840 1841 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1842 if (r != 0) { 1843 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1844 "bus_dmamap_create failed; error %u\n", r); 1845 goto fail_1; 1846 } 1847 1848 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1849 BUS_DMA_NOWAIT, &dma->dma_map); 1850 if (r != 0) { 1851 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1852 "bus_dmammem_alloc failed; size %zu, error %u\n", 1853 size, r); 1854 goto fail_2; 1855 } 1856 1857 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1858 size, 1859 ubsec_dmamap_cb, 1860 &dma->dma_paddr, 1861 mapflags | BUS_DMA_NOWAIT); 1862 if (r != 0) { 1863 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1864 "bus_dmamap_load failed; error %u\n", r); 1865 goto fail_3; 1866 } 1867 1868 dma->dma_size = size; 1869 return (0); 1870 1871fail_3: 1872 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1873fail_2: 1874 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1875fail_1: 1876 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1877 bus_dma_tag_destroy(dma->dma_tag); 1878fail_0: 1879 dma->dma_map = NULL; 1880 dma->dma_tag = NULL; 1881 return (r); 1882} 1883 1884static void 1885ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1886{ 1887 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1888 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1889 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1890 bus_dma_tag_destroy(dma->dma_tag); 1891} 1892 1893/* 1894 * Resets the board. Values in the regesters are left as is 1895 * from the reset (i.e. initial values are assigned elsewhere). 1896 */ 1897static void 1898ubsec_reset_board(struct ubsec_softc *sc) 1899{ 1900 volatile u_int32_t ctrl; 1901 1902 ctrl = READ_REG(sc, BS_CTRL); 1903 ctrl |= BS_CTRL_RESET; 1904 WRITE_REG(sc, BS_CTRL, ctrl); 1905 1906 /* 1907 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1908 */ 1909 DELAY(10); 1910} 1911 1912/* 1913 * Init Broadcom registers 1914 */ 1915static void 1916ubsec_init_board(struct ubsec_softc *sc) 1917{ 1918 u_int32_t ctrl; 1919 1920 ctrl = READ_REG(sc, BS_CTRL); 1921 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1922 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1923 1924 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) 1925 ctrl |= BS_CTRL_MCR2INT; 1926 else 1927 ctrl &= ~BS_CTRL_MCR2INT; 1928 1929 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1930 ctrl &= ~BS_CTRL_SWNORM; 1931 1932 WRITE_REG(sc, BS_CTRL, ctrl); 1933} 1934 1935/* 1936 * Init Broadcom PCI registers 1937 */ 1938static void 1939ubsec_init_pciregs(device_t dev) 1940{ 1941#if 0 1942 u_int32_t misc; 1943 1944 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT); 1945 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT)) 1946 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT); 1947 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT)) 1948 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT); 1949 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc); 1950#endif 1951 1952 /* 1953 * This will set the cache line size to 1, this will 1954 * force the BCM58xx chip just to do burst read/writes. 1955 * Cache line read/writes are to slow 1956 */ 1957 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1); 1958} 1959 1960/* 1961 * Clean up after a chip crash. 1962 * It is assumed that the caller in splimp() 1963 */ 1964static void 1965ubsec_cleanchip(struct ubsec_softc *sc) 1966{ 1967 struct ubsec_q *q; 1968 1969 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 1970 q = SIMPLEQ_FIRST(&sc->sc_qchip); 1971 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 1972 ubsec_free_q(sc, q); 1973 } 1974 sc->sc_nqchip = 0; 1975} 1976 1977/* 1978 * free a ubsec_q 1979 * It is assumed that the caller is within splimp(). 1980 */ 1981static int 1982ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 1983{ 1984 struct ubsec_q *q2; 1985 struct cryptop *crp; 1986 int npkts; 1987 int i; 1988 1989 npkts = q->q_nstacked_mcrs; 1990 1991 for (i = 0; i < npkts; i++) { 1992 if(q->q_stacked_mcr[i]) { 1993 q2 = q->q_stacked_mcr[i]; 1994 1995 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 1996 m_freem(q2->q_dst_m); 1997 1998 crp = (struct cryptop *)q2->q_crp; 1999 2000 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2001 2002 crp->crp_etype = EFAULT; 2003 crypto_done(crp); 2004 } else { 2005 break; 2006 } 2007 } 2008 2009 /* 2010 * Free header MCR 2011 */ 2012 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2013 m_freem(q->q_dst_m); 2014 2015 crp = (struct cryptop *)q->q_crp; 2016 2017 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2018 2019 crp->crp_etype = EFAULT; 2020 crypto_done(crp); 2021 return(0); 2022} 2023 2024/* 2025 * Routine to reset the chip and clean up. 2026 * It is assumed that the caller is in splimp() 2027 */ 2028static void 2029ubsec_totalreset(struct ubsec_softc *sc) 2030{ 2031 ubsec_reset_board(sc); 2032 ubsec_init_board(sc); 2033 ubsec_cleanchip(sc); 2034} 2035 2036static int 2037ubsec_dmamap_aligned(struct ubsec_operand *op) 2038{ 2039 int i; 2040 2041 for (i = 0; i < op->nsegs; i++) { 2042 if (op->segs[i].ds_addr & 3) 2043 return (0); 2044 if ((i != (op->nsegs - 1)) && 2045 (op->segs[i].ds_len & 3)) 2046 return (0); 2047 } 2048 return (1); 2049} 2050 2051static void 2052ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2053{ 2054 switch (q->q_type) { 2055 case UBS_CTXOP_MODEXP: { 2056 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2057 2058 ubsec_dma_free(sc, &me->me_q.q_mcr); 2059 ubsec_dma_free(sc, &me->me_q.q_ctx); 2060 ubsec_dma_free(sc, &me->me_M); 2061 ubsec_dma_free(sc, &me->me_E); 2062 ubsec_dma_free(sc, &me->me_C); 2063 ubsec_dma_free(sc, &me->me_epb); 2064 free(me, M_DEVBUF); 2065 break; 2066 } 2067 case UBS_CTXOP_RSAPRIV: { 2068 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2069 2070 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2071 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2072 ubsec_dma_free(sc, &rp->rpr_msgin); 2073 ubsec_dma_free(sc, &rp->rpr_msgout); 2074 free(rp, M_DEVBUF); 2075 break; 2076 } 2077 default: 2078 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type); 2079 break; 2080 } 2081} 2082 2083static int 2084ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2085{ 2086 struct ubsec_softc *sc = arg; 2087 int r; 2088 2089 if (krp == NULL || krp->krp_callback == NULL) 2090 return (EINVAL); 2091 2092 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2093 struct ubsec_q2 *q; 2094 2095 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2096 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next); 2097 ubsec_kfree(sc, q); 2098 } 2099 2100 switch (krp->krp_op) { 2101 case CRK_MOD_EXP: 2102 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2103 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2104 else 2105 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2106 break; 2107 case CRK_MOD_EXP_CRT: 2108 return (ubsec_kprocess_rsapriv(sc, krp, hint)); 2109 default: 2110 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n", 2111 krp->krp_op); 2112 krp->krp_status = EOPNOTSUPP; 2113 crypto_kdone(krp); 2114 return (0); 2115 } 2116 return (0); /* silence compiler */ 2117} 2118 2119/* 2120 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2121 */ 2122static int 2123ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2124{ 2125 struct ubsec_q2_modexp *me; 2126 struct ubsec_mcr *mcr; 2127 struct ubsec_ctx_modexp *ctx; 2128 struct ubsec_pktbuf *epb; 2129 int err = 0; 2130 u_int nbits, normbits, mbits, shiftbits, ebits; 2131 2132 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2133 if (me == NULL) { 2134 err = ENOMEM; 2135 goto errout; 2136 } 2137 bzero(me, sizeof *me); 2138 me->me_krp = krp; 2139 me->me_q.q_type = UBS_CTXOP_MODEXP; 2140 2141 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2142 if (nbits <= 512) 2143 normbits = 512; 2144 else if (nbits <= 768) 2145 normbits = 768; 2146 else if (nbits <= 1024) 2147 normbits = 1024; 2148 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2149 normbits = 1536; 2150 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2151 normbits = 2048; 2152 else { 2153 err = E2BIG; 2154 goto errout; 2155 } 2156 2157 shiftbits = normbits - nbits; 2158 2159 me->me_modbits = nbits; 2160 me->me_shiftbits = shiftbits; 2161 me->me_normbits = normbits; 2162 2163 /* Sanity check: result bits must be >= true modulus bits. */ 2164 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2165 err = ERANGE; 2166 goto errout; 2167 } 2168 2169 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2170 &me->me_q.q_mcr, 0)) { 2171 err = ENOMEM; 2172 goto errout; 2173 } 2174 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2175 2176 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2177 &me->me_q.q_ctx, 0)) { 2178 err = ENOMEM; 2179 goto errout; 2180 } 2181 2182 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2183 if (mbits > nbits) { 2184 err = E2BIG; 2185 goto errout; 2186 } 2187 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2188 err = ENOMEM; 2189 goto errout; 2190 } 2191 ubsec_kshift_r(shiftbits, 2192 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2193 me->me_M.dma_vaddr, normbits); 2194 2195 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2196 err = ENOMEM; 2197 goto errout; 2198 } 2199 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2200 2201 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2202 if (ebits > nbits) { 2203 err = E2BIG; 2204 goto errout; 2205 } 2206 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2207 err = ENOMEM; 2208 goto errout; 2209 } 2210 ubsec_kshift_r(shiftbits, 2211 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2212 me->me_E.dma_vaddr, normbits); 2213 2214 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2215 &me->me_epb, 0)) { 2216 err = ENOMEM; 2217 goto errout; 2218 } 2219 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2220 epb->pb_addr = htole32(me->me_E.dma_paddr); 2221 epb->pb_next = 0; 2222 epb->pb_len = htole32(normbits / 8); 2223 2224#ifdef UBSEC_DEBUG 2225 if (ubsec_debug) { 2226 printf("Epb "); 2227 ubsec_dump_pb(epb); 2228 } 2229#endif 2230 2231 mcr->mcr_pkts = htole16(1); 2232 mcr->mcr_flags = 0; 2233 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2234 mcr->mcr_reserved = 0; 2235 mcr->mcr_pktlen = 0; 2236 2237 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2238 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2239 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2240 2241 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2242 mcr->mcr_opktbuf.pb_next = 0; 2243 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2244 2245#ifdef DIAGNOSTIC 2246 /* Misaligned output buffer will hang the chip. */ 2247 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2248 panic("%s: modexp invalid addr 0x%x\n", 2249 device_get_nameunit(sc->sc_dev), 2250 letoh32(mcr->mcr_opktbuf.pb_addr)); 2251 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2252 panic("%s: modexp invalid len 0x%x\n", 2253 device_get_nameunit(sc->sc_dev), 2254 letoh32(mcr->mcr_opktbuf.pb_len)); 2255#endif 2256 2257 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2258 bzero(ctx, sizeof(*ctx)); 2259 ubsec_kshift_r(shiftbits, 2260 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2261 ctx->me_N, normbits); 2262 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2263 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2264 ctx->me_E_len = htole16(nbits); 2265 ctx->me_N_len = htole16(nbits); 2266 2267#ifdef UBSEC_DEBUG 2268 if (ubsec_debug) { 2269 ubsec_dump_mcr(mcr); 2270 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2271 } 2272#endif 2273 2274 /* 2275 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2276 * everything else. 2277 */ 2278 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2279 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2280 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2281 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2282 2283 /* Enqueue and we're done... */ 2284 UBSEC_LOCK(sc); 2285 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2286 ubsec_feed2(sc); 2287 ubsecstats.hst_modexp++; 2288 UBSEC_UNLOCK(sc); 2289 2290 return (0); 2291 2292errout: 2293 if (me != NULL) { 2294 if (me->me_q.q_mcr.dma_map != NULL) 2295 ubsec_dma_free(sc, &me->me_q.q_mcr); 2296 if (me->me_q.q_ctx.dma_map != NULL) { 2297 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2298 ubsec_dma_free(sc, &me->me_q.q_ctx); 2299 } 2300 if (me->me_M.dma_map != NULL) { 2301 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2302 ubsec_dma_free(sc, &me->me_M); 2303 } 2304 if (me->me_E.dma_map != NULL) { 2305 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2306 ubsec_dma_free(sc, &me->me_E); 2307 } 2308 if (me->me_C.dma_map != NULL) { 2309 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2310 ubsec_dma_free(sc, &me->me_C); 2311 } 2312 if (me->me_epb.dma_map != NULL) 2313 ubsec_dma_free(sc, &me->me_epb); 2314 free(me, M_DEVBUF); 2315 } 2316 krp->krp_status = err; 2317 crypto_kdone(krp); 2318 return (0); 2319} 2320 2321/* 2322 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2323 */ 2324static int 2325ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2326{ 2327 struct ubsec_q2_modexp *me; 2328 struct ubsec_mcr *mcr; 2329 struct ubsec_ctx_modexp *ctx; 2330 struct ubsec_pktbuf *epb; 2331 int err = 0; 2332 u_int nbits, normbits, mbits, shiftbits, ebits; 2333 2334 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2335 if (me == NULL) { 2336 err = ENOMEM; 2337 goto errout; 2338 } 2339 bzero(me, sizeof *me); 2340 me->me_krp = krp; 2341 me->me_q.q_type = UBS_CTXOP_MODEXP; 2342 2343 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2344 if (nbits <= 512) 2345 normbits = 512; 2346 else if (nbits <= 768) 2347 normbits = 768; 2348 else if (nbits <= 1024) 2349 normbits = 1024; 2350 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2351 normbits = 1536; 2352 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2353 normbits = 2048; 2354 else { 2355 err = E2BIG; 2356 goto errout; 2357 } 2358 2359 shiftbits = normbits - nbits; 2360 2361 /* XXX ??? */ 2362 me->me_modbits = nbits; 2363 me->me_shiftbits = shiftbits; 2364 me->me_normbits = normbits; 2365 2366 /* Sanity check: result bits must be >= true modulus bits. */ 2367 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2368 err = ERANGE; 2369 goto errout; 2370 } 2371 2372 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2373 &me->me_q.q_mcr, 0)) { 2374 err = ENOMEM; 2375 goto errout; 2376 } 2377 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2378 2379 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2380 &me->me_q.q_ctx, 0)) { 2381 err = ENOMEM; 2382 goto errout; 2383 } 2384 2385 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2386 if (mbits > nbits) { 2387 err = E2BIG; 2388 goto errout; 2389 } 2390 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2391 err = ENOMEM; 2392 goto errout; 2393 } 2394 bzero(me->me_M.dma_vaddr, normbits / 8); 2395 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2396 me->me_M.dma_vaddr, (mbits + 7) / 8); 2397 2398 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2399 err = ENOMEM; 2400 goto errout; 2401 } 2402 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2403 2404 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2405 if (ebits > nbits) { 2406 err = E2BIG; 2407 goto errout; 2408 } 2409 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2410 err = ENOMEM; 2411 goto errout; 2412 } 2413 bzero(me->me_E.dma_vaddr, normbits / 8); 2414 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2415 me->me_E.dma_vaddr, (ebits + 7) / 8); 2416 2417 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2418 &me->me_epb, 0)) { 2419 err = ENOMEM; 2420 goto errout; 2421 } 2422 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2423 epb->pb_addr = htole32(me->me_E.dma_paddr); 2424 epb->pb_next = 0; 2425 epb->pb_len = htole32((ebits + 7) / 8); 2426 2427#ifdef UBSEC_DEBUG 2428 if (ubsec_debug) { 2429 printf("Epb "); 2430 ubsec_dump_pb(epb); 2431 } 2432#endif 2433 2434 mcr->mcr_pkts = htole16(1); 2435 mcr->mcr_flags = 0; 2436 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2437 mcr->mcr_reserved = 0; 2438 mcr->mcr_pktlen = 0; 2439 2440 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2441 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2442 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2443 2444 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2445 mcr->mcr_opktbuf.pb_next = 0; 2446 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2447 2448#ifdef DIAGNOSTIC 2449 /* Misaligned output buffer will hang the chip. */ 2450 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2451 panic("%s: modexp invalid addr 0x%x\n", 2452 device_get_nameunit(sc->sc_dev), 2453 letoh32(mcr->mcr_opktbuf.pb_addr)); 2454 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2455 panic("%s: modexp invalid len 0x%x\n", 2456 device_get_nameunit(sc->sc_dev), 2457 letoh32(mcr->mcr_opktbuf.pb_len)); 2458#endif 2459 2460 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2461 bzero(ctx, sizeof(*ctx)); 2462 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2463 (nbits + 7) / 8); 2464 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2465 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2466 ctx->me_E_len = htole16(ebits); 2467 ctx->me_N_len = htole16(nbits); 2468 2469#ifdef UBSEC_DEBUG 2470 if (ubsec_debug) { 2471 ubsec_dump_mcr(mcr); 2472 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2473 } 2474#endif 2475 2476 /* 2477 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2478 * everything else. 2479 */ 2480 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2481 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2482 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2483 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2484 2485 /* Enqueue and we're done... */ 2486 UBSEC_LOCK(sc); 2487 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2488 ubsec_feed2(sc); 2489 UBSEC_UNLOCK(sc); 2490 2491 return (0); 2492 2493errout: 2494 if (me != NULL) { 2495 if (me->me_q.q_mcr.dma_map != NULL) 2496 ubsec_dma_free(sc, &me->me_q.q_mcr); 2497 if (me->me_q.q_ctx.dma_map != NULL) { 2498 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2499 ubsec_dma_free(sc, &me->me_q.q_ctx); 2500 } 2501 if (me->me_M.dma_map != NULL) { 2502 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2503 ubsec_dma_free(sc, &me->me_M); 2504 } 2505 if (me->me_E.dma_map != NULL) { 2506 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2507 ubsec_dma_free(sc, &me->me_E); 2508 } 2509 if (me->me_C.dma_map != NULL) { 2510 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2511 ubsec_dma_free(sc, &me->me_C); 2512 } 2513 if (me->me_epb.dma_map != NULL) 2514 ubsec_dma_free(sc, &me->me_epb); 2515 free(me, M_DEVBUF); 2516 } 2517 krp->krp_status = err; 2518 crypto_kdone(krp); 2519 return (0); 2520} 2521 2522static int 2523ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2524{ 2525 struct ubsec_q2_rsapriv *rp = NULL; 2526 struct ubsec_mcr *mcr; 2527 struct ubsec_ctx_rsapriv *ctx; 2528 int err = 0; 2529 u_int padlen, msglen; 2530 2531 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2532 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2533 if (msglen > padlen) 2534 padlen = msglen; 2535 2536 if (padlen <= 256) 2537 padlen = 256; 2538 else if (padlen <= 384) 2539 padlen = 384; 2540 else if (padlen <= 512) 2541 padlen = 512; 2542 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2543 padlen = 768; 2544 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2545 padlen = 1024; 2546 else { 2547 err = E2BIG; 2548 goto errout; 2549 } 2550 2551 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2552 err = E2BIG; 2553 goto errout; 2554 } 2555 2556 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2557 err = E2BIG; 2558 goto errout; 2559 } 2560 2561 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2562 err = E2BIG; 2563 goto errout; 2564 } 2565 2566 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT); 2567 if (rp == NULL) 2568 return (ENOMEM); 2569 bzero(rp, sizeof *rp); 2570 rp->rpr_krp = krp; 2571 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2572 2573 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2574 &rp->rpr_q.q_mcr, 0)) { 2575 err = ENOMEM; 2576 goto errout; 2577 } 2578 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2579 2580 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2581 &rp->rpr_q.q_ctx, 0)) { 2582 err = ENOMEM; 2583 goto errout; 2584 } 2585 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2586 bzero(ctx, sizeof *ctx); 2587 2588 /* Copy in p */ 2589 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2590 &ctx->rpr_buf[0 * (padlen / 8)], 2591 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2592 2593 /* Copy in q */ 2594 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2595 &ctx->rpr_buf[1 * (padlen / 8)], 2596 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2597 2598 /* Copy in dp */ 2599 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2600 &ctx->rpr_buf[2 * (padlen / 8)], 2601 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2602 2603 /* Copy in dq */ 2604 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2605 &ctx->rpr_buf[3 * (padlen / 8)], 2606 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2607 2608 /* Copy in pinv */ 2609 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2610 &ctx->rpr_buf[4 * (padlen / 8)], 2611 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2612 2613 msglen = padlen * 2; 2614 2615 /* Copy in input message (aligned buffer/length). */ 2616 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2617 /* Is this likely? */ 2618 err = E2BIG; 2619 goto errout; 2620 } 2621 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2622 err = ENOMEM; 2623 goto errout; 2624 } 2625 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2626 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2627 rp->rpr_msgin.dma_vaddr, 2628 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2629 2630 /* Prepare space for output message (aligned buffer/length). */ 2631 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2632 /* Is this likely? */ 2633 err = E2BIG; 2634 goto errout; 2635 } 2636 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2637 err = ENOMEM; 2638 goto errout; 2639 } 2640 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2641 2642 mcr->mcr_pkts = htole16(1); 2643 mcr->mcr_flags = 0; 2644 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2645 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2646 mcr->mcr_ipktbuf.pb_next = 0; 2647 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2648 mcr->mcr_reserved = 0; 2649 mcr->mcr_pktlen = htole16(msglen); 2650 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2651 mcr->mcr_opktbuf.pb_next = 0; 2652 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2653 2654#ifdef DIAGNOSTIC 2655 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2656 panic("%s: rsapriv: invalid msgin %x(0x%jx)", 2657 device_get_nameunit(sc->sc_dev), 2658 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size); 2659 } 2660 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2661 panic("%s: rsapriv: invalid msgout %x(0x%jx)", 2662 device_get_nameunit(sc->sc_dev), 2663 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size); 2664 } 2665#endif 2666 2667 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2668 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2669 ctx->rpr_q_len = htole16(padlen); 2670 ctx->rpr_p_len = htole16(padlen); 2671 2672 /* 2673 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2674 * everything else. 2675 */ 2676 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE); 2677 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD); 2678 2679 /* Enqueue and we're done... */ 2680 UBSEC_LOCK(sc); 2681 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2682 ubsec_feed2(sc); 2683 ubsecstats.hst_modexpcrt++; 2684 UBSEC_UNLOCK(sc); 2685 return (0); 2686 2687errout: 2688 if (rp != NULL) { 2689 if (rp->rpr_q.q_mcr.dma_map != NULL) 2690 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2691 if (rp->rpr_msgin.dma_map != NULL) { 2692 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2693 ubsec_dma_free(sc, &rp->rpr_msgin); 2694 } 2695 if (rp->rpr_msgout.dma_map != NULL) { 2696 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2697 ubsec_dma_free(sc, &rp->rpr_msgout); 2698 } 2699 free(rp, M_DEVBUF); 2700 } 2701 krp->krp_status = err; 2702 crypto_kdone(krp); 2703 return (0); 2704} 2705 2706#ifdef UBSEC_DEBUG 2707static void 2708ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2709{ 2710 printf("addr 0x%x (0x%x) next 0x%x\n", 2711 pb->pb_addr, pb->pb_len, pb->pb_next); 2712} 2713 2714static void 2715ubsec_dump_ctx2(struct ubsec_ctx_keyop *c) 2716{ 2717 printf("CTX (0x%x):\n", c->ctx_len); 2718 switch (letoh16(c->ctx_op)) { 2719 case UBS_CTXOP_RNGBYPASS: 2720 case UBS_CTXOP_RNGSHA1: 2721 break; 2722 case UBS_CTXOP_MODEXP: 2723 { 2724 struct ubsec_ctx_modexp *cx = (void *)c; 2725 int i, len; 2726 2727 printf(" Elen %u, Nlen %u\n", 2728 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2729 len = (cx->me_N_len + 7)/8; 2730 for (i = 0; i < len; i++) 2731 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2732 printf("\n"); 2733 break; 2734 } 2735 default: 2736 printf("unknown context: %x\n", c->ctx_op); 2737 } 2738 printf("END CTX\n"); 2739} 2740 2741static void 2742ubsec_dump_mcr(struct ubsec_mcr *mcr) 2743{ 2744 volatile struct ubsec_mcr_add *ma; 2745 int i; 2746 2747 printf("MCR:\n"); 2748 printf(" pkts: %u, flags 0x%x\n", 2749 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2750 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2751 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2752 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2753 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2754 letoh16(ma->mcr_reserved)); 2755 printf(" %d: ipkt ", i); 2756 ubsec_dump_pb(&ma->mcr_ipktbuf); 2757 printf(" %d: opkt ", i); 2758 ubsec_dump_pb(&ma->mcr_opktbuf); 2759 ma++; 2760 } 2761 printf("END MCR\n"); 2762} 2763#endif /* UBSEC_DEBUG */ 2764 2765/* 2766 * Return the number of significant bits of a big number. 2767 */ 2768static int 2769ubsec_ksigbits(struct crparam *cr) 2770{ 2771 u_int plen = (cr->crp_nbits + 7) / 8; 2772 int i, sig = plen * 8; 2773 u_int8_t c, *p = cr->crp_p; 2774 2775 for (i = plen - 1; i >= 0; i--) { 2776 c = p[i]; 2777 if (c != 0) { 2778 while ((c & 0x80) == 0) { 2779 sig--; 2780 c <<= 1; 2781 } 2782 break; 2783 } 2784 sig -= 8; 2785 } 2786 return (sig); 2787} 2788 2789static void 2790ubsec_kshift_r( 2791 u_int shiftbits, 2792 u_int8_t *src, u_int srcbits, 2793 u_int8_t *dst, u_int dstbits) 2794{ 2795 u_int slen, dlen; 2796 int i, si, di, n; 2797 2798 slen = (srcbits + 7) / 8; 2799 dlen = (dstbits + 7) / 8; 2800 2801 for (i = 0; i < slen; i++) 2802 dst[i] = src[i]; 2803 for (i = 0; i < dlen - slen; i++) 2804 dst[slen + i] = 0; 2805 2806 n = shiftbits / 8; 2807 if (n != 0) { 2808 si = dlen - n - 1; 2809 di = dlen - 1; 2810 while (si >= 0) 2811 dst[di--] = dst[si--]; 2812 while (di >= 0) 2813 dst[di--] = 0; 2814 } 2815 2816 n = shiftbits % 8; 2817 if (n != 0) { 2818 for (i = dlen - 1; i > 0; i--) 2819 dst[i] = (dst[i] << n) | 2820 (dst[i - 1] >> (8 - n)); 2821 dst[0] = dst[0] << n; 2822 } 2823} 2824 2825static void 2826ubsec_kshift_l( 2827 u_int shiftbits, 2828 u_int8_t *src, u_int srcbits, 2829 u_int8_t *dst, u_int dstbits) 2830{ 2831 int slen, dlen, i, n; 2832 2833 slen = (srcbits + 7) / 8; 2834 dlen = (dstbits + 7) / 8; 2835 2836 n = shiftbits / 8; 2837 for (i = 0; i < slen; i++) 2838 dst[i] = src[i + n]; 2839 for (i = 0; i < dlen - slen; i++) 2840 dst[slen + i] = 0; 2841 2842 n = shiftbits % 8; 2843 if (n != 0) { 2844 for (i = 0; i < (dlen - 1); i++) 2845 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2846 dst[dlen - 1] = dst[dlen - 1] >> n; 2847 } 2848} 2849