ubsec.c revision 159232
1/* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */ 2 3/*- 4 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 5 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 6 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Jason L. Wright 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Effort sponsored in part by the Defense Advanced Research Projects 37 * Agency (DARPA) and Air Force Research Laboratory, Air Force 38 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/dev/ubsec/ubsec.c 159232 2006-06-04 14:49:34Z pjd $"); 43 44/* 45 * uBsec 5[56]01, 58xx hardware crypto accelerator 46 */ 47 48#include "opt_ubsec.h" 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/proc.h> 53#include <sys/errno.h> 54#include <sys/malloc.h> 55#include <sys/kernel.h> 56#include <sys/module.h> 57#include <sys/mbuf.h> 58#include <sys/lock.h> 59#include <sys/mutex.h> 60#include <sys/sysctl.h> 61#include <sys/endian.h> 62 63#include <vm/vm.h> 64#include <vm/pmap.h> 65 66#include <machine/bus.h> 67#include <machine/resource.h> 68#include <sys/bus.h> 69#include <sys/rman.h> 70 71#include <crypto/sha1.h> 72#include <opencrypto/cryptodev.h> 73#include <opencrypto/cryptosoft.h> 74#include <sys/md5.h> 75#include <sys/random.h> 76 77#include <dev/pci/pcivar.h> 78#include <dev/pci/pcireg.h> 79 80/* grr, #defines for gratuitous incompatibility in queue.h */ 81#define SIMPLEQ_HEAD STAILQ_HEAD 82#define SIMPLEQ_ENTRY STAILQ_ENTRY 83#define SIMPLEQ_INIT STAILQ_INIT 84#define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL 85#define SIMPLEQ_EMPTY STAILQ_EMPTY 86#define SIMPLEQ_FIRST STAILQ_FIRST 87#define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD_UNTIL 88#define SIMPLEQ_FOREACH STAILQ_FOREACH 89/* ditto for endian.h */ 90#define letoh16(x) le16toh(x) 91#define letoh32(x) le32toh(x) 92 93#ifdef UBSEC_RNDTEST 94#include <dev/rndtest/rndtest.h> 95#endif 96#include <dev/ubsec/ubsecreg.h> 97#include <dev/ubsec/ubsecvar.h> 98 99/* 100 * Prototypes and count for the pci_device structure 101 */ 102static int ubsec_probe(device_t); 103static int ubsec_attach(device_t); 104static int ubsec_detach(device_t); 105static int ubsec_suspend(device_t); 106static int ubsec_resume(device_t); 107static void ubsec_shutdown(device_t); 108 109static device_method_t ubsec_methods[] = { 110 /* Device interface */ 111 DEVMETHOD(device_probe, ubsec_probe), 112 DEVMETHOD(device_attach, ubsec_attach), 113 DEVMETHOD(device_detach, ubsec_detach), 114 DEVMETHOD(device_suspend, ubsec_suspend), 115 DEVMETHOD(device_resume, ubsec_resume), 116 DEVMETHOD(device_shutdown, ubsec_shutdown), 117 118 /* bus interface */ 119 DEVMETHOD(bus_print_child, bus_generic_print_child), 120 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 121 122 { 0, 0 } 123}; 124static driver_t ubsec_driver = { 125 "ubsec", 126 ubsec_methods, 127 sizeof (struct ubsec_softc) 128}; 129static devclass_t ubsec_devclass; 130 131DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0); 132MODULE_DEPEND(ubsec, crypto, 1, 1, 1); 133#ifdef UBSEC_RNDTEST 134MODULE_DEPEND(ubsec, rndtest, 1, 1, 1); 135#endif 136 137static void ubsec_intr(void *); 138static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *); 139static int ubsec_freesession(void *, u_int64_t); 140static int ubsec_process(void *, struct cryptop *, int); 141static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 142static void ubsec_feed(struct ubsec_softc *); 143static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 144static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 145static int ubsec_feed2(struct ubsec_softc *); 146static void ubsec_rng(void *); 147static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 148 struct ubsec_dma_alloc *, int); 149#define ubsec_dma_sync(_dma, _flags) \ 150 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 151static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 152static int ubsec_dmamap_aligned(struct ubsec_operand *op); 153 154static void ubsec_reset_board(struct ubsec_softc *sc); 155static void ubsec_init_board(struct ubsec_softc *sc); 156static void ubsec_init_pciregs(device_t dev); 157static void ubsec_totalreset(struct ubsec_softc *sc); 158 159static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q); 160 161static int ubsec_kprocess(void*, struct cryptkop *, int); 162static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int); 163static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int); 164static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int); 165static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 166static int ubsec_ksigbits(struct crparam *); 167static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 168static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 169 170SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters"); 171 172#ifdef UBSEC_DEBUG 173static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 174static void ubsec_dump_mcr(struct ubsec_mcr *); 175static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *); 176 177static int ubsec_debug = 0; 178SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug, 179 0, "control debugging msgs"); 180#endif 181 182#define READ_REG(sc,r) \ 183 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 184 185#define WRITE_REG(sc,reg,val) \ 186 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 187 188#define SWAP32(x) (x) = htole32(ntohl((x))) 189#define HTOLE32(x) (x) = htole32(x) 190 191struct ubsec_stats ubsecstats; 192SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats, 193 ubsec_stats, "driver statistics"); 194 195static int 196ubsec_probe(device_t dev) 197{ 198 if (pci_get_vendor(dev) == PCI_VENDOR_SUN && 199 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 || 200 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K)) 201 return (BUS_PROBE_DEFAULT); 202 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 203 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 || 204 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)) 205 return (BUS_PROBE_DEFAULT); 206 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 207 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 || 208 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 209 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 || 210 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 || 211 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 212 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 213 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 214 )) 215 return (BUS_PROBE_DEFAULT); 216 return (ENXIO); 217} 218 219static const char* 220ubsec_partname(struct ubsec_softc *sc) 221{ 222 /* XXX sprintf numbers when not decoded */ 223 switch (pci_get_vendor(sc->sc_dev)) { 224 case PCI_VENDOR_BROADCOM: 225 switch (pci_get_device(sc->sc_dev)) { 226 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801"; 227 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802"; 228 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805"; 229 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820"; 230 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821"; 231 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822"; 232 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823"; 233 } 234 return "Broadcom unknown-part"; 235 case PCI_VENDOR_BLUESTEEL: 236 switch (pci_get_device(sc->sc_dev)) { 237 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601"; 238 } 239 return "Bluesteel unknown-part"; 240 case PCI_VENDOR_SUN: 241 switch (pci_get_device(sc->sc_dev)) { 242 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821"; 243 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K"; 244 } 245 return "Sun unknown-part"; 246 } 247 return "Unknown-vendor unknown-part"; 248} 249 250static void 251default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 252{ 253 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 254} 255 256static int 257ubsec_attach(device_t dev) 258{ 259 struct ubsec_softc *sc = device_get_softc(dev); 260 struct ubsec_dma *dmap; 261 u_int32_t cmd, i; 262 int rid; 263 264 bzero(sc, sizeof (*sc)); 265 sc->sc_dev = dev; 266 267 SIMPLEQ_INIT(&sc->sc_queue); 268 SIMPLEQ_INIT(&sc->sc_qchip); 269 SIMPLEQ_INIT(&sc->sc_queue2); 270 SIMPLEQ_INIT(&sc->sc_qchip2); 271 SIMPLEQ_INIT(&sc->sc_q2free); 272 273 /* XXX handle power management */ 274 275 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; 276 277 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 278 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601) 279 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 280 281 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 282 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 283 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805)) 284 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 285 286 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 287 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820) 288 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 289 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 290 291 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 292 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 293 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 294 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) || 295 (pci_get_vendor(dev) == PCI_VENDOR_SUN && 296 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K || 297 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) { 298 /* NB: the 5821/5822 defines some additional status bits */ 299 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY | 300 BS_STAT_MCR2_ALLEMPTY; 301 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 302 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 303 } 304 305 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 306 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 307 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 308 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 309 310 if (!(cmd & PCIM_CMD_MEMEN)) { 311 device_printf(dev, "failed to enable memory mapping\n"); 312 goto bad; 313 } 314 315 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 316 device_printf(dev, "failed to enable bus mastering\n"); 317 goto bad; 318 } 319 320 /* 321 * Setup memory-mapping of PCI registers. 322 */ 323 rid = BS_BAR; 324 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 325 RF_ACTIVE); 326 if (sc->sc_sr == NULL) { 327 device_printf(dev, "cannot map register space\n"); 328 goto bad; 329 } 330 sc->sc_st = rman_get_bustag(sc->sc_sr); 331 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 332 333 /* 334 * Arrange interrupt line. 335 */ 336 rid = 0; 337 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 338 RF_SHAREABLE|RF_ACTIVE); 339 if (sc->sc_irq == NULL) { 340 device_printf(dev, "could not map interrupt\n"); 341 goto bad1; 342 } 343 /* 344 * NB: Network code assumes we are blocked with splimp() 345 * so make sure the IRQ is mapped appropriately. 346 */ 347 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 348 ubsec_intr, sc, &sc->sc_ih)) { 349 device_printf(dev, "could not establish interrupt\n"); 350 goto bad2; 351 } 352 353 sc->sc_cid = crypto_get_driverid(0); 354 if (sc->sc_cid < 0) { 355 device_printf(dev, "could not get crypto driver id\n"); 356 goto bad3; 357 } 358 359 /* 360 * Setup DMA descriptor area. 361 */ 362 if (bus_dma_tag_create(NULL, /* parent */ 363 1, 0, /* alignment, bounds */ 364 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 365 BUS_SPACE_MAXADDR, /* highaddr */ 366 NULL, NULL, /* filter, filterarg */ 367 0x3ffff, /* maxsize */ 368 UBS_MAX_SCATTER, /* nsegments */ 369 0xffff, /* maxsegsize */ 370 BUS_DMA_ALLOCNOW, /* flags */ 371 NULL, NULL, /* lockfunc, lockarg */ 372 &sc->sc_dmat)) { 373 device_printf(dev, "cannot allocate DMA tag\n"); 374 goto bad4; 375 } 376 SIMPLEQ_INIT(&sc->sc_freequeue); 377 dmap = sc->sc_dmaa; 378 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 379 struct ubsec_q *q; 380 381 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 382 M_DEVBUF, M_NOWAIT); 383 if (q == NULL) { 384 device_printf(dev, "cannot allocate queue buffers\n"); 385 break; 386 } 387 388 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 389 &dmap->d_alloc, 0)) { 390 device_printf(dev, "cannot allocate dma buffers\n"); 391 free(q, M_DEVBUF); 392 break; 393 } 394 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 395 396 q->q_dma = dmap; 397 sc->sc_queuea[i] = q; 398 399 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 400 } 401 mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev), 402 "mcr1 operations", MTX_DEF); 403 mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev), 404 "mcr1 free q", MTX_DEF); 405 406 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc)); 407 408 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 409 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 410 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 411 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 412 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 413 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 414 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 415 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 416 417 /* 418 * Reset Broadcom chip 419 */ 420 ubsec_reset_board(sc); 421 422 /* 423 * Init Broadcom specific PCI settings 424 */ 425 ubsec_init_pciregs(dev); 426 427 /* 428 * Init Broadcom chip 429 */ 430 ubsec_init_board(sc); 431 432#ifndef UBSEC_NO_RNG 433 if (sc->sc_flags & UBS_FLAGS_RNG) { 434 sc->sc_statmask |= BS_STAT_MCR2_DONE; 435#ifdef UBSEC_RNDTEST 436 sc->sc_rndtest = rndtest_attach(dev); 437 if (sc->sc_rndtest) 438 sc->sc_harvest = rndtest_harvest; 439 else 440 sc->sc_harvest = default_harvest; 441#else 442 sc->sc_harvest = default_harvest; 443#endif 444 445 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 446 &sc->sc_rng.rng_q.q_mcr, 0)) 447 goto skip_rng; 448 449 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 450 &sc->sc_rng.rng_q.q_ctx, 0)) { 451 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 452 goto skip_rng; 453 } 454 455 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 456 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 457 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 458 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 459 goto skip_rng; 460 } 461 462 if (hz >= 100) 463 sc->sc_rnghz = hz / 100; 464 else 465 sc->sc_rnghz = 1; 466 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 467 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 468skip_rng: 469 ; 470 } 471#endif /* UBSEC_NO_RNG */ 472 mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev), 473 "mcr2 operations", MTX_DEF); 474 475 if (sc->sc_flags & UBS_FLAGS_KEY) { 476 sc->sc_statmask |= BS_STAT_MCR2_DONE; 477 478 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 479 ubsec_kprocess, sc); 480#if 0 481 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 482 ubsec_kprocess, sc); 483#endif 484 } 485 return (0); 486bad4: 487 crypto_unregister_all(sc->sc_cid); 488bad3: 489 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 490bad2: 491 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 492bad1: 493 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 494bad: 495 return (ENXIO); 496} 497 498/* 499 * Detach a device that successfully probed. 500 */ 501static int 502ubsec_detach(device_t dev) 503{ 504 struct ubsec_softc *sc = device_get_softc(dev); 505 506 /* XXX wait/abort active ops */ 507 508 /* disable interrupts */ 509 WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~ 510 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR)); 511 512 callout_stop(&sc->sc_rngto); 513 514 crypto_unregister_all(sc->sc_cid); 515 516#ifdef UBSEC_RNDTEST 517 if (sc->sc_rndtest) 518 rndtest_detach(sc->sc_rndtest); 519#endif 520 521 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 522 struct ubsec_q *q; 523 524 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 525 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 526 ubsec_dma_free(sc, &q->q_dma->d_alloc); 527 free(q, M_DEVBUF); 528 } 529 mtx_destroy(&sc->sc_mcr1lock); 530 mtx_destroy(&sc->sc_freeqlock); 531#ifndef UBSEC_NO_RNG 532 if (sc->sc_flags & UBS_FLAGS_RNG) { 533 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 534 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 535 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 536 } 537#endif /* UBSEC_NO_RNG */ 538 mtx_destroy(&sc->sc_mcr2lock); 539 540 bus_generic_detach(dev); 541 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 542 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 543 544 bus_dma_tag_destroy(sc->sc_dmat); 545 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 546 547 return (0); 548} 549 550/* 551 * Stop all chip i/o so that the kernel's probe routines don't 552 * get confused by errant DMAs when rebooting. 553 */ 554static void 555ubsec_shutdown(device_t dev) 556{ 557#ifdef notyet 558 ubsec_stop(device_get_softc(dev)); 559#endif 560} 561 562/* 563 * Device suspend routine. 564 */ 565static int 566ubsec_suspend(device_t dev) 567{ 568 struct ubsec_softc *sc = device_get_softc(dev); 569 570#ifdef notyet 571 /* XXX stop the device and save PCI settings */ 572#endif 573 sc->sc_suspended = 1; 574 575 return (0); 576} 577 578static int 579ubsec_resume(device_t dev) 580{ 581 struct ubsec_softc *sc = device_get_softc(dev); 582 583#ifdef notyet 584 /* XXX retore PCI settings and start the device */ 585#endif 586 sc->sc_suspended = 0; 587 return (0); 588} 589 590/* 591 * UBSEC Interrupt routine 592 */ 593static void 594ubsec_intr(void *arg) 595{ 596 struct ubsec_softc *sc = arg; 597 volatile u_int32_t stat; 598 struct ubsec_q *q; 599 struct ubsec_dma *dmap; 600 int npkts = 0, i; 601 602 stat = READ_REG(sc, BS_STAT); 603 stat &= sc->sc_statmask; 604 if (stat == 0) 605 return; 606 607 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 608 609 /* 610 * Check to see if we have any packets waiting for us 611 */ 612 if ((stat & BS_STAT_MCR1_DONE)) { 613 mtx_lock(&sc->sc_mcr1lock); 614 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 615 q = SIMPLEQ_FIRST(&sc->sc_qchip); 616 dmap = q->q_dma; 617 618 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 619 break; 620 621 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 622 623 npkts = q->q_nstacked_mcrs; 624 sc->sc_nqchip -= 1+npkts; 625 /* 626 * search for further sc_qchip ubsec_q's that share 627 * the same MCR, and complete them too, they must be 628 * at the top. 629 */ 630 for (i = 0; i < npkts; i++) { 631 if(q->q_stacked_mcr[i]) { 632 ubsec_callback(sc, q->q_stacked_mcr[i]); 633 } else { 634 break; 635 } 636 } 637 ubsec_callback(sc, q); 638 } 639 /* 640 * Don't send any more packet to chip if there has been 641 * a DMAERR. 642 */ 643 if (!(stat & BS_STAT_DMAERR)) 644 ubsec_feed(sc); 645 mtx_unlock(&sc->sc_mcr1lock); 646 } 647 648 /* 649 * Check to see if we have any key setups/rng's waiting for us 650 */ 651 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 652 (stat & BS_STAT_MCR2_DONE)) { 653 struct ubsec_q2 *q2; 654 struct ubsec_mcr *mcr; 655 656 mtx_lock(&sc->sc_mcr2lock); 657 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 658 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 659 660 ubsec_dma_sync(&q2->q_mcr, 661 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 662 663 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 664 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 665 ubsec_dma_sync(&q2->q_mcr, 666 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 667 break; 668 } 669 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next); 670 ubsec_callback2(sc, q2); 671 /* 672 * Don't send any more packet to chip if there has been 673 * a DMAERR. 674 */ 675 if (!(stat & BS_STAT_DMAERR)) 676 ubsec_feed2(sc); 677 } 678 mtx_unlock(&sc->sc_mcr2lock); 679 } 680 681 /* 682 * Check to see if we got any DMA Error 683 */ 684 if (stat & BS_STAT_DMAERR) { 685#ifdef UBSEC_DEBUG 686 if (ubsec_debug) { 687 volatile u_int32_t a = READ_REG(sc, BS_ERR); 688 689 printf("dmaerr %s@%08x\n", 690 (a & BS_ERR_READ) ? "read" : "write", 691 a & BS_ERR_ADDR); 692 } 693#endif /* UBSEC_DEBUG */ 694 ubsecstats.hst_dmaerr++; 695 mtx_lock(&sc->sc_mcr1lock); 696 ubsec_totalreset(sc); 697 ubsec_feed(sc); 698 mtx_unlock(&sc->sc_mcr1lock); 699 } 700 701 if (sc->sc_needwakeup) { /* XXX check high watermark */ 702 int wakeup; 703 704 mtx_lock(&sc->sc_freeqlock); 705 wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 706#ifdef UBSEC_DEBUG 707 if (ubsec_debug) 708 device_printf(sc->sc_dev, "wakeup crypto (%x)\n", 709 sc->sc_needwakeup); 710#endif /* UBSEC_DEBUG */ 711 sc->sc_needwakeup &= ~wakeup; 712 mtx_unlock(&sc->sc_freeqlock); 713 crypto_unblock(sc->sc_cid, wakeup); 714 } 715} 716 717/* 718 * ubsec_feed() - aggregate and post requests to chip 719 */ 720static void 721ubsec_feed(struct ubsec_softc *sc) 722{ 723 struct ubsec_q *q, *q2; 724 int npkts, i; 725 void *v; 726 u_int32_t stat; 727 728 /* 729 * Decide how many ops to combine in a single MCR. We cannot 730 * aggregate more than UBS_MAX_AGGR because this is the number 731 * of slots defined in the data structure. Note that 732 * aggregation only happens if ops are marked batch'able. 733 * Aggregating ops reduces the number of interrupts to the host 734 * but also (potentially) increases the latency for processing 735 * completed ops as we only get an interrupt when all aggregated 736 * ops have completed. 737 */ 738 if (sc->sc_nqueue == 0) 739 return; 740 if (sc->sc_nqueue > 1) { 741 npkts = 0; 742 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) { 743 npkts++; 744 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0) 745 break; 746 } 747 } else 748 npkts = 1; 749 /* 750 * Check device status before going any further. 751 */ 752 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 753 if (stat & BS_STAT_DMAERR) { 754 ubsec_totalreset(sc); 755 ubsecstats.hst_dmaerr++; 756 } else 757 ubsecstats.hst_mcr1full++; 758 return; 759 } 760 if (sc->sc_nqueue > ubsecstats.hst_maxqueue) 761 ubsecstats.hst_maxqueue = sc->sc_nqueue; 762 if (npkts > UBS_MAX_AGGR) 763 npkts = UBS_MAX_AGGR; 764 if (npkts < 2) /* special case 1 op */ 765 goto feed1; 766 767 ubsecstats.hst_totbatch += npkts-1; 768#ifdef UBSEC_DEBUG 769 if (ubsec_debug) 770 printf("merging %d records\n", npkts); 771#endif /* UBSEC_DEBUG */ 772 773 q = SIMPLEQ_FIRST(&sc->sc_queue); 774 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 775 --sc->sc_nqueue; 776 777 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 778 if (q->q_dst_map != NULL) 779 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 780 781 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 782 783 for (i = 0; i < q->q_nstacked_mcrs; i++) { 784 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 785 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 786 BUS_DMASYNC_PREWRITE); 787 if (q2->q_dst_map != NULL) 788 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 789 BUS_DMASYNC_PREREAD); 790 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next); 791 --sc->sc_nqueue; 792 793 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - 794 sizeof(struct ubsec_mcr_add)); 795 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 796 q->q_stacked_mcr[i] = q2; 797 } 798 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 799 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 800 sc->sc_nqchip += npkts; 801 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 802 ubsecstats.hst_maxqchip = sc->sc_nqchip; 803 ubsec_dma_sync(&q->q_dma->d_alloc, 804 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 805 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 806 offsetof(struct ubsec_dmachunk, d_mcr)); 807 return; 808feed1: 809 q = SIMPLEQ_FIRST(&sc->sc_queue); 810 811 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 812 if (q->q_dst_map != NULL) 813 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 814 ubsec_dma_sync(&q->q_dma->d_alloc, 815 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 816 817 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 818 offsetof(struct ubsec_dmachunk, d_mcr)); 819#ifdef UBSEC_DEBUG 820 if (ubsec_debug) 821 printf("feed1: q->chip %p %08x stat %08x\n", 822 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr), 823 stat); 824#endif /* UBSEC_DEBUG */ 825 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 826 --sc->sc_nqueue; 827 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 828 sc->sc_nqchip++; 829 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 830 ubsecstats.hst_maxqchip = sc->sc_nqchip; 831 return; 832} 833 834static void 835ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key) 836{ 837 838 /* Go ahead and compute key in ubsec's byte order */ 839 if (algo == CRYPTO_DES_CBC) { 840 bcopy(key, &ses->ses_deskey[0], 8); 841 bcopy(key, &ses->ses_deskey[2], 8); 842 bcopy(key, &ses->ses_deskey[4], 8); 843 } else 844 bcopy(key, ses->ses_deskey, 24); 845 846 SWAP32(ses->ses_deskey[0]); 847 SWAP32(ses->ses_deskey[1]); 848 SWAP32(ses->ses_deskey[2]); 849 SWAP32(ses->ses_deskey[3]); 850 SWAP32(ses->ses_deskey[4]); 851 SWAP32(ses->ses_deskey[5]); 852} 853 854static void 855ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen) 856{ 857 MD5_CTX md5ctx; 858 SHA1_CTX sha1ctx; 859 int i; 860 861 for (i = 0; i < klen; i++) 862 key[i] ^= HMAC_IPAD_VAL; 863 864 if (algo == CRYPTO_MD5_HMAC) { 865 MD5Init(&md5ctx); 866 MD5Update(&md5ctx, key, klen); 867 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); 868 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state)); 869 } else { 870 SHA1Init(&sha1ctx); 871 SHA1Update(&sha1ctx, key, klen); 872 SHA1Update(&sha1ctx, hmac_ipad_buffer, 873 SHA1_HMAC_BLOCK_LEN - klen); 874 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); 875 } 876 877 for (i = 0; i < klen; i++) 878 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 879 880 if (algo == CRYPTO_MD5_HMAC) { 881 MD5Init(&md5ctx); 882 MD5Update(&md5ctx, key, klen); 883 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); 884 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state)); 885 } else { 886 SHA1Init(&sha1ctx); 887 SHA1Update(&sha1ctx, key, klen); 888 SHA1Update(&sha1ctx, hmac_opad_buffer, 889 SHA1_HMAC_BLOCK_LEN - klen); 890 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); 891 } 892 893 for (i = 0; i < klen; i++) 894 key[i] ^= HMAC_OPAD_VAL; 895} 896 897/* 898 * Allocate a new 'session' and return an encoded session id. 'sidp' 899 * contains our registration id, and should contain an encoded session 900 * id on successful allocation. 901 */ 902static int 903ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 904{ 905 struct cryptoini *c, *encini = NULL, *macini = NULL; 906 struct ubsec_softc *sc = arg; 907 struct ubsec_session *ses = NULL; 908 int sesn; 909 910 if (sidp == NULL || cri == NULL || sc == NULL) 911 return (EINVAL); 912 913 for (c = cri; c != NULL; c = c->cri_next) { 914 if (c->cri_alg == CRYPTO_MD5_HMAC || 915 c->cri_alg == CRYPTO_SHA1_HMAC) { 916 if (macini) 917 return (EINVAL); 918 macini = c; 919 } else if (c->cri_alg == CRYPTO_DES_CBC || 920 c->cri_alg == CRYPTO_3DES_CBC) { 921 if (encini) 922 return (EINVAL); 923 encini = c; 924 } else 925 return (EINVAL); 926 } 927 if (encini == NULL && macini == NULL) 928 return (EINVAL); 929 930 if (sc->sc_sessions == NULL) { 931 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 932 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 933 if (ses == NULL) 934 return (ENOMEM); 935 sesn = 0; 936 sc->sc_nsessions = 1; 937 } else { 938 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 939 if (sc->sc_sessions[sesn].ses_used == 0) { 940 ses = &sc->sc_sessions[sesn]; 941 break; 942 } 943 } 944 945 if (ses == NULL) { 946 sesn = sc->sc_nsessions; 947 ses = (struct ubsec_session *)malloc((sesn + 1) * 948 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 949 if (ses == NULL) 950 return (ENOMEM); 951 bcopy(sc->sc_sessions, ses, sesn * 952 sizeof(struct ubsec_session)); 953 bzero(sc->sc_sessions, sesn * 954 sizeof(struct ubsec_session)); 955 free(sc->sc_sessions, M_DEVBUF); 956 sc->sc_sessions = ses; 957 ses = &sc->sc_sessions[sesn]; 958 sc->sc_nsessions++; 959 } 960 } 961 bzero(ses, sizeof(struct ubsec_session)); 962 ses->ses_used = 1; 963 964 if (encini) { 965 /* get an IV, network byte order */ 966 /* XXX may read fewer than requested */ 967 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 968 969 if (encini->cri_key != NULL) { 970 ubsec_setup_enckey(ses, encini->cri_alg, 971 encini->cri_key); 972 } 973 } 974 975 if (macini) { 976 ses->ses_mlen = macini->cri_mlen; 977 if (ses->ses_mlen == 0) { 978 if (macini->cri_alg == CRYPTO_MD5_HMAC) 979 ses->ses_mlen = MD5_DIGEST_LENGTH; 980 else 981 ses->ses_mlen = SHA1_RESULTLEN; 982 } 983 984 if (macini->cri_key != NULL) { 985 ubsec_setup_mackey(ses, macini->cri_alg, 986 macini->cri_key, macini->cri_klen / 8); 987 } 988 } 989 990 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); 991 return (0); 992} 993 994/* 995 * Deallocate a session. 996 */ 997static int 998ubsec_freesession(void *arg, u_int64_t tid) 999{ 1000 struct ubsec_softc *sc = arg; 1001 int session, ret; 1002 u_int32_t sid = CRYPTO_SESID2LID(tid); 1003 1004 if (sc == NULL) 1005 return (EINVAL); 1006 1007 session = UBSEC_SESSION(sid); 1008 if (session < sc->sc_nsessions) { 1009 bzero(&sc->sc_sessions[session], 1010 sizeof(sc->sc_sessions[session])); 1011 ret = 0; 1012 } else 1013 ret = EINVAL; 1014 1015 return (ret); 1016} 1017 1018static void 1019ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1020{ 1021 struct ubsec_operand *op = arg; 1022 1023 KASSERT(nsegs <= UBS_MAX_SCATTER, 1024 ("Too many DMA segments returned when mapping operand")); 1025#ifdef UBSEC_DEBUG 1026 if (ubsec_debug) 1027 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 1028 (u_int) mapsize, nsegs); 1029#endif 1030 op->mapsize = mapsize; 1031 op->nsegs = nsegs; 1032 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1033} 1034 1035static int 1036ubsec_process(void *arg, struct cryptop *crp, int hint) 1037{ 1038 struct ubsec_q *q = NULL; 1039 int err = 0, i, j, nicealign; 1040 struct ubsec_softc *sc = arg; 1041 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 1042 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 1043 int sskip, dskip, stheend, dtheend; 1044 int16_t coffset; 1045 struct ubsec_session *ses; 1046 struct ubsec_pktctx ctx; 1047 struct ubsec_dma *dmap = NULL; 1048 1049 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 1050 ubsecstats.hst_invalid++; 1051 return (EINVAL); 1052 } 1053 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 1054 ubsecstats.hst_badsession++; 1055 return (EINVAL); 1056 } 1057 1058 mtx_lock(&sc->sc_freeqlock); 1059 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 1060 ubsecstats.hst_queuefull++; 1061 sc->sc_needwakeup |= CRYPTO_SYMQ; 1062 mtx_unlock(&sc->sc_freeqlock); 1063 return (ERESTART); 1064 } 1065 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1066 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 1067 mtx_unlock(&sc->sc_freeqlock); 1068 1069 dmap = q->q_dma; /* Save dma pointer */ 1070 bzero(q, sizeof(struct ubsec_q)); 1071 bzero(&ctx, sizeof(ctx)); 1072 1073 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 1074 q->q_dma = dmap; 1075 ses = &sc->sc_sessions[q->q_sesn]; 1076 1077 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1078 q->q_src_m = (struct mbuf *)crp->crp_buf; 1079 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1080 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1081 q->q_src_io = (struct uio *)crp->crp_buf; 1082 q->q_dst_io = (struct uio *)crp->crp_buf; 1083 } else { 1084 ubsecstats.hst_badflags++; 1085 err = EINVAL; 1086 goto errout; /* XXX we don't handle contiguous blocks! */ 1087 } 1088 1089 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 1090 1091 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1092 dmap->d_dma->d_mcr.mcr_flags = 0; 1093 q->q_crp = crp; 1094 1095 crd1 = crp->crp_desc; 1096 if (crd1 == NULL) { 1097 ubsecstats.hst_nodesc++; 1098 err = EINVAL; 1099 goto errout; 1100 } 1101 crd2 = crd1->crd_next; 1102 1103 if (crd2 == NULL) { 1104 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 1105 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 1106 maccrd = crd1; 1107 enccrd = NULL; 1108 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1109 crd1->crd_alg == CRYPTO_3DES_CBC) { 1110 maccrd = NULL; 1111 enccrd = crd1; 1112 } else { 1113 ubsecstats.hst_badalg++; 1114 err = EINVAL; 1115 goto errout; 1116 } 1117 } else { 1118 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1119 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1120 (crd2->crd_alg == CRYPTO_DES_CBC || 1121 crd2->crd_alg == CRYPTO_3DES_CBC) && 1122 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1123 maccrd = crd1; 1124 enccrd = crd2; 1125 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1126 crd1->crd_alg == CRYPTO_3DES_CBC) && 1127 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1128 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1129 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1130 enccrd = crd1; 1131 maccrd = crd2; 1132 } else { 1133 /* 1134 * We cannot order the ubsec as requested 1135 */ 1136 ubsecstats.hst_badalg++; 1137 err = EINVAL; 1138 goto errout; 1139 } 1140 } 1141 1142 if (enccrd) { 1143 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1144 ubsec_setup_enckey(ses, enccrd->crd_alg, 1145 enccrd->crd_key); 1146 } 1147 1148 encoffset = enccrd->crd_skip; 1149 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1150 1151 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1152 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1153 1154 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1155 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1156 else { 1157 ctx.pc_iv[0] = ses->ses_iv[0]; 1158 ctx.pc_iv[1] = ses->ses_iv[1]; 1159 } 1160 1161 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1162 if (crp->crp_flags & CRYPTO_F_IMBUF) 1163 m_copyback(q->q_src_m, 1164 enccrd->crd_inject, 1165 8, (caddr_t)ctx.pc_iv); 1166 else if (crp->crp_flags & CRYPTO_F_IOV) 1167 cuio_copyback(q->q_src_io, 1168 enccrd->crd_inject, 1169 8, (caddr_t)ctx.pc_iv); 1170 } 1171 } else { 1172 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1173 1174 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1175 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1176 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1177 m_copydata(q->q_src_m, enccrd->crd_inject, 1178 8, (caddr_t)ctx.pc_iv); 1179 else if (crp->crp_flags & CRYPTO_F_IOV) 1180 cuio_copydata(q->q_src_io, 1181 enccrd->crd_inject, 8, 1182 (caddr_t)ctx.pc_iv); 1183 } 1184 1185 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1186 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1187 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1188 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1189 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1190 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1191 SWAP32(ctx.pc_iv[0]); 1192 SWAP32(ctx.pc_iv[1]); 1193 } 1194 1195 if (maccrd) { 1196 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1197 ubsec_setup_mackey(ses, maccrd->crd_alg, 1198 maccrd->crd_key, maccrd->crd_klen / 8); 1199 } 1200 1201 macoffset = maccrd->crd_skip; 1202 1203 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1204 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1205 else 1206 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1207 1208 for (i = 0; i < 5; i++) { 1209 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1210 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1211 1212 HTOLE32(ctx.pc_hminner[i]); 1213 HTOLE32(ctx.pc_hmouter[i]); 1214 } 1215 } 1216 1217 if (enccrd && maccrd) { 1218 /* 1219 * ubsec cannot handle packets where the end of encryption 1220 * and authentication are not the same, or where the 1221 * encrypted part begins before the authenticated part. 1222 */ 1223 if ((encoffset + enccrd->crd_len) != 1224 (macoffset + maccrd->crd_len)) { 1225 ubsecstats.hst_lenmismatch++; 1226 err = EINVAL; 1227 goto errout; 1228 } 1229 if (enccrd->crd_skip < maccrd->crd_skip) { 1230 ubsecstats.hst_skipmismatch++; 1231 err = EINVAL; 1232 goto errout; 1233 } 1234 sskip = maccrd->crd_skip; 1235 cpskip = dskip = enccrd->crd_skip; 1236 stheend = maccrd->crd_len; 1237 dtheend = enccrd->crd_len; 1238 coffset = enccrd->crd_skip - maccrd->crd_skip; 1239 cpoffset = cpskip + dtheend; 1240#ifdef UBSEC_DEBUG 1241 if (ubsec_debug) { 1242 printf("mac: skip %d, len %d, inject %d\n", 1243 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1244 printf("enc: skip %d, len %d, inject %d\n", 1245 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1246 printf("src: skip %d, len %d\n", sskip, stheend); 1247 printf("dst: skip %d, len %d\n", dskip, dtheend); 1248 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1249 coffset, stheend, cpskip, cpoffset); 1250 } 1251#endif 1252 } else { 1253 cpskip = dskip = sskip = macoffset + encoffset; 1254 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1255 cpoffset = cpskip + dtheend; 1256 coffset = 0; 1257 } 1258 ctx.pc_offset = htole16(coffset >> 2); 1259 1260 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) { 1261 ubsecstats.hst_nomap++; 1262 err = ENOMEM; 1263 goto errout; 1264 } 1265 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1266 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1267 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1268 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1269 q->q_src_map = NULL; 1270 ubsecstats.hst_noload++; 1271 err = ENOMEM; 1272 goto errout; 1273 } 1274 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1275 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1276 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1277 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1278 q->q_src_map = NULL; 1279 ubsecstats.hst_noload++; 1280 err = ENOMEM; 1281 goto errout; 1282 } 1283 } 1284 nicealign = ubsec_dmamap_aligned(&q->q_src); 1285 1286 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1287 1288#ifdef UBSEC_DEBUG 1289 if (ubsec_debug) 1290 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1291#endif 1292 for (i = j = 0; i < q->q_src_nsegs; i++) { 1293 struct ubsec_pktbuf *pb; 1294 bus_size_t packl = q->q_src_segs[i].ds_len; 1295 bus_addr_t packp = q->q_src_segs[i].ds_addr; 1296 1297 if (sskip >= packl) { 1298 sskip -= packl; 1299 continue; 1300 } 1301 1302 packl -= sskip; 1303 packp += sskip; 1304 sskip = 0; 1305 1306 if (packl > 0xfffc) { 1307 err = EIO; 1308 goto errout; 1309 } 1310 1311 if (j == 0) 1312 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1313 else 1314 pb = &dmap->d_dma->d_sbuf[j - 1]; 1315 1316 pb->pb_addr = htole32(packp); 1317 1318 if (stheend) { 1319 if (packl > stheend) { 1320 pb->pb_len = htole32(stheend); 1321 stheend = 0; 1322 } else { 1323 pb->pb_len = htole32(packl); 1324 stheend -= packl; 1325 } 1326 } else 1327 pb->pb_len = htole32(packl); 1328 1329 if ((i + 1) == q->q_src_nsegs) 1330 pb->pb_next = 0; 1331 else 1332 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1333 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1334 j++; 1335 } 1336 1337 if (enccrd == NULL && maccrd != NULL) { 1338 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1339 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1340 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1341 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1342#ifdef UBSEC_DEBUG 1343 if (ubsec_debug) 1344 printf("opkt: %x %x %x\n", 1345 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1346 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1347 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1348#endif 1349 } else { 1350 if (crp->crp_flags & CRYPTO_F_IOV) { 1351 if (!nicealign) { 1352 ubsecstats.hst_iovmisaligned++; 1353 err = EINVAL; 1354 goto errout; 1355 } 1356 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1357 &q->q_dst_map)) { 1358 ubsecstats.hst_nomap++; 1359 err = ENOMEM; 1360 goto errout; 1361 } 1362 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1363 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) { 1364 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1365 q->q_dst_map = NULL; 1366 ubsecstats.hst_noload++; 1367 err = ENOMEM; 1368 goto errout; 1369 } 1370 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1371 if (nicealign) { 1372 q->q_dst = q->q_src; 1373 } else { 1374 int totlen, len; 1375 struct mbuf *m, *top, **mp; 1376 1377 ubsecstats.hst_unaligned++; 1378 totlen = q->q_src_mapsize; 1379 if (q->q_src_m->m_flags & M_PKTHDR) { 1380 len = MHLEN; 1381 MGETHDR(m, M_DONTWAIT, MT_DATA); 1382 if (m && !m_dup_pkthdr(m, q->q_src_m, M_DONTWAIT)) { 1383 m_free(m); 1384 m = NULL; 1385 } 1386 } else { 1387 len = MLEN; 1388 MGET(m, M_DONTWAIT, MT_DATA); 1389 } 1390 if (m == NULL) { 1391 ubsecstats.hst_nombuf++; 1392 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1393 goto errout; 1394 } 1395 if (totlen >= MINCLSIZE) { 1396 MCLGET(m, M_DONTWAIT); 1397 if ((m->m_flags & M_EXT) == 0) { 1398 m_free(m); 1399 ubsecstats.hst_nomcl++; 1400 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1401 goto errout; 1402 } 1403 len = MCLBYTES; 1404 } 1405 m->m_len = len; 1406 top = NULL; 1407 mp = ⊤ 1408 1409 while (totlen > 0) { 1410 if (top) { 1411 MGET(m, M_DONTWAIT, MT_DATA); 1412 if (m == NULL) { 1413 m_freem(top); 1414 ubsecstats.hst_nombuf++; 1415 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1416 goto errout; 1417 } 1418 len = MLEN; 1419 } 1420 if (top && totlen >= MINCLSIZE) { 1421 MCLGET(m, M_DONTWAIT); 1422 if ((m->m_flags & M_EXT) == 0) { 1423 *mp = m; 1424 m_freem(top); 1425 ubsecstats.hst_nomcl++; 1426 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1427 goto errout; 1428 } 1429 len = MCLBYTES; 1430 } 1431 m->m_len = len = min(totlen, len); 1432 totlen -= len; 1433 *mp = m; 1434 mp = &m->m_next; 1435 } 1436 q->q_dst_m = top; 1437 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1438 cpskip, cpoffset); 1439 if (bus_dmamap_create(sc->sc_dmat, 1440 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) { 1441 ubsecstats.hst_nomap++; 1442 err = ENOMEM; 1443 goto errout; 1444 } 1445 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1446 q->q_dst_map, q->q_dst_m, 1447 ubsec_op_cb, &q->q_dst, 1448 BUS_DMA_NOWAIT) != 0) { 1449 bus_dmamap_destroy(sc->sc_dmat, 1450 q->q_dst_map); 1451 q->q_dst_map = NULL; 1452 ubsecstats.hst_noload++; 1453 err = ENOMEM; 1454 goto errout; 1455 } 1456 } 1457 } else { 1458 ubsecstats.hst_badflags++; 1459 err = EINVAL; 1460 goto errout; 1461 } 1462 1463#ifdef UBSEC_DEBUG 1464 if (ubsec_debug) 1465 printf("dst skip: %d\n", dskip); 1466#endif 1467 for (i = j = 0; i < q->q_dst_nsegs; i++) { 1468 struct ubsec_pktbuf *pb; 1469 bus_size_t packl = q->q_dst_segs[i].ds_len; 1470 bus_addr_t packp = q->q_dst_segs[i].ds_addr; 1471 1472 if (dskip >= packl) { 1473 dskip -= packl; 1474 continue; 1475 } 1476 1477 packl -= dskip; 1478 packp += dskip; 1479 dskip = 0; 1480 1481 if (packl > 0xfffc) { 1482 err = EIO; 1483 goto errout; 1484 } 1485 1486 if (j == 0) 1487 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1488 else 1489 pb = &dmap->d_dma->d_dbuf[j - 1]; 1490 1491 pb->pb_addr = htole32(packp); 1492 1493 if (dtheend) { 1494 if (packl > dtheend) { 1495 pb->pb_len = htole32(dtheend); 1496 dtheend = 0; 1497 } else { 1498 pb->pb_len = htole32(packl); 1499 dtheend -= packl; 1500 } 1501 } else 1502 pb->pb_len = htole32(packl); 1503 1504 if ((i + 1) == q->q_dst_nsegs) { 1505 if (maccrd) 1506 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1507 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1508 else 1509 pb->pb_next = 0; 1510 } else 1511 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1512 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1513 j++; 1514 } 1515 } 1516 1517 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1518 offsetof(struct ubsec_dmachunk, d_ctx)); 1519 1520 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1521 struct ubsec_pktctx_long *ctxl; 1522 1523 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr + 1524 offsetof(struct ubsec_dmachunk, d_ctx)); 1525 1526 /* transform small context into long context */ 1527 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1528 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1529 ctxl->pc_flags = ctx.pc_flags; 1530 ctxl->pc_offset = ctx.pc_offset; 1531 for (i = 0; i < 6; i++) 1532 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1533 for (i = 0; i < 5; i++) 1534 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1535 for (i = 0; i < 5; i++) 1536 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1537 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1538 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1539 } else 1540 bcopy(&ctx, dmap->d_alloc.dma_vaddr + 1541 offsetof(struct ubsec_dmachunk, d_ctx), 1542 sizeof(struct ubsec_pktctx)); 1543 1544 mtx_lock(&sc->sc_mcr1lock); 1545 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1546 sc->sc_nqueue++; 1547 ubsecstats.hst_ipackets++; 1548 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size; 1549 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR) 1550 ubsec_feed(sc); 1551 mtx_unlock(&sc->sc_mcr1lock); 1552 return (0); 1553 1554errout: 1555 if (q != NULL) { 1556 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1557 m_freem(q->q_dst_m); 1558 1559 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1560 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1561 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1562 } 1563 if (q->q_src_map != NULL) { 1564 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1565 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1566 } 1567 } 1568 if (q != NULL || err == ERESTART) { 1569 mtx_lock(&sc->sc_freeqlock); 1570 if (q != NULL) 1571 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1572 if (err == ERESTART) 1573 sc->sc_needwakeup |= CRYPTO_SYMQ; 1574 mtx_unlock(&sc->sc_freeqlock); 1575 } 1576 if (err != ERESTART) { 1577 crp->crp_etype = err; 1578 crypto_done(crp); 1579 } 1580 return (err); 1581} 1582 1583static void 1584ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1585{ 1586 struct cryptop *crp = (struct cryptop *)q->q_crp; 1587 struct cryptodesc *crd; 1588 struct ubsec_dma *dmap = q->q_dma; 1589 1590 ubsecstats.hst_opackets++; 1591 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1592 1593 ubsec_dma_sync(&dmap->d_alloc, 1594 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1595 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1596 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1597 BUS_DMASYNC_POSTREAD); 1598 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1599 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1600 } 1601 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE); 1602 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1603 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1604 1605 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1606 m_freem(q->q_src_m); 1607 crp->crp_buf = (caddr_t)q->q_dst_m; 1608 } 1609 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len; 1610 1611 /* copy out IV for future use */ 1612 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1613 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1614 if (crd->crd_alg != CRYPTO_DES_CBC && 1615 crd->crd_alg != CRYPTO_3DES_CBC) 1616 continue; 1617 if (crp->crp_flags & CRYPTO_F_IMBUF) 1618 m_copydata((struct mbuf *)crp->crp_buf, 1619 crd->crd_skip + crd->crd_len - 8, 8, 1620 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1621 else if (crp->crp_flags & CRYPTO_F_IOV) { 1622 cuio_copydata((struct uio *)crp->crp_buf, 1623 crd->crd_skip + crd->crd_len - 8, 8, 1624 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1625 } 1626 break; 1627 } 1628 } 1629 1630 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1631 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1632 crd->crd_alg != CRYPTO_SHA1_HMAC) 1633 continue; 1634 if (crp->crp_flags & CRYPTO_F_IMBUF) 1635 m_copyback((struct mbuf *)crp->crp_buf, 1636 crd->crd_inject, 1637 sc->sc_sessions[q->q_sesn].ses_mlen, 1638 (caddr_t)dmap->d_dma->d_macbuf); 1639 else if (crp->crp_flags & CRYPTO_F_IOV) 1640 cuio_copyback((struct uio *)crp->crp_buf, 1641 crd->crd_inject, 1642 sc->sc_sessions[q->q_sesn].ses_mlen, 1643 (caddr_t)dmap->d_dma->d_macbuf); 1644 break; 1645 } 1646 mtx_lock(&sc->sc_freeqlock); 1647 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1648 mtx_unlock(&sc->sc_freeqlock); 1649 crypto_done(crp); 1650} 1651 1652static void 1653ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1654{ 1655 int i, j, dlen, slen; 1656 caddr_t dptr, sptr; 1657 1658 j = 0; 1659 sptr = srcm->m_data; 1660 slen = srcm->m_len; 1661 dptr = dstm->m_data; 1662 dlen = dstm->m_len; 1663 1664 while (1) { 1665 for (i = 0; i < min(slen, dlen); i++) { 1666 if (j < hoffset || j >= toffset) 1667 *dptr++ = *sptr++; 1668 slen--; 1669 dlen--; 1670 j++; 1671 } 1672 if (slen == 0) { 1673 srcm = srcm->m_next; 1674 if (srcm == NULL) 1675 return; 1676 sptr = srcm->m_data; 1677 slen = srcm->m_len; 1678 } 1679 if (dlen == 0) { 1680 dstm = dstm->m_next; 1681 if (dstm == NULL) 1682 return; 1683 dptr = dstm->m_data; 1684 dlen = dstm->m_len; 1685 } 1686 } 1687} 1688 1689/* 1690 * feed the key generator, must be called at splimp() or higher. 1691 */ 1692static int 1693ubsec_feed2(struct ubsec_softc *sc) 1694{ 1695 struct ubsec_q2 *q; 1696 1697 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1698 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1699 break; 1700 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1701 1702 ubsec_dma_sync(&q->q_mcr, 1703 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1704 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE); 1705 1706 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1707 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next); 1708 --sc->sc_nqueue2; 1709 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1710 } 1711 return (0); 1712} 1713 1714/* 1715 * Callback for handling random numbers 1716 */ 1717static void 1718ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1719{ 1720 struct cryptkop *krp; 1721 struct ubsec_ctx_keyop *ctx; 1722 1723 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1724 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE); 1725 1726 switch (q->q_type) { 1727#ifndef UBSEC_NO_RNG 1728 case UBS_CTXOP_RNGBYPASS: { 1729 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1730 1731 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD); 1732 (*sc->sc_harvest)(sc->sc_rndtest, 1733 rng->rng_buf.dma_vaddr, 1734 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t)); 1735 rng->rng_used = 0; 1736 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1737 break; 1738 } 1739#endif 1740 case UBS_CTXOP_MODEXP: { 1741 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1742 u_int rlen, clen; 1743 1744 krp = me->me_krp; 1745 rlen = (me->me_modbits + 7) / 8; 1746 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1747 1748 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE); 1749 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE); 1750 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD); 1751 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE); 1752 1753 if (clen < rlen) 1754 krp->krp_status = E2BIG; 1755 else { 1756 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1757 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1758 (krp->krp_param[krp->krp_iparams].crp_nbits 1759 + 7) / 8); 1760 bcopy(me->me_C.dma_vaddr, 1761 krp->krp_param[krp->krp_iparams].crp_p, 1762 (me->me_modbits + 7) / 8); 1763 } else 1764 ubsec_kshift_l(me->me_shiftbits, 1765 me->me_C.dma_vaddr, me->me_normbits, 1766 krp->krp_param[krp->krp_iparams].crp_p, 1767 krp->krp_param[krp->krp_iparams].crp_nbits); 1768 } 1769 1770 crypto_kdone(krp); 1771 1772 /* bzero all potentially sensitive data */ 1773 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1774 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1775 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1776 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1777 1778 /* Can't free here, so put us on the free list. */ 1779 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1780 break; 1781 } 1782 case UBS_CTXOP_RSAPRIV: { 1783 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1784 u_int len; 1785 1786 krp = rp->rpr_krp; 1787 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE); 1788 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD); 1789 1790 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1791 bcopy(rp->rpr_msgout.dma_vaddr, 1792 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1793 1794 crypto_kdone(krp); 1795 1796 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1797 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1798 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1799 1800 /* Can't free here, so put us on the free list. */ 1801 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1802 break; 1803 } 1804 default: 1805 device_printf(sc->sc_dev, "unknown ctx op: %x\n", 1806 letoh16(ctx->ctx_op)); 1807 break; 1808 } 1809} 1810 1811#ifndef UBSEC_NO_RNG 1812static void 1813ubsec_rng(void *vsc) 1814{ 1815 struct ubsec_softc *sc = vsc; 1816 struct ubsec_q2_rng *rng = &sc->sc_rng; 1817 struct ubsec_mcr *mcr; 1818 struct ubsec_ctx_rngbypass *ctx; 1819 1820 mtx_lock(&sc->sc_mcr2lock); 1821 if (rng->rng_used) { 1822 mtx_unlock(&sc->sc_mcr2lock); 1823 return; 1824 } 1825 sc->sc_nqueue2++; 1826 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1827 goto out; 1828 1829 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1830 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1831 1832 mcr->mcr_pkts = htole16(1); 1833 mcr->mcr_flags = 0; 1834 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1835 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1836 mcr->mcr_ipktbuf.pb_len = 0; 1837 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1838 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1839 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1840 UBS_PKTBUF_LEN); 1841 mcr->mcr_opktbuf.pb_next = 0; 1842 1843 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1844 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS); 1845 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS; 1846 1847 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD); 1848 1849 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1850 rng->rng_used = 1; 1851 ubsec_feed2(sc); 1852 ubsecstats.hst_rng++; 1853 mtx_unlock(&sc->sc_mcr2lock); 1854 1855 return; 1856 1857out: 1858 /* 1859 * Something weird happened, generate our own call back. 1860 */ 1861 sc->sc_nqueue2--; 1862 mtx_unlock(&sc->sc_mcr2lock); 1863 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1864} 1865#endif /* UBSEC_NO_RNG */ 1866 1867static void 1868ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1869{ 1870 bus_addr_t *paddr = (bus_addr_t*) arg; 1871 *paddr = segs->ds_addr; 1872} 1873 1874static int 1875ubsec_dma_malloc( 1876 struct ubsec_softc *sc, 1877 bus_size_t size, 1878 struct ubsec_dma_alloc *dma, 1879 int mapflags 1880) 1881{ 1882 int r; 1883 1884 /* XXX could specify sc_dmat as parent but that just adds overhead */ 1885 r = bus_dma_tag_create(NULL, /* parent */ 1886 1, 0, /* alignment, bounds */ 1887 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1888 BUS_SPACE_MAXADDR, /* highaddr */ 1889 NULL, NULL, /* filter, filterarg */ 1890 size, /* maxsize */ 1891 1, /* nsegments */ 1892 size, /* maxsegsize */ 1893 BUS_DMA_ALLOCNOW, /* flags */ 1894 NULL, NULL, /* lockfunc, lockarg */ 1895 &dma->dma_tag); 1896 if (r != 0) { 1897 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1898 "bus_dma_tag_create failed; error %u\n", r); 1899 goto fail_0; 1900 } 1901 1902 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map); 1903 if (r != 0) { 1904 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1905 "bus_dmamap_create failed; error %u\n", r); 1906 goto fail_1; 1907 } 1908 1909 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1910 BUS_DMA_NOWAIT, &dma->dma_map); 1911 if (r != 0) { 1912 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1913 "bus_dmammem_alloc failed; size %zu, error %u\n", 1914 size, r); 1915 goto fail_2; 1916 } 1917 1918 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1919 size, 1920 ubsec_dmamap_cb, 1921 &dma->dma_paddr, 1922 mapflags | BUS_DMA_NOWAIT); 1923 if (r != 0) { 1924 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1925 "bus_dmamap_load failed; error %u\n", r); 1926 goto fail_3; 1927 } 1928 1929 dma->dma_size = size; 1930 return (0); 1931 1932fail_3: 1933 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1934fail_2: 1935 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1936fail_1: 1937 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1938 bus_dma_tag_destroy(dma->dma_tag); 1939fail_0: 1940 dma->dma_map = NULL; 1941 dma->dma_tag = NULL; 1942 return (r); 1943} 1944 1945static void 1946ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1947{ 1948 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1949 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1950 bus_dmamap_destroy(dma->dma_tag, dma->dma_map); 1951 bus_dma_tag_destroy(dma->dma_tag); 1952} 1953 1954/* 1955 * Resets the board. Values in the regesters are left as is 1956 * from the reset (i.e. initial values are assigned elsewhere). 1957 */ 1958static void 1959ubsec_reset_board(struct ubsec_softc *sc) 1960{ 1961 volatile u_int32_t ctrl; 1962 1963 ctrl = READ_REG(sc, BS_CTRL); 1964 ctrl |= BS_CTRL_RESET; 1965 WRITE_REG(sc, BS_CTRL, ctrl); 1966 1967 /* 1968 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1969 */ 1970 DELAY(10); 1971} 1972 1973/* 1974 * Init Broadcom registers 1975 */ 1976static void 1977ubsec_init_board(struct ubsec_softc *sc) 1978{ 1979 u_int32_t ctrl; 1980 1981 ctrl = READ_REG(sc, BS_CTRL); 1982 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1983 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1984 1985 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) 1986 ctrl |= BS_CTRL_MCR2INT; 1987 else 1988 ctrl &= ~BS_CTRL_MCR2INT; 1989 1990 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1991 ctrl &= ~BS_CTRL_SWNORM; 1992 1993 WRITE_REG(sc, BS_CTRL, ctrl); 1994} 1995 1996/* 1997 * Init Broadcom PCI registers 1998 */ 1999static void 2000ubsec_init_pciregs(device_t dev) 2001{ 2002#if 0 2003 u_int32_t misc; 2004 2005 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT); 2006 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT)) 2007 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT); 2008 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT)) 2009 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT); 2010 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc); 2011#endif 2012 2013 /* 2014 * This will set the cache line size to 1, this will 2015 * force the BCM58xx chip just to do burst read/writes. 2016 * Cache line read/writes are to slow 2017 */ 2018 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1); 2019} 2020 2021/* 2022 * Clean up after a chip crash. 2023 * It is assumed that the caller in splimp() 2024 */ 2025static void 2026ubsec_cleanchip(struct ubsec_softc *sc) 2027{ 2028 struct ubsec_q *q; 2029 2030 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 2031 q = SIMPLEQ_FIRST(&sc->sc_qchip); 2032 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 2033 ubsec_free_q(sc, q); 2034 } 2035 sc->sc_nqchip = 0; 2036} 2037 2038/* 2039 * free a ubsec_q 2040 * It is assumed that the caller is within splimp(). 2041 */ 2042static int 2043ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 2044{ 2045 struct ubsec_q *q2; 2046 struct cryptop *crp; 2047 int npkts; 2048 int i; 2049 2050 npkts = q->q_nstacked_mcrs; 2051 2052 for (i = 0; i < npkts; i++) { 2053 if(q->q_stacked_mcr[i]) { 2054 q2 = q->q_stacked_mcr[i]; 2055 2056 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 2057 m_freem(q2->q_dst_m); 2058 2059 crp = (struct cryptop *)q2->q_crp; 2060 2061 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 2062 2063 crp->crp_etype = EFAULT; 2064 crypto_done(crp); 2065 } else { 2066 break; 2067 } 2068 } 2069 2070 /* 2071 * Free header MCR 2072 */ 2073 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 2074 m_freem(q->q_dst_m); 2075 2076 crp = (struct cryptop *)q->q_crp; 2077 2078 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 2079 2080 crp->crp_etype = EFAULT; 2081 crypto_done(crp); 2082 return(0); 2083} 2084 2085/* 2086 * Routine to reset the chip and clean up. 2087 * It is assumed that the caller is in splimp() 2088 */ 2089static void 2090ubsec_totalreset(struct ubsec_softc *sc) 2091{ 2092 ubsec_reset_board(sc); 2093 ubsec_init_board(sc); 2094 ubsec_cleanchip(sc); 2095} 2096 2097static int 2098ubsec_dmamap_aligned(struct ubsec_operand *op) 2099{ 2100 int i; 2101 2102 for (i = 0; i < op->nsegs; i++) { 2103 if (op->segs[i].ds_addr & 3) 2104 return (0); 2105 if ((i != (op->nsegs - 1)) && 2106 (op->segs[i].ds_len & 3)) 2107 return (0); 2108 } 2109 return (1); 2110} 2111 2112static void 2113ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2114{ 2115 switch (q->q_type) { 2116 case UBS_CTXOP_MODEXP: { 2117 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2118 2119 ubsec_dma_free(sc, &me->me_q.q_mcr); 2120 ubsec_dma_free(sc, &me->me_q.q_ctx); 2121 ubsec_dma_free(sc, &me->me_M); 2122 ubsec_dma_free(sc, &me->me_E); 2123 ubsec_dma_free(sc, &me->me_C); 2124 ubsec_dma_free(sc, &me->me_epb); 2125 free(me, M_DEVBUF); 2126 break; 2127 } 2128 case UBS_CTXOP_RSAPRIV: { 2129 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2130 2131 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2132 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2133 ubsec_dma_free(sc, &rp->rpr_msgin); 2134 ubsec_dma_free(sc, &rp->rpr_msgout); 2135 free(rp, M_DEVBUF); 2136 break; 2137 } 2138 default: 2139 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type); 2140 break; 2141 } 2142} 2143 2144static int 2145ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 2146{ 2147 struct ubsec_softc *sc = arg; 2148 int r; 2149 2150 if (krp == NULL || krp->krp_callback == NULL) 2151 return (EINVAL); 2152 2153 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2154 struct ubsec_q2 *q; 2155 2156 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2157 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next); 2158 ubsec_kfree(sc, q); 2159 } 2160 2161 switch (krp->krp_op) { 2162 case CRK_MOD_EXP: 2163 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2164 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2165 else 2166 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2167 break; 2168 case CRK_MOD_EXP_CRT: 2169 return (ubsec_kprocess_rsapriv(sc, krp, hint)); 2170 default: 2171 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n", 2172 krp->krp_op); 2173 krp->krp_status = EOPNOTSUPP; 2174 crypto_kdone(krp); 2175 return (0); 2176 } 2177 return (0); /* silence compiler */ 2178} 2179 2180/* 2181 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2182 */ 2183static int 2184ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2185{ 2186 struct ubsec_q2_modexp *me; 2187 struct ubsec_mcr *mcr; 2188 struct ubsec_ctx_modexp *ctx; 2189 struct ubsec_pktbuf *epb; 2190 int err = 0; 2191 u_int nbits, normbits, mbits, shiftbits, ebits; 2192 2193 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2194 if (me == NULL) { 2195 err = ENOMEM; 2196 goto errout; 2197 } 2198 bzero(me, sizeof *me); 2199 me->me_krp = krp; 2200 me->me_q.q_type = UBS_CTXOP_MODEXP; 2201 2202 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2203 if (nbits <= 512) 2204 normbits = 512; 2205 else if (nbits <= 768) 2206 normbits = 768; 2207 else if (nbits <= 1024) 2208 normbits = 1024; 2209 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2210 normbits = 1536; 2211 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2212 normbits = 2048; 2213 else { 2214 err = E2BIG; 2215 goto errout; 2216 } 2217 2218 shiftbits = normbits - nbits; 2219 2220 me->me_modbits = nbits; 2221 me->me_shiftbits = shiftbits; 2222 me->me_normbits = normbits; 2223 2224 /* Sanity check: result bits must be >= true modulus bits. */ 2225 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2226 err = ERANGE; 2227 goto errout; 2228 } 2229 2230 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2231 &me->me_q.q_mcr, 0)) { 2232 err = ENOMEM; 2233 goto errout; 2234 } 2235 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2236 2237 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2238 &me->me_q.q_ctx, 0)) { 2239 err = ENOMEM; 2240 goto errout; 2241 } 2242 2243 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2244 if (mbits > nbits) { 2245 err = E2BIG; 2246 goto errout; 2247 } 2248 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2249 err = ENOMEM; 2250 goto errout; 2251 } 2252 ubsec_kshift_r(shiftbits, 2253 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2254 me->me_M.dma_vaddr, normbits); 2255 2256 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2257 err = ENOMEM; 2258 goto errout; 2259 } 2260 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2261 2262 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2263 if (ebits > nbits) { 2264 err = E2BIG; 2265 goto errout; 2266 } 2267 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2268 err = ENOMEM; 2269 goto errout; 2270 } 2271 ubsec_kshift_r(shiftbits, 2272 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2273 me->me_E.dma_vaddr, normbits); 2274 2275 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2276 &me->me_epb, 0)) { 2277 err = ENOMEM; 2278 goto errout; 2279 } 2280 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2281 epb->pb_addr = htole32(me->me_E.dma_paddr); 2282 epb->pb_next = 0; 2283 epb->pb_len = htole32(normbits / 8); 2284 2285#ifdef UBSEC_DEBUG 2286 if (ubsec_debug) { 2287 printf("Epb "); 2288 ubsec_dump_pb(epb); 2289 } 2290#endif 2291 2292 mcr->mcr_pkts = htole16(1); 2293 mcr->mcr_flags = 0; 2294 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2295 mcr->mcr_reserved = 0; 2296 mcr->mcr_pktlen = 0; 2297 2298 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2299 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2300 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2301 2302 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2303 mcr->mcr_opktbuf.pb_next = 0; 2304 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2305 2306#ifdef DIAGNOSTIC 2307 /* Misaligned output buffer will hang the chip. */ 2308 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2309 panic("%s: modexp invalid addr 0x%x\n", 2310 device_get_nameunit(sc->sc_dev), 2311 letoh32(mcr->mcr_opktbuf.pb_addr)); 2312 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2313 panic("%s: modexp invalid len 0x%x\n", 2314 device_get_nameunit(sc->sc_dev), 2315 letoh32(mcr->mcr_opktbuf.pb_len)); 2316#endif 2317 2318 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2319 bzero(ctx, sizeof(*ctx)); 2320 ubsec_kshift_r(shiftbits, 2321 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2322 ctx->me_N, normbits); 2323 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2324 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2325 ctx->me_E_len = htole16(nbits); 2326 ctx->me_N_len = htole16(nbits); 2327 2328#ifdef UBSEC_DEBUG 2329 if (ubsec_debug) { 2330 ubsec_dump_mcr(mcr); 2331 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2332 } 2333#endif 2334 2335 /* 2336 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2337 * everything else. 2338 */ 2339 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2340 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2341 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2342 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2343 2344 /* Enqueue and we're done... */ 2345 mtx_lock(&sc->sc_mcr2lock); 2346 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2347 ubsec_feed2(sc); 2348 ubsecstats.hst_modexp++; 2349 mtx_unlock(&sc->sc_mcr2lock); 2350 2351 return (0); 2352 2353errout: 2354 if (me != NULL) { 2355 if (me->me_q.q_mcr.dma_map != NULL) 2356 ubsec_dma_free(sc, &me->me_q.q_mcr); 2357 if (me->me_q.q_ctx.dma_map != NULL) { 2358 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2359 ubsec_dma_free(sc, &me->me_q.q_ctx); 2360 } 2361 if (me->me_M.dma_map != NULL) { 2362 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2363 ubsec_dma_free(sc, &me->me_M); 2364 } 2365 if (me->me_E.dma_map != NULL) { 2366 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2367 ubsec_dma_free(sc, &me->me_E); 2368 } 2369 if (me->me_C.dma_map != NULL) { 2370 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2371 ubsec_dma_free(sc, &me->me_C); 2372 } 2373 if (me->me_epb.dma_map != NULL) 2374 ubsec_dma_free(sc, &me->me_epb); 2375 free(me, M_DEVBUF); 2376 } 2377 krp->krp_status = err; 2378 crypto_kdone(krp); 2379 return (0); 2380} 2381 2382/* 2383 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2384 */ 2385static int 2386ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2387{ 2388 struct ubsec_q2_modexp *me; 2389 struct ubsec_mcr *mcr; 2390 struct ubsec_ctx_modexp *ctx; 2391 struct ubsec_pktbuf *epb; 2392 int err = 0; 2393 u_int nbits, normbits, mbits, shiftbits, ebits; 2394 2395 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2396 if (me == NULL) { 2397 err = ENOMEM; 2398 goto errout; 2399 } 2400 bzero(me, sizeof *me); 2401 me->me_krp = krp; 2402 me->me_q.q_type = UBS_CTXOP_MODEXP; 2403 2404 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2405 if (nbits <= 512) 2406 normbits = 512; 2407 else if (nbits <= 768) 2408 normbits = 768; 2409 else if (nbits <= 1024) 2410 normbits = 1024; 2411 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2412 normbits = 1536; 2413 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2414 normbits = 2048; 2415 else { 2416 err = E2BIG; 2417 goto errout; 2418 } 2419 2420 shiftbits = normbits - nbits; 2421 2422 /* XXX ??? */ 2423 me->me_modbits = nbits; 2424 me->me_shiftbits = shiftbits; 2425 me->me_normbits = normbits; 2426 2427 /* Sanity check: result bits must be >= true modulus bits. */ 2428 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2429 err = ERANGE; 2430 goto errout; 2431 } 2432 2433 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2434 &me->me_q.q_mcr, 0)) { 2435 err = ENOMEM; 2436 goto errout; 2437 } 2438 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2439 2440 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2441 &me->me_q.q_ctx, 0)) { 2442 err = ENOMEM; 2443 goto errout; 2444 } 2445 2446 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2447 if (mbits > nbits) { 2448 err = E2BIG; 2449 goto errout; 2450 } 2451 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2452 err = ENOMEM; 2453 goto errout; 2454 } 2455 bzero(me->me_M.dma_vaddr, normbits / 8); 2456 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2457 me->me_M.dma_vaddr, (mbits + 7) / 8); 2458 2459 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2460 err = ENOMEM; 2461 goto errout; 2462 } 2463 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2464 2465 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2466 if (ebits > nbits) { 2467 err = E2BIG; 2468 goto errout; 2469 } 2470 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2471 err = ENOMEM; 2472 goto errout; 2473 } 2474 bzero(me->me_E.dma_vaddr, normbits / 8); 2475 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2476 me->me_E.dma_vaddr, (ebits + 7) / 8); 2477 2478 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2479 &me->me_epb, 0)) { 2480 err = ENOMEM; 2481 goto errout; 2482 } 2483 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2484 epb->pb_addr = htole32(me->me_E.dma_paddr); 2485 epb->pb_next = 0; 2486 epb->pb_len = htole32((ebits + 7) / 8); 2487 2488#ifdef UBSEC_DEBUG 2489 if (ubsec_debug) { 2490 printf("Epb "); 2491 ubsec_dump_pb(epb); 2492 } 2493#endif 2494 2495 mcr->mcr_pkts = htole16(1); 2496 mcr->mcr_flags = 0; 2497 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2498 mcr->mcr_reserved = 0; 2499 mcr->mcr_pktlen = 0; 2500 2501 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2502 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2503 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2504 2505 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2506 mcr->mcr_opktbuf.pb_next = 0; 2507 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2508 2509#ifdef DIAGNOSTIC 2510 /* Misaligned output buffer will hang the chip. */ 2511 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2512 panic("%s: modexp invalid addr 0x%x\n", 2513 device_get_nameunit(sc->sc_dev), 2514 letoh32(mcr->mcr_opktbuf.pb_addr)); 2515 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2516 panic("%s: modexp invalid len 0x%x\n", 2517 device_get_nameunit(sc->sc_dev), 2518 letoh32(mcr->mcr_opktbuf.pb_len)); 2519#endif 2520 2521 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2522 bzero(ctx, sizeof(*ctx)); 2523 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2524 (nbits + 7) / 8); 2525 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2526 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2527 ctx->me_E_len = htole16(ebits); 2528 ctx->me_N_len = htole16(nbits); 2529 2530#ifdef UBSEC_DEBUG 2531 if (ubsec_debug) { 2532 ubsec_dump_mcr(mcr); 2533 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2534 } 2535#endif 2536 2537 /* 2538 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2539 * everything else. 2540 */ 2541 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2542 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2543 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2544 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2545 2546 /* Enqueue and we're done... */ 2547 mtx_lock(&sc->sc_mcr2lock); 2548 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2549 ubsec_feed2(sc); 2550 mtx_unlock(&sc->sc_mcr2lock); 2551 2552 return (0); 2553 2554errout: 2555 if (me != NULL) { 2556 if (me->me_q.q_mcr.dma_map != NULL) 2557 ubsec_dma_free(sc, &me->me_q.q_mcr); 2558 if (me->me_q.q_ctx.dma_map != NULL) { 2559 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2560 ubsec_dma_free(sc, &me->me_q.q_ctx); 2561 } 2562 if (me->me_M.dma_map != NULL) { 2563 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2564 ubsec_dma_free(sc, &me->me_M); 2565 } 2566 if (me->me_E.dma_map != NULL) { 2567 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2568 ubsec_dma_free(sc, &me->me_E); 2569 } 2570 if (me->me_C.dma_map != NULL) { 2571 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2572 ubsec_dma_free(sc, &me->me_C); 2573 } 2574 if (me->me_epb.dma_map != NULL) 2575 ubsec_dma_free(sc, &me->me_epb); 2576 free(me, M_DEVBUF); 2577 } 2578 krp->krp_status = err; 2579 crypto_kdone(krp); 2580 return (0); 2581} 2582 2583static int 2584ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2585{ 2586 struct ubsec_q2_rsapriv *rp = NULL; 2587 struct ubsec_mcr *mcr; 2588 struct ubsec_ctx_rsapriv *ctx; 2589 int err = 0; 2590 u_int padlen, msglen; 2591 2592 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2593 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2594 if (msglen > padlen) 2595 padlen = msglen; 2596 2597 if (padlen <= 256) 2598 padlen = 256; 2599 else if (padlen <= 384) 2600 padlen = 384; 2601 else if (padlen <= 512) 2602 padlen = 512; 2603 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2604 padlen = 768; 2605 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2606 padlen = 1024; 2607 else { 2608 err = E2BIG; 2609 goto errout; 2610 } 2611 2612 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2613 err = E2BIG; 2614 goto errout; 2615 } 2616 2617 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2618 err = E2BIG; 2619 goto errout; 2620 } 2621 2622 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2623 err = E2BIG; 2624 goto errout; 2625 } 2626 2627 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT); 2628 if (rp == NULL) 2629 return (ENOMEM); 2630 bzero(rp, sizeof *rp); 2631 rp->rpr_krp = krp; 2632 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2633 2634 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2635 &rp->rpr_q.q_mcr, 0)) { 2636 err = ENOMEM; 2637 goto errout; 2638 } 2639 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2640 2641 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2642 &rp->rpr_q.q_ctx, 0)) { 2643 err = ENOMEM; 2644 goto errout; 2645 } 2646 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2647 bzero(ctx, sizeof *ctx); 2648 2649 /* Copy in p */ 2650 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2651 &ctx->rpr_buf[0 * (padlen / 8)], 2652 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2653 2654 /* Copy in q */ 2655 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2656 &ctx->rpr_buf[1 * (padlen / 8)], 2657 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2658 2659 /* Copy in dp */ 2660 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2661 &ctx->rpr_buf[2 * (padlen / 8)], 2662 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2663 2664 /* Copy in dq */ 2665 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2666 &ctx->rpr_buf[3 * (padlen / 8)], 2667 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2668 2669 /* Copy in pinv */ 2670 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2671 &ctx->rpr_buf[4 * (padlen / 8)], 2672 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2673 2674 msglen = padlen * 2; 2675 2676 /* Copy in input message (aligned buffer/length). */ 2677 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2678 /* Is this likely? */ 2679 err = E2BIG; 2680 goto errout; 2681 } 2682 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2683 err = ENOMEM; 2684 goto errout; 2685 } 2686 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2687 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2688 rp->rpr_msgin.dma_vaddr, 2689 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2690 2691 /* Prepare space for output message (aligned buffer/length). */ 2692 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2693 /* Is this likely? */ 2694 err = E2BIG; 2695 goto errout; 2696 } 2697 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2698 err = ENOMEM; 2699 goto errout; 2700 } 2701 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2702 2703 mcr->mcr_pkts = htole16(1); 2704 mcr->mcr_flags = 0; 2705 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2706 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2707 mcr->mcr_ipktbuf.pb_next = 0; 2708 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2709 mcr->mcr_reserved = 0; 2710 mcr->mcr_pktlen = htole16(msglen); 2711 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2712 mcr->mcr_opktbuf.pb_next = 0; 2713 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2714 2715#ifdef DIAGNOSTIC 2716 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2717 panic("%s: rsapriv: invalid msgin %x(0x%jx)", 2718 device_get_nameunit(sc->sc_dev), 2719 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size); 2720 } 2721 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2722 panic("%s: rsapriv: invalid msgout %x(0x%jx)", 2723 device_get_nameunit(sc->sc_dev), 2724 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size); 2725 } 2726#endif 2727 2728 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2729 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2730 ctx->rpr_q_len = htole16(padlen); 2731 ctx->rpr_p_len = htole16(padlen); 2732 2733 /* 2734 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2735 * everything else. 2736 */ 2737 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE); 2738 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD); 2739 2740 /* Enqueue and we're done... */ 2741 mtx_lock(&sc->sc_mcr2lock); 2742 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2743 ubsec_feed2(sc); 2744 ubsecstats.hst_modexpcrt++; 2745 mtx_unlock(&sc->sc_mcr2lock); 2746 return (0); 2747 2748errout: 2749 if (rp != NULL) { 2750 if (rp->rpr_q.q_mcr.dma_map != NULL) 2751 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2752 if (rp->rpr_msgin.dma_map != NULL) { 2753 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2754 ubsec_dma_free(sc, &rp->rpr_msgin); 2755 } 2756 if (rp->rpr_msgout.dma_map != NULL) { 2757 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2758 ubsec_dma_free(sc, &rp->rpr_msgout); 2759 } 2760 free(rp, M_DEVBUF); 2761 } 2762 krp->krp_status = err; 2763 crypto_kdone(krp); 2764 return (0); 2765} 2766 2767#ifdef UBSEC_DEBUG 2768static void 2769ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2770{ 2771 printf("addr 0x%x (0x%x) next 0x%x\n", 2772 pb->pb_addr, pb->pb_len, pb->pb_next); 2773} 2774 2775static void 2776ubsec_dump_ctx2(struct ubsec_ctx_keyop *c) 2777{ 2778 printf("CTX (0x%x):\n", c->ctx_len); 2779 switch (letoh16(c->ctx_op)) { 2780 case UBS_CTXOP_RNGBYPASS: 2781 case UBS_CTXOP_RNGSHA1: 2782 break; 2783 case UBS_CTXOP_MODEXP: 2784 { 2785 struct ubsec_ctx_modexp *cx = (void *)c; 2786 int i, len; 2787 2788 printf(" Elen %u, Nlen %u\n", 2789 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2790 len = (cx->me_N_len + 7)/8; 2791 for (i = 0; i < len; i++) 2792 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2793 printf("\n"); 2794 break; 2795 } 2796 default: 2797 printf("unknown context: %x\n", c->ctx_op); 2798 } 2799 printf("END CTX\n"); 2800} 2801 2802static void 2803ubsec_dump_mcr(struct ubsec_mcr *mcr) 2804{ 2805 volatile struct ubsec_mcr_add *ma; 2806 int i; 2807 2808 printf("MCR:\n"); 2809 printf(" pkts: %u, flags 0x%x\n", 2810 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2811 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2812 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2813 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2814 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2815 letoh16(ma->mcr_reserved)); 2816 printf(" %d: ipkt ", i); 2817 ubsec_dump_pb(&ma->mcr_ipktbuf); 2818 printf(" %d: opkt ", i); 2819 ubsec_dump_pb(&ma->mcr_opktbuf); 2820 ma++; 2821 } 2822 printf("END MCR\n"); 2823} 2824#endif /* UBSEC_DEBUG */ 2825 2826/* 2827 * Return the number of significant bits of a big number. 2828 */ 2829static int 2830ubsec_ksigbits(struct crparam *cr) 2831{ 2832 u_int plen = (cr->crp_nbits + 7) / 8; 2833 int i, sig = plen * 8; 2834 u_int8_t c, *p = cr->crp_p; 2835 2836 for (i = plen - 1; i >= 0; i--) { 2837 c = p[i]; 2838 if (c != 0) { 2839 while ((c & 0x80) == 0) { 2840 sig--; 2841 c <<= 1; 2842 } 2843 break; 2844 } 2845 sig -= 8; 2846 } 2847 return (sig); 2848} 2849 2850static void 2851ubsec_kshift_r( 2852 u_int shiftbits, 2853 u_int8_t *src, u_int srcbits, 2854 u_int8_t *dst, u_int dstbits) 2855{ 2856 u_int slen, dlen; 2857 int i, si, di, n; 2858 2859 slen = (srcbits + 7) / 8; 2860 dlen = (dstbits + 7) / 8; 2861 2862 for (i = 0; i < slen; i++) 2863 dst[i] = src[i]; 2864 for (i = 0; i < dlen - slen; i++) 2865 dst[slen + i] = 0; 2866 2867 n = shiftbits / 8; 2868 if (n != 0) { 2869 si = dlen - n - 1; 2870 di = dlen - 1; 2871 while (si >= 0) 2872 dst[di--] = dst[si--]; 2873 while (di >= 0) 2874 dst[di--] = 0; 2875 } 2876 2877 n = shiftbits % 8; 2878 if (n != 0) { 2879 for (i = dlen - 1; i > 0; i--) 2880 dst[i] = (dst[i] << n) | 2881 (dst[i - 1] >> (8 - n)); 2882 dst[0] = dst[0] << n; 2883 } 2884} 2885 2886static void 2887ubsec_kshift_l( 2888 u_int shiftbits, 2889 u_int8_t *src, u_int srcbits, 2890 u_int8_t *dst, u_int dstbits) 2891{ 2892 int slen, dlen, i, n; 2893 2894 slen = (srcbits + 7) / 8; 2895 dlen = (dstbits + 7) / 8; 2896 2897 n = shiftbits / 8; 2898 for (i = 0; i < slen; i++) 2899 dst[i] = src[i + n]; 2900 for (i = 0; i < dlen - slen; i++) 2901 dst[slen + i] = 0; 2902 2903 n = shiftbits % 8; 2904 if (n != 0) { 2905 for (i = 0; i < (dlen - 1); i++) 2906 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2907 dst[dlen - 1] = dst[dlen - 1] >> n; 2908 } 2909} 2910