ubsec.c revision 104630
1/* $FreeBSD: head/sys/dev/ubsec/ubsec.c 104630 2002-10-07 20:02:34Z sam $ */ 2/* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */ 3 4/* 5 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 6 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 7 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 8 * 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Jason L. Wright 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 34 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Effort sponsored in part by the Defense Advanced Research Projects 38 * Agency (DARPA) and Air Force Research Laboratory, Air Force 39 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 40 * 41 */ 42 43#define UBSEC_DEBUG 44 45/* 46 * uBsec 5[56]01, 58xx hardware crypto accelerator 47 */ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/proc.h> 52#include <sys/errno.h> 53#include <sys/malloc.h> 54#include <sys/kernel.h> 55#include <sys/mbuf.h> 56#include <sys/lock.h> 57#include <sys/mutex.h> 58#include <sys/sysctl.h> 59#include <sys/endian.h> 60 61#include <vm/vm.h> 62#include <vm/pmap.h> 63 64#include <machine/clock.h> 65#include <machine/bus.h> 66#include <machine/resource.h> 67#include <sys/bus.h> 68#include <sys/rman.h> 69 70#include <crypto/sha1.h> 71#include <opencrypto/cryptodev.h> 72#include <opencrypto/cryptosoft.h> 73#include <sys/md5.h> 74#include <sys/random.h> 75 76#include <pci/pcivar.h> 77#include <pci/pcireg.h> 78 79/* grr, #defines for gratuitous incompatibility in queue.h */ 80#define SIMPLEQ_HEAD STAILQ_HEAD 81#define SIMPLEQ_ENTRY STAILQ_ENTRY 82#define SIMPLEQ_INIT STAILQ_INIT 83#define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL 84#define SIMPLEQ_EMPTY STAILQ_EMPTY 85#define SIMPLEQ_FIRST STAILQ_FIRST 86#define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD_UNTIL 87/* ditto for endian.h */ 88#define letoh16(x) le16toh(x) 89#define letoh32(x) le32toh(x) 90 91#include <dev/ubsec/ubsecreg.h> 92#include <dev/ubsec/ubsecvar.h> 93 94/* 95 * Prototypes and count for the pci_device structure 96 */ 97static int ubsec_probe(device_t); 98static int ubsec_attach(device_t); 99static int ubsec_detach(device_t); 100static int ubsec_suspend(device_t); 101static int ubsec_resume(device_t); 102static void ubsec_shutdown(device_t); 103 104static device_method_t ubsec_methods[] = { 105 /* Device interface */ 106 DEVMETHOD(device_probe, ubsec_probe), 107 DEVMETHOD(device_attach, ubsec_attach), 108 DEVMETHOD(device_detach, ubsec_detach), 109 DEVMETHOD(device_suspend, ubsec_suspend), 110 DEVMETHOD(device_resume, ubsec_resume), 111 DEVMETHOD(device_shutdown, ubsec_shutdown), 112 113 /* bus interface */ 114 DEVMETHOD(bus_print_child, bus_generic_print_child), 115 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 116 117 { 0, 0 } 118}; 119static driver_t ubsec_driver = { 120 "ubsec", 121 ubsec_methods, 122 sizeof (struct ubsec_softc) 123}; 124static devclass_t ubsec_devclass; 125 126DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0); 127 128static void ubsec_intr(void *); 129static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *); 130static int ubsec_freesession(void *, u_int64_t); 131static int ubsec_process(void *, struct cryptop *, int); 132static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 133static int ubsec_feed(struct ubsec_softc *); 134static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 135static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 136static int ubsec_feed2(struct ubsec_softc *); 137static void ubsec_rng(void *); 138static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 139 struct ubsec_dma_alloc *, int); 140static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 141static int ubsec_dmamap_aligned(struct ubsec_operand *op); 142 143static void ubsec_reset_board(struct ubsec_softc *sc); 144static void ubsec_init_board(struct ubsec_softc *sc); 145static void ubsec_init_pciregs(device_t dev); 146static void ubsec_totalreset(struct ubsec_softc *sc); 147 148static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q); 149 150static int ubsec_kprocess(void*, struct cryptkop *, int); 151static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int); 152static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int); 153static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int); 154static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 155static int ubsec_ksigbits(struct crparam *); 156static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 157static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 158 159#ifdef UBSEC_DEBUG 160static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 161static void ubsec_dump_mcr(struct ubsec_mcr *); 162static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *); 163 164static int ubsec_debug = 0; 165SYSCTL_INT(_debug, OID_AUTO, ubsec, CTLFLAG_RW, &ubsec_debug, 166 0, "UBSEC driver debugging printfs"); 167#endif 168 169#define READ_REG(sc,r) \ 170 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 171 172#define WRITE_REG(sc,reg,val) \ 173 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 174 175#define SWAP32(x) (x) = htole32(ntohl((x))) 176#define HTOLE32(x) (x) = htole32(x) 177 178 179struct ubsec_stats ubsecstats; 180SYSCTL_STRUCT(_kern, OID_AUTO, ubsec_stats, CTLFLAG_RD, &ubsecstats, 181 ubsec_stats, "Broadcom driver statistics"); 182static int ubsec_maxbatch = 2; /* XXX tune based on part+sys speed */ 183SYSCTL_INT(_kern, OID_AUTO, ubsec_maxbatch, CTLFLAG_RW, &ubsec_maxbatch, 184 0, "Broadcom driver: max ops to batch w/o interrupt"); 185 186int 187ubsec_probe(device_t dev) 188{ 189 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 190 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 || 191 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)) 192 return (0); 193 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 194 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 || 195 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 || 196 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 197 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822)) 198 return (0); 199 return (ENXIO); 200} 201 202static const char* 203ubsec_partname(struct ubsec_softc *sc) 204{ 205 /* XXX sprintf numbers when not decoded */ 206 switch (pci_get_vendor(sc->sc_dev)) { 207 case PCI_VENDOR_BROADCOM: 208 switch (pci_get_device(sc->sc_dev)) { 209 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805"; 210 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820"; 211 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821"; 212 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822"; 213 } 214 return "Broadcom unknown-part"; 215 case PCI_VENDOR_BLUESTEEL: 216 switch (pci_get_device(sc->sc_dev)) { 217 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601"; 218 } 219 return "Bluesteel unknown-part"; 220 } 221 return "Unknown-vendor unknown-part"; 222} 223 224static int 225ubsec_attach(device_t dev) 226{ 227 struct ubsec_softc *sc = device_get_softc(dev); 228 struct ubsec_dma *dmap; 229 u_int32_t cmd, i; 230 int rid; 231 232 KASSERT(sc != NULL, ("ubsec_attach: null software carrier!")); 233 bzero(sc, sizeof (*sc)); 234 sc->sc_dev = dev; 235 236 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "crypto driver", MTX_DEF); 237 238 SIMPLEQ_INIT(&sc->sc_queue); 239 SIMPLEQ_INIT(&sc->sc_qchip); 240 SIMPLEQ_INIT(&sc->sc_queue2); 241 SIMPLEQ_INIT(&sc->sc_qchip2); 242 SIMPLEQ_INIT(&sc->sc_q2free); 243 244 /* XXX handle power management */ 245 246 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; 247 248 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 249 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601) 250 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 251 252 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 253 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805) 254 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 255 256 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 257 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820) 258 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 259 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 260 261 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 262 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 263 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822)) { 264 /* NB: the 5821/5822 defines some additional status bits */ 265 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY | 266 BS_STAT_MCR2_ALLEMPTY; 267 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 268 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 269 } 270 /* XXX no PK key support until we sort out the bus_dma stuff */ 271 sc->sc_flags &= ~UBS_FLAGS_KEY; 272 273 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 274 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN; 275 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 276 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 277 278 if (!(cmd & PCIM_CMD_MEMEN)) { 279 device_printf(dev, "failed to enable memory mapping\n"); 280 goto bad; 281 } 282 283 if (!(cmd & PCIM_CMD_BUSMASTEREN)) { 284 device_printf(dev, "failed to enable bus mastering\n"); 285 goto bad; 286 } 287 288 /* 289 * Setup memory-mapping of PCI registers. 290 */ 291 rid = BS_BAR; 292 sc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 293 0, ~0, 1, RF_ACTIVE); 294 if (sc->sc_sr == NULL) { 295 device_printf(dev, "cannot map register space\n"); 296 goto bad; 297 } 298 sc->sc_st = rman_get_bustag(sc->sc_sr); 299 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 300 301 /* 302 * Arrange interrupt line. 303 */ 304 rid = 0; 305 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 306 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE); 307 if (sc->sc_irq == NULL) { 308 device_printf(dev, "could not map interrupt\n"); 309 goto bad; 310 } 311 /* 312 * NB: Network code assumes we are blocked with splimp() 313 * so make sure the IRQ is mapped appropriately. 314 */ 315 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 316 ubsec_intr, sc, &sc->sc_ih)) { 317 device_printf(dev, "could not establish interrupt\n"); 318 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 319 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 320 goto bad; 321 } 322 323 sc->sc_cid = crypto_get_driverid(0); 324 if (sc->sc_cid < 0) { 325 device_printf(dev, "could not get crypto driver id\n"); 326 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 327 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 328 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 329 goto bad; 330 } 331 332 /* 333 * Setup DMA descriptor area. 334 */ 335 if (bus_dma_tag_create(NULL, /* parent */ 336 1, 0, /* alignment, bounds */ 337 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 338 BUS_SPACE_MAXADDR, /* highaddr */ 339 NULL, NULL, /* filter, filterarg */ 340 0x3ffff, /* maxsize XXX */ 341 UBS_MAX_SCATTER, /* nsegments */ 342 0xffff, /* maxsegsize XXX */ 343 BUS_DMA_ALLOCNOW, /* flags */ 344 &sc->sc_dmat)) { 345 device_printf(dev, "cannot allocate DMA tag\n"); 346 crypto_unregister_all(sc->sc_cid); 347 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 348 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 349 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 350 goto bad; 351 } 352 SIMPLEQ_INIT(&sc->sc_freequeue); 353 dmap = sc->sc_dmaa; 354 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 355 struct ubsec_q *q; 356 357 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 358 M_DEVBUF, M_NOWAIT); 359 if (q == NULL) { 360 device_printf(dev, "cannot allocate queue buffers\n"); 361 break; 362 } 363 364 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 365 &dmap->d_alloc, 0)) { 366 device_printf(dev, "cannot allocate dma buffers\n"); 367 free(q, M_DEVBUF); 368 break; 369 } 370 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 371 372 q->q_dma = dmap; 373 sc->sc_queuea[i] = q; 374 375 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 376 } 377 378 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc)); 379 380 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0, 381 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 382 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0, 383 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 384 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0, 385 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 386 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0, 387 ubsec_newsession, ubsec_freesession, ubsec_process, sc); 388 389 /* 390 * Reset Broadcom chip 391 */ 392 ubsec_reset_board(sc); 393 394 /* 395 * Init Broadcom specific PCI settings 396 */ 397 ubsec_init_pciregs(dev); 398 399 /* 400 * Init Broadcom chip 401 */ 402 ubsec_init_board(sc); 403 404#ifndef UBSEC_NO_RNG 405 if (sc->sc_flags & UBS_FLAGS_RNG) { 406 sc->sc_statmask |= BS_STAT_MCR2_DONE; 407 408 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 409 &sc->sc_rng.rng_q.q_mcr, 0)) 410 goto skip_rng; 411 412 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 413 &sc->sc_rng.rng_q.q_ctx, 0)) { 414 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 415 goto skip_rng; 416 } 417 418 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 419 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 420 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 421 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 422 goto skip_rng; 423 } 424 425 if (hz >= 100) 426 sc->sc_rnghz = hz / 100; 427 else 428 sc->sc_rnghz = 1; 429 callout_init(&sc->sc_rngto, 0); 430 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 431skip_rng: 432 ; 433 } 434#endif /* UBSEC_NO_RNG */ 435 436 if (sc->sc_flags & UBS_FLAGS_KEY) { 437 sc->sc_statmask |= BS_STAT_MCR2_DONE; 438 439 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0, 440 ubsec_kprocess, sc); 441#if 0 442 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0, 443 ubsec_kprocess, sc); 444#endif 445 } 446 return (0); 447bad: 448 mtx_destroy(&sc->sc_mtx); 449 return (ENXIO); 450} 451 452/* 453 * Detach a device that successfully probed. 454 */ 455static int 456ubsec_detach(device_t dev) 457{ 458 struct ubsec_softc *sc = device_get_softc(dev); 459 460 KASSERT(sc != NULL, ("ubsec_detach: null software carrier")); 461 462 UBSEC_LOCK(sc); 463 464 callout_stop(&sc->sc_rngto); 465 466 crypto_unregister_all(sc->sc_cid); 467 468 bus_generic_detach(dev); 469 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 470 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 471 472 bus_dma_tag_destroy(sc->sc_dmat); 473 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 474 475 UBSEC_UNLOCK(sc); 476 477 mtx_destroy(&sc->sc_mtx); 478 479 return (0); 480} 481 482/* 483 * Stop all chip i/o so that the kernel's probe routines don't 484 * get confused by errant DMAs when rebooting. 485 */ 486static void 487ubsec_shutdown(device_t dev) 488{ 489#ifdef notyet 490 ubsec_stop(device_get_softc(dev)); 491#endif 492} 493 494/* 495 * Device suspend routine. 496 */ 497static int 498ubsec_suspend(device_t dev) 499{ 500 struct ubsec_softc *sc = device_get_softc(dev); 501 502 KASSERT(sc != NULL, ("ubsec_suspend: null software carrier")); 503#ifdef notyet 504 /* XXX stop the device and save PCI settings */ 505#endif 506 sc->sc_suspended = 1; 507 508 return (0); 509} 510 511static int 512ubsec_resume(device_t dev) 513{ 514 struct ubsec_softc *sc = device_get_softc(dev); 515 516 KASSERT(sc != NULL, ("ubsec_resume: null software carrier")); 517#ifdef notyet 518 /* XXX retore PCI settings and start the device */ 519#endif 520 sc->sc_suspended = 0; 521 return (0); 522} 523 524/* 525 * UBSEC Interrupt routine 526 */ 527static void 528ubsec_intr(void *arg) 529{ 530 struct ubsec_softc *sc = arg; 531 volatile u_int32_t stat; 532 struct ubsec_q *q; 533 struct ubsec_dma *dmap; 534 int npkts = 0, i; 535 536 UBSEC_LOCK(sc); 537 538 stat = READ_REG(sc, BS_STAT); 539 stat &= sc->sc_statmask; 540 if (stat == 0) { 541 UBSEC_UNLOCK(sc); 542 return; 543 } 544 545 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 546 547 /* 548 * Check to see if we have any packets waiting for us 549 */ 550 if ((stat & BS_STAT_MCR1_DONE)) { 551 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 552 q = SIMPLEQ_FIRST(&sc->sc_qchip); 553 dmap = q->q_dma; 554 555 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 556 break; 557 558 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 559 560 npkts = q->q_nstacked_mcrs; 561 /* 562 * search for further sc_qchip ubsec_q's that share 563 * the same MCR, and complete them too, they must be 564 * at the top. 565 */ 566 for (i = 0; i < npkts; i++) { 567 if(q->q_stacked_mcr[i]) { 568 ubsec_callback(sc, q->q_stacked_mcr[i]); 569 ubsecstats.hst_opackets++; 570 } else { 571 break; 572 } 573 } 574 ubsec_callback(sc, q); 575 ubsecstats.hst_opackets++; 576 } 577 578 /* 579 * Don't send any more packet to chip if there has been 580 * a DMAERR. 581 */ 582 if (!(stat & BS_STAT_DMAERR)) 583 ubsec_feed(sc); 584 } 585 586 /* 587 * Check to see if we have any key setups/rng's waiting for us 588 */ 589 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 590 (stat & BS_STAT_MCR2_DONE)) { 591 struct ubsec_q2 *q2; 592 struct ubsec_mcr *mcr; 593 594 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 595 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 596 597 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 598 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 599 600 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 601 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 602 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map, 603 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 604 break; 605 } 606 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q2, q_next); 607 ubsec_callback2(sc, q2); 608 /* 609 * Don't send any more packet to chip if there has been 610 * a DMAERR. 611 */ 612 if (!(stat & BS_STAT_DMAERR)) 613 ubsec_feed2(sc); 614 } 615 } 616 617 /* 618 * Check to see if we got any DMA Error 619 */ 620 if (stat & BS_STAT_DMAERR) { 621#ifdef UBSEC_DEBUG 622 if (ubsec_debug) { 623 volatile u_int32_t a = READ_REG(sc, BS_ERR); 624 625 printf("dmaerr %s@%08x\n", 626 (a & BS_ERR_READ) ? "read" : "write", 627 a & BS_ERR_ADDR); 628 } 629#endif /* UBSEC_DEBUG */ 630 ubsecstats.hst_dmaerr++; 631 ubsec_totalreset(sc); 632 ubsec_feed(sc); 633 } 634 635 if (sc->sc_needwakeup) { /* XXX check high watermark */ 636 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 637#ifdef UBSEC_DEBUG 638 if (ubsec_debug) 639 device_printf(sc->sc_dev, "wakeup crypto (%x)\n", 640 sc->sc_needwakeup); 641#endif /* UBSEC_DEBUG */ 642 sc->sc_needwakeup &= ~wakeup; 643 crypto_unblock(sc->sc_cid, wakeup); 644 } 645 646 UBSEC_UNLOCK(sc); 647} 648 649/* 650 * ubsec_feed() - aggregate and post requests to chip 651 */ 652static int 653ubsec_feed(struct ubsec_softc *sc) 654{ 655 struct ubsec_q *q, *q2; 656 int npkts, i; 657 void *v; 658 u_int32_t stat; 659 660 npkts = sc->sc_nqueue; 661 if (npkts > UBS_MAX_AGGR) 662 npkts = UBS_MAX_AGGR; 663 if (npkts > ubsecstats.hst_maxbatch) 664 ubsecstats.hst_maxbatch = npkts; 665 if (npkts < 2) 666 goto feed1; 667 ubsecstats.hst_totbatch += npkts-1; 668 669 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 670 if(stat & BS_STAT_DMAERR) { 671 ubsec_totalreset(sc); 672 ubsecstats.hst_dmaerr++; 673 } 674 return (0); 675 } 676 677#ifdef UBSEC_DEBUG 678 if (ubsec_debug) 679 printf("merging %d records\n", npkts); 680#endif /* UBSEC_DEBUG */ 681 682 q = SIMPLEQ_FIRST(&sc->sc_queue); 683 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 684 --sc->sc_nqueue; 685 686 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 687 if (q->q_dst_map != NULL) 688 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 689 690 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 691 692 for (i = 0; i < q->q_nstacked_mcrs; i++) { 693 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 694 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 695 BUS_DMASYNC_PREWRITE); 696 if (q2->q_dst_map != NULL) 697 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 698 BUS_DMASYNC_PREREAD); 699 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q2, q_next); 700 --sc->sc_nqueue; 701 702 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - 703 sizeof(struct ubsec_mcr_add)); 704 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 705 q->q_stacked_mcr[i] = q2; 706 } 707 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 708 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 709 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 710 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 711 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 712 offsetof(struct ubsec_dmachunk, d_mcr)); 713 return (0); 714 715feed1: 716 while (!SIMPLEQ_EMPTY(&sc->sc_queue)) { 717 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 718 if(stat & BS_STAT_DMAERR) { 719 ubsec_totalreset(sc); 720 ubsecstats.hst_dmaerr++; 721 } 722 break; 723 } 724 725 q = SIMPLEQ_FIRST(&sc->sc_queue); 726 727 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, 728 BUS_DMASYNC_PREWRITE); 729 if (q->q_dst_map != NULL) 730 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 731 BUS_DMASYNC_PREREAD); 732 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, 733 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 734 735 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 736 offsetof(struct ubsec_dmachunk, d_mcr)); 737#ifdef UBSEC_DEBUG 738 if (ubsec_debug) 739 printf("feed: q->chip %p %08x stat %08x\n", 740 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr), 741 stat); 742#endif /* UBSEC_DEBUG */ 743 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q, q_next); 744 --sc->sc_nqueue; 745 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 746 } 747 return (0); 748} 749 750/* 751 * Allocate a new 'session' and return an encoded session id. 'sidp' 752 * contains our registration id, and should contain an encoded session 753 * id on successful allocation. 754 */ 755static int 756ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri) 757{ 758 struct cryptoini *c, *encini = NULL, *macini = NULL; 759 struct ubsec_softc *sc = arg; 760 struct ubsec_session *ses = NULL; 761 MD5_CTX md5ctx; 762 SHA1_CTX sha1ctx; 763 int i, sesn; 764 765 KASSERT(sc != NULL, ("ubsec_newsession: null softc")); 766 if (sidp == NULL || cri == NULL || sc == NULL) 767 return (EINVAL); 768 769 for (c = cri; c != NULL; c = c->cri_next) { 770 if (c->cri_alg == CRYPTO_MD5_HMAC || 771 c->cri_alg == CRYPTO_SHA1_HMAC) { 772 if (macini) 773 return (EINVAL); 774 macini = c; 775 } else if (c->cri_alg == CRYPTO_DES_CBC || 776 c->cri_alg == CRYPTO_3DES_CBC) { 777 if (encini) 778 return (EINVAL); 779 encini = c; 780 } else 781 return (EINVAL); 782 } 783 if (encini == NULL && macini == NULL) 784 return (EINVAL); 785 786 if (sc->sc_sessions == NULL) { 787 ses = sc->sc_sessions = (struct ubsec_session *)malloc( 788 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 789 if (ses == NULL) 790 return (ENOMEM); 791 sesn = 0; 792 sc->sc_nsessions = 1; 793 } else { 794 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 795 if (sc->sc_sessions[sesn].ses_used == 0) { 796 ses = &sc->sc_sessions[sesn]; 797 break; 798 } 799 } 800 801 if (ses == NULL) { 802 sesn = sc->sc_nsessions; 803 ses = (struct ubsec_session *)malloc((sesn + 1) * 804 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT); 805 if (ses == NULL) 806 return (ENOMEM); 807 bcopy(sc->sc_sessions, ses, sesn * 808 sizeof(struct ubsec_session)); 809 bzero(sc->sc_sessions, sesn * 810 sizeof(struct ubsec_session)); 811 free(sc->sc_sessions, M_DEVBUF); 812 sc->sc_sessions = ses; 813 ses = &sc->sc_sessions[sesn]; 814 sc->sc_nsessions++; 815 } 816 } 817 818 bzero(ses, sizeof(struct ubsec_session)); 819 ses->ses_used = 1; 820 if (encini) { 821 /* get an IV, network byte order */ 822 /* XXX may read fewer than requested */ 823 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 824 825 /* Go ahead and compute key in ubsec's byte order */ 826 if (encini->cri_alg == CRYPTO_DES_CBC) { 827 bcopy(encini->cri_key, &ses->ses_deskey[0], 8); 828 bcopy(encini->cri_key, &ses->ses_deskey[2], 8); 829 bcopy(encini->cri_key, &ses->ses_deskey[4], 8); 830 } else 831 bcopy(encini->cri_key, ses->ses_deskey, 24); 832 833 SWAP32(ses->ses_deskey[0]); 834 SWAP32(ses->ses_deskey[1]); 835 SWAP32(ses->ses_deskey[2]); 836 SWAP32(ses->ses_deskey[3]); 837 SWAP32(ses->ses_deskey[4]); 838 SWAP32(ses->ses_deskey[5]); 839 } 840 841 if (macini) { 842 for (i = 0; i < macini->cri_klen / 8; i++) 843 macini->cri_key[i] ^= HMAC_IPAD_VAL; 844 845 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 846 MD5Init(&md5ctx); 847 MD5Update(&md5ctx, macini->cri_key, 848 macini->cri_klen / 8); 849 MD5Update(&md5ctx, hmac_ipad_buffer, 850 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 851 bcopy(md5ctx.state, ses->ses_hminner, 852 sizeof(md5ctx.state)); 853 } else { 854 SHA1Init(&sha1ctx); 855 SHA1Update(&sha1ctx, macini->cri_key, 856 macini->cri_klen / 8); 857 SHA1Update(&sha1ctx, hmac_ipad_buffer, 858 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 859 bcopy(sha1ctx.h.b32, ses->ses_hminner, 860 sizeof(sha1ctx.h.b32)); 861 } 862 863 for (i = 0; i < macini->cri_klen / 8; i++) 864 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 865 866 if (macini->cri_alg == CRYPTO_MD5_HMAC) { 867 MD5Init(&md5ctx); 868 MD5Update(&md5ctx, macini->cri_key, 869 macini->cri_klen / 8); 870 MD5Update(&md5ctx, hmac_opad_buffer, 871 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 872 bcopy(md5ctx.state, ses->ses_hmouter, 873 sizeof(md5ctx.state)); 874 } else { 875 SHA1Init(&sha1ctx); 876 SHA1Update(&sha1ctx, macini->cri_key, 877 macini->cri_klen / 8); 878 SHA1Update(&sha1ctx, hmac_opad_buffer, 879 HMAC_BLOCK_LEN - (macini->cri_klen / 8)); 880 bcopy(sha1ctx.h.b32, ses->ses_hmouter, 881 sizeof(sha1ctx.h.b32)); 882 } 883 884 for (i = 0; i < macini->cri_klen / 8; i++) 885 macini->cri_key[i] ^= HMAC_OPAD_VAL; 886 } 887 888 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); 889 return (0); 890} 891 892/* 893 * Deallocate a session. 894 */ 895static int 896ubsec_freesession(void *arg, u_int64_t tid) 897{ 898 struct ubsec_softc *sc = arg; 899 int session; 900 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; 901 902 KASSERT(sc != NULL, ("ubsec_freesession: null softc")); 903 if (sc == NULL) 904 return (EINVAL); 905 906 session = UBSEC_SESSION(sid); 907 if (session >= sc->sc_nsessions) 908 return (EINVAL); 909 910 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); 911 return (0); 912} 913 914static void 915ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 916{ 917 struct ubsec_operand *op = arg; 918 919 KASSERT(nsegs <= UBS_MAX_SCATTER, 920 ("Too many DMA segments returned when mapping operand")); 921#ifdef UBSEC_DEBUG 922 if (ubsec_debug) 923 printf("ubsec_op_cb: mapsize %u nsegs %d\n", 924 (u_int) mapsize, nsegs); 925#endif 926 op->mapsize = mapsize; 927 op->nsegs = nsegs; 928 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 929} 930 931static int 932ubsec_process(void *arg, struct cryptop *crp, int hint) 933{ 934 struct ubsec_q *q = NULL; 935 int err = 0, i, j, nicealign; 936 struct ubsec_softc *sc = arg; 937 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 938 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 939 int sskip, dskip, stheend, dtheend; 940 int16_t coffset; 941 struct ubsec_session *ses; 942 struct ubsec_pktctx ctx; 943 struct ubsec_dma *dmap = NULL; 944 945 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 946 ubsecstats.hst_invalid++; 947 return (EINVAL); 948 } 949 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) { 950 ubsecstats.hst_invalid++; 951 return (EINVAL); 952 } 953 954 UBSEC_LOCK(sc); 955 956 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 957 ubsecstats.hst_queuefull++; 958 sc->sc_needwakeup |= CRYPTO_SYMQ; 959 UBSEC_UNLOCK(sc); 960 return (ERESTART); 961 } 962 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 963 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q, q_next); 964 UBSEC_UNLOCK(sc); 965 966 dmap = q->q_dma; /* Save dma pointer */ 967 bzero(q, sizeof(struct ubsec_q)); 968 bzero(&ctx, sizeof(ctx)); 969 970 q->q_sesn = UBSEC_SESSION(crp->crp_sid); 971 q->q_dma = dmap; 972 ses = &sc->sc_sessions[q->q_sesn]; 973 974 if (crp->crp_flags & CRYPTO_F_IMBUF) { 975 q->q_src_m = (struct mbuf *)crp->crp_buf; 976 q->q_dst_m = (struct mbuf *)crp->crp_buf; 977 } else if (crp->crp_flags & CRYPTO_F_IOV) { 978 q->q_src_io = (struct uio *)crp->crp_buf; 979 q->q_dst_io = (struct uio *)crp->crp_buf; 980 } else { 981 ubsecstats.hst_invalid++; 982 err = EINVAL; 983 goto errout; /* XXX we don't handle contiguous blocks! */ 984 } 985 986 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 987 988 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 989 dmap->d_dma->d_mcr.mcr_flags = 0; 990 q->q_crp = crp; 991 992 crd1 = crp->crp_desc; 993 if (crd1 == NULL) { 994 ubsecstats.hst_invalid++; 995 err = EINVAL; 996 goto errout; 997 } 998 crd2 = crd1->crd_next; 999 1000 if (crd2 == NULL) { 1001 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 1002 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 1003 maccrd = crd1; 1004 enccrd = NULL; 1005 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1006 crd1->crd_alg == CRYPTO_3DES_CBC) { 1007 maccrd = NULL; 1008 enccrd = crd1; 1009 } else { 1010 ubsecstats.hst_invalid++; 1011 err = EINVAL; 1012 goto errout; 1013 } 1014 } else { 1015 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1016 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1017 (crd2->crd_alg == CRYPTO_DES_CBC || 1018 crd2->crd_alg == CRYPTO_3DES_CBC) && 1019 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1020 maccrd = crd1; 1021 enccrd = crd2; 1022 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1023 crd1->crd_alg == CRYPTO_3DES_CBC) && 1024 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1025 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1026 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1027 enccrd = crd1; 1028 maccrd = crd2; 1029 } else { 1030 /* 1031 * We cannot order the ubsec as requested 1032 */ 1033 ubsecstats.hst_invalid++; 1034 err = EINVAL; 1035 goto errout; 1036 } 1037 } 1038 1039 if (enccrd) { 1040 encoffset = enccrd->crd_skip; 1041 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1042 1043 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1044 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1045 1046 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1047 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1048 else { 1049 ctx.pc_iv[0] = ses->ses_iv[0]; 1050 ctx.pc_iv[1] = ses->ses_iv[1]; 1051 } 1052 1053 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1054 if (crp->crp_flags & CRYPTO_F_IMBUF) 1055 m_copyback(q->q_src_m, 1056 enccrd->crd_inject, 1057 8, (caddr_t)ctx.pc_iv); 1058 else if (crp->crp_flags & CRYPTO_F_IOV) 1059 cuio_copyback(q->q_src_io, 1060 enccrd->crd_inject, 1061 8, (caddr_t)ctx.pc_iv); 1062 } 1063 } else { 1064 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1065 1066 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1067 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1068 else if (crp->crp_flags & CRYPTO_F_IMBUF) 1069 m_copydata(q->q_src_m, enccrd->crd_inject, 1070 8, (caddr_t)ctx.pc_iv); 1071 else if (crp->crp_flags & CRYPTO_F_IOV) 1072 cuio_copydata(q->q_src_io, 1073 enccrd->crd_inject, 8, 1074 (caddr_t)ctx.pc_iv); 1075 } 1076 1077 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1078 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1079 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1080 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1081 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1082 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1083 SWAP32(ctx.pc_iv[0]); 1084 SWAP32(ctx.pc_iv[1]); 1085 } 1086 1087 if (maccrd) { 1088 macoffset = maccrd->crd_skip; 1089 1090 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1091 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1092 else 1093 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1094 1095 for (i = 0; i < 5; i++) { 1096 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1097 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1098 1099 HTOLE32(ctx.pc_hminner[i]); 1100 HTOLE32(ctx.pc_hmouter[i]); 1101 } 1102 } 1103 1104 if (enccrd && maccrd) { 1105 /* 1106 * ubsec cannot handle packets where the end of encryption 1107 * and authentication are not the same, or where the 1108 * encrypted part begins before the authenticated part. 1109 */ 1110 if ((encoffset + enccrd->crd_len) != 1111 (macoffset + maccrd->crd_len)) { 1112 ubsecstats.hst_lenmismatch++; 1113 err = EINVAL; 1114 goto errout; 1115 } 1116 if (enccrd->crd_skip < maccrd->crd_skip) { 1117 ubsecstats.hst_skipmismatch++; 1118 err = EINVAL; 1119 goto errout; 1120 } 1121 sskip = maccrd->crd_skip; 1122 cpskip = dskip = enccrd->crd_skip; 1123 stheend = maccrd->crd_len; 1124 dtheend = enccrd->crd_len; 1125 coffset = enccrd->crd_skip - maccrd->crd_skip; 1126 cpoffset = cpskip + dtheend; 1127#ifdef UBSEC_DEBUG 1128 if (ubsec_debug) { 1129 printf("mac: skip %d, len %d, inject %d\n", 1130 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1131 printf("enc: skip %d, len %d, inject %d\n", 1132 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1133 printf("src: skip %d, len %d\n", sskip, stheend); 1134 printf("dst: skip %d, len %d\n", dskip, dtheend); 1135 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1136 coffset, stheend, cpskip, cpoffset); 1137 } 1138#endif 1139 } else { 1140 cpskip = dskip = sskip = macoffset + encoffset; 1141 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1142 cpoffset = cpskip + dtheend; 1143 coffset = 0; 1144 } 1145 ctx.pc_offset = htole16(coffset >> 2); 1146 1147 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) { 1148 ubsecstats.hst_nomap++; 1149 err = ENOMEM; 1150 goto errout; 1151 } 1152 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1153 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1154 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1155 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1156 q->q_src_map = NULL; 1157 ubsecstats.hst_noload++; 1158 err = ENOMEM; 1159 goto errout; 1160 } 1161 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1162 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1163 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1164 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1165 q->q_src_map = NULL; 1166 ubsecstats.hst_noload++; 1167 err = ENOMEM; 1168 goto errout; 1169 } 1170 } 1171 nicealign = ubsec_dmamap_aligned(&q->q_src); 1172 1173 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1174 1175#ifdef UBSEC_DEBUG 1176 if (ubsec_debug) 1177 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1178#endif 1179 for (i = j = 0; i < q->q_src_nsegs; i++) { 1180 struct ubsec_pktbuf *pb; 1181 bus_size_t packl = q->q_src_segs[i].ds_len; 1182 bus_addr_t packp = q->q_src_segs[i].ds_addr; 1183 1184 if (sskip >= packl) { 1185 sskip -= packl; 1186 continue; 1187 } 1188 1189 packl -= sskip; 1190 packp += sskip; 1191 sskip = 0; 1192 1193 if (packl > 0xfffc) { 1194 err = EIO; 1195 goto errout; 1196 } 1197 1198 if (j == 0) 1199 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1200 else 1201 pb = &dmap->d_dma->d_sbuf[j - 1]; 1202 1203 pb->pb_addr = htole32(packp); 1204 1205 if (stheend) { 1206 if (packl > stheend) { 1207 pb->pb_len = htole32(stheend); 1208 stheend = 0; 1209 } else { 1210 pb->pb_len = htole32(packl); 1211 stheend -= packl; 1212 } 1213 } else 1214 pb->pb_len = htole32(packl); 1215 1216 if ((i + 1) == q->q_src_nsegs) 1217 pb->pb_next = 0; 1218 else 1219 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1220 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1221 j++; 1222 } 1223 1224 if (enccrd == NULL && maccrd != NULL) { 1225 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1226 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1227 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1228 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1229#ifdef UBSEC_DEBUG 1230 if (ubsec_debug) 1231 printf("opkt: %x %x %x\n", 1232 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1233 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1234 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1235#endif 1236 } else { 1237 if (crp->crp_flags & CRYPTO_F_IOV) { 1238 if (!nicealign) { 1239 ubsecstats.hst_iovmisaligned++; 1240 err = EINVAL; 1241 goto errout; 1242 } 1243 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1244 &q->q_dst_map)) { 1245 ubsecstats.hst_nomap++; 1246 err = ENOMEM; 1247 goto errout; 1248 } 1249 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1250 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) { 1251 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1252 q->q_dst_map = NULL; 1253 ubsecstats.hst_noload++; 1254 err = ENOMEM; 1255 goto errout; 1256 } 1257 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1258 if (nicealign) { 1259 q->q_dst = q->q_src; 1260 } else { 1261 int totlen, len; 1262 struct mbuf *m, *top, **mp; 1263 1264 ubsecstats.hst_unaligned++; 1265 totlen = q->q_src_mapsize; 1266 if (q->q_src_m->m_flags & M_PKTHDR) { 1267 len = MHLEN; 1268 MGETHDR(m, M_DONTWAIT, MT_DATA); 1269 } else { 1270 len = MLEN; 1271 MGET(m, M_DONTWAIT, MT_DATA); 1272 } 1273 if (m == NULL) { 1274 ubsecstats.hst_nombuf++; 1275 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1276 goto errout; 1277 } 1278 if (len == MHLEN) 1279 M_COPY_PKTHDR(m, q->q_src_m); 1280 if (totlen >= MINCLSIZE) { 1281 MCLGET(m, M_DONTWAIT); 1282 if ((m->m_flags & M_EXT) == 0) { 1283 m_free(m); 1284 ubsecstats.hst_nomcl++; 1285 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1286 goto errout; 1287 } 1288 len = MCLBYTES; 1289 } 1290 m->m_len = len; 1291 top = NULL; 1292 mp = ⊤ 1293 1294 while (totlen > 0) { 1295 if (top) { 1296 MGET(m, M_DONTWAIT, MT_DATA); 1297 if (m == NULL) { 1298 m_freem(top); 1299 ubsecstats.hst_nombuf++; 1300 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1301 goto errout; 1302 } 1303 len = MLEN; 1304 } 1305 if (top && totlen >= MINCLSIZE) { 1306 MCLGET(m, M_DONTWAIT); 1307 if ((m->m_flags & M_EXT) == 0) { 1308 *mp = m; 1309 m_freem(top); 1310 ubsecstats.hst_nomcl++; 1311 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1312 goto errout; 1313 } 1314 len = MCLBYTES; 1315 } 1316 m->m_len = len = min(totlen, len); 1317 totlen -= len; 1318 *mp = m; 1319 mp = &m->m_next; 1320 } 1321 q->q_dst_m = top; 1322 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1323 cpskip, cpoffset); 1324 if (bus_dmamap_create(sc->sc_dmat, 1325 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) { 1326 ubsecstats.hst_nomap++; 1327 err = ENOMEM; 1328 goto errout; 1329 } 1330 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1331 q->q_dst_map, q->q_dst_m, 1332 ubsec_op_cb, &q->q_dst, 1333 BUS_DMA_NOWAIT) != 0) { 1334 bus_dmamap_destroy(sc->sc_dmat, 1335 q->q_dst_map); 1336 q->q_dst_map = NULL; 1337 ubsecstats.hst_noload++; 1338 err = ENOMEM; 1339 goto errout; 1340 } 1341 } 1342 } else { 1343 ubsecstats.hst_invalid++; 1344 err = EINVAL; 1345 goto errout; 1346 } 1347 1348#ifdef UBSEC_DEBUG 1349 if (ubsec_debug) 1350 printf("dst skip: %d\n", dskip); 1351#endif 1352 for (i = j = 0; i < q->q_dst_nsegs; i++) { 1353 struct ubsec_pktbuf *pb; 1354 bus_size_t packl = q->q_dst_segs[i].ds_len; 1355 bus_addr_t packp = q->q_dst_segs[i].ds_addr; 1356 1357 if (dskip >= packl) { 1358 dskip -= packl; 1359 continue; 1360 } 1361 1362 packl -= dskip; 1363 packp += dskip; 1364 dskip = 0; 1365 1366 if (packl > 0xfffc) { 1367 err = EIO; 1368 goto errout; 1369 } 1370 1371 if (j == 0) 1372 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1373 else 1374 pb = &dmap->d_dma->d_dbuf[j - 1]; 1375 1376 pb->pb_addr = htole32(packp); 1377 1378 if (dtheend) { 1379 if (packl > dtheend) { 1380 pb->pb_len = htole32(dtheend); 1381 dtheend = 0; 1382 } else { 1383 pb->pb_len = htole32(packl); 1384 dtheend -= packl; 1385 } 1386 } else 1387 pb->pb_len = htole32(packl); 1388 1389 if ((i + 1) == q->q_dst_nsegs) { 1390 if (maccrd) 1391 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1392 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1393 else 1394 pb->pb_next = 0; 1395 } else 1396 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1397 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1398 j++; 1399 } 1400 } 1401 1402 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1403 offsetof(struct ubsec_dmachunk, d_ctx)); 1404 1405 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1406 struct ubsec_pktctx_long *ctxl; 1407 1408 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr + 1409 offsetof(struct ubsec_dmachunk, d_ctx)); 1410 1411 /* transform small context into long context */ 1412 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1413 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1414 ctxl->pc_flags = ctx.pc_flags; 1415 ctxl->pc_offset = ctx.pc_offset; 1416 for (i = 0; i < 6; i++) 1417 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1418 for (i = 0; i < 5; i++) 1419 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1420 for (i = 0; i < 5; i++) 1421 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1422 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1423 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1424 } else 1425 bcopy(&ctx, dmap->d_alloc.dma_vaddr + 1426 offsetof(struct ubsec_dmachunk, d_ctx), 1427 sizeof(struct ubsec_pktctx)); 1428 1429 UBSEC_LOCK(sc); 1430 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1431 sc->sc_nqueue++; 1432 ubsecstats.hst_ipackets++; 1433 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size; 1434 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= ubsec_maxbatch) 1435 ubsec_feed(sc); 1436 UBSEC_UNLOCK(sc); 1437 return (0); 1438 1439errout: 1440 if (q != NULL) { 1441 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1442 m_freem(q->q_dst_m); 1443 1444 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1445 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1446 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1447 } 1448 if (q->q_src_map != NULL) { 1449 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1450 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1451 } 1452 1453 UBSEC_LOCK(sc); 1454 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1455 UBSEC_UNLOCK(sc); 1456 } 1457 if (err != ERESTART) { 1458 crp->crp_etype = err; 1459 crypto_done(crp); 1460 } else { 1461 sc->sc_needwakeup |= CRYPTO_SYMQ; 1462 } 1463 return (err); 1464} 1465 1466static void 1467ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1468{ 1469 struct cryptop *crp = (struct cryptop *)q->q_crp; 1470 struct cryptodesc *crd; 1471 struct ubsec_dma *dmap = q->q_dma; 1472 1473 bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 1474 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1475 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1476 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1477 BUS_DMASYNC_POSTREAD); 1478 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1479 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1480 } 1481 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE); 1482 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1483 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1484 1485 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1486 m_freem(q->q_src_m); 1487 crp->crp_buf = (caddr_t)q->q_dst_m; 1488 } 1489 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len; 1490 1491 /* copy out IV for future use */ 1492 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1493 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1494 if (crd->crd_alg != CRYPTO_DES_CBC && 1495 crd->crd_alg != CRYPTO_3DES_CBC) 1496 continue; 1497 if (crp->crp_flags & CRYPTO_F_IMBUF) 1498 m_copydata((struct mbuf *)crp->crp_buf, 1499 crd->crd_skip + crd->crd_len - 8, 8, 1500 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1501 else if (crp->crp_flags & CRYPTO_F_IOV) { 1502 cuio_copydata((struct uio *)crp->crp_buf, 1503 crd->crd_skip + crd->crd_len - 8, 8, 1504 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); 1505 } 1506 break; 1507 } 1508 } 1509 1510 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1511 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1512 crd->crd_alg != CRYPTO_SHA1_HMAC) 1513 continue; 1514 if (crp->crp_flags & CRYPTO_F_IMBUF) 1515 m_copyback((struct mbuf *)crp->crp_buf, 1516 crd->crd_inject, 12, 1517 (caddr_t)dmap->d_dma->d_macbuf); 1518 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) 1519 bcopy((caddr_t)dmap->d_dma->d_macbuf, 1520 crp->crp_mac, 12); 1521 break; 1522 } 1523 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1524 crypto_done(crp); 1525} 1526 1527static void 1528ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1529{ 1530 int i, j, dlen, slen; 1531 caddr_t dptr, sptr; 1532 1533 j = 0; 1534 sptr = srcm->m_data; 1535 slen = srcm->m_len; 1536 dptr = dstm->m_data; 1537 dlen = dstm->m_len; 1538 1539 while (1) { 1540 for (i = 0; i < min(slen, dlen); i++) { 1541 if (j < hoffset || j >= toffset) 1542 *dptr++ = *sptr++; 1543 slen--; 1544 dlen--; 1545 j++; 1546 } 1547 if (slen == 0) { 1548 srcm = srcm->m_next; 1549 if (srcm == NULL) 1550 return; 1551 sptr = srcm->m_data; 1552 slen = srcm->m_len; 1553 } 1554 if (dlen == 0) { 1555 dstm = dstm->m_next; 1556 if (dstm == NULL) 1557 return; 1558 dptr = dstm->m_data; 1559 dlen = dstm->m_len; 1560 } 1561 } 1562} 1563 1564/* 1565 * feed the key generator, must be called at splimp() or higher. 1566 */ 1567static int 1568ubsec_feed2(struct ubsec_softc *sc) 1569{ 1570 struct ubsec_q2 *q; 1571 1572 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1573 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1574 break; 1575 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1576 1577 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 1578 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1579 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 1580 BUS_DMASYNC_PREWRITE); 1581 1582 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1583 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q, q_next); 1584 --sc->sc_nqueue2; 1585 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1586 } 1587 return (0); 1588} 1589 1590/* 1591 * Callback for handling random numbers 1592 */ 1593static void 1594ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1595{ 1596 struct cryptkop *krp; 1597 struct ubsec_ctx_keyop *ctx; 1598 1599 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1600 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, BUS_DMASYNC_POSTWRITE); 1601 1602 switch (q->q_type) { 1603#ifndef UBSEC_NO_RNG 1604 case UBS_CTXOP_RNGBYPASS: { 1605 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1606 1607 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 1608 BUS_DMASYNC_POSTREAD); 1609 random_harvest(rng->rng_buf.dma_vaddr, 1610 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t), 1611 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t)*NBBY, 0, 1612 RANDOM_PURE); 1613 rng->rng_used = 0; 1614 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1615 break; 1616 } 1617#endif 1618 case UBS_CTXOP_MODEXP: { 1619 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1620 u_int rlen, clen; 1621 1622 krp = me->me_krp; 1623 rlen = (me->me_modbits + 7) / 8; 1624 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1625 1626 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, 1627 BUS_DMASYNC_POSTWRITE); 1628 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, 1629 BUS_DMASYNC_POSTWRITE); 1630 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, 1631 BUS_DMASYNC_POSTREAD); 1632 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, 1633 BUS_DMASYNC_POSTWRITE); 1634 1635 if (clen < rlen) 1636 krp->krp_status = E2BIG; 1637 else { 1638 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1639 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1640 (krp->krp_param[krp->krp_iparams].crp_nbits 1641 + 7) / 8); 1642 bcopy(me->me_C.dma_vaddr, 1643 krp->krp_param[krp->krp_iparams].crp_p, 1644 (me->me_modbits + 7) / 8); 1645 } else 1646 ubsec_kshift_l(me->me_shiftbits, 1647 me->me_C.dma_vaddr, me->me_normbits, 1648 krp->krp_param[krp->krp_iparams].crp_p, 1649 krp->krp_param[krp->krp_iparams].crp_nbits); 1650 } 1651 1652 crypto_kdone(krp); 1653 1654 /* bzero all potentially sensitive data */ 1655 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1656 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1657 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1658 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1659 1660 /* Can't free here, so put us on the free list. */ 1661 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1662 break; 1663 } 1664 case UBS_CTXOP_RSAPRIV: { 1665 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1666 u_int len; 1667 1668 krp = rp->rpr_krp; 1669 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 1670 BUS_DMASYNC_POSTWRITE); 1671 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 1672 BUS_DMASYNC_POSTREAD); 1673 1674 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1675 bcopy(rp->rpr_msgout.dma_vaddr, 1676 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1677 1678 crypto_kdone(krp); 1679 1680 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1681 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1682 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1683 1684 /* Can't free here, so put us on the free list. */ 1685 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1686 break; 1687 } 1688 default: 1689 device_printf(sc->sc_dev, "unknown ctx op: %x\n", 1690 letoh16(ctx->ctx_op)); 1691 break; 1692 } 1693} 1694 1695#ifndef UBSEC_NO_RNG 1696static void 1697ubsec_rng(void *vsc) 1698{ 1699 struct ubsec_softc *sc = vsc; 1700 struct ubsec_q2_rng *rng = &sc->sc_rng; 1701 struct ubsec_mcr *mcr; 1702 struct ubsec_ctx_rngbypass *ctx; 1703 1704 UBSEC_LOCK(sc); 1705 if (rng->rng_used) { 1706 UBSEC_UNLOCK(sc); 1707 return; 1708 } 1709 sc->sc_nqueue2++; 1710 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1711 goto out; 1712 1713 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1714 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1715 1716 mcr->mcr_pkts = htole16(1); 1717 mcr->mcr_flags = 0; 1718 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1719 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1720 mcr->mcr_ipktbuf.pb_len = 0; 1721 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1722 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1723 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1724 UBS_PKTBUF_LEN); 1725 mcr->mcr_opktbuf.pb_next = 0; 1726 1727 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1728 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS); 1729 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS; 1730 1731 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, BUS_DMASYNC_PREREAD); 1732 1733 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1734 rng->rng_used = 1; 1735 ubsec_feed2(sc); 1736 ubsecstats.hst_rng++; 1737 UBSEC_UNLOCK(sc); 1738 1739 return; 1740 1741out: 1742 /* 1743 * Something weird happened, generate our own call back. 1744 */ 1745 sc->sc_nqueue2--; 1746 UBSEC_UNLOCK(sc); 1747 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1748} 1749#endif /* UBSEC_NO_RNG */ 1750 1751static void 1752ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1753{ 1754 bus_addr_t *paddr = (bus_addr_t*) arg; 1755 *paddr = segs->ds_addr; 1756} 1757 1758static int 1759ubsec_dma_malloc( 1760 struct ubsec_softc *sc, 1761 bus_size_t size, 1762 struct ubsec_dma_alloc *dma, 1763 int mapflags 1764) 1765{ 1766 int r; 1767 1768 r = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &dma->dma_map); 1769 if (r != 0) 1770 goto fail_0; 1771 1772 r = bus_dmamem_alloc(sc->sc_dmat, (void**) &dma->dma_vaddr, 1773 BUS_DMA_NOWAIT, &dma->dma_map); 1774 if (r != 0) 1775 goto fail_1; 1776 1777 r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1778 size, 1779 ubsec_dmamap_cb, 1780 &dma->dma_paddr, 1781 mapflags | BUS_DMA_NOWAIT); 1782 if (r != 0) 1783 goto fail_2; 1784 1785 dma->dma_size = size; 1786 return (0); 1787 1788fail_2: 1789 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1790fail_1: 1791 bus_dmamem_free(sc->sc_dmat, dma->dma_vaddr, dma->dma_map); 1792fail_0: 1793 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1794 dma->dma_map = NULL; 1795 return (r); 1796} 1797 1798static void 1799ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1800{ 1801 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1802 bus_dmamem_free(sc->sc_dmat, dma->dma_vaddr, dma->dma_map); 1803 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1804} 1805 1806/* 1807 * Resets the board. Values in the regesters are left as is 1808 * from the reset (i.e. initial values are assigned elsewhere). 1809 */ 1810static void 1811ubsec_reset_board(struct ubsec_softc *sc) 1812{ 1813 volatile u_int32_t ctrl; 1814 1815 ctrl = READ_REG(sc, BS_CTRL); 1816 ctrl |= BS_CTRL_RESET; 1817 WRITE_REG(sc, BS_CTRL, ctrl); 1818 1819 /* 1820 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1821 */ 1822 DELAY(10); 1823} 1824 1825/* 1826 * Init Broadcom registers 1827 */ 1828static void 1829ubsec_init_board(struct ubsec_softc *sc) 1830{ 1831 u_int32_t ctrl; 1832 1833 ctrl = READ_REG(sc, BS_CTRL); 1834 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1835 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1836 1837 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) 1838 ctrl |= BS_CTRL_MCR2INT; 1839 else 1840 ctrl &= ~BS_CTRL_MCR2INT; 1841 1842 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1843 ctrl &= ~BS_CTRL_SWNORM; 1844 1845 WRITE_REG(sc, BS_CTRL, ctrl); 1846} 1847 1848/* 1849 * Init Broadcom PCI registers 1850 */ 1851static void 1852ubsec_init_pciregs(device_t dev) 1853{ 1854#if 0 1855 u_int32_t misc; 1856 1857 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT); 1858 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT)) 1859 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT); 1860 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT)) 1861 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT); 1862 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc); 1863#endif 1864 1865 /* 1866 * This will set the cache line size to 1, this will 1867 * force the BCM58xx chip just to do burst read/writes. 1868 * Cache line read/writes are to slow 1869 */ 1870 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1); 1871} 1872 1873/* 1874 * Clean up after a chip crash. 1875 * It is assumed that the caller in splimp() 1876 */ 1877static void 1878ubsec_cleanchip(struct ubsec_softc *sc) 1879{ 1880 struct ubsec_q *q; 1881 1882 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 1883 q = SIMPLEQ_FIRST(&sc->sc_qchip); 1884 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q, q_next); 1885 ubsec_free_q(sc, q); 1886 } 1887} 1888 1889/* 1890 * free a ubsec_q 1891 * It is assumed that the caller is within spimp() 1892 */ 1893static int 1894ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 1895{ 1896 struct ubsec_q *q2; 1897 struct cryptop *crp; 1898 int npkts; 1899 int i; 1900 1901 npkts = q->q_nstacked_mcrs; 1902 1903 for (i = 0; i < npkts; i++) { 1904 if(q->q_stacked_mcr[i]) { 1905 q2 = q->q_stacked_mcr[i]; 1906 1907 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 1908 m_freem(q2->q_dst_m); 1909 1910 crp = (struct cryptop *)q2->q_crp; 1911 1912 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 1913 1914 crp->crp_etype = EFAULT; 1915 crypto_done(crp); 1916 } else { 1917 break; 1918 } 1919 } 1920 1921 /* 1922 * Free header MCR 1923 */ 1924 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1925 m_freem(q->q_dst_m); 1926 1927 crp = (struct cryptop *)q->q_crp; 1928 1929 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1930 1931 crp->crp_etype = EFAULT; 1932 crypto_done(crp); 1933 return(0); 1934} 1935 1936/* 1937 * Routine to reset the chip and clean up. 1938 * It is assumed that the caller is in splimp() 1939 */ 1940static void 1941ubsec_totalreset(struct ubsec_softc *sc) 1942{ 1943 ubsec_reset_board(sc); 1944 ubsec_init_board(sc); 1945 ubsec_cleanchip(sc); 1946} 1947 1948static int 1949ubsec_dmamap_aligned(struct ubsec_operand *op) 1950{ 1951 int i; 1952 1953 for (i = 0; i < op->nsegs; i++) { 1954 if (op->segs[i].ds_addr & 3) 1955 return (0); 1956 if ((i != (op->nsegs - 1)) && 1957 (op->segs[i].ds_len & 3)) 1958 return (0); 1959 } 1960 return (1); 1961} 1962 1963static void 1964ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 1965{ 1966 switch (q->q_type) { 1967 case UBS_CTXOP_MODEXP: { 1968 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1969 1970 ubsec_dma_free(sc, &me->me_q.q_mcr); 1971 ubsec_dma_free(sc, &me->me_q.q_ctx); 1972 ubsec_dma_free(sc, &me->me_M); 1973 ubsec_dma_free(sc, &me->me_E); 1974 ubsec_dma_free(sc, &me->me_C); 1975 ubsec_dma_free(sc, &me->me_epb); 1976 free(me, M_DEVBUF); 1977 break; 1978 } 1979 case UBS_CTXOP_RSAPRIV: { 1980 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1981 1982 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 1983 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 1984 ubsec_dma_free(sc, &rp->rpr_msgin); 1985 ubsec_dma_free(sc, &rp->rpr_msgout); 1986 free(rp, M_DEVBUF); 1987 break; 1988 } 1989 default: 1990 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type); 1991 break; 1992 } 1993} 1994 1995static int 1996ubsec_kprocess(void *arg, struct cryptkop *krp, int hint) 1997{ 1998 struct ubsec_softc *sc = arg; 1999 int r; 2000 2001 if (krp == NULL || krp->krp_callback == NULL) 2002 return (EINVAL); 2003 2004 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2005 struct ubsec_q2 *q; 2006 2007 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2008 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q, q_next); 2009 ubsec_kfree(sc, q); 2010 } 2011 2012 switch (krp->krp_op) { 2013 case CRK_MOD_EXP: 2014 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2015 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2016 else 2017 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2018 break; 2019 case CRK_MOD_EXP_CRT: 2020 return (ubsec_kprocess_rsapriv(sc, krp, hint)); 2021 default: 2022 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n", 2023 krp->krp_op); 2024 krp->krp_status = EOPNOTSUPP; 2025 crypto_kdone(krp); 2026 return (0); 2027 } 2028 return (0); /* silence compiler */ 2029} 2030 2031/* 2032 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2033 */ 2034static int 2035ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2036{ 2037 struct ubsec_q2_modexp *me; 2038 struct ubsec_mcr *mcr; 2039 struct ubsec_ctx_modexp *ctx; 2040 struct ubsec_pktbuf *epb; 2041 int err = 0; 2042 u_int nbits, normbits, mbits, shiftbits, ebits; 2043 2044 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2045 if (me == NULL) { 2046 err = ENOMEM; 2047 goto errout; 2048 } 2049 bzero(me, sizeof *me); 2050 me->me_krp = krp; 2051 me->me_q.q_type = UBS_CTXOP_MODEXP; 2052 2053 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2054 if (nbits <= 512) 2055 normbits = 512; 2056 else if (nbits <= 768) 2057 normbits = 768; 2058 else if (nbits <= 1024) 2059 normbits = 1024; 2060 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2061 normbits = 1536; 2062 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2063 normbits = 2048; 2064 else { 2065 err = E2BIG; 2066 goto errout; 2067 } 2068 2069 shiftbits = normbits - nbits; 2070 2071 me->me_modbits = nbits; 2072 me->me_shiftbits = shiftbits; 2073 me->me_normbits = normbits; 2074 2075 /* Sanity check: result bits must be >= true modulus bits. */ 2076 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2077 err = ERANGE; 2078 goto errout; 2079 } 2080 2081 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2082 &me->me_q.q_mcr, 0)) { 2083 err = ENOMEM; 2084 goto errout; 2085 } 2086 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2087 2088 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2089 &me->me_q.q_ctx, 0)) { 2090 err = ENOMEM; 2091 goto errout; 2092 } 2093 2094 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2095 if (mbits > nbits) { 2096 err = E2BIG; 2097 goto errout; 2098 } 2099 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2100 err = ENOMEM; 2101 goto errout; 2102 } 2103 ubsec_kshift_r(shiftbits, 2104 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2105 me->me_M.dma_vaddr, normbits); 2106 2107 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2108 err = ENOMEM; 2109 goto errout; 2110 } 2111 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2112 2113 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2114 if (ebits > nbits) { 2115 err = E2BIG; 2116 goto errout; 2117 } 2118 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2119 err = ENOMEM; 2120 goto errout; 2121 } 2122 ubsec_kshift_r(shiftbits, 2123 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2124 me->me_E.dma_vaddr, normbits); 2125 2126 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2127 &me->me_epb, 0)) { 2128 err = ENOMEM; 2129 goto errout; 2130 } 2131 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2132 epb->pb_addr = htole32(me->me_E.dma_paddr); 2133 epb->pb_next = 0; 2134 epb->pb_len = htole32(normbits / 8); 2135 2136#ifdef UBSEC_DEBUG 2137 if (ubsec_debug) { 2138 printf("Epb "); 2139 ubsec_dump_pb(epb); 2140 } 2141#endif 2142 2143 mcr->mcr_pkts = htole16(1); 2144 mcr->mcr_flags = 0; 2145 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2146 mcr->mcr_reserved = 0; 2147 mcr->mcr_pktlen = 0; 2148 2149 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2150 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2151 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2152 2153 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2154 mcr->mcr_opktbuf.pb_next = 0; 2155 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2156 2157#ifdef DIAGNOSTIC 2158 /* Misaligned output buffer will hang the chip. */ 2159 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2160 panic("%s: modexp invalid addr 0x%x\n", 2161 device_get_nameunit(sc->sc_dev), 2162 letoh32(mcr->mcr_opktbuf.pb_addr)); 2163 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2164 panic("%s: modexp invalid len 0x%x\n", 2165 device_get_nameunit(sc->sc_dev), 2166 letoh32(mcr->mcr_opktbuf.pb_len)); 2167#endif 2168 2169 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2170 bzero(ctx, sizeof(*ctx)); 2171 ubsec_kshift_r(shiftbits, 2172 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2173 ctx->me_N, normbits); 2174 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2175 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2176 ctx->me_E_len = htole16(nbits); 2177 ctx->me_N_len = htole16(nbits); 2178 2179#ifdef UBSEC_DEBUG 2180 if (ubsec_debug) { 2181 ubsec_dump_mcr(mcr); 2182 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2183 } 2184#endif 2185 2186 /* 2187 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2188 * everything else. 2189 */ 2190 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, BUS_DMASYNC_PREWRITE); 2191 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, BUS_DMASYNC_PREWRITE); 2192 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, BUS_DMASYNC_PREREAD); 2193 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, BUS_DMASYNC_PREWRITE); 2194 2195 /* Enqueue and we're done... */ 2196 UBSEC_LOCK(sc); 2197 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2198 ubsec_feed2(sc); 2199 ubsecstats.hst_modexp++; 2200 UBSEC_UNLOCK(sc); 2201 2202 return (0); 2203 2204errout: 2205 if (me != NULL) { 2206 if (me->me_q.q_mcr.dma_map != NULL) 2207 ubsec_dma_free(sc, &me->me_q.q_mcr); 2208 if (me->me_q.q_ctx.dma_map != NULL) { 2209 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2210 ubsec_dma_free(sc, &me->me_q.q_ctx); 2211 } 2212 if (me->me_M.dma_map != NULL) { 2213 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2214 ubsec_dma_free(sc, &me->me_M); 2215 } 2216 if (me->me_E.dma_map != NULL) { 2217 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2218 ubsec_dma_free(sc, &me->me_E); 2219 } 2220 if (me->me_C.dma_map != NULL) { 2221 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2222 ubsec_dma_free(sc, &me->me_C); 2223 } 2224 if (me->me_epb.dma_map != NULL) 2225 ubsec_dma_free(sc, &me->me_epb); 2226 free(me, M_DEVBUF); 2227 } 2228 krp->krp_status = err; 2229 crypto_kdone(krp); 2230 return (0); 2231} 2232 2233/* 2234 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2235 */ 2236int 2237ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2238{ 2239 struct ubsec_q2_modexp *me; 2240 struct ubsec_mcr *mcr; 2241 struct ubsec_ctx_modexp *ctx; 2242 struct ubsec_pktbuf *epb; 2243 int err = 0; 2244 u_int nbits, normbits, mbits, shiftbits, ebits; 2245 2246 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2247 if (me == NULL) { 2248 err = ENOMEM; 2249 goto errout; 2250 } 2251 bzero(me, sizeof *me); 2252 me->me_krp = krp; 2253 me->me_q.q_type = UBS_CTXOP_MODEXP; 2254 2255 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2256 if (nbits <= 512) 2257 normbits = 512; 2258 else if (nbits <= 768) 2259 normbits = 768; 2260 else if (nbits <= 1024) 2261 normbits = 1024; 2262 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2263 normbits = 1536; 2264 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2265 normbits = 2048; 2266 else { 2267 err = E2BIG; 2268 goto errout; 2269 } 2270 2271 shiftbits = normbits - nbits; 2272 2273 /* XXX ??? */ 2274 me->me_modbits = nbits; 2275 me->me_shiftbits = shiftbits; 2276 me->me_normbits = normbits; 2277 2278 /* Sanity check: result bits must be >= true modulus bits. */ 2279 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2280 err = ERANGE; 2281 goto errout; 2282 } 2283 2284 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2285 &me->me_q.q_mcr, 0)) { 2286 err = ENOMEM; 2287 goto errout; 2288 } 2289 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2290 2291 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2292 &me->me_q.q_ctx, 0)) { 2293 err = ENOMEM; 2294 goto errout; 2295 } 2296 2297 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2298 if (mbits > nbits) { 2299 err = E2BIG; 2300 goto errout; 2301 } 2302 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2303 err = ENOMEM; 2304 goto errout; 2305 } 2306 bzero(me->me_M.dma_vaddr, normbits / 8); 2307 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2308 me->me_M.dma_vaddr, (mbits + 7) / 8); 2309 2310 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2311 err = ENOMEM; 2312 goto errout; 2313 } 2314 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2315 2316 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2317 if (ebits > nbits) { 2318 err = E2BIG; 2319 goto errout; 2320 } 2321 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2322 err = ENOMEM; 2323 goto errout; 2324 } 2325 bzero(me->me_E.dma_vaddr, normbits / 8); 2326 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2327 me->me_E.dma_vaddr, (ebits + 7) / 8); 2328 2329 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2330 &me->me_epb, 0)) { 2331 err = ENOMEM; 2332 goto errout; 2333 } 2334 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2335 epb->pb_addr = htole32(me->me_E.dma_paddr); 2336 epb->pb_next = 0; 2337 epb->pb_len = htole32((ebits + 7) / 8); 2338 2339#ifdef UBSEC_DEBUG 2340 printf("Epb "); 2341 ubsec_dump_pb(epb); 2342#endif 2343 2344 mcr->mcr_pkts = htole16(1); 2345 mcr->mcr_flags = 0; 2346 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2347 mcr->mcr_reserved = 0; 2348 mcr->mcr_pktlen = 0; 2349 2350 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2351 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2352 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2353 2354 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2355 mcr->mcr_opktbuf.pb_next = 0; 2356 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2357 2358#ifdef DIAGNOSTIC 2359 /* Misaligned output buffer will hang the chip. */ 2360 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2361 panic("%s: modexp invalid addr 0x%x\n", 2362 device_get_nameunit(sc->sc_dev), 2363 letoh32(mcr->mcr_opktbuf.pb_addr)); 2364 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2365 panic("%s: modexp invalid len 0x%x\n", 2366 device_get_nameunit(sc->sc_dev), 2367 letoh32(mcr->mcr_opktbuf.pb_len)); 2368#endif 2369 2370 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2371 bzero(ctx, sizeof(*ctx)); 2372 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2373 (nbits + 7) / 8); 2374 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2375 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2376 ctx->me_E_len = htole16(ebits); 2377 ctx->me_N_len = htole16(nbits); 2378 2379#ifdef UBSEC_DEBUG 2380 if (ubsec_debug) { 2381 ubsec_dump_mcr(mcr); 2382 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2383 } 2384#endif 2385 2386 /* 2387 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2388 * everything else. 2389 */ 2390 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map, BUS_DMASYNC_PREWRITE); 2391 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map, BUS_DMASYNC_PREWRITE); 2392 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map, BUS_DMASYNC_PREREAD); 2393 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map, BUS_DMASYNC_PREWRITE); 2394 2395 /* Enqueue and we're done... */ 2396 UBSEC_LOCK(sc); 2397 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2398 ubsec_feed2(sc); 2399 UBSEC_UNLOCK(sc); 2400 2401 return (0); 2402 2403errout: 2404 if (me != NULL) { 2405 if (me->me_q.q_mcr.dma_map != NULL) 2406 ubsec_dma_free(sc, &me->me_q.q_mcr); 2407 if (me->me_q.q_ctx.dma_map != NULL) { 2408 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2409 ubsec_dma_free(sc, &me->me_q.q_ctx); 2410 } 2411 if (me->me_M.dma_map != NULL) { 2412 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2413 ubsec_dma_free(sc, &me->me_M); 2414 } 2415 if (me->me_E.dma_map != NULL) { 2416 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2417 ubsec_dma_free(sc, &me->me_E); 2418 } 2419 if (me->me_C.dma_map != NULL) { 2420 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2421 ubsec_dma_free(sc, &me->me_C); 2422 } 2423 if (me->me_epb.dma_map != NULL) 2424 ubsec_dma_free(sc, &me->me_epb); 2425 free(me, M_DEVBUF); 2426 } 2427 krp->krp_status = err; 2428 crypto_kdone(krp); 2429 return (0); 2430} 2431 2432static int 2433ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2434{ 2435 struct ubsec_q2_rsapriv *rp = NULL; 2436 struct ubsec_mcr *mcr; 2437 struct ubsec_ctx_rsapriv *ctx; 2438 int err = 0; 2439 u_int padlen, msglen; 2440 2441 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2442 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2443 if (msglen > padlen) 2444 padlen = msglen; 2445 2446 if (padlen <= 256) 2447 padlen = 256; 2448 else if (padlen <= 384) 2449 padlen = 384; 2450 else if (padlen <= 512) 2451 padlen = 512; 2452 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2453 padlen = 768; 2454 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2455 padlen = 1024; 2456 else { 2457 err = E2BIG; 2458 goto errout; 2459 } 2460 2461 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2462 err = E2BIG; 2463 goto errout; 2464 } 2465 2466 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2467 err = E2BIG; 2468 goto errout; 2469 } 2470 2471 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2472 err = E2BIG; 2473 goto errout; 2474 } 2475 2476 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT); 2477 if (rp == NULL) 2478 return (ENOMEM); 2479 bzero(rp, sizeof *rp); 2480 rp->rpr_krp = krp; 2481 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2482 2483 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2484 &rp->rpr_q.q_mcr, 0)) { 2485 err = ENOMEM; 2486 goto errout; 2487 } 2488 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2489 2490 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2491 &rp->rpr_q.q_ctx, 0)) { 2492 err = ENOMEM; 2493 goto errout; 2494 } 2495 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2496 bzero(ctx, sizeof *ctx); 2497 2498 /* Copy in p */ 2499 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2500 &ctx->rpr_buf[0 * (padlen / 8)], 2501 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2502 2503 /* Copy in q */ 2504 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2505 &ctx->rpr_buf[1 * (padlen / 8)], 2506 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2507 2508 /* Copy in dp */ 2509 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2510 &ctx->rpr_buf[2 * (padlen / 8)], 2511 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2512 2513 /* Copy in dq */ 2514 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2515 &ctx->rpr_buf[3 * (padlen / 8)], 2516 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2517 2518 /* Copy in pinv */ 2519 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2520 &ctx->rpr_buf[4 * (padlen / 8)], 2521 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2522 2523 msglen = padlen * 2; 2524 2525 /* Copy in input message (aligned buffer/length). */ 2526 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2527 /* Is this likely? */ 2528 err = E2BIG; 2529 goto errout; 2530 } 2531 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2532 err = ENOMEM; 2533 goto errout; 2534 } 2535 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2536 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2537 rp->rpr_msgin.dma_vaddr, 2538 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2539 2540 /* Prepare space for output message (aligned buffer/length). */ 2541 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2542 /* Is this likely? */ 2543 err = E2BIG; 2544 goto errout; 2545 } 2546 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2547 err = ENOMEM; 2548 goto errout; 2549 } 2550 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2551 2552 mcr->mcr_pkts = htole16(1); 2553 mcr->mcr_flags = 0; 2554 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2555 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2556 mcr->mcr_ipktbuf.pb_next = 0; 2557 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2558 mcr->mcr_reserved = 0; 2559 mcr->mcr_pktlen = htole16(msglen); 2560 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2561 mcr->mcr_opktbuf.pb_next = 0; 2562 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2563 2564#ifdef DIAGNOSTIC 2565 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2566 panic("%s: rsapriv: invalid msgin %x(0x%x)", 2567 device_get_nameunit(sc->sc_dev), 2568 rp->rpr_msgin.dma_paddr, rp->rpr_msgin.dma_size); 2569 } 2570 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2571 panic("%s: rsapriv: invalid msgout %x(0x%x)", 2572 device_get_nameunit(sc->sc_dev), 2573 rp->rpr_msgout.dma_paddr, rp->rpr_msgout.dma_size); 2574 } 2575#endif 2576 2577 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2578 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2579 ctx->rpr_q_len = htole16(padlen); 2580 ctx->rpr_p_len = htole16(padlen); 2581 2582 /* 2583 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2584 * everything else. 2585 */ 2586 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 2587 BUS_DMASYNC_PREWRITE); 2588 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 2589 BUS_DMASYNC_PREREAD); 2590 2591 /* Enqueue and we're done... */ 2592 UBSEC_LOCK(sc); 2593 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2594 ubsec_feed2(sc); 2595 ubsecstats.hst_modexpcrt++; 2596 UBSEC_UNLOCK(sc); 2597 return (0); 2598 2599errout: 2600 if (rp != NULL) { 2601 if (rp->rpr_q.q_mcr.dma_map != NULL) 2602 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2603 if (rp->rpr_msgin.dma_map != NULL) { 2604 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2605 ubsec_dma_free(sc, &rp->rpr_msgin); 2606 } 2607 if (rp->rpr_msgout.dma_map != NULL) { 2608 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2609 ubsec_dma_free(sc, &rp->rpr_msgout); 2610 } 2611 free(rp, M_DEVBUF); 2612 } 2613 krp->krp_status = err; 2614 crypto_kdone(krp); 2615 return (0); 2616} 2617 2618#ifdef UBSEC_DEBUG 2619static void 2620ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2621{ 2622 printf("addr 0x%x (0x%x) next 0x%x\n", 2623 pb->pb_addr, pb->pb_len, pb->pb_next); 2624} 2625 2626static void 2627ubsec_dump_ctx2(struct ubsec_ctx_keyop *c) 2628{ 2629 printf("CTX (0x%x):\n", c->ctx_len); 2630 switch (letoh16(c->ctx_op)) { 2631 case UBS_CTXOP_RNGBYPASS: 2632 case UBS_CTXOP_RNGSHA1: 2633 break; 2634 case UBS_CTXOP_MODEXP: 2635 { 2636 struct ubsec_ctx_modexp *cx = (void *)c; 2637 int i, len; 2638 2639 printf(" Elen %u, Nlen %u\n", 2640 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2641 len = (cx->me_N_len + 7)/8; 2642 for (i = 0; i < len; i++) 2643 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2644 printf("\n"); 2645 break; 2646 } 2647 default: 2648 printf("unknown context: %x\n", c->ctx_op); 2649 } 2650 printf("END CTX\n"); 2651} 2652 2653static void 2654ubsec_dump_mcr(struct ubsec_mcr *mcr) 2655{ 2656 volatile struct ubsec_mcr_add *ma; 2657 int i; 2658 2659 printf("MCR:\n"); 2660 printf(" pkts: %u, flags 0x%x\n", 2661 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2662 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2663 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2664 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2665 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2666 letoh16(ma->mcr_reserved)); 2667 printf(" %d: ipkt ", i); 2668 ubsec_dump_pb(&ma->mcr_ipktbuf); 2669 printf(" %d: opkt ", i); 2670 ubsec_dump_pb(&ma->mcr_opktbuf); 2671 ma++; 2672 } 2673 printf("END MCR\n"); 2674} 2675#endif /* UBSEC_DEBUG */ 2676 2677/* 2678 * Return the number of significant bits of a big number. 2679 */ 2680static int 2681ubsec_ksigbits(struct crparam *cr) 2682{ 2683 u_int plen = (cr->crp_nbits + 7) / 8; 2684 int i, sig = plen * 8; 2685 u_int8_t c, *p = cr->crp_p; 2686 2687 for (i = plen - 1; i >= 0; i--) { 2688 c = p[i]; 2689 if (c != 0) { 2690 while ((c & 0x80) == 0) { 2691 sig--; 2692 c <<= 1; 2693 } 2694 break; 2695 } 2696 sig -= 8; 2697 } 2698 return (sig); 2699} 2700 2701static void 2702ubsec_kshift_r( 2703 u_int shiftbits, 2704 u_int8_t *src, u_int srcbits, 2705 u_int8_t *dst, u_int dstbits) 2706{ 2707 u_int slen, dlen; 2708 int i, si, di, n; 2709 2710 slen = (srcbits + 7) / 8; 2711 dlen = (dstbits + 7) / 8; 2712 2713 for (i = 0; i < slen; i++) 2714 dst[i] = src[i]; 2715 for (i = 0; i < dlen - slen; i++) 2716 dst[slen + i] = 0; 2717 2718 n = shiftbits / 8; 2719 if (n != 0) { 2720 si = dlen - n - 1; 2721 di = dlen - 1; 2722 while (si >= 0) 2723 dst[di--] = dst[si--]; 2724 while (di >= 0) 2725 dst[di--] = 0; 2726 } 2727 2728 n = shiftbits % 8; 2729 if (n != 0) { 2730 for (i = dlen - 1; i > 0; i--) 2731 dst[i] = (dst[i] << n) | 2732 (dst[i - 1] >> (8 - n)); 2733 dst[0] = dst[0] << n; 2734 } 2735} 2736 2737static void 2738ubsec_kshift_l( 2739 u_int shiftbits, 2740 u_int8_t *src, u_int srcbits, 2741 u_int8_t *dst, u_int dstbits) 2742{ 2743 int slen, dlen, i, n; 2744 2745 slen = (srcbits + 7) / 8; 2746 dlen = (dstbits + 7) / 8; 2747 2748 n = shiftbits / 8; 2749 for (i = 0; i < slen; i++) 2750 dst[i] = src[i + n]; 2751 for (i = 0; i < dlen - slen; i++) 2752 dst[slen + i] = 0; 2753 2754 n = shiftbits % 8; 2755 if (n != 0) { 2756 for (i = 0; i < (dlen - 1); i++) 2757 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2758 dst[dlen - 1] = dst[dlen - 1] >> n; 2759 } 2760} 2761