uart_dev_ns8250.c revision 255031
1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include "opt_platform.h" 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_ns8250.c 255031 2013-08-29 16:26:04Z marcel $"); 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/bus.h> 35#include <sys/conf.h> 36#include <sys/kernel.h> 37#include <sys/sysctl.h> 38#include <machine/bus.h> 39 40#ifdef FDT 41#include <dev/fdt/fdt_common.h> 42#include <dev/ofw/ofw_bus.h> 43#include <dev/ofw/ofw_bus_subr.h> 44#endif 45 46#include <dev/uart/uart.h> 47#include <dev/uart/uart_cpu.h> 48#include <dev/uart/uart_bus.h> 49#include <dev/uart/uart_dev_ns8250.h> 50 51#include <dev/ic/ns16550.h> 52 53#include "uart_if.h" 54 55#define DEFAULT_RCLK 1843200 56 57static int broken_txfifo = 0; 58SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN, 59 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 60TUNABLE_INT("hw.broken_txfifo", &broken_txfifo); 61 62/* 63 * Clear pending interrupts. THRE is cleared by reading IIR. Data 64 * that may have been received gets lost here. 65 */ 66static void 67ns8250_clrint(struct uart_bas *bas) 68{ 69 uint8_t iir, lsr; 70 71 iir = uart_getreg(bas, REG_IIR); 72 while ((iir & IIR_NOPEND) == 0) { 73 iir &= IIR_IMASK; 74 if (iir == IIR_RLS) { 75 lsr = uart_getreg(bas, REG_LSR); 76 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 77 (void)uart_getreg(bas, REG_DATA); 78 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 79 (void)uart_getreg(bas, REG_DATA); 80 else if (iir == IIR_MLSC) 81 (void)uart_getreg(bas, REG_MSR); 82 uart_barrier(bas); 83 iir = uart_getreg(bas, REG_IIR); 84 } 85} 86 87static int 88ns8250_delay(struct uart_bas *bas) 89{ 90 int divisor; 91 u_char lcr; 92 93 lcr = uart_getreg(bas, REG_LCR); 94 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 95 uart_barrier(bas); 96 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 97 uart_barrier(bas); 98 uart_setreg(bas, REG_LCR, lcr); 99 uart_barrier(bas); 100 101 /* 1/10th the time to transmit 1 character (estimate). */ 102 if (divisor <= 134) 103 return (16000000 * divisor / bas->rclk); 104 return (16000 * divisor / (bas->rclk / 1000)); 105} 106 107static int 108ns8250_divisor(int rclk, int baudrate) 109{ 110 int actual_baud, divisor; 111 int error; 112 113 if (baudrate == 0) 114 return (0); 115 116 divisor = (rclk / (baudrate << 3) + 1) >> 1; 117 if (divisor == 0 || divisor >= 65536) 118 return (0); 119 actual_baud = rclk / (divisor << 4); 120 121 /* 10 times error in percent: */ 122 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 123 124 /* 3.0% maximum error tolerance: */ 125 if (error < -30 || error > 30) 126 return (0); 127 128 return (divisor); 129} 130 131static int 132ns8250_drain(struct uart_bas *bas, int what) 133{ 134 int delay, limit; 135 136 delay = ns8250_delay(bas); 137 138 if (what & UART_DRAIN_TRANSMITTER) { 139 /* 140 * Pick an arbitrary high limit to avoid getting stuck in 141 * an infinite loop when the hardware is broken. Make the 142 * limit high enough to handle large FIFOs. 143 */ 144 limit = 10*1024; 145 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 146 DELAY(delay); 147 if (limit == 0) { 148 /* printf("ns8250: transmitter appears stuck... "); */ 149 return (EIO); 150 } 151 } 152 153 if (what & UART_DRAIN_RECEIVER) { 154 /* 155 * Pick an arbitrary high limit to avoid getting stuck in 156 * an infinite loop when the hardware is broken. Make the 157 * limit high enough to handle large FIFOs and integrated 158 * UARTs. The HP rx2600 for example has 3 UARTs on the 159 * management board that tend to get a lot of data send 160 * to it when the UART is first activated. 161 */ 162 limit=10*4096; 163 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 164 (void)uart_getreg(bas, REG_DATA); 165 uart_barrier(bas); 166 DELAY(delay << 2); 167 } 168 if (limit == 0) { 169 /* printf("ns8250: receiver appears broken... "); */ 170 return (EIO); 171 } 172 } 173 174 return (0); 175} 176 177/* 178 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 179 * drained. WARNING: this function clobbers the FIFO setting! 180 */ 181static void 182ns8250_flush(struct uart_bas *bas, int what) 183{ 184 uint8_t fcr; 185 186 fcr = FCR_ENABLE; 187 if (what & UART_FLUSH_TRANSMITTER) 188 fcr |= FCR_XMT_RST; 189 if (what & UART_FLUSH_RECEIVER) 190 fcr |= FCR_RCV_RST; 191 uart_setreg(bas, REG_FCR, fcr); 192 uart_barrier(bas); 193} 194 195static int 196ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 197 int parity) 198{ 199 int divisor; 200 uint8_t lcr; 201 202 lcr = 0; 203 if (databits >= 8) 204 lcr |= LCR_8BITS; 205 else if (databits == 7) 206 lcr |= LCR_7BITS; 207 else if (databits == 6) 208 lcr |= LCR_6BITS; 209 else 210 lcr |= LCR_5BITS; 211 if (stopbits > 1) 212 lcr |= LCR_STOPB; 213 lcr |= parity << 3; 214 215 /* Set baudrate. */ 216 if (baudrate > 0) { 217 divisor = ns8250_divisor(bas->rclk, baudrate); 218 if (divisor == 0) 219 return (EINVAL); 220 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 221 uart_barrier(bas); 222 uart_setreg(bas, REG_DLL, divisor & 0xff); 223 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 224 uart_barrier(bas); 225 } 226 227 /* Set LCR and clear DLAB. */ 228 uart_setreg(bas, REG_LCR, lcr); 229 uart_barrier(bas); 230 return (0); 231} 232 233/* 234 * Low-level UART interface. 235 */ 236static int ns8250_probe(struct uart_bas *bas); 237static void ns8250_init(struct uart_bas *bas, int, int, int, int); 238static void ns8250_term(struct uart_bas *bas); 239static void ns8250_putc(struct uart_bas *bas, int); 240static int ns8250_rxready(struct uart_bas *bas); 241static int ns8250_getc(struct uart_bas *bas, struct mtx *); 242 243struct uart_ops uart_ns8250_ops = { 244 .probe = ns8250_probe, 245 .init = ns8250_init, 246 .term = ns8250_term, 247 .putc = ns8250_putc, 248 .rxready = ns8250_rxready, 249 .getc = ns8250_getc, 250}; 251 252static int 253ns8250_probe(struct uart_bas *bas) 254{ 255 u_char val; 256 257 /* Check known 0 bits that don't depend on DLAB. */ 258 val = uart_getreg(bas, REG_IIR); 259 if (val & 0x30) 260 return (ENXIO); 261 /* 262 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 263 * chip, but otherwise doesn't seem to have a function. In 264 * other words, uart(4) works regardless. Ignore that bit so 265 * the probe succeeds. 266 */ 267 val = uart_getreg(bas, REG_MCR); 268 if (val & 0xa0) 269 return (ENXIO); 270 271 return (0); 272} 273 274static void 275ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 276 int parity) 277{ 278 u_char ier; 279 280 if (bas->rclk == 0) 281 bas->rclk = DEFAULT_RCLK; 282 ns8250_param(bas, baudrate, databits, stopbits, parity); 283 284 /* Disable all interrupt sources. */ 285 /* 286 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 287 * UARTs split the receive time-out interrupt bit out separately as 288 * 0x10. This gets handled by ier_mask and ier_rxbits below. 289 */ 290 ier = uart_getreg(bas, REG_IER) & 0xe0; 291 uart_setreg(bas, REG_IER, ier); 292 uart_barrier(bas); 293 294 /* Disable the FIFO (if present). */ 295 uart_setreg(bas, REG_FCR, 0); 296 uart_barrier(bas); 297 298 /* Set RTS & DTR. */ 299 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 300 uart_barrier(bas); 301 302 ns8250_clrint(bas); 303} 304 305static void 306ns8250_term(struct uart_bas *bas) 307{ 308 309 /* Clear RTS & DTR. */ 310 uart_setreg(bas, REG_MCR, MCR_IE); 311 uart_barrier(bas); 312} 313 314static void 315ns8250_putc(struct uart_bas *bas, int c) 316{ 317 int limit; 318 319 limit = 250000; 320 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 321 DELAY(4); 322 uart_setreg(bas, REG_DATA, c); 323 uart_barrier(bas); 324 limit = 250000; 325 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 326 DELAY(4); 327} 328 329static int 330ns8250_rxready(struct uart_bas *bas) 331{ 332 333 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 334} 335 336static int 337ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 338{ 339 int c; 340 341 uart_lock(hwmtx); 342 343 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 344 uart_unlock(hwmtx); 345 DELAY(4); 346 uart_lock(hwmtx); 347 } 348 349 c = uart_getreg(bas, REG_DATA); 350 351 uart_unlock(hwmtx); 352 353 return (c); 354} 355 356static kobj_method_t ns8250_methods[] = { 357 KOBJMETHOD(uart_attach, ns8250_bus_attach), 358 KOBJMETHOD(uart_detach, ns8250_bus_detach), 359 KOBJMETHOD(uart_flush, ns8250_bus_flush), 360 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 361 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 362 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 363 KOBJMETHOD(uart_param, ns8250_bus_param), 364 KOBJMETHOD(uart_probe, ns8250_bus_probe), 365 KOBJMETHOD(uart_receive, ns8250_bus_receive), 366 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 367 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 368 { 0, 0 } 369}; 370 371struct uart_class uart_ns8250_class = { 372 "ns8250", 373 ns8250_methods, 374 sizeof(struct ns8250_softc), 375 .uc_ops = &uart_ns8250_ops, 376 .uc_range = 8, 377 .uc_rclk = DEFAULT_RCLK 378}; 379 380#define SIGCHG(c, i, s, d) \ 381 if (c) { \ 382 i |= (i & s) ? s : s | d; \ 383 } else { \ 384 i = (i & s) ? (i & ~s) | d : i; \ 385 } 386 387int 388ns8250_bus_attach(struct uart_softc *sc) 389{ 390 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 391 struct uart_bas *bas; 392 unsigned int ivar; 393#ifdef FDT 394 phandle_t node; 395 pcell_t cell; 396#endif 397 398 ns8250->busy_detect = 0; 399 400#ifdef FDT 401 /* 402 * Check whether uart requires to read USR reg when IIR_BUSY and 403 * has broken txfifo. 404 */ 405 node = ofw_bus_get_node(sc->sc_dev); 406 if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 407 ns8250->busy_detect = 1; 408 if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 409 broken_txfifo = 1; 410#endif 411 412 bas = &sc->sc_bas; 413 414 ns8250->mcr = uart_getreg(bas, REG_MCR); 415 ns8250->fcr = FCR_ENABLE; 416 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 417 &ivar)) { 418 if (UART_FLAGS_FCR_RX_LOW(ivar)) 419 ns8250->fcr |= FCR_RX_LOW; 420 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 421 ns8250->fcr |= FCR_RX_MEDL; 422 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 423 ns8250->fcr |= FCR_RX_HIGH; 424 else 425 ns8250->fcr |= FCR_RX_MEDH; 426 } else 427 ns8250->fcr |= FCR_RX_MEDH; 428 429 /* Get IER mask */ 430 ivar = 0xf0; 431 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 432 &ivar); 433 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 434 435 /* Get IER RX interrupt bits */ 436 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 437 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 438 &ivar); 439 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 440 441 uart_setreg(bas, REG_FCR, ns8250->fcr); 442 uart_barrier(bas); 443 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 444 445 if (ns8250->mcr & MCR_DTR) 446 sc->sc_hwsig |= SER_DTR; 447 if (ns8250->mcr & MCR_RTS) 448 sc->sc_hwsig |= SER_RTS; 449 ns8250_bus_getsig(sc); 450 451 ns8250_clrint(bas); 452 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 453 ns8250->ier |= ns8250->ier_rxbits; 454 uart_setreg(bas, REG_IER, ns8250->ier); 455 uart_barrier(bas); 456 457 /* 458 * Timing of the H/W access was changed with r253161 of uart_core.c 459 * It has been observed that an ITE IT8513E would signal a break 460 * condition with pretty much every character it received, unless 461 * it had enough time to settle between ns8250_bus_attach() and 462 * ns8250_bus_ipend() -- which it accidentally had before r253161. 463 * It's not understood why the UART chip behaves this way and it 464 * could very well be that the DELAY make the H/W work in the same 465 * accidental manner as before. More analysis is warranted, but 466 * at least now we fixed a known regression. 467 */ 468 DELAY(150); 469 return (0); 470} 471 472int 473ns8250_bus_detach(struct uart_softc *sc) 474{ 475 struct ns8250_softc *ns8250; 476 struct uart_bas *bas; 477 u_char ier; 478 479 ns8250 = (struct ns8250_softc *)sc; 480 bas = &sc->sc_bas; 481 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 482 uart_setreg(bas, REG_IER, ier); 483 uart_barrier(bas); 484 ns8250_clrint(bas); 485 return (0); 486} 487 488int 489ns8250_bus_flush(struct uart_softc *sc, int what) 490{ 491 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 492 struct uart_bas *bas; 493 int error; 494 495 bas = &sc->sc_bas; 496 uart_lock(sc->sc_hwmtx); 497 if (sc->sc_rxfifosz > 1) { 498 ns8250_flush(bas, what); 499 uart_setreg(bas, REG_FCR, ns8250->fcr); 500 uart_barrier(bas); 501 error = 0; 502 } else 503 error = ns8250_drain(bas, what); 504 uart_unlock(sc->sc_hwmtx); 505 return (error); 506} 507 508int 509ns8250_bus_getsig(struct uart_softc *sc) 510{ 511 uint32_t new, old, sig; 512 uint8_t msr; 513 514 do { 515 old = sc->sc_hwsig; 516 sig = old; 517 uart_lock(sc->sc_hwmtx); 518 msr = uart_getreg(&sc->sc_bas, REG_MSR); 519 uart_unlock(sc->sc_hwmtx); 520 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 521 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 522 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 523 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 524 new = sig & ~SER_MASK_DELTA; 525 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 526 return (sig); 527} 528 529int 530ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 531{ 532 struct uart_bas *bas; 533 int baudrate, divisor, error; 534 uint8_t efr, lcr; 535 536 bas = &sc->sc_bas; 537 error = 0; 538 uart_lock(sc->sc_hwmtx); 539 switch (request) { 540 case UART_IOCTL_BREAK: 541 lcr = uart_getreg(bas, REG_LCR); 542 if (data) 543 lcr |= LCR_SBREAK; 544 else 545 lcr &= ~LCR_SBREAK; 546 uart_setreg(bas, REG_LCR, lcr); 547 uart_barrier(bas); 548 break; 549 case UART_IOCTL_IFLOW: 550 lcr = uart_getreg(bas, REG_LCR); 551 uart_barrier(bas); 552 uart_setreg(bas, REG_LCR, 0xbf); 553 uart_barrier(bas); 554 efr = uart_getreg(bas, REG_EFR); 555 if (data) 556 efr |= EFR_RTS; 557 else 558 efr &= ~EFR_RTS; 559 uart_setreg(bas, REG_EFR, efr); 560 uart_barrier(bas); 561 uart_setreg(bas, REG_LCR, lcr); 562 uart_barrier(bas); 563 break; 564 case UART_IOCTL_OFLOW: 565 lcr = uart_getreg(bas, REG_LCR); 566 uart_barrier(bas); 567 uart_setreg(bas, REG_LCR, 0xbf); 568 uart_barrier(bas); 569 efr = uart_getreg(bas, REG_EFR); 570 if (data) 571 efr |= EFR_CTS; 572 else 573 efr &= ~EFR_CTS; 574 uart_setreg(bas, REG_EFR, efr); 575 uart_barrier(bas); 576 uart_setreg(bas, REG_LCR, lcr); 577 uart_barrier(bas); 578 break; 579 case UART_IOCTL_BAUD: 580 lcr = uart_getreg(bas, REG_LCR); 581 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 582 uart_barrier(bas); 583 divisor = uart_getreg(bas, REG_DLL) | 584 (uart_getreg(bas, REG_DLH) << 8); 585 uart_barrier(bas); 586 uart_setreg(bas, REG_LCR, lcr); 587 uart_barrier(bas); 588 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 589 if (baudrate > 0) 590 *(int*)data = baudrate; 591 else 592 error = ENXIO; 593 break; 594 default: 595 error = EINVAL; 596 break; 597 } 598 uart_unlock(sc->sc_hwmtx); 599 return (error); 600} 601 602int 603ns8250_bus_ipend(struct uart_softc *sc) 604{ 605 struct uart_bas *bas; 606 struct ns8250_softc *ns8250; 607 int ipend; 608 uint8_t iir, lsr; 609 610 ns8250 = (struct ns8250_softc *)sc; 611 bas = &sc->sc_bas; 612 uart_lock(sc->sc_hwmtx); 613 iir = uart_getreg(bas, REG_IIR); 614 615 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 616 (void)uart_getreg(bas, DW_REG_USR); 617 uart_unlock(sc->sc_hwmtx); 618 return (0); 619 } 620 if (iir & IIR_NOPEND) { 621 uart_unlock(sc->sc_hwmtx); 622 return (0); 623 } 624 ipend = 0; 625 if (iir & IIR_RXRDY) { 626 lsr = uart_getreg(bas, REG_LSR); 627 if (lsr & LSR_OE) 628 ipend |= SER_INT_OVERRUN; 629 if (lsr & LSR_BI) 630 ipend |= SER_INT_BREAK; 631 if (lsr & LSR_RXRDY) 632 ipend |= SER_INT_RXREADY; 633 } else { 634 if (iir & IIR_TXRDY) { 635 ipend |= SER_INT_TXIDLE; 636 uart_setreg(bas, REG_IER, ns8250->ier); 637 } else 638 ipend |= SER_INT_SIGCHG; 639 } 640 if (ipend == 0) 641 ns8250_clrint(bas); 642 uart_unlock(sc->sc_hwmtx); 643 return (ipend); 644} 645 646int 647ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 648 int stopbits, int parity) 649{ 650 struct uart_bas *bas; 651 int error; 652 653 bas = &sc->sc_bas; 654 uart_lock(sc->sc_hwmtx); 655 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 656 uart_unlock(sc->sc_hwmtx); 657 return (error); 658} 659 660int 661ns8250_bus_probe(struct uart_softc *sc) 662{ 663 struct ns8250_softc *ns8250; 664 struct uart_bas *bas; 665 int count, delay, error, limit; 666 uint8_t lsr, mcr, ier; 667 668 ns8250 = (struct ns8250_softc *)sc; 669 bas = &sc->sc_bas; 670 671 error = ns8250_probe(bas); 672 if (error) 673 return (error); 674 675 mcr = MCR_IE; 676 if (sc->sc_sysdev == NULL) { 677 /* By using ns8250_init() we also set DTR and RTS. */ 678 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 679 } else 680 mcr |= MCR_DTR | MCR_RTS; 681 682 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 683 if (error) 684 return (error); 685 686 /* 687 * Set loopback mode. This avoids having garbage on the wire and 688 * also allows us send and receive data. We set DTR and RTS to 689 * avoid the possibility that automatic flow-control prevents 690 * any data from being sent. 691 */ 692 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 693 uart_barrier(bas); 694 695 /* 696 * Enable FIFOs. And check that the UART has them. If not, we're 697 * done. Since this is the first time we enable the FIFOs, we reset 698 * them. 699 */ 700 uart_setreg(bas, REG_FCR, FCR_ENABLE); 701 uart_barrier(bas); 702 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 703 /* 704 * NS16450 or INS8250. We don't bother to differentiate 705 * between them. They're too old to be interesting. 706 */ 707 uart_setreg(bas, REG_MCR, mcr); 708 uart_barrier(bas); 709 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 710 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 711 return (0); 712 } 713 714 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 715 uart_barrier(bas); 716 717 count = 0; 718 delay = ns8250_delay(bas); 719 720 /* We have FIFOs. Drain the transmitter and receiver. */ 721 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 722 if (error) { 723 uart_setreg(bas, REG_MCR, mcr); 724 uart_setreg(bas, REG_FCR, 0); 725 uart_barrier(bas); 726 goto describe; 727 } 728 729 /* 730 * We should have a sufficiently clean "pipe" to determine the 731 * size of the FIFOs. We send as much characters as is reasonable 732 * and wait for the overflow bit in the LSR register to be 733 * asserted, counting the characters as we send them. Based on 734 * that count we know the FIFO size. 735 */ 736 do { 737 uart_setreg(bas, REG_DATA, 0); 738 uart_barrier(bas); 739 count++; 740 741 limit = 30; 742 lsr = 0; 743 /* 744 * LSR bits are cleared upon read, so we must accumulate 745 * them to be able to test LSR_OE below. 746 */ 747 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 748 --limit) 749 DELAY(delay); 750 if (limit == 0) { 751 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 752 uart_setreg(bas, REG_IER, ier); 753 uart_setreg(bas, REG_MCR, mcr); 754 uart_setreg(bas, REG_FCR, 0); 755 uart_barrier(bas); 756 count = 0; 757 goto describe; 758 } 759 } while ((lsr & LSR_OE) == 0 && count < 130); 760 count--; 761 762 uart_setreg(bas, REG_MCR, mcr); 763 764 /* Reset FIFOs. */ 765 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 766 767 describe: 768 if (count >= 14 && count <= 16) { 769 sc->sc_rxfifosz = 16; 770 device_set_desc(sc->sc_dev, "16550 or compatible"); 771 } else if (count >= 28 && count <= 32) { 772 sc->sc_rxfifosz = 32; 773 device_set_desc(sc->sc_dev, "16650 or compatible"); 774 } else if (count >= 56 && count <= 64) { 775 sc->sc_rxfifosz = 64; 776 device_set_desc(sc->sc_dev, "16750 or compatible"); 777 } else if (count >= 112 && count <= 128) { 778 sc->sc_rxfifosz = 128; 779 device_set_desc(sc->sc_dev, "16950 or compatible"); 780 } else { 781 sc->sc_rxfifosz = 16; 782 device_set_desc(sc->sc_dev, 783 "Non-standard ns8250 class UART with FIFOs"); 784 } 785 786 /* 787 * Force the Tx FIFO size to 16 bytes for now. We don't program the 788 * Tx trigger. Also, we assume that all data has been sent when the 789 * interrupt happens. 790 */ 791 sc->sc_txfifosz = 16; 792 793#if 0 794 /* 795 * XXX there are some issues related to hardware flow control and 796 * it's likely that uart(4) is the cause. This basicly needs more 797 * investigation, but we avoid using for hardware flow control 798 * until then. 799 */ 800 /* 16650s or higher have automatic flow control. */ 801 if (sc->sc_rxfifosz > 16) { 802 sc->sc_hwiflow = 1; 803 sc->sc_hwoflow = 1; 804 } 805#endif 806 807 return (0); 808} 809 810int 811ns8250_bus_receive(struct uart_softc *sc) 812{ 813 struct uart_bas *bas; 814 int xc; 815 uint8_t lsr; 816 817 bas = &sc->sc_bas; 818 uart_lock(sc->sc_hwmtx); 819 lsr = uart_getreg(bas, REG_LSR); 820 while (lsr & LSR_RXRDY) { 821 if (uart_rx_full(sc)) { 822 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 823 break; 824 } 825 xc = uart_getreg(bas, REG_DATA); 826 if (lsr & LSR_FE) 827 xc |= UART_STAT_FRAMERR; 828 if (lsr & LSR_PE) 829 xc |= UART_STAT_PARERR; 830 uart_rx_put(sc, xc); 831 lsr = uart_getreg(bas, REG_LSR); 832 } 833 /* Discard everything left in the Rx FIFO. */ 834 while (lsr & LSR_RXRDY) { 835 (void)uart_getreg(bas, REG_DATA); 836 uart_barrier(bas); 837 lsr = uart_getreg(bas, REG_LSR); 838 } 839 uart_unlock(sc->sc_hwmtx); 840 return (0); 841} 842 843int 844ns8250_bus_setsig(struct uart_softc *sc, int sig) 845{ 846 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 847 struct uart_bas *bas; 848 uint32_t new, old; 849 850 bas = &sc->sc_bas; 851 do { 852 old = sc->sc_hwsig; 853 new = old; 854 if (sig & SER_DDTR) { 855 SIGCHG(sig & SER_DTR, new, SER_DTR, 856 SER_DDTR); 857 } 858 if (sig & SER_DRTS) { 859 SIGCHG(sig & SER_RTS, new, SER_RTS, 860 SER_DRTS); 861 } 862 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 863 uart_lock(sc->sc_hwmtx); 864 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 865 if (new & SER_DTR) 866 ns8250->mcr |= MCR_DTR; 867 if (new & SER_RTS) 868 ns8250->mcr |= MCR_RTS; 869 uart_setreg(bas, REG_MCR, ns8250->mcr); 870 uart_barrier(bas); 871 uart_unlock(sc->sc_hwmtx); 872 return (0); 873} 874 875int 876ns8250_bus_transmit(struct uart_softc *sc) 877{ 878 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 879 struct uart_bas *bas; 880 int i; 881 882 bas = &sc->sc_bas; 883 uart_lock(sc->sc_hwmtx); 884 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 885 ; 886 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 887 uart_barrier(bas); 888 for (i = 0; i < sc->sc_txdatasz; i++) { 889 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 890 uart_barrier(bas); 891 } 892 if (broken_txfifo) 893 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 894 else 895 sc->sc_txbusy = 1; 896 uart_unlock(sc->sc_hwmtx); 897 if (broken_txfifo) 898 uart_sched_softih(sc, SER_INT_TXIDLE); 899 return (0); 900} 901