uart_dev_ns8250.c revision 227032
1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_ns8250.c 227032 2011-11-02 20:45:44Z cognet $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <machine/bus.h> 35 36#include <dev/uart/uart.h> 37#include <dev/uart/uart_cpu.h> 38#include <dev/uart/uart_bus.h> 39 40#include <dev/ic/ns16550.h> 41 42#include "uart_if.h" 43 44#define DEFAULT_RCLK 1843200 45 46/* 47 * Clear pending interrupts. THRE is cleared by reading IIR. Data 48 * that may have been received gets lost here. 49 */ 50static void 51ns8250_clrint(struct uart_bas *bas) 52{ 53 uint8_t iir, lsr; 54 55 iir = uart_getreg(bas, REG_IIR); 56 while ((iir & IIR_NOPEND) == 0) { 57 iir &= IIR_IMASK; 58 if (iir == IIR_RLS) { 59 lsr = uart_getreg(bas, REG_LSR); 60 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 61 (void)uart_getreg(bas, REG_DATA); 62 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 63 (void)uart_getreg(bas, REG_DATA); 64 else if (iir == IIR_MLSC) 65 (void)uart_getreg(bas, REG_MSR); 66 uart_barrier(bas); 67 iir = uart_getreg(bas, REG_IIR); 68 } 69} 70 71static int 72ns8250_delay(struct uart_bas *bas) 73{ 74 int divisor; 75 u_char lcr; 76 77 lcr = uart_getreg(bas, REG_LCR); 78 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 79 uart_barrier(bas); 80 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 81 uart_barrier(bas); 82 uart_setreg(bas, REG_LCR, lcr); 83 uart_barrier(bas); 84 85 /* 1/10th the time to transmit 1 character (estimate). */ 86 if (divisor <= 134) 87 return (16000000 * divisor / bas->rclk); 88 return (16000 * divisor / (bas->rclk / 1000)); 89} 90 91static int 92ns8250_divisor(int rclk, int baudrate) 93{ 94 int actual_baud, divisor; 95 int error; 96 97 if (baudrate == 0) 98 return (0); 99 100 divisor = (rclk / (baudrate << 3) + 1) >> 1; 101 if (divisor == 0 || divisor >= 65536) 102 return (0); 103 actual_baud = rclk / (divisor << 4); 104 105 /* 10 times error in percent: */ 106 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 107 108 /* 3.0% maximum error tolerance: */ 109 if (error < -30 || error > 30) 110 return (0); 111 112 return (divisor); 113} 114 115static int 116ns8250_drain(struct uart_bas *bas, int what) 117{ 118 int delay, limit; 119 120 delay = ns8250_delay(bas); 121 122 if (what & UART_DRAIN_TRANSMITTER) { 123 /* 124 * Pick an arbitrary high limit to avoid getting stuck in 125 * an infinite loop when the hardware is broken. Make the 126 * limit high enough to handle large FIFOs. 127 */ 128 limit = 10*1024; 129 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 130 DELAY(delay); 131 if (limit == 0) { 132 /* printf("ns8250: transmitter appears stuck... "); */ 133 return (EIO); 134 } 135 } 136 137 if (what & UART_DRAIN_RECEIVER) { 138 /* 139 * Pick an arbitrary high limit to avoid getting stuck in 140 * an infinite loop when the hardware is broken. Make the 141 * limit high enough to handle large FIFOs and integrated 142 * UARTs. The HP rx2600 for example has 3 UARTs on the 143 * management board that tend to get a lot of data send 144 * to it when the UART is first activated. 145 */ 146 limit=10*4096; 147 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 148 (void)uart_getreg(bas, REG_DATA); 149 uart_barrier(bas); 150 DELAY(delay << 2); 151 } 152 if (limit == 0) { 153 /* printf("ns8250: receiver appears broken... "); */ 154 return (EIO); 155 } 156 } 157 158 return (0); 159} 160 161/* 162 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 163 * drained. WARNING: this function clobbers the FIFO setting! 164 */ 165static void 166ns8250_flush(struct uart_bas *bas, int what) 167{ 168 uint8_t fcr; 169 170 fcr = FCR_ENABLE; 171 if (what & UART_FLUSH_TRANSMITTER) 172 fcr |= FCR_XMT_RST; 173 if (what & UART_FLUSH_RECEIVER) 174 fcr |= FCR_RCV_RST; 175 uart_setreg(bas, REG_FCR, fcr); 176 uart_barrier(bas); 177} 178 179static int 180ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 181 int parity) 182{ 183 int divisor; 184 uint8_t lcr; 185 186 lcr = 0; 187 if (databits >= 8) 188 lcr |= LCR_8BITS; 189 else if (databits == 7) 190 lcr |= LCR_7BITS; 191 else if (databits == 6) 192 lcr |= LCR_6BITS; 193 else 194 lcr |= LCR_5BITS; 195 if (stopbits > 1) 196 lcr |= LCR_STOPB; 197 lcr |= parity << 3; 198 199 /* Set baudrate. */ 200 if (baudrate > 0) { 201 divisor = ns8250_divisor(bas->rclk, baudrate); 202 if (divisor == 0) 203 return (EINVAL); 204 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 205 uart_barrier(bas); 206 uart_setreg(bas, REG_DLL, divisor & 0xff); 207 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 208 uart_barrier(bas); 209 } 210 211 /* Set LCR and clear DLAB. */ 212 uart_setreg(bas, REG_LCR, lcr); 213 uart_barrier(bas); 214 return (0); 215} 216 217/* 218 * Low-level UART interface. 219 */ 220static int ns8250_probe(struct uart_bas *bas); 221static void ns8250_init(struct uart_bas *bas, int, int, int, int); 222static void ns8250_term(struct uart_bas *bas); 223static void ns8250_putc(struct uart_bas *bas, int); 224static int ns8250_rxready(struct uart_bas *bas); 225static int ns8250_getc(struct uart_bas *bas, struct mtx *); 226 227static struct uart_ops uart_ns8250_ops = { 228 .probe = ns8250_probe, 229 .init = ns8250_init, 230 .term = ns8250_term, 231 .putc = ns8250_putc, 232 .rxready = ns8250_rxready, 233 .getc = ns8250_getc, 234}; 235 236static int 237ns8250_probe(struct uart_bas *bas) 238{ 239 u_char val; 240 241 /* Check known 0 bits that don't depend on DLAB. */ 242 val = uart_getreg(bas, REG_IIR); 243 if (val & 0x30) 244 return (ENXIO); 245 /* 246 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 247 * chip, but otherwise doesn't seem to have a function. In 248 * other words, uart(4) works regardless. Ignore that bit so 249 * the probe succeeds. 250 */ 251 val = uart_getreg(bas, REG_MCR); 252 if (val & 0xa0) 253 return (ENXIO); 254 255 return (0); 256} 257 258static void 259ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 260 int parity) 261{ 262 u_char ier; 263 264 if (bas->rclk == 0) 265 bas->rclk = DEFAULT_RCLK; 266 ns8250_param(bas, baudrate, databits, stopbits, parity); 267 268 /* Disable all interrupt sources. */ 269 /* 270 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 271 * UARTs split the receive time-out interrupt bit out separately as 272 * 0x10. This gets handled by ier_mask and ier_rxbits below. 273 */ 274 ier = uart_getreg(bas, REG_IER) & 0xe0; 275 uart_setreg(bas, REG_IER, ier); 276 uart_barrier(bas); 277 278 /* Disable the FIFO (if present). */ 279 uart_setreg(bas, REG_FCR, 0); 280 uart_barrier(bas); 281 282 /* Set RTS & DTR. */ 283 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 284 uart_barrier(bas); 285 286 ns8250_clrint(bas); 287} 288 289static void 290ns8250_term(struct uart_bas *bas) 291{ 292 293 /* Clear RTS & DTR. */ 294 uart_setreg(bas, REG_MCR, MCR_IE); 295 uart_barrier(bas); 296} 297 298static void 299ns8250_putc(struct uart_bas *bas, int c) 300{ 301 int limit; 302 303 limit = 250000; 304 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 305 DELAY(4); 306 uart_setreg(bas, REG_DATA, c); 307 uart_barrier(bas); 308 limit = 250000; 309 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 310 DELAY(4); 311} 312 313static int 314ns8250_rxready(struct uart_bas *bas) 315{ 316 317 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 318} 319 320static int 321ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 322{ 323 int c; 324 325 uart_lock(hwmtx); 326 327 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 328 uart_unlock(hwmtx); 329 DELAY(4); 330 uart_lock(hwmtx); 331 } 332 333 c = uart_getreg(bas, REG_DATA); 334 335 uart_unlock(hwmtx); 336 337 return (c); 338} 339 340/* 341 * High-level UART interface. 342 */ 343struct ns8250_softc { 344 struct uart_softc base; 345 uint8_t fcr; 346 uint8_t ier; 347 uint8_t mcr; 348 349 uint8_t ier_mask; 350 uint8_t ier_rxbits; 351}; 352 353static int ns8250_bus_attach(struct uart_softc *); 354static int ns8250_bus_detach(struct uart_softc *); 355static int ns8250_bus_flush(struct uart_softc *, int); 356static int ns8250_bus_getsig(struct uart_softc *); 357static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 358static int ns8250_bus_ipend(struct uart_softc *); 359static int ns8250_bus_param(struct uart_softc *, int, int, int, int); 360static int ns8250_bus_probe(struct uart_softc *); 361static int ns8250_bus_receive(struct uart_softc *); 362static int ns8250_bus_setsig(struct uart_softc *, int); 363static int ns8250_bus_transmit(struct uart_softc *); 364 365static kobj_method_t ns8250_methods[] = { 366 KOBJMETHOD(uart_attach, ns8250_bus_attach), 367 KOBJMETHOD(uart_detach, ns8250_bus_detach), 368 KOBJMETHOD(uart_flush, ns8250_bus_flush), 369 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 370 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 371 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 372 KOBJMETHOD(uart_param, ns8250_bus_param), 373 KOBJMETHOD(uart_probe, ns8250_bus_probe), 374 KOBJMETHOD(uart_receive, ns8250_bus_receive), 375 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 376 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 377 { 0, 0 } 378}; 379 380struct uart_class uart_ns8250_class = { 381 "ns8250", 382 ns8250_methods, 383 sizeof(struct ns8250_softc), 384 .uc_ops = &uart_ns8250_ops, 385 .uc_range = 8, 386 .uc_rclk = DEFAULT_RCLK 387}; 388 389#define SIGCHG(c, i, s, d) \ 390 if (c) { \ 391 i |= (i & s) ? s : s | d; \ 392 } else { \ 393 i = (i & s) ? (i & ~s) | d : i; \ 394 } 395 396static int 397ns8250_bus_attach(struct uart_softc *sc) 398{ 399 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 400 struct uart_bas *bas; 401 unsigned int ivar; 402 403 bas = &sc->sc_bas; 404 405 ns8250->mcr = uart_getreg(bas, REG_MCR); 406 ns8250->fcr = FCR_ENABLE; 407 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 408 &ivar)) { 409 if (UART_FLAGS_FCR_RX_LOW(ivar)) 410 ns8250->fcr |= FCR_RX_LOW; 411 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 412 ns8250->fcr |= FCR_RX_MEDL; 413 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 414 ns8250->fcr |= FCR_RX_HIGH; 415 else 416 ns8250->fcr |= FCR_RX_MEDH; 417 } else 418 ns8250->fcr |= FCR_RX_MEDH; 419 420 /* Get IER mask */ 421 ivar = 0xf0; 422 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 423 &ivar); 424 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 425 426 /* Get IER RX interrupt bits */ 427 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 428 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 429 &ivar); 430 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 431 432 uart_setreg(bas, REG_FCR, ns8250->fcr); 433 uart_barrier(bas); 434 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 435 436 if (ns8250->mcr & MCR_DTR) 437 sc->sc_hwsig |= SER_DTR; 438 if (ns8250->mcr & MCR_RTS) 439 sc->sc_hwsig |= SER_RTS; 440 ns8250_bus_getsig(sc); 441 442 ns8250_clrint(bas); 443 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 444 ns8250->ier |= ns8250->ier_rxbits; 445 uart_setreg(bas, REG_IER, ns8250->ier); 446 uart_barrier(bas); 447 448 return (0); 449} 450 451static int 452ns8250_bus_detach(struct uart_softc *sc) 453{ 454 struct ns8250_softc *ns8250; 455 struct uart_bas *bas; 456 u_char ier; 457 458 ns8250 = (struct ns8250_softc *)sc; 459 bas = &sc->sc_bas; 460 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 461 uart_setreg(bas, REG_IER, ier); 462 uart_barrier(bas); 463 ns8250_clrint(bas); 464 return (0); 465} 466 467static int 468ns8250_bus_flush(struct uart_softc *sc, int what) 469{ 470 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 471 struct uart_bas *bas; 472 int error; 473 474 bas = &sc->sc_bas; 475 uart_lock(sc->sc_hwmtx); 476 if (sc->sc_rxfifosz > 1) { 477 ns8250_flush(bas, what); 478 uart_setreg(bas, REG_FCR, ns8250->fcr); 479 uart_barrier(bas); 480 error = 0; 481 } else 482 error = ns8250_drain(bas, what); 483 uart_unlock(sc->sc_hwmtx); 484 return (error); 485} 486 487static int 488ns8250_bus_getsig(struct uart_softc *sc) 489{ 490 uint32_t new, old, sig; 491 uint8_t msr; 492 493 do { 494 old = sc->sc_hwsig; 495 sig = old; 496 uart_lock(sc->sc_hwmtx); 497 msr = uart_getreg(&sc->sc_bas, REG_MSR); 498 uart_unlock(sc->sc_hwmtx); 499 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 500 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 501 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 502 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 503 new = sig & ~SER_MASK_DELTA; 504 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 505 return (sig); 506} 507 508static int 509ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 510{ 511 struct uart_bas *bas; 512 int baudrate, divisor, error; 513 uint8_t efr, lcr; 514 515 bas = &sc->sc_bas; 516 error = 0; 517 uart_lock(sc->sc_hwmtx); 518 switch (request) { 519 case UART_IOCTL_BREAK: 520 lcr = uart_getreg(bas, REG_LCR); 521 if (data) 522 lcr |= LCR_SBREAK; 523 else 524 lcr &= ~LCR_SBREAK; 525 uart_setreg(bas, REG_LCR, lcr); 526 uart_barrier(bas); 527 break; 528 case UART_IOCTL_IFLOW: 529 lcr = uart_getreg(bas, REG_LCR); 530 uart_barrier(bas); 531 uart_setreg(bas, REG_LCR, 0xbf); 532 uart_barrier(bas); 533 efr = uart_getreg(bas, REG_EFR); 534 if (data) 535 efr |= EFR_RTS; 536 else 537 efr &= ~EFR_RTS; 538 uart_setreg(bas, REG_EFR, efr); 539 uart_barrier(bas); 540 uart_setreg(bas, REG_LCR, lcr); 541 uart_barrier(bas); 542 break; 543 case UART_IOCTL_OFLOW: 544 lcr = uart_getreg(bas, REG_LCR); 545 uart_barrier(bas); 546 uart_setreg(bas, REG_LCR, 0xbf); 547 uart_barrier(bas); 548 efr = uart_getreg(bas, REG_EFR); 549 if (data) 550 efr |= EFR_CTS; 551 else 552 efr &= ~EFR_CTS; 553 uart_setreg(bas, REG_EFR, efr); 554 uart_barrier(bas); 555 uart_setreg(bas, REG_LCR, lcr); 556 uart_barrier(bas); 557 break; 558 case UART_IOCTL_BAUD: 559 lcr = uart_getreg(bas, REG_LCR); 560 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 561 uart_barrier(bas); 562 divisor = uart_getreg(bas, REG_DLL) | 563 (uart_getreg(bas, REG_DLH) << 8); 564 uart_barrier(bas); 565 uart_setreg(bas, REG_LCR, lcr); 566 uart_barrier(bas); 567 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 568 if (baudrate > 0) 569 *(int*)data = baudrate; 570 else 571 error = ENXIO; 572 break; 573 default: 574 error = EINVAL; 575 break; 576 } 577 uart_unlock(sc->sc_hwmtx); 578 return (error); 579} 580 581static int 582ns8250_bus_ipend(struct uart_softc *sc) 583{ 584 struct uart_bas *bas; 585 struct ns8250_softc *ns8250; 586 int ipend; 587 uint8_t iir, lsr; 588 589 ns8250 = (struct ns8250_softc *)sc; 590 bas = &sc->sc_bas; 591 uart_lock(sc->sc_hwmtx); 592 iir = uart_getreg(bas, REG_IIR); 593 if (iir & IIR_NOPEND) { 594 uart_unlock(sc->sc_hwmtx); 595 return (0); 596 } 597 ipend = 0; 598 if (iir & IIR_RXRDY) { 599 lsr = uart_getreg(bas, REG_LSR); 600 if (lsr & LSR_OE) 601 ipend |= SER_INT_OVERRUN; 602 if (lsr & LSR_BI) 603 ipend |= SER_INT_BREAK; 604 if (lsr & LSR_RXRDY) 605 ipend |= SER_INT_RXREADY; 606 } else { 607 if (iir & IIR_TXRDY) { 608 ipend |= SER_INT_TXIDLE; 609 uart_setreg(bas, REG_IER, ns8250->ier); 610 } else 611 ipend |= SER_INT_SIGCHG; 612 } 613 if (ipend == 0) 614 ns8250_clrint(bas); 615 uart_unlock(sc->sc_hwmtx); 616 return (ipend); 617} 618 619static int 620ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 621 int stopbits, int parity) 622{ 623 struct uart_bas *bas; 624 int error; 625 626 bas = &sc->sc_bas; 627 uart_lock(sc->sc_hwmtx); 628 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 629 uart_unlock(sc->sc_hwmtx); 630 return (error); 631} 632 633static int 634ns8250_bus_probe(struct uart_softc *sc) 635{ 636 struct ns8250_softc *ns8250; 637 struct uart_bas *bas; 638 int count, delay, error, limit; 639 uint8_t lsr, mcr, ier; 640 641 ns8250 = (struct ns8250_softc *)sc; 642 bas = &sc->sc_bas; 643 644 error = ns8250_probe(bas); 645 if (error) 646 return (error); 647 648 mcr = MCR_IE; 649 if (sc->sc_sysdev == NULL) { 650 /* By using ns8250_init() we also set DTR and RTS. */ 651 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 652 } else 653 mcr |= MCR_DTR | MCR_RTS; 654 655 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 656 if (error) 657 return (error); 658 659 /* 660 * Set loopback mode. This avoids having garbage on the wire and 661 * also allows us send and receive data. We set DTR and RTS to 662 * avoid the possibility that automatic flow-control prevents 663 * any data from being sent. 664 */ 665 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 666 uart_barrier(bas); 667 668 /* 669 * Enable FIFOs. And check that the UART has them. If not, we're 670 * done. Since this is the first time we enable the FIFOs, we reset 671 * them. 672 */ 673 uart_setreg(bas, REG_FCR, FCR_ENABLE); 674 uart_barrier(bas); 675 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 676 /* 677 * NS16450 or INS8250. We don't bother to differentiate 678 * between them. They're too old to be interesting. 679 */ 680 uart_setreg(bas, REG_MCR, mcr); 681 uart_barrier(bas); 682 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 683 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 684 return (0); 685 } 686 687 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 688 uart_barrier(bas); 689 690 count = 0; 691 delay = ns8250_delay(bas); 692 693 /* We have FIFOs. Drain the transmitter and receiver. */ 694 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 695 if (error) { 696 uart_setreg(bas, REG_MCR, mcr); 697 uart_setreg(bas, REG_FCR, 0); 698 uart_barrier(bas); 699 goto describe; 700 } 701 702 /* 703 * We should have a sufficiently clean "pipe" to determine the 704 * size of the FIFOs. We send as much characters as is reasonable 705 * and wait for the overflow bit in the LSR register to be 706 * asserted, counting the characters as we send them. Based on 707 * that count we know the FIFO size. 708 */ 709 do { 710 uart_setreg(bas, REG_DATA, 0); 711 uart_barrier(bas); 712 count++; 713 714 limit = 30; 715 lsr = 0; 716 /* 717 * LSR bits are cleared upon read, so we must accumulate 718 * them to be able to test LSR_OE below. 719 */ 720 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 721 --limit) 722 DELAY(delay); 723 if (limit == 0) { 724 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 725 uart_setreg(bas, REG_IER, ier); 726 uart_setreg(bas, REG_MCR, mcr); 727 uart_setreg(bas, REG_FCR, 0); 728 uart_barrier(bas); 729 count = 0; 730 goto describe; 731 } 732 } while ((lsr & LSR_OE) == 0 && count < 130); 733 count--; 734 735 uart_setreg(bas, REG_MCR, mcr); 736 737 /* Reset FIFOs. */ 738 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 739 740 describe: 741 if (count >= 14 && count <= 16) { 742 sc->sc_rxfifosz = 16; 743 device_set_desc(sc->sc_dev, "16550 or compatible"); 744 } else if (count >= 28 && count <= 32) { 745 sc->sc_rxfifosz = 32; 746 device_set_desc(sc->sc_dev, "16650 or compatible"); 747 } else if (count >= 56 && count <= 64) { 748 sc->sc_rxfifosz = 64; 749 device_set_desc(sc->sc_dev, "16750 or compatible"); 750 } else if (count >= 112 && count <= 128) { 751 sc->sc_rxfifosz = 128; 752 device_set_desc(sc->sc_dev, "16950 or compatible"); 753 } else { 754 sc->sc_rxfifosz = 16; 755 device_set_desc(sc->sc_dev, 756 "Non-standard ns8250 class UART with FIFOs"); 757 } 758 759 /* 760 * Force the Tx FIFO size to 16 bytes for now. We don't program the 761 * Tx trigger. Also, we assume that all data has been sent when the 762 * interrupt happens. 763 */ 764 sc->sc_txfifosz = 16; 765 766#if 0 767 /* 768 * XXX there are some issues related to hardware flow control and 769 * it's likely that uart(4) is the cause. This basicly needs more 770 * investigation, but we avoid using for hardware flow control 771 * until then. 772 */ 773 /* 16650s or higher have automatic flow control. */ 774 if (sc->sc_rxfifosz > 16) { 775 sc->sc_hwiflow = 1; 776 sc->sc_hwoflow = 1; 777 } 778#endif 779 780 return (0); 781} 782 783static int 784ns8250_bus_receive(struct uart_softc *sc) 785{ 786 struct uart_bas *bas; 787 int xc; 788 uint8_t lsr; 789 790 bas = &sc->sc_bas; 791 uart_lock(sc->sc_hwmtx); 792 lsr = uart_getreg(bas, REG_LSR); 793 while (lsr & LSR_RXRDY) { 794 if (uart_rx_full(sc)) { 795 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 796 break; 797 } 798 xc = uart_getreg(bas, REG_DATA); 799 if (lsr & LSR_FE) 800 xc |= UART_STAT_FRAMERR; 801 if (lsr & LSR_PE) 802 xc |= UART_STAT_PARERR; 803 uart_rx_put(sc, xc); 804 lsr = uart_getreg(bas, REG_LSR); 805 } 806 /* Discard everything left in the Rx FIFO. */ 807 while (lsr & LSR_RXRDY) { 808 (void)uart_getreg(bas, REG_DATA); 809 uart_barrier(bas); 810 lsr = uart_getreg(bas, REG_LSR); 811 } 812 uart_unlock(sc->sc_hwmtx); 813 return (0); 814} 815 816static int 817ns8250_bus_setsig(struct uart_softc *sc, int sig) 818{ 819 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 820 struct uart_bas *bas; 821 uint32_t new, old; 822 823 bas = &sc->sc_bas; 824 do { 825 old = sc->sc_hwsig; 826 new = old; 827 if (sig & SER_DDTR) { 828 SIGCHG(sig & SER_DTR, new, SER_DTR, 829 SER_DDTR); 830 } 831 if (sig & SER_DRTS) { 832 SIGCHG(sig & SER_RTS, new, SER_RTS, 833 SER_DRTS); 834 } 835 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 836 uart_lock(sc->sc_hwmtx); 837 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 838 if (new & SER_DTR) 839 ns8250->mcr |= MCR_DTR; 840 if (new & SER_RTS) 841 ns8250->mcr |= MCR_RTS; 842 uart_setreg(bas, REG_MCR, ns8250->mcr); 843 uart_barrier(bas); 844 uart_unlock(sc->sc_hwmtx); 845 return (0); 846} 847 848static int 849ns8250_bus_transmit(struct uart_softc *sc) 850{ 851 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 852 struct uart_bas *bas; 853 int i; 854 855 bas = &sc->sc_bas; 856 uart_lock(sc->sc_hwmtx); 857 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 858 ; 859 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 860 uart_barrier(bas); 861 for (i = 0; i < sc->sc_txdatasz; i++) { 862 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 863 uart_barrier(bas); 864 } 865 sc->sc_txbusy = 1; 866 uart_unlock(sc->sc_hwmtx); 867 return (0); 868} 869