uart_dev_ns8250.c revision 190834
1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/uart/uart_dev_ns8250.c 190834 2009-04-08 00:14:06Z marcel $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <machine/bus.h> 35 36#include <dev/uart/uart.h> 37#include <dev/uart/uart_cpu.h> 38#include <dev/uart/uart_bus.h> 39 40#include <dev/ic/ns16550.h> 41 42#include "uart_if.h" 43 44#define DEFAULT_RCLK 1843200 45 46/* 47 * Clear pending interrupts. THRE is cleared by reading IIR. Data 48 * that may have been received gets lost here. 49 */ 50static void 51ns8250_clrint(struct uart_bas *bas) 52{ 53 uint8_t iir, lsr; 54 55 iir = uart_getreg(bas, REG_IIR); 56 while ((iir & IIR_NOPEND) == 0) { 57 iir &= IIR_IMASK; 58 if (iir == IIR_RLS) { 59 lsr = uart_getreg(bas, REG_LSR); 60 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 61 (void)uart_getreg(bas, REG_DATA); 62 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 63 (void)uart_getreg(bas, REG_DATA); 64 else if (iir == IIR_MLSC) 65 (void)uart_getreg(bas, REG_MSR); 66 uart_barrier(bas); 67 iir = uart_getreg(bas, REG_IIR); 68 } 69} 70 71static int 72ns8250_delay(struct uart_bas *bas) 73{ 74 int divisor; 75 u_char lcr; 76 77 lcr = uart_getreg(bas, REG_LCR); 78 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 79 uart_barrier(bas); 80 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 81 uart_barrier(bas); 82 uart_setreg(bas, REG_LCR, lcr); 83 uart_barrier(bas); 84 85 /* 1/10th the time to transmit 1 character (estimate). */ 86 if (divisor <= 134) 87 return (16000000 * divisor / bas->rclk); 88 return (16000 * divisor / (bas->rclk / 1000)); 89} 90 91static int 92ns8250_divisor(int rclk, int baudrate) 93{ 94 int actual_baud, divisor; 95 int error; 96 97 if (baudrate == 0) 98 return (0); 99 100 divisor = (rclk / (baudrate << 3) + 1) >> 1; 101 if (divisor == 0 || divisor >= 65536) 102 return (0); 103 actual_baud = rclk / (divisor << 4); 104 105 /* 10 times error in percent: */ 106 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 107 108 /* 3.0% maximum error tolerance: */ 109 if (error < -30 || error > 30) 110 return (0); 111 112 return (divisor); 113} 114 115static int 116ns8250_drain(struct uart_bas *bas, int what) 117{ 118 int delay, limit; 119 120 delay = ns8250_delay(bas); 121 122 if (what & UART_DRAIN_TRANSMITTER) { 123 /* 124 * Pick an arbitrary high limit to avoid getting stuck in 125 * an infinite loop when the hardware is broken. Make the 126 * limit high enough to handle large FIFOs. 127 */ 128 limit = 10*1024; 129 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 130 DELAY(delay); 131 if (limit == 0) { 132 /* printf("ns8250: transmitter appears stuck... "); */ 133 return (EIO); 134 } 135 } 136 137 if (what & UART_DRAIN_RECEIVER) { 138 /* 139 * Pick an arbitrary high limit to avoid getting stuck in 140 * an infinite loop when the hardware is broken. Make the 141 * limit high enough to handle large FIFOs and integrated 142 * UARTs. The HP rx2600 for example has 3 UARTs on the 143 * management board that tend to get a lot of data send 144 * to it when the UART is first activated. 145 */ 146 limit=10*4096; 147 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 148 (void)uart_getreg(bas, REG_DATA); 149 uart_barrier(bas); 150 DELAY(delay << 2); 151 } 152 if (limit == 0) { 153 /* printf("ns8250: receiver appears broken... "); */ 154 return (EIO); 155 } 156 } 157 158 return (0); 159} 160 161/* 162 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 163 * drained. WARNING: this function clobbers the FIFO setting! 164 */ 165static void 166ns8250_flush(struct uart_bas *bas, int what) 167{ 168 uint8_t fcr; 169 170 fcr = FCR_ENABLE; 171 if (what & UART_FLUSH_TRANSMITTER) 172 fcr |= FCR_XMT_RST; 173 if (what & UART_FLUSH_RECEIVER) 174 fcr |= FCR_RCV_RST; 175 uart_setreg(bas, REG_FCR, fcr); 176 uart_barrier(bas); 177} 178 179static int 180ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 181 int parity) 182{ 183 int divisor; 184 uint8_t lcr; 185 186 lcr = 0; 187 if (databits >= 8) 188 lcr |= LCR_8BITS; 189 else if (databits == 7) 190 lcr |= LCR_7BITS; 191 else if (databits == 6) 192 lcr |= LCR_6BITS; 193 else 194 lcr |= LCR_5BITS; 195 if (stopbits > 1) 196 lcr |= LCR_STOPB; 197 lcr |= parity << 3; 198 199 /* Set baudrate. */ 200 if (baudrate > 0) { 201 divisor = ns8250_divisor(bas->rclk, baudrate); 202 if (divisor == 0) 203 return (EINVAL); 204 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 205 uart_barrier(bas); 206 uart_setreg(bas, REG_DLL, divisor & 0xff); 207 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 208 uart_barrier(bas); 209 } 210 211 /* Set LCR and clear DLAB. */ 212 uart_setreg(bas, REG_LCR, lcr); 213 uart_barrier(bas); 214 return (0); 215} 216 217/* 218 * Low-level UART interface. 219 */ 220static int ns8250_probe(struct uart_bas *bas); 221static void ns8250_init(struct uart_bas *bas, int, int, int, int); 222static void ns8250_term(struct uart_bas *bas); 223static void ns8250_putc(struct uart_bas *bas, int); 224static int ns8250_rxready(struct uart_bas *bas); 225static int ns8250_getc(struct uart_bas *bas, struct mtx *); 226 227static struct uart_ops uart_ns8250_ops = { 228 .probe = ns8250_probe, 229 .init = ns8250_init, 230 .term = ns8250_term, 231 .putc = ns8250_putc, 232 .rxready = ns8250_rxready, 233 .getc = ns8250_getc, 234}; 235 236static int 237ns8250_probe(struct uart_bas *bas) 238{ 239 u_char val; 240 241 /* Check known 0 bits that don't depend on DLAB. */ 242 val = uart_getreg(bas, REG_IIR); 243 if (val & 0x30) 244 return (ENXIO); 245 val = uart_getreg(bas, REG_MCR); 246 if (val & 0xe0) 247 return (ENXIO); 248 249 return (0); 250} 251 252static void 253ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 254 int parity) 255{ 256 u_char ier; 257 258 if (bas->rclk == 0) 259 bas->rclk = DEFAULT_RCLK; 260 ns8250_param(bas, baudrate, databits, stopbits, parity); 261 262 /* Disable all interrupt sources. */ 263 /* 264 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 265 * UARTs split the receive time-out interrupt bit out separately as 266 * 0x10. This gets handled by ier_mask and ier_rxbits below. 267 */ 268 ier = uart_getreg(bas, REG_IER) & 0xe0; 269 uart_setreg(bas, REG_IER, ier); 270 uart_barrier(bas); 271 272 /* Disable the FIFO (if present). */ 273 uart_setreg(bas, REG_FCR, 0); 274 uart_barrier(bas); 275 276 /* Set RTS & DTR. */ 277 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 278 uart_barrier(bas); 279 280 ns8250_clrint(bas); 281} 282 283static void 284ns8250_term(struct uart_bas *bas) 285{ 286 287 /* Clear RTS & DTR. */ 288 uart_setreg(bas, REG_MCR, MCR_IE); 289 uart_barrier(bas); 290} 291 292static void 293ns8250_putc(struct uart_bas *bas, int c) 294{ 295 int limit; 296 297 limit = 250000; 298 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 299 DELAY(4); 300 uart_setreg(bas, REG_DATA, c); 301 uart_barrier(bas); 302 limit = 250000; 303 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 304 DELAY(4); 305} 306 307static int 308ns8250_rxready(struct uart_bas *bas) 309{ 310 311 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 312} 313 314static int 315ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 316{ 317 int c; 318 319 uart_lock(hwmtx); 320 321 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 322 uart_unlock(hwmtx); 323 DELAY(4); 324 uart_lock(hwmtx); 325 } 326 327 c = uart_getreg(bas, REG_DATA); 328 329 uart_unlock(hwmtx); 330 331 return (c); 332} 333 334/* 335 * High-level UART interface. 336 */ 337struct ns8250_softc { 338 struct uart_softc base; 339 uint8_t fcr; 340 uint8_t ier; 341 uint8_t mcr; 342 343 uint8_t ier_mask; 344 uint8_t ier_rxbits; 345}; 346 347static int ns8250_bus_attach(struct uart_softc *); 348static int ns8250_bus_detach(struct uart_softc *); 349static int ns8250_bus_flush(struct uart_softc *, int); 350static int ns8250_bus_getsig(struct uart_softc *); 351static int ns8250_bus_ioctl(struct uart_softc *, int, intptr_t); 352static int ns8250_bus_ipend(struct uart_softc *); 353static int ns8250_bus_param(struct uart_softc *, int, int, int, int); 354static int ns8250_bus_probe(struct uart_softc *); 355static int ns8250_bus_receive(struct uart_softc *); 356static int ns8250_bus_setsig(struct uart_softc *, int); 357static int ns8250_bus_transmit(struct uart_softc *); 358 359static kobj_method_t ns8250_methods[] = { 360 KOBJMETHOD(uart_attach, ns8250_bus_attach), 361 KOBJMETHOD(uart_detach, ns8250_bus_detach), 362 KOBJMETHOD(uart_flush, ns8250_bus_flush), 363 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 364 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 365 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 366 KOBJMETHOD(uart_param, ns8250_bus_param), 367 KOBJMETHOD(uart_probe, ns8250_bus_probe), 368 KOBJMETHOD(uart_receive, ns8250_bus_receive), 369 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 370 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 371 { 0, 0 } 372}; 373 374struct uart_class uart_ns8250_class = { 375 "ns8250", 376 ns8250_methods, 377 sizeof(struct ns8250_softc), 378 .uc_ops = &uart_ns8250_ops, 379 .uc_range = 8, 380 .uc_rclk = DEFAULT_RCLK 381}; 382 383#define SIGCHG(c, i, s, d) \ 384 if (c) { \ 385 i |= (i & s) ? s : s | d; \ 386 } else { \ 387 i = (i & s) ? (i & ~s) | d : i; \ 388 } 389 390static int 391ns8250_bus_attach(struct uart_softc *sc) 392{ 393 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 394 struct uart_bas *bas; 395 unsigned int ivar; 396 397 bas = &sc->sc_bas; 398 399 ns8250->mcr = uart_getreg(bas, REG_MCR); 400 ns8250->fcr = FCR_ENABLE; 401 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 402 &ivar)) { 403 if (UART_FLAGS_FCR_RX_LOW(ivar)) 404 ns8250->fcr |= FCR_RX_LOW; 405 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 406 ns8250->fcr |= FCR_RX_MEDL; 407 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 408 ns8250->fcr |= FCR_RX_HIGH; 409 else 410 ns8250->fcr |= FCR_RX_MEDH; 411 } else 412 ns8250->fcr |= FCR_RX_MEDH; 413 414 /* Get IER mask */ 415 ivar = 0xf0; 416 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 417 &ivar); 418 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 419 420 /* Get IER RX interrupt bits */ 421 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 422 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 423 &ivar); 424 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 425 426 uart_setreg(bas, REG_FCR, ns8250->fcr); 427 uart_barrier(bas); 428 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 429 430 if (ns8250->mcr & MCR_DTR) 431 sc->sc_hwsig |= SER_DTR; 432 if (ns8250->mcr & MCR_RTS) 433 sc->sc_hwsig |= SER_RTS; 434 ns8250_bus_getsig(sc); 435 436 ns8250_clrint(bas); 437 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 438 ns8250->ier |= ns8250->ier_rxbits; 439 uart_setreg(bas, REG_IER, ns8250->ier); 440 uart_barrier(bas); 441 442 return (0); 443} 444 445static int 446ns8250_bus_detach(struct uart_softc *sc) 447{ 448 struct ns8250_softc *ns8250; 449 struct uart_bas *bas; 450 u_char ier; 451 452 ns8250 = (struct ns8250_softc *)sc; 453 bas = &sc->sc_bas; 454 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 455 uart_setreg(bas, REG_IER, ier); 456 uart_barrier(bas); 457 ns8250_clrint(bas); 458 return (0); 459} 460 461static int 462ns8250_bus_flush(struct uart_softc *sc, int what) 463{ 464 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 465 struct uart_bas *bas; 466 int error; 467 468 bas = &sc->sc_bas; 469 uart_lock(sc->sc_hwmtx); 470 if (sc->sc_rxfifosz > 1) { 471 ns8250_flush(bas, what); 472 uart_setreg(bas, REG_FCR, ns8250->fcr); 473 uart_barrier(bas); 474 error = 0; 475 } else 476 error = ns8250_drain(bas, what); 477 uart_unlock(sc->sc_hwmtx); 478 return (error); 479} 480 481static int 482ns8250_bus_getsig(struct uart_softc *sc) 483{ 484 uint32_t new, old, sig; 485 uint8_t msr; 486 487 do { 488 old = sc->sc_hwsig; 489 sig = old; 490 uart_lock(sc->sc_hwmtx); 491 msr = uart_getreg(&sc->sc_bas, REG_MSR); 492 uart_unlock(sc->sc_hwmtx); 493 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 494 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 495 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 496 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 497 new = sig & ~SER_MASK_DELTA; 498 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 499 return (sig); 500} 501 502static int 503ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 504{ 505 struct uart_bas *bas; 506 int baudrate, divisor, error; 507 uint8_t efr, lcr; 508 509 bas = &sc->sc_bas; 510 error = 0; 511 uart_lock(sc->sc_hwmtx); 512 switch (request) { 513 case UART_IOCTL_BREAK: 514 lcr = uart_getreg(bas, REG_LCR); 515 if (data) 516 lcr |= LCR_SBREAK; 517 else 518 lcr &= ~LCR_SBREAK; 519 uart_setreg(bas, REG_LCR, lcr); 520 uart_barrier(bas); 521 break; 522 case UART_IOCTL_IFLOW: 523 lcr = uart_getreg(bas, REG_LCR); 524 uart_barrier(bas); 525 uart_setreg(bas, REG_LCR, 0xbf); 526 uart_barrier(bas); 527 efr = uart_getreg(bas, REG_EFR); 528 if (data) 529 efr |= EFR_RTS; 530 else 531 efr &= ~EFR_RTS; 532 uart_setreg(bas, REG_EFR, efr); 533 uart_barrier(bas); 534 uart_setreg(bas, REG_LCR, lcr); 535 uart_barrier(bas); 536 break; 537 case UART_IOCTL_OFLOW: 538 lcr = uart_getreg(bas, REG_LCR); 539 uart_barrier(bas); 540 uart_setreg(bas, REG_LCR, 0xbf); 541 uart_barrier(bas); 542 efr = uart_getreg(bas, REG_EFR); 543 if (data) 544 efr |= EFR_CTS; 545 else 546 efr &= ~EFR_CTS; 547 uart_setreg(bas, REG_EFR, efr); 548 uart_barrier(bas); 549 uart_setreg(bas, REG_LCR, lcr); 550 uart_barrier(bas); 551 break; 552 case UART_IOCTL_BAUD: 553 lcr = uart_getreg(bas, REG_LCR); 554 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 555 uart_barrier(bas); 556 divisor = uart_getreg(bas, REG_DLL) | 557 (uart_getreg(bas, REG_DLH) << 8); 558 uart_barrier(bas); 559 uart_setreg(bas, REG_LCR, lcr); 560 uart_barrier(bas); 561 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 562 if (baudrate > 0) 563 *(int*)data = baudrate; 564 else 565 error = ENXIO; 566 break; 567 default: 568 error = EINVAL; 569 break; 570 } 571 uart_unlock(sc->sc_hwmtx); 572 return (error); 573} 574 575static int 576ns8250_bus_ipend(struct uart_softc *sc) 577{ 578 struct uart_bas *bas; 579 int ipend; 580 uint8_t iir, lsr; 581 582 bas = &sc->sc_bas; 583 uart_lock(sc->sc_hwmtx); 584 iir = uart_getreg(bas, REG_IIR); 585 if (iir & IIR_NOPEND) { 586 uart_unlock(sc->sc_hwmtx); 587 return (0); 588 } 589 ipend = 0; 590 if (iir & IIR_RXRDY) { 591 lsr = uart_getreg(bas, REG_LSR); 592 if (lsr & LSR_OE) 593 ipend |= SER_INT_OVERRUN; 594 if (lsr & LSR_BI) 595 ipend |= SER_INT_BREAK; 596 if (lsr & LSR_RXRDY) 597 ipend |= SER_INT_RXREADY; 598 } else { 599 if (iir & IIR_TXRDY) 600 ipend |= SER_INT_TXIDLE; 601 else 602 ipend |= SER_INT_SIGCHG; 603 } 604 if (ipend == 0) 605 ns8250_clrint(bas); 606 uart_unlock(sc->sc_hwmtx); 607 return ((sc->sc_leaving) ? 0 : ipend); 608} 609 610static int 611ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 612 int stopbits, int parity) 613{ 614 struct uart_bas *bas; 615 int error; 616 617 bas = &sc->sc_bas; 618 uart_lock(sc->sc_hwmtx); 619 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 620 uart_unlock(sc->sc_hwmtx); 621 return (error); 622} 623 624static int 625ns8250_bus_probe(struct uart_softc *sc) 626{ 627 struct ns8250_softc *ns8250; 628 struct uart_bas *bas; 629 int count, delay, error, limit; 630 uint8_t lsr, mcr, ier; 631 632 ns8250 = (struct ns8250_softc *)sc; 633 bas = &sc->sc_bas; 634 635 error = ns8250_probe(bas); 636 if (error) 637 return (error); 638 639 mcr = MCR_IE; 640 if (sc->sc_sysdev == NULL) { 641 /* By using ns8250_init() we also set DTR and RTS. */ 642 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 643 } else 644 mcr |= MCR_DTR | MCR_RTS; 645 646 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 647 if (error) 648 return (error); 649 650 /* 651 * Set loopback mode. This avoids having garbage on the wire and 652 * also allows us send and receive data. We set DTR and RTS to 653 * avoid the possibility that automatic flow-control prevents 654 * any data from being sent. 655 */ 656 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 657 uart_barrier(bas); 658 659 /* 660 * Enable FIFOs. And check that the UART has them. If not, we're 661 * done. Since this is the first time we enable the FIFOs, we reset 662 * them. 663 */ 664 uart_setreg(bas, REG_FCR, FCR_ENABLE); 665 uart_barrier(bas); 666 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 667 /* 668 * NS16450 or INS8250. We don't bother to differentiate 669 * between them. They're too old to be interesting. 670 */ 671 uart_setreg(bas, REG_MCR, mcr); 672 uart_barrier(bas); 673 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 674 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 675 return (0); 676 } 677 678 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 679 uart_barrier(bas); 680 681 count = 0; 682 delay = ns8250_delay(bas); 683 684 /* We have FIFOs. Drain the transmitter and receiver. */ 685 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 686 if (error) { 687 uart_setreg(bas, REG_MCR, mcr); 688 uart_setreg(bas, REG_FCR, 0); 689 uart_barrier(bas); 690 goto describe; 691 } 692 693 /* 694 * We should have a sufficiently clean "pipe" to determine the 695 * size of the FIFOs. We send as much characters as is reasonable 696 * and wait for the the overflow bit in the LSR register to be 697 * asserted, counting the characters as we send them. Based on 698 * that count we know the FIFO size. 699 */ 700 do { 701 uart_setreg(bas, REG_DATA, 0); 702 uart_barrier(bas); 703 count++; 704 705 limit = 30; 706 lsr = 0; 707 /* 708 * LSR bits are cleared upon read, so we must accumulate 709 * them to be able to test LSR_OE below. 710 */ 711 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 712 --limit) 713 DELAY(delay); 714 if (limit == 0) { 715 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 716 uart_setreg(bas, REG_IER, ier); 717 uart_setreg(bas, REG_MCR, mcr); 718 uart_setreg(bas, REG_FCR, 0); 719 uart_barrier(bas); 720 count = 0; 721 goto describe; 722 } 723 } while ((lsr & LSR_OE) == 0 && count < 130); 724 count--; 725 726 uart_setreg(bas, REG_MCR, mcr); 727 728 /* Reset FIFOs. */ 729 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 730 731 describe: 732 if (count >= 14 && count <= 16) { 733 sc->sc_rxfifosz = 16; 734 device_set_desc(sc->sc_dev, "16550 or compatible"); 735 } else if (count >= 28 && count <= 32) { 736 sc->sc_rxfifosz = 32; 737 device_set_desc(sc->sc_dev, "16650 or compatible"); 738 } else if (count >= 56 && count <= 64) { 739 sc->sc_rxfifosz = 64; 740 device_set_desc(sc->sc_dev, "16750 or compatible"); 741 } else if (count >= 112 && count <= 128) { 742 sc->sc_rxfifosz = 128; 743 device_set_desc(sc->sc_dev, "16950 or compatible"); 744 } else { 745 sc->sc_rxfifosz = 16; 746 device_set_desc(sc->sc_dev, 747 "Non-standard ns8250 class UART with FIFOs"); 748 } 749 750 /* 751 * Force the Tx FIFO size to 16 bytes for now. We don't program the 752 * Tx trigger. Also, we assume that all data has been sent when the 753 * interrupt happens. 754 */ 755 sc->sc_txfifosz = 16; 756 757#if 0 758 /* 759 * XXX there are some issues related to hardware flow control and 760 * it's likely that uart(4) is the cause. This basicly needs more 761 * investigation, but we avoid using for hardware flow control 762 * until then. 763 */ 764 /* 16650s or higher have automatic flow control. */ 765 if (sc->sc_rxfifosz > 16) { 766 sc->sc_hwiflow = 1; 767 sc->sc_hwoflow = 1; 768 } 769#endif 770 771 return (0); 772} 773 774static int 775ns8250_bus_receive(struct uart_softc *sc) 776{ 777 struct uart_bas *bas; 778 int xc; 779 uint8_t lsr; 780 781 bas = &sc->sc_bas; 782 uart_lock(sc->sc_hwmtx); 783 lsr = uart_getreg(bas, REG_LSR); 784 while (lsr & LSR_RXRDY) { 785 if (uart_rx_full(sc)) { 786 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 787 break; 788 } 789 xc = uart_getreg(bas, REG_DATA); 790 if (lsr & LSR_FE) 791 xc |= UART_STAT_FRAMERR; 792 if (lsr & LSR_PE) 793 xc |= UART_STAT_PARERR; 794 uart_rx_put(sc, xc); 795 lsr = uart_getreg(bas, REG_LSR); 796 } 797 /* Discard everything left in the Rx FIFO. */ 798 while (lsr & LSR_RXRDY) { 799 (void)uart_getreg(bas, REG_DATA); 800 uart_barrier(bas); 801 lsr = uart_getreg(bas, REG_LSR); 802 } 803 uart_unlock(sc->sc_hwmtx); 804 return (0); 805} 806 807static int 808ns8250_bus_setsig(struct uart_softc *sc, int sig) 809{ 810 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 811 struct uart_bas *bas; 812 uint32_t new, old; 813 814 bas = &sc->sc_bas; 815 do { 816 old = sc->sc_hwsig; 817 new = old; 818 if (sig & SER_DDTR) { 819 SIGCHG(sig & SER_DTR, new, SER_DTR, 820 SER_DDTR); 821 } 822 if (sig & SER_DRTS) { 823 SIGCHG(sig & SER_RTS, new, SER_RTS, 824 SER_DRTS); 825 } 826 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 827 uart_lock(sc->sc_hwmtx); 828 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 829 if (new & SER_DTR) 830 ns8250->mcr |= MCR_DTR; 831 if (new & SER_RTS) 832 ns8250->mcr |= MCR_RTS; 833 uart_setreg(bas, REG_MCR, ns8250->mcr); 834 uart_barrier(bas); 835 uart_unlock(sc->sc_hwmtx); 836 return (0); 837} 838 839static int 840ns8250_bus_transmit(struct uart_softc *sc) 841{ 842 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 843 struct uart_bas *bas; 844 int i; 845 846 bas = &sc->sc_bas; 847 uart_lock(sc->sc_hwmtx); 848 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 849 ; 850 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 851 uart_barrier(bas); 852 for (i = 0; i < sc->sc_txdatasz; i++) { 853 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 854 uart_barrier(bas); 855 } 856 sc->sc_txbusy = 1; 857 uart_unlock(sc->sc_hwmtx); 858 return (0); 859} 860