uart_bus.h revision 155973 
1/*-
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/uart/uart_bus.h 155973 2006-02-24 05:40:17Z marcel $
27 */
28
29#ifndef _DEV_UART_BUS_H_
30#define _DEV_UART_BUS_H_
31
32#ifndef KLD_MODULE
33#include "opt_uart.h"
34#endif
35
36#include <sys/serial.h>
37#include <sys/timepps.h>
38
39/* Drain and flush targets. */
40#define	UART_DRAIN_RECEIVER	0x0001
41#define	UART_DRAIN_TRANSMITTER	0x0002
42#define	UART_FLUSH_RECEIVER	UART_DRAIN_RECEIVER
43#define	UART_FLUSH_TRANSMITTER	UART_DRAIN_TRANSMITTER
44
45/* Received character status bits. */
46#define	UART_STAT_BREAK		0x0100
47#define	UART_STAT_FRAMERR	0x0200
48#define	UART_STAT_OVERRUN	0x0400
49#define	UART_STAT_PARERR	0x0800
50
51#ifdef UART_PPS_ON_CTS
52#define	UART_SIG_DPPS		SER_DCTS
53#define	UART_SIG_PPS		SER_CTS
54#else
55#define	UART_SIG_DPPS		SER_DDCD
56#define	UART_SIG_PPS		SER_DCD
57#endif
58
59/* UART_IOCTL() requests */
60#define	UART_IOCTL_BREAK	1
61#define	UART_IOCTL_IFLOW	2
62#define	UART_IOCTL_OFLOW	3
63#define	UART_IOCTL_BAUD		4
64
65/*
66 * UART class & instance (=softc)
67 */
68struct uart_class {
69	KOBJ_CLASS_FIELDS;
70	u_int	uc_range;		/* Bus space address range. */
71	u_int	uc_rclk;		/* Default rclk for this device. */
72};
73
74extern struct uart_class uart_ns8250_class;
75extern struct uart_class uart_sab82532_class;
76extern struct uart_class uart_z8530_class;
77
78struct uart_softc {
79	KOBJ_FIELDS;
80	struct uart_class *sc_class;
81	struct uart_bas	sc_bas;
82	device_t	sc_dev;
83
84	struct mtx	sc_hwmtx;	/* Spinlock protecting hardware. */
85
86	struct resource	*sc_rres;	/* Register resource. */
87	int		sc_rrid;
88	int		sc_rtype;	/* SYS_RES_{IOPORT|MEMORY}. */
89	struct resource *sc_ires;	/* Interrupt resource. */
90	void		*sc_icookie;
91	int		sc_irid;
92
93	int		sc_callout:1;	/* This UART is opened for callout. */
94	int		sc_fastintr:1;	/* This UART uses fast interrupts. */
95	int		sc_hasfifo:1;	/* This UART has FIFOs. */
96	int		sc_hwiflow:1;	/* This UART has HW input flow ctl. */
97	int		sc_hwoflow:1;	/* This UART has HW output flow ctl. */
98	int		sc_leaving:1;	/* This UART is going away. */
99	int		sc_opened:1;	/* This UART is open for business. */
100	int		sc_polled:1;	/* This UART has no interrupts. */
101	int		sc_txbusy:1;	/* This UART is transmitting. */
102
103	struct uart_devinfo *sc_sysdev;	/* System device (or NULL). */
104
105	int		sc_altbrk;	/* State for alt break sequence. */
106	uint32_t	sc_hwsig;	/* Signal state. Used by HW driver. */
107
108	/* Receiver data. */
109	uint16_t	*sc_rxbuf;
110	int		sc_rxbufsz;
111	int		sc_rxput;
112	int		sc_rxget;
113	int		sc_rxfifosz;	/* Size of RX FIFO. */
114
115	/* Transmitter data. */
116	uint8_t		*sc_txbuf;
117	int		sc_txdatasz;
118	int		sc_txfifosz;	/* Size of TX FIFO and buffer. */
119
120	/* Pulse capturing support (PPS). */
121	struct pps_state sc_pps;
122
123	/* Upper layer data. */
124	void		*sc_softih;
125	uint32_t	sc_ttypend;
126	union {
127		/* TTY specific data. */
128		struct {
129			struct tty *tp;
130		} u_tty;
131		/* Keyboard specific data. */
132		struct {
133		} u_kbd;
134	} sc_u;
135};
136
137extern devclass_t uart_devclass;
138extern char uart_driver_name[];
139
140int uart_bus_attach(device_t dev);
141int uart_bus_detach(device_t dev);
142int uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan);
143
144int uart_tty_attach(struct uart_softc *);
145int uart_tty_detach(struct uart_softc *);
146void uart_tty_intr(void *arg);
147
148/*
149 * Receive buffer operations.
150 */
151static __inline int
152uart_rx_empty(struct uart_softc *sc)
153{
154	return ((sc->sc_rxget == sc->sc_rxput) ? 1 : 0);
155}
156
157static __inline int
158uart_rx_full(struct uart_softc *sc)
159{
160	return ((sc->sc_rxput + 1 < sc->sc_rxbufsz)
161	    ? (sc->sc_rxput + 1 == sc->sc_rxget) : (sc->sc_rxget == 0));
162}
163
164static __inline int
165uart_rx_get(struct uart_softc *sc)
166{
167	int ptr, xc;
168
169	ptr = sc->sc_rxget;
170	if (ptr == sc->sc_rxput)
171		return (-1);
172	xc = sc->sc_rxbuf[ptr++];
173	sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0;
174	return (xc);
175}
176
177static __inline int
178uart_rx_put(struct uart_softc *sc, int xc)
179{
180	int ptr;
181
182	ptr = (sc->sc_rxput + 1 < sc->sc_rxbufsz) ? sc->sc_rxput + 1 : 0;
183	if (ptr == sc->sc_rxget)
184		return (ENOSPC);
185	sc->sc_rxbuf[sc->sc_rxput] = xc;
186	sc->sc_rxput = ptr;
187	return (0);
188}
189
190#endif /* _DEV_UART_BUS_H_ */
191