uart_bus.h revision 136421 
1/*
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/uart/uart_bus.h 136421 2004-10-12 08:22:31Z phk $
27 */
28
29#ifndef _DEV_UART_BUS_H_
30#define _DEV_UART_BUS_H_
31
32#ifndef KLD_MODULE
33#include "opt_uart.h"
34#endif
35
36#include <sys/serial.h>
37#include <sys/timepps.h>
38
39/* Drain and flush targets. */
40#define	UART_DRAIN_RECEIVER	0x0001
41#define	UART_DRAIN_TRANSMITTER	0x0002
42#define	UART_FLUSH_RECEIVER	UART_DRAIN_RECEIVER
43#define	UART_FLUSH_TRANSMITTER	UART_DRAIN_TRANSMITTER
44
45/*
46 * Interrupt sources (in priority order). See also uart_core.c
47 * Note that the low order 16 bits are used to pass modem signals
48 * from the hardware interrupt handler to the software interrupt
49 * handler.
50 */
51#define	UART_IPEND_OVERRUN	0x010000
52#define	UART_IPEND_BREAK	0x020000
53#define	UART_IPEND_RXREADY	0x040000
54#define	UART_IPEND_SIGCHG	0x080000
55#define	UART_IPEND_TXIDLE	0x100000
56
57#define	UART_IPEND_MASK		0x1f0000
58#define	UART_IPEND_SIGMASK	0x00ffff
59
60/* Received character status bits. */
61#define	UART_STAT_BREAK		0x0100
62#define	UART_STAT_FRAMERR	0x0200
63#define	UART_STAT_OVERRUN	0x0400
64#define	UART_STAT_PARERR	0x0800
65
66#define	UART_SIGMASK_DTE	(SER_DTR | SER_RTS)
67#define	UART_SIGMASK_DCE	(SER_DSR | SER_CTS | SER_DCD | SER_RI)
68#define	UART_SIGMASK_STATE	(UART_SIGMASK_DTE | UART_SIGMASK_DCE)
69#define	UART_SIGMASK_DELTA	(UART_SIGMASK_STATE << 8)
70
71#ifdef UART_PPS_ON_CTS
72#define	UART_SIG_DPPS		SER_DCTS
73#define	UART_SIG_PPS		SER_CTS
74#else
75#define	UART_SIG_DPPS		SER_DDCD
76#define	UART_SIG_PPS		SER_DCD
77#endif
78
79/* UART_IOCTL() requests */
80#define	UART_IOCTL_BREAK	1
81#define	UART_IOCTL_IFLOW	2
82#define	UART_IOCTL_OFLOW	3
83
84/*
85 * UART class & instance (=softc)
86 */
87struct uart_class {
88	KOBJ_CLASS_FIELDS;
89	u_int	uc_range;		/* Bus space address range. */
90	u_int	uc_rclk;		/* Default rclk for this device. */
91};
92
93extern struct uart_class uart_ns8250_class;
94extern struct uart_class uart_sab82532_class;
95extern struct uart_class uart_z8530_class;
96
97struct uart_softc {
98	KOBJ_FIELDS;
99	struct uart_class *sc_class;
100	struct uart_bas	sc_bas;
101	device_t	sc_dev;
102
103	struct mtx	sc_hwmtx;	/* Spinlock protecting hardware. */
104
105	struct resource	*sc_rres;	/* Register resource. */
106	int		sc_rrid;
107	int		sc_rtype;	/* SYS_RES_{IOPORT|MEMORY}. */
108	struct resource *sc_ires;	/* Interrupt resource. */
109	void		*sc_icookie;
110	int		sc_irid;
111
112	int		sc_callout:1;	/* This UART is opened for callout. */
113	int		sc_fastintr:1;	/* This UART uses fast interrupts. */
114	int		sc_hasfifo:1;	/* This UART has FIFOs. */
115	int		sc_hwiflow:1;	/* This UART has HW input flow ctl. */
116	int		sc_hwoflow:1;	/* This UART has HW output flow ctl. */
117	int		sc_leaving:1;	/* This UART is going away. */
118	int		sc_opened:1;	/* This UART is open for business. */
119	int		sc_polled:1;	/* This UART has no interrupts. */
120	int		sc_txbusy:1;	/* This UART is transmitting. */
121
122	struct uart_devinfo *sc_sysdev;	/* System device (or NULL). */
123
124	int		sc_altbrk;	/* State for alt break sequence. */
125	uint32_t	sc_hwsig;	/* Signal state. Used by HW driver. */
126
127	/* Receiver data. */
128	uint16_t	*sc_rxbuf;
129	int		sc_rxbufsz;
130	int		sc_rxput;
131	int		sc_rxget;
132	int		sc_rxfifosz;	/* Size of RX FIFO. */
133
134	/* Transmitter data. */
135	uint8_t		*sc_txbuf;
136	int		sc_txdatasz;
137	int		sc_txfifosz;	/* Size of TX FIFO and buffer. */
138
139	/* Pulse capturing support (PPS). */
140	struct pps_state sc_pps;
141
142	/* Upper layer data. */
143	void		*sc_softih;
144	uint32_t	sc_ttypend;
145	union {
146		/* TTY specific data. */
147		struct {
148			struct tty *tp;
149		} u_tty;
150		/* Keyboard specific data. */
151		struct {
152		} u_kbd;
153	} sc_u;
154};
155
156extern devclass_t uart_devclass;
157extern char uart_driver_name[];
158
159int uart_bus_attach(device_t dev);
160int uart_bus_detach(device_t dev);
161int uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan);
162
163int uart_tty_attach(struct uart_softc *);
164int uart_tty_detach(struct uart_softc *);
165void uart_tty_intr(void *arg);
166
167/*
168 * Receive buffer operations.
169 */
170static __inline int
171uart_rx_empty(struct uart_softc *sc)
172{
173	return ((sc->sc_rxget == sc->sc_rxput) ? 1 : 0);
174}
175
176static __inline int
177uart_rx_full(struct uart_softc *sc)
178{
179	return ((sc->sc_rxput + 1 < sc->sc_rxbufsz)
180	    ? (sc->sc_rxput + 1 == sc->sc_rxget) : (sc->sc_rxget == 0));
181}
182
183static __inline int
184uart_rx_get(struct uart_softc *sc)
185{
186	int ptr, xc;
187
188	ptr = sc->sc_rxget;
189	if (ptr == sc->sc_rxput)
190		return (-1);
191	xc = sc->sc_rxbuf[ptr++];
192	sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0;
193	return (xc);
194}
195
196static __inline int
197uart_rx_put(struct uart_softc *sc, int xc)
198{
199	int ptr;
200
201	ptr = (sc->sc_rxput + 1 < sc->sc_rxbufsz) ? sc->sc_rxput + 1 : 0;
202	if (ptr == sc->sc_rxget)
203		return (ENOSPC);
204	sc->sc_rxbuf[sc->sc_rxput] = xc;
205	sc->sc_rxput = ptr;
206	return (0);
207}
208
209#endif /* _DEV_UART_BUS_H_ */
210