if_txp.c revision 87276
1/* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */ 2/* $FreeBSD: head/sys/dev/txp/if_txp.c 87276 2001-12-03 17:28:27Z brooks $ */ 3 4/* 5 * Copyright (c) 2001 6 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 7 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Jason L. Wright, 20 * Theo de Raadt and Aaron Campbell. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/* 39 * Driver for 3c990 (Typhoon) Ethernet ASIC 40 */ 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/sockio.h> 45#include <sys/mbuf.h> 46#include <sys/malloc.h> 47#include <sys/kernel.h> 48#include <sys/socket.h> 49 50#include <net/if.h> 51#include <net/if_arp.h> 52#include <net/ethernet.h> 53#include <net/if_dl.h> 54#include <net/if_types.h> 55#include <net/if_vlan_var.h> 56 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/ip.h> 61#include <netinet/if_ether.h> 62#include <machine/in_cksum.h> 63 64#include <net/if_media.h> 65 66#include <net/bpf.h> 67 68#include <vm/vm.h> /* for vtophys */ 69#include <vm/pmap.h> /* for vtophys */ 70#include <machine/clock.h> /* for DELAY */ 71#include <machine/bus_pio.h> 72#include <machine/bus_memio.h> 73#include <machine/bus.h> 74#include <machine/resource.h> 75#include <sys/bus.h> 76#include <sys/rman.h> 77 78#include <dev/mii/mii.h> 79#include <dev/mii/miivar.h> 80#include <dev/pci/pcireg.h> 81#include <dev/pci/pcivar.h> 82 83#define TXP_USEIOSPACE 84#define __STRICT_ALIGNMENT 85 86#include <dev/txp/if_txpreg.h> 87#include <dev/txp/3c990img.h> 88 89#ifndef lint 90static const char rcsid[] = 91 "$FreeBSD: head/sys/dev/txp/if_txp.c 87276 2001-12-03 17:28:27Z brooks $"; 92#endif 93 94/* 95 * Various supported device vendors/types and their names. 96 */ 97static struct txp_type txp_devs[] = { 98 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95, 99 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" }, 100 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97, 101 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" }, 102 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM, 103 "3Com 3cR990B-TXM Etherlink with 3XP Processor" }, 104 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95, 105 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" }, 106 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97, 107 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" }, 108 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV, 109 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" }, 110 { 0, 0, NULL } 111}; 112 113static int txp_probe __P((device_t)); 114static int txp_attach __P((device_t)); 115static int txp_detach __P((device_t)); 116static void txp_intr __P((void *)); 117static void txp_tick __P((void *)); 118static int txp_shutdown __P((device_t)); 119static int txp_ioctl __P((struct ifnet *, u_long, caddr_t)); 120static void txp_start __P((struct ifnet *)); 121static void txp_stop __P((struct txp_softc *)); 122static void txp_init __P((void *)); 123static void txp_watchdog __P((struct ifnet *)); 124 125static void txp_release_resources __P((struct txp_softc *)); 126static int txp_chip_init __P((struct txp_softc *)); 127static int txp_reset_adapter __P((struct txp_softc *)); 128static int txp_download_fw __P((struct txp_softc *)); 129static int txp_download_fw_wait __P((struct txp_softc *)); 130static int txp_download_fw_section __P((struct txp_softc *, 131 struct txp_fw_section_header *, int)); 132static int txp_alloc_rings __P((struct txp_softc *)); 133static int txp_rxring_fill __P((struct txp_softc *)); 134static void txp_rxring_empty __P((struct txp_softc *)); 135static void txp_set_filter __P((struct txp_softc *)); 136 137static int txp_cmd_desc_numfree __P((struct txp_softc *)); 138static int txp_command __P((struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 139 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int)); 140static int txp_command2 __P((struct txp_softc *, u_int16_t, u_int16_t, 141 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 142 struct txp_rsp_desc **, int)); 143static int txp_response __P((struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 144 struct txp_rsp_desc **)); 145static void txp_rsp_fixup __P((struct txp_softc *, struct txp_rsp_desc *, 146 struct txp_rsp_desc *)); 147static void txp_capabilities __P((struct txp_softc *)); 148 149static void txp_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 150static int txp_ifmedia_upd __P((struct ifnet *)); 151#ifdef TXP_DEBUG 152static void txp_show_descriptor __P((void *)); 153#endif 154static void txp_tx_reclaim __P((struct txp_softc *, struct txp_tx_ring *)); 155static void txp_rxbuf_reclaim __P((struct txp_softc *)); 156static void txp_rx_reclaim __P((struct txp_softc *, struct txp_rx_ring *)); 157 158#ifdef TXP_USEIOSPACE 159#define TXP_RES SYS_RES_IOPORT 160#define TXP_RID TXP_PCI_LOIO 161#else 162#define TXP_RES SYS_RES_MEMORY 163#define TXP_RID TXP_PCI_LOMEM 164#endif 165 166static device_method_t txp_methods[] = { 167 /* Device interface */ 168 DEVMETHOD(device_probe, txp_probe), 169 DEVMETHOD(device_attach, txp_attach), 170 DEVMETHOD(device_detach, txp_detach), 171 DEVMETHOD(device_shutdown, txp_shutdown), 172 { 0, 0 } 173}; 174 175static driver_t txp_driver = { 176 "txp", 177 txp_methods, 178 sizeof(struct txp_softc) 179}; 180 181static devclass_t txp_devclass; 182 183DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0); 184 185static int 186txp_probe(dev) 187 device_t dev; 188{ 189 struct txp_type *t; 190 191 t = txp_devs; 192 193 while(t->txp_name != NULL) { 194 if ((pci_get_vendor(dev) == t->txp_vid) && 195 (pci_get_device(dev) == t->txp_did)) { 196 device_set_desc(dev, t->txp_name); 197 return(0); 198 } 199 t++; 200 } 201 202 return(ENXIO); 203} 204 205static int 206txp_attach(dev) 207 device_t dev; 208{ 209 struct txp_softc *sc; 210 struct ifnet *ifp; 211 u_int32_t command; 212 u_int16_t p1; 213 u_int32_t p2; 214 int unit, error = 0, rid; 215 216 sc = device_get_softc(dev); 217 unit = device_get_unit(dev); 218 sc->sc_dev = dev; 219 sc->sc_cold = 1; 220 221 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF|MTX_RECURSE); 222 223 /* 224 * Handle power management nonsense. 225 */ 226 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 227 u_int32_t iobase, membase, irq; 228 229 /* Save important PCI config data. */ 230 iobase = pci_read_config(dev, TXP_PCI_LOIO, 4); 231 membase = pci_read_config(dev, TXP_PCI_LOMEM, 4); 232 irq = pci_read_config(dev, TXP_PCI_INTLINE, 4); 233 234 /* Reset the power state. */ 235 device_printf(dev, "chip is in D%d power mode " 236 "-- setting to D0\n", pci_get_powerstate(dev)); 237 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 238 239 /* Restore PCI config data. */ 240 pci_write_config(dev, TXP_PCI_LOIO, iobase, 4); 241 pci_write_config(dev, TXP_PCI_LOMEM, membase, 4); 242 pci_write_config(dev, TXP_PCI_INTLINE, irq, 4); 243 } 244 245 /* 246 * Map control/status registers. 247 */ 248 pci_enable_busmaster(dev); 249 pci_enable_io(dev, SYS_RES_IOPORT); 250 pci_enable_io(dev, SYS_RES_MEMORY); 251 command = pci_read_config(dev, PCIR_COMMAND, 4); 252 253#ifdef TXP_USEIOSPACE 254 if (!(command & PCIM_CMD_PORTEN)) { 255 device_printf(dev, "failed to enable I/O ports!\n"); 256 error = ENXIO; 257 goto fail; 258 } 259#else 260 if (!(command & PCIM_CMD_MEMEN)) { 261 device_printf(dev, "failed to enable memory mapping!\n"); 262 error = ENXIO; 263 goto fail; 264 } 265#endif 266 267 rid = TXP_RID; 268 sc->sc_res = bus_alloc_resource(dev, TXP_RES, &rid, 269 0, ~0, 1, RF_ACTIVE); 270 271 if (sc->sc_res == NULL) { 272 device_printf(dev, "couldn't map ports/memory\n"); 273 error = ENXIO; 274 goto fail; 275 } 276 277 sc->sc_bt = rman_get_bustag(sc->sc_res); 278 sc->sc_bh = rman_get_bushandle(sc->sc_res); 279 280 /* Allocate interrupt */ 281 rid = 0; 282 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 283 RF_SHAREABLE | RF_ACTIVE); 284 285 if (sc->sc_irq == NULL) { 286 device_printf(dev, "couldn't map interrupt\n"); 287 txp_release_resources(sc); 288 error = ENXIO; 289 goto fail; 290 } 291 292 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 293 txp_intr, sc, &sc->sc_intrhand); 294 295 if (error) { 296 txp_release_resources(sc); 297 device_printf(dev, "couldn't set up irq\n"); 298 goto fail; 299 } 300 301 if (txp_chip_init(sc)) { 302 txp_release_resources(sc); 303 goto fail; 304 } 305 306 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF, 307 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 308 error = txp_download_fw(sc); 309 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF); 310 sc->sc_fwbuf = NULL; 311 312 if (error) { 313 txp_release_resources(sc); 314 goto fail; 315 } 316 317 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF, 318 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 319 bzero(sc->sc_ldata, sizeof(struct txp_ldata)); 320 321 if (txp_alloc_rings(sc)) { 322 txp_release_resources(sc); 323 goto fail; 324 } 325 326 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 327 NULL, NULL, NULL, 1)) { 328 txp_release_resources(sc); 329 goto fail; 330 } 331 332 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 333 &p1, &p2, NULL, 1)) { 334 txp_release_resources(sc); 335 goto fail; 336 } 337 338 txp_set_filter(sc); 339 340 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 341 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 342 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 343 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 344 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 345 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 346 347 printf("txp%d: Ethernet address %6D\n", unit, 348 sc->sc_arpcom.ac_enaddr, ":"); 349 350 sc->sc_cold = 0; 351 352 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 353 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 354 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 355 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 356 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 357 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 358 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 359 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 360 361 sc->sc_xcvr = TXP_XCVR_AUTO; 362 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 363 NULL, NULL, NULL, 0); 364 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 365 366 ifp = &sc->sc_arpcom.ac_if; 367 ifp->if_softc = sc; 368 ifp->if_unit = unit; 369 ifp->if_name = "txp"; 370 ifp->if_mtu = ETHERMTU; 371 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 372 ifp->if_ioctl = txp_ioctl; 373 ifp->if_output = ether_output; 374 ifp->if_start = txp_start; 375 ifp->if_watchdog = txp_watchdog; 376 ifp->if_init = txp_init; 377 ifp->if_baudrate = 100000000; 378 ifp->if_snd.ifq_maxlen = TX_ENTRIES; 379 ifp->if_hwassist = 0; 380 txp_capabilities(sc); 381 382 /* 383 * Attach us everywhere 384 */ 385 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 386 callout_handle_init(&sc->sc_tick); 387 return(0); 388 389fail: 390 txp_release_resources(sc); 391 mtx_destroy(&sc->sc_mtx); 392 return(error); 393} 394 395static int 396txp_detach(dev) 397 device_t dev; 398{ 399 struct txp_softc *sc; 400 struct ifnet *ifp; 401 int i; 402 403 sc = device_get_softc(dev); 404 ifp = &sc->sc_arpcom.ac_if; 405 406 txp_stop(sc); 407 txp_shutdown(dev); 408 409 ifmedia_removeall(&sc->sc_ifmedia); 410 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 411 412 for (i = 0; i < RXBUF_ENTRIES; i++) 413 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF); 414 415 txp_release_resources(sc); 416 417 mtx_destroy(&sc->sc_mtx); 418 return(0); 419} 420 421static void 422txp_release_resources(sc) 423 struct txp_softc *sc; 424{ 425 device_t dev; 426 427 dev = sc->sc_dev; 428 429 if (sc->sc_intrhand != NULL) 430 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 431 432 if (sc->sc_irq != NULL) 433 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 434 435 if (sc->sc_res != NULL) 436 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res); 437 438 if (sc->sc_ldata != NULL) 439 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF); 440 441 return; 442} 443 444static int 445txp_chip_init(sc) 446 struct txp_softc *sc; 447{ 448 /* disable interrupts */ 449 WRITE_REG(sc, TXP_IER, 0); 450 WRITE_REG(sc, TXP_IMR, 451 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 452 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 453 TXP_INT_LATCH); 454 455 /* ack all interrupts */ 456 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 457 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 458 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 459 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 460 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 461 462 if (txp_reset_adapter(sc)) 463 return (-1); 464 465 /* disable interrupts */ 466 WRITE_REG(sc, TXP_IER, 0); 467 WRITE_REG(sc, TXP_IMR, 468 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 469 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 470 TXP_INT_LATCH); 471 472 /* ack all interrupts */ 473 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 474 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 475 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 476 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 477 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 478 479 return (0); 480} 481 482static int 483txp_reset_adapter(sc) 484 struct txp_softc *sc; 485{ 486 u_int32_t r; 487 int i; 488 489 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 490 DELAY(1000); 491 WRITE_REG(sc, TXP_SRR, 0); 492 493 /* Should wait max 6 seconds */ 494 for (i = 0; i < 6000; i++) { 495 r = READ_REG(sc, TXP_A2H_0); 496 if (r == STAT_WAITING_FOR_HOST_REQUEST) 497 break; 498 DELAY(1000); 499 } 500 501 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 502 device_printf(sc->sc_dev, "reset hung\n"); 503 return (-1); 504 } 505 506 return (0); 507} 508 509static int 510txp_download_fw(sc) 511 struct txp_softc *sc; 512{ 513 struct txp_fw_file_header *fileheader; 514 struct txp_fw_section_header *secthead; 515 int sect; 516 u_int32_t r, i, ier, imr; 517 518 ier = READ_REG(sc, TXP_IER); 519 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 520 521 imr = READ_REG(sc, TXP_IMR); 522 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 523 524 for (i = 0; i < 10000; i++) { 525 r = READ_REG(sc, TXP_A2H_0); 526 if (r == STAT_WAITING_FOR_HOST_REQUEST) 527 break; 528 DELAY(50); 529 } 530 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 531 device_printf(sc->sc_dev, "not waiting for host request\n"); 532 return (-1); 533 } 534 535 /* Ack the status */ 536 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 537 538 fileheader = (struct txp_fw_file_header *)tc990image; 539 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 540 device_printf(sc->sc_dev, "fw invalid magic\n"); 541 return (-1); 542 } 543 544 /* Tell boot firmware to get ready for image */ 545 WRITE_REG(sc, TXP_H2A_1, fileheader->addr); 546 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 547 548 if (txp_download_fw_wait(sc)) { 549 device_printf(sc->sc_dev, "fw wait failed, initial\n"); 550 return (-1); 551 } 552 553 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 554 sizeof(struct txp_fw_file_header)); 555 556 for (sect = 0; sect < fileheader->nsections; sect++) { 557 if (txp_download_fw_section(sc, secthead, sect)) 558 return (-1); 559 secthead = (struct txp_fw_section_header *) 560 (((u_int8_t *)secthead) + secthead->nbytes + 561 sizeof(*secthead)); 562 } 563 564 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 565 566 for (i = 0; i < 10000; i++) { 567 r = READ_REG(sc, TXP_A2H_0); 568 if (r == STAT_WAITING_FOR_BOOT) 569 break; 570 DELAY(50); 571 } 572 if (r != STAT_WAITING_FOR_BOOT) { 573 device_printf(sc->sc_dev, "not waiting for boot\n"); 574 return (-1); 575 } 576 577 WRITE_REG(sc, TXP_IER, ier); 578 WRITE_REG(sc, TXP_IMR, imr); 579 580 return (0); 581} 582 583static int 584txp_download_fw_wait(sc) 585 struct txp_softc *sc; 586{ 587 u_int32_t i, r; 588 589 for (i = 0; i < 10000; i++) { 590 r = READ_REG(sc, TXP_ISR); 591 if (r & TXP_INT_A2H_0) 592 break; 593 DELAY(50); 594 } 595 596 if (!(r & TXP_INT_A2H_0)) { 597 device_printf(sc->sc_dev, "fw wait failed comm0\n"); 598 return (-1); 599 } 600 601 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 602 603 r = READ_REG(sc, TXP_A2H_0); 604 if (r != STAT_WAITING_FOR_SEGMENT) { 605 device_printf(sc->sc_dev, "fw not waiting for segment\n"); 606 return (-1); 607 } 608 return (0); 609} 610 611static int 612txp_download_fw_section(sc, sect, sectnum) 613 struct txp_softc *sc; 614 struct txp_fw_section_header *sect; 615 int sectnum; 616{ 617 vm_offset_t dma; 618 int rseg, err = 0; 619 struct mbuf m; 620 u_int16_t csum; 621 622 /* Skip zero length sections */ 623 if (sect->nbytes == 0) 624 return (0); 625 626 /* Make sure we aren't past the end of the image */ 627 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 628 if (rseg >= sizeof(tc990image)) { 629 device_printf(sc->sc_dev, "fw invalid section address, " 630 "section %d\n", sectnum); 631 return (-1); 632 } 633 634 /* Make sure this section doesn't go past the end */ 635 rseg += sect->nbytes; 636 if (rseg >= sizeof(tc990image)) { 637 device_printf(sc->sc_dev, "fw truncated section %d\n", 638 sectnum); 639 return (-1); 640 } 641 642 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes); 643 dma = vtophys(sc->sc_fwbuf); 644 645 /* 646 * dummy up mbuf and verify section checksum 647 */ 648 m.m_type = MT_DATA; 649 m.m_next = m.m_nextpkt = NULL; 650 m.m_len = sect->nbytes; 651 m.m_data = sc->sc_fwbuf; 652 m.m_flags = 0; 653 csum = in_cksum(&m, sect->nbytes); 654 if (csum != sect->cksum) { 655 device_printf(sc->sc_dev, "fw section %d, bad " 656 "cksum (expected 0x%x got 0x%x)\n", 657 sectnum, sect->cksum, csum); 658 err = -1; 659 goto bail; 660 } 661 662 WRITE_REG(sc, TXP_H2A_1, sect->nbytes); 663 WRITE_REG(sc, TXP_H2A_2, sect->cksum); 664 WRITE_REG(sc, TXP_H2A_3, sect->addr); 665 WRITE_REG(sc, TXP_H2A_4, 0); 666 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff); 667 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 668 669 if (txp_download_fw_wait(sc)) { 670 device_printf(sc->sc_dev, "fw wait failed, " 671 "section %d\n", sectnum); 672 err = -1; 673 } 674 675bail: 676 return (err); 677} 678 679static void 680txp_intr(vsc) 681 void *vsc; 682{ 683 struct txp_softc *sc = vsc; 684 struct txp_hostvar *hv = sc->sc_hostvar; 685 u_int32_t isr; 686 687 /* mask all interrupts */ 688 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 689 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 690 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 691 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 692 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 693 694 isr = READ_REG(sc, TXP_ISR); 695 while (isr) { 696 WRITE_REG(sc, TXP_ISR, isr); 697 698 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 699 txp_rx_reclaim(sc, &sc->sc_rxhir); 700 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 701 txp_rx_reclaim(sc, &sc->sc_rxlor); 702 703 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 704 txp_rxbuf_reclaim(sc); 705 706 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 707 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off)))) 708 txp_tx_reclaim(sc, &sc->sc_txhir); 709 710 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 711 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off)))) 712 txp_tx_reclaim(sc, &sc->sc_txlor); 713 714 isr = READ_REG(sc, TXP_ISR); 715 } 716 717 /* unmask all interrupts */ 718 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 719 720 txp_start(&sc->sc_arpcom.ac_if); 721 722 return; 723} 724 725static void 726txp_rx_reclaim(sc, r) 727 struct txp_softc *sc; 728 struct txp_rx_ring *r; 729{ 730 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 731 struct txp_rx_desc *rxd; 732 struct mbuf *m; 733 struct txp_swdesc *sd = NULL; 734 u_int32_t roff, woff; 735 struct ether_header *eh = NULL; 736 737 roff = *r->r_roff; 738 woff = *r->r_woff; 739 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc)); 740 741 while (roff != woff) { 742 743 if (rxd->rx_flags & RX_FLAGS_ERROR) { 744 device_printf(sc->sc_dev, "error 0x%x\n", 745 rxd->rx_stat); 746 ifp->if_ierrors++; 747 goto next; 748 } 749 750 /* retrieve stashed pointer */ 751 sd = rxd->rx_sd; 752 753 m = sd->sd_mbuf; 754 sd->sd_mbuf = NULL; 755 756 m->m_pkthdr.len = m->m_len = rxd->rx_len; 757 758#ifdef __STRICT_ALIGNMENT 759 { 760 /* 761 * XXX Nice chip, except it won't accept "off by 2" 762 * buffers, so we're force to copy. Supposedly 763 * this will be fixed in a newer firmware rev 764 * and this will be temporary. 765 */ 766 struct mbuf *mnew; 767 768 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 769 if (mnew == NULL) { 770 m_freem(m); 771 goto next; 772 } 773 if (m->m_len > (MHLEN - 2)) { 774 MCLGET(mnew, M_DONTWAIT); 775 if (!(mnew->m_flags & M_EXT)) { 776 m_freem(mnew); 777 m_freem(m); 778 goto next; 779 } 780 } 781 mnew->m_pkthdr.rcvif = ifp; 782 m_adj(mnew, 2); 783 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 784 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 785 m_freem(m); 786 m = mnew; 787 } 788#endif 789 790 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD) 791 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 792 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD) 793 m->m_pkthdr.csum_flags |= 794 CSUM_IP_CHECKED|CSUM_IP_VALID; 795 796 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) || 797 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) { 798 m->m_pkthdr.csum_flags |= 799 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 800 m->m_pkthdr.csum_data = 0xffff; 801 } 802 803 eh = mtod(m, struct ether_header *); 804 /* Remove header from mbuf and pass it on. */ 805 m_adj(m, sizeof(struct ether_header)); 806 807 if (rxd->rx_stat & RX_STAT_VLAN) { 808 VLAN_INPUT_TAG(eh, m, htons(rxd->rx_vlan >> 16)); 809 goto next; 810 } 811 812 ether_input(ifp, eh, m); 813 814next: 815 816 roff += sizeof(struct txp_rx_desc); 817 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 818 roff = 0; 819 rxd = r->r_desc; 820 } else 821 rxd++; 822 woff = *r->r_woff; 823 } 824 825 *r->r_roff = woff; 826 827 return; 828} 829 830static void 831txp_rxbuf_reclaim(sc) 832 struct txp_softc *sc; 833{ 834 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 835 struct txp_hostvar *hv = sc->sc_hostvar; 836 struct txp_rxbuf_desc *rbd; 837 struct txp_swdesc *sd; 838 u_int32_t i; 839 840 if (!(ifp->if_flags & IFF_RUNNING)) 841 return; 842 843 i = sc->sc_rxbufprod; 844 rbd = sc->sc_rxbufs + i; 845 846 while (1) { 847 sd = rbd->rb_sd; 848 if (sd->sd_mbuf != NULL) 849 break; 850 851 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 852 if (sd->sd_mbuf == NULL) 853 goto err_sd; 854 855 MCLGET(sd->sd_mbuf, M_DONTWAIT); 856 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 857 goto err_mbuf; 858 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 859 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 860 861 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t)) 862 & 0xffffffff; 863 rbd->rb_paddrhi = 0; 864 865 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i); 866 867 if (++i == RXBUF_ENTRIES) { 868 i = 0; 869 rbd = sc->sc_rxbufs; 870 } else 871 rbd++; 872 } 873 874 sc->sc_rxbufprod = i; 875 876 return; 877 878err_mbuf: 879 m_freem(sd->sd_mbuf); 880err_sd: 881 free(sd, M_DEVBUF); 882} 883 884/* 885 * Reclaim mbufs and entries from a transmit ring. 886 */ 887static void 888txp_tx_reclaim(sc, r) 889 struct txp_softc *sc; 890 struct txp_tx_ring *r; 891{ 892 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 893 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off)); 894 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 895 struct txp_tx_desc *txd = r->r_desc + cons; 896 struct txp_swdesc *sd = sc->sc_txd + cons; 897 struct mbuf *m; 898 899 while (cons != idx) { 900 if (cnt == 0) 901 break; 902 903 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 904 TX_FLAGS_TYPE_DATA) { 905 m = sd->sd_mbuf; 906 if (m != NULL) { 907 m_freem(m); 908 txd->tx_addrlo = 0; 909 txd->tx_addrhi = 0; 910 ifp->if_opackets++; 911 } 912 } 913 ifp->if_flags &= ~IFF_OACTIVE; 914 915 if (++cons == TX_ENTRIES) { 916 txd = r->r_desc; 917 cons = 0; 918 sd = sc->sc_txd; 919 } else { 920 txd++; 921 sd++; 922 } 923 924 cnt--; 925 } 926 927 r->r_cons = cons; 928 r->r_cnt = cnt; 929 if (cnt == 0) 930 ifp->if_timer = 0; 931} 932 933static int 934txp_shutdown(dev) 935 device_t dev; 936{ 937 struct txp_softc *sc; 938 939 sc = device_get_softc(dev); 940 941 /* mask all interrupts */ 942 WRITE_REG(sc, TXP_IMR, 943 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 944 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 945 TXP_INT_LATCH); 946 947 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 948 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 949 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 950 951 return(0); 952} 953 954static int 955txp_alloc_rings(sc) 956 struct txp_softc *sc; 957{ 958 struct txp_boot_record *boot; 959 struct txp_ldata *ld; 960 u_int32_t r; 961 int i; 962 963 ld = sc->sc_ldata; 964 boot = &ld->txp_boot; 965 966 /* boot record */ 967 sc->sc_boot = boot; 968 969 /* host variables */ 970 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar)); 971 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar); 972 boot->br_hostvar_hi = 0; 973 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar; 974 975 /* hi priority tx ring */ 976 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);; 977 boot->br_txhipri_hi = 0; 978 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 979 sc->sc_txhir.r_reg = TXP_H2A_1; 980 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring; 981 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 982 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 983 984 /* lo priority tx ring */ 985 boot->br_txlopri_lo = vtophys(&ld->txp_txloring); 986 boot->br_txlopri_hi = 0; 987 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 988 sc->sc_txlor.r_reg = TXP_H2A_3; 989 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring; 990 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 991 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 992 993 /* high priority rx ring */ 994 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring); 995 boot->br_rxhipri_hi = 0; 996 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 997 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring; 998 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 999 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1000 1001 /* low priority rx ring */ 1002 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring); 1003 boot->br_rxlopri_hi = 0; 1004 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 1005 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring; 1006 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1007 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1008 1009 /* command ring */ 1010 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1011 boot->br_cmd_lo = vtophys(&ld->txp_cmdring); 1012 boot->br_cmd_hi = 0; 1013 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1014 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring; 1015 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1016 sc->sc_cmdring.lastwrite = 0; 1017 1018 /* response ring */ 1019 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1020 boot->br_resp_lo = vtophys(&ld->txp_rspring); 1021 boot->br_resp_hi = 0; 1022 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc); 1023 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring; 1024 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1025 sc->sc_rspring.lastwrite = 0; 1026 1027 /* receive buffer ring */ 1028 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs); 1029 boot->br_rxbuf_hi = 0; 1030 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc); 1031 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs; 1032 1033 for (i = 0; i < RXBUF_ENTRIES; i++) { 1034 struct txp_swdesc *sd; 1035 if (sc->sc_rxbufs[i].rb_sd != NULL) 1036 continue; 1037 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc), 1038 M_DEVBUF, M_NOWAIT); 1039 if (sc->sc_rxbufs[i].rb_sd == NULL) 1040 return(ENOBUFS); 1041 sd = sc->sc_rxbufs[i].rb_sd; 1042 sd->sd_mbuf = NULL; 1043 } 1044 sc->sc_rxbufprod = 0; 1045 1046 /* zero dma */ 1047 bzero(&ld->txp_zero, sizeof(u_int32_t)); 1048 boot->br_zero_lo = vtophys(&ld->txp_zero); 1049 boot->br_zero_hi = 0; 1050 1051 /* See if it's waiting for boot, and try to boot it */ 1052 for (i = 0; i < 10000; i++) { 1053 r = READ_REG(sc, TXP_A2H_0); 1054 if (r == STAT_WAITING_FOR_BOOT) 1055 break; 1056 DELAY(50); 1057 } 1058 1059 if (r != STAT_WAITING_FOR_BOOT) { 1060 device_printf(sc->sc_dev, "not waiting for boot\n"); 1061 return(ENXIO); 1062 } 1063 1064 WRITE_REG(sc, TXP_H2A_2, 0); 1065 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot)); 1066 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1067 1068 /* See if it booted */ 1069 for (i = 0; i < 10000; i++) { 1070 r = READ_REG(sc, TXP_A2H_0); 1071 if (r == STAT_RUNNING) 1072 break; 1073 DELAY(50); 1074 } 1075 if (r != STAT_RUNNING) { 1076 device_printf(sc->sc_dev, "fw not running\n"); 1077 return(ENXIO); 1078 } 1079 1080 /* Clear TX and CMD ring write registers */ 1081 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1082 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1083 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1084 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1085 1086 return (0); 1087} 1088 1089static int 1090txp_ioctl(ifp, command, data) 1091 struct ifnet *ifp; 1092 u_long command; 1093 caddr_t data; 1094{ 1095 struct txp_softc *sc = ifp->if_softc; 1096 struct ifreq *ifr = (struct ifreq *)data; 1097 int s, error = 0; 1098 1099 s = splnet(); 1100 1101 if ((error = ether_ioctl(ifp, command, data)) > 0) { 1102 splx(s); 1103 return error; 1104 } 1105 1106 switch(command) { 1107 case SIOCSIFADDR: 1108 case SIOCGIFADDR: 1109 case SIOCSIFMTU: 1110 error = ether_ioctl(ifp, command, data); 1111 break; 1112 case SIOCSIFFLAGS: 1113 if (ifp->if_flags & IFF_UP) { 1114 txp_init(sc); 1115 } else { 1116 if (ifp->if_flags & IFF_RUNNING) 1117 txp_stop(sc); 1118 } 1119 break; 1120 case SIOCADDMULTI: 1121 case SIOCDELMULTI: 1122 /* 1123 * Multicast list has changed; set the hardware 1124 * filter accordingly. 1125 */ 1126 txp_set_filter(sc); 1127 error = 0; 1128 break; 1129 case SIOCGIFMEDIA: 1130 case SIOCSIFMEDIA: 1131 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1132 break; 1133 default: 1134 error = EINVAL; 1135 break; 1136 } 1137 1138 (void)splx(s); 1139 1140 return(error); 1141} 1142 1143static int 1144txp_rxring_fill(sc) 1145 struct txp_softc *sc; 1146{ 1147 int i; 1148 struct ifnet *ifp; 1149 struct txp_swdesc *sd; 1150 1151 ifp = &sc->sc_arpcom.ac_if; 1152 1153 for (i = 0; i < RXBUF_ENTRIES; i++) { 1154 sd = sc->sc_rxbufs[i].rb_sd; 1155 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1156 if (sd->sd_mbuf == NULL) 1157 return(ENOBUFS); 1158 1159 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1160 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1161 m_freem(sd->sd_mbuf); 1162 return(ENOBUFS); 1163 } 1164 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1165 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1166 1167 sc->sc_rxbufs[i].rb_paddrlo = 1168 vtophys(mtod(sd->sd_mbuf, vm_offset_t)); 1169 sc->sc_rxbufs[i].rb_paddrhi = 0; 1170 } 1171 1172 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) * 1173 sizeof(struct txp_rxbuf_desc); 1174 1175 return(0); 1176} 1177 1178static void 1179txp_rxring_empty(sc) 1180 struct txp_softc *sc; 1181{ 1182 int i; 1183 struct txp_swdesc *sd; 1184 1185 if (sc->sc_rxbufs == NULL) 1186 return; 1187 1188 for (i = 0; i < RXBUF_ENTRIES; i++) { 1189 if (&sc->sc_rxbufs[i] == NULL) 1190 continue; 1191 sd = sc->sc_rxbufs[i].rb_sd; 1192 if (sd == NULL) 1193 continue; 1194 if (sd->sd_mbuf != NULL) { 1195 m_freem(sd->sd_mbuf); 1196 sd->sd_mbuf = NULL; 1197 } 1198 } 1199 1200 return; 1201} 1202 1203static void 1204txp_init(xsc) 1205 void *xsc; 1206{ 1207 struct txp_softc *sc; 1208 struct ifnet *ifp; 1209 u_int16_t p1; 1210 u_int32_t p2; 1211 int s; 1212 1213 sc = xsc; 1214 ifp = &sc->sc_arpcom.ac_if; 1215 1216 if (ifp->if_flags & IFF_RUNNING) 1217 return; 1218 1219 txp_stop(sc); 1220 1221 s = splnet(); 1222 1223 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 1224 NULL, NULL, NULL, 1); 1225 1226 /* Set station address. */ 1227 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0]; 1228 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1]; 1229 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2]; 1230 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3]; 1231 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4]; 1232 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5]; 1233 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0, 1234 NULL, NULL, NULL, 1); 1235 1236 txp_set_filter(sc); 1237 1238 txp_rxring_fill(sc); 1239 1240 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1241 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1242 1243 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1244 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1245 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1246 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1247 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1248 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1249 1250 ifp->if_flags |= IFF_RUNNING; 1251 ifp->if_flags &= ~IFF_OACTIVE; 1252 ifp->if_timer = 0; 1253 1254 sc->sc_tick = timeout(txp_tick, sc, hz); 1255 1256 splx(s); 1257} 1258 1259static void 1260txp_tick(vsc) 1261 void *vsc; 1262{ 1263 struct txp_softc *sc = vsc; 1264 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1265 struct txp_rsp_desc *rsp = NULL; 1266 struct txp_ext_desc *ext; 1267 int s; 1268 1269 s = splnet(); 1270 txp_rxbuf_reclaim(sc); 1271 1272 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1273 &rsp, 1)) 1274 goto out; 1275 if (rsp->rsp_numdesc != 6) 1276 goto out; 1277 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1278 NULL, NULL, NULL, 1)) 1279 goto out; 1280 ext = (struct txp_ext_desc *)(rsp + 1); 1281 1282 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1283 ext[4].ext_1 + ext[4].ext_4; 1284 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1285 ext[2].ext_1; 1286 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1287 ext[1].ext_3; 1288 ifp->if_opackets += rsp->rsp_par2; 1289 ifp->if_ipackets += ext[2].ext_3; 1290 1291out: 1292 if (rsp != NULL) 1293 free(rsp, M_DEVBUF); 1294 1295 splx(s); 1296 sc->sc_tick = timeout(txp_tick, sc, hz); 1297 1298 return; 1299} 1300 1301static void 1302txp_start(ifp) 1303 struct ifnet *ifp; 1304{ 1305 struct txp_softc *sc = ifp->if_softc; 1306 struct txp_tx_ring *r = &sc->sc_txhir; 1307 struct txp_tx_desc *txd; 1308 struct txp_frag_desc *fxd; 1309 struct mbuf *m, *m0; 1310 struct txp_swdesc *sd; 1311 u_int32_t firstprod, firstcnt, prod, cnt; 1312 struct ifvlan *ifv; 1313 1314 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1315 return; 1316 1317 prod = r->r_prod; 1318 cnt = r->r_cnt; 1319 1320 while (1) { 1321 IF_DEQUEUE(&ifp->if_snd, m); 1322 if (m == NULL) 1323 break; 1324 1325 firstprod = prod; 1326 firstcnt = cnt; 1327 1328 sd = sc->sc_txd + prod; 1329 sd->sd_mbuf = m; 1330 1331 if ((TX_ENTRIES - cnt) < 4) 1332 goto oactive; 1333 1334 txd = r->r_desc + prod; 1335 1336 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1337 txd->tx_numdesc = 0; 1338 txd->tx_addrlo = 0; 1339 txd->tx_addrhi = 0; 1340 txd->tx_totlen = 0; 1341 txd->tx_pflags = 0; 1342 1343 if (++prod == TX_ENTRIES) 1344 prod = 0; 1345 1346 if (++cnt >= (TX_ENTRIES - 4)) 1347 goto oactive; 1348 1349 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1350 m->m_pkthdr.rcvif != NULL) { 1351 ifv = m->m_pkthdr.rcvif->if_softc; 1352 txd->tx_pflags = TX_PFLAGS_VLAN | 1353 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S); 1354 } 1355 1356 if (m->m_pkthdr.csum_flags & CSUM_IP) 1357 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1358 1359#if 0 1360 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1361 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1362 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1363 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1364#endif 1365 1366 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1367 for (m0 = m; m0 != NULL; m0 = m0->m_next) { 1368 if (m0->m_len == 0) 1369 continue; 1370 if (++cnt >= (TX_ENTRIES - 4)) 1371 goto oactive; 1372 1373 txd->tx_numdesc++; 1374 1375 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG; 1376 fxd->frag_rsvd1 = 0; 1377 fxd->frag_len = m0->m_len; 1378 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t)); 1379 fxd->frag_addrhi = 0; 1380 fxd->frag_rsvd2 = 0; 1381 1382 if (++prod == TX_ENTRIES) { 1383 fxd = (struct txp_frag_desc *)r->r_desc; 1384 prod = 0; 1385 } else 1386 fxd++; 1387 1388 } 1389 1390 ifp->if_timer = 5; 1391 1392 if (ifp->if_bpf) 1393 bpf_mtap(ifp, m); 1394 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1395 } 1396 1397 r->r_prod = prod; 1398 r->r_cnt = cnt; 1399 return; 1400 1401oactive: 1402 ifp->if_flags |= IFF_OACTIVE; 1403 r->r_prod = firstprod; 1404 r->r_cnt = firstcnt; 1405 IF_PREPEND(&ifp->if_snd, m); 1406 return; 1407} 1408 1409/* 1410 * Handle simple commands sent to the typhoon 1411 */ 1412static int 1413txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1414 struct txp_softc *sc; 1415 u_int16_t id, in1, *out1; 1416 u_int32_t in2, in3, *out2, *out3; 1417 int wait; 1418{ 1419 struct txp_rsp_desc *rsp = NULL; 1420 1421 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1422 return (-1); 1423 1424 if (!wait) 1425 return (0); 1426 1427 if (out1 != NULL) 1428 *out1 = rsp->rsp_par1; 1429 if (out2 != NULL) 1430 *out2 = rsp->rsp_par2; 1431 if (out3 != NULL) 1432 *out3 = rsp->rsp_par3; 1433 free(rsp, M_DEVBUF); 1434 return (0); 1435} 1436 1437static int 1438txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1439 struct txp_softc *sc; 1440 u_int16_t id, in1; 1441 u_int32_t in2, in3; 1442 struct txp_ext_desc *in_extp; 1443 u_int8_t in_extn; 1444 struct txp_rsp_desc **rspp; 1445 int wait; 1446{ 1447 struct txp_hostvar *hv = sc->sc_hostvar; 1448 struct txp_cmd_desc *cmd; 1449 struct txp_ext_desc *ext; 1450 u_int32_t idx, i; 1451 u_int16_t seq; 1452 1453 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1454 device_printf(sc->sc_dev, "no free cmd descriptors\n"); 1455 return (-1); 1456 } 1457 1458 idx = sc->sc_cmdring.lastwrite; 1459 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1460 bzero(cmd, sizeof(*cmd)); 1461 1462 cmd->cmd_numdesc = in_extn; 1463 cmd->cmd_seq = seq = sc->sc_seq++; 1464 cmd->cmd_id = id; 1465 cmd->cmd_par1 = in1; 1466 cmd->cmd_par2 = in2; 1467 cmd->cmd_par3 = in3; 1468 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1469 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1470 1471 idx += sizeof(struct txp_cmd_desc); 1472 if (idx == sc->sc_cmdring.size) 1473 idx = 0; 1474 1475 for (i = 0; i < in_extn; i++) { 1476 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1477 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1478 in_extp++; 1479 idx += sizeof(struct txp_cmd_desc); 1480 if (idx == sc->sc_cmdring.size) 1481 idx = 0; 1482 } 1483 1484 sc->sc_cmdring.lastwrite = idx; 1485 1486 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1487 1488 if (!wait) 1489 return (0); 1490 1491 for (i = 0; i < 10000; i++) { 1492 idx = hv->hv_resp_read_idx; 1493 if (idx != hv->hv_resp_write_idx) { 1494 *rspp = NULL; 1495 if (txp_response(sc, idx, id, seq, rspp)) 1496 return (-1); 1497 if (*rspp != NULL) 1498 break; 1499 } 1500 DELAY(50); 1501 } 1502 if (i == 1000 || (*rspp) == NULL) { 1503 device_printf(sc->sc_dev, "0x%x command failed\n", id); 1504 return (-1); 1505 } 1506 1507 return (0); 1508} 1509 1510static int 1511txp_response(sc, ridx, id, seq, rspp) 1512 struct txp_softc *sc; 1513 u_int32_t ridx; 1514 u_int16_t id; 1515 u_int16_t seq; 1516 struct txp_rsp_desc **rspp; 1517{ 1518 struct txp_hostvar *hv = sc->sc_hostvar; 1519 struct txp_rsp_desc *rsp; 1520 1521 while (ridx != hv->hv_resp_write_idx) { 1522 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1523 1524 if (id == rsp->rsp_id && rsp->rsp_seq == seq) { 1525 *rspp = (struct txp_rsp_desc *)malloc( 1526 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1527 M_DEVBUF, M_NOWAIT); 1528 if ((*rspp) == NULL) 1529 return (-1); 1530 txp_rsp_fixup(sc, rsp, *rspp); 1531 return (0); 1532 } 1533 1534 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1535 device_printf(sc->sc_dev, "response error!\n"); 1536 txp_rsp_fixup(sc, rsp, NULL); 1537 ridx = hv->hv_resp_read_idx; 1538 continue; 1539 } 1540 1541 switch (rsp->rsp_id) { 1542 case TXP_CMD_CYCLE_STATISTICS: 1543 case TXP_CMD_MEDIA_STATUS_READ: 1544 break; 1545 case TXP_CMD_HELLO_RESPONSE: 1546 device_printf(sc->sc_dev, "hello\n"); 1547 break; 1548 default: 1549 device_printf(sc->sc_dev, "unknown id(0x%x)\n", 1550 rsp->rsp_id); 1551 } 1552 1553 txp_rsp_fixup(sc, rsp, NULL); 1554 ridx = hv->hv_resp_read_idx; 1555 hv->hv_resp_read_idx = ridx; 1556 } 1557 1558 return (0); 1559} 1560 1561static void 1562txp_rsp_fixup(sc, rsp, dst) 1563 struct txp_softc *sc; 1564 struct txp_rsp_desc *rsp, *dst; 1565{ 1566 struct txp_rsp_desc *src = rsp; 1567 struct txp_hostvar *hv = sc->sc_hostvar; 1568 u_int32_t i, ridx; 1569 1570 ridx = hv->hv_resp_read_idx; 1571 1572 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1573 if (dst != NULL) 1574 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1575 ridx += sizeof(struct txp_rsp_desc); 1576 if (ridx == sc->sc_rspring.size) { 1577 src = sc->sc_rspring.base; 1578 ridx = 0; 1579 } else 1580 src++; 1581 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx; 1582 } 1583 1584 hv->hv_resp_read_idx = ridx; 1585} 1586 1587static int 1588txp_cmd_desc_numfree(sc) 1589 struct txp_softc *sc; 1590{ 1591 struct txp_hostvar *hv = sc->sc_hostvar; 1592 struct txp_boot_record *br = sc->sc_boot; 1593 u_int32_t widx, ridx, nfree; 1594 1595 widx = sc->sc_cmdring.lastwrite; 1596 ridx = hv->hv_cmd_read_idx; 1597 1598 if (widx == ridx) { 1599 /* Ring is completely free */ 1600 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc); 1601 } else { 1602 if (widx > ridx) 1603 nfree = br->br_cmd_siz - 1604 (widx - ridx + sizeof(struct txp_cmd_desc)); 1605 else 1606 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1607 } 1608 1609 return (nfree / sizeof(struct txp_cmd_desc)); 1610} 1611 1612static void 1613txp_stop(sc) 1614 struct txp_softc *sc; 1615{ 1616 struct ifnet *ifp; 1617 1618 ifp = &sc->sc_arpcom.ac_if; 1619 1620 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1621 1622 untimeout(txp_tick, sc, sc->sc_tick); 1623 1624 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1625 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1626 1627 txp_rxring_empty(sc); 1628 1629 return; 1630} 1631 1632static void 1633txp_watchdog(ifp) 1634 struct ifnet *ifp; 1635{ 1636 return; 1637} 1638 1639static int 1640txp_ifmedia_upd(ifp) 1641 struct ifnet *ifp; 1642{ 1643 struct txp_softc *sc = ifp->if_softc; 1644 struct ifmedia *ifm = &sc->sc_ifmedia; 1645 u_int16_t new_xcvr; 1646 1647 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1648 return (EINVAL); 1649 1650 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1651 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1652 new_xcvr = TXP_XCVR_10_FDX; 1653 else 1654 new_xcvr = TXP_XCVR_10_HDX; 1655 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1656 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1657 new_xcvr = TXP_XCVR_100_FDX; 1658 else 1659 new_xcvr = TXP_XCVR_100_HDX; 1660 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1661 new_xcvr = TXP_XCVR_AUTO; 1662 } else 1663 return (EINVAL); 1664 1665 /* nothing to do */ 1666 if (sc->sc_xcvr == new_xcvr) 1667 return (0); 1668 1669 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1670 NULL, NULL, NULL, 0); 1671 sc->sc_xcvr = new_xcvr; 1672 1673 return (0); 1674} 1675 1676static void 1677txp_ifmedia_sts(ifp, ifmr) 1678 struct ifnet *ifp; 1679 struct ifmediareq *ifmr; 1680{ 1681 struct txp_softc *sc = ifp->if_softc; 1682 struct ifmedia *ifm = &sc->sc_ifmedia; 1683 u_int16_t bmsr, bmcr, anlpar; 1684 1685 ifmr->ifm_status = IFM_AVALID; 1686 ifmr->ifm_active = IFM_ETHER; 1687 1688 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1689 &bmsr, NULL, NULL, 1)) 1690 goto bail; 1691 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1692 &bmsr, NULL, NULL, 1)) 1693 goto bail; 1694 1695 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1696 &bmcr, NULL, NULL, 1)) 1697 goto bail; 1698 1699 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1700 &anlpar, NULL, NULL, 1)) 1701 goto bail; 1702 1703 if (bmsr & BMSR_LINK) 1704 ifmr->ifm_status |= IFM_ACTIVE; 1705 1706 if (bmcr & BMCR_ISO) { 1707 ifmr->ifm_active |= IFM_NONE; 1708 ifmr->ifm_status = 0; 1709 return; 1710 } 1711 1712 if (bmcr & BMCR_LOOP) 1713 ifmr->ifm_active |= IFM_LOOP; 1714 1715 if (bmcr & BMCR_AUTOEN) { 1716 if ((bmsr & BMSR_ACOMP) == 0) { 1717 ifmr->ifm_active |= IFM_NONE; 1718 return; 1719 } 1720 1721 if (anlpar & ANLPAR_T4) 1722 ifmr->ifm_active |= IFM_100_T4; 1723 else if (anlpar & ANLPAR_TX_FD) 1724 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1725 else if (anlpar & ANLPAR_TX) 1726 ifmr->ifm_active |= IFM_100_TX; 1727 else if (anlpar & ANLPAR_10_FD) 1728 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1729 else if (anlpar & ANLPAR_10) 1730 ifmr->ifm_active |= IFM_10_T; 1731 else 1732 ifmr->ifm_active |= IFM_NONE; 1733 } else 1734 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1735 return; 1736 1737bail: 1738 ifmr->ifm_active |= IFM_NONE; 1739 ifmr->ifm_status &= ~IFM_AVALID; 1740} 1741 1742#ifdef TXP_DEBUG 1743static void 1744txp_show_descriptor(d) 1745 void *d; 1746{ 1747 struct txp_cmd_desc *cmd = d; 1748 struct txp_rsp_desc *rsp = d; 1749 struct txp_tx_desc *txd = d; 1750 struct txp_frag_desc *frgd = d; 1751 1752 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1753 case CMD_FLAGS_TYPE_CMD: 1754 /* command descriptor */ 1755 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1756 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1757 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1758 break; 1759 case CMD_FLAGS_TYPE_RESP: 1760 /* response descriptor */ 1761 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1762 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq, 1763 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3); 1764 break; 1765 case CMD_FLAGS_TYPE_DATA: 1766 /* data header (assuming tx for now) */ 1767 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1768 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1769 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1770 break; 1771 case CMD_FLAGS_TYPE_FRAG: 1772 /* fragment descriptor */ 1773 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1774 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1775 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1776 break; 1777 default: 1778 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1779 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1780 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1781 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1782 break; 1783 } 1784} 1785#endif 1786 1787static void 1788txp_set_filter(sc) 1789 struct txp_softc *sc; 1790{ 1791 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1792 u_int32_t crc, carry, hashbit, hash[2]; 1793 u_int16_t filter; 1794 u_int8_t octet; 1795 int i, j, mcnt = 0; 1796 struct ifmultiaddr *ifma; 1797 char *enm; 1798 1799 if (ifp->if_flags & IFF_PROMISC) { 1800 filter = TXP_RXFILT_PROMISC; 1801 goto setit; 1802 } 1803 1804 filter = TXP_RXFILT_DIRECT; 1805 1806 if (ifp->if_flags & IFF_BROADCAST) 1807 filter |= TXP_RXFILT_BROADCAST; 1808 1809 if (ifp->if_flags & IFF_ALLMULTI) 1810 filter |= TXP_RXFILT_ALLMULTI; 1811 else { 1812 hash[0] = hash[1] = 0; 1813 1814 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1815 if (ifma->ifma_addr->sa_family != AF_LINK) 1816 continue; 1817 1818 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1819 mcnt++; 1820 crc = 0xffffffff; 1821 1822 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1823 octet = enm[i]; 1824 for (j = 0; j < 8; j++) { 1825 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1826 (octet & 1); 1827 crc <<= 1; 1828 octet >>= 1; 1829 if (carry) 1830 crc = (crc ^ TXP_POLYNOMIAL) | 1831 carry; 1832 } 1833 } 1834 hashbit = (u_int16_t)(crc & (64 - 1)); 1835 hash[hashbit / 32] |= (1 << hashbit % 32); 1836 } 1837 1838 if (mcnt > 0) { 1839 filter |= TXP_RXFILT_HASHMULTI; 1840 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1841 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1842 } 1843 } 1844 1845setit: 1846 1847 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1848 NULL, NULL, NULL, 1); 1849 1850 return; 1851} 1852 1853static void 1854txp_capabilities(sc) 1855 struct txp_softc *sc; 1856{ 1857 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1858 struct txp_rsp_desc *rsp = NULL; 1859 struct txp_ext_desc *ext; 1860 1861 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1862 goto out; 1863 1864 if (rsp->rsp_numdesc != 1) 1865 goto out; 1866 ext = (struct txp_ext_desc *)(rsp + 1); 1867 1868 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1869 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1870 ifp->if_capabilities = 0; 1871 1872 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1873 sc->sc_tx_capability |= OFFLOAD_VLAN; 1874 sc->sc_rx_capability |= OFFLOAD_VLAN; 1875 } 1876 1877#if 0 1878 /* not ready yet */ 1879 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1880 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1881 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1882 ifp->if_capabilities |= IFCAP_IPSEC; 1883 } 1884#endif 1885 1886 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1887 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1888 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1889 ifp->if_capabilities |= IFCAP_HWCSUM; 1890 ifp->if_hwassist |= CSUM_IP; 1891 } 1892 1893 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1894#if 0 1895 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1896#endif 1897 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1898 ifp->if_capabilities |= IFCAP_HWCSUM; 1899 } 1900 1901 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1902#if 0 1903 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1904#endif 1905 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1906 ifp->if_capabilities |= IFCAP_HWCSUM; 1907 } 1908 ifp->if_capenable = ifp->if_capabilities; 1909 1910 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1911 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1912 goto out; 1913 1914out: 1915 if (rsp != NULL) 1916 free(rsp, M_DEVBUF); 1917 1918 return; 1919} 1920